Add Elkhart Lake support

Elkhart Lake has a chipset called Mule Creek Canyon which is quite
compatible with 300 series chipsets. There are a few differences though,
e.g. different encoding for the SPI clock values for read and write in
the FLCOMP register. In addition Elkhart Lake has a new PCI device ID
for the SPI controller which is added, too.

Tested: Read and flash complete flash on Siemens MC EHL1

Change-Id: I711e39a3ec9cd7098389231eaa1cb864d615a475
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60711
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71443
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/ichspi.c b/ichspi.c
index 0b00466..21f6d9b 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -400,6 +400,7 @@
 	case CHIPSET_C620_SERIES_LEWISBURG:
 	case CHIPSET_300_SERIES_CANNON_POINT:
 	case CHIPSET_500_SERIES_TIGER_POINT:
+	case CHIPSET_ELKHART_LAKE:
 		break;
 	default:
 		pprint_reg(HSFS, BERASE, reg_val, ", ");
@@ -411,6 +412,7 @@
 	case CHIPSET_C620_SERIES_LEWISBURG:
 	case CHIPSET_300_SERIES_CANNON_POINT:
 	case CHIPSET_500_SERIES_TIGER_POINT:
+	case CHIPSET_ELKHART_LAKE:
 		pprint_reg(HSFS, PRR34_LOCKDN, reg_val, ", ");
 		pprint_reg(HSFS, WRSDIS, reg_val, ", ");
 		break;
@@ -431,6 +433,7 @@
 	case CHIPSET_C620_SERIES_LEWISBURG:
 	case CHIPSET_300_SERIES_CANNON_POINT:
 	case CHIPSET_500_SERIES_TIGER_POINT:
+	case CHIPSET_ELKHART_LAKE:
 		_pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", ");
 		pprint_reg(HSFC, WET, reg_val, ", ");
 		break;
@@ -1745,6 +1748,7 @@
 	case CHIPSET_500_SERIES_TIGER_POINT:
 	case CHIPSET_APOLLO_LAKE:
 	case CHIPSET_GEMINI_LAKE:
+	case CHIPSET_ELKHART_LAKE:
 		num_pr			= 6;	/* Includes GPR0 */
 		reg_pr0			= PCH100_REG_FPR0;
 		swseq_data.reg_ssfsc	= PCH100_REG_SSFSC;
@@ -1778,6 +1782,7 @@
 	case CHIPSET_500_SERIES_TIGER_POINT:
 	case CHIPSET_APOLLO_LAKE:
 	case CHIPSET_GEMINI_LAKE:
+	case CHIPSET_ELKHART_LAKE:
 		num_freg = 16;
 		break;
 	default:
@@ -1875,6 +1880,7 @@
 		case CHIPSET_500_SERIES_TIGER_POINT:
 		case CHIPSET_APOLLO_LAKE:
 		case CHIPSET_GEMINI_LAKE:
+		case CHIPSET_ELKHART_LAKE:
 			tmp = mmio_readl(ich_spibar + PCH100_REG_DLOCK);
 			msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp);
 			prettyprint_pch100_reg_dlock(tmp);
@@ -1951,6 +1957,7 @@
 			case CHIPSET_500_SERIES_TIGER_POINT:
 			case CHIPSET_APOLLO_LAKE:
 			case CHIPSET_GEMINI_LAKE:
+			case CHIPSET_ELKHART_LAKE:
 			case CHIPSET_BAYTRAIL:
 				break;
 			default:
@@ -1985,6 +1992,7 @@
 			case CHIPSET_500_SERIES_TIGER_POINT:
 			case CHIPSET_APOLLO_LAKE:
 			case CHIPSET_GEMINI_LAKE:
+			case CHIPSET_ELKHART_LAKE:
 				break;
 			default:
 				tmp = mmio_readl(ich_spibar + ICH9_REG_FPB);
@@ -2023,8 +2031,9 @@
 
 		if (ich_spi_mode == ich_auto &&
 		    (ich_gen == CHIPSET_APOLLO_LAKE ||
-		     ich_gen == CHIPSET_GEMINI_LAKE)) {
-			msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini Lake.\n");
+		     ich_gen == CHIPSET_GEMINI_LAKE ||
+		     ich_gen == CHIPSET_ELKHART_LAKE)) {
+			msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Elkhart Lake.\n");
 			ich_spi_mode = ich_hwseq;
 		}