blob: 34f089199a4029859555414bd3fc108aed97d479 [file] [log] [blame]
Dominik Geyerb46acba2008-05-16 12:55:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
5 * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
6 * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
Stefan Reinauera9424d52008-06-27 16:28:34 +00007 * Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00008 * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
Stefan Tauner8b391b82011-08-09 01:49:34 +00009 * Copyright (C) 2011 Stefan Tauner
Dominik Geyerb46acba2008-05-16 12:55:55 +000010 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Dominik Geyerb46acba2008-05-16 12:55:55 +000024 */
25
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000026#if defined(__i386__) || defined(__x86_64__)
27
Dominik Geyerb46acba2008-05-16 12:55:55 +000028#include <string.h>
Dominik Geyerb46acba2008-05-16 12:55:55 +000029#include "flash.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000030#include "chipdrivers.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000031#include "programmer.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000032#include "spi.h"
33
Stefan Reinauera9424d52008-06-27 16:28:34 +000034/* ICH9 controller register definition */
Stefan Tauner55206942011-06-11 09:53:22 +000035#define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */
36#define HSFS_FDONE_OFF 0 /* 0: Flash Cycle Done */
37#define HSFS_FDONE (0x1 << HSFS_FDONE_OFF)
38#define HSFS_FCERR_OFF 1 /* 1: Flash Cycle Error */
39#define HSFS_FCERR (0x1 << HSFS_FCERR_OFF)
40#define HSFS_AEL_OFF 2 /* 2: Access Error Log */
41#define HSFS_AEL (0x1 << HSFS_AEL_OFF)
42#define HSFS_BERASE_OFF 3 /* 3-4: Block/Sector Erase Size */
43#define HSFS_BERASE (0x3 << HSFS_BERASE_OFF)
44#define HSFS_SCIP_OFF 5 /* 5: SPI Cycle In Progress */
45#define HSFS_SCIP (0x1 << HSFS_SCIP_OFF)
46 /* 6-12: reserved */
47#define HSFS_FDOPSS_OFF 13 /* 13: Flash Descriptor Override Pin-Strap Status */
48#define HSFS_FDOPSS (0x1 << HSFS_FDOPSS_OFF)
49#define HSFS_FDV_OFF 14 /* 14: Flash Descriptor Valid */
50#define HSFS_FDV (0x1 << HSFS_FDV_OFF)
51#define HSFS_FLOCKDN_OFF 15 /* 15: Flash Configuration Lock-Down */
52#define HSFS_FLOCKDN (0x1 << HSFS_FLOCKDN_OFF)
53
54#define ICH9_REG_HSFC 0x06 /* 16 Bits Hardware Sequencing Flash Control */
55#define HSFC_FGO_OFF 0 /* 0: Flash Cycle Go */
56#define HSFC_FGO (0x1 << HSFC_FGO_OFF)
57#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
58#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
59 /* 3-7: reserved */
60#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
61#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
62 /* 14: reserved */
63#define HSFC_SME_OFF 15 /* 15: SPI SMI# Enable */
64#define HSFC_SME (0x1 << HSFC_SME_OFF)
65
Stefan Taunerc0aaf952011-05-19 02:58:17 +000066#define ICH9_REG_FADDR 0x08 /* 32 Bits */
67#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
Stefan Reinauera9424d52008-06-27 16:28:34 +000068
Stefan Tauner29c80832011-06-12 08:14:10 +000069#define ICH9_REG_FRAP 0x50 /* 32 Bytes Flash Region Access Permissions */
70#define ICH9_REG_FREG0 0x54 /* 32 Bytes Flash Region 0 */
71
72#define ICH9_REG_PR0 0x74 /* 32 Bytes Protected Range 0 */
73#define ICH9_REG_PR1 0x78 /* 32 Bytes Protected Range 1 */
74#define ICH9_REG_PR2 0x7c /* 32 Bytes Protected Range 2 */
75#define ICH9_REG_PR3 0x80 /* 32 Bytes Protected Range 3 */
76#define ICH9_REG_PR4 0x84 /* 32 Bytes Protected Range 4 */
77
Stefan Taunerc0aaf952011-05-19 02:58:17 +000078#define ICH9_REG_SSFS 0x90 /* 08 Bits */
Stefan Tauner0c1ec452011-06-11 09:53:09 +000079#define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */
80#define SSFS_SCIP (0x1 << SSFS_SCIP_OFF)
81#define SSFS_FDONE_OFF 2 /* Cycle Done Status */
82#define SSFS_FDONE (0x1 << SSFS_FDONE_OFF)
83#define SSFS_FCERR_OFF 3 /* Flash Cycle Error */
84#define SSFS_FCERR (0x1 << SSFS_FCERR_OFF)
85#define SSFS_AEL_OFF 4 /* Access Error Log */
86#define SSFS_AEL (0x1 << SSFS_AEL_OFF)
Stefan Taunerc0aaf952011-05-19 02:58:17 +000087/* The following bits are reserved in SSFS: 1,5-7. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +000088#define SSFS_RESERVED_MASK 0x000000e2
Stefan Reinauera9424d52008-06-27 16:28:34 +000089
Stefan Taunerc0aaf952011-05-19 02:58:17 +000090#define ICH9_REG_SSFC 0x91 /* 24 Bits */
Stefan Taunerc0aaf952011-05-19 02:58:17 +000091/* We combine SSFS and SSFC to one 32-bit word,
Stefan Tauner0c1ec452011-06-11 09:53:09 +000092 * therefore SSFC bits are off by 8. */
93 /* 0: reserved */
94#define SSFC_SCGO_OFF (1 + 8) /* 1: SPI Cycle Go */
95#define SSFC_SCGO (0x1 << SSFC_SCGO_OFF)
96#define SSFC_ACS_OFF (2 + 8) /* 2: Atomic Cycle Sequence */
97#define SSFC_ACS (0x1 << SSFC_ACS_OFF)
98#define SSFC_SPOP_OFF (3 + 8) /* 3: Sequence Prefix Opcode Pointer */
99#define SSFC_SPOP (0x1 << SSFC_SPOP_OFF)
100#define SSFC_COP_OFF (4 + 8) /* 4-6: Cycle Opcode Pointer */
101#define SSFC_COP (0x7 << SSFC_COP_OFF)
102 /* 7: reserved */
103#define SSFC_DBC_OFF (8 + 8) /* 8-13: Data Byte Count */
104#define SSFC_DBC (0x3f << SSFC_DBC_OFF)
105#define SSFC_DS_OFF (14 + 8) /* 14: Data Cycle */
106#define SSFC_DS (0x1 << SSFC_DS_OFF)
107#define SSFC_SME_OFF (15 + 8) /* 15: SPI SMI# Enable */
108#define SSFC_SME (0x1 << SSFC_SME_OFF)
109#define SSFC_SCF_OFF (16 + 8) /* 16-18: SPI Cycle Frequency */
110#define SSFC_SCF (0x7 << SSFC_SCF_OFF)
111#define SSFC_SCF_20MHZ 0x00000000
112#define SSFC_SCF_33MHZ 0x01000000
113 /* 19-23: reserved */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000114#define SSFC_RESERVED_MASK 0xf8008100
Stefan Reinauera9424d52008-06-27 16:28:34 +0000115
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000116#define ICH9_REG_PREOP 0x94 /* 16 Bits */
117#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
118#define ICH9_REG_OPMENU 0x98 /* 64 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000119
Stefan Tauner29c80832011-06-12 08:14:10 +0000120#define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */
121#define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */
122
Stefan Taunerbd649e42011-07-01 00:39:16 +0000123#define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */
124#define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */
125#define FPB_FPBA (0x1FFF << FPB_FPBA_OFF)
126
Dominik Geyerb46acba2008-05-16 12:55:55 +0000127// ICH9R SPI commands
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000128#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
129#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
130#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
131#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
Dominik Geyerb46acba2008-05-16 12:55:55 +0000132
Stefan Reinauera9424d52008-06-27 16:28:34 +0000133// ICH7 registers
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000134#define ICH7_REG_SPIS 0x00 /* 16 Bits */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000135#define SPIS_SCIP 0x0001
136#define SPIS_GRANT 0x0002
137#define SPIS_CDS 0x0004
138#define SPIS_FCERR 0x0008
139#define SPIS_RESERVED_MASK 0x7ff0
Stefan Reinauera9424d52008-06-27 16:28:34 +0000140
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000141/* VIA SPI is compatible with ICH7, but maxdata
142 to transfer is 16 bytes.
143
144 DATA byte count on ICH7 is 8:13, on VIA 8:11
145
146 bit 12 is port select CS0 CS1
147 bit 13 is FAST READ enable
148 bit 7 is used with fast read and one shot controls CS de-assert?
149*/
150
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000151#define ICH7_REG_SPIC 0x02 /* 16 Bits */
152#define SPIC_SCGO 0x0002
153#define SPIC_ACS 0x0004
154#define SPIC_SPOP 0x0008
155#define SPIC_DS 0x4000
Stefan Reinauera9424d52008-06-27 16:28:34 +0000156
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000157#define ICH7_REG_SPIA 0x04 /* 32 Bits */
158#define ICH7_REG_SPID0 0x08 /* 64 Bytes */
159#define ICH7_REG_PREOP 0x54 /* 16 Bits */
160#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
161#define ICH7_REG_OPMENU 0x58 /* 64 Bits */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000162
FENG yu ningc05a2952008-12-08 18:16:58 +0000163/* ICH SPI configuration lock-down. May be set during chipset enabling. */
Michael Karchera4448d92010-07-22 18:04:15 +0000164static int ichspi_lock = 0;
FENG yu ningc05a2952008-12-08 18:16:58 +0000165
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000166uint32_t ichspi_bbar = 0;
167
Michael Karchera4448d92010-07-22 18:04:15 +0000168static void *ich_spibar = NULL;
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000169
Dominik Geyerb46acba2008-05-16 12:55:55 +0000170typedef struct _OPCODE {
171 uint8_t opcode; //This commands spi opcode
172 uint8_t spi_type; //This commands spi type
173 uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1
174} OPCODE;
175
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000176/* Suggested opcode definition:
Dominik Geyerb46acba2008-05-16 12:55:55 +0000177 * Preop 1: Write Enable
178 * Preop 2: Write Status register enable
179 *
180 * OP 0: Write address
181 * OP 1: Read Address
182 * OP 2: ERASE block
183 * OP 3: Read Status register
184 * OP 4: Read ID
185 * OP 5: Write Status register
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000186 * OP 6: chip private (read JEDEC id)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000187 * OP 7: Chip erase
188 */
189typedef struct _OPCODES {
190 uint8_t preop[2];
191 OPCODE opcode[8];
192} OPCODES;
193
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000194static OPCODES *curopcodes = NULL;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000195
196/* HW access functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000197static uint32_t REGREAD32(int X)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000198{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000199 return mmio_readl(ich_spibar + X);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000200}
201
Uwe Hermann09e04f72009-05-16 22:36:00 +0000202static uint16_t REGREAD16(int X)
Stefan Reinauera9424d52008-06-27 16:28:34 +0000203{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000204 return mmio_readw(ich_spibar + X);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000205}
206
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000207static uint16_t REGREAD8(int X)
208{
209 return mmio_readb(ich_spibar + X);
210}
211
Stefan Taunerccd92a12011-07-01 00:39:01 +0000212#define REGWRITE32(off, val) mmio_writel(val, ich_spibar+(off))
213#define REGWRITE16(off, val) mmio_writew(val, ich_spibar+(off))
214#define REGWRITE8(off, val) mmio_writeb(val, ich_spibar+(off))
Dominik Geyerb46acba2008-05-16 12:55:55 +0000215
Dominik Geyerb46acba2008-05-16 12:55:55 +0000216/* Common SPI functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000217static int find_opcode(OPCODES *op, uint8_t opcode);
218static int find_preop(OPCODES *op, uint8_t preop);
FENG yu ningf041e9b2008-12-15 02:32:11 +0000219static int generate_opcodes(OPCODES * op);
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000220static int program_opcodes(OPCODES *op, int enable_undo);
Stefan Reinauer43119562008-11-02 19:51:50 +0000221static int run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000222 uint8_t datalength, uint8_t * data);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000223
FENG yu ningf041e9b2008-12-15 02:32:11 +0000224/* for pairing opcodes with their required preop */
225struct preop_opcode_pair {
226 uint8_t preop;
227 uint8_t opcode;
228};
229
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000230/* List of opcodes which need preopcodes and matching preopcodes. Unused. */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000231const struct preop_opcode_pair pops[] = {
FENG yu ningf041e9b2008-12-15 02:32:11 +0000232 {JEDEC_WREN, JEDEC_BYTE_PROGRAM},
233 {JEDEC_WREN, JEDEC_SE}, /* sector erase */
234 {JEDEC_WREN, JEDEC_BE_52}, /* block erase */
235 {JEDEC_WREN, JEDEC_BE_D8}, /* block erase */
236 {JEDEC_WREN, JEDEC_CE_60}, /* chip erase */
237 {JEDEC_WREN, JEDEC_CE_C7}, /* chip erase */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000238 /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */
239 {JEDEC_WREN, JEDEC_WRSR},
FENG yu ningf041e9b2008-12-15 02:32:11 +0000240 {JEDEC_EWSR, JEDEC_WRSR},
241 {0,}
242};
243
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000244/* Reasonable default configuration. Needs ad-hoc modifications if we
245 * encounter unlisted opcodes. Fun.
246 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000247static OPCODES O_ST_M25P = {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000248 {
249 JEDEC_WREN,
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000250 JEDEC_EWSR,
251 },
Dominik Geyerb46acba2008-05-16 12:55:55 +0000252 {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000253 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000254 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000255 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000256 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
Carl-Daniel Hailfinger15aa7c62009-05-26 21:25:08 +0000257 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000258 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000259 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000260 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
261 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000262};
263
Helge Wagner738e2522010-10-05 22:06:05 +0000264/* List of opcodes with their corresponding spi_type
265 * It is used to reprogram the chipset OPCODE table on-the-fly if an opcode
266 * is needed which is currently not in the chipset OPCODE table
267 */
268static OPCODE POSSIBLE_OPCODES[] = {
269 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
270 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
271 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
272 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
273 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
274 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
275 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
276 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
277 {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Sector erase
278 {JEDEC_BE_52, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Block erase
279 {JEDEC_AAI_WORD_PROGRAM, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Auto Address Increment
280};
281
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000282static OPCODES O_EXISTING = {};
FENG yu ningc05a2952008-12-08 18:16:58 +0000283
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000284/* pretty printing functions */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000285static void prettyprint_opcodes(OPCODES *ops)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000286{
287 if(ops == NULL)
288 return;
289
290 msg_pdbg("preop0=0x%02x, preop1=0x%02x\n", ops->preop[0],
291 ops->preop[1]);
292
293 OPCODE oc;
294 uint8_t i;
295 for (i = 0; i < 8; i++) {
296 oc = ops->opcode[i];
297 msg_pdbg("op[%d]=0x%02x, %d, %d\n",
298 i,
299 oc.opcode,
300 oc.spi_type,
301 oc.atomic);
302 }
303}
304
305#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF)
306
Stefan Tauner55206942011-06-11 09:53:22 +0000307static void prettyprint_ich9_reg_hsfs(uint16_t reg_val)
308{
309 msg_pdbg("HSFS: ");
310 pprint_reg(HSFS, FDONE, reg_val, ", ");
311 pprint_reg(HSFS, FCERR, reg_val, ", ");
312 pprint_reg(HSFS, AEL, reg_val, ", ");
313 pprint_reg(HSFS, BERASE, reg_val, ", ");
314 pprint_reg(HSFS, SCIP, reg_val, ", ");
315 pprint_reg(HSFS, FDOPSS, reg_val, ", ");
316 pprint_reg(HSFS, FDV, reg_val, ", ");
317 pprint_reg(HSFS, FLOCKDN, reg_val, "\n");
318}
319
320static void prettyprint_ich9_reg_hsfc(uint16_t reg_val)
321{
322 msg_pdbg("HSFC: ");
323 pprint_reg(HSFC, FGO, reg_val, ", ");
324 pprint_reg(HSFC, FCYCLE, reg_val, ", ");
325 pprint_reg(HSFC, FDBC, reg_val, ", ");
326 pprint_reg(HSFC, SME, reg_val, "\n");
327}
328
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000329static void prettyprint_ich9_reg_ssfs(uint32_t reg_val)
330{
331 msg_pdbg("SSFS: ");
332 pprint_reg(SSFS, SCIP, reg_val, ", ");
333 pprint_reg(SSFS, FDONE, reg_val, ", ");
334 pprint_reg(SSFS, FCERR, reg_val, ", ");
335 pprint_reg(SSFS, AEL, reg_val, "\n");
336}
337
338static void prettyprint_ich9_reg_ssfc(uint32_t reg_val)
339{
340 msg_pdbg("SSFC: ");
341 pprint_reg(SSFC, SCGO, reg_val, ", ");
342 pprint_reg(SSFC, ACS, reg_val, ", ");
343 pprint_reg(SSFC, SPOP, reg_val, ", ");
344 pprint_reg(SSFC, COP, reg_val, ", ");
345 pprint_reg(SSFC, DBC, reg_val, ", ");
346 pprint_reg(SSFC, SME, reg_val, ", ");
347 pprint_reg(SSFC, SCF, reg_val, "\n");
348}
349
Helge Wagner738e2522010-10-05 22:06:05 +0000350static uint8_t lookup_spi_type(uint8_t opcode)
351{
352 int a;
353
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000354 for (a = 0; a < ARRAY_SIZE(POSSIBLE_OPCODES); a++) {
Helge Wagner738e2522010-10-05 22:06:05 +0000355 if (POSSIBLE_OPCODES[a].opcode == opcode)
356 return POSSIBLE_OPCODES[a].spi_type;
357 }
358
359 return 0xFF;
360}
361
362static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt)
363{
364 uint8_t spi_type;
365
366 spi_type = lookup_spi_type(opcode);
367 if (spi_type > 3) {
368 /* Try to guess spi type from read/write sizes.
369 * The following valid writecnt/readcnt combinations exist:
370 * writecnt = 4, readcnt >= 0
371 * writecnt = 1, readcnt >= 0
372 * writecnt >= 4, readcnt = 0
373 * writecnt >= 1, readcnt = 0
374 * writecnt >= 1 is guaranteed for all commands.
375 */
376 if (readcnt == 0)
377 /* if readcnt=0 and writecount >= 4, we don't know if it is WRITE_NO_ADDRESS
378 * or WRITE_WITH_ADDRESS. But if we use WRITE_NO_ADDRESS and the first 3 data
379 * bytes are actual the address, they go to the bus anyhow
380 */
381 spi_type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
382 else if (writecnt == 1) // and readcnt is > 0
383 spi_type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
384 else if (writecnt == 4) // and readcnt is > 0
385 spi_type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
386 // else we have an invalid case, will be handled below
387 }
388 if (spi_type <= 3) {
389 int oppos=2; // use original JEDEC_BE_D8 offset
390 curopcodes->opcode[oppos].opcode = opcode;
391 curopcodes->opcode[oppos].spi_type = spi_type;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000392 program_opcodes(curopcodes, 0);
Helge Wagner738e2522010-10-05 22:06:05 +0000393 oppos = find_opcode(curopcodes, opcode);
394 msg_pdbg ("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos);
395 return oppos;
396 }
397 return -1;
398}
399
Uwe Hermann09e04f72009-05-16 22:36:00 +0000400static int find_opcode(OPCODES *op, uint8_t opcode)
FENG yu ningc05a2952008-12-08 18:16:58 +0000401{
402 int a;
403
404 for (a = 0; a < 8; a++) {
405 if (op->opcode[a].opcode == opcode)
406 return a;
407 }
408
409 return -1;
410}
411
Uwe Hermann09e04f72009-05-16 22:36:00 +0000412static int find_preop(OPCODES *op, uint8_t preop)
FENG yu ningc05a2952008-12-08 18:16:58 +0000413{
414 int a;
415
416 for (a = 0; a < 2; a++) {
417 if (op->preop[a] == preop)
418 return a;
419 }
420
421 return -1;
422}
423
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000424/* Create a struct OPCODES based on what we find in the locked down chipset. */
FENG yu ningf041e9b2008-12-15 02:32:11 +0000425static int generate_opcodes(OPCODES * op)
FENG yu ningc05a2952008-12-08 18:16:58 +0000426{
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000427 int a;
FENG yu ningc05a2952008-12-08 18:16:58 +0000428 uint16_t preop, optype;
429 uint32_t opmenu[2];
FENG yu ningc05a2952008-12-08 18:16:58 +0000430
431 if (op == NULL) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000432 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
FENG yu ningc05a2952008-12-08 18:16:58 +0000433 return -1;
434 }
435
Michael Karcherb9dbe482011-05-11 17:07:07 +0000436 switch (spi_programmer->type) {
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000437 case SPI_CONTROLLER_ICH7:
438 case SPI_CONTROLLER_VIA:
FENG yu ningc05a2952008-12-08 18:16:58 +0000439 preop = REGREAD16(ICH7_REG_PREOP);
440 optype = REGREAD16(ICH7_REG_OPTYPE);
441 opmenu[0] = REGREAD32(ICH7_REG_OPMENU);
442 opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4);
443 break;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000444 case SPI_CONTROLLER_ICH9:
FENG yu ningc05a2952008-12-08 18:16:58 +0000445 preop = REGREAD16(ICH9_REG_PREOP);
446 optype = REGREAD16(ICH9_REG_OPTYPE);
447 opmenu[0] = REGREAD32(ICH9_REG_OPMENU);
448 opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4);
449 break;
450 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000451 msg_perr("%s: unsupported chipset\n", __func__);
FENG yu ningc05a2952008-12-08 18:16:58 +0000452 return -1;
453 }
454
455 op->preop[0] = (uint8_t) preop;
456 op->preop[1] = (uint8_t) (preop >> 8);
457
458 for (a = 0; a < 8; a++) {
459 op->opcode[a].spi_type = (uint8_t) (optype & 0x3);
460 optype >>= 2;
461 }
462
463 for (a = 0; a < 4; a++) {
464 op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff);
465 opmenu[0] >>= 8;
466 }
467
468 for (a = 4; a < 8; a++) {
469 op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff);
470 opmenu[1] >>= 8;
471 }
472
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000473 /* No preopcodes used by default. */
474 for (a = 0; a < 8; a++)
FENG yu ningc05a2952008-12-08 18:16:58 +0000475 op->opcode[a].atomic = 0;
476
FENG yu ningc05a2952008-12-08 18:16:58 +0000477 return 0;
478}
479
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000480static int program_opcodes(OPCODES *op, int enable_undo)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000481{
482 uint8_t a;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000483 uint16_t preop, optype;
484 uint32_t opmenu[2];
Dominik Geyerb46acba2008-05-16 12:55:55 +0000485
486 /* Program Prefix Opcodes */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000487 /* 0:7 Prefix Opcode 1 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000488 preop = (op->preop[0]);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000489 /* 8:16 Prefix Opcode 2 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000490 preop |= ((uint16_t) op->preop[1]) << 8;
Uwe Hermann394131e2008-10-18 21:14:13 +0000491
Stefan Reinauera9424d52008-06-27 16:28:34 +0000492 /* Program Opcode Types 0 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000493 optype = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000494 for (a = 0; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000495 optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000496 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000497
Stefan Reinauera9424d52008-06-27 16:28:34 +0000498 /* Program Allowable Opcodes 0 - 3 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000499 opmenu[0] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000500 for (a = 0; a < 4; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000501 opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000502 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000503
Dominik Geyerb46acba2008-05-16 12:55:55 +0000504 /*Program Allowable Opcodes 4 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000505 opmenu[1] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000506 for (a = 4; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000507 opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000508 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000509
Sean Nelson316a29f2010-05-07 20:09:04 +0000510 msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]);
Michael Karcherb9dbe482011-05-11 17:07:07 +0000511 switch (spi_programmer->type) {
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000512 case SPI_CONTROLLER_ICH7:
513 case SPI_CONTROLLER_VIA:
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000514 /* Register undo only for enable_undo=1, i.e. first call. */
515 if (enable_undo) {
516 rmmio_valw(ich_spibar + ICH7_REG_PREOP);
517 rmmio_valw(ich_spibar + ICH7_REG_OPTYPE);
518 rmmio_vall(ich_spibar + ICH7_REG_OPMENU);
519 rmmio_vall(ich_spibar + ICH7_REG_OPMENU + 4);
520 }
521 mmio_writew(preop, ich_spibar + ICH7_REG_PREOP);
522 mmio_writew(optype, ich_spibar + ICH7_REG_OPTYPE);
523 mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU);
524 mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000525 break;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000526 case SPI_CONTROLLER_ICH9:
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000527 /* Register undo only for enable_undo=1, i.e. first call. */
528 if (enable_undo) {
529 rmmio_valw(ich_spibar + ICH9_REG_PREOP);
530 rmmio_valw(ich_spibar + ICH9_REG_OPTYPE);
531 rmmio_vall(ich_spibar + ICH9_REG_OPMENU);
532 rmmio_vall(ich_spibar + ICH9_REG_OPMENU + 4);
533 }
534 mmio_writew(preop, ich_spibar + ICH9_REG_PREOP);
535 mmio_writew(optype, ich_spibar + ICH9_REG_OPTYPE);
536 mmio_writel(opmenu[0], ich_spibar + ICH9_REG_OPMENU);
537 mmio_writel(opmenu[1], ich_spibar + ICH9_REG_OPMENU + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000538 break;
539 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000540 msg_perr("%s: unsupported chipset\n", __func__);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000541 return -1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000542 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000543
544 return 0;
545}
546
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000547/*
548 * Try to set BBAR (BIOS Base Address Register), but read back the value in case
549 * it didn't stick.
550 */
Stefan Taunere27b2d42011-07-01 00:39:09 +0000551static void ich_set_bbar(uint32_t min_addr)
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000552{
Stefan Taunere27b2d42011-07-01 00:39:09 +0000553 int bbar_off;
Michael Karcherb9dbe482011-05-11 17:07:07 +0000554 switch (spi_programmer->type) {
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000555 case SPI_CONTROLLER_ICH7:
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +0000556 case SPI_CONTROLLER_VIA:
Stefan Taunere27b2d42011-07-01 00:39:09 +0000557 bbar_off = 0x50;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000558 break;
559 case SPI_CONTROLLER_ICH9:
Stefan Taunere27b2d42011-07-01 00:39:09 +0000560 bbar_off = ICH9_REG_BBAR;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000561 break;
562 default:
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +0000563 msg_perr("Unknown chipset for BBAR setting!\n");
Stefan Taunere27b2d42011-07-01 00:39:09 +0000564 return;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000565 }
Stefan Taunere27b2d42011-07-01 00:39:09 +0000566
567 ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK;
568 if (ichspi_bbar) {
569 msg_pdbg("Reserved bits in BBAR not zero: 0x%08x\n",
570 ichspi_bbar);
571 }
572 min_addr &= BBAR_MASK;
573 ichspi_bbar |= min_addr;
574 rmmio_writel(ichspi_bbar, ich_spibar + bbar_off);
575 ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & BBAR_MASK;
576
577 /* We don't have any option except complaining. And if the write
578 * failed, the restore will fail as well, so no problem there.
579 */
580 if (ichspi_bbar != min_addr)
581 msg_perr("Setting BBAR failed!\n");
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000582}
583
Stefan Tauner8b391b82011-08-09 01:49:34 +0000584/* Read len bytes from the fdata/spid register into the data array.
585 *
586 * Note that using len > spi_programmer->max_data_read will return garbage or
587 * may even crash.
588 */
589 static void ich_read_data(uint8_t *data, int len, int reg0_off)
590 {
591 int i;
592 uint32_t temp32 = 0;
593
594 for (i = 0; i < len; i++) {
595 if ((i % 4) == 0)
596 temp32 = REGREAD32(reg0_off + i);
597
598 data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
599 }
600}
601
602/* Fill len bytes from the data array into the fdata/spid registers.
603 *
604 * Note that using len > spi_programmer->max_data_write will trash the registers
605 * following the data registers.
606 */
607static void ich_fill_data(const uint8_t *data, int len, int reg0_off)
608{
609 uint32_t temp32 = 0;
610 int i;
611
612 if (len <= 0)
613 return;
614
615 for (i = 0; i < len; i++) {
616 if ((i % 4) == 0)
617 temp32 = 0;
618
619 temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
620
621 if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
622 REGWRITE32(reg0_off + (i - (i % 4)), temp32);
623 }
624 i--;
625 if ((i % 4) != 3) /* Write remaining data to regs. */
626 REGWRITE32(reg0_off + (i - (i % 4)), temp32);
627}
628
FENG yu ningf041e9b2008-12-15 02:32:11 +0000629/* This function generates OPCODES from or programs OPCODES to ICH according to
630 * the chipset's SPI configuration lock.
FENG yu ningc05a2952008-12-08 18:16:58 +0000631 *
FENG yu ningf041e9b2008-12-15 02:32:11 +0000632 * It should be called before ICH sends any spi command.
FENG yu ningc05a2952008-12-08 18:16:58 +0000633 */
Michael Karchera4448d92010-07-22 18:04:15 +0000634static int ich_init_opcodes(void)
FENG yu ningc05a2952008-12-08 18:16:58 +0000635{
636 int rc = 0;
637 OPCODES *curopcodes_done;
638
639 if (curopcodes)
640 return 0;
641
642 if (ichspi_lock) {
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000643 msg_pdbg("Reading OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000644 curopcodes_done = &O_EXISTING;
FENG yu ningf041e9b2008-12-15 02:32:11 +0000645 rc = generate_opcodes(curopcodes_done);
FENG yu ningc05a2952008-12-08 18:16:58 +0000646 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000647 msg_pdbg("Programming OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000648 curopcodes_done = &O_ST_M25P;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000649 rc = program_opcodes(curopcodes_done, 1);
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000650 /* Technically not part of opcode init, but it allows opcodes
651 * to run without transaction errors by setting the lowest
652 * allowed address to zero.
653 */
654 ich_set_bbar(0);
FENG yu ningc05a2952008-12-08 18:16:58 +0000655 }
656
657 if (rc) {
658 curopcodes = NULL;
Sean Nelson316a29f2010-05-07 20:09:04 +0000659 msg_perr("failed\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000660 return 1;
661 } else {
662 curopcodes = curopcodes_done;
Sean Nelson316a29f2010-05-07 20:09:04 +0000663 msg_pdbg("done\n");
Stefan Tauner8b391b82011-08-09 01:49:34 +0000664 prettyprint_opcodes(curopcodes);
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000665 msg_pdbg("\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000666 return 0;
667 }
668}
669
Stefan Reinauer43119562008-11-02 19:51:50 +0000670static int ich7_run_opcode(OPCODE op, uint32_t offset,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000671 uint8_t datalength, uint8_t * data, int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000672{
673 int write_cmd = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000674 int timeout;
Stefan Tauner8b391b82011-08-09 01:49:34 +0000675 uint32_t temp32;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000676 uint16_t temp16;
Stefan Reinauer43119562008-11-02 19:51:50 +0000677 uint64_t opmenu;
678 int opcode_index;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000679
680 /* Is it a write command? */
681 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
682 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
683 write_cmd = 1;
684 }
685
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000686 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
687 while ((REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) && --timeout) {
688 programmer_delay(10);
689 }
690 if (!timeout) {
691 msg_perr("Error: SCIP never cleared!\n");
692 return 1;
693 }
694
Stefan Tauner10b3e222011-07-01 00:39:23 +0000695 /* Program offset in flash into SPIA while preserving reserved bits. */
696 temp32 = REGREAD32(ICH7_REG_SPIA) & ~0x00FFFFFF;
697 REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000698
Stefan Tauner10b3e222011-07-01 00:39:23 +0000699 /* Program data into SPID0 to N */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000700 if (write_cmd && (datalength != 0))
701 ich_fill_data(data, datalength, ICH7_REG_SPID0);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000702
703 /* Assemble SPIS */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000704 temp16 = REGREAD16(ICH7_REG_SPIS);
705 /* keep reserved bits */
706 temp16 &= SPIS_RESERVED_MASK;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000707 /* clear error status registers */
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000708 temp16 |= (SPIS_CDS | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000709 REGWRITE16(ICH7_REG_SPIS, temp16);
710
711 /* Assemble SPIC */
712 temp16 = 0;
713
714 if (datalength != 0) {
715 temp16 |= SPIC_DS;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000716 temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000717 }
718
719 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000720 opmenu = REGREAD32(ICH7_REG_OPMENU);
721 opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32;
722
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000723 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
724 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000725 break;
726 }
727 opmenu >>= 8;
728 }
729 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000730 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000731 return 1;
732 }
733 temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000734
Michael Karcher136125a2011-04-29 22:11:36 +0000735 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
736 /* Handle Atomic. Atomic commands include three steps:
737 - sending the preop (mainly EWSR or WREN)
738 - sending the main command
739 - waiting for the busy bit (WIP) to be cleared
740 This means the timeout must be sufficient for chip erase
741 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000742 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000743 switch (op.atomic) {
744 case 2:
745 /* Select second preop. */
746 temp16 |= SPIC_SPOP;
747 /* And fall through. */
748 case 1:
749 /* Atomic command (preop+op) */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000750 temp16 |= SPIC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +0000751 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000752 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000753 }
754
755 /* Start */
756 temp16 |= SPIC_SCGO;
757
758 /* write it */
759 REGWRITE16(ICH7_REG_SPIC, temp16);
760
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000761 /* Wait for Cycle Done Status or Flash Cycle Error. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000762 while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) &&
763 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000764 programmer_delay(10);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000765 }
766 if (!timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000767 msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n",
768 REGREAD16(ICH7_REG_SPIS));
769 return 1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000770 }
771
Sean Nelson316a29f2010-05-07 20:09:04 +0000772 /* FIXME: make sure we do not needlessly cause transaction errors. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000773 temp16 = REGREAD16(ICH7_REG_SPIS);
774 if (temp16 & SPIS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +0000775 msg_perr("Transaction error!\n");
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000776 /* keep reserved bits */
777 temp16 &= SPIS_RESERVED_MASK;
778 REGWRITE16(ICH7_REG_SPIS, temp16 | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000779 return 1;
780 }
781
Stefan Tauner8b391b82011-08-09 01:49:34 +0000782 if ((!write_cmd) && (datalength != 0))
783 ich_read_data(data, datalength, ICH7_REG_SPID0);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000784
785 return 0;
786}
787
Stefan Reinauer43119562008-11-02 19:51:50 +0000788static int ich9_run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000789 uint8_t datalength, uint8_t * data)
790{
791 int write_cmd = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000792 int timeout;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000793 uint32_t temp32;
Stefan Reinauer43119562008-11-02 19:51:50 +0000794 uint64_t opmenu;
795 int opcode_index;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000796
797 /* Is it a write command? */
798 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
799 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
800 write_cmd = 1;
801 }
802
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000803 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
804 while ((REGREAD8(ICH9_REG_SSFS) & SSFS_SCIP) && --timeout) {
805 programmer_delay(10);
806 }
807 if (!timeout) {
808 msg_perr("Error: SCIP never cleared!\n");
809 return 1;
810 }
811
Stefan Tauner10b3e222011-07-01 00:39:23 +0000812 /* Program offset in flash into FADDR while preserve the reserved bits
813 * and clearing the 25. address bit which is only useable in hwseq. */
814 temp32 = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF;
815 REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000816
817 /* Program data into FDATA0 to N */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000818 if (write_cmd && (datalength != 0))
819 ich_fill_data(data, datalength, ICH9_REG_FDATA0);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000820
821 /* Assemble SSFS + SSFC */
Helge Wagnera319be12010-08-11 21:06:10 +0000822 temp32 = REGREAD32(ICH9_REG_SSFS);
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000823 /* Keep reserved bits only */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000824 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000825 /* Clear cycle done and cycle error status registers */
826 temp32 |= (SSFS_FDONE | SSFS_FCERR);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000827 REGWRITE32(ICH9_REG_SSFS, temp32);
828
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000829 /* Use 20 MHz */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000830 temp32 |= SSFC_SCF_20MHZ;
831
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000832 /* Set data byte count (DBC) and data cycle bit (DS) */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000833 if (datalength != 0) {
834 uint32_t datatemp;
835 temp32 |= SSFC_DS;
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000836 datatemp = ((((uint32_t)datalength - 1) << SSFC_DBC_OFF) &
837 SSFC_DBC);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000838 temp32 |= datatemp;
839 }
840
841 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000842 opmenu = REGREAD32(ICH9_REG_OPMENU);
843 opmenu |= ((uint64_t)REGREAD32(ICH9_REG_OPMENU + 4)) << 32;
844
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000845 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
846 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000847 break;
848 }
849 opmenu >>= 8;
850 }
851 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000852 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000853 return 1;
854 }
855 temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000856
Michael Karcher136125a2011-04-29 22:11:36 +0000857 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
858 /* Handle Atomic. Atomic commands include three steps:
859 - sending the preop (mainly EWSR or WREN)
860 - sending the main command
861 - waiting for the busy bit (WIP) to be cleared
862 This means the timeout must be sufficient for chip erase
863 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000864 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000865 switch (op.atomic) {
866 case 2:
867 /* Select second preop. */
868 temp32 |= SSFC_SPOP;
869 /* And fall through. */
870 case 1:
871 /* Atomic command (preop+op) */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000872 temp32 |= SSFC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +0000873 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000874 break;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000875 }
876
877 /* Start */
878 temp32 |= SSFC_SCGO;
879
880 /* write it */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000881 REGWRITE32(ICH9_REG_SSFS, temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000882
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000883 /* Wait for Cycle Done Status or Flash Cycle Error. */
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000884 while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_FDONE | SSFS_FCERR)) == 0) &&
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000885 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000886 programmer_delay(10);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000887 }
888 if (!timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000889 msg_perr("timeout, ICH9_REG_SSFS=0x%08x\n",
890 REGREAD32(ICH9_REG_SSFS));
891 return 1;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000892 }
893
Sean Nelson316a29f2010-05-07 20:09:04 +0000894 /* FIXME make sure we do not needlessly cause transaction errors. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000895 temp32 = REGREAD32(ICH9_REG_SSFS);
896 if (temp32 & SSFS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +0000897 msg_perr("Transaction error!\n");
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000898 prettyprint_ich9_reg_ssfs(temp32);
899 prettyprint_ich9_reg_ssfc(temp32);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000900 /* keep reserved bits */
901 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
902 /* Clear the transaction error. */
903 REGWRITE32(ICH9_REG_SSFS, temp32 | SSFS_FCERR);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000904 return 1;
905 }
906
Stefan Tauner8b391b82011-08-09 01:49:34 +0000907 if ((!write_cmd) && (datalength != 0))
908 ich_read_data(data, datalength, ICH9_REG_FDATA0);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000909
910 return 0;
911}
912
Stefan Reinauer43119562008-11-02 19:51:50 +0000913static int run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000914 uint8_t datalength, uint8_t * data)
915{
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000916 /* max_data_read == max_data_write for all Intel/VIA SPI masters */
917 uint8_t maxlength = spi_programmer->max_data_read;
918
919 if (spi_programmer->type == SPI_CONTROLLER_NONE) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000920 msg_perr("%s: unsupported chipset\n", __func__);
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000921 return -1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000922 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000923
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000924 if (datalength > maxlength) {
925 msg_perr("%s: Internal command size error for "
926 "opcode 0x%02x, got datalength=%i, want <=%i\n",
927 __func__, op.opcode, datalength, maxlength);
928 return SPI_INVALID_LENGTH;
929 }
930
931 switch (spi_programmer->type) {
932 case SPI_CONTROLLER_VIA:
933 case SPI_CONTROLLER_ICH7:
934 return ich7_run_opcode(op, offset, datalength, data, maxlength);
935 case SPI_CONTROLLER_ICH9:
936 return ich9_run_opcode(op, offset, datalength, data);
937 default:
938 /* If we ever get here, something really weird happened */
939 return -1;
940 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000941}
942
Michael Karcherb9dbe482011-05-11 17:07:07 +0000943static int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000944 const unsigned char *writearr, unsigned char *readarr)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000945{
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000946 int result;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000947 int opcode_index = -1;
948 const unsigned char cmd = *writearr;
949 OPCODE *opcode;
950 uint32_t addr = 0;
951 uint8_t *data;
952 int count;
953
Dominik Geyerb46acba2008-05-16 12:55:55 +0000954 /* find cmd in opcodes-table */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000955 opcode_index = find_opcode(curopcodes, cmd);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000956 if (opcode_index == -1) {
Helge Wagner738e2522010-10-05 22:06:05 +0000957 if (!ichspi_lock)
958 opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt);
959 if (opcode_index == -1) {
Stefan Tauner355cbfd2011-05-28 02:37:14 +0000960 msg_pdbg("Invalid OPCODE 0x%02x, will not execute.\n",
961 cmd);
Helge Wagner738e2522010-10-05 22:06:05 +0000962 return SPI_INVALID_OPCODE;
963 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000964 }
965
966 opcode = &(curopcodes->opcode[opcode_index]);
967
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000968 /* The following valid writecnt/readcnt combinations exist:
969 * writecnt = 4, readcnt >= 0
970 * writecnt = 1, readcnt >= 0
971 * writecnt >= 4, readcnt = 0
972 * writecnt >= 1, readcnt = 0
973 * writecnt >= 1 is guaranteed for all commands.
974 */
975 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) &&
976 (writecnt != 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000977 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000978 "0x%02x, got writecnt=%i, want =4\n", __func__, cmd,
979 writecnt);
980 return SPI_INVALID_LENGTH;
981 }
982 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) &&
983 (writecnt != 1)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000984 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000985 "0x%02x, got writecnt=%i, want =1\n", __func__, cmd,
986 writecnt);
987 return SPI_INVALID_LENGTH;
988 }
989 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) &&
990 (writecnt < 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000991 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000992 "0x%02x, got writecnt=%i, want >=4\n", __func__, cmd,
993 writecnt);
994 return SPI_INVALID_LENGTH;
995 }
996 if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
997 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) &&
998 (readcnt)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000999 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001000 "0x%02x, got readcnt=%i, want =0\n", __func__, cmd,
1001 readcnt);
1002 return SPI_INVALID_LENGTH;
1003 }
1004
Dominik Geyerb46acba2008-05-16 12:55:55 +00001005 /* if opcode-type requires an address */
1006 if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS ||
1007 opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001008 addr = (writearr[1] << 16) |
1009 (writearr[2] << 8) | (writearr[3] << 0);
Michael Karcherb9dbe482011-05-11 17:07:07 +00001010 switch (spi_programmer->type) {
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +00001011 case SPI_CONTROLLER_ICH7:
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00001012 case SPI_CONTROLLER_VIA:
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +00001013 case SPI_CONTROLLER_ICH9:
1014 if (addr < ichspi_bbar) {
1015 msg_perr("%s: Address 0x%06x below allowed "
1016 "range 0x%06x-0xffffff\n", __func__,
1017 addr, ichspi_bbar);
1018 return SPI_INVALID_ADDRESS;
1019 }
1020 break;
1021 default:
1022 break;
1023 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001024 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001025
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001026 /* Translate read/write array/count.
1027 * The maximum data length is identical for the maximum read length and
1028 * for the maximum write length excluding opcode and address. Opcode and
1029 * address are stored in separate registers, not in the data registers
1030 * and are thus not counted towards data length. The only exception
1031 * applies if the opcode definition (un)intentionally classifies said
1032 * opcode incorrectly as non-address opcode or vice versa. */
Dominik Geyerb46acba2008-05-16 12:55:55 +00001033 if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001034 data = (uint8_t *) (writearr + 1);
1035 count = writecnt - 1;
1036 } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
1037 data = (uint8_t *) (writearr + 4);
1038 count = writecnt - 4;
1039 } else {
1040 data = (uint8_t *) readarr;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001041 count = readcnt;
1042 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001043
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001044 result = run_opcode(*opcode, addr, count, data);
1045 if (result) {
Stefan Tauner8ed29342011-04-29 23:53:09 +00001046 msg_pdbg("Running OPCODE 0x%02x failed ", opcode->opcode);
1047 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1048 (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS)) {
1049 msg_pdbg("at address 0x%06x ", addr);
1050 }
1051 msg_pdbg("(payload length was %d).\n", count);
1052
1053 /* Print out the data array if it contains data to write.
1054 * Errors are detected before the received data is read back into
1055 * the array so it won't make sense to print it then. */
1056 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1057 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) {
1058 int i;
1059 msg_pspew("The data was:\n");
1060 for(i=0; i<count; i++){
1061 msg_pspew("%3d: 0x%02x\n", i, data[i]);
1062 }
1063 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001064 }
1065
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001066 return result;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001067}
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001068
Michael Karcherb9dbe482011-05-11 17:07:07 +00001069static int ich_spi_send_multicommand(struct spi_command *cmds)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001070{
1071 int ret = 0;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001072 int i;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001073 int oppos, preoppos;
1074 for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) {
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001075 if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001076 /* Next command is valid. */
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001077 preoppos = find_preop(curopcodes, cmds->writearr[0]);
1078 oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001079 if ((oppos == -1) && (preoppos != -1)) {
1080 /* Current command is listed as preopcode in
1081 * ICH struct OPCODES, but next command is not
1082 * listed as opcode in that struct.
1083 * Check for command sanity, then
1084 * try to reprogram the ICH opcode list.
1085 */
1086 if (find_preop(curopcodes,
1087 (cmds + 1)->writearr[0]) != -1) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001088 msg_perr("%s: Two subsequent "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001089 "preopcodes 0x%02x and 0x%02x, "
1090 "ignoring the first.\n",
1091 __func__, cmds->writearr[0],
1092 (cmds + 1)->writearr[0]);
1093 continue;
1094 }
1095 /* If the chipset is locked down, we'll fail
1096 * during execution of the next command anyway.
1097 * No need to bother with fixups.
1098 */
1099 if (!ichspi_lock) {
Helge Wagner738e2522010-10-05 22:06:05 +00001100 oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt);
1101 if (oppos == -1)
1102 continue;
1103 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001104 continue;
1105 }
1106 }
1107 if ((oppos != -1) && (preoppos != -1)) {
1108 /* Current command is listed as preopcode in
1109 * ICH struct OPCODES and next command is listed
1110 * as opcode in that struct. Match them up.
1111 */
1112 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001113 continue;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001114 }
1115 /* If none of the above if-statements about oppos or
1116 * preoppos matched, this is a normal opcode.
1117 */
1118 }
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001119 ret = ich_spi_send_command(cmds->writecnt, cmds->readcnt,
1120 cmds->writearr, cmds->readarr);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001121 /* Reset the type of all opcodes to non-atomic. */
1122 for (i = 0; i < 8; i++)
1123 curopcodes->opcode[i].atomic = 0;
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001124 }
1125 return ret;
1126}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001127
Michael Karchera4448d92010-07-22 18:04:15 +00001128#define ICH_BMWAG(x) ((x >> 24) & 0xff)
1129#define ICH_BMRAG(x) ((x >> 16) & 0xff)
1130#define ICH_BRWA(x) ((x >> 8) & 0xff)
1131#define ICH_BRRA(x) ((x >> 0) & 0xff)
1132
1133#define ICH_FREG_BASE(x) ((x >> 0) & 0x1fff)
1134#define ICH_FREG_LIMIT(x) ((x >> 16) & 0x1fff)
1135
1136static void do_ich9_spi_frap(uint32_t frap, int i)
1137{
Mathias Krausea60faab2011-01-17 07:50:42 +00001138 static const char *const access_names[4] = {
Michael Karchera4448d92010-07-22 18:04:15 +00001139 "locked", "read-only", "write-only", "read-write"
1140 };
Mathias Krausea60faab2011-01-17 07:50:42 +00001141 static const char *const region_names[5] = {
Michael Karchera4448d92010-07-22 18:04:15 +00001142 "Flash Descriptor", "BIOS", "Management Engine",
1143 "Gigabit Ethernet", "Platform Data"
1144 };
1145 uint32_t base, limit;
1146 int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) |
1147 (((ICH_BRRA(frap) >> i) & 1) << 0);
Stefan Tauner29c80832011-06-12 08:14:10 +00001148 int offset = ICH9_REG_FREG0 + i * 4;
Michael Karchera4448d92010-07-22 18:04:15 +00001149 uint32_t freg = mmio_readl(ich_spibar + offset);
1150
1151 msg_pdbg("0x%02X: 0x%08x (FREG%i: %s)\n",
1152 offset, freg, i, region_names[i]);
1153
1154 base = ICH_FREG_BASE(freg);
1155 limit = ICH_FREG_LIMIT(freg);
Joshua Roysd172ecd2011-05-26 13:30:51 +00001156 if (base > limit) {
Michael Karchera4448d92010-07-22 18:04:15 +00001157 /* this FREG is disabled */
1158 msg_pdbg("%s region is unused.\n", region_names[i]);
1159 return;
1160 }
1161
1162 msg_pdbg("0x%08x-0x%08x is %s\n",
1163 (base << 12), (limit << 12) | 0x0fff,
1164 access_names[rwperms]);
1165}
1166
Michael Karcherb9dbe482011-05-11 17:07:07 +00001167static const struct spi_programmer spi_programmer_ich7 = {
1168 .type = SPI_CONTROLLER_ICH7,
1169 .max_data_read = 64,
1170 .max_data_write = 64,
1171 .command = ich_spi_send_command,
1172 .multicommand = ich_spi_send_multicommand,
1173 .read = default_spi_read,
1174 .write_256 = default_spi_write_256,
1175};
1176
1177static const struct spi_programmer spi_programmer_ich9 = {
1178 .type = SPI_CONTROLLER_ICH9,
1179 .max_data_read = 64,
1180 .max_data_write = 64,
1181 .command = ich_spi_send_command,
1182 .multicommand = ich_spi_send_multicommand,
1183 .read = default_spi_read,
1184 .write_256 = default_spi_write_256,
1185};
1186
Michael Karchera4448d92010-07-22 18:04:15 +00001187int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
1188 int ich_generation)
1189{
1190 int i;
1191 uint8_t old, new;
1192 uint16_t spibar_offset, tmp2;
1193 uint32_t tmp;
1194
Michael Karchera4448d92010-07-22 18:04:15 +00001195 switch (ich_generation) {
1196 case 7:
Michael Karcherb9dbe482011-05-11 17:07:07 +00001197 register_spi_programmer(&spi_programmer_ich7);
Michael Karchera4448d92010-07-22 18:04:15 +00001198 spibar_offset = 0x3020;
1199 break;
1200 case 8:
Michael Karcherb9dbe482011-05-11 17:07:07 +00001201 register_spi_programmer(&spi_programmer_ich9);
Michael Karchera4448d92010-07-22 18:04:15 +00001202 spibar_offset = 0x3020;
1203 break;
1204 case 9:
1205 case 10:
1206 default: /* Future version might behave the same */
Michael Karcherb9dbe482011-05-11 17:07:07 +00001207 register_spi_programmer(&spi_programmer_ich9);
Michael Karchera4448d92010-07-22 18:04:15 +00001208 spibar_offset = 0x3800;
1209 break;
1210 }
1211
1212 /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
1213 msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", base, spibar_offset);
1214
1215 /* Assign Virtual Address */
1216 ich_spibar = rcrb + spibar_offset;
1217
Michael Karcherb9dbe482011-05-11 17:07:07 +00001218 switch (spi_programmer->type) {
Michael Karchera4448d92010-07-22 18:04:15 +00001219 case SPI_CONTROLLER_ICH7:
1220 msg_pdbg("0x00: 0x%04x (SPIS)\n",
1221 mmio_readw(ich_spibar + 0));
1222 msg_pdbg("0x02: 0x%04x (SPIC)\n",
1223 mmio_readw(ich_spibar + 2));
1224 msg_pdbg("0x04: 0x%08x (SPIA)\n",
1225 mmio_readl(ich_spibar + 4));
1226 for (i = 0; i < 8; i++) {
1227 int offs;
1228 offs = 8 + (i * 8);
1229 msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs,
1230 mmio_readl(ich_spibar + offs), i);
1231 msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
1232 mmio_readl(ich_spibar + offs + 4), i);
1233 }
1234 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
1235 msg_pdbg("0x50: 0x%08x (BBAR)\n",
1236 ichspi_bbar);
1237 msg_pdbg("0x54: 0x%04x (PREOP)\n",
1238 mmio_readw(ich_spibar + 0x54));
1239 msg_pdbg("0x56: 0x%04x (OPTYPE)\n",
1240 mmio_readw(ich_spibar + 0x56));
1241 msg_pdbg("0x58: 0x%08x (OPMENU)\n",
1242 mmio_readl(ich_spibar + 0x58));
1243 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n",
1244 mmio_readl(ich_spibar + 0x5c));
Stefan Tauner122dd122011-07-24 15:34:56 +00001245 for (i = 0; i < 3; i++) {
Michael Karchera4448d92010-07-22 18:04:15 +00001246 int offs;
1247 offs = 0x60 + (i * 4);
1248 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
1249 mmio_readl(ich_spibar + offs), i);
1250 }
Michael Karchera4448d92010-07-22 18:04:15 +00001251 if (mmio_readw(ich_spibar) & (1 << 15)) {
1252 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
1253 ichspi_lock = 1;
1254 }
1255 ich_init_opcodes();
1256 break;
1257 case SPI_CONTROLLER_ICH9:
Stefan Tauner29c80832011-06-12 08:14:10 +00001258 tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS);
Michael Karchera4448d92010-07-22 18:04:15 +00001259 msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2);
Stefan Tauner55206942011-06-11 09:53:22 +00001260 prettyprint_ich9_reg_hsfs(tmp2);
Stefan Tauner29c80832011-06-12 08:14:10 +00001261 if (tmp2 & HSFS_FLOCKDN) {
Stefan Tauner55206942011-06-11 09:53:22 +00001262 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
1263 ichspi_lock = 1;
1264 }
1265
Stefan Tauner29c80832011-06-12 08:14:10 +00001266 tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC);
Stefan Tauner55206942011-06-11 09:53:22 +00001267 msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2);
1268 prettyprint_ich9_reg_hsfc(tmp2);
Michael Karchera4448d92010-07-22 18:04:15 +00001269
Stefan Tauner5ffe65b2011-07-07 04:10:57 +00001270 tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR);
1271 msg_pdbg("0x08: 0x%08x (FADDR)\n", tmp);
Stefan Tauner29c80832011-06-12 08:14:10 +00001272 tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP);
Michael Karchera4448d92010-07-22 18:04:15 +00001273 msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp);
1274 msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp));
1275 msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp));
1276 msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp));
1277 msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp));
1278
1279 /* print out the FREGx registers along with FRAP access bits */
1280 for(i = 0; i < 5; i++)
1281 do_ich9_spi_frap(tmp, i);
1282
1283 msg_pdbg("0x74: 0x%08x (PR0)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001284 mmio_readl(ich_spibar + ICH9_REG_PR0));
Michael Karchera4448d92010-07-22 18:04:15 +00001285 msg_pdbg("0x78: 0x%08x (PR1)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001286 mmio_readl(ich_spibar + ICH9_REG_PR1));
Michael Karchera4448d92010-07-22 18:04:15 +00001287 msg_pdbg("0x7C: 0x%08x (PR2)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001288 mmio_readl(ich_spibar + ICH9_REG_PR2));
Michael Karchera4448d92010-07-22 18:04:15 +00001289 msg_pdbg("0x80: 0x%08x (PR3)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001290 mmio_readl(ich_spibar + ICH9_REG_PR3));
Michael Karchera4448d92010-07-22 18:04:15 +00001291 msg_pdbg("0x84: 0x%08x (PR4)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001292 mmio_readl(ich_spibar + ICH9_REG_PR4));
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001293
Stefan Tauner29c80832011-06-12 08:14:10 +00001294 tmp = mmio_readl(ich_spibar + ICH9_REG_SSFS);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001295 msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff);
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001296 prettyprint_ich9_reg_ssfs(tmp);
Stefan Tauner29c80832011-06-12 08:14:10 +00001297 if (tmp & SSFS_FCERR) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001298 msg_pdbg("Clearing SSFS.FCERR\n");
Stefan Tauner29c80832011-06-12 08:14:10 +00001299 mmio_writeb(SSFS_FCERR, ich_spibar + ICH9_REG_SSFS);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001300 }
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001301 msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp >> 8);
1302 prettyprint_ich9_reg_ssfc(tmp);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001303
Michael Karchera4448d92010-07-22 18:04:15 +00001304 msg_pdbg("0x94: 0x%04x (PREOP)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001305 mmio_readw(ich_spibar + ICH9_REG_PREOP));
Michael Karchera4448d92010-07-22 18:04:15 +00001306 msg_pdbg("0x96: 0x%04x (OPTYPE)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001307 mmio_readw(ich_spibar + ICH9_REG_OPTYPE));
Michael Karchera4448d92010-07-22 18:04:15 +00001308 msg_pdbg("0x98: 0x%08x (OPMENU)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001309 mmio_readl(ich_spibar + ICH9_REG_OPMENU));
Michael Karchera4448d92010-07-22 18:04:15 +00001310 msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001311 mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4));
1312 ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR);
Michael Karchera4448d92010-07-22 18:04:15 +00001313 msg_pdbg("0xA0: 0x%08x (BBAR)\n",
1314 ichspi_bbar);
Stefan Taunerbd649e42011-07-01 00:39:16 +00001315 tmp = mmio_readl(ich_spibar + ICH9_REG_FPB);
1316 msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp);
1317
Michael Karchera4448d92010-07-22 18:04:15 +00001318 ich_init_opcodes();
1319 break;
1320 default:
1321 /* Nothing */
1322 break;
1323 }
1324
1325 old = pci_read_byte(dev, 0xdc);
1326 msg_pdbg("SPI Read Configuration: ");
1327 new = (old >> 2) & 0x3;
1328 switch (new) {
1329 case 0:
1330 case 1:
1331 case 2:
1332 msg_pdbg("prefetching %sabled, caching %sabled, ",
1333 (new & 0x2) ? "en" : "dis",
1334 (new & 0x1) ? "dis" : "en");
1335 break;
1336 default:
1337 msg_pdbg("invalid prefetching/caching settings, ");
1338 break;
1339 }
1340 return 0;
1341}
1342
Michael Karcherb9dbe482011-05-11 17:07:07 +00001343static const struct spi_programmer spi_programmer_via = {
1344 .type = SPI_CONTROLLER_VIA,
1345 .max_data_read = 16,
1346 .max_data_write = 16,
1347 .command = ich_spi_send_command,
1348 .multicommand = ich_spi_send_multicommand,
1349 .read = default_spi_read,
1350 .write_256 = default_spi_write_256,
1351};
1352
Michael Karchera4448d92010-07-22 18:04:15 +00001353int via_init_spi(struct pci_dev *dev)
1354{
1355 uint32_t mmio_base;
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00001356 int i;
Michael Karchera4448d92010-07-22 18:04:15 +00001357
1358 mmio_base = (pci_read_long(dev, 0xbc)) << 8;
1359 msg_pdbg("MMIO base at = 0x%x\n", mmio_base);
1360 ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70);
1361
Michael Karchera4448d92010-07-22 18:04:15 +00001362 /* Not sure if it speaks all these bus protocols. */
Carl-Daniel Hailfinger1a227952011-07-27 07:13:06 +00001363 buses_supported = BUS_LPC | BUS_FWH;
Michael Karcherb9dbe482011-05-11 17:07:07 +00001364 register_spi_programmer(&spi_programmer_via);
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00001365
1366 msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0));
1367 msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2));
1368 msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(ich_spibar + 4));
1369 for (i = 0; i < 2; i++) {
1370 int offs;
1371 offs = 8 + (i * 8);
1372 msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs,
1373 mmio_readl(ich_spibar + offs), i);
1374 msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
1375 mmio_readl(ich_spibar + offs + 4), i);
1376 }
1377 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
1378 msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar);
1379 msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x54));
1380 msg_pdbg("0x56: 0x%04x (OPTYPE)\n", mmio_readw(ich_spibar + 0x56));
1381 msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(ich_spibar + 0x58));
1382 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + 0x5c));
1383 for (i = 0; i < 3; i++) {
1384 int offs;
1385 offs = 0x60 + (i * 4);
1386 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
1387 mmio_readl(ich_spibar + offs), i);
1388 }
1389 msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n",
1390 mmio_readw(ich_spibar + 0x6c));
1391 if (mmio_readw(ich_spibar) & (1 << 15)) {
1392 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
1393 ichspi_lock = 1;
1394 }
1395
Michael Karchera4448d92010-07-22 18:04:15 +00001396 ich_init_opcodes();
1397
1398 return 0;
1399}
1400
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001401#endif