Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the flashrom project. |
| 3 | * |
| 4 | * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com> |
| 5 | * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com> |
| 6 | * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com> |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 7 | * Copyright (C) 2008 coresystems GmbH <info@coresystems.de> |
Carl-Daniel Hailfinger | 5824fbf | 2010-05-21 23:09:42 +0000 | [diff] [blame] | 8 | * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger |
Stefan Tauner | 8b391b8 | 2011-08-09 01:49:34 +0000 | [diff] [blame] | 9 | * Copyright (C) 2011 Stefan Tauner |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or |
| 14 | * (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 20 | */ |
| 21 | |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 22 | #if defined(__i386__) || defined(__x86_64__) |
| 23 | |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 24 | #include <string.h> |
Stefan Tauner | d0c5dc2 | 2011-10-20 12:57:14 +0000 | [diff] [blame] | 25 | #include <stdlib.h> |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 26 | #include "flash.h" |
Carl-Daniel Hailfinger | 5b997c3 | 2010-07-27 22:41:39 +0000 | [diff] [blame] | 27 | #include "programmer.h" |
Patrick Georgi | 32508eb | 2012-07-20 20:35:14 +0000 | [diff] [blame] | 28 | #include "hwaccess.h" |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 29 | #include "spi.h" |
Stefan Tauner | 1e14639 | 2011-09-15 23:52:55 +0000 | [diff] [blame] | 30 | #include "ich_descriptors.h" |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 31 | |
Nico Huber | d2d3993 | 2019-01-18 16:49:37 +0100 | [diff] [blame] | 32 | /* Apollo Lake */ |
| 33 | #define APL_REG_FREG12 0xe0 /* 32 Bytes Flash Region 12 */ |
| 34 | |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 35 | /* Sunrise Point */ |
| 36 | |
| 37 | /* Added HSFS Status bits */ |
| 38 | #define HSFS_WRSDIS_OFF 11 /* 11: Flash Configuration Lock-Down */ |
| 39 | #define HSFS_WRSDIS (0x1 << HSFS_WRSDIS_OFF) |
| 40 | #define HSFS_PRR34_LOCKDN_OFF 12 /* 12: PRR3 PRR4 Lock-Down */ |
| 41 | #define HSFS_PRR34_LOCKDN (0x1 << HSFS_PRR34_LOCKDN_OFF) |
| 42 | /* HSFS_BERASE vanished */ |
| 43 | |
| 44 | /* |
| 45 | * HSFC and HSFS 16-bit registers are combined into the 32-bit |
| 46 | * BIOS_HSFSTS_CTL register in the Sunrise Point datasheet, |
| 47 | * however we still treat them separately in order to reuse code. |
| 48 | */ |
| 49 | |
| 50 | /* Changed HSFC Control bits */ |
| 51 | #define PCH100_HSFC_FCYCLE_OFF (17 - 16) /* 1-4: FLASH Cycle */ |
| 52 | #define PCH100_HSFC_FCYCLE (0xf << PCH100_HSFC_FCYCLE_OFF) |
| 53 | /* New HSFC Control bit */ |
| 54 | #define HSFC_WET_OFF (21 - 16) /* 5: Write Enable Type */ |
| 55 | #define HSFC_WET (0x1 << HSFC_WET_OFF) |
| 56 | |
| 57 | #define PCH100_FADDR_FLA 0x07ffffff |
| 58 | |
| 59 | #define PCH100_REG_DLOCK 0x0c /* 32 Bits Discrete Lock Bits */ |
| 60 | #define DLOCK_BMWAG_LOCKDN_OFF 0 |
| 61 | #define DLOCK_BMWAG_LOCKDN (0x1 << DLOCK_BMWAG_LOCKDN_OFF) |
| 62 | #define DLOCK_BMRAG_LOCKDN_OFF 1 |
| 63 | #define DLOCK_BMRAG_LOCKDN (0x1 << DLOCK_BMRAG_LOCKDN_OFF) |
| 64 | #define DLOCK_SBMWAG_LOCKDN_OFF 2 |
| 65 | #define DLOCK_SBMWAG_LOCKDN (0x1 << DLOCK_SBMWAG_LOCKDN_OFF) |
| 66 | #define DLOCK_SBMRAG_LOCKDN_OFF 3 |
| 67 | #define DLOCK_SBMRAG_LOCKDN (0x1 << DLOCK_SBMRAG_LOCKDN_OFF) |
| 68 | #define DLOCK_PR0_LOCKDN_OFF 8 |
| 69 | #define DLOCK_PR0_LOCKDN (0x1 << DLOCK_PR0_LOCKDN_OFF) |
| 70 | #define DLOCK_PR1_LOCKDN_OFF 9 |
| 71 | #define DLOCK_PR1_LOCKDN (0x1 << DLOCK_PR1_LOCKDN_OFF) |
| 72 | #define DLOCK_PR2_LOCKDN_OFF 10 |
| 73 | #define DLOCK_PR2_LOCKDN (0x1 << DLOCK_PR2_LOCKDN_OFF) |
| 74 | #define DLOCK_PR3_LOCKDN_OFF 11 |
| 75 | #define DLOCK_PR3_LOCKDN (0x1 << DLOCK_PR3_LOCKDN_OFF) |
| 76 | #define DLOCK_PR4_LOCKDN_OFF 12 |
| 77 | #define DLOCK_PR4_LOCKDN (0x1 << DLOCK_PR4_LOCKDN_OFF) |
| 78 | #define DLOCK_SSEQ_LOCKDN_OFF 16 |
| 79 | #define DLOCK_SSEQ_LOCKDN (0x1 << DLOCK_SSEQ_LOCKDN_OFF) |
| 80 | |
| 81 | #define PCH100_REG_FPR0 0x84 /* 32 Bits Protected Range 0 */ |
| 82 | #define PCH100_REG_GPR0 0x98 /* 32 Bits Global Protected Range 0 */ |
| 83 | |
| 84 | #define PCH100_REG_SSFSC 0xA0 /* 32 Bits Status (8) + Control (24) */ |
| 85 | #define PCH100_REG_PREOP 0xA4 /* 16 Bits */ |
| 86 | #define PCH100_REG_OPTYPE 0xA6 /* 16 Bits */ |
| 87 | #define PCH100_REG_OPMENU 0xA8 /* 64 Bits */ |
| 88 | |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 89 | /* ICH9 controller register definition */ |
Stefan Tauner | 5520694 | 2011-06-11 09:53:22 +0000 | [diff] [blame] | 90 | #define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */ |
| 91 | #define HSFS_FDONE_OFF 0 /* 0: Flash Cycle Done */ |
| 92 | #define HSFS_FDONE (0x1 << HSFS_FDONE_OFF) |
| 93 | #define HSFS_FCERR_OFF 1 /* 1: Flash Cycle Error */ |
| 94 | #define HSFS_FCERR (0x1 << HSFS_FCERR_OFF) |
| 95 | #define HSFS_AEL_OFF 2 /* 2: Access Error Log */ |
| 96 | #define HSFS_AEL (0x1 << HSFS_AEL_OFF) |
| 97 | #define HSFS_BERASE_OFF 3 /* 3-4: Block/Sector Erase Size */ |
| 98 | #define HSFS_BERASE (0x3 << HSFS_BERASE_OFF) |
| 99 | #define HSFS_SCIP_OFF 5 /* 5: SPI Cycle In Progress */ |
| 100 | #define HSFS_SCIP (0x1 << HSFS_SCIP_OFF) |
| 101 | /* 6-12: reserved */ |
| 102 | #define HSFS_FDOPSS_OFF 13 /* 13: Flash Descriptor Override Pin-Strap Status */ |
| 103 | #define HSFS_FDOPSS (0x1 << HSFS_FDOPSS_OFF) |
| 104 | #define HSFS_FDV_OFF 14 /* 14: Flash Descriptor Valid */ |
| 105 | #define HSFS_FDV (0x1 << HSFS_FDV_OFF) |
| 106 | #define HSFS_FLOCKDN_OFF 15 /* 15: Flash Configuration Lock-Down */ |
| 107 | #define HSFS_FLOCKDN (0x1 << HSFS_FLOCKDN_OFF) |
| 108 | |
| 109 | #define ICH9_REG_HSFC 0x06 /* 16 Bits Hardware Sequencing Flash Control */ |
| 110 | #define HSFC_FGO_OFF 0 /* 0: Flash Cycle Go */ |
| 111 | #define HSFC_FGO (0x1 << HSFC_FGO_OFF) |
| 112 | #define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ |
| 113 | #define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) |
| 114 | /* 3-7: reserved */ |
| 115 | #define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ |
| 116 | #define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) |
| 117 | /* 14: reserved */ |
| 118 | #define HSFC_SME_OFF 15 /* 15: SPI SMI# Enable */ |
| 119 | #define HSFC_SME (0x1 << HSFC_SME_OFF) |
| 120 | |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 121 | #define ICH9_REG_FADDR 0x08 /* 32 Bits */ |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 122 | #define ICH9_FADDR_FLA 0x01ffffff |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 123 | #define ICH9_REG_FDATA0 0x10 /* 64 Bytes */ |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 124 | |
Stefan Tauner | 29c8083 | 2011-06-12 08:14:10 +0000 | [diff] [blame] | 125 | #define ICH9_REG_FRAP 0x50 /* 32 Bytes Flash Region Access Permissions */ |
| 126 | #define ICH9_REG_FREG0 0x54 /* 32 Bytes Flash Region 0 */ |
| 127 | |
| 128 | #define ICH9_REG_PR0 0x74 /* 32 Bytes Protected Range 0 */ |
Stefan Tauner | bf69aaa | 2011-09-17 21:21:48 +0000 | [diff] [blame] | 129 | #define PR_WP_OFF 31 /* 31: write protection enable */ |
| 130 | #define PR_RP_OFF 15 /* 15: read protection enable */ |
Stefan Tauner | 29c8083 | 2011-06-12 08:14:10 +0000 | [diff] [blame] | 131 | |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 132 | #define ICH9_REG_SSFS 0x90 /* 08 Bits */ |
Stefan Tauner | 0c1ec45 | 2011-06-11 09:53:09 +0000 | [diff] [blame] | 133 | #define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */ |
| 134 | #define SSFS_SCIP (0x1 << SSFS_SCIP_OFF) |
| 135 | #define SSFS_FDONE_OFF 2 /* Cycle Done Status */ |
| 136 | #define SSFS_FDONE (0x1 << SSFS_FDONE_OFF) |
| 137 | #define SSFS_FCERR_OFF 3 /* Flash Cycle Error */ |
| 138 | #define SSFS_FCERR (0x1 << SSFS_FCERR_OFF) |
| 139 | #define SSFS_AEL_OFF 4 /* Access Error Log */ |
| 140 | #define SSFS_AEL (0x1 << SSFS_AEL_OFF) |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 141 | /* The following bits are reserved in SSFS: 1,5-7. */ |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 142 | #define SSFS_RESERVED_MASK 0x000000e2 |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 143 | |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 144 | #define ICH9_REG_SSFC 0x91 /* 24 Bits */ |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 145 | /* We combine SSFS and SSFC to one 32-bit word, |
Stefan Tauner | 0c1ec45 | 2011-06-11 09:53:09 +0000 | [diff] [blame] | 146 | * therefore SSFC bits are off by 8. */ |
| 147 | /* 0: reserved */ |
| 148 | #define SSFC_SCGO_OFF (1 + 8) /* 1: SPI Cycle Go */ |
| 149 | #define SSFC_SCGO (0x1 << SSFC_SCGO_OFF) |
| 150 | #define SSFC_ACS_OFF (2 + 8) /* 2: Atomic Cycle Sequence */ |
| 151 | #define SSFC_ACS (0x1 << SSFC_ACS_OFF) |
| 152 | #define SSFC_SPOP_OFF (3 + 8) /* 3: Sequence Prefix Opcode Pointer */ |
| 153 | #define SSFC_SPOP (0x1 << SSFC_SPOP_OFF) |
| 154 | #define SSFC_COP_OFF (4 + 8) /* 4-6: Cycle Opcode Pointer */ |
| 155 | #define SSFC_COP (0x7 << SSFC_COP_OFF) |
| 156 | /* 7: reserved */ |
| 157 | #define SSFC_DBC_OFF (8 + 8) /* 8-13: Data Byte Count */ |
| 158 | #define SSFC_DBC (0x3f << SSFC_DBC_OFF) |
| 159 | #define SSFC_DS_OFF (14 + 8) /* 14: Data Cycle */ |
| 160 | #define SSFC_DS (0x1 << SSFC_DS_OFF) |
| 161 | #define SSFC_SME_OFF (15 + 8) /* 15: SPI SMI# Enable */ |
| 162 | #define SSFC_SME (0x1 << SSFC_SME_OFF) |
| 163 | #define SSFC_SCF_OFF (16 + 8) /* 16-18: SPI Cycle Frequency */ |
| 164 | #define SSFC_SCF (0x7 << SSFC_SCF_OFF) |
| 165 | #define SSFC_SCF_20MHZ 0x00000000 |
| 166 | #define SSFC_SCF_33MHZ 0x01000000 |
| 167 | /* 19-23: reserved */ |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 168 | #define SSFC_RESERVED_MASK 0xf8008100 |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 169 | |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 170 | #define ICH9_REG_PREOP 0x94 /* 16 Bits */ |
| 171 | #define ICH9_REG_OPTYPE 0x96 /* 16 Bits */ |
| 172 | #define ICH9_REG_OPMENU 0x98 /* 64 Bits */ |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 173 | |
Stefan Tauner | 29c8083 | 2011-06-12 08:14:10 +0000 | [diff] [blame] | 174 | #define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */ |
| 175 | #define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */ |
| 176 | |
Stefan Tauner | 1e14639 | 2011-09-15 23:52:55 +0000 | [diff] [blame] | 177 | #define ICH8_REG_VSCC 0xC1 /* 32 Bits Vendor Specific Component Capabilities */ |
| 178 | #define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */ |
| 179 | #define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */ |
| 180 | /* The individual fields of the VSCC registers are defined in the file |
| 181 | * ich_descriptors.h. The reason is that the same layout is also used in the |
| 182 | * flash descriptor to define the properties of the different flash chips |
| 183 | * supported. The BIOS (or the ME?) is responsible to populate the ICH registers |
| 184 | * with the information from the descriptor on startup depending on the actual |
| 185 | * chip(s) detected. */ |
| 186 | |
Stefan Tauner | bd649e4 | 2011-07-01 00:39:16 +0000 | [diff] [blame] | 187 | #define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */ |
| 188 | #define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */ |
| 189 | #define FPB_FPBA (0x1FFF << FPB_FPBA_OFF) |
| 190 | |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 191 | // ICH9R SPI commands |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 192 | #define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0 |
| 193 | #define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1 |
| 194 | #define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2 |
| 195 | #define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3 |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 196 | |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 197 | // ICH7 registers |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 198 | #define ICH7_REG_SPIS 0x00 /* 16 Bits */ |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 199 | #define SPIS_SCIP 0x0001 |
| 200 | #define SPIS_GRANT 0x0002 |
| 201 | #define SPIS_CDS 0x0004 |
| 202 | #define SPIS_FCERR 0x0008 |
| 203 | #define SPIS_RESERVED_MASK 0x7ff0 |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 204 | |
Rudolf Marek | 3fdbccf | 2008-06-30 21:38:30 +0000 | [diff] [blame] | 205 | /* VIA SPI is compatible with ICH7, but maxdata |
| 206 | to transfer is 16 bytes. |
| 207 | |
| 208 | DATA byte count on ICH7 is 8:13, on VIA 8:11 |
| 209 | |
| 210 | bit 12 is port select CS0 CS1 |
| 211 | bit 13 is FAST READ enable |
| 212 | bit 7 is used with fast read and one shot controls CS de-assert? |
| 213 | */ |
| 214 | |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 215 | #define ICH7_REG_SPIC 0x02 /* 16 Bits */ |
| 216 | #define SPIC_SCGO 0x0002 |
| 217 | #define SPIC_ACS 0x0004 |
| 218 | #define SPIC_SPOP 0x0008 |
| 219 | #define SPIC_DS 0x4000 |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 220 | |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 221 | #define ICH7_REG_SPIA 0x04 /* 32 Bits */ |
| 222 | #define ICH7_REG_SPID0 0x08 /* 64 Bytes */ |
| 223 | #define ICH7_REG_PREOP 0x54 /* 16 Bits */ |
| 224 | #define ICH7_REG_OPTYPE 0x56 /* 16 Bits */ |
| 225 | #define ICH7_REG_OPMENU 0x58 /* 64 Bits */ |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 226 | |
Nico Huber | 7590d1a | 2016-05-03 13:38:28 +0200 | [diff] [blame] | 227 | enum ich_access_protection { |
| 228 | NO_PROT = 0, |
| 229 | READ_PROT = 1, |
| 230 | WRITE_PROT = 2, |
| 231 | LOCKED = 3, |
| 232 | }; |
| 233 | |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 234 | /* ICH SPI configuration lock-down. May be set during chipset enabling. */ |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 235 | static int ichspi_lock = 0; |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 236 | |
Stefan Tauner | a8d838d | 2011-11-06 23:51:09 +0000 | [diff] [blame] | 237 | static enum ich_chipset ich_generation = CHIPSET_ICH_UNKNOWN; |
Nico Huber | ed098d6 | 2017-04-21 23:47:08 +0200 | [diff] [blame] | 238 | static uint32_t ichspi_bbar; |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 239 | |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 240 | static void *ich_spibar = NULL; |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 241 | |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 242 | typedef struct _OPCODE { |
| 243 | uint8_t opcode; //This commands spi opcode |
| 244 | uint8_t spi_type; //This commands spi type |
| 245 | uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1 |
| 246 | } OPCODE; |
| 247 | |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 248 | /* Suggested opcode definition: |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 249 | * Preop 1: Write Enable |
| 250 | * Preop 2: Write Status register enable |
| 251 | * |
| 252 | * OP 0: Write address |
| 253 | * OP 1: Read Address |
| 254 | * OP 2: ERASE block |
| 255 | * OP 3: Read Status register |
| 256 | * OP 4: Read ID |
| 257 | * OP 5: Write Status register |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 258 | * OP 6: chip private (read JEDEC id) |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 259 | * OP 7: Chip erase |
| 260 | */ |
| 261 | typedef struct _OPCODES { |
| 262 | uint8_t preop[2]; |
| 263 | OPCODE opcode[8]; |
| 264 | } OPCODES; |
| 265 | |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 266 | static OPCODES *curopcodes = NULL; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 267 | |
| 268 | /* HW access functions */ |
Uwe Hermann | 09e04f7 | 2009-05-16 22:36:00 +0000 | [diff] [blame] | 269 | static uint32_t REGREAD32(int X) |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 270 | { |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 271 | return mmio_readl(ich_spibar + X); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 272 | } |
| 273 | |
Uwe Hermann | 09e04f7 | 2009-05-16 22:36:00 +0000 | [diff] [blame] | 274 | static uint16_t REGREAD16(int X) |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 275 | { |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 276 | return mmio_readw(ich_spibar + X); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 277 | } |
| 278 | |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 279 | static uint16_t REGREAD8(int X) |
| 280 | { |
| 281 | return mmio_readb(ich_spibar + X); |
| 282 | } |
| 283 | |
Stefan Tauner | ccd92a1 | 2011-07-01 00:39:01 +0000 | [diff] [blame] | 284 | #define REGWRITE32(off, val) mmio_writel(val, ich_spibar+(off)) |
| 285 | #define REGWRITE16(off, val) mmio_writew(val, ich_spibar+(off)) |
| 286 | #define REGWRITE8(off, val) mmio_writeb(val, ich_spibar+(off)) |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 287 | |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 288 | /* Common SPI functions */ |
Uwe Hermann | 09e04f7 | 2009-05-16 22:36:00 +0000 | [diff] [blame] | 289 | static int find_opcode(OPCODES *op, uint8_t opcode); |
| 290 | static int find_preop(OPCODES *op, uint8_t preop); |
FENG yu ning | f041e9b | 2008-12-15 02:32:11 +0000 | [diff] [blame] | 291 | static int generate_opcodes(OPCODES * op); |
Carl-Daniel Hailfinger | 54ce73a | 2011-05-03 21:49:41 +0000 | [diff] [blame] | 292 | static int program_opcodes(OPCODES *op, int enable_undo); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 293 | static int run_opcode(const struct flashctx *flash, OPCODE op, uint32_t offset, |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 294 | uint8_t datalength, uint8_t * data); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 295 | |
FENG yu ning | f041e9b | 2008-12-15 02:32:11 +0000 | [diff] [blame] | 296 | /* for pairing opcodes with their required preop */ |
| 297 | struct preop_opcode_pair { |
| 298 | uint8_t preop; |
| 299 | uint8_t opcode; |
| 300 | }; |
| 301 | |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 302 | /* List of opcodes which need preopcodes and matching preopcodes. Unused. */ |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 303 | const struct preop_opcode_pair pops[] = { |
FENG yu ning | f041e9b | 2008-12-15 02:32:11 +0000 | [diff] [blame] | 304 | {JEDEC_WREN, JEDEC_BYTE_PROGRAM}, |
| 305 | {JEDEC_WREN, JEDEC_SE}, /* sector erase */ |
| 306 | {JEDEC_WREN, JEDEC_BE_52}, /* block erase */ |
| 307 | {JEDEC_WREN, JEDEC_BE_D8}, /* block erase */ |
| 308 | {JEDEC_WREN, JEDEC_CE_60}, /* chip erase */ |
| 309 | {JEDEC_WREN, JEDEC_CE_C7}, /* chip erase */ |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 310 | /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */ |
| 311 | {JEDEC_WREN, JEDEC_WRSR}, |
FENG yu ning | f041e9b | 2008-12-15 02:32:11 +0000 | [diff] [blame] | 312 | {JEDEC_EWSR, JEDEC_WRSR}, |
| 313 | {0,} |
| 314 | }; |
| 315 | |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 316 | /* Reasonable default configuration. Needs ad-hoc modifications if we |
| 317 | * encounter unlisted opcodes. Fun. |
| 318 | */ |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 319 | static OPCODES O_ST_M25P = { |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 320 | { |
| 321 | JEDEC_WREN, |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 322 | JEDEC_EWSR, |
| 323 | }, |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 324 | { |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 325 | {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 326 | {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data |
David Hendricks | 15f539c | 2010-08-26 21:27:17 -0700 | [diff] [blame] | 327 | {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 328 | {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg |
Carl-Daniel Hailfinger | 15aa7c6 | 2009-05-26 21:25:08 +0000 | [diff] [blame] | 329 | {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 330 | {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 331 | {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 332 | {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase |
| 333 | } |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 334 | }; |
| 335 | |
Helge Wagner | 738e252 | 2010-10-05 22:06:05 +0000 | [diff] [blame] | 336 | /* List of opcodes with their corresponding spi_type |
| 337 | * It is used to reprogram the chipset OPCODE table on-the-fly if an opcode |
| 338 | * is needed which is currently not in the chipset OPCODE table |
| 339 | */ |
| 340 | static OPCODE POSSIBLE_OPCODES[] = { |
| 341 | {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte |
| 342 | {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data |
| 343 | {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector |
| 344 | {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg |
| 345 | {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature |
| 346 | {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register |
| 347 | {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID |
| 348 | {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase |
| 349 | {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Sector erase |
| 350 | {JEDEC_BE_52, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Block erase |
| 351 | {JEDEC_AAI_WORD_PROGRAM, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Auto Address Increment |
| 352 | }; |
| 353 | |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 354 | static OPCODES O_EXISTING = {}; |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 355 | |
Stefan Tauner | 2a8b262 | 2011-06-11 09:53:16 +0000 | [diff] [blame] | 356 | /* pretty printing functions */ |
Stefan Tauner | 8b391b8 | 2011-08-09 01:49:34 +0000 | [diff] [blame] | 357 | static void prettyprint_opcodes(OPCODES *ops) |
Stefan Tauner | 2a8b262 | 2011-06-11 09:53:16 +0000 | [diff] [blame] | 358 | { |
Stefan Tauner | 84e1dde | 2011-09-17 19:53:11 +0000 | [diff] [blame] | 359 | OPCODE oc; |
| 360 | const char *t; |
| 361 | const char *a; |
| 362 | uint8_t i; |
| 363 | static const char *const spi_type[4] = { |
| 364 | "read w/o addr", |
| 365 | "write w/o addr", |
| 366 | "read w/ addr", |
| 367 | "write w/ addr" |
| 368 | }; |
| 369 | static const char *const atomic_type[3] = { |
| 370 | "none", |
| 371 | " 0 ", |
| 372 | " 1 " |
| 373 | }; |
| 374 | |
| 375 | if (ops == NULL) |
Stefan Tauner | 2a8b262 | 2011-06-11 09:53:16 +0000 | [diff] [blame] | 376 | return; |
| 377 | |
Stefan Tauner | 84e1dde | 2011-09-17 19:53:11 +0000 | [diff] [blame] | 378 | msg_pdbg2(" OP Type Pre-OP\n"); |
Stefan Tauner | 2a8b262 | 2011-06-11 09:53:16 +0000 | [diff] [blame] | 379 | for (i = 0; i < 8; i++) { |
| 380 | oc = ops->opcode[i]; |
Stefan Tauner | 84e1dde | 2011-09-17 19:53:11 +0000 | [diff] [blame] | 381 | t = (oc.spi_type > 3) ? "invalid" : spi_type[oc.spi_type]; |
| 382 | a = (oc.atomic > 2) ? "invalid" : atomic_type[oc.atomic]; |
| 383 | msg_pdbg2("op[%d]: 0x%02x, %s, %s\n", i, oc.opcode, t, a); |
Stefan Tauner | 2a8b262 | 2011-06-11 09:53:16 +0000 | [diff] [blame] | 384 | } |
Stefan Tauner | 84e1dde | 2011-09-17 19:53:11 +0000 | [diff] [blame] | 385 | msg_pdbg2("Pre-OP 0: 0x%02x, Pre-OP 1: 0x%02x\n", ops->preop[0], |
| 386 | ops->preop[1]); |
Stefan Tauner | 2a8b262 | 2011-06-11 09:53:16 +0000 | [diff] [blame] | 387 | } |
| 388 | |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 389 | #define _pprint_reg(bit, mask, off, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & mask) >> off) |
| 390 | #define pprint_reg(reg, bit, val, sep) _pprint_reg(bit, reg##_##bit, reg##_##bit##_OFF, val, sep) |
Stefan Tauner | 2a8b262 | 2011-06-11 09:53:16 +0000 | [diff] [blame] | 391 | |
Stefan Tauner | 5520694 | 2011-06-11 09:53:22 +0000 | [diff] [blame] | 392 | static void prettyprint_ich9_reg_hsfs(uint16_t reg_val) |
| 393 | { |
| 394 | msg_pdbg("HSFS: "); |
| 395 | pprint_reg(HSFS, FDONE, reg_val, ", "); |
| 396 | pprint_reg(HSFS, FCERR, reg_val, ", "); |
| 397 | pprint_reg(HSFS, AEL, reg_val, ", "); |
Nico Huber | 2a5dfaf | 2019-07-04 16:01:51 +0200 | [diff] [blame] | 398 | switch (ich_generation) { |
| 399 | case CHIPSET_100_SERIES_SUNRISE_POINT: |
| 400 | case CHIPSET_C620_SERIES_LEWISBURG: |
| 401 | case CHIPSET_300_SERIES_CANNON_POINT: |
| 402 | break; |
| 403 | default: |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 404 | pprint_reg(HSFS, BERASE, reg_val, ", "); |
Nico Huber | 2a5dfaf | 2019-07-04 16:01:51 +0200 | [diff] [blame] | 405 | break; |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 406 | } |
Stefan Tauner | 5520694 | 2011-06-11 09:53:22 +0000 | [diff] [blame] | 407 | pprint_reg(HSFS, SCIP, reg_val, ", "); |
Nico Huber | 2a5dfaf | 2019-07-04 16:01:51 +0200 | [diff] [blame] | 408 | switch (ich_generation) { |
| 409 | case CHIPSET_100_SERIES_SUNRISE_POINT: |
| 410 | case CHIPSET_C620_SERIES_LEWISBURG: |
| 411 | case CHIPSET_300_SERIES_CANNON_POINT: |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 412 | pprint_reg(HSFS, PRR34_LOCKDN, reg_val, ", "); |
| 413 | pprint_reg(HSFS, WRSDIS, reg_val, ", "); |
Nico Huber | 2a5dfaf | 2019-07-04 16:01:51 +0200 | [diff] [blame] | 414 | break; |
| 415 | default: |
| 416 | break; |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 417 | } |
Stefan Tauner | 5520694 | 2011-06-11 09:53:22 +0000 | [diff] [blame] | 418 | pprint_reg(HSFS, FDOPSS, reg_val, ", "); |
| 419 | pprint_reg(HSFS, FDV, reg_val, ", "); |
| 420 | pprint_reg(HSFS, FLOCKDN, reg_val, "\n"); |
| 421 | } |
| 422 | |
| 423 | static void prettyprint_ich9_reg_hsfc(uint16_t reg_val) |
| 424 | { |
| 425 | msg_pdbg("HSFC: "); |
| 426 | pprint_reg(HSFC, FGO, reg_val, ", "); |
Nico Huber | 2a5dfaf | 2019-07-04 16:01:51 +0200 | [diff] [blame] | 427 | switch (ich_generation) { |
| 428 | case CHIPSET_100_SERIES_SUNRISE_POINT: |
| 429 | case CHIPSET_C620_SERIES_LEWISBURG: |
| 430 | case CHIPSET_300_SERIES_CANNON_POINT: |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 431 | _pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", "); |
| 432 | pprint_reg(HSFC, WET, reg_val, ", "); |
Nico Huber | 2a5dfaf | 2019-07-04 16:01:51 +0200 | [diff] [blame] | 433 | break; |
| 434 | default: |
| 435 | pprint_reg(HSFC, FCYCLE, reg_val, ", "); |
| 436 | break; |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 437 | } |
Stefan Tauner | 5520694 | 2011-06-11 09:53:22 +0000 | [diff] [blame] | 438 | pprint_reg(HSFC, FDBC, reg_val, ", "); |
| 439 | pprint_reg(HSFC, SME, reg_val, "\n"); |
| 440 | } |
| 441 | |
Stefan Tauner | 2a8b262 | 2011-06-11 09:53:16 +0000 | [diff] [blame] | 442 | static void prettyprint_ich9_reg_ssfs(uint32_t reg_val) |
| 443 | { |
| 444 | msg_pdbg("SSFS: "); |
| 445 | pprint_reg(SSFS, SCIP, reg_val, ", "); |
| 446 | pprint_reg(SSFS, FDONE, reg_val, ", "); |
| 447 | pprint_reg(SSFS, FCERR, reg_val, ", "); |
| 448 | pprint_reg(SSFS, AEL, reg_val, "\n"); |
| 449 | } |
| 450 | |
| 451 | static void prettyprint_ich9_reg_ssfc(uint32_t reg_val) |
| 452 | { |
| 453 | msg_pdbg("SSFC: "); |
| 454 | pprint_reg(SSFC, SCGO, reg_val, ", "); |
| 455 | pprint_reg(SSFC, ACS, reg_val, ", "); |
| 456 | pprint_reg(SSFC, SPOP, reg_val, ", "); |
| 457 | pprint_reg(SSFC, COP, reg_val, ", "); |
| 458 | pprint_reg(SSFC, DBC, reg_val, ", "); |
| 459 | pprint_reg(SSFC, SME, reg_val, ", "); |
| 460 | pprint_reg(SSFC, SCF, reg_val, "\n"); |
| 461 | } |
| 462 | |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 463 | static void prettyprint_pch100_reg_dlock(const uint32_t reg_val) |
| 464 | { |
| 465 | msg_pdbg("DLOCK: "); |
| 466 | pprint_reg(DLOCK, BMWAG_LOCKDN, reg_val, ", "); |
| 467 | pprint_reg(DLOCK, BMRAG_LOCKDN, reg_val, ", "); |
| 468 | pprint_reg(DLOCK, SBMWAG_LOCKDN, reg_val, ", "); |
| 469 | pprint_reg(DLOCK, SBMRAG_LOCKDN, reg_val, ",\n "); |
| 470 | pprint_reg(DLOCK, PR0_LOCKDN, reg_val, ", "); |
| 471 | pprint_reg(DLOCK, PR1_LOCKDN, reg_val, ", "); |
| 472 | pprint_reg(DLOCK, PR2_LOCKDN, reg_val, ", "); |
| 473 | pprint_reg(DLOCK, PR3_LOCKDN, reg_val, ", "); |
| 474 | pprint_reg(DLOCK, PR4_LOCKDN, reg_val, ",\n "); |
| 475 | pprint_reg(DLOCK, SSEQ_LOCKDN, reg_val, "\n"); |
| 476 | } |
| 477 | |
| 478 | static struct { |
| 479 | size_t reg_ssfsc; |
| 480 | size_t reg_preop; |
| 481 | size_t reg_optype; |
| 482 | size_t reg_opmenu; |
| 483 | } swseq_data; |
| 484 | |
Helge Wagner | 738e252 | 2010-10-05 22:06:05 +0000 | [diff] [blame] | 485 | static uint8_t lookup_spi_type(uint8_t opcode) |
| 486 | { |
Nico Huber | 519be66 | 2018-12-23 20:03:35 +0100 | [diff] [blame] | 487 | unsigned int a; |
Helge Wagner | 738e252 | 2010-10-05 22:06:05 +0000 | [diff] [blame] | 488 | |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 489 | for (a = 0; a < ARRAY_SIZE(POSSIBLE_OPCODES); a++) { |
Helge Wagner | 738e252 | 2010-10-05 22:06:05 +0000 | [diff] [blame] | 490 | if (POSSIBLE_OPCODES[a].opcode == opcode) |
| 491 | return POSSIBLE_OPCODES[a].spi_type; |
| 492 | } |
| 493 | |
| 494 | return 0xFF; |
| 495 | } |
| 496 | |
| 497 | static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt) |
| 498 | { |
| 499 | uint8_t spi_type; |
| 500 | |
| 501 | spi_type = lookup_spi_type(opcode); |
| 502 | if (spi_type > 3) { |
| 503 | /* Try to guess spi type from read/write sizes. |
| 504 | * The following valid writecnt/readcnt combinations exist: |
| 505 | * writecnt = 4, readcnt >= 0 |
| 506 | * writecnt = 1, readcnt >= 0 |
| 507 | * writecnt >= 4, readcnt = 0 |
| 508 | * writecnt >= 1, readcnt = 0 |
| 509 | * writecnt >= 1 is guaranteed for all commands. |
| 510 | */ |
| 511 | if (readcnt == 0) |
| 512 | /* if readcnt=0 and writecount >= 4, we don't know if it is WRITE_NO_ADDRESS |
| 513 | * or WRITE_WITH_ADDRESS. But if we use WRITE_NO_ADDRESS and the first 3 data |
| 514 | * bytes are actual the address, they go to the bus anyhow |
| 515 | */ |
| 516 | spi_type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; |
| 517 | else if (writecnt == 1) // and readcnt is > 0 |
| 518 | spi_type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; |
| 519 | else if (writecnt == 4) // and readcnt is > 0 |
| 520 | spi_type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; |
Stefan Tauner | dc704ed | 2012-05-06 15:11:26 +0000 | [diff] [blame] | 521 | else // we have an invalid case |
| 522 | return SPI_INVALID_LENGTH; |
Helge Wagner | 738e252 | 2010-10-05 22:06:05 +0000 | [diff] [blame] | 523 | } |
Stefan Tauner | dc704ed | 2012-05-06 15:11:26 +0000 | [diff] [blame] | 524 | int oppos = 2; // use original JEDEC_BE_D8 offset |
| 525 | curopcodes->opcode[oppos].opcode = opcode; |
| 526 | curopcodes->opcode[oppos].spi_type = spi_type; |
| 527 | program_opcodes(curopcodes, 0); |
| 528 | oppos = find_opcode(curopcodes, opcode); |
Stefan Tauner | d94d25d | 2012-07-28 03:17:15 +0000 | [diff] [blame] | 529 | msg_pdbg2("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos); |
Stefan Tauner | dc704ed | 2012-05-06 15:11:26 +0000 | [diff] [blame] | 530 | return oppos; |
Helge Wagner | 738e252 | 2010-10-05 22:06:05 +0000 | [diff] [blame] | 531 | } |
| 532 | |
Uwe Hermann | 09e04f7 | 2009-05-16 22:36:00 +0000 | [diff] [blame] | 533 | static int find_opcode(OPCODES *op, uint8_t opcode) |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 534 | { |
| 535 | int a; |
| 536 | |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 537 | if (op == NULL) { |
| 538 | msg_perr("\n%s: null OPCODES pointer!\n", __func__); |
| 539 | return -1; |
| 540 | } |
| 541 | |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 542 | for (a = 0; a < 8; a++) { |
| 543 | if (op->opcode[a].opcode == opcode) |
| 544 | return a; |
| 545 | } |
| 546 | |
| 547 | return -1; |
| 548 | } |
| 549 | |
Uwe Hermann | 09e04f7 | 2009-05-16 22:36:00 +0000 | [diff] [blame] | 550 | static int find_preop(OPCODES *op, uint8_t preop) |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 551 | { |
| 552 | int a; |
| 553 | |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 554 | if (op == NULL) { |
| 555 | msg_perr("\n%s: null OPCODES pointer!\n", __func__); |
| 556 | return -1; |
| 557 | } |
| 558 | |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 559 | for (a = 0; a < 2; a++) { |
| 560 | if (op->preop[a] == preop) |
| 561 | return a; |
| 562 | } |
| 563 | |
| 564 | return -1; |
| 565 | } |
| 566 | |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 567 | /* Create a struct OPCODES based on what we find in the locked down chipset. */ |
FENG yu ning | f041e9b | 2008-12-15 02:32:11 +0000 | [diff] [blame] | 568 | static int generate_opcodes(OPCODES * op) |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 569 | { |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 570 | int a; |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 571 | uint16_t preop, optype; |
| 572 | uint32_t opmenu[2]; |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 573 | |
| 574 | if (op == NULL) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 575 | msg_perr("\n%s: null OPCODES pointer!\n", __func__); |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 576 | return -1; |
| 577 | } |
| 578 | |
Stefan Tauner | a8d838d | 2011-11-06 23:51:09 +0000 | [diff] [blame] | 579 | switch (ich_generation) { |
| 580 | case CHIPSET_ICH7: |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 581 | case CHIPSET_TUNNEL_CREEK: |
| 582 | case CHIPSET_CENTERTON: |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 583 | preop = REGREAD16(ICH7_REG_PREOP); |
| 584 | optype = REGREAD16(ICH7_REG_OPTYPE); |
| 585 | opmenu[0] = REGREAD32(ICH7_REG_OPMENU); |
| 586 | opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4); |
| 587 | break; |
Stefan Tauner | a8d838d | 2011-11-06 23:51:09 +0000 | [diff] [blame] | 588 | case CHIPSET_ICH8: |
| 589 | default: /* Future version might behave the same */ |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 590 | preop = REGREAD16(swseq_data.reg_preop); |
| 591 | optype = REGREAD16(swseq_data.reg_optype); |
| 592 | opmenu[0] = REGREAD32(swseq_data.reg_opmenu); |
| 593 | opmenu[1] = REGREAD32(swseq_data.reg_opmenu + 4); |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 594 | break; |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 595 | } |
| 596 | |
| 597 | op->preop[0] = (uint8_t) preop; |
| 598 | op->preop[1] = (uint8_t) (preop >> 8); |
| 599 | |
| 600 | for (a = 0; a < 8; a++) { |
| 601 | op->opcode[a].spi_type = (uint8_t) (optype & 0x3); |
| 602 | optype >>= 2; |
| 603 | } |
| 604 | |
| 605 | for (a = 0; a < 4; a++) { |
| 606 | op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff); |
| 607 | opmenu[0] >>= 8; |
| 608 | } |
| 609 | |
| 610 | for (a = 4; a < 8; a++) { |
| 611 | op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff); |
| 612 | opmenu[1] >>= 8; |
| 613 | } |
| 614 | |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 615 | /* No preopcodes used by default. */ |
| 616 | for (a = 0; a < 8; a++) |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 617 | op->opcode[a].atomic = 0; |
| 618 | |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 619 | return 0; |
| 620 | } |
| 621 | |
Carl-Daniel Hailfinger | 54ce73a | 2011-05-03 21:49:41 +0000 | [diff] [blame] | 622 | static int program_opcodes(OPCODES *op, int enable_undo) |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 623 | { |
| 624 | uint8_t a; |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 625 | uint16_t preop, optype; |
| 626 | uint32_t opmenu[2]; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 627 | |
| 628 | /* Program Prefix Opcodes */ |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 629 | /* 0:7 Prefix Opcode 1 */ |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 630 | preop = (op->preop[0]); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 631 | /* 8:16 Prefix Opcode 2 */ |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 632 | preop |= ((uint16_t) op->preop[1]) << 8; |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 633 | |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 634 | /* Program Opcode Types 0 - 7 */ |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 635 | optype = 0; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 636 | for (a = 0; a < 8; a++) { |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 637 | optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 638 | } |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 639 | |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 640 | /* Program Allowable Opcodes 0 - 3 */ |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 641 | opmenu[0] = 0; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 642 | for (a = 0; a < 4; a++) { |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 643 | opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 644 | } |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 645 | |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 646 | /* Program Allowable Opcodes 4 - 7 */ |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 647 | opmenu[1] = 0; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 648 | for (a = 4; a < 8; a++) { |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 649 | opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 650 | } |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 651 | |
Stefan Tauner | d94d25d | 2012-07-28 03:17:15 +0000 | [diff] [blame] | 652 | msg_pdbg2("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]); |
Stefan Tauner | a8d838d | 2011-11-06 23:51:09 +0000 | [diff] [blame] | 653 | switch (ich_generation) { |
| 654 | case CHIPSET_ICH7: |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 655 | case CHIPSET_TUNNEL_CREEK: |
| 656 | case CHIPSET_CENTERTON: |
Carl-Daniel Hailfinger | 54ce73a | 2011-05-03 21:49:41 +0000 | [diff] [blame] | 657 | /* Register undo only for enable_undo=1, i.e. first call. */ |
| 658 | if (enable_undo) { |
| 659 | rmmio_valw(ich_spibar + ICH7_REG_PREOP); |
| 660 | rmmio_valw(ich_spibar + ICH7_REG_OPTYPE); |
| 661 | rmmio_vall(ich_spibar + ICH7_REG_OPMENU); |
| 662 | rmmio_vall(ich_spibar + ICH7_REG_OPMENU + 4); |
| 663 | } |
| 664 | mmio_writew(preop, ich_spibar + ICH7_REG_PREOP); |
| 665 | mmio_writew(optype, ich_spibar + ICH7_REG_OPTYPE); |
| 666 | mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU); |
| 667 | mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 668 | break; |
Stefan Tauner | a8d838d | 2011-11-06 23:51:09 +0000 | [diff] [blame] | 669 | case CHIPSET_ICH8: |
| 670 | default: /* Future version might behave the same */ |
Carl-Daniel Hailfinger | 54ce73a | 2011-05-03 21:49:41 +0000 | [diff] [blame] | 671 | /* Register undo only for enable_undo=1, i.e. first call. */ |
| 672 | if (enable_undo) { |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 673 | rmmio_valw(ich_spibar + swseq_data.reg_preop); |
| 674 | rmmio_valw(ich_spibar + swseq_data.reg_optype); |
| 675 | rmmio_vall(ich_spibar + swseq_data.reg_opmenu); |
| 676 | rmmio_vall(ich_spibar + swseq_data.reg_opmenu + 4); |
Carl-Daniel Hailfinger | 54ce73a | 2011-05-03 21:49:41 +0000 | [diff] [blame] | 677 | } |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 678 | mmio_writew(preop, ich_spibar + swseq_data.reg_preop); |
| 679 | mmio_writew(optype, ich_spibar + swseq_data.reg_optype); |
| 680 | mmio_writel(opmenu[0], ich_spibar + swseq_data.reg_opmenu); |
| 681 | mmio_writel(opmenu[1], ich_spibar + swseq_data.reg_opmenu + 4); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 682 | break; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 683 | } |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 684 | |
| 685 | return 0; |
| 686 | } |
| 687 | |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 688 | /* |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 689 | * Returns -1 if at least one mandatory opcode is inaccessible, 0 otherwise. |
| 690 | * FIXME: this should also check for |
| 691 | * - at least one probing opcode (RDID (incl. AT25F variants?), REMS, RES?) |
| 692 | * - at least one erasing opcode (lots.) |
| 693 | * - at least one program opcode (BYTE_PROGRAM, AAI_WORD_PROGRAM, ...?) |
| 694 | * - necessary preops? (EWSR, WREN, ...?) |
| 695 | */ |
Richard Hughes | 93e1625 | 2018-12-19 11:54:47 +0000 | [diff] [blame] | 696 | static int ich_missing_opcodes(void) |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 697 | { |
| 698 | uint8_t ops[] = { |
| 699 | JEDEC_READ, |
| 700 | JEDEC_RDSR, |
| 701 | 0 |
| 702 | }; |
| 703 | int i = 0; |
| 704 | while (ops[i] != 0) { |
| 705 | msg_pspew("checking for opcode 0x%02x\n", ops[i]); |
| 706 | if (find_opcode(curopcodes, ops[i]) == -1) |
| 707 | return -1; |
| 708 | i++; |
| 709 | } |
| 710 | return 0; |
| 711 | } |
| 712 | |
| 713 | /* |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 714 | * Try to set BBAR (BIOS Base Address Register), but read back the value in case |
| 715 | * it didn't stick. |
| 716 | */ |
Stefan Tauner | a8d838d | 2011-11-06 23:51:09 +0000 | [diff] [blame] | 717 | static void ich_set_bbar(uint32_t min_addr) |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 718 | { |
Stefan Tauner | e27b2d4 | 2011-07-01 00:39:09 +0000 | [diff] [blame] | 719 | int bbar_off; |
Stefan Tauner | 7783f31 | 2011-09-17 21:21:42 +0000 | [diff] [blame] | 720 | switch (ich_generation) { |
Stefan Tauner | a8d838d | 2011-11-06 23:51:09 +0000 | [diff] [blame] | 721 | case CHIPSET_ICH7: |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 722 | case CHIPSET_TUNNEL_CREEK: |
| 723 | case CHIPSET_CENTERTON: |
Stefan Tauner | e27b2d4 | 2011-07-01 00:39:09 +0000 | [diff] [blame] | 724 | bbar_off = 0x50; |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 725 | break; |
Stefan Tauner | a8d838d | 2011-11-06 23:51:09 +0000 | [diff] [blame] | 726 | case CHIPSET_ICH8: |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 727 | case CHIPSET_BAYTRAIL: |
| 728 | msg_pdbg("BBAR offset is unknown!\n"); |
Stefan Tauner | 7783f31 | 2011-09-17 21:21:42 +0000 | [diff] [blame] | 729 | return; |
Stefan Tauner | a8d838d | 2011-11-06 23:51:09 +0000 | [diff] [blame] | 730 | case CHIPSET_ICH9: |
Stefan Tauner | 7783f31 | 2011-09-17 21:21:42 +0000 | [diff] [blame] | 731 | default: /* Future version might behave the same */ |
Stefan Tauner | e27b2d4 | 2011-07-01 00:39:09 +0000 | [diff] [blame] | 732 | bbar_off = ICH9_REG_BBAR; |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 733 | break; |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 734 | } |
Elyes HAOUAS | 124ef38 | 2018-03-27 12:15:09 +0200 | [diff] [blame] | 735 | |
Stefan Tauner | e27b2d4 | 2011-07-01 00:39:09 +0000 | [diff] [blame] | 736 | ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK; |
| 737 | if (ichspi_bbar) { |
| 738 | msg_pdbg("Reserved bits in BBAR not zero: 0x%08x\n", |
| 739 | ichspi_bbar); |
| 740 | } |
| 741 | min_addr &= BBAR_MASK; |
| 742 | ichspi_bbar |= min_addr; |
| 743 | rmmio_writel(ichspi_bbar, ich_spibar + bbar_off); |
| 744 | ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & BBAR_MASK; |
| 745 | |
| 746 | /* We don't have any option except complaining. And if the write |
| 747 | * failed, the restore will fail as well, so no problem there. |
| 748 | */ |
| 749 | if (ichspi_bbar != min_addr) |
Stefan Tauner | 7783f31 | 2011-09-17 21:21:42 +0000 | [diff] [blame] | 750 | msg_perr("Setting BBAR to 0x%08x failed! New value: 0x%08x.\n", |
| 751 | min_addr, ichspi_bbar); |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 752 | } |
| 753 | |
Stefan Tauner | 8b391b8 | 2011-08-09 01:49:34 +0000 | [diff] [blame] | 754 | /* Read len bytes from the fdata/spid register into the data array. |
| 755 | * |
Carl-Daniel Hailfinger | a5bcbce | 2014-07-19 22:03:29 +0000 | [diff] [blame] | 756 | * Note that using len > flash->mst->spi.max_data_read will return garbage or |
Stefan Tauner | 8b391b8 | 2011-08-09 01:49:34 +0000 | [diff] [blame] | 757 | * may even crash. |
| 758 | */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 759 | static void ich_read_data(uint8_t *data, int len, int reg0_off) |
Elyes HAOUAS | 124ef38 | 2018-03-27 12:15:09 +0200 | [diff] [blame] | 760 | { |
Stefan Tauner | 8b391b8 | 2011-08-09 01:49:34 +0000 | [diff] [blame] | 761 | int i; |
| 762 | uint32_t temp32 = 0; |
| 763 | |
| 764 | for (i = 0; i < len; i++) { |
| 765 | if ((i % 4) == 0) |
| 766 | temp32 = REGREAD32(reg0_off + i); |
| 767 | |
| 768 | data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; |
| 769 | } |
| 770 | } |
| 771 | |
| 772 | /* Fill len bytes from the data array into the fdata/spid registers. |
| 773 | * |
Carl-Daniel Hailfinger | a5bcbce | 2014-07-19 22:03:29 +0000 | [diff] [blame] | 774 | * Note that using len > flash->mst->spi.max_data_write will trash the registers |
Stefan Tauner | 8b391b8 | 2011-08-09 01:49:34 +0000 | [diff] [blame] | 775 | * following the data registers. |
| 776 | */ |
| 777 | static void ich_fill_data(const uint8_t *data, int len, int reg0_off) |
| 778 | { |
| 779 | uint32_t temp32 = 0; |
| 780 | int i; |
| 781 | |
| 782 | if (len <= 0) |
| 783 | return; |
| 784 | |
| 785 | for (i = 0; i < len; i++) { |
| 786 | if ((i % 4) == 0) |
| 787 | temp32 = 0; |
| 788 | |
| 789 | temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); |
| 790 | |
| 791 | if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ |
| 792 | REGWRITE32(reg0_off + (i - (i % 4)), temp32); |
| 793 | } |
| 794 | i--; |
| 795 | if ((i % 4) != 3) /* Write remaining data to regs. */ |
| 796 | REGWRITE32(reg0_off + (i - (i % 4)), temp32); |
| 797 | } |
| 798 | |
FENG yu ning | f041e9b | 2008-12-15 02:32:11 +0000 | [diff] [blame] | 799 | /* This function generates OPCODES from or programs OPCODES to ICH according to |
| 800 | * the chipset's SPI configuration lock. |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 801 | * |
FENG yu ning | f041e9b | 2008-12-15 02:32:11 +0000 | [diff] [blame] | 802 | * It should be called before ICH sends any spi command. |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 803 | */ |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 804 | static int ich_init_opcodes(void) |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 805 | { |
| 806 | int rc = 0; |
| 807 | OPCODES *curopcodes_done; |
| 808 | |
| 809 | if (curopcodes) |
| 810 | return 0; |
| 811 | |
| 812 | if (ichspi_lock) { |
Carl-Daniel Hailfinger | 80f3d05 | 2010-05-28 15:53:08 +0000 | [diff] [blame] | 813 | msg_pdbg("Reading OPCODES... "); |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 814 | curopcodes_done = &O_EXISTING; |
FENG yu ning | f041e9b | 2008-12-15 02:32:11 +0000 | [diff] [blame] | 815 | rc = generate_opcodes(curopcodes_done); |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 816 | } else { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 817 | msg_pdbg("Programming OPCODES... "); |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 818 | curopcodes_done = &O_ST_M25P; |
Carl-Daniel Hailfinger | 54ce73a | 2011-05-03 21:49:41 +0000 | [diff] [blame] | 819 | rc = program_opcodes(curopcodes_done, 1); |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 820 | } |
| 821 | |
| 822 | if (rc) { |
| 823 | curopcodes = NULL; |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 824 | msg_perr("failed\n"); |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 825 | return 1; |
| 826 | } else { |
| 827 | curopcodes = curopcodes_done; |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 828 | msg_pdbg("done\n"); |
Stefan Tauner | 8b391b8 | 2011-08-09 01:49:34 +0000 | [diff] [blame] | 829 | prettyprint_opcodes(curopcodes); |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 830 | return 0; |
| 831 | } |
| 832 | } |
| 833 | |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 834 | static int ich7_run_opcode(OPCODE op, uint32_t offset, |
Rudolf Marek | 3fdbccf | 2008-06-30 21:38:30 +0000 | [diff] [blame] | 835 | uint8_t datalength, uint8_t * data, int maxdata) |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 836 | { |
| 837 | int write_cmd = 0; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 838 | int timeout; |
Stefan Tauner | 8b391b8 | 2011-08-09 01:49:34 +0000 | [diff] [blame] | 839 | uint32_t temp32; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 840 | uint16_t temp16; |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 841 | uint64_t opmenu; |
| 842 | int opcode_index; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 843 | |
| 844 | /* Is it a write command? */ |
| 845 | if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) |
| 846 | || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) { |
| 847 | write_cmd = 1; |
| 848 | } |
| 849 | |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 850 | timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ |
| 851 | while ((REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) && --timeout) { |
| 852 | programmer_delay(10); |
| 853 | } |
| 854 | if (!timeout) { |
| 855 | msg_perr("Error: SCIP never cleared!\n"); |
| 856 | return 1; |
| 857 | } |
| 858 | |
Stefan Tauner | 10b3e22 | 2011-07-01 00:39:23 +0000 | [diff] [blame] | 859 | /* Program offset in flash into SPIA while preserving reserved bits. */ |
| 860 | temp32 = REGREAD32(ICH7_REG_SPIA) & ~0x00FFFFFF; |
| 861 | REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 862 | |
Stefan Tauner | 10b3e22 | 2011-07-01 00:39:23 +0000 | [diff] [blame] | 863 | /* Program data into SPID0 to N */ |
Stefan Tauner | 8b391b8 | 2011-08-09 01:49:34 +0000 | [diff] [blame] | 864 | if (write_cmd && (datalength != 0)) |
| 865 | ich_fill_data(data, datalength, ICH7_REG_SPID0); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 866 | |
| 867 | /* Assemble SPIS */ |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 868 | temp16 = REGREAD16(ICH7_REG_SPIS); |
| 869 | /* keep reserved bits */ |
| 870 | temp16 &= SPIS_RESERVED_MASK; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 871 | /* clear error status registers */ |
Stefan Tauner | 0c1ec45 | 2011-06-11 09:53:09 +0000 | [diff] [blame] | 872 | temp16 |= (SPIS_CDS | SPIS_FCERR); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 873 | REGWRITE16(ICH7_REG_SPIS, temp16); |
| 874 | |
| 875 | /* Assemble SPIC */ |
| 876 | temp16 = 0; |
| 877 | |
| 878 | if (datalength != 0) { |
| 879 | temp16 |= SPIC_DS; |
Rudolf Marek | 3fdbccf | 2008-06-30 21:38:30 +0000 | [diff] [blame] | 880 | temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 881 | } |
| 882 | |
| 883 | /* Select opcode */ |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 884 | opmenu = REGREAD32(ICH7_REG_OPMENU); |
| 885 | opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32; |
| 886 | |
Uwe Hermann | 7b2969b | 2009-04-15 10:52:49 +0000 | [diff] [blame] | 887 | for (opcode_index = 0; opcode_index < 8; opcode_index++) { |
| 888 | if ((opmenu & 0xff) == op.opcode) { |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 889 | break; |
| 890 | } |
| 891 | opmenu >>= 8; |
| 892 | } |
| 893 | if (opcode_index == 8) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 894 | msg_pdbg("Opcode %x not found.\n", op.opcode); |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 895 | return 1; |
| 896 | } |
| 897 | temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 898 | |
Michael Karcher | 136125a | 2011-04-29 22:11:36 +0000 | [diff] [blame] | 899 | timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ |
| 900 | /* Handle Atomic. Atomic commands include three steps: |
| 901 | - sending the preop (mainly EWSR or WREN) |
| 902 | - sending the main command |
| 903 | - waiting for the busy bit (WIP) to be cleared |
| 904 | This means the timeout must be sufficient for chip erase |
| 905 | of slow high-capacity chips. |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 906 | */ |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 907 | switch (op.atomic) { |
| 908 | case 2: |
| 909 | /* Select second preop. */ |
| 910 | temp16 |= SPIC_SPOP; |
Richard Hughes | db7482b | 2018-12-19 12:04:30 +0000 | [diff] [blame] | 911 | /* Fall through. */ |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 912 | case 1: |
| 913 | /* Atomic command (preop+op) */ |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 914 | temp16 |= SPIC_ACS; |
Michael Karcher | 136125a | 2011-04-29 22:11:36 +0000 | [diff] [blame] | 915 | timeout = 100 * 1000 * 60; /* 60 seconds */ |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 916 | break; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 917 | } |
| 918 | |
| 919 | /* Start */ |
| 920 | temp16 |= SPIC_SCGO; |
| 921 | |
| 922 | /* write it */ |
| 923 | REGWRITE16(ICH7_REG_SPIC, temp16); |
| 924 | |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 925 | /* Wait for Cycle Done Status or Flash Cycle Error. */ |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 926 | while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) && |
| 927 | --timeout) { |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 928 | programmer_delay(10); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 929 | } |
| 930 | if (!timeout) { |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 931 | msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n", |
| 932 | REGREAD16(ICH7_REG_SPIS)); |
| 933 | return 1; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 934 | } |
| 935 | |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 936 | /* FIXME: make sure we do not needlessly cause transaction errors. */ |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 937 | temp16 = REGREAD16(ICH7_REG_SPIS); |
| 938 | if (temp16 & SPIS_FCERR) { |
Stefan Tauner | 8ed2934 | 2011-04-29 23:53:09 +0000 | [diff] [blame] | 939 | msg_perr("Transaction error!\n"); |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 940 | /* keep reserved bits */ |
| 941 | temp16 &= SPIS_RESERVED_MASK; |
| 942 | REGWRITE16(ICH7_REG_SPIS, temp16 | SPIS_FCERR); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 943 | return 1; |
| 944 | } |
| 945 | |
Stefan Tauner | 8b391b8 | 2011-08-09 01:49:34 +0000 | [diff] [blame] | 946 | if ((!write_cmd) && (datalength != 0)) |
| 947 | ich_read_data(data, datalength, ICH7_REG_SPID0); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 948 | |
| 949 | return 0; |
| 950 | } |
| 951 | |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 952 | static int ich9_run_opcode(OPCODE op, uint32_t offset, |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 953 | uint8_t datalength, uint8_t * data) |
| 954 | { |
| 955 | int write_cmd = 0; |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 956 | int timeout; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 957 | uint32_t temp32; |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 958 | uint64_t opmenu; |
| 959 | int opcode_index; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 960 | |
| 961 | /* Is it a write command? */ |
| 962 | if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) |
| 963 | || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) { |
| 964 | write_cmd = 1; |
| 965 | } |
| 966 | |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 967 | timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 968 | while ((REGREAD8(swseq_data.reg_ssfsc) & SSFS_SCIP) && --timeout) { |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 969 | programmer_delay(10); |
| 970 | } |
| 971 | if (!timeout) { |
| 972 | msg_perr("Error: SCIP never cleared!\n"); |
| 973 | return 1; |
| 974 | } |
| 975 | |
Stefan Tauner | 10b3e22 | 2011-07-01 00:39:23 +0000 | [diff] [blame] | 976 | /* Program offset in flash into FADDR while preserve the reserved bits |
| 977 | * and clearing the 25. address bit which is only useable in hwseq. */ |
| 978 | temp32 = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF; |
| 979 | REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 980 | |
| 981 | /* Program data into FDATA0 to N */ |
Stefan Tauner | 8b391b8 | 2011-08-09 01:49:34 +0000 | [diff] [blame] | 982 | if (write_cmd && (datalength != 0)) |
| 983 | ich_fill_data(data, datalength, ICH9_REG_FDATA0); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 984 | |
| 985 | /* Assemble SSFS + SSFC */ |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 986 | temp32 = REGREAD32(swseq_data.reg_ssfsc); |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 987 | /* Keep reserved bits only */ |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 988 | temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; |
Stefan Tauner | 0c1ec45 | 2011-06-11 09:53:09 +0000 | [diff] [blame] | 989 | /* Clear cycle done and cycle error status registers */ |
| 990 | temp32 |= (SSFS_FDONE | SSFS_FCERR); |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 991 | REGWRITE32(swseq_data.reg_ssfsc, temp32); |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 992 | |
Uwe Hermann | 4e3d0b3 | 2010-03-25 23:18:41 +0000 | [diff] [blame] | 993 | /* Use 20 MHz */ |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 994 | temp32 |= SSFC_SCF_20MHZ; |
| 995 | |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 996 | /* Set data byte count (DBC) and data cycle bit (DS) */ |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 997 | if (datalength != 0) { |
| 998 | uint32_t datatemp; |
| 999 | temp32 |= SSFC_DS; |
Stefan Tauner | 0c1ec45 | 2011-06-11 09:53:09 +0000 | [diff] [blame] | 1000 | datatemp = ((((uint32_t)datalength - 1) << SSFC_DBC_OFF) & |
| 1001 | SSFC_DBC); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1002 | temp32 |= datatemp; |
| 1003 | } |
| 1004 | |
| 1005 | /* Select opcode */ |
Nico Huber | 8b2152d | 2017-08-31 13:18:49 +0200 | [diff] [blame] | 1006 | opmenu = REGREAD32(swseq_data.reg_opmenu); |
| 1007 | opmenu |= ((uint64_t)REGREAD32(swseq_data.reg_opmenu + 4)) << 32; |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 1008 | |
Uwe Hermann | 7b2969b | 2009-04-15 10:52:49 +0000 | [diff] [blame] | 1009 | for (opcode_index = 0; opcode_index < 8; opcode_index++) { |
| 1010 | if ((opmenu & 0xff) == op.opcode) { |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 1011 | break; |
| 1012 | } |
| 1013 | opmenu >>= 8; |
| 1014 | } |
| 1015 | if (opcode_index == 8) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1016 | msg_pdbg("Opcode %x not found.\n", op.opcode); |
Stefan Reinauer | 4311956 | 2008-11-02 19:51:50 +0000 | [diff] [blame] | 1017 | return 1; |
| 1018 | } |
| 1019 | temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1020 | |
Michael Karcher | 136125a | 2011-04-29 22:11:36 +0000 | [diff] [blame] | 1021 | timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */ |
| 1022 | /* Handle Atomic. Atomic commands include three steps: |
| 1023 | - sending the preop (mainly EWSR or WREN) |
| 1024 | - sending the main command |
| 1025 | - waiting for the busy bit (WIP) to be cleared |
| 1026 | This means the timeout must be sufficient for chip erase |
| 1027 | of slow high-capacity chips. |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 1028 | */ |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1029 | switch (op.atomic) { |
| 1030 | case 2: |
| 1031 | /* Select second preop. */ |
| 1032 | temp32 |= SSFC_SPOP; |
Richard Hughes | db7482b | 2018-12-19 12:04:30 +0000 | [diff] [blame] | 1033 | /* Fall through. */ |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1034 | case 1: |
| 1035 | /* Atomic command (preop+op) */ |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1036 | temp32 |= SSFC_ACS; |
Michael Karcher | 136125a | 2011-04-29 22:11:36 +0000 | [diff] [blame] | 1037 | timeout = 100 * 1000 * 60; /* 60 seconds */ |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1038 | break; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1039 | } |
| 1040 | |
| 1041 | /* Start */ |
| 1042 | temp32 |= SSFC_SCGO; |
| 1043 | |
| 1044 | /* write it */ |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1045 | REGWRITE32(swseq_data.reg_ssfsc, temp32); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1046 | |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 1047 | /* Wait for Cycle Done Status or Flash Cycle Error. */ |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1048 | while (((REGREAD32(swseq_data.reg_ssfsc) & (SSFS_FDONE | SSFS_FCERR)) == 0) && |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 1049 | --timeout) { |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 1050 | programmer_delay(10); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 1051 | } |
| 1052 | if (!timeout) { |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1053 | msg_perr("timeout, REG_SSFS=0x%08x\n", |
| 1054 | REGREAD32(swseq_data.reg_ssfsc)); |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 1055 | return 1; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1056 | } |
| 1057 | |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1058 | /* FIXME make sure we do not needlessly cause transaction errors. */ |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1059 | temp32 = REGREAD32(swseq_data.reg_ssfsc); |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 1060 | if (temp32 & SSFS_FCERR) { |
Stefan Tauner | 8ed2934 | 2011-04-29 23:53:09 +0000 | [diff] [blame] | 1061 | msg_perr("Transaction error!\n"); |
Stefan Tauner | 2a8b262 | 2011-06-11 09:53:16 +0000 | [diff] [blame] | 1062 | prettyprint_ich9_reg_ssfs(temp32); |
| 1063 | prettyprint_ich9_reg_ssfc(temp32); |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 1064 | /* keep reserved bits */ |
| 1065 | temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK; |
| 1066 | /* Clear the transaction error. */ |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1067 | REGWRITE32(swseq_data.reg_ssfsc, temp32 | SSFS_FCERR); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1068 | return 1; |
| 1069 | } |
| 1070 | |
Stefan Tauner | 8b391b8 | 2011-08-09 01:49:34 +0000 | [diff] [blame] | 1071 | if ((!write_cmd) && (datalength != 0)) |
| 1072 | ich_read_data(data, datalength, ICH9_REG_FDATA0); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1073 | |
| 1074 | return 0; |
| 1075 | } |
| 1076 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 1077 | static int run_opcode(const struct flashctx *flash, OPCODE op, uint32_t offset, |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 1078 | uint8_t datalength, uint8_t * data) |
| 1079 | { |
Stefan Tauner | b2d5f6a | 2011-06-11 19:44:31 +0000 | [diff] [blame] | 1080 | /* max_data_read == max_data_write for all Intel/VIA SPI masters */ |
Carl-Daniel Hailfinger | a5bcbce | 2014-07-19 22:03:29 +0000 | [diff] [blame] | 1081 | uint8_t maxlength = flash->mst->spi.max_data_read; |
Stefan Tauner | b2d5f6a | 2011-06-11 19:44:31 +0000 | [diff] [blame] | 1082 | |
Carl-Daniel Hailfinger | c40cff7 | 2011-12-20 00:19:29 +0000 | [diff] [blame] | 1083 | if (ich_generation == CHIPSET_ICH_UNKNOWN) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1084 | msg_perr("%s: unsupported chipset\n", __func__); |
Stefan Tauner | b2d5f6a | 2011-06-11 19:44:31 +0000 | [diff] [blame] | 1085 | return -1; |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 1086 | } |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 1087 | |
Stefan Tauner | b2d5f6a | 2011-06-11 19:44:31 +0000 | [diff] [blame] | 1088 | if (datalength > maxlength) { |
| 1089 | msg_perr("%s: Internal command size error for " |
| 1090 | "opcode 0x%02x, got datalength=%i, want <=%i\n", |
| 1091 | __func__, op.opcode, datalength, maxlength); |
| 1092 | return SPI_INVALID_LENGTH; |
| 1093 | } |
| 1094 | |
Stefan Tauner | a8d838d | 2011-11-06 23:51:09 +0000 | [diff] [blame] | 1095 | switch (ich_generation) { |
| 1096 | case CHIPSET_ICH7: |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 1097 | case CHIPSET_TUNNEL_CREEK: |
| 1098 | case CHIPSET_CENTERTON: |
Stefan Tauner | b2d5f6a | 2011-06-11 19:44:31 +0000 | [diff] [blame] | 1099 | return ich7_run_opcode(op, offset, datalength, data, maxlength); |
Stefan Tauner | a8d838d | 2011-11-06 23:51:09 +0000 | [diff] [blame] | 1100 | case CHIPSET_ICH8: |
| 1101 | default: /* Future version might behave the same */ |
Stefan Tauner | b2d5f6a | 2011-06-11 19:44:31 +0000 | [diff] [blame] | 1102 | return ich9_run_opcode(op, offset, datalength, data); |
Stefan Tauner | b2d5f6a | 2011-06-11 19:44:31 +0000 | [diff] [blame] | 1103 | } |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 1104 | } |
| 1105 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 1106 | static int ich_spi_send_command(struct flashctx *flash, unsigned int writecnt, |
| 1107 | unsigned int readcnt, |
| 1108 | const unsigned char *writearr, |
| 1109 | unsigned char *readarr) |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1110 | { |
Carl-Daniel Hailfinger | 142e30f | 2009-07-14 10:26:56 +0000 | [diff] [blame] | 1111 | int result; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1112 | int opcode_index = -1; |
| 1113 | const unsigned char cmd = *writearr; |
| 1114 | OPCODE *opcode; |
| 1115 | uint32_t addr = 0; |
| 1116 | uint8_t *data; |
| 1117 | int count; |
| 1118 | |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1119 | /* find cmd in opcodes-table */ |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1120 | opcode_index = find_opcode(curopcodes, cmd); |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1121 | if (opcode_index == -1) { |
Helge Wagner | 738e252 | 2010-10-05 22:06:05 +0000 | [diff] [blame] | 1122 | if (!ichspi_lock) |
| 1123 | opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt); |
Stefan Tauner | dc704ed | 2012-05-06 15:11:26 +0000 | [diff] [blame] | 1124 | if (opcode_index == SPI_INVALID_LENGTH) { |
| 1125 | msg_pdbg("OPCODE 0x%02x has unsupported length, will not execute.\n", cmd); |
| 1126 | return SPI_INVALID_LENGTH; |
| 1127 | } else if (opcode_index == -1) { |
Stefan Tauner | 355cbfd | 2011-05-28 02:37:14 +0000 | [diff] [blame] | 1128 | msg_pdbg("Invalid OPCODE 0x%02x, will not execute.\n", |
| 1129 | cmd); |
Helge Wagner | 738e252 | 2010-10-05 22:06:05 +0000 | [diff] [blame] | 1130 | return SPI_INVALID_OPCODE; |
| 1131 | } |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1132 | } |
| 1133 | |
| 1134 | opcode = &(curopcodes->opcode[opcode_index]); |
| 1135 | |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1136 | /* The following valid writecnt/readcnt combinations exist: |
| 1137 | * writecnt = 4, readcnt >= 0 |
| 1138 | * writecnt = 1, readcnt >= 0 |
| 1139 | * writecnt >= 4, readcnt = 0 |
| 1140 | * writecnt >= 1, readcnt = 0 |
| 1141 | * writecnt >= 1 is guaranteed for all commands. |
| 1142 | */ |
| 1143 | if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) && |
| 1144 | (writecnt != 4)) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1145 | msg_perr("%s: Internal command size error for opcode " |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1146 | "0x%02x, got writecnt=%i, want =4\n", __func__, cmd, |
| 1147 | writecnt); |
| 1148 | return SPI_INVALID_LENGTH; |
| 1149 | } |
| 1150 | if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) && |
| 1151 | (writecnt != 1)) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1152 | msg_perr("%s: Internal command size error for opcode " |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1153 | "0x%02x, got writecnt=%i, want =1\n", __func__, cmd, |
| 1154 | writecnt); |
| 1155 | return SPI_INVALID_LENGTH; |
| 1156 | } |
| 1157 | if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) && |
| 1158 | (writecnt < 4)) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1159 | msg_perr("%s: Internal command size error for opcode " |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1160 | "0x%02x, got writecnt=%i, want >=4\n", __func__, cmd, |
| 1161 | writecnt); |
| 1162 | return SPI_INVALID_LENGTH; |
| 1163 | } |
| 1164 | if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) || |
| 1165 | (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) && |
| 1166 | (readcnt)) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1167 | msg_perr("%s: Internal command size error for opcode " |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1168 | "0x%02x, got readcnt=%i, want =0\n", __func__, cmd, |
| 1169 | readcnt); |
| 1170 | return SPI_INVALID_LENGTH; |
| 1171 | } |
| 1172 | |
Stefan Tauner | b2d5f6a | 2011-06-11 19:44:31 +0000 | [diff] [blame] | 1173 | /* Translate read/write array/count. |
| 1174 | * The maximum data length is identical for the maximum read length and |
| 1175 | * for the maximum write length excluding opcode and address. Opcode and |
| 1176 | * address are stored in separate registers, not in the data registers |
| 1177 | * and are thus not counted towards data length. The only exception |
| 1178 | * applies if the opcode definition (un)intentionally classifies said |
| 1179 | * opcode incorrectly as non-address opcode or vice versa. */ |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1180 | if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) { |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 1181 | data = (uint8_t *) (writearr + 1); |
| 1182 | count = writecnt - 1; |
| 1183 | } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { |
| 1184 | data = (uint8_t *) (writearr + 4); |
| 1185 | count = writecnt - 4; |
| 1186 | } else { |
| 1187 | data = (uint8_t *) readarr; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1188 | count = readcnt; |
| 1189 | } |
Stefan Reinauer | 325b5d4 | 2008-06-27 15:18:20 +0000 | [diff] [blame] | 1190 | |
Nico Huber | ed098d6 | 2017-04-21 23:47:08 +0200 | [diff] [blame] | 1191 | /* if opcode-type requires an address */ |
| 1192 | if (cmd == JEDEC_REMS || cmd == JEDEC_RES) { |
| 1193 | addr = ichspi_bbar; |
| 1194 | } else if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS || |
| 1195 | opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) { |
| 1196 | /* BBAR may cut part of the chip off at the lower end. */ |
| 1197 | const uint32_t valid_base = ichspi_bbar & ((flash->chip->total_size * 1024) - 1); |
| 1198 | const uint32_t addr_offset = ichspi_bbar - valid_base; |
| 1199 | /* Highest address we can program is (2^24 - 1). */ |
| 1200 | const uint32_t valid_end = (1 << 24) - addr_offset; |
| 1201 | |
| 1202 | addr = writearr[1] << 16 | writearr[2] << 8 | writearr[3]; |
| 1203 | const uint32_t addr_end = addr + count; |
| 1204 | |
| 1205 | if (addr < valid_base || |
| 1206 | addr_end < addr || /* integer overflow check */ |
| 1207 | addr_end > valid_end) { |
| 1208 | msg_perr("%s: Addressed region 0x%06x-0x%06x not in allowed range 0x%06x-0x%06x\n", |
| 1209 | __func__, addr, addr_end - 1, valid_base, valid_end - 1); |
| 1210 | return SPI_INVALID_ADDRESS; |
| 1211 | } |
| 1212 | addr += addr_offset; |
| 1213 | } |
| 1214 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 1215 | result = run_opcode(flash, *opcode, addr, count, data); |
Carl-Daniel Hailfinger | 142e30f | 2009-07-14 10:26:56 +0000 | [diff] [blame] | 1216 | if (result) { |
Stefan Tauner | 8ed2934 | 2011-04-29 23:53:09 +0000 | [diff] [blame] | 1217 | msg_pdbg("Running OPCODE 0x%02x failed ", opcode->opcode); |
| 1218 | if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) || |
| 1219 | (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS)) { |
| 1220 | msg_pdbg("at address 0x%06x ", addr); |
| 1221 | } |
| 1222 | msg_pdbg("(payload length was %d).\n", count); |
| 1223 | |
| 1224 | /* Print out the data array if it contains data to write. |
| 1225 | * Errors are detected before the received data is read back into |
| 1226 | * the array so it won't make sense to print it then. */ |
| 1227 | if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) || |
| 1228 | (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) { |
| 1229 | int i; |
| 1230 | msg_pspew("The data was:\n"); |
Stefan Tauner | f382e35 | 2011-11-08 11:55:24 +0000 | [diff] [blame] | 1231 | for (i = 0; i < count; i++){ |
Stefan Tauner | 8ed2934 | 2011-04-29 23:53:09 +0000 | [diff] [blame] | 1232 | msg_pspew("%3d: 0x%02x\n", i, data[i]); |
| 1233 | } |
| 1234 | } |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1235 | } |
| 1236 | |
Carl-Daniel Hailfinger | 142e30f | 2009-07-14 10:26:56 +0000 | [diff] [blame] | 1237 | return result; |
Dominik Geyer | b46acba | 2008-05-16 12:55:55 +0000 | [diff] [blame] | 1238 | } |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 1239 | |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1240 | static struct hwseq_data { |
| 1241 | uint32_t size_comp0; |
| 1242 | uint32_t size_comp1; |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1243 | uint32_t addr_mask; |
| 1244 | bool only_4k; |
| 1245 | uint32_t hsfc_fcycle; |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1246 | } hwseq_data; |
| 1247 | |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1248 | /* Sets FLA in FADDR to (addr & hwseq_data.addr_mask) without touching other bits. */ |
Stefan Tauner | d0c5dc2 | 2011-10-20 12:57:14 +0000 | [diff] [blame] | 1249 | static void ich_hwseq_set_addr(uint32_t addr) |
| 1250 | { |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1251 | uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~hwseq_data.addr_mask; |
| 1252 | REGWRITE32(ICH9_REG_FADDR, (addr & hwseq_data.addr_mask) | addr_old); |
Stefan Tauner | d0c5dc2 | 2011-10-20 12:57:14 +0000 | [diff] [blame] | 1253 | } |
| 1254 | |
| 1255 | /* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes |
| 1256 | * of the block containing this address. May return nonsense if the address is |
| 1257 | * not valid. The erase block size for a specific address depends on the flash |
| 1258 | * partition layout as specified by FPB and the partition properties as defined |
| 1259 | * by UVSCC and LVSCC respectively. An alternative to implement this method |
| 1260 | * would be by querying FPB and the respective VSCC register directly. |
| 1261 | */ |
| 1262 | static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr) |
| 1263 | { |
Elyes HAOUAS | 29e46d0 | 2019-06-09 17:38:25 +0200 | [diff] [blame] | 1264 | uint8_t enc_berase; |
| 1265 | static const uint32_t dec_berase[4] = { |
| 1266 | 256, |
| 1267 | 4 * 1024, |
| 1268 | 8 * 1024, |
| 1269 | 64 * 1024 |
| 1270 | }; |
| 1271 | |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1272 | if (hwseq_data.only_4k) { |
| 1273 | return 4 * 1024; |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1274 | } |
Elyes HAOUAS | 29e46d0 | 2019-06-09 17:38:25 +0200 | [diff] [blame] | 1275 | |
| 1276 | ich_hwseq_set_addr(addr); |
| 1277 | enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >> HSFS_BERASE_OFF; |
| 1278 | return dec_berase[enc_berase]; |
Stefan Tauner | d0c5dc2 | 2011-10-20 12:57:14 +0000 | [diff] [blame] | 1279 | } |
| 1280 | |
| 1281 | /* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals. |
| 1282 | Resets all error flags in HSFS. |
| 1283 | Returns 0 if the cycle completes successfully without errors within |
| 1284 | timeout us, 1 on errors. */ |
Subrata Banik | 7cb4395 | 2022-03-16 20:40:42 +0530 | [diff] [blame^] | 1285 | static int ich_hwseq_wait_for_cycle_complete(unsigned int len) |
Stefan Tauner | d0c5dc2 | 2011-10-20 12:57:14 +0000 | [diff] [blame] | 1286 | { |
Subrata Banik | 7cb4395 | 2022-03-16 20:40:42 +0530 | [diff] [blame^] | 1287 | /* |
| 1288 | * The SPI bus may be busy due to performing operations from other masters, hence |
| 1289 | * introduce the long timeout of 30s to cover the worst case scenarios as well. |
| 1290 | */ |
| 1291 | unsigned int timeout_us = 30 * 1000 * 1000; |
Stefan Tauner | d0c5dc2 | 2011-10-20 12:57:14 +0000 | [diff] [blame] | 1292 | uint16_t hsfs; |
| 1293 | uint32_t addr; |
| 1294 | |
Subrata Banik | 7cb4395 | 2022-03-16 20:40:42 +0530 | [diff] [blame^] | 1295 | timeout_us /= 8; /* scale timeout duration to counter */ |
Stefan Tauner | d0c5dc2 | 2011-10-20 12:57:14 +0000 | [diff] [blame] | 1296 | while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) & |
| 1297 | (HSFS_FDONE | HSFS_FCERR)) == 0) && |
Subrata Banik | 7cb4395 | 2022-03-16 20:40:42 +0530 | [diff] [blame^] | 1298 | --timeout_us) { |
Stefan Tauner | d0c5dc2 | 2011-10-20 12:57:14 +0000 | [diff] [blame] | 1299 | programmer_delay(8); |
| 1300 | } |
| 1301 | REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); |
Subrata Banik | 7cb4395 | 2022-03-16 20:40:42 +0530 | [diff] [blame^] | 1302 | if (!timeout_us) { |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1303 | addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask; |
Stefan Tauner | d0c5dc2 | 2011-10-20 12:57:14 +0000 | [diff] [blame] | 1304 | msg_perr("Timeout error between offset 0x%08x and " |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1305 | "0x%08x (= 0x%08x + %d)!\n", |
| 1306 | addr, addr + len - 1, addr, len - 1); |
Stefan Tauner | d0c5dc2 | 2011-10-20 12:57:14 +0000 | [diff] [blame] | 1307 | prettyprint_ich9_reg_hsfs(hsfs); |
| 1308 | prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); |
| 1309 | return 1; |
| 1310 | } |
| 1311 | |
| 1312 | if (hsfs & HSFS_FCERR) { |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1313 | addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask; |
Stefan Tauner | d0c5dc2 | 2011-10-20 12:57:14 +0000 | [diff] [blame] | 1314 | msg_perr("Transaction error between offset 0x%08x and " |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1315 | "0x%08x (= 0x%08x + %d)!\n", |
Stefan Tauner | d0c5dc2 | 2011-10-20 12:57:14 +0000 | [diff] [blame] | 1316 | addr, addr + len - 1, addr, len - 1); |
| 1317 | prettyprint_ich9_reg_hsfs(hsfs); |
| 1318 | prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC)); |
| 1319 | return 1; |
| 1320 | } |
| 1321 | return 0; |
| 1322 | } |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1323 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 1324 | static int ich_hwseq_probe(struct flashctx *flash) |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1325 | { |
| 1326 | uint32_t total_size, boundary; |
| 1327 | uint32_t erase_size_low, size_low, erase_size_high, size_high; |
| 1328 | struct block_eraser *eraser; |
| 1329 | |
| 1330 | total_size = hwseq_data.size_comp0 + hwseq_data.size_comp1; |
Stefan Tauner | 5c316f9 | 2015-02-08 21:57:52 +0000 | [diff] [blame] | 1331 | msg_cdbg("Hardware sequencing reports %d attached SPI flash chip", |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1332 | (hwseq_data.size_comp1 != 0) ? 2 : 1); |
| 1333 | if (hwseq_data.size_comp1 != 0) |
| 1334 | msg_cdbg("s with a combined"); |
| 1335 | else |
| 1336 | msg_cdbg(" with a"); |
| 1337 | msg_cdbg(" density of %d kB.\n", total_size / 1024); |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 1338 | flash->chip->total_size = total_size / 1024; |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1339 | |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 1340 | eraser = &(flash->chip->block_erasers[0]); |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1341 | if (!hwseq_data.only_4k) |
| 1342 | boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12; |
| 1343 | else |
| 1344 | boundary = 0; |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1345 | size_high = total_size - boundary; |
| 1346 | erase_size_high = ich_hwseq_get_erase_block_size(boundary); |
| 1347 | |
| 1348 | if (boundary == 0) { |
Stefan Tauner | 5c316f9 | 2015-02-08 21:57:52 +0000 | [diff] [blame] | 1349 | msg_cdbg2("There is only one partition containing the whole " |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1350 | "address space (0x%06x - 0x%06x).\n", 0, size_high-1); |
| 1351 | eraser->eraseblocks[0].size = erase_size_high; |
| 1352 | eraser->eraseblocks[0].count = size_high / erase_size_high; |
Stefan Tauner | 5c316f9 | 2015-02-08 21:57:52 +0000 | [diff] [blame] | 1353 | msg_cdbg2("There are %d erase blocks with %d B each.\n", |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1354 | size_high / erase_size_high, erase_size_high); |
| 1355 | } else { |
Stefan Tauner | 5c316f9 | 2015-02-08 21:57:52 +0000 | [diff] [blame] | 1356 | msg_cdbg2("The flash address space (0x%06x - 0x%06x) is divided " |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1357 | "at address 0x%06x in two partitions.\n", |
Stefan Tauner | dbac46c | 2013-08-13 22:10:41 +0000 | [diff] [blame] | 1358 | 0, total_size-1, boundary); |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1359 | size_low = total_size - size_high; |
| 1360 | erase_size_low = ich_hwseq_get_erase_block_size(0); |
| 1361 | |
| 1362 | eraser->eraseblocks[0].size = erase_size_low; |
| 1363 | eraser->eraseblocks[0].count = size_low / erase_size_low; |
| 1364 | msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n", |
| 1365 | 0, size_low-1); |
| 1366 | msg_cdbg("In that range are %d erase blocks with %d B each.\n", |
| 1367 | size_low / erase_size_low, erase_size_low); |
| 1368 | |
| 1369 | eraser->eraseblocks[1].size = erase_size_high; |
| 1370 | eraser->eraseblocks[1].count = size_high / erase_size_high; |
| 1371 | msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n", |
Stefan Tauner | dbac46c | 2013-08-13 22:10:41 +0000 | [diff] [blame] | 1372 | boundary, total_size-1); |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1373 | msg_cdbg("In that range are %d erase blocks with %d B each.\n", |
| 1374 | size_high / erase_size_high, erase_size_high); |
| 1375 | } |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 1376 | flash->chip->tested = TEST_OK_PREW; |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1377 | return 1; |
| 1378 | } |
| 1379 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 1380 | static int ich_hwseq_block_erase(struct flashctx *flash, unsigned int addr, |
| 1381 | unsigned int len) |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1382 | { |
| 1383 | uint32_t erase_block; |
| 1384 | uint16_t hsfc; |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1385 | |
| 1386 | erase_block = ich_hwseq_get_erase_block_size(addr); |
| 1387 | if (len != erase_block) { |
| 1388 | msg_cerr("Erase block size for address 0x%06x is %d B, " |
| 1389 | "but requested erase block size is %d B. " |
| 1390 | "Not erasing anything.\n", addr, erase_block, len); |
| 1391 | return -1; |
| 1392 | } |
| 1393 | |
| 1394 | /* Although the hardware supports this (it would erase the whole block |
| 1395 | * containing the address) we play safe here. */ |
| 1396 | if (addr % erase_block != 0) { |
| 1397 | msg_cerr("Erase address 0x%06x is not aligned to the erase " |
| 1398 | "block boundary (any multiple of %d). " |
| 1399 | "Not erasing anything.\n", addr, erase_block); |
| 1400 | return -1; |
| 1401 | } |
| 1402 | |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 1403 | if (addr + len > flash->chip->total_size * 1024) { |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1404 | msg_perr("Request to erase some inaccessible memory address(es)" |
| 1405 | " (addr=0x%x, len=%d). " |
| 1406 | "Not erasing anything.\n", addr, len); |
| 1407 | return -1; |
| 1408 | } |
| 1409 | |
| 1410 | msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr); |
Stefan Tauner | 7608d36 | 2014-08-05 23:28:47 +0000 | [diff] [blame] | 1411 | ich_hwseq_set_addr(addr); |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1412 | |
| 1413 | /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */ |
| 1414 | REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); |
| 1415 | |
| 1416 | hsfc = REGREAD16(ICH9_REG_HSFC); |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1417 | hsfc &= ~hwseq_data.hsfc_fcycle; /* clear operation */ |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1418 | hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */ |
| 1419 | hsfc |= HSFC_FGO; /* start */ |
| 1420 | msg_pdbg("HSFC used for block erasing: "); |
| 1421 | prettyprint_ich9_reg_hsfc(hsfc); |
| 1422 | REGWRITE16(ICH9_REG_HSFC, hsfc); |
| 1423 | |
Subrata Banik | 7cb4395 | 2022-03-16 20:40:42 +0530 | [diff] [blame^] | 1424 | if (ich_hwseq_wait_for_cycle_complete(len)) |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1425 | return -1; |
| 1426 | return 0; |
| 1427 | } |
| 1428 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 1429 | static int ich_hwseq_read(struct flashctx *flash, uint8_t *buf, |
| 1430 | unsigned int addr, unsigned int len) |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1431 | { |
| 1432 | uint16_t hsfc; |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1433 | uint8_t block_len; |
| 1434 | |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 1435 | if (addr + len > flash->chip->total_size * 1024) { |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1436 | msg_perr("Request to read from an inaccessible memory address " |
| 1437 | "(addr=0x%x, len=%d).\n", addr, len); |
| 1438 | return -1; |
| 1439 | } |
| 1440 | |
| 1441 | msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr); |
| 1442 | /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ |
| 1443 | REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); |
| 1444 | |
| 1445 | while (len > 0) { |
Stefan Tauner | 7608d36 | 2014-08-05 23:28:47 +0000 | [diff] [blame] | 1446 | /* Obey programmer limit... */ |
Carl-Daniel Hailfinger | a5bcbce | 2014-07-19 22:03:29 +0000 | [diff] [blame] | 1447 | block_len = min(len, flash->mst->opaque.max_data_read); |
Stefan Tauner | 7608d36 | 2014-08-05 23:28:47 +0000 | [diff] [blame] | 1448 | /* as well as flash chip page borders as demanded in the Intel datasheets. */ |
| 1449 | block_len = min(block_len, 256 - (addr & 0xFF)); |
| 1450 | |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1451 | ich_hwseq_set_addr(addr); |
| 1452 | hsfc = REGREAD16(ICH9_REG_HSFC); |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1453 | hsfc &= ~hwseq_data.hsfc_fcycle; /* set read operation */ |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1454 | hsfc &= ~HSFC_FDBC; /* clear byte count */ |
| 1455 | /* set byte count */ |
| 1456 | hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); |
| 1457 | hsfc |= HSFC_FGO; /* start */ |
| 1458 | REGWRITE16(ICH9_REG_HSFC, hsfc); |
| 1459 | |
Subrata Banik | 7cb4395 | 2022-03-16 20:40:42 +0530 | [diff] [blame^] | 1460 | if (ich_hwseq_wait_for_cycle_complete(block_len)) |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1461 | return 1; |
| 1462 | ich_read_data(buf, block_len, ICH9_REG_FDATA0); |
| 1463 | addr += block_len; |
| 1464 | buf += block_len; |
| 1465 | len -= block_len; |
| 1466 | } |
| 1467 | return 0; |
| 1468 | } |
| 1469 | |
Mark Marshall | f20b7be | 2014-05-09 21:16:21 +0000 | [diff] [blame] | 1470 | static int ich_hwseq_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len) |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1471 | { |
| 1472 | uint16_t hsfc; |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1473 | uint8_t block_len; |
| 1474 | |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 1475 | if (addr + len > flash->chip->total_size * 1024) { |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1476 | msg_perr("Request to write to an inaccessible memory address " |
| 1477 | "(addr=0x%x, len=%d).\n", addr, len); |
| 1478 | return -1; |
| 1479 | } |
| 1480 | |
| 1481 | msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr); |
| 1482 | /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ |
| 1483 | REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS)); |
| 1484 | |
| 1485 | while (len > 0) { |
| 1486 | ich_hwseq_set_addr(addr); |
Stefan Tauner | 7608d36 | 2014-08-05 23:28:47 +0000 | [diff] [blame] | 1487 | /* Obey programmer limit... */ |
Carl-Daniel Hailfinger | a5bcbce | 2014-07-19 22:03:29 +0000 | [diff] [blame] | 1488 | block_len = min(len, flash->mst->opaque.max_data_write); |
Stefan Tauner | 7608d36 | 2014-08-05 23:28:47 +0000 | [diff] [blame] | 1489 | /* as well as flash chip page borders as demanded in the Intel datasheets. */ |
| 1490 | block_len = min(block_len, 256 - (addr & 0xFF)); |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1491 | ich_fill_data(buf, block_len, ICH9_REG_FDATA0); |
| 1492 | hsfc = REGREAD16(ICH9_REG_HSFC); |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1493 | hsfc &= ~hwseq_data.hsfc_fcycle; /* clear operation */ |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1494 | hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */ |
| 1495 | hsfc &= ~HSFC_FDBC; /* clear byte count */ |
| 1496 | /* set byte count */ |
| 1497 | hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); |
| 1498 | hsfc |= HSFC_FGO; /* start */ |
| 1499 | REGWRITE16(ICH9_REG_HSFC, hsfc); |
| 1500 | |
Subrata Banik | 7cb4395 | 2022-03-16 20:40:42 +0530 | [diff] [blame^] | 1501 | if (ich_hwseq_wait_for_cycle_complete(block_len)) |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1502 | return -1; |
| 1503 | addr += block_len; |
| 1504 | buf += block_len; |
| 1505 | len -= block_len; |
| 1506 | } |
| 1507 | return 0; |
| 1508 | } |
Stefan Tauner | d0c5dc2 | 2011-10-20 12:57:14 +0000 | [diff] [blame] | 1509 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 1510 | static int ich_spi_send_multicommand(struct flashctx *flash, |
| 1511 | struct spi_command *cmds) |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 1512 | { |
| 1513 | int ret = 0; |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1514 | int i; |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 1515 | int oppos, preoppos; |
| 1516 | for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) { |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 1517 | if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) { |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1518 | /* Next command is valid. */ |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 1519 | preoppos = find_preop(curopcodes, cmds->writearr[0]); |
| 1520 | oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]); |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1521 | if ((oppos == -1) && (preoppos != -1)) { |
| 1522 | /* Current command is listed as preopcode in |
| 1523 | * ICH struct OPCODES, but next command is not |
| 1524 | * listed as opcode in that struct. |
| 1525 | * Check for command sanity, then |
| 1526 | * try to reprogram the ICH opcode list. |
| 1527 | */ |
| 1528 | if (find_preop(curopcodes, |
| 1529 | (cmds + 1)->writearr[0]) != -1) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1530 | msg_perr("%s: Two subsequent " |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1531 | "preopcodes 0x%02x and 0x%02x, " |
| 1532 | "ignoring the first.\n", |
| 1533 | __func__, cmds->writearr[0], |
| 1534 | (cmds + 1)->writearr[0]); |
| 1535 | continue; |
| 1536 | } |
| 1537 | /* If the chipset is locked down, we'll fail |
| 1538 | * during execution of the next command anyway. |
| 1539 | * No need to bother with fixups. |
| 1540 | */ |
| 1541 | if (!ichspi_lock) { |
Helge Wagner | 738e252 | 2010-10-05 22:06:05 +0000 | [diff] [blame] | 1542 | oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt); |
| 1543 | if (oppos == -1) |
| 1544 | continue; |
| 1545 | curopcodes->opcode[oppos].atomic = preoppos + 1; |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1546 | continue; |
| 1547 | } |
| 1548 | } |
| 1549 | if ((oppos != -1) && (preoppos != -1)) { |
| 1550 | /* Current command is listed as preopcode in |
| 1551 | * ICH struct OPCODES and next command is listed |
| 1552 | * as opcode in that struct. Match them up. |
| 1553 | */ |
| 1554 | curopcodes->opcode[oppos].atomic = preoppos + 1; |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 1555 | continue; |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1556 | } |
| 1557 | /* If none of the above if-statements about oppos or |
| 1558 | * preoppos matched, this is a normal opcode. |
| 1559 | */ |
| 1560 | } |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 1561 | ret = ich_spi_send_command(flash, cmds->writecnt, cmds->readcnt, |
Carl-Daniel Hailfinger | 26f7e64 | 2009-09-18 15:50:56 +0000 | [diff] [blame] | 1562 | cmds->writearr, cmds->readarr); |
Carl-Daniel Hailfinger | f15e1ab | 2010-02-11 11:28:37 +0000 | [diff] [blame] | 1563 | /* Reset the type of all opcodes to non-atomic. */ |
| 1564 | for (i = 0; i < 8; i++) |
| 1565 | curopcodes->opcode[i].atomic = 0; |
Carl-Daniel Hailfinger | 02487aa | 2009-07-22 15:36:50 +0000 | [diff] [blame] | 1566 | } |
| 1567 | return ret; |
| 1568 | } |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 1569 | |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1570 | #define ICH_BMWAG(x) ((x >> 24) & 0xff) |
| 1571 | #define ICH_BMRAG(x) ((x >> 16) & 0xff) |
| 1572 | #define ICH_BRWA(x) ((x >> 8) & 0xff) |
| 1573 | #define ICH_BRRA(x) ((x >> 0) & 0xff) |
| 1574 | |
Nico Huber | 7590d1a | 2016-05-03 13:38:28 +0200 | [diff] [blame] | 1575 | static const enum ich_access_protection access_perms_to_protection[] = { |
| 1576 | LOCKED, WRITE_PROT, READ_PROT, NO_PROT |
| 1577 | }; |
| 1578 | static const char *const access_names[] = { |
| 1579 | "locked", "read-only", "write-only", "read-write" |
| 1580 | }; |
| 1581 | |
Nico Huber | 519be66 | 2018-12-23 20:03:35 +0100 | [diff] [blame] | 1582 | static enum ich_access_protection ich9_handle_frap(uint32_t frap, unsigned int i) |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1583 | { |
Nico Huber | aa91d5c | 2017-08-19 17:04:21 +0200 | [diff] [blame] | 1584 | const int rwperms_unknown = ARRAY_SIZE(access_names); |
Nico Huber | 2a5dfaf | 2019-07-04 16:01:51 +0200 | [diff] [blame] | 1585 | static const char *const region_names[] = { |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1586 | "Flash Descriptor", "BIOS", "Management Engine", |
Nico Huber | d2d3993 | 2019-01-18 16:49:37 +0100 | [diff] [blame] | 1587 | "Gigabit Ethernet", "Platform Data", "Device Expansion", |
Nico Huber | 2a5dfaf | 2019-07-04 16:01:51 +0200 | [diff] [blame] | 1588 | "BIOS2", "unknown", "EC/BMC", |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1589 | }; |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1590 | const char *const region_name = i < ARRAY_SIZE(region_names) ? region_names[i] : "unknown"; |
| 1591 | |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1592 | uint32_t base, limit; |
Nico Huber | aa91d5c | 2017-08-19 17:04:21 +0200 | [diff] [blame] | 1593 | int rwperms; |
Nico Huber | d2d3993 | 2019-01-18 16:49:37 +0100 | [diff] [blame] | 1594 | const int offset = i < 12 |
| 1595 | ? ICH9_REG_FREG0 + i * 4 |
| 1596 | : APL_REG_FREG12 + (i - 12) * 4; |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1597 | uint32_t freg = mmio_readl(ich_spibar + offset); |
| 1598 | |
Nico Huber | aa91d5c | 2017-08-19 17:04:21 +0200 | [diff] [blame] | 1599 | if (i < 8) { |
| 1600 | rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) | |
| 1601 | (((ICH_BRRA(frap) >> i) & 1) << 0); |
| 1602 | } else { |
| 1603 | /* Datasheets don't define any access bits for regions > 7. We |
| 1604 | can't rely on the actual descriptor settings either as there |
| 1605 | are several overrides for them (those by other masters are |
| 1606 | not even readable by us, *shrug*). */ |
| 1607 | rwperms = rwperms_unknown; |
| 1608 | } |
| 1609 | |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1610 | base = ICH_FREG_BASE(freg); |
| 1611 | limit = ICH_FREG_LIMIT(freg); |
Stefan Tauner | e3adea0 | 2012-08-27 15:12:36 +0000 | [diff] [blame] | 1612 | if (base > limit || (freg == 0 && i > 0)) { |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1613 | /* this FREG is disabled */ |
Nico Huber | 519be66 | 2018-12-23 20:03:35 +0100 | [diff] [blame] | 1614 | msg_pdbg2("0x%02X: 0x%08x FREG%u: %s region is unused.\n", |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1615 | offset, freg, i, region_name); |
Nico Huber | 7590d1a | 2016-05-03 13:38:28 +0200 | [diff] [blame] | 1616 | return NO_PROT; |
Stefan Tauner | 5210e72 | 2012-02-16 01:13:00 +0000 | [diff] [blame] | 1617 | } |
| 1618 | msg_pdbg("0x%02X: 0x%08x ", offset, freg); |
| 1619 | if (rwperms == 0x3) { |
Nico Huber | 519be66 | 2018-12-23 20:03:35 +0100 | [diff] [blame] | 1620 | msg_pdbg("FREG%u: %s region (0x%08x-0x%08x) is %s.\n", i, |
Nico Huber | 0bb3f71 | 2017-03-29 16:44:33 +0200 | [diff] [blame] | 1621 | region_name, base, limit, access_names[rwperms]); |
Nico Huber | 7590d1a | 2016-05-03 13:38:28 +0200 | [diff] [blame] | 1622 | return NO_PROT; |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1623 | } |
Nico Huber | aa91d5c | 2017-08-19 17:04:21 +0200 | [diff] [blame] | 1624 | if (rwperms == rwperms_unknown) { |
Nico Huber | 519be66 | 2018-12-23 20:03:35 +0100 | [diff] [blame] | 1625 | msg_pdbg("FREG%u: %s region (0x%08x-0x%08x) has unknown permissions.\n", |
Nico Huber | aa91d5c | 2017-08-19 17:04:21 +0200 | [diff] [blame] | 1626 | i, region_name, base, limit); |
Nico Huber | 7590d1a | 2016-05-03 13:38:28 +0200 | [diff] [blame] | 1627 | return NO_PROT; |
Nico Huber | aa91d5c | 2017-08-19 17:04:21 +0200 | [diff] [blame] | 1628 | } |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1629 | |
Nico Huber | 519be66 | 2018-12-23 20:03:35 +0100 | [diff] [blame] | 1630 | msg_pinfo("FREG%u: %s region (0x%08x-0x%08x) is %s.\n", i, |
Nico Huber | 0bb3f71 | 2017-03-29 16:44:33 +0200 | [diff] [blame] | 1631 | region_name, base, limit, access_names[rwperms]); |
Nico Huber | 7590d1a | 2016-05-03 13:38:28 +0200 | [diff] [blame] | 1632 | return access_perms_to_protection[rwperms]; |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1633 | } |
| 1634 | |
Stefan Tauner | bf69aaa | 2011-09-17 21:21:48 +0000 | [diff] [blame] | 1635 | /* In contrast to FRAP and the master section of the descriptor the bits |
| 1636 | * in the PR registers have an inverted meaning. The bits in FRAP |
| 1637 | * indicate read and write access _grant_. Here they indicate read |
| 1638 | * and write _protection_ respectively. If both bits are 0 the address |
| 1639 | * bits are ignored. |
| 1640 | */ |
| 1641 | #define ICH_PR_PERMS(pr) (((~((pr) >> PR_RP_OFF) & 1) << 0) | \ |
| 1642 | ((~((pr) >> PR_WP_OFF) & 1) << 1)) |
| 1643 | |
Nico Huber | 519be66 | 2018-12-23 20:03:35 +0100 | [diff] [blame] | 1644 | static enum ich_access_protection ich9_handle_pr(const size_t reg_pr0, unsigned int i) |
Stefan Tauner | bf69aaa | 2011-09-17 21:21:48 +0000 | [diff] [blame] | 1645 | { |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1646 | uint8_t off = reg_pr0 + (i * 4); |
Stefan Tauner | bf69aaa | 2011-09-17 21:21:48 +0000 | [diff] [blame] | 1647 | uint32_t pr = mmio_readl(ich_spibar + off); |
Stefan Tauner | 5210e72 | 2012-02-16 01:13:00 +0000 | [diff] [blame] | 1648 | unsigned int rwperms = ICH_PR_PERMS(pr); |
Stefan Tauner | bf69aaa | 2011-09-17 21:21:48 +0000 | [diff] [blame] | 1649 | |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1650 | /* From 5 on we have GPR registers and start from 0 again. */ |
| 1651 | const char *const prefix = i >= 5 ? "G" : ""; |
| 1652 | if (i >= 5) |
| 1653 | i -= 5; |
| 1654 | |
Stefan Tauner | 5210e72 | 2012-02-16 01:13:00 +0000 | [diff] [blame] | 1655 | if (rwperms == 0x3) { |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1656 | msg_pdbg2("0x%02X: 0x%08x (%sPR%u is unused)\n", off, pr, prefix, i); |
Nico Huber | 7590d1a | 2016-05-03 13:38:28 +0200 | [diff] [blame] | 1657 | return NO_PROT; |
Stefan Tauner | 5210e72 | 2012-02-16 01:13:00 +0000 | [diff] [blame] | 1658 | } |
| 1659 | |
| 1660 | msg_pdbg("0x%02X: 0x%08x ", off, pr); |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1661 | msg_pwarn("%sPR%u: Warning: 0x%08x-0x%08x is %s.\n", prefix, i, ICH_FREG_BASE(pr), |
Nico Huber | 0bb3f71 | 2017-03-29 16:44:33 +0200 | [diff] [blame] | 1662 | ICH_FREG_LIMIT(pr), access_names[rwperms]); |
Nico Huber | 7590d1a | 2016-05-03 13:38:28 +0200 | [diff] [blame] | 1663 | return access_perms_to_protection[rwperms]; |
Stefan Tauner | bf69aaa | 2011-09-17 21:21:48 +0000 | [diff] [blame] | 1664 | } |
| 1665 | |
Stefan Tauner | 75da80c | 2011-09-17 22:21:55 +0000 | [diff] [blame] | 1666 | /* Set/Clear the read and write protection enable bits of PR register @i |
| 1667 | * according to @read_prot and @write_prot. */ |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1668 | static void ich9_set_pr(const size_t reg_pr0, int i, int read_prot, int write_prot) |
Stefan Tauner | 75da80c | 2011-09-17 22:21:55 +0000 | [diff] [blame] | 1669 | { |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1670 | void *addr = ich_spibar + reg_pr0 + (i * 4); |
Stefan Tauner | 75da80c | 2011-09-17 22:21:55 +0000 | [diff] [blame] | 1671 | uint32_t old = mmio_readl(addr); |
| 1672 | uint32_t new; |
| 1673 | |
| 1674 | msg_gspew("PR%u is 0x%08x", i, old); |
| 1675 | new = old & ~((1 << PR_RP_OFF) | (1 << PR_WP_OFF)); |
| 1676 | if (read_prot) |
| 1677 | new |= (1 << PR_RP_OFF); |
| 1678 | if (write_prot) |
| 1679 | new |= (1 << PR_WP_OFF); |
| 1680 | if (old == new) { |
| 1681 | msg_gspew(" already.\n"); |
| 1682 | return; |
| 1683 | } |
| 1684 | msg_gspew(", trying to set it to 0x%08x ", new); |
| 1685 | rmmio_writel(new, addr); |
| 1686 | msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr)); |
| 1687 | } |
| 1688 | |
Carl-Daniel Hailfinger | a5bcbce | 2014-07-19 22:03:29 +0000 | [diff] [blame] | 1689 | static const struct spi_master spi_master_ich7 = { |
Michael Karcher | b9dbe48 | 2011-05-11 17:07:07 +0000 | [diff] [blame] | 1690 | .max_data_read = 64, |
| 1691 | .max_data_write = 64, |
| 1692 | .command = ich_spi_send_command, |
| 1693 | .multicommand = ich_spi_send_multicommand, |
| 1694 | .read = default_spi_read, |
| 1695 | .write_256 = default_spi_write_256, |
Nico Huber | 7bca126 | 2012-06-15 22:28:12 +0000 | [diff] [blame] | 1696 | .write_aai = default_spi_write_aai, |
Michael Karcher | b9dbe48 | 2011-05-11 17:07:07 +0000 | [diff] [blame] | 1697 | }; |
| 1698 | |
Carl-Daniel Hailfinger | a5bcbce | 2014-07-19 22:03:29 +0000 | [diff] [blame] | 1699 | static const struct spi_master spi_master_ich9 = { |
Michael Karcher | b9dbe48 | 2011-05-11 17:07:07 +0000 | [diff] [blame] | 1700 | .max_data_read = 64, |
| 1701 | .max_data_write = 64, |
| 1702 | .command = ich_spi_send_command, |
| 1703 | .multicommand = ich_spi_send_multicommand, |
| 1704 | .read = default_spi_read, |
| 1705 | .write_256 = default_spi_write_256, |
Nico Huber | 7bca126 | 2012-06-15 22:28:12 +0000 | [diff] [blame] | 1706 | .write_aai = default_spi_write_aai, |
Michael Karcher | b9dbe48 | 2011-05-11 17:07:07 +0000 | [diff] [blame] | 1707 | }; |
| 1708 | |
Carl-Daniel Hailfinger | a5bcbce | 2014-07-19 22:03:29 +0000 | [diff] [blame] | 1709 | static const struct opaque_master opaque_master_ich_hwseq = { |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1710 | .max_data_read = 64, |
| 1711 | .max_data_write = 64, |
| 1712 | .probe = ich_hwseq_probe, |
| 1713 | .read = ich_hwseq_read, |
| 1714 | .write = ich_hwseq_write, |
| 1715 | .erase = ich_hwseq_block_erase, |
| 1716 | }; |
| 1717 | |
Nico Huber | 560111e | 2017-04-26 12:27:17 +0200 | [diff] [blame] | 1718 | int ich_init_spi(void *spibar, enum ich_chipset ich_gen) |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1719 | { |
Nico Huber | 519be66 | 2018-12-23 20:03:35 +0100 | [diff] [blame] | 1720 | unsigned int i; |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 1721 | uint16_t tmp2; |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1722 | uint32_t tmp; |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1723 | char *arg; |
Stefan Tauner | 5210e72 | 2012-02-16 01:13:00 +0000 | [diff] [blame] | 1724 | int ich_spi_rw_restricted = 0; |
Stefan Tauner | d0c5dc2 | 2011-10-20 12:57:14 +0000 | [diff] [blame] | 1725 | int desc_valid = 0; |
Richard Hughes | e2cbb12 | 2019-01-02 21:11:08 +0000 | [diff] [blame] | 1726 | struct ich_descriptors desc; |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1727 | enum ich_spi_mode { |
| 1728 | ich_auto, |
| 1729 | ich_hwseq, |
| 1730 | ich_swseq |
| 1731 | } ich_spi_mode = ich_auto; |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1732 | size_t num_freg, num_pr, reg_pr0; |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1733 | |
Stefan Tauner | a8d838d | 2011-11-06 23:51:09 +0000 | [diff] [blame] | 1734 | ich_generation = ich_gen; |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 1735 | ich_spibar = spibar; |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1736 | |
Richard Hughes | e2cbb12 | 2019-01-02 21:11:08 +0000 | [diff] [blame] | 1737 | memset(&desc, 0x00, sizeof(struct ich_descriptors)); |
| 1738 | |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1739 | /* Moving registers / bits */ |
Nico Huber | d2d3993 | 2019-01-18 16:49:37 +0100 | [diff] [blame] | 1740 | switch (ich_generation) { |
| 1741 | case CHIPSET_100_SERIES_SUNRISE_POINT: |
| 1742 | case CHIPSET_C620_SERIES_LEWISBURG: |
Nico Huber | 2a5dfaf | 2019-07-04 16:01:51 +0200 | [diff] [blame] | 1743 | case CHIPSET_300_SERIES_CANNON_POINT: |
Nico Huber | d2d3993 | 2019-01-18 16:49:37 +0100 | [diff] [blame] | 1744 | case CHIPSET_APOLLO_LAKE: |
David Hendricks | a521636 | 2017-08-08 20:02:22 -0700 | [diff] [blame] | 1745 | num_pr = 6; /* Includes GPR0 */ |
| 1746 | reg_pr0 = PCH100_REG_FPR0; |
| 1747 | swseq_data.reg_ssfsc = PCH100_REG_SSFSC; |
| 1748 | swseq_data.reg_preop = PCH100_REG_PREOP; |
| 1749 | swseq_data.reg_optype = PCH100_REG_OPTYPE; |
| 1750 | swseq_data.reg_opmenu = PCH100_REG_OPMENU; |
| 1751 | hwseq_data.addr_mask = PCH100_FADDR_FLA; |
| 1752 | hwseq_data.only_4k = true; |
| 1753 | hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE; |
Nico Huber | d2d3993 | 2019-01-18 16:49:37 +0100 | [diff] [blame] | 1754 | break; |
| 1755 | default: |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1756 | num_pr = 5; |
| 1757 | reg_pr0 = ICH9_REG_PR0; |
| 1758 | swseq_data.reg_ssfsc = ICH9_REG_SSFS; |
| 1759 | swseq_data.reg_preop = ICH9_REG_PREOP; |
| 1760 | swseq_data.reg_optype = ICH9_REG_OPTYPE; |
| 1761 | swseq_data.reg_opmenu = ICH9_REG_OPMENU; |
| 1762 | hwseq_data.addr_mask = ICH9_FADDR_FLA; |
| 1763 | hwseq_data.only_4k = false; |
| 1764 | hwseq_data.hsfc_fcycle = HSFC_FCYCLE; |
Nico Huber | d2d3993 | 2019-01-18 16:49:37 +0100 | [diff] [blame] | 1765 | break; |
| 1766 | } |
| 1767 | switch (ich_generation) { |
| 1768 | case CHIPSET_100_SERIES_SUNRISE_POINT: |
| 1769 | num_freg = 10; |
| 1770 | break; |
| 1771 | case CHIPSET_C620_SERIES_LEWISBURG: |
| 1772 | num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */ |
| 1773 | break; |
Nico Huber | 2a5dfaf | 2019-07-04 16:01:51 +0200 | [diff] [blame] | 1774 | case CHIPSET_300_SERIES_CANNON_POINT: |
Nico Huber | d2d3993 | 2019-01-18 16:49:37 +0100 | [diff] [blame] | 1775 | case CHIPSET_APOLLO_LAKE: |
| 1776 | num_freg = 16; |
| 1777 | break; |
| 1778 | default: |
| 1779 | num_freg = 5; |
| 1780 | break; |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1781 | } |
| 1782 | |
Stefan Tauner | d0c5dc2 | 2011-10-20 12:57:14 +0000 | [diff] [blame] | 1783 | switch (ich_generation) { |
Stefan Tauner | a8d838d | 2011-11-06 23:51:09 +0000 | [diff] [blame] | 1784 | case CHIPSET_ICH7: |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 1785 | case CHIPSET_TUNNEL_CREEK: |
| 1786 | case CHIPSET_CENTERTON: |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1787 | msg_pdbg("0x00: 0x%04x (SPIS)\n", |
| 1788 | mmio_readw(ich_spibar + 0)); |
| 1789 | msg_pdbg("0x02: 0x%04x (SPIC)\n", |
| 1790 | mmio_readw(ich_spibar + 2)); |
| 1791 | msg_pdbg("0x04: 0x%08x (SPIA)\n", |
| 1792 | mmio_readl(ich_spibar + 4)); |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1793 | ichspi_bbar = mmio_readl(ich_spibar + 0x50); |
| 1794 | msg_pdbg("0x50: 0x%08x (BBAR)\n", |
| 1795 | ichspi_bbar); |
| 1796 | msg_pdbg("0x54: 0x%04x (PREOP)\n", |
| 1797 | mmio_readw(ich_spibar + 0x54)); |
| 1798 | msg_pdbg("0x56: 0x%04x (OPTYPE)\n", |
| 1799 | mmio_readw(ich_spibar + 0x56)); |
| 1800 | msg_pdbg("0x58: 0x%08x (OPMENU)\n", |
| 1801 | mmio_readl(ich_spibar + 0x58)); |
| 1802 | msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", |
| 1803 | mmio_readl(ich_spibar + 0x5c)); |
Stefan Tauner | 122dd12 | 2011-07-24 15:34:56 +0000 | [diff] [blame] | 1804 | for (i = 0; i < 3; i++) { |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1805 | int offs; |
| 1806 | offs = 0x60 + (i * 4); |
Nico Huber | 519be66 | 2018-12-23 20:03:35 +0100 | [diff] [blame] | 1807 | msg_pdbg("0x%02x: 0x%08x (PBR%u)\n", offs, |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1808 | mmio_readl(ich_spibar + offs), i); |
| 1809 | } |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1810 | if (mmio_readw(ich_spibar) & (1 << 15)) { |
Stefan Tauner | c6fa32d | 2013-01-04 22:54:07 +0000 | [diff] [blame] | 1811 | msg_pwarn("WARNING: SPI Configuration Lockdown activated.\n"); |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1812 | ichspi_lock = 1; |
| 1813 | } |
Stefan Tauner | 745f6bb | 2011-11-13 15:17:10 +0000 | [diff] [blame] | 1814 | ich_init_opcodes(); |
Stefan Tauner | a8d838d | 2011-11-06 23:51:09 +0000 | [diff] [blame] | 1815 | ich_set_bbar(0); |
Carl-Daniel Hailfinger | a5bcbce | 2014-07-19 22:03:29 +0000 | [diff] [blame] | 1816 | register_spi_master(&spi_master_ich7); |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1817 | break; |
Stefan Tauner | a8d838d | 2011-11-06 23:51:09 +0000 | [diff] [blame] | 1818 | case CHIPSET_ICH8: |
Stefan Tauner | d0c5dc2 | 2011-10-20 12:57:14 +0000 | [diff] [blame] | 1819 | default: /* Future version might behave the same */ |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1820 | arg = extract_programmer_param("ich_spi_mode"); |
| 1821 | if (arg && !strcmp(arg, "hwseq")) { |
| 1822 | ich_spi_mode = ich_hwseq; |
| 1823 | msg_pspew("user selected hwseq\n"); |
| 1824 | } else if (arg && !strcmp(arg, "swseq")) { |
| 1825 | ich_spi_mode = ich_swseq; |
| 1826 | msg_pspew("user selected swseq\n"); |
| 1827 | } else if (arg && !strcmp(arg, "auto")) { |
| 1828 | msg_pspew("user selected auto\n"); |
| 1829 | ich_spi_mode = ich_auto; |
| 1830 | } else if (arg && !strlen(arg)) { |
| 1831 | msg_perr("Missing argument for ich_spi_mode.\n"); |
| 1832 | free(arg); |
| 1833 | return ERROR_FATAL; |
| 1834 | } else if (arg) { |
| 1835 | msg_perr("Unknown argument for ich_spi_mode: %s\n", |
| 1836 | arg); |
| 1837 | free(arg); |
| 1838 | return ERROR_FATAL; |
| 1839 | } |
| 1840 | free(arg); |
| 1841 | |
Stefan Tauner | 29c8083 | 2011-06-12 08:14:10 +0000 | [diff] [blame] | 1842 | tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS); |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1843 | msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2); |
Stefan Tauner | 5520694 | 2011-06-11 09:53:22 +0000 | [diff] [blame] | 1844 | prettyprint_ich9_reg_hsfs(tmp2); |
Stefan Tauner | 29c8083 | 2011-06-12 08:14:10 +0000 | [diff] [blame] | 1845 | if (tmp2 & HSFS_FLOCKDN) { |
Nico Huber | 7590d1a | 2016-05-03 13:38:28 +0200 | [diff] [blame] | 1846 | msg_pinfo("SPI Configuration is locked down.\n"); |
Stefan Tauner | 5520694 | 2011-06-11 09:53:22 +0000 | [diff] [blame] | 1847 | ichspi_lock = 1; |
| 1848 | } |
Stefan Tauner | 1e14639 | 2011-09-15 23:52:55 +0000 | [diff] [blame] | 1849 | if (tmp2 & HSFS_FDV) |
Stefan Tauner | d0c5dc2 | 2011-10-20 12:57:14 +0000 | [diff] [blame] | 1850 | desc_valid = 1; |
| 1851 | if (!(tmp2 & HSFS_FDOPSS) && desc_valid) |
Stefan Tauner | d7d423b | 2012-10-20 09:13:16 +0000 | [diff] [blame] | 1852 | msg_pinfo("The Flash Descriptor Override Strap-Pin is set. Restrictions implied by\n" |
| 1853 | "the Master Section of the flash descriptor are NOT in effect. Please note\n" |
| 1854 | "that Protected Range (PR) restrictions still apply.\n"); |
Stefan Tauner | 745f6bb | 2011-11-13 15:17:10 +0000 | [diff] [blame] | 1855 | ich_init_opcodes(); |
Stefan Tauner | 5520694 | 2011-06-11 09:53:22 +0000 | [diff] [blame] | 1856 | |
Stefan Tauner | f382e35 | 2011-11-08 11:55:24 +0000 | [diff] [blame] | 1857 | if (desc_valid) { |
| 1858 | tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC); |
| 1859 | msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2); |
| 1860 | prettyprint_ich9_reg_hsfc(tmp2); |
| 1861 | } |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1862 | |
Stefan Tauner | 5ffe65b | 2011-07-07 04:10:57 +0000 | [diff] [blame] | 1863 | tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR); |
Stefan Tauner | eb58257 | 2012-09-21 12:52:50 +0000 | [diff] [blame] | 1864 | msg_pdbg2("0x08: 0x%08x (FADDR)\n", tmp); |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1865 | |
Nico Huber | d2d3993 | 2019-01-18 16:49:37 +0100 | [diff] [blame] | 1866 | switch (ich_gen) { |
| 1867 | case CHIPSET_100_SERIES_SUNRISE_POINT: |
| 1868 | case CHIPSET_C620_SERIES_LEWISBURG: |
Nico Huber | 2a5dfaf | 2019-07-04 16:01:51 +0200 | [diff] [blame] | 1869 | case CHIPSET_300_SERIES_CANNON_POINT: |
Nico Huber | d2d3993 | 2019-01-18 16:49:37 +0100 | [diff] [blame] | 1870 | case CHIPSET_APOLLO_LAKE: |
| 1871 | tmp = mmio_readl(ich_spibar + PCH100_REG_DLOCK); |
| 1872 | msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp); |
| 1873 | prettyprint_pch100_reg_dlock(tmp); |
| 1874 | break; |
| 1875 | default: |
| 1876 | break; |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1877 | } |
| 1878 | |
Stefan Tauner | f382e35 | 2011-11-08 11:55:24 +0000 | [diff] [blame] | 1879 | if (desc_valid) { |
| 1880 | tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP); |
| 1881 | msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp); |
| 1882 | msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp)); |
| 1883 | msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp)); |
| 1884 | msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp)); |
| 1885 | msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp)); |
| 1886 | |
Stefan Tauner | 5210e72 | 2012-02-16 01:13:00 +0000 | [diff] [blame] | 1887 | /* Handle FREGx and FRAP registers */ |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1888 | for (i = 0; i < num_freg; i++) |
Stefan Tauner | 5210e72 | 2012-02-16 01:13:00 +0000 | [diff] [blame] | 1889 | ich_spi_rw_restricted |= ich9_handle_frap(tmp, i); |
Stefan Tauner | 27cb34b | 2013-06-01 00:06:12 +0000 | [diff] [blame] | 1890 | if (ich_spi_rw_restricted) |
Nico Huber | 7590d1a | 2016-05-03 13:38:28 +0200 | [diff] [blame] | 1891 | msg_pinfo("Not all flash regions are freely accessible by flashrom. This is " |
Stefan Tauner | 4c72315 | 2016-01-14 22:47:55 +0000 | [diff] [blame] | 1892 | "most likely\ndue to an active ME. Please see " |
| 1893 | "https://flashrom.org/ME for details.\n"); |
Stefan Tauner | f382e35 | 2011-11-08 11:55:24 +0000 | [diff] [blame] | 1894 | } |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 1895 | |
Stefan Tauner | eb58257 | 2012-09-21 12:52:50 +0000 | [diff] [blame] | 1896 | /* Handle PR registers */ |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1897 | for (i = 0; i < num_pr; i++) { |
Stefan Tauner | 5210e72 | 2012-02-16 01:13:00 +0000 | [diff] [blame] | 1898 | /* if not locked down try to disable PR locks first */ |
| 1899 | if (!ichspi_lock) |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1900 | ich9_set_pr(reg_pr0, i, 0, 0); |
| 1901 | ich_spi_rw_restricted |= ich9_handle_pr(reg_pr0, i); |
Stefan Tauner | 5210e72 | 2012-02-16 01:13:00 +0000 | [diff] [blame] | 1902 | } |
| 1903 | |
Nico Huber | 7590d1a | 2016-05-03 13:38:28 +0200 | [diff] [blame] | 1904 | switch (ich_spi_rw_restricted) { |
| 1905 | case WRITE_PROT: |
| 1906 | msg_pwarn("At least some flash regions are write protected. For write operations,\n" |
| 1907 | "you should use a flash layout and include only writable regions. See\n" |
| 1908 | "manpage for more details.\n"); |
| 1909 | break; |
| 1910 | case READ_PROT: |
| 1911 | case LOCKED: |
| 1912 | msg_pwarn("At least some flash regions are read protected. You have to use a flash\n" |
| 1913 | "layout and include only accessible regions. For write operations, you'll\n" |
| 1914 | "additionally need the --noverify-all switch. See manpage for more details.\n" |
| 1915 | ); |
| 1916 | break; |
Stefan Tauner | 5210e72 | 2012-02-16 01:13:00 +0000 | [diff] [blame] | 1917 | } |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 1918 | |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1919 | tmp = mmio_readl(ich_spibar + swseq_data.reg_ssfsc); |
| 1920 | msg_pdbg("0x%zx: 0x%02x (SSFS)\n", swseq_data.reg_ssfsc, tmp & 0xff); |
Stefan Tauner | 2a8b262 | 2011-06-11 09:53:16 +0000 | [diff] [blame] | 1921 | prettyprint_ich9_reg_ssfs(tmp); |
Stefan Tauner | 29c8083 | 2011-06-12 08:14:10 +0000 | [diff] [blame] | 1922 | if (tmp & SSFS_FCERR) { |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 1923 | msg_pdbg("Clearing SSFS.FCERR\n"); |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1924 | mmio_writeb(SSFS_FCERR, ich_spibar + swseq_data.reg_ssfsc); |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 1925 | } |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1926 | msg_pdbg("0x%zx: 0x%06x (SSFC)\n", swseq_data.reg_ssfsc + 1, tmp >> 8); |
Stefan Tauner | 2a8b262 | 2011-06-11 09:53:16 +0000 | [diff] [blame] | 1927 | prettyprint_ich9_reg_ssfc(tmp); |
Carl-Daniel Hailfinger | eacbd16 | 2011-03-17 00:10:25 +0000 | [diff] [blame] | 1928 | |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1929 | msg_pdbg("0x%zx: 0x%04x (PREOP)\n", |
| 1930 | swseq_data.reg_preop, mmio_readw(ich_spibar + swseq_data.reg_preop)); |
| 1931 | msg_pdbg("0x%zx: 0x%04x (OPTYPE)\n", |
| 1932 | swseq_data.reg_optype, mmio_readw(ich_spibar + swseq_data.reg_optype)); |
| 1933 | msg_pdbg("0x%zx: 0x%08x (OPMENU)\n", |
| 1934 | swseq_data.reg_opmenu, mmio_readl(ich_spibar + swseq_data.reg_opmenu)); |
| 1935 | msg_pdbg("0x%zx: 0x%08x (OPMENU+4)\n", |
| 1936 | swseq_data.reg_opmenu + 4, mmio_readl(ich_spibar + swseq_data.reg_opmenu + 4)); |
Nico Huber | d2d3993 | 2019-01-18 16:49:37 +0100 | [diff] [blame] | 1937 | |
| 1938 | if (desc_valid) { |
| 1939 | switch (ich_gen) { |
| 1940 | case CHIPSET_ICH8: |
| 1941 | case CHIPSET_100_SERIES_SUNRISE_POINT: |
| 1942 | case CHIPSET_C620_SERIES_LEWISBURG: |
Nico Huber | 2a5dfaf | 2019-07-04 16:01:51 +0200 | [diff] [blame] | 1943 | case CHIPSET_300_SERIES_CANNON_POINT: |
Nico Huber | d2d3993 | 2019-01-18 16:49:37 +0100 | [diff] [blame] | 1944 | case CHIPSET_APOLLO_LAKE: |
| 1945 | case CHIPSET_BAYTRAIL: |
| 1946 | break; |
| 1947 | default: |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 1948 | ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR); |
Nico Huber | d2d3993 | 2019-01-18 16:49:37 +0100 | [diff] [blame] | 1949 | msg_pdbg("0x%x: 0x%08x (BBAR)\n", ICH9_REG_BBAR, ichspi_bbar); |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 1950 | ich_set_bbar(0); |
Nico Huber | d2d3993 | 2019-01-18 16:49:37 +0100 | [diff] [blame] | 1951 | break; |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 1952 | } |
Stefan Tauner | bd649e4 | 2011-07-01 00:39:16 +0000 | [diff] [blame] | 1953 | |
Nico Huber | d2d3993 | 2019-01-18 16:49:37 +0100 | [diff] [blame] | 1954 | if (ich_gen == CHIPSET_ICH8) { |
| 1955 | tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC); |
| 1956 | msg_pdbg("0x%x: 0x%08x (VSCC)\n", ICH8_REG_VSCC, tmp); |
| 1957 | msg_pdbg("VSCC: "); |
| 1958 | prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true); |
| 1959 | } else { |
Stefan Tauner | f382e35 | 2011-11-08 11:55:24 +0000 | [diff] [blame] | 1960 | tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC); |
Nico Huber | d2d3993 | 2019-01-18 16:49:37 +0100 | [diff] [blame] | 1961 | msg_pdbg("0x%x: 0x%08x (LVSCC)\n", ICH9_REG_LVSCC, tmp); |
Stefan Tauner | f382e35 | 2011-11-08 11:55:24 +0000 | [diff] [blame] | 1962 | msg_pdbg("LVSCC: "); |
Nico Huber | d152fb9 | 2017-06-19 12:57:10 +0200 | [diff] [blame] | 1963 | prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true); |
Stefan Tauner | 1e14639 | 2011-09-15 23:52:55 +0000 | [diff] [blame] | 1964 | |
Stefan Tauner | f382e35 | 2011-11-08 11:55:24 +0000 | [diff] [blame] | 1965 | tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC); |
Nico Huber | d2d3993 | 2019-01-18 16:49:37 +0100 | [diff] [blame] | 1966 | msg_pdbg("0x%x: 0x%08x (UVSCC)\n", ICH9_REG_UVSCC, tmp); |
Stefan Tauner | f382e35 | 2011-11-08 11:55:24 +0000 | [diff] [blame] | 1967 | msg_pdbg("UVSCC: "); |
Nico Huber | d152fb9 | 2017-06-19 12:57:10 +0200 | [diff] [blame] | 1968 | prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, false); |
Stefan Tauner | f382e35 | 2011-11-08 11:55:24 +0000 | [diff] [blame] | 1969 | } |
Stefan Tauner | 1e14639 | 2011-09-15 23:52:55 +0000 | [diff] [blame] | 1970 | |
Nico Huber | d2d3993 | 2019-01-18 16:49:37 +0100 | [diff] [blame] | 1971 | switch (ich_gen) { |
| 1972 | case CHIPSET_ICH8: |
| 1973 | case CHIPSET_100_SERIES_SUNRISE_POINT: |
| 1974 | case CHIPSET_C620_SERIES_LEWISBURG: |
Nico Huber | 2a5dfaf | 2019-07-04 16:01:51 +0200 | [diff] [blame] | 1975 | case CHIPSET_300_SERIES_CANNON_POINT: |
Nico Huber | d2d3993 | 2019-01-18 16:49:37 +0100 | [diff] [blame] | 1976 | case CHIPSET_APOLLO_LAKE: |
| 1977 | break; |
| 1978 | default: |
| 1979 | tmp = mmio_readl(ich_spibar + ICH9_REG_FPB); |
| 1980 | msg_pdbg("0x%x: 0x%08x (FPB)\n", ICH9_REG_FPB, tmp); |
| 1981 | break; |
| 1982 | } |
| 1983 | |
Nico Huber | d54e4f4 | 2017-03-23 23:45:47 +0100 | [diff] [blame] | 1984 | if (read_ich_descriptors_via_fdo(ich_gen, ich_spibar, &desc) == ICH_RET_OK) |
Stefan Tauner | 2ba9f6e | 2014-08-20 15:39:19 +0000 | [diff] [blame] | 1985 | prettyprint_ich_descriptors(ich_gen, &desc); |
| 1986 | |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1987 | /* If the descriptor is valid and indicates multiple |
| 1988 | * flash devices we need to use hwseq to be able to |
| 1989 | * access the second flash device. |
| 1990 | */ |
| 1991 | if (ich_spi_mode == ich_auto && desc.content.NC != 0) { |
| 1992 | msg_pinfo("Enabling hardware sequencing due to " |
| 1993 | "multiple flash chips detected.\n"); |
| 1994 | ich_spi_mode = ich_hwseq; |
| 1995 | } |
Stefan Tauner | 1e14639 | 2011-09-15 23:52:55 +0000 | [diff] [blame] | 1996 | } |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 1997 | |
| 1998 | if (ich_spi_mode == ich_auto && ichspi_lock && |
| 1999 | ich_missing_opcodes()) { |
| 2000 | msg_pinfo("Enabling hardware sequencing because " |
| 2001 | "some important opcode is locked.\n"); |
| 2002 | ich_spi_mode = ich_hwseq; |
| 2003 | } |
| 2004 | |
Nico Huber | 2a5dfaf | 2019-07-04 16:01:51 +0200 | [diff] [blame] | 2005 | if (ich_spi_mode == ich_auto && |
| 2006 | (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT || |
| 2007 | ich_gen == CHIPSET_300_SERIES_CANNON_POINT)) { |
| 2008 | msg_pdbg("Enabling hardware sequencing by default for 100+ series PCH.\n"); |
Nico Huber | 22f2dc5 | 2017-08-31 16:14:22 +0200 | [diff] [blame] | 2009 | ich_spi_mode = ich_hwseq; |
| 2010 | } |
| 2011 | |
Nico Huber | d2d3993 | 2019-01-18 16:49:37 +0100 | [diff] [blame] | 2012 | if (ich_spi_mode == ich_auto && ich_gen == CHIPSET_APOLLO_LAKE) { |
| 2013 | msg_pdbg("Enabling hardware sequencing by default for Apollo Lake.\n"); |
| 2014 | ich_spi_mode = ich_hwseq; |
| 2015 | } |
| 2016 | |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 2017 | if (ich_spi_mode == ich_hwseq) { |
| 2018 | if (!desc_valid) { |
| 2019 | msg_perr("Hardware sequencing was requested " |
| 2020 | "but the flash descriptor is not " |
| 2021 | "valid. Aborting.\n"); |
| 2022 | return ERROR_FATAL; |
| 2023 | } |
Stefan Tauner | 2ba9f6e | 2014-08-20 15:39:19 +0000 | [diff] [blame] | 2024 | |
| 2025 | int tmpi = getFCBA_component_density(ich_generation, &desc, 0); |
| 2026 | if (tmpi < 0) { |
| 2027 | msg_perr("Could not determine density of flash component %d.\n", 0); |
| 2028 | return ERROR_FATAL; |
| 2029 | } |
| 2030 | hwseq_data.size_comp0 = tmpi; |
| 2031 | |
| 2032 | tmpi = getFCBA_component_density(ich_generation, &desc, 1); |
| 2033 | if (tmpi < 0) { |
| 2034 | msg_perr("Could not determine density of flash component %d.\n", 1); |
| 2035 | return ERROR_FATAL; |
| 2036 | } |
| 2037 | hwseq_data.size_comp1 = tmpi; |
| 2038 | |
Carl-Daniel Hailfinger | a5bcbce | 2014-07-19 22:03:29 +0000 | [diff] [blame] | 2039 | register_opaque_master(&opaque_master_ich_hwseq); |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 2040 | } else { |
Carl-Daniel Hailfinger | a5bcbce | 2014-07-19 22:03:29 +0000 | [diff] [blame] | 2041 | register_spi_master(&spi_master_ich9); |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 2042 | } |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 2043 | break; |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 2044 | } |
| 2045 | |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 2046 | return 0; |
| 2047 | } |
| 2048 | |
Carl-Daniel Hailfinger | a5bcbce | 2014-07-19 22:03:29 +0000 | [diff] [blame] | 2049 | static const struct spi_master spi_master_via = { |
Michael Karcher | b9dbe48 | 2011-05-11 17:07:07 +0000 | [diff] [blame] | 2050 | .max_data_read = 16, |
| 2051 | .max_data_write = 16, |
| 2052 | .command = ich_spi_send_command, |
| 2053 | .multicommand = ich_spi_send_multicommand, |
| 2054 | .read = default_spi_read, |
| 2055 | .write_256 = default_spi_write_256, |
Nico Huber | 7bca126 | 2012-06-15 22:28:12 +0000 | [diff] [blame] | 2056 | .write_aai = default_spi_write_aai, |
Michael Karcher | b9dbe48 | 2011-05-11 17:07:07 +0000 | [diff] [blame] | 2057 | }; |
| 2058 | |
Nico Huber | 560111e | 2017-04-26 12:27:17 +0200 | [diff] [blame] | 2059 | int via_init_spi(uint32_t mmio_base) |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 2060 | { |
Carl-Daniel Hailfinger | 841d631 | 2010-11-24 23:37:22 +0000 | [diff] [blame] | 2061 | int i; |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 2062 | |
Stefan Tauner | 7fb5aa0 | 2013-08-14 15:48:44 +0000 | [diff] [blame] | 2063 | ich_spibar = rphysmap("VIA SPI MMIO registers", mmio_base, 0x70); |
| 2064 | if (ich_spibar == ERROR_PTR) |
| 2065 | return ERROR_FATAL; |
Helge Wagner | dd73d83 | 2012-08-24 23:03:46 +0000 | [diff] [blame] | 2066 | /* Do we really need no write enable? Like the LPC one at D17F0 0x40 */ |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 2067 | |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 2068 | /* Not sure if it speaks all these bus protocols. */ |
Nico Huber | 2e50cdc | 2018-09-23 20:20:26 +0200 | [diff] [blame] | 2069 | internal_buses_supported &= BUS_LPC | BUS_FWH; |
Stefan Tauner | a8d838d | 2011-11-06 23:51:09 +0000 | [diff] [blame] | 2070 | ich_generation = CHIPSET_ICH7; |
Carl-Daniel Hailfinger | a5bcbce | 2014-07-19 22:03:29 +0000 | [diff] [blame] | 2071 | register_spi_master(&spi_master_via); |
Carl-Daniel Hailfinger | 841d631 | 2010-11-24 23:37:22 +0000 | [diff] [blame] | 2072 | |
| 2073 | msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); |
| 2074 | msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2)); |
| 2075 | msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(ich_spibar + 4)); |
| 2076 | for (i = 0; i < 2; i++) { |
| 2077 | int offs; |
| 2078 | offs = 8 + (i * 8); |
| 2079 | msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs, |
| 2080 | mmio_readl(ich_spibar + offs), i); |
| 2081 | msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, |
| 2082 | mmio_readl(ich_spibar + offs + 4), i); |
| 2083 | } |
| 2084 | ichspi_bbar = mmio_readl(ich_spibar + 0x50); |
| 2085 | msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar); |
| 2086 | msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x54)); |
| 2087 | msg_pdbg("0x56: 0x%04x (OPTYPE)\n", mmio_readw(ich_spibar + 0x56)); |
| 2088 | msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(ich_spibar + 0x58)); |
| 2089 | msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + 0x5c)); |
| 2090 | for (i = 0; i < 3; i++) { |
| 2091 | int offs; |
| 2092 | offs = 0x60 + (i * 4); |
| 2093 | msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs, |
| 2094 | mmio_readl(ich_spibar + offs), i); |
| 2095 | } |
| 2096 | msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n", |
| 2097 | mmio_readw(ich_spibar + 0x6c)); |
| 2098 | if (mmio_readw(ich_spibar) & (1 << 15)) { |
Stefan Tauner | c6fa32d | 2013-01-04 22:54:07 +0000 | [diff] [blame] | 2099 | msg_pwarn("Warning: SPI Configuration Lockdown activated.\n"); |
Carl-Daniel Hailfinger | 841d631 | 2010-11-24 23:37:22 +0000 | [diff] [blame] | 2100 | ichspi_lock = 1; |
| 2101 | } |
| 2102 | |
Stefan Tauner | a8d838d | 2011-11-06 23:51:09 +0000 | [diff] [blame] | 2103 | ich_set_bbar(0); |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 2104 | ich_init_opcodes(); |
| 2105 | |
| 2106 | return 0; |
| 2107 | } |
| 2108 | |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 2109 | #endif |