blob: 21f6d9b2e1f39ddb422aec0bc351ec414cbf9806 [file] [log] [blame]
Dominik Geyerb46acba2008-05-16 12:55:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
5 * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
6 * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
Stefan Reinauera9424d52008-06-27 16:28:34 +00007 * Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00008 * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
Stefan Tauner8b391b82011-08-09 01:49:34 +00009 * Copyright (C) 2011 Stefan Tauner
Dominik Geyerb46acba2008-05-16 12:55:55 +000010 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
Dominik Geyerb46acba2008-05-16 12:55:55 +000020 */
21
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000022#if defined(__i386__) || defined(__x86_64__)
23
Dominik Geyerb46acba2008-05-16 12:55:55 +000024#include <string.h>
Stefan Taunerd0c5dc22011-10-20 12:57:14 +000025#include <stdlib.h>
Dominik Geyerb46acba2008-05-16 12:55:55 +000026#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000027#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000028#include "hwaccess.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000029#include "spi.h"
Stefan Tauner1e146392011-09-15 23:52:55 +000030#include "ich_descriptors.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000031
Nico Huberd2d39932019-01-18 16:49:37 +010032/* Apollo Lake */
33#define APL_REG_FREG12 0xe0 /* 32 Bytes Flash Region 12 */
34
Nico Huberd54e4f42017-03-23 23:45:47 +010035/* Sunrise Point */
36
37/* Added HSFS Status bits */
38#define HSFS_WRSDIS_OFF 11 /* 11: Flash Configuration Lock-Down */
39#define HSFS_WRSDIS (0x1 << HSFS_WRSDIS_OFF)
40#define HSFS_PRR34_LOCKDN_OFF 12 /* 12: PRR3 PRR4 Lock-Down */
41#define HSFS_PRR34_LOCKDN (0x1 << HSFS_PRR34_LOCKDN_OFF)
42/* HSFS_BERASE vanished */
43
44/*
45 * HSFC and HSFS 16-bit registers are combined into the 32-bit
46 * BIOS_HSFSTS_CTL register in the Sunrise Point datasheet,
47 * however we still treat them separately in order to reuse code.
48 */
49
50/* Changed HSFC Control bits */
51#define PCH100_HSFC_FCYCLE_OFF (17 - 16) /* 1-4: FLASH Cycle */
52#define PCH100_HSFC_FCYCLE (0xf << PCH100_HSFC_FCYCLE_OFF)
53/* New HSFC Control bit */
54#define HSFC_WET_OFF (21 - 16) /* 5: Write Enable Type */
55#define HSFC_WET (0x1 << HSFC_WET_OFF)
56
57#define PCH100_FADDR_FLA 0x07ffffff
58
59#define PCH100_REG_DLOCK 0x0c /* 32 Bits Discrete Lock Bits */
60#define DLOCK_BMWAG_LOCKDN_OFF 0
61#define DLOCK_BMWAG_LOCKDN (0x1 << DLOCK_BMWAG_LOCKDN_OFF)
62#define DLOCK_BMRAG_LOCKDN_OFF 1
63#define DLOCK_BMRAG_LOCKDN (0x1 << DLOCK_BMRAG_LOCKDN_OFF)
64#define DLOCK_SBMWAG_LOCKDN_OFF 2
65#define DLOCK_SBMWAG_LOCKDN (0x1 << DLOCK_SBMWAG_LOCKDN_OFF)
66#define DLOCK_SBMRAG_LOCKDN_OFF 3
67#define DLOCK_SBMRAG_LOCKDN (0x1 << DLOCK_SBMRAG_LOCKDN_OFF)
68#define DLOCK_PR0_LOCKDN_OFF 8
69#define DLOCK_PR0_LOCKDN (0x1 << DLOCK_PR0_LOCKDN_OFF)
70#define DLOCK_PR1_LOCKDN_OFF 9
71#define DLOCK_PR1_LOCKDN (0x1 << DLOCK_PR1_LOCKDN_OFF)
72#define DLOCK_PR2_LOCKDN_OFF 10
73#define DLOCK_PR2_LOCKDN (0x1 << DLOCK_PR2_LOCKDN_OFF)
74#define DLOCK_PR3_LOCKDN_OFF 11
75#define DLOCK_PR3_LOCKDN (0x1 << DLOCK_PR3_LOCKDN_OFF)
76#define DLOCK_PR4_LOCKDN_OFF 12
77#define DLOCK_PR4_LOCKDN (0x1 << DLOCK_PR4_LOCKDN_OFF)
78#define DLOCK_SSEQ_LOCKDN_OFF 16
79#define DLOCK_SSEQ_LOCKDN (0x1 << DLOCK_SSEQ_LOCKDN_OFF)
80
81#define PCH100_REG_FPR0 0x84 /* 32 Bits Protected Range 0 */
82#define PCH100_REG_GPR0 0x98 /* 32 Bits Global Protected Range 0 */
83
84#define PCH100_REG_SSFSC 0xA0 /* 32 Bits Status (8) + Control (24) */
85#define PCH100_REG_PREOP 0xA4 /* 16 Bits */
86#define PCH100_REG_OPTYPE 0xA6 /* 16 Bits */
87#define PCH100_REG_OPMENU 0xA8 /* 64 Bits */
88
Stefan Reinauera9424d52008-06-27 16:28:34 +000089/* ICH9 controller register definition */
Stefan Tauner55206942011-06-11 09:53:22 +000090#define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */
91#define HSFS_FDONE_OFF 0 /* 0: Flash Cycle Done */
92#define HSFS_FDONE (0x1 << HSFS_FDONE_OFF)
93#define HSFS_FCERR_OFF 1 /* 1: Flash Cycle Error */
94#define HSFS_FCERR (0x1 << HSFS_FCERR_OFF)
95#define HSFS_AEL_OFF 2 /* 2: Access Error Log */
96#define HSFS_AEL (0x1 << HSFS_AEL_OFF)
97#define HSFS_BERASE_OFF 3 /* 3-4: Block/Sector Erase Size */
98#define HSFS_BERASE (0x3 << HSFS_BERASE_OFF)
99#define HSFS_SCIP_OFF 5 /* 5: SPI Cycle In Progress */
100#define HSFS_SCIP (0x1 << HSFS_SCIP_OFF)
101 /* 6-12: reserved */
102#define HSFS_FDOPSS_OFF 13 /* 13: Flash Descriptor Override Pin-Strap Status */
103#define HSFS_FDOPSS (0x1 << HSFS_FDOPSS_OFF)
104#define HSFS_FDV_OFF 14 /* 14: Flash Descriptor Valid */
105#define HSFS_FDV (0x1 << HSFS_FDV_OFF)
106#define HSFS_FLOCKDN_OFF 15 /* 15: Flash Configuration Lock-Down */
107#define HSFS_FLOCKDN (0x1 << HSFS_FLOCKDN_OFF)
108
109#define ICH9_REG_HSFC 0x06 /* 16 Bits Hardware Sequencing Flash Control */
110#define HSFC_FGO_OFF 0 /* 0: Flash Cycle Go */
111#define HSFC_FGO (0x1 << HSFC_FGO_OFF)
112#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
113#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
114 /* 3-7: reserved */
115#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
116#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
117 /* 14: reserved */
118#define HSFC_SME_OFF 15 /* 15: SPI SMI# Enable */
119#define HSFC_SME (0x1 << HSFC_SME_OFF)
120
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000121#define ICH9_REG_FADDR 0x08 /* 32 Bits */
Nico Huberd54e4f42017-03-23 23:45:47 +0100122#define ICH9_FADDR_FLA 0x01ffffff
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000123#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000124
Stefan Tauner29c80832011-06-12 08:14:10 +0000125#define ICH9_REG_FRAP 0x50 /* 32 Bytes Flash Region Access Permissions */
126#define ICH9_REG_FREG0 0x54 /* 32 Bytes Flash Region 0 */
127
128#define ICH9_REG_PR0 0x74 /* 32 Bytes Protected Range 0 */
Stefan Taunerbf69aaa2011-09-17 21:21:48 +0000129#define PR_WP_OFF 31 /* 31: write protection enable */
130#define PR_RP_OFF 15 /* 15: read protection enable */
Stefan Tauner29c80832011-06-12 08:14:10 +0000131
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000132#define ICH9_REG_SSFS 0x90 /* 08 Bits */
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000133#define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */
134#define SSFS_SCIP (0x1 << SSFS_SCIP_OFF)
135#define SSFS_FDONE_OFF 2 /* Cycle Done Status */
136#define SSFS_FDONE (0x1 << SSFS_FDONE_OFF)
137#define SSFS_FCERR_OFF 3 /* Flash Cycle Error */
138#define SSFS_FCERR (0x1 << SSFS_FCERR_OFF)
139#define SSFS_AEL_OFF 4 /* Access Error Log */
140#define SSFS_AEL (0x1 << SSFS_AEL_OFF)
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000141/* The following bits are reserved in SSFS: 1,5-7. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000142#define SSFS_RESERVED_MASK 0x000000e2
Stefan Reinauera9424d52008-06-27 16:28:34 +0000143
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000144#define ICH9_REG_SSFC 0x91 /* 24 Bits */
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000145/* We combine SSFS and SSFC to one 32-bit word,
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000146 * therefore SSFC bits are off by 8. */
147 /* 0: reserved */
148#define SSFC_SCGO_OFF (1 + 8) /* 1: SPI Cycle Go */
149#define SSFC_SCGO (0x1 << SSFC_SCGO_OFF)
150#define SSFC_ACS_OFF (2 + 8) /* 2: Atomic Cycle Sequence */
151#define SSFC_ACS (0x1 << SSFC_ACS_OFF)
152#define SSFC_SPOP_OFF (3 + 8) /* 3: Sequence Prefix Opcode Pointer */
153#define SSFC_SPOP (0x1 << SSFC_SPOP_OFF)
154#define SSFC_COP_OFF (4 + 8) /* 4-6: Cycle Opcode Pointer */
155#define SSFC_COP (0x7 << SSFC_COP_OFF)
156 /* 7: reserved */
157#define SSFC_DBC_OFF (8 + 8) /* 8-13: Data Byte Count */
158#define SSFC_DBC (0x3f << SSFC_DBC_OFF)
159#define SSFC_DS_OFF (14 + 8) /* 14: Data Cycle */
160#define SSFC_DS (0x1 << SSFC_DS_OFF)
161#define SSFC_SME_OFF (15 + 8) /* 15: SPI SMI# Enable */
162#define SSFC_SME (0x1 << SSFC_SME_OFF)
163#define SSFC_SCF_OFF (16 + 8) /* 16-18: SPI Cycle Frequency */
164#define SSFC_SCF (0x7 << SSFC_SCF_OFF)
165#define SSFC_SCF_20MHZ 0x00000000
166#define SSFC_SCF_33MHZ 0x01000000
167 /* 19-23: reserved */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000168#define SSFC_RESERVED_MASK 0xf8008100
Stefan Reinauera9424d52008-06-27 16:28:34 +0000169
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000170#define ICH9_REG_PREOP 0x94 /* 16 Bits */
171#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
172#define ICH9_REG_OPMENU 0x98 /* 64 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000173
Stefan Tauner29c80832011-06-12 08:14:10 +0000174#define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */
175#define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */
176
Stefan Tauner1e146392011-09-15 23:52:55 +0000177#define ICH8_REG_VSCC 0xC1 /* 32 Bits Vendor Specific Component Capabilities */
178#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */
179#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */
180/* The individual fields of the VSCC registers are defined in the file
181 * ich_descriptors.h. The reason is that the same layout is also used in the
182 * flash descriptor to define the properties of the different flash chips
183 * supported. The BIOS (or the ME?) is responsible to populate the ICH registers
184 * with the information from the descriptor on startup depending on the actual
185 * chip(s) detected. */
186
Stefan Taunerbd649e42011-07-01 00:39:16 +0000187#define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */
188#define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */
189#define FPB_FPBA (0x1FFF << FPB_FPBA_OFF)
190
Dominik Geyerb46acba2008-05-16 12:55:55 +0000191// ICH9R SPI commands
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000192#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
193#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
194#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
195#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
Dominik Geyerb46acba2008-05-16 12:55:55 +0000196
Stefan Reinauera9424d52008-06-27 16:28:34 +0000197// ICH7 registers
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000198#define ICH7_REG_SPIS 0x00 /* 16 Bits */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000199#define SPIS_SCIP 0x0001
200#define SPIS_GRANT 0x0002
201#define SPIS_CDS 0x0004
202#define SPIS_FCERR 0x0008
203#define SPIS_RESERVED_MASK 0x7ff0
Stefan Reinauera9424d52008-06-27 16:28:34 +0000204
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000205/* VIA SPI is compatible with ICH7, but maxdata
206 to transfer is 16 bytes.
207
208 DATA byte count on ICH7 is 8:13, on VIA 8:11
209
210 bit 12 is port select CS0 CS1
211 bit 13 is FAST READ enable
212 bit 7 is used with fast read and one shot controls CS de-assert?
213*/
214
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000215#define ICH7_REG_SPIC 0x02 /* 16 Bits */
216#define SPIC_SCGO 0x0002
217#define SPIC_ACS 0x0004
218#define SPIC_SPOP 0x0008
219#define SPIC_DS 0x4000
Stefan Reinauera9424d52008-06-27 16:28:34 +0000220
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000221#define ICH7_REG_SPIA 0x04 /* 32 Bits */
222#define ICH7_REG_SPID0 0x08 /* 64 Bytes */
223#define ICH7_REG_PREOP 0x54 /* 16 Bits */
224#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
225#define ICH7_REG_OPMENU 0x58 /* 64 Bits */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000226
Nico Huber7590d1a2016-05-03 13:38:28 +0200227enum ich_access_protection {
228 NO_PROT = 0,
229 READ_PROT = 1,
230 WRITE_PROT = 2,
231 LOCKED = 3,
232};
233
FENG yu ningc05a2952008-12-08 18:16:58 +0000234/* ICH SPI configuration lock-down. May be set during chipset enabling. */
Michael Karchera4448d92010-07-22 18:04:15 +0000235static int ichspi_lock = 0;
FENG yu ningc05a2952008-12-08 18:16:58 +0000236
Stefan Taunera8d838d2011-11-06 23:51:09 +0000237static enum ich_chipset ich_generation = CHIPSET_ICH_UNKNOWN;
Nico Hubered098d62017-04-21 23:47:08 +0200238static uint32_t ichspi_bbar;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000239
Michael Karchera4448d92010-07-22 18:04:15 +0000240static void *ich_spibar = NULL;
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000241
Dominik Geyerb46acba2008-05-16 12:55:55 +0000242typedef struct _OPCODE {
243 uint8_t opcode; //This commands spi opcode
244 uint8_t spi_type; //This commands spi type
245 uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1
246} OPCODE;
247
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000248/* Suggested opcode definition:
Dominik Geyerb46acba2008-05-16 12:55:55 +0000249 * Preop 1: Write Enable
250 * Preop 2: Write Status register enable
251 *
252 * OP 0: Write address
253 * OP 1: Read Address
254 * OP 2: ERASE block
255 * OP 3: Read Status register
256 * OP 4: Read ID
257 * OP 5: Write Status register
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000258 * OP 6: chip private (read JEDEC id)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000259 * OP 7: Chip erase
260 */
261typedef struct _OPCODES {
262 uint8_t preop[2];
263 OPCODE opcode[8];
264} OPCODES;
265
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000266static OPCODES *curopcodes = NULL;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000267
268/* HW access functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000269static uint32_t REGREAD32(int X)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000270{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000271 return mmio_readl(ich_spibar + X);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000272}
273
Uwe Hermann09e04f72009-05-16 22:36:00 +0000274static uint16_t REGREAD16(int X)
Stefan Reinauera9424d52008-06-27 16:28:34 +0000275{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000276 return mmio_readw(ich_spibar + X);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000277}
278
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000279static uint16_t REGREAD8(int X)
280{
281 return mmio_readb(ich_spibar + X);
282}
283
Stefan Taunerccd92a12011-07-01 00:39:01 +0000284#define REGWRITE32(off, val) mmio_writel(val, ich_spibar+(off))
285#define REGWRITE16(off, val) mmio_writew(val, ich_spibar+(off))
286#define REGWRITE8(off, val) mmio_writeb(val, ich_spibar+(off))
Dominik Geyerb46acba2008-05-16 12:55:55 +0000287
Dominik Geyerb46acba2008-05-16 12:55:55 +0000288/* Common SPI functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000289static int find_opcode(OPCODES *op, uint8_t opcode);
290static int find_preop(OPCODES *op, uint8_t preop);
FENG yu ningf041e9b2008-12-15 02:32:11 +0000291static int generate_opcodes(OPCODES * op);
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000292static int program_opcodes(OPCODES *op, int enable_undo);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000293static int run_opcode(const struct flashctx *flash, OPCODE op, uint32_t offset,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000294 uint8_t datalength, uint8_t * data);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000295
FENG yu ningf041e9b2008-12-15 02:32:11 +0000296/* for pairing opcodes with their required preop */
297struct preop_opcode_pair {
298 uint8_t preop;
299 uint8_t opcode;
300};
301
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000302/* List of opcodes which need preopcodes and matching preopcodes. Unused. */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000303const struct preop_opcode_pair pops[] = {
FENG yu ningf041e9b2008-12-15 02:32:11 +0000304 {JEDEC_WREN, JEDEC_BYTE_PROGRAM},
305 {JEDEC_WREN, JEDEC_SE}, /* sector erase */
306 {JEDEC_WREN, JEDEC_BE_52}, /* block erase */
307 {JEDEC_WREN, JEDEC_BE_D8}, /* block erase */
308 {JEDEC_WREN, JEDEC_CE_60}, /* chip erase */
309 {JEDEC_WREN, JEDEC_CE_C7}, /* chip erase */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000310 /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */
311 {JEDEC_WREN, JEDEC_WRSR},
FENG yu ningf041e9b2008-12-15 02:32:11 +0000312 {JEDEC_EWSR, JEDEC_WRSR},
313 {0,}
314};
315
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000316/* Reasonable default configuration. Needs ad-hoc modifications if we
317 * encounter unlisted opcodes. Fun.
318 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000319static OPCODES O_ST_M25P = {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000320 {
321 JEDEC_WREN,
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000322 JEDEC_EWSR,
323 },
Dominik Geyerb46acba2008-05-16 12:55:55 +0000324 {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000325 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000326 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
David Hendricks15f539c2010-08-26 21:27:17 -0700327 {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000328 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
Carl-Daniel Hailfinger15aa7c62009-05-26 21:25:08 +0000329 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000330 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000331 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000332 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
333 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000334};
335
Helge Wagner738e2522010-10-05 22:06:05 +0000336/* List of opcodes with their corresponding spi_type
337 * It is used to reprogram the chipset OPCODE table on-the-fly if an opcode
338 * is needed which is currently not in the chipset OPCODE table
339 */
340static OPCODE POSSIBLE_OPCODES[] = {
341 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
342 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
343 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
344 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
345 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
346 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
347 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
348 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
349 {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Sector erase
350 {JEDEC_BE_52, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Block erase
351 {JEDEC_AAI_WORD_PROGRAM, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Auto Address Increment
352};
353
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000354static OPCODES O_EXISTING = {};
FENG yu ningc05a2952008-12-08 18:16:58 +0000355
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000356/* pretty printing functions */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000357static void prettyprint_opcodes(OPCODES *ops)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000358{
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000359 OPCODE oc;
360 const char *t;
361 const char *a;
362 uint8_t i;
363 static const char *const spi_type[4] = {
364 "read w/o addr",
365 "write w/o addr",
366 "read w/ addr",
367 "write w/ addr"
368 };
369 static const char *const atomic_type[3] = {
370 "none",
371 " 0 ",
372 " 1 "
373 };
374
375 if (ops == NULL)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000376 return;
377
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000378 msg_pdbg2(" OP Type Pre-OP\n");
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000379 for (i = 0; i < 8; i++) {
380 oc = ops->opcode[i];
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000381 t = (oc.spi_type > 3) ? "invalid" : spi_type[oc.spi_type];
382 a = (oc.atomic > 2) ? "invalid" : atomic_type[oc.atomic];
383 msg_pdbg2("op[%d]: 0x%02x, %s, %s\n", i, oc.opcode, t, a);
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000384 }
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000385 msg_pdbg2("Pre-OP 0: 0x%02x, Pre-OP 1: 0x%02x\n", ops->preop[0],
386 ops->preop[1]);
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000387}
388
Nico Huberd54e4f42017-03-23 23:45:47 +0100389#define _pprint_reg(bit, mask, off, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & mask) >> off)
390#define pprint_reg(reg, bit, val, sep) _pprint_reg(bit, reg##_##bit, reg##_##bit##_OFF, val, sep)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000391
Stefan Tauner55206942011-06-11 09:53:22 +0000392static void prettyprint_ich9_reg_hsfs(uint16_t reg_val)
393{
394 msg_pdbg("HSFS: ");
395 pprint_reg(HSFS, FDONE, reg_val, ", ");
396 pprint_reg(HSFS, FCERR, reg_val, ", ");
397 pprint_reg(HSFS, AEL, reg_val, ", ");
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200398 switch (ich_generation) {
399 case CHIPSET_100_SERIES_SUNRISE_POINT:
400 case CHIPSET_C620_SERIES_LEWISBURG:
401 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200402 case CHIPSET_500_SERIES_TIGER_POINT:
Werner Zehe57d4e42022-01-03 09:44:29 +0100403 case CHIPSET_ELKHART_LAKE:
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200404 break;
405 default:
Nico Huberd54e4f42017-03-23 23:45:47 +0100406 pprint_reg(HSFS, BERASE, reg_val, ", ");
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200407 break;
Nico Huberd54e4f42017-03-23 23:45:47 +0100408 }
Stefan Tauner55206942011-06-11 09:53:22 +0000409 pprint_reg(HSFS, SCIP, reg_val, ", ");
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200410 switch (ich_generation) {
411 case CHIPSET_100_SERIES_SUNRISE_POINT:
412 case CHIPSET_C620_SERIES_LEWISBURG:
413 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200414 case CHIPSET_500_SERIES_TIGER_POINT:
Werner Zehe57d4e42022-01-03 09:44:29 +0100415 case CHIPSET_ELKHART_LAKE:
Nico Huberd54e4f42017-03-23 23:45:47 +0100416 pprint_reg(HSFS, PRR34_LOCKDN, reg_val, ", ");
417 pprint_reg(HSFS, WRSDIS, reg_val, ", ");
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200418 break;
419 default:
420 break;
Nico Huberd54e4f42017-03-23 23:45:47 +0100421 }
Stefan Tauner55206942011-06-11 09:53:22 +0000422 pprint_reg(HSFS, FDOPSS, reg_val, ", ");
423 pprint_reg(HSFS, FDV, reg_val, ", ");
424 pprint_reg(HSFS, FLOCKDN, reg_val, "\n");
425}
426
427static void prettyprint_ich9_reg_hsfc(uint16_t reg_val)
428{
429 msg_pdbg("HSFC: ");
430 pprint_reg(HSFC, FGO, reg_val, ", ");
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200431 switch (ich_generation) {
432 case CHIPSET_100_SERIES_SUNRISE_POINT:
433 case CHIPSET_C620_SERIES_LEWISBURG:
434 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200435 case CHIPSET_500_SERIES_TIGER_POINT:
Werner Zehe57d4e42022-01-03 09:44:29 +0100436 case CHIPSET_ELKHART_LAKE:
Nico Huberd54e4f42017-03-23 23:45:47 +0100437 _pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", ");
438 pprint_reg(HSFC, WET, reg_val, ", ");
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200439 break;
440 default:
441 pprint_reg(HSFC, FCYCLE, reg_val, ", ");
442 break;
Nico Huberd54e4f42017-03-23 23:45:47 +0100443 }
Stefan Tauner55206942011-06-11 09:53:22 +0000444 pprint_reg(HSFC, FDBC, reg_val, ", ");
445 pprint_reg(HSFC, SME, reg_val, "\n");
446}
447
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000448static void prettyprint_ich9_reg_ssfs(uint32_t reg_val)
449{
450 msg_pdbg("SSFS: ");
451 pprint_reg(SSFS, SCIP, reg_val, ", ");
452 pprint_reg(SSFS, FDONE, reg_val, ", ");
453 pprint_reg(SSFS, FCERR, reg_val, ", ");
454 pprint_reg(SSFS, AEL, reg_val, "\n");
455}
456
457static void prettyprint_ich9_reg_ssfc(uint32_t reg_val)
458{
459 msg_pdbg("SSFC: ");
460 pprint_reg(SSFC, SCGO, reg_val, ", ");
461 pprint_reg(SSFC, ACS, reg_val, ", ");
462 pprint_reg(SSFC, SPOP, reg_val, ", ");
463 pprint_reg(SSFC, COP, reg_val, ", ");
464 pprint_reg(SSFC, DBC, reg_val, ", ");
465 pprint_reg(SSFC, SME, reg_val, ", ");
466 pprint_reg(SSFC, SCF, reg_val, "\n");
467}
468
Nico Huberd54e4f42017-03-23 23:45:47 +0100469static void prettyprint_pch100_reg_dlock(const uint32_t reg_val)
470{
471 msg_pdbg("DLOCK: ");
472 pprint_reg(DLOCK, BMWAG_LOCKDN, reg_val, ", ");
473 pprint_reg(DLOCK, BMRAG_LOCKDN, reg_val, ", ");
474 pprint_reg(DLOCK, SBMWAG_LOCKDN, reg_val, ", ");
475 pprint_reg(DLOCK, SBMRAG_LOCKDN, reg_val, ",\n ");
476 pprint_reg(DLOCK, PR0_LOCKDN, reg_val, ", ");
477 pprint_reg(DLOCK, PR1_LOCKDN, reg_val, ", ");
478 pprint_reg(DLOCK, PR2_LOCKDN, reg_val, ", ");
479 pprint_reg(DLOCK, PR3_LOCKDN, reg_val, ", ");
480 pprint_reg(DLOCK, PR4_LOCKDN, reg_val, ",\n ");
481 pprint_reg(DLOCK, SSEQ_LOCKDN, reg_val, "\n");
482}
483
484static struct {
485 size_t reg_ssfsc;
486 size_t reg_preop;
487 size_t reg_optype;
488 size_t reg_opmenu;
489} swseq_data;
490
Helge Wagner738e2522010-10-05 22:06:05 +0000491static uint8_t lookup_spi_type(uint8_t opcode)
492{
Nico Huber519be662018-12-23 20:03:35 +0100493 unsigned int a;
Helge Wagner738e2522010-10-05 22:06:05 +0000494
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000495 for (a = 0; a < ARRAY_SIZE(POSSIBLE_OPCODES); a++) {
Helge Wagner738e2522010-10-05 22:06:05 +0000496 if (POSSIBLE_OPCODES[a].opcode == opcode)
497 return POSSIBLE_OPCODES[a].spi_type;
498 }
499
500 return 0xFF;
501}
502
503static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt)
504{
505 uint8_t spi_type;
506
507 spi_type = lookup_spi_type(opcode);
508 if (spi_type > 3) {
509 /* Try to guess spi type from read/write sizes.
510 * The following valid writecnt/readcnt combinations exist:
511 * writecnt = 4, readcnt >= 0
512 * writecnt = 1, readcnt >= 0
513 * writecnt >= 4, readcnt = 0
514 * writecnt >= 1, readcnt = 0
515 * writecnt >= 1 is guaranteed for all commands.
516 */
517 if (readcnt == 0)
518 /* if readcnt=0 and writecount >= 4, we don't know if it is WRITE_NO_ADDRESS
519 * or WRITE_WITH_ADDRESS. But if we use WRITE_NO_ADDRESS and the first 3 data
520 * bytes are actual the address, they go to the bus anyhow
521 */
522 spi_type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
523 else if (writecnt == 1) // and readcnt is > 0
524 spi_type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
525 else if (writecnt == 4) // and readcnt is > 0
526 spi_type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
Stefan Taunerdc704ed2012-05-06 15:11:26 +0000527 else // we have an invalid case
528 return SPI_INVALID_LENGTH;
Helge Wagner738e2522010-10-05 22:06:05 +0000529 }
Stefan Taunerdc704ed2012-05-06 15:11:26 +0000530 int oppos = 2; // use original JEDEC_BE_D8 offset
531 curopcodes->opcode[oppos].opcode = opcode;
532 curopcodes->opcode[oppos].spi_type = spi_type;
533 program_opcodes(curopcodes, 0);
534 oppos = find_opcode(curopcodes, opcode);
Stefan Taunerd94d25d2012-07-28 03:17:15 +0000535 msg_pdbg2("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos);
Stefan Taunerdc704ed2012-05-06 15:11:26 +0000536 return oppos;
Helge Wagner738e2522010-10-05 22:06:05 +0000537}
538
Uwe Hermann09e04f72009-05-16 22:36:00 +0000539static int find_opcode(OPCODES *op, uint8_t opcode)
FENG yu ningc05a2952008-12-08 18:16:58 +0000540{
541 int a;
542
Stefan Tauner50e7c602011-11-08 10:55:54 +0000543 if (op == NULL) {
544 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
545 return -1;
546 }
547
FENG yu ningc05a2952008-12-08 18:16:58 +0000548 for (a = 0; a < 8; a++) {
549 if (op->opcode[a].opcode == opcode)
550 return a;
551 }
552
553 return -1;
554}
555
Uwe Hermann09e04f72009-05-16 22:36:00 +0000556static int find_preop(OPCODES *op, uint8_t preop)
FENG yu ningc05a2952008-12-08 18:16:58 +0000557{
558 int a;
559
Stefan Tauner50e7c602011-11-08 10:55:54 +0000560 if (op == NULL) {
561 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
562 return -1;
563 }
564
FENG yu ningc05a2952008-12-08 18:16:58 +0000565 for (a = 0; a < 2; a++) {
566 if (op->preop[a] == preop)
567 return a;
568 }
569
570 return -1;
571}
572
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000573/* Create a struct OPCODES based on what we find in the locked down chipset. */
FENG yu ningf041e9b2008-12-15 02:32:11 +0000574static int generate_opcodes(OPCODES * op)
FENG yu ningc05a2952008-12-08 18:16:58 +0000575{
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000576 int a;
FENG yu ningc05a2952008-12-08 18:16:58 +0000577 uint16_t preop, optype;
578 uint32_t opmenu[2];
FENG yu ningc05a2952008-12-08 18:16:58 +0000579
580 if (op == NULL) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000581 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
FENG yu ningc05a2952008-12-08 18:16:58 +0000582 return -1;
583 }
584
Stefan Taunera8d838d2011-11-06 23:51:09 +0000585 switch (ich_generation) {
586 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000587 case CHIPSET_TUNNEL_CREEK:
588 case CHIPSET_CENTERTON:
FENG yu ningc05a2952008-12-08 18:16:58 +0000589 preop = REGREAD16(ICH7_REG_PREOP);
590 optype = REGREAD16(ICH7_REG_OPTYPE);
591 opmenu[0] = REGREAD32(ICH7_REG_OPMENU);
592 opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4);
593 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000594 case CHIPSET_ICH8:
595 default: /* Future version might behave the same */
Nico Huberd54e4f42017-03-23 23:45:47 +0100596 preop = REGREAD16(swseq_data.reg_preop);
597 optype = REGREAD16(swseq_data.reg_optype);
598 opmenu[0] = REGREAD32(swseq_data.reg_opmenu);
599 opmenu[1] = REGREAD32(swseq_data.reg_opmenu + 4);
FENG yu ningc05a2952008-12-08 18:16:58 +0000600 break;
FENG yu ningc05a2952008-12-08 18:16:58 +0000601 }
602
603 op->preop[0] = (uint8_t) preop;
604 op->preop[1] = (uint8_t) (preop >> 8);
605
606 for (a = 0; a < 8; a++) {
607 op->opcode[a].spi_type = (uint8_t) (optype & 0x3);
608 optype >>= 2;
609 }
610
611 for (a = 0; a < 4; a++) {
612 op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff);
613 opmenu[0] >>= 8;
614 }
615
616 for (a = 4; a < 8; a++) {
617 op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff);
618 opmenu[1] >>= 8;
619 }
620
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000621 /* No preopcodes used by default. */
622 for (a = 0; a < 8; a++)
FENG yu ningc05a2952008-12-08 18:16:58 +0000623 op->opcode[a].atomic = 0;
624
FENG yu ningc05a2952008-12-08 18:16:58 +0000625 return 0;
626}
627
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000628static int program_opcodes(OPCODES *op, int enable_undo)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000629{
630 uint8_t a;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000631 uint16_t preop, optype;
632 uint32_t opmenu[2];
Dominik Geyerb46acba2008-05-16 12:55:55 +0000633
634 /* Program Prefix Opcodes */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000635 /* 0:7 Prefix Opcode 1 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000636 preop = (op->preop[0]);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000637 /* 8:16 Prefix Opcode 2 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000638 preop |= ((uint16_t) op->preop[1]) << 8;
Uwe Hermann394131e2008-10-18 21:14:13 +0000639
Stefan Reinauera9424d52008-06-27 16:28:34 +0000640 /* Program Opcode Types 0 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000641 optype = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000642 for (a = 0; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000643 optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000644 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000645
Stefan Reinauera9424d52008-06-27 16:28:34 +0000646 /* Program Allowable Opcodes 0 - 3 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000647 opmenu[0] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000648 for (a = 0; a < 4; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000649 opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000650 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000651
Stefan Tauner92d6a862013-10-25 00:33:37 +0000652 /* Program Allowable Opcodes 4 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000653 opmenu[1] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000654 for (a = 4; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000655 opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000656 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000657
Stefan Taunerd94d25d2012-07-28 03:17:15 +0000658 msg_pdbg2("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]);
Stefan Taunera8d838d2011-11-06 23:51:09 +0000659 switch (ich_generation) {
660 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000661 case CHIPSET_TUNNEL_CREEK:
662 case CHIPSET_CENTERTON:
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000663 /* Register undo only for enable_undo=1, i.e. first call. */
664 if (enable_undo) {
665 rmmio_valw(ich_spibar + ICH7_REG_PREOP);
666 rmmio_valw(ich_spibar + ICH7_REG_OPTYPE);
667 rmmio_vall(ich_spibar + ICH7_REG_OPMENU);
668 rmmio_vall(ich_spibar + ICH7_REG_OPMENU + 4);
669 }
670 mmio_writew(preop, ich_spibar + ICH7_REG_PREOP);
671 mmio_writew(optype, ich_spibar + ICH7_REG_OPTYPE);
672 mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU);
673 mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000674 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000675 case CHIPSET_ICH8:
676 default: /* Future version might behave the same */
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000677 /* Register undo only for enable_undo=1, i.e. first call. */
678 if (enable_undo) {
Nico Huberd54e4f42017-03-23 23:45:47 +0100679 rmmio_valw(ich_spibar + swseq_data.reg_preop);
680 rmmio_valw(ich_spibar + swseq_data.reg_optype);
681 rmmio_vall(ich_spibar + swseq_data.reg_opmenu);
682 rmmio_vall(ich_spibar + swseq_data.reg_opmenu + 4);
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000683 }
Nico Huberd54e4f42017-03-23 23:45:47 +0100684 mmio_writew(preop, ich_spibar + swseq_data.reg_preop);
685 mmio_writew(optype, ich_spibar + swseq_data.reg_optype);
686 mmio_writel(opmenu[0], ich_spibar + swseq_data.reg_opmenu);
687 mmio_writel(opmenu[1], ich_spibar + swseq_data.reg_opmenu + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000688 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000689 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000690
691 return 0;
692}
693
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000694/*
Stefan Tauner50e7c602011-11-08 10:55:54 +0000695 * Returns -1 if at least one mandatory opcode is inaccessible, 0 otherwise.
696 * FIXME: this should also check for
697 * - at least one probing opcode (RDID (incl. AT25F variants?), REMS, RES?)
698 * - at least one erasing opcode (lots.)
699 * - at least one program opcode (BYTE_PROGRAM, AAI_WORD_PROGRAM, ...?)
700 * - necessary preops? (EWSR, WREN, ...?)
701 */
Richard Hughes93e16252018-12-19 11:54:47 +0000702static int ich_missing_opcodes(void)
Stefan Tauner50e7c602011-11-08 10:55:54 +0000703{
704 uint8_t ops[] = {
705 JEDEC_READ,
706 JEDEC_RDSR,
707 0
708 };
709 int i = 0;
710 while (ops[i] != 0) {
711 msg_pspew("checking for opcode 0x%02x\n", ops[i]);
712 if (find_opcode(curopcodes, ops[i]) == -1)
713 return -1;
714 i++;
715 }
716 return 0;
717}
718
719/*
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000720 * Try to set BBAR (BIOS Base Address Register), but read back the value in case
721 * it didn't stick.
722 */
Stefan Taunera8d838d2011-11-06 23:51:09 +0000723static void ich_set_bbar(uint32_t min_addr)
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000724{
Stefan Taunere27b2d42011-07-01 00:39:09 +0000725 int bbar_off;
Stefan Tauner7783f312011-09-17 21:21:42 +0000726 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +0000727 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000728 case CHIPSET_TUNNEL_CREEK:
729 case CHIPSET_CENTERTON:
Stefan Taunere27b2d42011-07-01 00:39:09 +0000730 bbar_off = 0x50;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000731 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000732 case CHIPSET_ICH8:
Duncan Laurie4095ed72014-08-20 15:39:32 +0000733 case CHIPSET_BAYTRAIL:
734 msg_pdbg("BBAR offset is unknown!\n");
Stefan Tauner7783f312011-09-17 21:21:42 +0000735 return;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000736 case CHIPSET_ICH9:
Stefan Tauner7783f312011-09-17 21:21:42 +0000737 default: /* Future version might behave the same */
Stefan Taunere27b2d42011-07-01 00:39:09 +0000738 bbar_off = ICH9_REG_BBAR;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000739 break;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000740 }
Elyes HAOUAS124ef382018-03-27 12:15:09 +0200741
Stefan Taunere27b2d42011-07-01 00:39:09 +0000742 ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK;
743 if (ichspi_bbar) {
744 msg_pdbg("Reserved bits in BBAR not zero: 0x%08x\n",
745 ichspi_bbar);
746 }
747 min_addr &= BBAR_MASK;
748 ichspi_bbar |= min_addr;
749 rmmio_writel(ichspi_bbar, ich_spibar + bbar_off);
750 ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & BBAR_MASK;
751
752 /* We don't have any option except complaining. And if the write
753 * failed, the restore will fail as well, so no problem there.
754 */
755 if (ichspi_bbar != min_addr)
Stefan Tauner7783f312011-09-17 21:21:42 +0000756 msg_perr("Setting BBAR to 0x%08x failed! New value: 0x%08x.\n",
757 min_addr, ichspi_bbar);
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000758}
759
Stefan Tauner8b391b82011-08-09 01:49:34 +0000760/* Read len bytes from the fdata/spid register into the data array.
761 *
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000762 * Note that using len > flash->mst->spi.max_data_read will return garbage or
Stefan Tauner8b391b82011-08-09 01:49:34 +0000763 * may even crash.
764 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000765static void ich_read_data(uint8_t *data, int len, int reg0_off)
Elyes HAOUAS124ef382018-03-27 12:15:09 +0200766{
Stefan Tauner8b391b82011-08-09 01:49:34 +0000767 int i;
768 uint32_t temp32 = 0;
769
770 for (i = 0; i < len; i++) {
771 if ((i % 4) == 0)
772 temp32 = REGREAD32(reg0_off + i);
773
774 data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
775 }
776}
777
778/* Fill len bytes from the data array into the fdata/spid registers.
779 *
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000780 * Note that using len > flash->mst->spi.max_data_write will trash the registers
Stefan Tauner8b391b82011-08-09 01:49:34 +0000781 * following the data registers.
782 */
783static void ich_fill_data(const uint8_t *data, int len, int reg0_off)
784{
785 uint32_t temp32 = 0;
786 int i;
787
788 if (len <= 0)
789 return;
790
791 for (i = 0; i < len; i++) {
792 if ((i % 4) == 0)
793 temp32 = 0;
794
795 temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
796
797 if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
798 REGWRITE32(reg0_off + (i - (i % 4)), temp32);
799 }
800 i--;
801 if ((i % 4) != 3) /* Write remaining data to regs. */
802 REGWRITE32(reg0_off + (i - (i % 4)), temp32);
803}
804
FENG yu ningf041e9b2008-12-15 02:32:11 +0000805/* This function generates OPCODES from or programs OPCODES to ICH according to
806 * the chipset's SPI configuration lock.
FENG yu ningc05a2952008-12-08 18:16:58 +0000807 *
FENG yu ningf041e9b2008-12-15 02:32:11 +0000808 * It should be called before ICH sends any spi command.
FENG yu ningc05a2952008-12-08 18:16:58 +0000809 */
Michael Karchera4448d92010-07-22 18:04:15 +0000810static int ich_init_opcodes(void)
FENG yu ningc05a2952008-12-08 18:16:58 +0000811{
812 int rc = 0;
813 OPCODES *curopcodes_done;
814
815 if (curopcodes)
816 return 0;
817
818 if (ichspi_lock) {
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000819 msg_pdbg("Reading OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000820 curopcodes_done = &O_EXISTING;
FENG yu ningf041e9b2008-12-15 02:32:11 +0000821 rc = generate_opcodes(curopcodes_done);
FENG yu ningc05a2952008-12-08 18:16:58 +0000822 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000823 msg_pdbg("Programming OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000824 curopcodes_done = &O_ST_M25P;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000825 rc = program_opcodes(curopcodes_done, 1);
FENG yu ningc05a2952008-12-08 18:16:58 +0000826 }
827
828 if (rc) {
829 curopcodes = NULL;
Sean Nelson316a29f2010-05-07 20:09:04 +0000830 msg_perr("failed\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000831 return 1;
832 } else {
833 curopcodes = curopcodes_done;
Sean Nelson316a29f2010-05-07 20:09:04 +0000834 msg_pdbg("done\n");
Stefan Tauner8b391b82011-08-09 01:49:34 +0000835 prettyprint_opcodes(curopcodes);
FENG yu ningc05a2952008-12-08 18:16:58 +0000836 return 0;
837 }
838}
839
Stefan Reinauer43119562008-11-02 19:51:50 +0000840static int ich7_run_opcode(OPCODE op, uint32_t offset,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000841 uint8_t datalength, uint8_t * data, int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000842{
843 int write_cmd = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000844 int timeout;
Stefan Tauner8b391b82011-08-09 01:49:34 +0000845 uint32_t temp32;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000846 uint16_t temp16;
Stefan Reinauer43119562008-11-02 19:51:50 +0000847 uint64_t opmenu;
848 int opcode_index;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000849
850 /* Is it a write command? */
851 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
852 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
853 write_cmd = 1;
854 }
855
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000856 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
857 while ((REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) && --timeout) {
858 programmer_delay(10);
859 }
860 if (!timeout) {
861 msg_perr("Error: SCIP never cleared!\n");
862 return 1;
863 }
864
Stefan Tauner10b3e222011-07-01 00:39:23 +0000865 /* Program offset in flash into SPIA while preserving reserved bits. */
866 temp32 = REGREAD32(ICH7_REG_SPIA) & ~0x00FFFFFF;
867 REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000868
Stefan Tauner10b3e222011-07-01 00:39:23 +0000869 /* Program data into SPID0 to N */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000870 if (write_cmd && (datalength != 0))
871 ich_fill_data(data, datalength, ICH7_REG_SPID0);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000872
873 /* Assemble SPIS */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000874 temp16 = REGREAD16(ICH7_REG_SPIS);
875 /* keep reserved bits */
876 temp16 &= SPIS_RESERVED_MASK;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000877 /* clear error status registers */
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000878 temp16 |= (SPIS_CDS | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000879 REGWRITE16(ICH7_REG_SPIS, temp16);
880
881 /* Assemble SPIC */
882 temp16 = 0;
883
884 if (datalength != 0) {
885 temp16 |= SPIC_DS;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000886 temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000887 }
888
889 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000890 opmenu = REGREAD32(ICH7_REG_OPMENU);
891 opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32;
892
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000893 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
894 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000895 break;
896 }
897 opmenu >>= 8;
898 }
899 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000900 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000901 return 1;
902 }
903 temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000904
Michael Karcher136125a2011-04-29 22:11:36 +0000905 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
906 /* Handle Atomic. Atomic commands include three steps:
907 - sending the preop (mainly EWSR or WREN)
908 - sending the main command
909 - waiting for the busy bit (WIP) to be cleared
910 This means the timeout must be sufficient for chip erase
911 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000912 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000913 switch (op.atomic) {
914 case 2:
915 /* Select second preop. */
916 temp16 |= SPIC_SPOP;
Richard Hughesdb7482b2018-12-19 12:04:30 +0000917 /* Fall through. */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000918 case 1:
919 /* Atomic command (preop+op) */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000920 temp16 |= SPIC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +0000921 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000922 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000923 }
924
925 /* Start */
926 temp16 |= SPIC_SCGO;
927
928 /* write it */
929 REGWRITE16(ICH7_REG_SPIC, temp16);
930
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000931 /* Wait for Cycle Done Status or Flash Cycle Error. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000932 while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) &&
933 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000934 programmer_delay(10);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000935 }
936 if (!timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000937 msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n",
938 REGREAD16(ICH7_REG_SPIS));
939 return 1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000940 }
941
Sean Nelson316a29f2010-05-07 20:09:04 +0000942 /* FIXME: make sure we do not needlessly cause transaction errors. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000943 temp16 = REGREAD16(ICH7_REG_SPIS);
944 if (temp16 & SPIS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +0000945 msg_perr("Transaction error!\n");
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000946 /* keep reserved bits */
947 temp16 &= SPIS_RESERVED_MASK;
948 REGWRITE16(ICH7_REG_SPIS, temp16 | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000949 return 1;
950 }
951
Stefan Tauner8b391b82011-08-09 01:49:34 +0000952 if ((!write_cmd) && (datalength != 0))
953 ich_read_data(data, datalength, ICH7_REG_SPID0);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000954
955 return 0;
956}
957
Stefan Reinauer43119562008-11-02 19:51:50 +0000958static int ich9_run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000959 uint8_t datalength, uint8_t * data)
960{
961 int write_cmd = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000962 int timeout;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000963 uint32_t temp32;
Stefan Reinauer43119562008-11-02 19:51:50 +0000964 uint64_t opmenu;
965 int opcode_index;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000966
967 /* Is it a write command? */
968 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
969 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
970 write_cmd = 1;
971 }
972
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000973 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
Nico Huberd54e4f42017-03-23 23:45:47 +0100974 while ((REGREAD8(swseq_data.reg_ssfsc) & SSFS_SCIP) && --timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000975 programmer_delay(10);
976 }
977 if (!timeout) {
978 msg_perr("Error: SCIP never cleared!\n");
979 return 1;
980 }
981
Stefan Tauner10b3e222011-07-01 00:39:23 +0000982 /* Program offset in flash into FADDR while preserve the reserved bits
983 * and clearing the 25. address bit which is only useable in hwseq. */
984 temp32 = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF;
985 REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000986
987 /* Program data into FDATA0 to N */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000988 if (write_cmd && (datalength != 0))
989 ich_fill_data(data, datalength, ICH9_REG_FDATA0);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000990
991 /* Assemble SSFS + SSFC */
Nico Huberd54e4f42017-03-23 23:45:47 +0100992 temp32 = REGREAD32(swseq_data.reg_ssfsc);
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000993 /* Keep reserved bits only */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000994 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000995 /* Clear cycle done and cycle error status registers */
996 temp32 |= (SSFS_FDONE | SSFS_FCERR);
Nico Huberd54e4f42017-03-23 23:45:47 +0100997 REGWRITE32(swseq_data.reg_ssfsc, temp32);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000998
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000999 /* Use 20 MHz */
Dominik Geyerb46acba2008-05-16 12:55:55 +00001000 temp32 |= SSFC_SCF_20MHZ;
1001
Stefan Taunerc0aaf952011-05-19 02:58:17 +00001002 /* Set data byte count (DBC) and data cycle bit (DS) */
Dominik Geyerb46acba2008-05-16 12:55:55 +00001003 if (datalength != 0) {
1004 uint32_t datatemp;
1005 temp32 |= SSFC_DS;
Stefan Tauner0c1ec452011-06-11 09:53:09 +00001006 datatemp = ((((uint32_t)datalength - 1) << SSFC_DBC_OFF) &
1007 SSFC_DBC);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001008 temp32 |= datatemp;
1009 }
1010
1011 /* Select opcode */
Nico Huber8b2152d2017-08-31 13:18:49 +02001012 opmenu = REGREAD32(swseq_data.reg_opmenu);
1013 opmenu |= ((uint64_t)REGREAD32(swseq_data.reg_opmenu + 4)) << 32;
Stefan Reinauer43119562008-11-02 19:51:50 +00001014
Uwe Hermann7b2969b2009-04-15 10:52:49 +00001015 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
1016 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +00001017 break;
1018 }
1019 opmenu >>= 8;
1020 }
1021 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001022 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +00001023 return 1;
1024 }
1025 temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001026
Michael Karcher136125a2011-04-29 22:11:36 +00001027 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
1028 /* Handle Atomic. Atomic commands include three steps:
1029 - sending the preop (mainly EWSR or WREN)
1030 - sending the main command
1031 - waiting for the busy bit (WIP) to be cleared
1032 This means the timeout must be sufficient for chip erase
1033 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +00001034 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001035 switch (op.atomic) {
1036 case 2:
1037 /* Select second preop. */
1038 temp32 |= SSFC_SPOP;
Richard Hughesdb7482b2018-12-19 12:04:30 +00001039 /* Fall through. */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001040 case 1:
1041 /* Atomic command (preop+op) */
Dominik Geyerb46acba2008-05-16 12:55:55 +00001042 temp32 |= SSFC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +00001043 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001044 break;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001045 }
1046
1047 /* Start */
1048 temp32 |= SSFC_SCGO;
1049
1050 /* write it */
Nico Huberd54e4f42017-03-23 23:45:47 +01001051 REGWRITE32(swseq_data.reg_ssfsc, temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001052
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001053 /* Wait for Cycle Done Status or Flash Cycle Error. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001054 while (((REGREAD32(swseq_data.reg_ssfsc) & (SSFS_FDONE | SSFS_FCERR)) == 0) &&
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001055 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +00001056 programmer_delay(10);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +00001057 }
1058 if (!timeout) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001059 msg_perr("timeout, REG_SSFS=0x%08x\n",
1060 REGREAD32(swseq_data.reg_ssfsc));
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001061 return 1;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001062 }
1063
Sean Nelson316a29f2010-05-07 20:09:04 +00001064 /* FIXME make sure we do not needlessly cause transaction errors. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001065 temp32 = REGREAD32(swseq_data.reg_ssfsc);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001066 if (temp32 & SSFS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +00001067 msg_perr("Transaction error!\n");
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001068 prettyprint_ich9_reg_ssfs(temp32);
1069 prettyprint_ich9_reg_ssfc(temp32);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001070 /* keep reserved bits */
1071 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
1072 /* Clear the transaction error. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001073 REGWRITE32(swseq_data.reg_ssfsc, temp32 | SSFS_FCERR);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001074 return 1;
1075 }
1076
Stefan Tauner8b391b82011-08-09 01:49:34 +00001077 if ((!write_cmd) && (datalength != 0))
1078 ich_read_data(data, datalength, ICH9_REG_FDATA0);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001079
1080 return 0;
1081}
1082
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001083static int run_opcode(const struct flashctx *flash, OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +00001084 uint8_t datalength, uint8_t * data)
1085{
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001086 /* max_data_read == max_data_write for all Intel/VIA SPI masters */
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001087 uint8_t maxlength = flash->mst->spi.max_data_read;
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001088
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +00001089 if (ich_generation == CHIPSET_ICH_UNKNOWN) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001090 msg_perr("%s: unsupported chipset\n", __func__);
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001091 return -1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +00001092 }
Stefan Reinauera9424d52008-06-27 16:28:34 +00001093
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001094 if (datalength > maxlength) {
1095 msg_perr("%s: Internal command size error for "
1096 "opcode 0x%02x, got datalength=%i, want <=%i\n",
1097 __func__, op.opcode, datalength, maxlength);
1098 return SPI_INVALID_LENGTH;
1099 }
1100
Stefan Taunera8d838d2011-11-06 23:51:09 +00001101 switch (ich_generation) {
1102 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +00001103 case CHIPSET_TUNNEL_CREEK:
1104 case CHIPSET_CENTERTON:
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001105 return ich7_run_opcode(op, offset, datalength, data, maxlength);
Stefan Taunera8d838d2011-11-06 23:51:09 +00001106 case CHIPSET_ICH8:
1107 default: /* Future version might behave the same */
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001108 return ich9_run_opcode(op, offset, datalength, data);
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001109 }
Stefan Reinauera9424d52008-06-27 16:28:34 +00001110}
1111
Edward O'Callaghan5eca4272020-04-12 17:27:53 +10001112static int ich_spi_send_command(const struct flashctx *flash, unsigned int writecnt,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001113 unsigned int readcnt,
1114 const unsigned char *writearr,
1115 unsigned char *readarr)
Dominik Geyerb46acba2008-05-16 12:55:55 +00001116{
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001117 int result;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001118 int opcode_index = -1;
1119 const unsigned char cmd = *writearr;
1120 OPCODE *opcode;
1121 uint32_t addr = 0;
1122 uint8_t *data;
1123 int count;
1124
Dominik Geyerb46acba2008-05-16 12:55:55 +00001125 /* find cmd in opcodes-table */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001126 opcode_index = find_opcode(curopcodes, cmd);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001127 if (opcode_index == -1) {
Helge Wagner738e2522010-10-05 22:06:05 +00001128 if (!ichspi_lock)
1129 opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt);
Stefan Taunerdc704ed2012-05-06 15:11:26 +00001130 if (opcode_index == SPI_INVALID_LENGTH) {
1131 msg_pdbg("OPCODE 0x%02x has unsupported length, will not execute.\n", cmd);
1132 return SPI_INVALID_LENGTH;
1133 } else if (opcode_index == -1) {
Stefan Tauner355cbfd2011-05-28 02:37:14 +00001134 msg_pdbg("Invalid OPCODE 0x%02x, will not execute.\n",
1135 cmd);
Helge Wagner738e2522010-10-05 22:06:05 +00001136 return SPI_INVALID_OPCODE;
1137 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001138 }
1139
1140 opcode = &(curopcodes->opcode[opcode_index]);
1141
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001142 /* The following valid writecnt/readcnt combinations exist:
1143 * writecnt = 4, readcnt >= 0
1144 * writecnt = 1, readcnt >= 0
1145 * writecnt >= 4, readcnt = 0
1146 * writecnt >= 1, readcnt = 0
1147 * writecnt >= 1 is guaranteed for all commands.
1148 */
1149 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) &&
1150 (writecnt != 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001151 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001152 "0x%02x, got writecnt=%i, want =4\n", __func__, cmd,
1153 writecnt);
1154 return SPI_INVALID_LENGTH;
1155 }
1156 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) &&
1157 (writecnt != 1)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001158 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001159 "0x%02x, got writecnt=%i, want =1\n", __func__, cmd,
1160 writecnt);
1161 return SPI_INVALID_LENGTH;
1162 }
1163 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) &&
1164 (writecnt < 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001165 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001166 "0x%02x, got writecnt=%i, want >=4\n", __func__, cmd,
1167 writecnt);
1168 return SPI_INVALID_LENGTH;
1169 }
1170 if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1171 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) &&
1172 (readcnt)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001173 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001174 "0x%02x, got readcnt=%i, want =0\n", __func__, cmd,
1175 readcnt);
1176 return SPI_INVALID_LENGTH;
1177 }
1178
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001179 /* Translate read/write array/count.
1180 * The maximum data length is identical for the maximum read length and
1181 * for the maximum write length excluding opcode and address. Opcode and
1182 * address are stored in separate registers, not in the data registers
1183 * and are thus not counted towards data length. The only exception
1184 * applies if the opcode definition (un)intentionally classifies said
1185 * opcode incorrectly as non-address opcode or vice versa. */
Dominik Geyerb46acba2008-05-16 12:55:55 +00001186 if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001187 data = (uint8_t *) (writearr + 1);
1188 count = writecnt - 1;
1189 } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
1190 data = (uint8_t *) (writearr + 4);
1191 count = writecnt - 4;
1192 } else {
1193 data = (uint8_t *) readarr;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001194 count = readcnt;
1195 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001196
Nico Hubered098d62017-04-21 23:47:08 +02001197 /* if opcode-type requires an address */
1198 if (cmd == JEDEC_REMS || cmd == JEDEC_RES) {
1199 addr = ichspi_bbar;
1200 } else if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS ||
1201 opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
1202 /* BBAR may cut part of the chip off at the lower end. */
1203 const uint32_t valid_base = ichspi_bbar & ((flash->chip->total_size * 1024) - 1);
1204 const uint32_t addr_offset = ichspi_bbar - valid_base;
1205 /* Highest address we can program is (2^24 - 1). */
1206 const uint32_t valid_end = (1 << 24) - addr_offset;
1207
1208 addr = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
1209 const uint32_t addr_end = addr + count;
1210
1211 if (addr < valid_base ||
1212 addr_end < addr || /* integer overflow check */
1213 addr_end > valid_end) {
1214 msg_perr("%s: Addressed region 0x%06x-0x%06x not in allowed range 0x%06x-0x%06x\n",
1215 __func__, addr, addr_end - 1, valid_base, valid_end - 1);
1216 return SPI_INVALID_ADDRESS;
1217 }
1218 addr += addr_offset;
1219 }
1220
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001221 result = run_opcode(flash, *opcode, addr, count, data);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001222 if (result) {
Stefan Tauner8ed29342011-04-29 23:53:09 +00001223 msg_pdbg("Running OPCODE 0x%02x failed ", opcode->opcode);
1224 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1225 (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS)) {
1226 msg_pdbg("at address 0x%06x ", addr);
1227 }
1228 msg_pdbg("(payload length was %d).\n", count);
1229
1230 /* Print out the data array if it contains data to write.
1231 * Errors are detected before the received data is read back into
1232 * the array so it won't make sense to print it then. */
1233 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1234 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) {
1235 int i;
1236 msg_pspew("The data was:\n");
Stefan Taunerf382e352011-11-08 11:55:24 +00001237 for (i = 0; i < count; i++){
Stefan Tauner8ed29342011-04-29 23:53:09 +00001238 msg_pspew("%3d: 0x%02x\n", i, data[i]);
1239 }
1240 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001241 }
1242
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001243 return result;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001244}
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001245
Stefan Tauner50e7c602011-11-08 10:55:54 +00001246static struct hwseq_data {
1247 uint32_t size_comp0;
1248 uint32_t size_comp1;
Nico Huberd54e4f42017-03-23 23:45:47 +01001249 uint32_t addr_mask;
1250 bool only_4k;
1251 uint32_t hsfc_fcycle;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001252} hwseq_data;
1253
Nico Huberd54e4f42017-03-23 23:45:47 +01001254/* Sets FLA in FADDR to (addr & hwseq_data.addr_mask) without touching other bits. */
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001255static void ich_hwseq_set_addr(uint32_t addr)
1256{
Nico Huberd54e4f42017-03-23 23:45:47 +01001257 uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~hwseq_data.addr_mask;
1258 REGWRITE32(ICH9_REG_FADDR, (addr & hwseq_data.addr_mask) | addr_old);
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001259}
1260
1261/* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes
1262 * of the block containing this address. May return nonsense if the address is
1263 * not valid. The erase block size for a specific address depends on the flash
1264 * partition layout as specified by FPB and the partition properties as defined
1265 * by UVSCC and LVSCC respectively. An alternative to implement this method
1266 * would be by querying FPB and the respective VSCC register directly.
1267 */
1268static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr)
1269{
Elyes HAOUAS29e46d02019-06-09 17:38:25 +02001270 uint8_t enc_berase;
1271 static const uint32_t dec_berase[4] = {
1272 256,
1273 4 * 1024,
1274 8 * 1024,
1275 64 * 1024
1276 };
1277
Nico Huberd54e4f42017-03-23 23:45:47 +01001278 if (hwseq_data.only_4k) {
1279 return 4 * 1024;
Nico Huberd54e4f42017-03-23 23:45:47 +01001280 }
Elyes HAOUAS29e46d02019-06-09 17:38:25 +02001281
1282 ich_hwseq_set_addr(addr);
1283 enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >> HSFS_BERASE_OFF;
1284 return dec_berase[enc_berase];
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001285}
1286
1287/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
1288 Resets all error flags in HSFS.
1289 Returns 0 if the cycle completes successfully without errors within
1290 timeout us, 1 on errors. */
Subrata Banik7cb43952022-03-16 20:40:42 +05301291static int ich_hwseq_wait_for_cycle_complete(unsigned int len)
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001292{
Subrata Banik7cb43952022-03-16 20:40:42 +05301293 /*
1294 * The SPI bus may be busy due to performing operations from other masters, hence
1295 * introduce the long timeout of 30s to cover the worst case scenarios as well.
1296 */
1297 unsigned int timeout_us = 30 * 1000 * 1000;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001298 uint16_t hsfs;
1299 uint32_t addr;
1300
Subrata Banik7cb43952022-03-16 20:40:42 +05301301 timeout_us /= 8; /* scale timeout duration to counter */
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001302 while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) &
1303 (HSFS_FDONE | HSFS_FCERR)) == 0) &&
Subrata Banik7cb43952022-03-16 20:40:42 +05301304 --timeout_us) {
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001305 programmer_delay(8);
1306 }
1307 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
Subrata Banik7cb43952022-03-16 20:40:42 +05301308 if (!timeout_us) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001309 addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001310 msg_perr("Timeout error between offset 0x%08x and "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001311 "0x%08x (= 0x%08x + %d)!\n",
1312 addr, addr + len - 1, addr, len - 1);
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001313 prettyprint_ich9_reg_hsfs(hsfs);
1314 prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC));
1315 return 1;
1316 }
1317
1318 if (hsfs & HSFS_FCERR) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001319 addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001320 msg_perr("Transaction error between offset 0x%08x and "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001321 "0x%08x (= 0x%08x + %d)!\n",
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001322 addr, addr + len - 1, addr, len - 1);
1323 prettyprint_ich9_reg_hsfs(hsfs);
1324 prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC));
1325 return 1;
1326 }
1327 return 0;
1328}
Stefan Tauner50e7c602011-11-08 10:55:54 +00001329
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001330static int ich_hwseq_probe(struct flashctx *flash)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001331{
1332 uint32_t total_size, boundary;
1333 uint32_t erase_size_low, size_low, erase_size_high, size_high;
1334 struct block_eraser *eraser;
1335
1336 total_size = hwseq_data.size_comp0 + hwseq_data.size_comp1;
Stefan Tauner5c316f92015-02-08 21:57:52 +00001337 msg_cdbg("Hardware sequencing reports %d attached SPI flash chip",
Stefan Tauner50e7c602011-11-08 10:55:54 +00001338 (hwseq_data.size_comp1 != 0) ? 2 : 1);
1339 if (hwseq_data.size_comp1 != 0)
1340 msg_cdbg("s with a combined");
1341 else
1342 msg_cdbg(" with a");
1343 msg_cdbg(" density of %d kB.\n", total_size / 1024);
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001344 flash->chip->total_size = total_size / 1024;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001345
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001346 eraser = &(flash->chip->block_erasers[0]);
Nico Huberd54e4f42017-03-23 23:45:47 +01001347 if (!hwseq_data.only_4k)
1348 boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12;
1349 else
1350 boundary = 0;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001351 size_high = total_size - boundary;
1352 erase_size_high = ich_hwseq_get_erase_block_size(boundary);
1353
1354 if (boundary == 0) {
Stefan Tauner5c316f92015-02-08 21:57:52 +00001355 msg_cdbg2("There is only one partition containing the whole "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001356 "address space (0x%06x - 0x%06x).\n", 0, size_high-1);
1357 eraser->eraseblocks[0].size = erase_size_high;
1358 eraser->eraseblocks[0].count = size_high / erase_size_high;
Stefan Tauner5c316f92015-02-08 21:57:52 +00001359 msg_cdbg2("There are %d erase blocks with %d B each.\n",
Stefan Tauner50e7c602011-11-08 10:55:54 +00001360 size_high / erase_size_high, erase_size_high);
1361 } else {
Stefan Tauner5c316f92015-02-08 21:57:52 +00001362 msg_cdbg2("The flash address space (0x%06x - 0x%06x) is divided "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001363 "at address 0x%06x in two partitions.\n",
Stefan Taunerdbac46c2013-08-13 22:10:41 +00001364 0, total_size-1, boundary);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001365 size_low = total_size - size_high;
1366 erase_size_low = ich_hwseq_get_erase_block_size(0);
1367
1368 eraser->eraseblocks[0].size = erase_size_low;
1369 eraser->eraseblocks[0].count = size_low / erase_size_low;
1370 msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n",
1371 0, size_low-1);
1372 msg_cdbg("In that range are %d erase blocks with %d B each.\n",
1373 size_low / erase_size_low, erase_size_low);
1374
1375 eraser->eraseblocks[1].size = erase_size_high;
1376 eraser->eraseblocks[1].count = size_high / erase_size_high;
1377 msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n",
Stefan Taunerdbac46c2013-08-13 22:10:41 +00001378 boundary, total_size-1);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001379 msg_cdbg("In that range are %d erase blocks with %d B each.\n",
1380 size_high / erase_size_high, erase_size_high);
1381 }
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001382 flash->chip->tested = TEST_OK_PREW;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001383 return 1;
1384}
1385
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001386static int ich_hwseq_block_erase(struct flashctx *flash, unsigned int addr,
1387 unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001388{
1389 uint32_t erase_block;
1390 uint16_t hsfc;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001391
1392 erase_block = ich_hwseq_get_erase_block_size(addr);
1393 if (len != erase_block) {
1394 msg_cerr("Erase block size for address 0x%06x is %d B, "
1395 "but requested erase block size is %d B. "
1396 "Not erasing anything.\n", addr, erase_block, len);
1397 return -1;
1398 }
1399
1400 /* Although the hardware supports this (it would erase the whole block
1401 * containing the address) we play safe here. */
1402 if (addr % erase_block != 0) {
1403 msg_cerr("Erase address 0x%06x is not aligned to the erase "
1404 "block boundary (any multiple of %d). "
1405 "Not erasing anything.\n", addr, erase_block);
1406 return -1;
1407 }
1408
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001409 if (addr + len > flash->chip->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001410 msg_perr("Request to erase some inaccessible memory address(es)"
1411 " (addr=0x%x, len=%d). "
1412 "Not erasing anything.\n", addr, len);
1413 return -1;
1414 }
1415
1416 msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr);
Stefan Tauner7608d362014-08-05 23:28:47 +00001417 ich_hwseq_set_addr(addr);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001418
1419 /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
1420 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1421
1422 hsfc = REGREAD16(ICH9_REG_HSFC);
Nico Huberd54e4f42017-03-23 23:45:47 +01001423 hsfc &= ~hwseq_data.hsfc_fcycle; /* clear operation */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001424 hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
1425 hsfc |= HSFC_FGO; /* start */
1426 msg_pdbg("HSFC used for block erasing: ");
1427 prettyprint_ich9_reg_hsfc(hsfc);
1428 REGWRITE16(ICH9_REG_HSFC, hsfc);
1429
Subrata Banik7cb43952022-03-16 20:40:42 +05301430 if (ich_hwseq_wait_for_cycle_complete(len))
Stefan Tauner50e7c602011-11-08 10:55:54 +00001431 return -1;
1432 return 0;
1433}
1434
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001435static int ich_hwseq_read(struct flashctx *flash, uint8_t *buf,
1436 unsigned int addr, unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001437{
1438 uint16_t hsfc;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001439 uint8_t block_len;
1440
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001441 if (addr + len > flash->chip->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001442 msg_perr("Request to read from an inaccessible memory address "
1443 "(addr=0x%x, len=%d).\n", addr, len);
1444 return -1;
1445 }
1446
1447 msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr);
1448 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
1449 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1450
1451 while (len > 0) {
Stefan Tauner7608d362014-08-05 23:28:47 +00001452 /* Obey programmer limit... */
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001453 block_len = min(len, flash->mst->opaque.max_data_read);
Stefan Tauner7608d362014-08-05 23:28:47 +00001454 /* as well as flash chip page borders as demanded in the Intel datasheets. */
1455 block_len = min(block_len, 256 - (addr & 0xFF));
1456
Stefan Tauner50e7c602011-11-08 10:55:54 +00001457 ich_hwseq_set_addr(addr);
1458 hsfc = REGREAD16(ICH9_REG_HSFC);
Nico Huberd54e4f42017-03-23 23:45:47 +01001459 hsfc &= ~hwseq_data.hsfc_fcycle; /* set read operation */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001460 hsfc &= ~HSFC_FDBC; /* clear byte count */
1461 /* set byte count */
1462 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
1463 hsfc |= HSFC_FGO; /* start */
1464 REGWRITE16(ICH9_REG_HSFC, hsfc);
1465
Subrata Banik7cb43952022-03-16 20:40:42 +05301466 if (ich_hwseq_wait_for_cycle_complete(block_len))
Stefan Tauner50e7c602011-11-08 10:55:54 +00001467 return 1;
1468 ich_read_data(buf, block_len, ICH9_REG_FDATA0);
1469 addr += block_len;
1470 buf += block_len;
1471 len -= block_len;
1472 }
1473 return 0;
1474}
1475
Mark Marshallf20b7be2014-05-09 21:16:21 +00001476static int ich_hwseq_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001477{
1478 uint16_t hsfc;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001479 uint8_t block_len;
1480
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001481 if (addr + len > flash->chip->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001482 msg_perr("Request to write to an inaccessible memory address "
1483 "(addr=0x%x, len=%d).\n", addr, len);
1484 return -1;
1485 }
1486
1487 msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr);
1488 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
1489 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1490
1491 while (len > 0) {
1492 ich_hwseq_set_addr(addr);
Stefan Tauner7608d362014-08-05 23:28:47 +00001493 /* Obey programmer limit... */
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001494 block_len = min(len, flash->mst->opaque.max_data_write);
Stefan Tauner7608d362014-08-05 23:28:47 +00001495 /* as well as flash chip page borders as demanded in the Intel datasheets. */
1496 block_len = min(block_len, 256 - (addr & 0xFF));
Stefan Tauner50e7c602011-11-08 10:55:54 +00001497 ich_fill_data(buf, block_len, ICH9_REG_FDATA0);
1498 hsfc = REGREAD16(ICH9_REG_HSFC);
Nico Huberd54e4f42017-03-23 23:45:47 +01001499 hsfc &= ~hwseq_data.hsfc_fcycle; /* clear operation */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001500 hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */
1501 hsfc &= ~HSFC_FDBC; /* clear byte count */
1502 /* set byte count */
1503 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
1504 hsfc |= HSFC_FGO; /* start */
1505 REGWRITE16(ICH9_REG_HSFC, hsfc);
1506
Subrata Banik7cb43952022-03-16 20:40:42 +05301507 if (ich_hwseq_wait_for_cycle_complete(block_len))
Stefan Tauner50e7c602011-11-08 10:55:54 +00001508 return -1;
1509 addr += block_len;
1510 buf += block_len;
1511 len -= block_len;
1512 }
1513 return 0;
1514}
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001515
Edward O'Callaghan5eca4272020-04-12 17:27:53 +10001516static int ich_spi_send_multicommand(const struct flashctx *flash,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001517 struct spi_command *cmds)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001518{
1519 int ret = 0;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001520 int i;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001521 int oppos, preoppos;
1522 for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) {
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001523 if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001524 /* Next command is valid. */
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001525 preoppos = find_preop(curopcodes, cmds->writearr[0]);
1526 oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001527 if ((oppos == -1) && (preoppos != -1)) {
1528 /* Current command is listed as preopcode in
1529 * ICH struct OPCODES, but next command is not
1530 * listed as opcode in that struct.
1531 * Check for command sanity, then
1532 * try to reprogram the ICH opcode list.
1533 */
1534 if (find_preop(curopcodes,
1535 (cmds + 1)->writearr[0]) != -1) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001536 msg_perr("%s: Two subsequent "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001537 "preopcodes 0x%02x and 0x%02x, "
1538 "ignoring the first.\n",
1539 __func__, cmds->writearr[0],
1540 (cmds + 1)->writearr[0]);
1541 continue;
1542 }
1543 /* If the chipset is locked down, we'll fail
1544 * during execution of the next command anyway.
1545 * No need to bother with fixups.
1546 */
1547 if (!ichspi_lock) {
Helge Wagner738e2522010-10-05 22:06:05 +00001548 oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt);
1549 if (oppos == -1)
1550 continue;
1551 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001552 continue;
1553 }
1554 }
1555 if ((oppos != -1) && (preoppos != -1)) {
1556 /* Current command is listed as preopcode in
1557 * ICH struct OPCODES and next command is listed
1558 * as opcode in that struct. Match them up.
1559 */
1560 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001561 continue;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001562 }
1563 /* If none of the above if-statements about oppos or
1564 * preoppos matched, this is a normal opcode.
1565 */
1566 }
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001567 ret = ich_spi_send_command(flash, cmds->writecnt, cmds->readcnt,
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001568 cmds->writearr, cmds->readarr);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001569 /* Reset the type of all opcodes to non-atomic. */
1570 for (i = 0; i < 8; i++)
1571 curopcodes->opcode[i].atomic = 0;
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001572 }
1573 return ret;
1574}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001575
Michael Karchera4448d92010-07-22 18:04:15 +00001576#define ICH_BMWAG(x) ((x >> 24) & 0xff)
1577#define ICH_BMRAG(x) ((x >> 16) & 0xff)
1578#define ICH_BRWA(x) ((x >> 8) & 0xff)
1579#define ICH_BRRA(x) ((x >> 0) & 0xff)
1580
Nico Huber7590d1a2016-05-03 13:38:28 +02001581static const enum ich_access_protection access_perms_to_protection[] = {
1582 LOCKED, WRITE_PROT, READ_PROT, NO_PROT
1583};
1584static const char *const access_names[] = {
1585 "locked", "read-only", "write-only", "read-write"
1586};
1587
Nico Huber519be662018-12-23 20:03:35 +01001588static enum ich_access_protection ich9_handle_frap(uint32_t frap, unsigned int i)
Michael Karchera4448d92010-07-22 18:04:15 +00001589{
Nico Huberaa91d5c2017-08-19 17:04:21 +02001590 const int rwperms_unknown = ARRAY_SIZE(access_names);
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001591 static const char *const region_names[] = {
Michael Karchera4448d92010-07-22 18:04:15 +00001592 "Flash Descriptor", "BIOS", "Management Engine",
Nico Huberd2d39932019-01-18 16:49:37 +01001593 "Gigabit Ethernet", "Platform Data", "Device Expansion",
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001594 "BIOS2", "unknown", "EC/BMC",
Michael Karchera4448d92010-07-22 18:04:15 +00001595 };
Nico Huberd54e4f42017-03-23 23:45:47 +01001596 const char *const region_name = i < ARRAY_SIZE(region_names) ? region_names[i] : "unknown";
1597
Michael Karchera4448d92010-07-22 18:04:15 +00001598 uint32_t base, limit;
Nico Huberaa91d5c2017-08-19 17:04:21 +02001599 int rwperms;
Nico Huberd2d39932019-01-18 16:49:37 +01001600 const int offset = i < 12
1601 ? ICH9_REG_FREG0 + i * 4
1602 : APL_REG_FREG12 + (i - 12) * 4;
Michael Karchera4448d92010-07-22 18:04:15 +00001603 uint32_t freg = mmio_readl(ich_spibar + offset);
1604
Nico Huberaa91d5c2017-08-19 17:04:21 +02001605 if (i < 8) {
1606 rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) |
1607 (((ICH_BRRA(frap) >> i) & 1) << 0);
1608 } else {
1609 /* Datasheets don't define any access bits for regions > 7. We
1610 can't rely on the actual descriptor settings either as there
1611 are several overrides for them (those by other masters are
1612 not even readable by us, *shrug*). */
1613 rwperms = rwperms_unknown;
1614 }
1615
Michael Karchera4448d92010-07-22 18:04:15 +00001616 base = ICH_FREG_BASE(freg);
1617 limit = ICH_FREG_LIMIT(freg);
Stefan Taunere3adea02012-08-27 15:12:36 +00001618 if (base > limit || (freg == 0 && i > 0)) {
Michael Karchera4448d92010-07-22 18:04:15 +00001619 /* this FREG is disabled */
Nico Huber519be662018-12-23 20:03:35 +01001620 msg_pdbg2("0x%02X: 0x%08x FREG%u: %s region is unused.\n",
Nico Huberd54e4f42017-03-23 23:45:47 +01001621 offset, freg, i, region_name);
Nico Huber7590d1a2016-05-03 13:38:28 +02001622 return NO_PROT;
Stefan Tauner5210e722012-02-16 01:13:00 +00001623 }
1624 msg_pdbg("0x%02X: 0x%08x ", offset, freg);
1625 if (rwperms == 0x3) {
Nico Huber519be662018-12-23 20:03:35 +01001626 msg_pdbg("FREG%u: %s region (0x%08x-0x%08x) is %s.\n", i,
Nico Huber0bb3f712017-03-29 16:44:33 +02001627 region_name, base, limit, access_names[rwperms]);
Nico Huber7590d1a2016-05-03 13:38:28 +02001628 return NO_PROT;
Michael Karchera4448d92010-07-22 18:04:15 +00001629 }
Nico Huberaa91d5c2017-08-19 17:04:21 +02001630 if (rwperms == rwperms_unknown) {
Nico Huber519be662018-12-23 20:03:35 +01001631 msg_pdbg("FREG%u: %s region (0x%08x-0x%08x) has unknown permissions.\n",
Nico Huberaa91d5c2017-08-19 17:04:21 +02001632 i, region_name, base, limit);
Nico Huber7590d1a2016-05-03 13:38:28 +02001633 return NO_PROT;
Nico Huberaa91d5c2017-08-19 17:04:21 +02001634 }
Michael Karchera4448d92010-07-22 18:04:15 +00001635
Nico Huber519be662018-12-23 20:03:35 +01001636 msg_pinfo("FREG%u: %s region (0x%08x-0x%08x) is %s.\n", i,
Nico Huber0bb3f712017-03-29 16:44:33 +02001637 region_name, base, limit, access_names[rwperms]);
Nico Huber7590d1a2016-05-03 13:38:28 +02001638 return access_perms_to_protection[rwperms];
Michael Karchera4448d92010-07-22 18:04:15 +00001639}
1640
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001641 /* In contrast to FRAP and the master section of the descriptor the bits
1642 * in the PR registers have an inverted meaning. The bits in FRAP
1643 * indicate read and write access _grant_. Here they indicate read
1644 * and write _protection_ respectively. If both bits are 0 the address
1645 * bits are ignored.
1646 */
1647#define ICH_PR_PERMS(pr) (((~((pr) >> PR_RP_OFF) & 1) << 0) | \
1648 ((~((pr) >> PR_WP_OFF) & 1) << 1))
1649
Nico Huber519be662018-12-23 20:03:35 +01001650static enum ich_access_protection ich9_handle_pr(const size_t reg_pr0, unsigned int i)
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001651{
Nico Huberd54e4f42017-03-23 23:45:47 +01001652 uint8_t off = reg_pr0 + (i * 4);
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001653 uint32_t pr = mmio_readl(ich_spibar + off);
Stefan Tauner5210e722012-02-16 01:13:00 +00001654 unsigned int rwperms = ICH_PR_PERMS(pr);
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001655
Nico Huberd54e4f42017-03-23 23:45:47 +01001656 /* From 5 on we have GPR registers and start from 0 again. */
1657 const char *const prefix = i >= 5 ? "G" : "";
1658 if (i >= 5)
1659 i -= 5;
1660
Stefan Tauner5210e722012-02-16 01:13:00 +00001661 if (rwperms == 0x3) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001662 msg_pdbg2("0x%02X: 0x%08x (%sPR%u is unused)\n", off, pr, prefix, i);
Nico Huber7590d1a2016-05-03 13:38:28 +02001663 return NO_PROT;
Stefan Tauner5210e722012-02-16 01:13:00 +00001664 }
1665
1666 msg_pdbg("0x%02X: 0x%08x ", off, pr);
Nico Huberd54e4f42017-03-23 23:45:47 +01001667 msg_pwarn("%sPR%u: Warning: 0x%08x-0x%08x is %s.\n", prefix, i, ICH_FREG_BASE(pr),
Nico Huber0bb3f712017-03-29 16:44:33 +02001668 ICH_FREG_LIMIT(pr), access_names[rwperms]);
Nico Huber7590d1a2016-05-03 13:38:28 +02001669 return access_perms_to_protection[rwperms];
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001670}
1671
Stefan Tauner75da80c2011-09-17 22:21:55 +00001672/* Set/Clear the read and write protection enable bits of PR register @i
1673 * according to @read_prot and @write_prot. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001674static void ich9_set_pr(const size_t reg_pr0, int i, int read_prot, int write_prot)
Stefan Tauner75da80c2011-09-17 22:21:55 +00001675{
Nico Huberd54e4f42017-03-23 23:45:47 +01001676 void *addr = ich_spibar + reg_pr0 + (i * 4);
Stefan Tauner75da80c2011-09-17 22:21:55 +00001677 uint32_t old = mmio_readl(addr);
1678 uint32_t new;
1679
1680 msg_gspew("PR%u is 0x%08x", i, old);
1681 new = old & ~((1 << PR_RP_OFF) | (1 << PR_WP_OFF));
1682 if (read_prot)
1683 new |= (1 << PR_RP_OFF);
1684 if (write_prot)
1685 new |= (1 << PR_WP_OFF);
1686 if (old == new) {
1687 msg_gspew(" already.\n");
1688 return;
1689 }
1690 msg_gspew(", trying to set it to 0x%08x ", new);
1691 rmmio_writel(new, addr);
1692 msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr));
1693}
1694
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001695static const struct spi_master spi_master_ich7 = {
Michael Karcherb9dbe482011-05-11 17:07:07 +00001696 .max_data_read = 64,
1697 .max_data_write = 64,
1698 .command = ich_spi_send_command,
1699 .multicommand = ich_spi_send_multicommand,
1700 .read = default_spi_read,
1701 .write_256 = default_spi_write_256,
Nico Huber7bca1262012-06-15 22:28:12 +00001702 .write_aai = default_spi_write_aai,
Michael Karcherb9dbe482011-05-11 17:07:07 +00001703};
1704
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001705static const struct spi_master spi_master_ich9 = {
Michael Karcherb9dbe482011-05-11 17:07:07 +00001706 .max_data_read = 64,
1707 .max_data_write = 64,
1708 .command = ich_spi_send_command,
1709 .multicommand = ich_spi_send_multicommand,
1710 .read = default_spi_read,
1711 .write_256 = default_spi_write_256,
Nico Huber7bca1262012-06-15 22:28:12 +00001712 .write_aai = default_spi_write_aai,
Michael Karcherb9dbe482011-05-11 17:07:07 +00001713};
1714
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001715static const struct opaque_master opaque_master_ich_hwseq = {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001716 .max_data_read = 64,
1717 .max_data_write = 64,
1718 .probe = ich_hwseq_probe,
1719 .read = ich_hwseq_read,
1720 .write = ich_hwseq_write,
1721 .erase = ich_hwseq_block_erase,
1722};
1723
Nico Huber560111e2017-04-26 12:27:17 +02001724int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
Michael Karchera4448d92010-07-22 18:04:15 +00001725{
Nico Huber519be662018-12-23 20:03:35 +01001726 unsigned int i;
Stefan Tauner92d6a862013-10-25 00:33:37 +00001727 uint16_t tmp2;
Michael Karchera4448d92010-07-22 18:04:15 +00001728 uint32_t tmp;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001729 char *arg;
Stefan Tauner5210e722012-02-16 01:13:00 +00001730 int ich_spi_rw_restricted = 0;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001731 int desc_valid = 0;
Angel Pons7e134562021-06-07 13:29:13 +02001732 struct ich_descriptors desc = { 0 };
Stefan Tauner50e7c602011-11-08 10:55:54 +00001733 enum ich_spi_mode {
1734 ich_auto,
1735 ich_hwseq,
1736 ich_swseq
1737 } ich_spi_mode = ich_auto;
Nico Huberd54e4f42017-03-23 23:45:47 +01001738 size_t num_freg, num_pr, reg_pr0;
Michael Karchera4448d92010-07-22 18:04:15 +00001739
Stefan Taunera8d838d2011-11-06 23:51:09 +00001740 ich_generation = ich_gen;
Stefan Tauner92d6a862013-10-25 00:33:37 +00001741 ich_spibar = spibar;
Michael Karchera4448d92010-07-22 18:04:15 +00001742
Nico Huberd54e4f42017-03-23 23:45:47 +01001743 /* Moving registers / bits */
Nico Huberd2d39932019-01-18 16:49:37 +01001744 switch (ich_generation) {
1745 case CHIPSET_100_SERIES_SUNRISE_POINT:
1746 case CHIPSET_C620_SERIES_LEWISBURG:
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001747 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +02001748 case CHIPSET_500_SERIES_TIGER_POINT:
Nico Huberd2d39932019-01-18 16:49:37 +01001749 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +02001750 case CHIPSET_GEMINI_LAKE:
Werner Zehe57d4e42022-01-03 09:44:29 +01001751 case CHIPSET_ELKHART_LAKE:
David Hendricksa5216362017-08-08 20:02:22 -07001752 num_pr = 6; /* Includes GPR0 */
1753 reg_pr0 = PCH100_REG_FPR0;
1754 swseq_data.reg_ssfsc = PCH100_REG_SSFSC;
1755 swseq_data.reg_preop = PCH100_REG_PREOP;
1756 swseq_data.reg_optype = PCH100_REG_OPTYPE;
1757 swseq_data.reg_opmenu = PCH100_REG_OPMENU;
1758 hwseq_data.addr_mask = PCH100_FADDR_FLA;
1759 hwseq_data.only_4k = true;
1760 hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE;
Nico Huberd2d39932019-01-18 16:49:37 +01001761 break;
1762 default:
Nico Huberd54e4f42017-03-23 23:45:47 +01001763 num_pr = 5;
1764 reg_pr0 = ICH9_REG_PR0;
1765 swseq_data.reg_ssfsc = ICH9_REG_SSFS;
1766 swseq_data.reg_preop = ICH9_REG_PREOP;
1767 swseq_data.reg_optype = ICH9_REG_OPTYPE;
1768 swseq_data.reg_opmenu = ICH9_REG_OPMENU;
1769 hwseq_data.addr_mask = ICH9_FADDR_FLA;
1770 hwseq_data.only_4k = false;
1771 hwseq_data.hsfc_fcycle = HSFC_FCYCLE;
Nico Huberd2d39932019-01-18 16:49:37 +01001772 break;
1773 }
1774 switch (ich_generation) {
1775 case CHIPSET_100_SERIES_SUNRISE_POINT:
1776 num_freg = 10;
1777 break;
1778 case CHIPSET_C620_SERIES_LEWISBURG:
1779 num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */
1780 break;
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001781 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +02001782 case CHIPSET_500_SERIES_TIGER_POINT:
Nico Huberd2d39932019-01-18 16:49:37 +01001783 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +02001784 case CHIPSET_GEMINI_LAKE:
Werner Zehe57d4e42022-01-03 09:44:29 +01001785 case CHIPSET_ELKHART_LAKE:
Nico Huberd2d39932019-01-18 16:49:37 +01001786 num_freg = 16;
1787 break;
1788 default:
1789 num_freg = 5;
1790 break;
Nico Huberd54e4f42017-03-23 23:45:47 +01001791 }
1792
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001793 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +00001794 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +00001795 case CHIPSET_TUNNEL_CREEK:
1796 case CHIPSET_CENTERTON:
Michael Karchera4448d92010-07-22 18:04:15 +00001797 msg_pdbg("0x00: 0x%04x (SPIS)\n",
1798 mmio_readw(ich_spibar + 0));
1799 msg_pdbg("0x02: 0x%04x (SPIC)\n",
1800 mmio_readw(ich_spibar + 2));
1801 msg_pdbg("0x04: 0x%08x (SPIA)\n",
1802 mmio_readl(ich_spibar + 4));
Michael Karchera4448d92010-07-22 18:04:15 +00001803 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
1804 msg_pdbg("0x50: 0x%08x (BBAR)\n",
1805 ichspi_bbar);
1806 msg_pdbg("0x54: 0x%04x (PREOP)\n",
1807 mmio_readw(ich_spibar + 0x54));
1808 msg_pdbg("0x56: 0x%04x (OPTYPE)\n",
1809 mmio_readw(ich_spibar + 0x56));
1810 msg_pdbg("0x58: 0x%08x (OPMENU)\n",
1811 mmio_readl(ich_spibar + 0x58));
1812 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n",
1813 mmio_readl(ich_spibar + 0x5c));
Stefan Tauner122dd122011-07-24 15:34:56 +00001814 for (i = 0; i < 3; i++) {
Michael Karchera4448d92010-07-22 18:04:15 +00001815 int offs;
1816 offs = 0x60 + (i * 4);
Nico Huber519be662018-12-23 20:03:35 +01001817 msg_pdbg("0x%02x: 0x%08x (PBR%u)\n", offs,
Michael Karchera4448d92010-07-22 18:04:15 +00001818 mmio_readl(ich_spibar + offs), i);
1819 }
Michael Karchera4448d92010-07-22 18:04:15 +00001820 if (mmio_readw(ich_spibar) & (1 << 15)) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00001821 msg_pwarn("WARNING: SPI Configuration Lockdown activated.\n");
Michael Karchera4448d92010-07-22 18:04:15 +00001822 ichspi_lock = 1;
1823 }
Stefan Tauner745f6bb2011-11-13 15:17:10 +00001824 ich_init_opcodes();
Stefan Taunera8d838d2011-11-06 23:51:09 +00001825 ich_set_bbar(0);
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001826 register_spi_master(&spi_master_ich7);
Michael Karchera4448d92010-07-22 18:04:15 +00001827 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +00001828 case CHIPSET_ICH8:
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001829 default: /* Future version might behave the same */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001830 arg = extract_programmer_param("ich_spi_mode");
1831 if (arg && !strcmp(arg, "hwseq")) {
1832 ich_spi_mode = ich_hwseq;
1833 msg_pspew("user selected hwseq\n");
1834 } else if (arg && !strcmp(arg, "swseq")) {
1835 ich_spi_mode = ich_swseq;
1836 msg_pspew("user selected swseq\n");
1837 } else if (arg && !strcmp(arg, "auto")) {
1838 msg_pspew("user selected auto\n");
1839 ich_spi_mode = ich_auto;
1840 } else if (arg && !strlen(arg)) {
1841 msg_perr("Missing argument for ich_spi_mode.\n");
1842 free(arg);
1843 return ERROR_FATAL;
1844 } else if (arg) {
1845 msg_perr("Unknown argument for ich_spi_mode: %s\n",
1846 arg);
1847 free(arg);
1848 return ERROR_FATAL;
1849 }
1850 free(arg);
1851
Stefan Tauner29c80832011-06-12 08:14:10 +00001852 tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS);
Michael Karchera4448d92010-07-22 18:04:15 +00001853 msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2);
Stefan Tauner55206942011-06-11 09:53:22 +00001854 prettyprint_ich9_reg_hsfs(tmp2);
Stefan Tauner29c80832011-06-12 08:14:10 +00001855 if (tmp2 & HSFS_FLOCKDN) {
Nico Huber7590d1a2016-05-03 13:38:28 +02001856 msg_pinfo("SPI Configuration is locked down.\n");
Stefan Tauner55206942011-06-11 09:53:22 +00001857 ichspi_lock = 1;
1858 }
Stefan Tauner1e146392011-09-15 23:52:55 +00001859 if (tmp2 & HSFS_FDV)
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001860 desc_valid = 1;
1861 if (!(tmp2 & HSFS_FDOPSS) && desc_valid)
Stefan Taunerd7d423b2012-10-20 09:13:16 +00001862 msg_pinfo("The Flash Descriptor Override Strap-Pin is set. Restrictions implied by\n"
1863 "the Master Section of the flash descriptor are NOT in effect. Please note\n"
1864 "that Protected Range (PR) restrictions still apply.\n");
Stefan Tauner745f6bb2011-11-13 15:17:10 +00001865 ich_init_opcodes();
Stefan Tauner55206942011-06-11 09:53:22 +00001866
Stefan Taunerf382e352011-11-08 11:55:24 +00001867 if (desc_valid) {
1868 tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC);
1869 msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2);
1870 prettyprint_ich9_reg_hsfc(tmp2);
1871 }
Michael Karchera4448d92010-07-22 18:04:15 +00001872
Stefan Tauner5ffe65b2011-07-07 04:10:57 +00001873 tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR);
Stefan Taunereb582572012-09-21 12:52:50 +00001874 msg_pdbg2("0x08: 0x%08x (FADDR)\n", tmp);
Michael Karchera4448d92010-07-22 18:04:15 +00001875
Nico Huberd2d39932019-01-18 16:49:37 +01001876 switch (ich_gen) {
1877 case CHIPSET_100_SERIES_SUNRISE_POINT:
1878 case CHIPSET_C620_SERIES_LEWISBURG:
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001879 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +02001880 case CHIPSET_500_SERIES_TIGER_POINT:
Nico Huberd2d39932019-01-18 16:49:37 +01001881 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +02001882 case CHIPSET_GEMINI_LAKE:
Werner Zehe57d4e42022-01-03 09:44:29 +01001883 case CHIPSET_ELKHART_LAKE:
Nico Huberd2d39932019-01-18 16:49:37 +01001884 tmp = mmio_readl(ich_spibar + PCH100_REG_DLOCK);
1885 msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp);
1886 prettyprint_pch100_reg_dlock(tmp);
1887 break;
1888 default:
1889 break;
Nico Huberd54e4f42017-03-23 23:45:47 +01001890 }
1891
Stefan Taunerf382e352011-11-08 11:55:24 +00001892 if (desc_valid) {
1893 tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP);
1894 msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp);
1895 msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp));
1896 msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp));
1897 msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp));
1898 msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp));
1899
Stefan Tauner5210e722012-02-16 01:13:00 +00001900 /* Handle FREGx and FRAP registers */
Nico Huberd54e4f42017-03-23 23:45:47 +01001901 for (i = 0; i < num_freg; i++)
Stefan Tauner5210e722012-02-16 01:13:00 +00001902 ich_spi_rw_restricted |= ich9_handle_frap(tmp, i);
Stefan Tauner27cb34b2013-06-01 00:06:12 +00001903 if (ich_spi_rw_restricted)
Nico Huber7590d1a2016-05-03 13:38:28 +02001904 msg_pinfo("Not all flash regions are freely accessible by flashrom. This is "
Stefan Tauner4c723152016-01-14 22:47:55 +00001905 "most likely\ndue to an active ME. Please see "
1906 "https://flashrom.org/ME for details.\n");
Stefan Taunerf382e352011-11-08 11:55:24 +00001907 }
Michael Karchera4448d92010-07-22 18:04:15 +00001908
Stefan Taunereb582572012-09-21 12:52:50 +00001909 /* Handle PR registers */
Nico Huberd54e4f42017-03-23 23:45:47 +01001910 for (i = 0; i < num_pr; i++) {
Stefan Tauner5210e722012-02-16 01:13:00 +00001911 /* if not locked down try to disable PR locks first */
1912 if (!ichspi_lock)
Nico Huberd54e4f42017-03-23 23:45:47 +01001913 ich9_set_pr(reg_pr0, i, 0, 0);
1914 ich_spi_rw_restricted |= ich9_handle_pr(reg_pr0, i);
Stefan Tauner5210e722012-02-16 01:13:00 +00001915 }
1916
Nico Huber7590d1a2016-05-03 13:38:28 +02001917 switch (ich_spi_rw_restricted) {
1918 case WRITE_PROT:
1919 msg_pwarn("At least some flash regions are write protected. For write operations,\n"
1920 "you should use a flash layout and include only writable regions. See\n"
1921 "manpage for more details.\n");
1922 break;
1923 case READ_PROT:
1924 case LOCKED:
1925 msg_pwarn("At least some flash regions are read protected. You have to use a flash\n"
1926 "layout and include only accessible regions. For write operations, you'll\n"
1927 "additionally need the --noverify-all switch. See manpage for more details.\n"
1928 );
1929 break;
Stefan Tauner5210e722012-02-16 01:13:00 +00001930 }
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001931
Nico Huberd54e4f42017-03-23 23:45:47 +01001932 tmp = mmio_readl(ich_spibar + swseq_data.reg_ssfsc);
1933 msg_pdbg("0x%zx: 0x%02x (SSFS)\n", swseq_data.reg_ssfsc, tmp & 0xff);
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001934 prettyprint_ich9_reg_ssfs(tmp);
Stefan Tauner29c80832011-06-12 08:14:10 +00001935 if (tmp & SSFS_FCERR) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001936 msg_pdbg("Clearing SSFS.FCERR\n");
Nico Huberd54e4f42017-03-23 23:45:47 +01001937 mmio_writeb(SSFS_FCERR, ich_spibar + swseq_data.reg_ssfsc);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001938 }
Nico Huberd54e4f42017-03-23 23:45:47 +01001939 msg_pdbg("0x%zx: 0x%06x (SSFC)\n", swseq_data.reg_ssfsc + 1, tmp >> 8);
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001940 prettyprint_ich9_reg_ssfc(tmp);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001941
Nico Huberd54e4f42017-03-23 23:45:47 +01001942 msg_pdbg("0x%zx: 0x%04x (PREOP)\n",
1943 swseq_data.reg_preop, mmio_readw(ich_spibar + swseq_data.reg_preop));
1944 msg_pdbg("0x%zx: 0x%04x (OPTYPE)\n",
1945 swseq_data.reg_optype, mmio_readw(ich_spibar + swseq_data.reg_optype));
1946 msg_pdbg("0x%zx: 0x%08x (OPMENU)\n",
1947 swseq_data.reg_opmenu, mmio_readl(ich_spibar + swseq_data.reg_opmenu));
1948 msg_pdbg("0x%zx: 0x%08x (OPMENU+4)\n",
1949 swseq_data.reg_opmenu + 4, mmio_readl(ich_spibar + swseq_data.reg_opmenu + 4));
Nico Huberd2d39932019-01-18 16:49:37 +01001950
1951 if (desc_valid) {
1952 switch (ich_gen) {
1953 case CHIPSET_ICH8:
1954 case CHIPSET_100_SERIES_SUNRISE_POINT:
1955 case CHIPSET_C620_SERIES_LEWISBURG:
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001956 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +02001957 case CHIPSET_500_SERIES_TIGER_POINT:
Nico Huberd2d39932019-01-18 16:49:37 +01001958 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +02001959 case CHIPSET_GEMINI_LAKE:
Werner Zehe57d4e42022-01-03 09:44:29 +01001960 case CHIPSET_ELKHART_LAKE:
Nico Huberd2d39932019-01-18 16:49:37 +01001961 case CHIPSET_BAYTRAIL:
1962 break;
1963 default:
Duncan Laurie4095ed72014-08-20 15:39:32 +00001964 ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR);
Nico Huberd2d39932019-01-18 16:49:37 +01001965 msg_pdbg("0x%x: 0x%08x (BBAR)\n", ICH9_REG_BBAR, ichspi_bbar);
Duncan Laurie4095ed72014-08-20 15:39:32 +00001966 ich_set_bbar(0);
Nico Huberd2d39932019-01-18 16:49:37 +01001967 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +00001968 }
Stefan Taunerbd649e42011-07-01 00:39:16 +00001969
Nico Huberd2d39932019-01-18 16:49:37 +01001970 if (ich_gen == CHIPSET_ICH8) {
1971 tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC);
1972 msg_pdbg("0x%x: 0x%08x (VSCC)\n", ICH8_REG_VSCC, tmp);
1973 msg_pdbg("VSCC: ");
1974 prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true);
1975 } else {
Stefan Taunerf382e352011-11-08 11:55:24 +00001976 tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC);
Nico Huberd2d39932019-01-18 16:49:37 +01001977 msg_pdbg("0x%x: 0x%08x (LVSCC)\n", ICH9_REG_LVSCC, tmp);
Stefan Taunerf382e352011-11-08 11:55:24 +00001978 msg_pdbg("LVSCC: ");
Nico Huberd152fb92017-06-19 12:57:10 +02001979 prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true);
Stefan Tauner1e146392011-09-15 23:52:55 +00001980
Stefan Taunerf382e352011-11-08 11:55:24 +00001981 tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC);
Nico Huberd2d39932019-01-18 16:49:37 +01001982 msg_pdbg("0x%x: 0x%08x (UVSCC)\n", ICH9_REG_UVSCC, tmp);
Stefan Taunerf382e352011-11-08 11:55:24 +00001983 msg_pdbg("UVSCC: ");
Nico Huberd152fb92017-06-19 12:57:10 +02001984 prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, false);
Stefan Taunerf382e352011-11-08 11:55:24 +00001985 }
Stefan Tauner1e146392011-09-15 23:52:55 +00001986
Nico Huberd2d39932019-01-18 16:49:37 +01001987 switch (ich_gen) {
1988 case CHIPSET_ICH8:
1989 case CHIPSET_100_SERIES_SUNRISE_POINT:
1990 case CHIPSET_C620_SERIES_LEWISBURG:
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001991 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +02001992 case CHIPSET_500_SERIES_TIGER_POINT:
Nico Huberd2d39932019-01-18 16:49:37 +01001993 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +02001994 case CHIPSET_GEMINI_LAKE:
Werner Zehe57d4e42022-01-03 09:44:29 +01001995 case CHIPSET_ELKHART_LAKE:
Nico Huberd2d39932019-01-18 16:49:37 +01001996 break;
1997 default:
1998 tmp = mmio_readl(ich_spibar + ICH9_REG_FPB);
1999 msg_pdbg("0x%x: 0x%08x (FPB)\n", ICH9_REG_FPB, tmp);
2000 break;
2001 }
2002
Nico Huberd54e4f42017-03-23 23:45:47 +01002003 if (read_ich_descriptors_via_fdo(ich_gen, ich_spibar, &desc) == ICH_RET_OK)
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +00002004 prettyprint_ich_descriptors(ich_gen, &desc);
2005
Stefan Tauner50e7c602011-11-08 10:55:54 +00002006 /* If the descriptor is valid and indicates multiple
2007 * flash devices we need to use hwseq to be able to
2008 * access the second flash device.
2009 */
2010 if (ich_spi_mode == ich_auto && desc.content.NC != 0) {
2011 msg_pinfo("Enabling hardware sequencing due to "
2012 "multiple flash chips detected.\n");
2013 ich_spi_mode = ich_hwseq;
2014 }
Stefan Tauner1e146392011-09-15 23:52:55 +00002015 }
Stefan Tauner50e7c602011-11-08 10:55:54 +00002016
2017 if (ich_spi_mode == ich_auto && ichspi_lock &&
2018 ich_missing_opcodes()) {
2019 msg_pinfo("Enabling hardware sequencing because "
2020 "some important opcode is locked.\n");
2021 ich_spi_mode = ich_hwseq;
2022 }
2023
Nico Huber2a5dfaf2019-07-04 16:01:51 +02002024 if (ich_spi_mode == ich_auto &&
2025 (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT ||
Michał Żygowski5c9f5422021-06-16 15:13:54 +02002026 ich_gen == CHIPSET_300_SERIES_CANNON_POINT ||
2027 ich_gen == CHIPSET_500_SERIES_TIGER_POINT)) {
Nico Huber2a5dfaf2019-07-04 16:01:51 +02002028 msg_pdbg("Enabling hardware sequencing by default for 100+ series PCH.\n");
Nico Huber22f2dc52017-08-31 16:14:22 +02002029 ich_spi_mode = ich_hwseq;
2030 }
2031
Angel Pons4db0fdf2020-07-10 17:04:10 +02002032 if (ich_spi_mode == ich_auto &&
2033 (ich_gen == CHIPSET_APOLLO_LAKE ||
Werner Zehe57d4e42022-01-03 09:44:29 +01002034 ich_gen == CHIPSET_GEMINI_LAKE ||
2035 ich_gen == CHIPSET_ELKHART_LAKE)) {
2036 msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Elkhart Lake.\n");
Nico Huberd2d39932019-01-18 16:49:37 +01002037 ich_spi_mode = ich_hwseq;
2038 }
2039
Stefan Tauner50e7c602011-11-08 10:55:54 +00002040 if (ich_spi_mode == ich_hwseq) {
2041 if (!desc_valid) {
2042 msg_perr("Hardware sequencing was requested "
2043 "but the flash descriptor is not "
2044 "valid. Aborting.\n");
2045 return ERROR_FATAL;
2046 }
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +00002047
2048 int tmpi = getFCBA_component_density(ich_generation, &desc, 0);
2049 if (tmpi < 0) {
2050 msg_perr("Could not determine density of flash component %d.\n", 0);
2051 return ERROR_FATAL;
2052 }
2053 hwseq_data.size_comp0 = tmpi;
2054
2055 tmpi = getFCBA_component_density(ich_generation, &desc, 1);
2056 if (tmpi < 0) {
2057 msg_perr("Could not determine density of flash component %d.\n", 1);
2058 return ERROR_FATAL;
2059 }
2060 hwseq_data.size_comp1 = tmpi;
2061
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00002062 register_opaque_master(&opaque_master_ich_hwseq);
Stefan Tauner50e7c602011-11-08 10:55:54 +00002063 } else {
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00002064 register_spi_master(&spi_master_ich9);
Stefan Tauner50e7c602011-11-08 10:55:54 +00002065 }
Michael Karchera4448d92010-07-22 18:04:15 +00002066 break;
Michael Karchera4448d92010-07-22 18:04:15 +00002067 }
2068
Michael Karchera4448d92010-07-22 18:04:15 +00002069 return 0;
2070}
2071
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00002072static const struct spi_master spi_master_via = {
Michael Karcherb9dbe482011-05-11 17:07:07 +00002073 .max_data_read = 16,
2074 .max_data_write = 16,
2075 .command = ich_spi_send_command,
2076 .multicommand = ich_spi_send_multicommand,
2077 .read = default_spi_read,
2078 .write_256 = default_spi_write_256,
Nico Huber7bca1262012-06-15 22:28:12 +00002079 .write_aai = default_spi_write_aai,
Michael Karcherb9dbe482011-05-11 17:07:07 +00002080};
2081
Nico Huber560111e2017-04-26 12:27:17 +02002082int via_init_spi(uint32_t mmio_base)
Michael Karchera4448d92010-07-22 18:04:15 +00002083{
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00002084 int i;
Michael Karchera4448d92010-07-22 18:04:15 +00002085
Stefan Tauner7fb5aa02013-08-14 15:48:44 +00002086 ich_spibar = rphysmap("VIA SPI MMIO registers", mmio_base, 0x70);
2087 if (ich_spibar == ERROR_PTR)
2088 return ERROR_FATAL;
Helge Wagnerdd73d832012-08-24 23:03:46 +00002089 /* Do we really need no write enable? Like the LPC one at D17F0 0x40 */
Michael Karchera4448d92010-07-22 18:04:15 +00002090
Michael Karchera4448d92010-07-22 18:04:15 +00002091 /* Not sure if it speaks all these bus protocols. */
Nico Huber2e50cdc2018-09-23 20:20:26 +02002092 internal_buses_supported &= BUS_LPC | BUS_FWH;
Stefan Taunera8d838d2011-11-06 23:51:09 +00002093 ich_generation = CHIPSET_ICH7;
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00002094 register_spi_master(&spi_master_via);
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00002095
2096 msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0));
2097 msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2));
2098 msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(ich_spibar + 4));
2099 for (i = 0; i < 2; i++) {
2100 int offs;
2101 offs = 8 + (i * 8);
2102 msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs,
2103 mmio_readl(ich_spibar + offs), i);
2104 msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
2105 mmio_readl(ich_spibar + offs + 4), i);
2106 }
2107 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
2108 msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar);
2109 msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x54));
2110 msg_pdbg("0x56: 0x%04x (OPTYPE)\n", mmio_readw(ich_spibar + 0x56));
2111 msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(ich_spibar + 0x58));
2112 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + 0x5c));
2113 for (i = 0; i < 3; i++) {
2114 int offs;
2115 offs = 0x60 + (i * 4);
2116 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
2117 mmio_readl(ich_spibar + offs), i);
2118 }
2119 msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n",
2120 mmio_readw(ich_spibar + 0x6c));
2121 if (mmio_readw(ich_spibar) & (1 << 15)) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00002122 msg_pwarn("Warning: SPI Configuration Lockdown activated.\n");
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00002123 ichspi_lock = 1;
2124 }
2125
Stefan Taunera8d838d2011-11-06 23:51:09 +00002126 ich_set_bbar(0);
Michael Karchera4448d92010-07-22 18:04:15 +00002127 ich_init_opcodes();
2128
2129 return 0;
2130}
2131
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002132#endif