blob: 0996d2dbc64439ab66db35d959f3a51f3d0b751e [file] [log] [blame]
Dominik Geyerb46acba2008-05-16 12:55:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
5 * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
6 * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
Stefan Reinauera9424d52008-06-27 16:28:34 +00007 * Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00008 * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
Stefan Tauner8b391b82011-08-09 01:49:34 +00009 * Copyright (C) 2011 Stefan Tauner
Dominik Geyerb46acba2008-05-16 12:55:55 +000010 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
Dominik Geyerb46acba2008-05-16 12:55:55 +000020 */
21
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000022#if defined(__i386__) || defined(__x86_64__)
23
Dominik Geyerb46acba2008-05-16 12:55:55 +000024#include <string.h>
Felix Singer8cfc7372022-08-19 03:10:29 +020025#include <stdbool.h>
Stefan Taunerd0c5dc22011-10-20 12:57:14 +000026#include <stdlib.h>
Dominik Geyerb46acba2008-05-16 12:55:55 +000027#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000028#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000029#include "hwaccess.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000030#include "spi.h"
Stefan Tauner1e146392011-09-15 23:52:55 +000031#include "ich_descriptors.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000032
Nico Huberd2d39932019-01-18 16:49:37 +010033/* Apollo Lake */
34#define APL_REG_FREG12 0xe0 /* 32 Bytes Flash Region 12 */
35
Nico Huberd54e4f42017-03-23 23:45:47 +010036/* Sunrise Point */
37
38/* Added HSFS Status bits */
39#define HSFS_WRSDIS_OFF 11 /* 11: Flash Configuration Lock-Down */
40#define HSFS_WRSDIS (0x1 << HSFS_WRSDIS_OFF)
41#define HSFS_PRR34_LOCKDN_OFF 12 /* 12: PRR3 PRR4 Lock-Down */
42#define HSFS_PRR34_LOCKDN (0x1 << HSFS_PRR34_LOCKDN_OFF)
43/* HSFS_BERASE vanished */
44
45/*
46 * HSFC and HSFS 16-bit registers are combined into the 32-bit
47 * BIOS_HSFSTS_CTL register in the Sunrise Point datasheet,
48 * however we still treat them separately in order to reuse code.
49 */
50
51/* Changed HSFC Control bits */
52#define PCH100_HSFC_FCYCLE_OFF (17 - 16) /* 1-4: FLASH Cycle */
53#define PCH100_HSFC_FCYCLE (0xf << PCH100_HSFC_FCYCLE_OFF)
54/* New HSFC Control bit */
55#define HSFC_WET_OFF (21 - 16) /* 5: Write Enable Type */
56#define HSFC_WET (0x1 << HSFC_WET_OFF)
57
58#define PCH100_FADDR_FLA 0x07ffffff
59
60#define PCH100_REG_DLOCK 0x0c /* 32 Bits Discrete Lock Bits */
61#define DLOCK_BMWAG_LOCKDN_OFF 0
62#define DLOCK_BMWAG_LOCKDN (0x1 << DLOCK_BMWAG_LOCKDN_OFF)
63#define DLOCK_BMRAG_LOCKDN_OFF 1
64#define DLOCK_BMRAG_LOCKDN (0x1 << DLOCK_BMRAG_LOCKDN_OFF)
65#define DLOCK_SBMWAG_LOCKDN_OFF 2
66#define DLOCK_SBMWAG_LOCKDN (0x1 << DLOCK_SBMWAG_LOCKDN_OFF)
67#define DLOCK_SBMRAG_LOCKDN_OFF 3
68#define DLOCK_SBMRAG_LOCKDN (0x1 << DLOCK_SBMRAG_LOCKDN_OFF)
69#define DLOCK_PR0_LOCKDN_OFF 8
70#define DLOCK_PR0_LOCKDN (0x1 << DLOCK_PR0_LOCKDN_OFF)
71#define DLOCK_PR1_LOCKDN_OFF 9
72#define DLOCK_PR1_LOCKDN (0x1 << DLOCK_PR1_LOCKDN_OFF)
73#define DLOCK_PR2_LOCKDN_OFF 10
74#define DLOCK_PR2_LOCKDN (0x1 << DLOCK_PR2_LOCKDN_OFF)
75#define DLOCK_PR3_LOCKDN_OFF 11
76#define DLOCK_PR3_LOCKDN (0x1 << DLOCK_PR3_LOCKDN_OFF)
77#define DLOCK_PR4_LOCKDN_OFF 12
78#define DLOCK_PR4_LOCKDN (0x1 << DLOCK_PR4_LOCKDN_OFF)
79#define DLOCK_SSEQ_LOCKDN_OFF 16
80#define DLOCK_SSEQ_LOCKDN (0x1 << DLOCK_SSEQ_LOCKDN_OFF)
81
82#define PCH100_REG_FPR0 0x84 /* 32 Bits Protected Range 0 */
83#define PCH100_REG_GPR0 0x98 /* 32 Bits Global Protected Range 0 */
84
85#define PCH100_REG_SSFSC 0xA0 /* 32 Bits Status (8) + Control (24) */
86#define PCH100_REG_PREOP 0xA4 /* 16 Bits */
87#define PCH100_REG_OPTYPE 0xA6 /* 16 Bits */
88#define PCH100_REG_OPMENU 0xA8 /* 64 Bits */
89
Stefan Reinauera9424d52008-06-27 16:28:34 +000090/* ICH9 controller register definition */
Stefan Tauner55206942011-06-11 09:53:22 +000091#define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */
92#define HSFS_FDONE_OFF 0 /* 0: Flash Cycle Done */
93#define HSFS_FDONE (0x1 << HSFS_FDONE_OFF)
94#define HSFS_FCERR_OFF 1 /* 1: Flash Cycle Error */
95#define HSFS_FCERR (0x1 << HSFS_FCERR_OFF)
96#define HSFS_AEL_OFF 2 /* 2: Access Error Log */
97#define HSFS_AEL (0x1 << HSFS_AEL_OFF)
98#define HSFS_BERASE_OFF 3 /* 3-4: Block/Sector Erase Size */
99#define HSFS_BERASE (0x3 << HSFS_BERASE_OFF)
100#define HSFS_SCIP_OFF 5 /* 5: SPI Cycle In Progress */
101#define HSFS_SCIP (0x1 << HSFS_SCIP_OFF)
102 /* 6-12: reserved */
103#define HSFS_FDOPSS_OFF 13 /* 13: Flash Descriptor Override Pin-Strap Status */
104#define HSFS_FDOPSS (0x1 << HSFS_FDOPSS_OFF)
105#define HSFS_FDV_OFF 14 /* 14: Flash Descriptor Valid */
106#define HSFS_FDV (0x1 << HSFS_FDV_OFF)
107#define HSFS_FLOCKDN_OFF 15 /* 15: Flash Configuration Lock-Down */
108#define HSFS_FLOCKDN (0x1 << HSFS_FLOCKDN_OFF)
109
110#define ICH9_REG_HSFC 0x06 /* 16 Bits Hardware Sequencing Flash Control */
111#define HSFC_FGO_OFF 0 /* 0: Flash Cycle Go */
112#define HSFC_FGO (0x1 << HSFC_FGO_OFF)
113#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
114#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
115 /* 3-7: reserved */
116#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
117#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
118 /* 14: reserved */
119#define HSFC_SME_OFF 15 /* 15: SPI SMI# Enable */
120#define HSFC_SME (0x1 << HSFC_SME_OFF)
121
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000122#define ICH9_REG_FADDR 0x08 /* 32 Bits */
Nico Huberd54e4f42017-03-23 23:45:47 +0100123#define ICH9_FADDR_FLA 0x01ffffff
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000124#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000125
Stefan Tauner29c80832011-06-12 08:14:10 +0000126#define ICH9_REG_FRAP 0x50 /* 32 Bytes Flash Region Access Permissions */
127#define ICH9_REG_FREG0 0x54 /* 32 Bytes Flash Region 0 */
128
129#define ICH9_REG_PR0 0x74 /* 32 Bytes Protected Range 0 */
Stefan Taunerbf69aaa2011-09-17 21:21:48 +0000130#define PR_WP_OFF 31 /* 31: write protection enable */
131#define PR_RP_OFF 15 /* 15: read protection enable */
Stefan Tauner29c80832011-06-12 08:14:10 +0000132
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000133#define ICH9_REG_SSFS 0x90 /* 08 Bits */
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000134#define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */
135#define SSFS_SCIP (0x1 << SSFS_SCIP_OFF)
136#define SSFS_FDONE_OFF 2 /* Cycle Done Status */
137#define SSFS_FDONE (0x1 << SSFS_FDONE_OFF)
138#define SSFS_FCERR_OFF 3 /* Flash Cycle Error */
139#define SSFS_FCERR (0x1 << SSFS_FCERR_OFF)
140#define SSFS_AEL_OFF 4 /* Access Error Log */
141#define SSFS_AEL (0x1 << SSFS_AEL_OFF)
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000142/* The following bits are reserved in SSFS: 1,5-7. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000143#define SSFS_RESERVED_MASK 0x000000e2
Stefan Reinauera9424d52008-06-27 16:28:34 +0000144
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000145#define ICH9_REG_SSFC 0x91 /* 24 Bits */
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000146/* We combine SSFS and SSFC to one 32-bit word,
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000147 * therefore SSFC bits are off by 8. */
148 /* 0: reserved */
149#define SSFC_SCGO_OFF (1 + 8) /* 1: SPI Cycle Go */
150#define SSFC_SCGO (0x1 << SSFC_SCGO_OFF)
151#define SSFC_ACS_OFF (2 + 8) /* 2: Atomic Cycle Sequence */
152#define SSFC_ACS (0x1 << SSFC_ACS_OFF)
153#define SSFC_SPOP_OFF (3 + 8) /* 3: Sequence Prefix Opcode Pointer */
154#define SSFC_SPOP (0x1 << SSFC_SPOP_OFF)
155#define SSFC_COP_OFF (4 + 8) /* 4-6: Cycle Opcode Pointer */
156#define SSFC_COP (0x7 << SSFC_COP_OFF)
157 /* 7: reserved */
158#define SSFC_DBC_OFF (8 + 8) /* 8-13: Data Byte Count */
159#define SSFC_DBC (0x3f << SSFC_DBC_OFF)
160#define SSFC_DS_OFF (14 + 8) /* 14: Data Cycle */
161#define SSFC_DS (0x1 << SSFC_DS_OFF)
162#define SSFC_SME_OFF (15 + 8) /* 15: SPI SMI# Enable */
163#define SSFC_SME (0x1 << SSFC_SME_OFF)
164#define SSFC_SCF_OFF (16 + 8) /* 16-18: SPI Cycle Frequency */
165#define SSFC_SCF (0x7 << SSFC_SCF_OFF)
166#define SSFC_SCF_20MHZ 0x00000000
167#define SSFC_SCF_33MHZ 0x01000000
168 /* 19-23: reserved */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000169#define SSFC_RESERVED_MASK 0xf8008100
Stefan Reinauera9424d52008-06-27 16:28:34 +0000170
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000171#define ICH9_REG_PREOP 0x94 /* 16 Bits */
172#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
173#define ICH9_REG_OPMENU 0x98 /* 64 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000174
Stefan Tauner29c80832011-06-12 08:14:10 +0000175#define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */
176#define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */
177
Stefan Tauner1e146392011-09-15 23:52:55 +0000178#define ICH8_REG_VSCC 0xC1 /* 32 Bits Vendor Specific Component Capabilities */
179#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */
180#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */
181/* The individual fields of the VSCC registers are defined in the file
182 * ich_descriptors.h. The reason is that the same layout is also used in the
183 * flash descriptor to define the properties of the different flash chips
184 * supported. The BIOS (or the ME?) is responsible to populate the ICH registers
185 * with the information from the descriptor on startup depending on the actual
186 * chip(s) detected. */
187
Stefan Taunerbd649e42011-07-01 00:39:16 +0000188#define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */
189#define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */
190#define FPB_FPBA (0x1FFF << FPB_FPBA_OFF)
191
Dominik Geyerb46acba2008-05-16 12:55:55 +0000192// ICH9R SPI commands
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000193#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
194#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
195#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
196#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
Dominik Geyerb46acba2008-05-16 12:55:55 +0000197
Stefan Reinauera9424d52008-06-27 16:28:34 +0000198// ICH7 registers
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000199#define ICH7_REG_SPIS 0x00 /* 16 Bits */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000200#define SPIS_SCIP 0x0001
201#define SPIS_GRANT 0x0002
202#define SPIS_CDS 0x0004
203#define SPIS_FCERR 0x0008
204#define SPIS_RESERVED_MASK 0x7ff0
Stefan Reinauera9424d52008-06-27 16:28:34 +0000205
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000206/* VIA SPI is compatible with ICH7, but maxdata
207 to transfer is 16 bytes.
208
209 DATA byte count on ICH7 is 8:13, on VIA 8:11
210
211 bit 12 is port select CS0 CS1
212 bit 13 is FAST READ enable
213 bit 7 is used with fast read and one shot controls CS de-assert?
214*/
215
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000216#define ICH7_REG_SPIC 0x02 /* 16 Bits */
217#define SPIC_SCGO 0x0002
218#define SPIC_ACS 0x0004
219#define SPIC_SPOP 0x0008
220#define SPIC_DS 0x4000
Stefan Reinauera9424d52008-06-27 16:28:34 +0000221
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000222#define ICH7_REG_SPIA 0x04 /* 32 Bits */
223#define ICH7_REG_SPID0 0x08 /* 64 Bytes */
224#define ICH7_REG_PREOP 0x54 /* 16 Bits */
225#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
226#define ICH7_REG_OPMENU 0x58 /* 64 Bits */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000227
Nico Huber7590d1a2016-05-03 13:38:28 +0200228enum ich_access_protection {
229 NO_PROT = 0,
230 READ_PROT = 1,
231 WRITE_PROT = 2,
232 LOCKED = 3,
233};
234
FENG yu ningc05a2952008-12-08 18:16:58 +0000235/* ICH SPI configuration lock-down. May be set during chipset enabling. */
Felix Singer8cfc7372022-08-19 03:10:29 +0200236static bool ichspi_lock = false;
FENG yu ningc05a2952008-12-08 18:16:58 +0000237
Stefan Taunera8d838d2011-11-06 23:51:09 +0000238static enum ich_chipset ich_generation = CHIPSET_ICH_UNKNOWN;
Nico Hubered098d62017-04-21 23:47:08 +0200239static uint32_t ichspi_bbar;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000240
Michael Karchera4448d92010-07-22 18:04:15 +0000241static void *ich_spibar = NULL;
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000242
Dominik Geyerb46acba2008-05-16 12:55:55 +0000243typedef struct _OPCODE {
244 uint8_t opcode; //This commands spi opcode
245 uint8_t spi_type; //This commands spi type
246 uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1
247} OPCODE;
248
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000249/* Suggested opcode definition:
Dominik Geyerb46acba2008-05-16 12:55:55 +0000250 * Preop 1: Write Enable
251 * Preop 2: Write Status register enable
252 *
253 * OP 0: Write address
254 * OP 1: Read Address
255 * OP 2: ERASE block
256 * OP 3: Read Status register
257 * OP 4: Read ID
258 * OP 5: Write Status register
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000259 * OP 6: chip private (read JEDEC id)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000260 * OP 7: Chip erase
261 */
262typedef struct _OPCODES {
263 uint8_t preop[2];
264 OPCODE opcode[8];
265} OPCODES;
266
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000267static OPCODES *curopcodes = NULL;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000268
269/* HW access functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000270static uint32_t REGREAD32(int X)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000271{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000272 return mmio_readl(ich_spibar + X);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000273}
274
Uwe Hermann09e04f72009-05-16 22:36:00 +0000275static uint16_t REGREAD16(int X)
Stefan Reinauera9424d52008-06-27 16:28:34 +0000276{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000277 return mmio_readw(ich_spibar + X);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000278}
279
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000280static uint16_t REGREAD8(int X)
281{
282 return mmio_readb(ich_spibar + X);
283}
284
Stefan Taunerccd92a12011-07-01 00:39:01 +0000285#define REGWRITE32(off, val) mmio_writel(val, ich_spibar+(off))
286#define REGWRITE16(off, val) mmio_writew(val, ich_spibar+(off))
287#define REGWRITE8(off, val) mmio_writeb(val, ich_spibar+(off))
Dominik Geyerb46acba2008-05-16 12:55:55 +0000288
Dominik Geyerb46acba2008-05-16 12:55:55 +0000289/* Common SPI functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000290static int find_opcode(OPCODES *op, uint8_t opcode);
291static int find_preop(OPCODES *op, uint8_t preop);
FENG yu ningf041e9b2008-12-15 02:32:11 +0000292static int generate_opcodes(OPCODES * op);
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000293static int program_opcodes(OPCODES *op, int enable_undo);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000294static int run_opcode(const struct flashctx *flash, OPCODE op, uint32_t offset,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000295 uint8_t datalength, uint8_t * data);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000296
FENG yu ningf041e9b2008-12-15 02:32:11 +0000297/* for pairing opcodes with their required preop */
298struct preop_opcode_pair {
299 uint8_t preop;
300 uint8_t opcode;
301};
302
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000303/* List of opcodes which need preopcodes and matching preopcodes. Unused. */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000304const struct preop_opcode_pair pops[] = {
FENG yu ningf041e9b2008-12-15 02:32:11 +0000305 {JEDEC_WREN, JEDEC_BYTE_PROGRAM},
306 {JEDEC_WREN, JEDEC_SE}, /* sector erase */
307 {JEDEC_WREN, JEDEC_BE_52}, /* block erase */
308 {JEDEC_WREN, JEDEC_BE_D8}, /* block erase */
309 {JEDEC_WREN, JEDEC_CE_60}, /* chip erase */
310 {JEDEC_WREN, JEDEC_CE_C7}, /* chip erase */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000311 /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */
312 {JEDEC_WREN, JEDEC_WRSR},
FENG yu ningf041e9b2008-12-15 02:32:11 +0000313 {JEDEC_EWSR, JEDEC_WRSR},
314 {0,}
315};
316
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000317/* Reasonable default configuration. Needs ad-hoc modifications if we
318 * encounter unlisted opcodes. Fun.
319 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000320static OPCODES O_ST_M25P = {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000321 {
322 JEDEC_WREN,
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000323 JEDEC_EWSR,
324 },
Dominik Geyerb46acba2008-05-16 12:55:55 +0000325 {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000326 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000327 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
David Hendricks15f539c2010-08-26 21:27:17 -0700328 {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000329 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
Carl-Daniel Hailfinger15aa7c62009-05-26 21:25:08 +0000330 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000331 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000332 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000333 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
334 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000335};
336
Helge Wagner738e2522010-10-05 22:06:05 +0000337/* List of opcodes with their corresponding spi_type
338 * It is used to reprogram the chipset OPCODE table on-the-fly if an opcode
339 * is needed which is currently not in the chipset OPCODE table
340 */
341static OPCODE POSSIBLE_OPCODES[] = {
342 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
343 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
344 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
345 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
346 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
347 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
348 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
349 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
350 {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Sector erase
351 {JEDEC_BE_52, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Block erase
352 {JEDEC_AAI_WORD_PROGRAM, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Auto Address Increment
353};
354
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000355static OPCODES O_EXISTING = {};
FENG yu ningc05a2952008-12-08 18:16:58 +0000356
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000357/* pretty printing functions */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000358static void prettyprint_opcodes(OPCODES *ops)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000359{
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000360 OPCODE oc;
361 const char *t;
362 const char *a;
363 uint8_t i;
364 static const char *const spi_type[4] = {
365 "read w/o addr",
366 "write w/o addr",
367 "read w/ addr",
368 "write w/ addr"
369 };
370 static const char *const atomic_type[3] = {
371 "none",
372 " 0 ",
373 " 1 "
374 };
375
376 if (ops == NULL)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000377 return;
378
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000379 msg_pdbg2(" OP Type Pre-OP\n");
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000380 for (i = 0; i < 8; i++) {
381 oc = ops->opcode[i];
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000382 t = (oc.spi_type > 3) ? "invalid" : spi_type[oc.spi_type];
383 a = (oc.atomic > 2) ? "invalid" : atomic_type[oc.atomic];
384 msg_pdbg2("op[%d]: 0x%02x, %s, %s\n", i, oc.opcode, t, a);
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000385 }
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000386 msg_pdbg2("Pre-OP 0: 0x%02x, Pre-OP 1: 0x%02x\n", ops->preop[0],
387 ops->preop[1]);
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000388}
389
Nico Huberd54e4f42017-03-23 23:45:47 +0100390#define _pprint_reg(bit, mask, off, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & mask) >> off)
391#define pprint_reg(reg, bit, val, sep) _pprint_reg(bit, reg##_##bit, reg##_##bit##_OFF, val, sep)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000392
Stefan Tauner55206942011-06-11 09:53:22 +0000393static void prettyprint_ich9_reg_hsfs(uint16_t reg_val)
394{
395 msg_pdbg("HSFS: ");
396 pprint_reg(HSFS, FDONE, reg_val, ", ");
397 pprint_reg(HSFS, FCERR, reg_val, ", ");
398 pprint_reg(HSFS, AEL, reg_val, ", ");
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200399 switch (ich_generation) {
400 case CHIPSET_100_SERIES_SUNRISE_POINT:
401 case CHIPSET_C620_SERIES_LEWISBURG:
402 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200403 case CHIPSET_500_SERIES_TIGER_POINT:
Werner Zehe57d4e42022-01-03 09:44:29 +0100404 case CHIPSET_ELKHART_LAKE:
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200405 break;
406 default:
Nico Huberd54e4f42017-03-23 23:45:47 +0100407 pprint_reg(HSFS, BERASE, reg_val, ", ");
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200408 break;
Nico Huberd54e4f42017-03-23 23:45:47 +0100409 }
Stefan Tauner55206942011-06-11 09:53:22 +0000410 pprint_reg(HSFS, SCIP, reg_val, ", ");
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200411 switch (ich_generation) {
412 case CHIPSET_100_SERIES_SUNRISE_POINT:
413 case CHIPSET_C620_SERIES_LEWISBURG:
414 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200415 case CHIPSET_500_SERIES_TIGER_POINT:
Werner Zehe57d4e42022-01-03 09:44:29 +0100416 case CHIPSET_ELKHART_LAKE:
Nico Huberd54e4f42017-03-23 23:45:47 +0100417 pprint_reg(HSFS, PRR34_LOCKDN, reg_val, ", ");
418 pprint_reg(HSFS, WRSDIS, reg_val, ", ");
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200419 break;
420 default:
421 break;
Nico Huberd54e4f42017-03-23 23:45:47 +0100422 }
Stefan Tauner55206942011-06-11 09:53:22 +0000423 pprint_reg(HSFS, FDOPSS, reg_val, ", ");
424 pprint_reg(HSFS, FDV, reg_val, ", ");
425 pprint_reg(HSFS, FLOCKDN, reg_val, "\n");
426}
427
428static void prettyprint_ich9_reg_hsfc(uint16_t reg_val)
429{
430 msg_pdbg("HSFC: ");
431 pprint_reg(HSFC, FGO, reg_val, ", ");
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200432 switch (ich_generation) {
433 case CHIPSET_100_SERIES_SUNRISE_POINT:
434 case CHIPSET_C620_SERIES_LEWISBURG:
435 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200436 case CHIPSET_500_SERIES_TIGER_POINT:
Werner Zehe57d4e42022-01-03 09:44:29 +0100437 case CHIPSET_ELKHART_LAKE:
Nico Huberd54e4f42017-03-23 23:45:47 +0100438 _pprint_reg(HSFC, PCH100_HSFC_FCYCLE, PCH100_HSFC_FCYCLE_OFF, reg_val, ", ");
439 pprint_reg(HSFC, WET, reg_val, ", ");
Nico Huber2a5dfaf2019-07-04 16:01:51 +0200440 break;
441 default:
442 pprint_reg(HSFC, FCYCLE, reg_val, ", ");
443 break;
Nico Huberd54e4f42017-03-23 23:45:47 +0100444 }
Stefan Tauner55206942011-06-11 09:53:22 +0000445 pprint_reg(HSFC, FDBC, reg_val, ", ");
446 pprint_reg(HSFC, SME, reg_val, "\n");
447}
448
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000449static void prettyprint_ich9_reg_ssfs(uint32_t reg_val)
450{
451 msg_pdbg("SSFS: ");
452 pprint_reg(SSFS, SCIP, reg_val, ", ");
453 pprint_reg(SSFS, FDONE, reg_val, ", ");
454 pprint_reg(SSFS, FCERR, reg_val, ", ");
455 pprint_reg(SSFS, AEL, reg_val, "\n");
456}
457
458static void prettyprint_ich9_reg_ssfc(uint32_t reg_val)
459{
460 msg_pdbg("SSFC: ");
461 pprint_reg(SSFC, SCGO, reg_val, ", ");
462 pprint_reg(SSFC, ACS, reg_val, ", ");
463 pprint_reg(SSFC, SPOP, reg_val, ", ");
464 pprint_reg(SSFC, COP, reg_val, ", ");
465 pprint_reg(SSFC, DBC, reg_val, ", ");
466 pprint_reg(SSFC, SME, reg_val, ", ");
467 pprint_reg(SSFC, SCF, reg_val, "\n");
468}
469
Nico Huberd54e4f42017-03-23 23:45:47 +0100470static void prettyprint_pch100_reg_dlock(const uint32_t reg_val)
471{
472 msg_pdbg("DLOCK: ");
473 pprint_reg(DLOCK, BMWAG_LOCKDN, reg_val, ", ");
474 pprint_reg(DLOCK, BMRAG_LOCKDN, reg_val, ", ");
475 pprint_reg(DLOCK, SBMWAG_LOCKDN, reg_val, ", ");
476 pprint_reg(DLOCK, SBMRAG_LOCKDN, reg_val, ",\n ");
477 pprint_reg(DLOCK, PR0_LOCKDN, reg_val, ", ");
478 pprint_reg(DLOCK, PR1_LOCKDN, reg_val, ", ");
479 pprint_reg(DLOCK, PR2_LOCKDN, reg_val, ", ");
480 pprint_reg(DLOCK, PR3_LOCKDN, reg_val, ", ");
481 pprint_reg(DLOCK, PR4_LOCKDN, reg_val, ",\n ");
482 pprint_reg(DLOCK, SSEQ_LOCKDN, reg_val, "\n");
483}
484
485static struct {
486 size_t reg_ssfsc;
487 size_t reg_preop;
488 size_t reg_optype;
489 size_t reg_opmenu;
490} swseq_data;
491
Helge Wagner738e2522010-10-05 22:06:05 +0000492static uint8_t lookup_spi_type(uint8_t opcode)
493{
Nico Huber519be662018-12-23 20:03:35 +0100494 unsigned int a;
Helge Wagner738e2522010-10-05 22:06:05 +0000495
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000496 for (a = 0; a < ARRAY_SIZE(POSSIBLE_OPCODES); a++) {
Helge Wagner738e2522010-10-05 22:06:05 +0000497 if (POSSIBLE_OPCODES[a].opcode == opcode)
498 return POSSIBLE_OPCODES[a].spi_type;
499 }
500
501 return 0xFF;
502}
503
504static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt)
505{
506 uint8_t spi_type;
507
508 spi_type = lookup_spi_type(opcode);
509 if (spi_type > 3) {
510 /* Try to guess spi type from read/write sizes.
511 * The following valid writecnt/readcnt combinations exist:
512 * writecnt = 4, readcnt >= 0
513 * writecnt = 1, readcnt >= 0
514 * writecnt >= 4, readcnt = 0
515 * writecnt >= 1, readcnt = 0
516 * writecnt >= 1 is guaranteed for all commands.
517 */
518 if (readcnt == 0)
519 /* if readcnt=0 and writecount >= 4, we don't know if it is WRITE_NO_ADDRESS
520 * or WRITE_WITH_ADDRESS. But if we use WRITE_NO_ADDRESS and the first 3 data
521 * bytes are actual the address, they go to the bus anyhow
522 */
523 spi_type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
524 else if (writecnt == 1) // and readcnt is > 0
525 spi_type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
526 else if (writecnt == 4) // and readcnt is > 0
527 spi_type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
Stefan Taunerdc704ed2012-05-06 15:11:26 +0000528 else // we have an invalid case
529 return SPI_INVALID_LENGTH;
Helge Wagner738e2522010-10-05 22:06:05 +0000530 }
Stefan Taunerdc704ed2012-05-06 15:11:26 +0000531 int oppos = 2; // use original JEDEC_BE_D8 offset
532 curopcodes->opcode[oppos].opcode = opcode;
533 curopcodes->opcode[oppos].spi_type = spi_type;
534 program_opcodes(curopcodes, 0);
535 oppos = find_opcode(curopcodes, opcode);
Stefan Taunerd94d25d2012-07-28 03:17:15 +0000536 msg_pdbg2("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos);
Stefan Taunerdc704ed2012-05-06 15:11:26 +0000537 return oppos;
Helge Wagner738e2522010-10-05 22:06:05 +0000538}
539
Uwe Hermann09e04f72009-05-16 22:36:00 +0000540static int find_opcode(OPCODES *op, uint8_t opcode)
FENG yu ningc05a2952008-12-08 18:16:58 +0000541{
542 int a;
543
Stefan Tauner50e7c602011-11-08 10:55:54 +0000544 if (op == NULL) {
545 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
546 return -1;
547 }
548
FENG yu ningc05a2952008-12-08 18:16:58 +0000549 for (a = 0; a < 8; a++) {
550 if (op->opcode[a].opcode == opcode)
551 return a;
552 }
553
554 return -1;
555}
556
Uwe Hermann09e04f72009-05-16 22:36:00 +0000557static int find_preop(OPCODES *op, uint8_t preop)
FENG yu ningc05a2952008-12-08 18:16:58 +0000558{
559 int a;
560
Stefan Tauner50e7c602011-11-08 10:55:54 +0000561 if (op == NULL) {
562 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
563 return -1;
564 }
565
FENG yu ningc05a2952008-12-08 18:16:58 +0000566 for (a = 0; a < 2; a++) {
567 if (op->preop[a] == preop)
568 return a;
569 }
570
571 return -1;
572}
573
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000574/* Create a struct OPCODES based on what we find in the locked down chipset. */
FENG yu ningf041e9b2008-12-15 02:32:11 +0000575static int generate_opcodes(OPCODES * op)
FENG yu ningc05a2952008-12-08 18:16:58 +0000576{
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000577 int a;
FENG yu ningc05a2952008-12-08 18:16:58 +0000578 uint16_t preop, optype;
579 uint32_t opmenu[2];
FENG yu ningc05a2952008-12-08 18:16:58 +0000580
581 if (op == NULL) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000582 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
FENG yu ningc05a2952008-12-08 18:16:58 +0000583 return -1;
584 }
585
Stefan Taunera8d838d2011-11-06 23:51:09 +0000586 switch (ich_generation) {
587 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000588 case CHIPSET_TUNNEL_CREEK:
589 case CHIPSET_CENTERTON:
FENG yu ningc05a2952008-12-08 18:16:58 +0000590 preop = REGREAD16(ICH7_REG_PREOP);
591 optype = REGREAD16(ICH7_REG_OPTYPE);
592 opmenu[0] = REGREAD32(ICH7_REG_OPMENU);
593 opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4);
594 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000595 case CHIPSET_ICH8:
596 default: /* Future version might behave the same */
Nico Huberd54e4f42017-03-23 23:45:47 +0100597 preop = REGREAD16(swseq_data.reg_preop);
598 optype = REGREAD16(swseq_data.reg_optype);
599 opmenu[0] = REGREAD32(swseq_data.reg_opmenu);
600 opmenu[1] = REGREAD32(swseq_data.reg_opmenu + 4);
FENG yu ningc05a2952008-12-08 18:16:58 +0000601 break;
FENG yu ningc05a2952008-12-08 18:16:58 +0000602 }
603
604 op->preop[0] = (uint8_t) preop;
605 op->preop[1] = (uint8_t) (preop >> 8);
606
607 for (a = 0; a < 8; a++) {
608 op->opcode[a].spi_type = (uint8_t) (optype & 0x3);
609 optype >>= 2;
610 }
611
612 for (a = 0; a < 4; a++) {
613 op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff);
614 opmenu[0] >>= 8;
615 }
616
617 for (a = 4; a < 8; a++) {
618 op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff);
619 opmenu[1] >>= 8;
620 }
621
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000622 /* No preopcodes used by default. */
623 for (a = 0; a < 8; a++)
FENG yu ningc05a2952008-12-08 18:16:58 +0000624 op->opcode[a].atomic = 0;
625
FENG yu ningc05a2952008-12-08 18:16:58 +0000626 return 0;
627}
628
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000629static int program_opcodes(OPCODES *op, int enable_undo)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000630{
631 uint8_t a;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000632 uint16_t preop, optype;
633 uint32_t opmenu[2];
Dominik Geyerb46acba2008-05-16 12:55:55 +0000634
635 /* Program Prefix Opcodes */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000636 /* 0:7 Prefix Opcode 1 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000637 preop = (op->preop[0]);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000638 /* 8:16 Prefix Opcode 2 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000639 preop |= ((uint16_t) op->preop[1]) << 8;
Uwe Hermann394131e2008-10-18 21:14:13 +0000640
Stefan Reinauera9424d52008-06-27 16:28:34 +0000641 /* Program Opcode Types 0 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000642 optype = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000643 for (a = 0; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000644 optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000645 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000646
Stefan Reinauera9424d52008-06-27 16:28:34 +0000647 /* Program Allowable Opcodes 0 - 3 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000648 opmenu[0] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000649 for (a = 0; a < 4; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000650 opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000651 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000652
Stefan Tauner92d6a862013-10-25 00:33:37 +0000653 /* Program Allowable Opcodes 4 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000654 opmenu[1] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000655 for (a = 4; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000656 opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000657 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000658
Stefan Taunerd94d25d2012-07-28 03:17:15 +0000659 msg_pdbg2("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]);
Stefan Taunera8d838d2011-11-06 23:51:09 +0000660 switch (ich_generation) {
661 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000662 case CHIPSET_TUNNEL_CREEK:
663 case CHIPSET_CENTERTON:
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000664 /* Register undo only for enable_undo=1, i.e. first call. */
665 if (enable_undo) {
666 rmmio_valw(ich_spibar + ICH7_REG_PREOP);
667 rmmio_valw(ich_spibar + ICH7_REG_OPTYPE);
668 rmmio_vall(ich_spibar + ICH7_REG_OPMENU);
669 rmmio_vall(ich_spibar + ICH7_REG_OPMENU + 4);
670 }
671 mmio_writew(preop, ich_spibar + ICH7_REG_PREOP);
672 mmio_writew(optype, ich_spibar + ICH7_REG_OPTYPE);
673 mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU);
674 mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000675 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000676 case CHIPSET_ICH8:
677 default: /* Future version might behave the same */
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000678 /* Register undo only for enable_undo=1, i.e. first call. */
679 if (enable_undo) {
Nico Huberd54e4f42017-03-23 23:45:47 +0100680 rmmio_valw(ich_spibar + swseq_data.reg_preop);
681 rmmio_valw(ich_spibar + swseq_data.reg_optype);
682 rmmio_vall(ich_spibar + swseq_data.reg_opmenu);
683 rmmio_vall(ich_spibar + swseq_data.reg_opmenu + 4);
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000684 }
Nico Huberd54e4f42017-03-23 23:45:47 +0100685 mmio_writew(preop, ich_spibar + swseq_data.reg_preop);
686 mmio_writew(optype, ich_spibar + swseq_data.reg_optype);
687 mmio_writel(opmenu[0], ich_spibar + swseq_data.reg_opmenu);
688 mmio_writel(opmenu[1], ich_spibar + swseq_data.reg_opmenu + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000689 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000690 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000691
692 return 0;
693}
694
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000695/*
Stefan Tauner50e7c602011-11-08 10:55:54 +0000696 * Returns -1 if at least one mandatory opcode is inaccessible, 0 otherwise.
697 * FIXME: this should also check for
698 * - at least one probing opcode (RDID (incl. AT25F variants?), REMS, RES?)
699 * - at least one erasing opcode (lots.)
700 * - at least one program opcode (BYTE_PROGRAM, AAI_WORD_PROGRAM, ...?)
701 * - necessary preops? (EWSR, WREN, ...?)
702 */
Richard Hughes93e16252018-12-19 11:54:47 +0000703static int ich_missing_opcodes(void)
Stefan Tauner50e7c602011-11-08 10:55:54 +0000704{
705 uint8_t ops[] = {
706 JEDEC_READ,
707 JEDEC_RDSR,
708 0
709 };
710 int i = 0;
711 while (ops[i] != 0) {
712 msg_pspew("checking for opcode 0x%02x\n", ops[i]);
713 if (find_opcode(curopcodes, ops[i]) == -1)
714 return -1;
715 i++;
716 }
717 return 0;
718}
719
720/*
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000721 * Try to set BBAR (BIOS Base Address Register), but read back the value in case
722 * it didn't stick.
723 */
Stefan Taunera8d838d2011-11-06 23:51:09 +0000724static void ich_set_bbar(uint32_t min_addr)
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000725{
Stefan Taunere27b2d42011-07-01 00:39:09 +0000726 int bbar_off;
Stefan Tauner7783f312011-09-17 21:21:42 +0000727 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +0000728 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000729 case CHIPSET_TUNNEL_CREEK:
730 case CHIPSET_CENTERTON:
Stefan Taunere27b2d42011-07-01 00:39:09 +0000731 bbar_off = 0x50;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000732 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000733 case CHIPSET_ICH8:
Duncan Laurie4095ed72014-08-20 15:39:32 +0000734 case CHIPSET_BAYTRAIL:
735 msg_pdbg("BBAR offset is unknown!\n");
Stefan Tauner7783f312011-09-17 21:21:42 +0000736 return;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000737 case CHIPSET_ICH9:
Stefan Tauner7783f312011-09-17 21:21:42 +0000738 default: /* Future version might behave the same */
Stefan Taunere27b2d42011-07-01 00:39:09 +0000739 bbar_off = ICH9_REG_BBAR;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000740 break;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000741 }
Elyes HAOUAS124ef382018-03-27 12:15:09 +0200742
Stefan Taunere27b2d42011-07-01 00:39:09 +0000743 ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK;
744 if (ichspi_bbar) {
745 msg_pdbg("Reserved bits in BBAR not zero: 0x%08x\n",
746 ichspi_bbar);
747 }
748 min_addr &= BBAR_MASK;
749 ichspi_bbar |= min_addr;
750 rmmio_writel(ichspi_bbar, ich_spibar + bbar_off);
751 ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & BBAR_MASK;
752
753 /* We don't have any option except complaining. And if the write
754 * failed, the restore will fail as well, so no problem there.
755 */
756 if (ichspi_bbar != min_addr)
Stefan Tauner7783f312011-09-17 21:21:42 +0000757 msg_perr("Setting BBAR to 0x%08x failed! New value: 0x%08x.\n",
758 min_addr, ichspi_bbar);
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000759}
760
Stefan Tauner8b391b82011-08-09 01:49:34 +0000761/* Read len bytes from the fdata/spid register into the data array.
762 *
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000763 * Note that using len > flash->mst->spi.max_data_read will return garbage or
Stefan Tauner8b391b82011-08-09 01:49:34 +0000764 * may even crash.
765 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000766static void ich_read_data(uint8_t *data, int len, int reg0_off)
Elyes HAOUAS124ef382018-03-27 12:15:09 +0200767{
Stefan Tauner8b391b82011-08-09 01:49:34 +0000768 int i;
769 uint32_t temp32 = 0;
770
771 for (i = 0; i < len; i++) {
772 if ((i % 4) == 0)
773 temp32 = REGREAD32(reg0_off + i);
774
775 data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
776 }
777}
778
779/* Fill len bytes from the data array into the fdata/spid registers.
780 *
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000781 * Note that using len > flash->mst->spi.max_data_write will trash the registers
Stefan Tauner8b391b82011-08-09 01:49:34 +0000782 * following the data registers.
783 */
784static void ich_fill_data(const uint8_t *data, int len, int reg0_off)
785{
786 uint32_t temp32 = 0;
787 int i;
788
789 if (len <= 0)
790 return;
791
792 for (i = 0; i < len; i++) {
793 if ((i % 4) == 0)
794 temp32 = 0;
795
796 temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
797
798 if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
799 REGWRITE32(reg0_off + (i - (i % 4)), temp32);
800 }
801 i--;
802 if ((i % 4) != 3) /* Write remaining data to regs. */
803 REGWRITE32(reg0_off + (i - (i % 4)), temp32);
804}
805
FENG yu ningf041e9b2008-12-15 02:32:11 +0000806/* This function generates OPCODES from or programs OPCODES to ICH according to
807 * the chipset's SPI configuration lock.
FENG yu ningc05a2952008-12-08 18:16:58 +0000808 *
FENG yu ningf041e9b2008-12-15 02:32:11 +0000809 * It should be called before ICH sends any spi command.
FENG yu ningc05a2952008-12-08 18:16:58 +0000810 */
Michael Karchera4448d92010-07-22 18:04:15 +0000811static int ich_init_opcodes(void)
FENG yu ningc05a2952008-12-08 18:16:58 +0000812{
813 int rc = 0;
814 OPCODES *curopcodes_done;
815
816 if (curopcodes)
817 return 0;
818
819 if (ichspi_lock) {
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000820 msg_pdbg("Reading OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000821 curopcodes_done = &O_EXISTING;
FENG yu ningf041e9b2008-12-15 02:32:11 +0000822 rc = generate_opcodes(curopcodes_done);
FENG yu ningc05a2952008-12-08 18:16:58 +0000823 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000824 msg_pdbg("Programming OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000825 curopcodes_done = &O_ST_M25P;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000826 rc = program_opcodes(curopcodes_done, 1);
FENG yu ningc05a2952008-12-08 18:16:58 +0000827 }
828
829 if (rc) {
830 curopcodes = NULL;
Sean Nelson316a29f2010-05-07 20:09:04 +0000831 msg_perr("failed\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000832 return 1;
833 } else {
834 curopcodes = curopcodes_done;
Sean Nelson316a29f2010-05-07 20:09:04 +0000835 msg_pdbg("done\n");
Stefan Tauner8b391b82011-08-09 01:49:34 +0000836 prettyprint_opcodes(curopcodes);
FENG yu ningc05a2952008-12-08 18:16:58 +0000837 return 0;
838 }
839}
840
Stefan Reinauer43119562008-11-02 19:51:50 +0000841static int ich7_run_opcode(OPCODE op, uint32_t offset,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000842 uint8_t datalength, uint8_t * data, int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000843{
Felix Singer8cfc7372022-08-19 03:10:29 +0200844 bool write_cmd = false;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000845 int timeout;
Stefan Tauner8b391b82011-08-09 01:49:34 +0000846 uint32_t temp32;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000847 uint16_t temp16;
Stefan Reinauer43119562008-11-02 19:51:50 +0000848 uint64_t opmenu;
849 int opcode_index;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000850
851 /* Is it a write command? */
852 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
853 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
Felix Singer8cfc7372022-08-19 03:10:29 +0200854 write_cmd = true;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000855 }
856
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000857 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
858 while ((REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) && --timeout) {
859 programmer_delay(10);
860 }
861 if (!timeout) {
862 msg_perr("Error: SCIP never cleared!\n");
863 return 1;
864 }
865
Stefan Tauner10b3e222011-07-01 00:39:23 +0000866 /* Program offset in flash into SPIA while preserving reserved bits. */
867 temp32 = REGREAD32(ICH7_REG_SPIA) & ~0x00FFFFFF;
868 REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000869
Stefan Tauner10b3e222011-07-01 00:39:23 +0000870 /* Program data into SPID0 to N */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000871 if (write_cmd && (datalength != 0))
872 ich_fill_data(data, datalength, ICH7_REG_SPID0);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000873
874 /* Assemble SPIS */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000875 temp16 = REGREAD16(ICH7_REG_SPIS);
876 /* keep reserved bits */
877 temp16 &= SPIS_RESERVED_MASK;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000878 /* clear error status registers */
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000879 temp16 |= (SPIS_CDS | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000880 REGWRITE16(ICH7_REG_SPIS, temp16);
881
882 /* Assemble SPIC */
883 temp16 = 0;
884
885 if (datalength != 0) {
886 temp16 |= SPIC_DS;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000887 temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000888 }
889
890 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000891 opmenu = REGREAD32(ICH7_REG_OPMENU);
892 opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32;
893
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000894 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
895 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000896 break;
897 }
898 opmenu >>= 8;
899 }
900 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000901 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000902 return 1;
903 }
904 temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000905
Michael Karcher136125a2011-04-29 22:11:36 +0000906 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
907 /* Handle Atomic. Atomic commands include three steps:
908 - sending the preop (mainly EWSR or WREN)
909 - sending the main command
910 - waiting for the busy bit (WIP) to be cleared
911 This means the timeout must be sufficient for chip erase
912 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000913 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000914 switch (op.atomic) {
915 case 2:
916 /* Select second preop. */
917 temp16 |= SPIC_SPOP;
Richard Hughesdb7482b2018-12-19 12:04:30 +0000918 /* Fall through. */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000919 case 1:
920 /* Atomic command (preop+op) */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000921 temp16 |= SPIC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +0000922 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000923 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000924 }
925
926 /* Start */
927 temp16 |= SPIC_SCGO;
928
929 /* write it */
930 REGWRITE16(ICH7_REG_SPIC, temp16);
931
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000932 /* Wait for Cycle Done Status or Flash Cycle Error. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000933 while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) &&
934 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000935 programmer_delay(10);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000936 }
937 if (!timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000938 msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n",
939 REGREAD16(ICH7_REG_SPIS));
940 return 1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000941 }
942
Sean Nelson316a29f2010-05-07 20:09:04 +0000943 /* FIXME: make sure we do not needlessly cause transaction errors. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000944 temp16 = REGREAD16(ICH7_REG_SPIS);
945 if (temp16 & SPIS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +0000946 msg_perr("Transaction error!\n");
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000947 /* keep reserved bits */
948 temp16 &= SPIS_RESERVED_MASK;
949 REGWRITE16(ICH7_REG_SPIS, temp16 | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000950 return 1;
951 }
952
Stefan Tauner8b391b82011-08-09 01:49:34 +0000953 if ((!write_cmd) && (datalength != 0))
954 ich_read_data(data, datalength, ICH7_REG_SPID0);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000955
956 return 0;
957}
958
Stefan Reinauer43119562008-11-02 19:51:50 +0000959static int ich9_run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000960 uint8_t datalength, uint8_t * data)
961{
Felix Singer8cfc7372022-08-19 03:10:29 +0200962 bool write_cmd = false;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000963 int timeout;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000964 uint32_t temp32;
Stefan Reinauer43119562008-11-02 19:51:50 +0000965 uint64_t opmenu;
966 int opcode_index;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000967
968 /* Is it a write command? */
969 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
970 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
Felix Singer8cfc7372022-08-19 03:10:29 +0200971 write_cmd = true;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000972 }
973
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000974 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
Nico Huberd54e4f42017-03-23 23:45:47 +0100975 while ((REGREAD8(swseq_data.reg_ssfsc) & SSFS_SCIP) && --timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000976 programmer_delay(10);
977 }
978 if (!timeout) {
979 msg_perr("Error: SCIP never cleared!\n");
980 return 1;
981 }
982
Stefan Tauner10b3e222011-07-01 00:39:23 +0000983 /* Program offset in flash into FADDR while preserve the reserved bits
Martin Rothf6c1cb12022-03-15 10:55:25 -0600984 * and clearing the 25. address bit which is only usable in hwseq. */
Stefan Tauner10b3e222011-07-01 00:39:23 +0000985 temp32 = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF;
986 REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000987
988 /* Program data into FDATA0 to N */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000989 if (write_cmd && (datalength != 0))
990 ich_fill_data(data, datalength, ICH9_REG_FDATA0);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000991
992 /* Assemble SSFS + SSFC */
Nico Huberd54e4f42017-03-23 23:45:47 +0100993 temp32 = REGREAD32(swseq_data.reg_ssfsc);
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000994 /* Keep reserved bits only */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000995 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000996 /* Clear cycle done and cycle error status registers */
997 temp32 |= (SSFS_FDONE | SSFS_FCERR);
Nico Huberd54e4f42017-03-23 23:45:47 +0100998 REGWRITE32(swseq_data.reg_ssfsc, temp32);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000999
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001000 /* Use 20 MHz */
Dominik Geyerb46acba2008-05-16 12:55:55 +00001001 temp32 |= SSFC_SCF_20MHZ;
1002
Stefan Taunerc0aaf952011-05-19 02:58:17 +00001003 /* Set data byte count (DBC) and data cycle bit (DS) */
Dominik Geyerb46acba2008-05-16 12:55:55 +00001004 if (datalength != 0) {
1005 uint32_t datatemp;
1006 temp32 |= SSFC_DS;
Stefan Tauner0c1ec452011-06-11 09:53:09 +00001007 datatemp = ((((uint32_t)datalength - 1) << SSFC_DBC_OFF) &
1008 SSFC_DBC);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001009 temp32 |= datatemp;
1010 }
1011
1012 /* Select opcode */
Nico Huber8b2152d2017-08-31 13:18:49 +02001013 opmenu = REGREAD32(swseq_data.reg_opmenu);
1014 opmenu |= ((uint64_t)REGREAD32(swseq_data.reg_opmenu + 4)) << 32;
Stefan Reinauer43119562008-11-02 19:51:50 +00001015
Uwe Hermann7b2969b2009-04-15 10:52:49 +00001016 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
1017 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +00001018 break;
1019 }
1020 opmenu >>= 8;
1021 }
1022 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001023 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +00001024 return 1;
1025 }
1026 temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001027
Michael Karcher136125a2011-04-29 22:11:36 +00001028 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
1029 /* Handle Atomic. Atomic commands include three steps:
1030 - sending the preop (mainly EWSR or WREN)
1031 - sending the main command
1032 - waiting for the busy bit (WIP) to be cleared
1033 This means the timeout must be sufficient for chip erase
1034 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +00001035 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001036 switch (op.atomic) {
1037 case 2:
1038 /* Select second preop. */
1039 temp32 |= SSFC_SPOP;
Richard Hughesdb7482b2018-12-19 12:04:30 +00001040 /* Fall through. */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001041 case 1:
1042 /* Atomic command (preop+op) */
Dominik Geyerb46acba2008-05-16 12:55:55 +00001043 temp32 |= SSFC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +00001044 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001045 break;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001046 }
1047
1048 /* Start */
1049 temp32 |= SSFC_SCGO;
1050
1051 /* write it */
Nico Huberd54e4f42017-03-23 23:45:47 +01001052 REGWRITE32(swseq_data.reg_ssfsc, temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001053
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001054 /* Wait for Cycle Done Status or Flash Cycle Error. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001055 while (((REGREAD32(swseq_data.reg_ssfsc) & (SSFS_FDONE | SSFS_FCERR)) == 0) &&
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001056 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +00001057 programmer_delay(10);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +00001058 }
1059 if (!timeout) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001060 msg_perr("timeout, REG_SSFS=0x%08x\n",
1061 REGREAD32(swseq_data.reg_ssfsc));
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001062 return 1;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001063 }
1064
Sean Nelson316a29f2010-05-07 20:09:04 +00001065 /* FIXME make sure we do not needlessly cause transaction errors. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001066 temp32 = REGREAD32(swseq_data.reg_ssfsc);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001067 if (temp32 & SSFS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +00001068 msg_perr("Transaction error!\n");
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001069 prettyprint_ich9_reg_ssfs(temp32);
1070 prettyprint_ich9_reg_ssfc(temp32);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001071 /* keep reserved bits */
1072 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
1073 /* Clear the transaction error. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001074 REGWRITE32(swseq_data.reg_ssfsc, temp32 | SSFS_FCERR);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001075 return 1;
1076 }
1077
Stefan Tauner8b391b82011-08-09 01:49:34 +00001078 if ((!write_cmd) && (datalength != 0))
1079 ich_read_data(data, datalength, ICH9_REG_FDATA0);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001080
1081 return 0;
1082}
1083
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001084static int run_opcode(const struct flashctx *flash, OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +00001085 uint8_t datalength, uint8_t * data)
1086{
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001087 /* max_data_read == max_data_write for all Intel/VIA SPI masters */
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001088 uint8_t maxlength = flash->mst->spi.max_data_read;
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001089
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +00001090 if (ich_generation == CHIPSET_ICH_UNKNOWN) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001091 msg_perr("%s: unsupported chipset\n", __func__);
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001092 return -1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +00001093 }
Stefan Reinauera9424d52008-06-27 16:28:34 +00001094
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001095 if (datalength > maxlength) {
1096 msg_perr("%s: Internal command size error for "
1097 "opcode 0x%02x, got datalength=%i, want <=%i\n",
1098 __func__, op.opcode, datalength, maxlength);
1099 return SPI_INVALID_LENGTH;
1100 }
1101
Stefan Taunera8d838d2011-11-06 23:51:09 +00001102 switch (ich_generation) {
1103 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +00001104 case CHIPSET_TUNNEL_CREEK:
1105 case CHIPSET_CENTERTON:
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001106 return ich7_run_opcode(op, offset, datalength, data, maxlength);
Stefan Taunera8d838d2011-11-06 23:51:09 +00001107 case CHIPSET_ICH8:
1108 default: /* Future version might behave the same */
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001109 return ich9_run_opcode(op, offset, datalength, data);
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001110 }
Stefan Reinauera9424d52008-06-27 16:28:34 +00001111}
1112
Edward O'Callaghan5eca4272020-04-12 17:27:53 +10001113static int ich_spi_send_command(const struct flashctx *flash, unsigned int writecnt,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001114 unsigned int readcnt,
1115 const unsigned char *writearr,
1116 unsigned char *readarr)
Dominik Geyerb46acba2008-05-16 12:55:55 +00001117{
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001118 int result;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001119 int opcode_index = -1;
1120 const unsigned char cmd = *writearr;
1121 OPCODE *opcode;
1122 uint32_t addr = 0;
1123 uint8_t *data;
1124 int count;
1125
Dominik Geyerb46acba2008-05-16 12:55:55 +00001126 /* find cmd in opcodes-table */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001127 opcode_index = find_opcode(curopcodes, cmd);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001128 if (opcode_index == -1) {
Helge Wagner738e2522010-10-05 22:06:05 +00001129 if (!ichspi_lock)
1130 opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt);
Stefan Taunerdc704ed2012-05-06 15:11:26 +00001131 if (opcode_index == SPI_INVALID_LENGTH) {
1132 msg_pdbg("OPCODE 0x%02x has unsupported length, will not execute.\n", cmd);
1133 return SPI_INVALID_LENGTH;
1134 } else if (opcode_index == -1) {
Stefan Tauner355cbfd2011-05-28 02:37:14 +00001135 msg_pdbg("Invalid OPCODE 0x%02x, will not execute.\n",
1136 cmd);
Helge Wagner738e2522010-10-05 22:06:05 +00001137 return SPI_INVALID_OPCODE;
1138 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001139 }
1140
1141 opcode = &(curopcodes->opcode[opcode_index]);
1142
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001143 /* The following valid writecnt/readcnt combinations exist:
1144 * writecnt = 4, readcnt >= 0
1145 * writecnt = 1, readcnt >= 0
1146 * writecnt >= 4, readcnt = 0
1147 * writecnt >= 1, readcnt = 0
1148 * writecnt >= 1 is guaranteed for all commands.
1149 */
1150 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) &&
1151 (writecnt != 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001152 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001153 "0x%02x, got writecnt=%i, want =4\n", __func__, cmd,
1154 writecnt);
1155 return SPI_INVALID_LENGTH;
1156 }
1157 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) &&
1158 (writecnt != 1)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001159 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001160 "0x%02x, got writecnt=%i, want =1\n", __func__, cmd,
1161 writecnt);
1162 return SPI_INVALID_LENGTH;
1163 }
1164 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) &&
1165 (writecnt < 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001166 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001167 "0x%02x, got writecnt=%i, want >=4\n", __func__, cmd,
1168 writecnt);
1169 return SPI_INVALID_LENGTH;
1170 }
1171 if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1172 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) &&
1173 (readcnt)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001174 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001175 "0x%02x, got readcnt=%i, want =0\n", __func__, cmd,
1176 readcnt);
1177 return SPI_INVALID_LENGTH;
1178 }
1179
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001180 /* Translate read/write array/count.
1181 * The maximum data length is identical for the maximum read length and
1182 * for the maximum write length excluding opcode and address. Opcode and
1183 * address are stored in separate registers, not in the data registers
1184 * and are thus not counted towards data length. The only exception
1185 * applies if the opcode definition (un)intentionally classifies said
1186 * opcode incorrectly as non-address opcode or vice versa. */
Dominik Geyerb46acba2008-05-16 12:55:55 +00001187 if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001188 data = (uint8_t *) (writearr + 1);
1189 count = writecnt - 1;
1190 } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
1191 data = (uint8_t *) (writearr + 4);
1192 count = writecnt - 4;
1193 } else {
1194 data = (uint8_t *) readarr;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001195 count = readcnt;
1196 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001197
Nico Hubered098d62017-04-21 23:47:08 +02001198 /* if opcode-type requires an address */
1199 if (cmd == JEDEC_REMS || cmd == JEDEC_RES) {
1200 addr = ichspi_bbar;
1201 } else if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS ||
1202 opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
1203 /* BBAR may cut part of the chip off at the lower end. */
1204 const uint32_t valid_base = ichspi_bbar & ((flash->chip->total_size * 1024) - 1);
1205 const uint32_t addr_offset = ichspi_bbar - valid_base;
1206 /* Highest address we can program is (2^24 - 1). */
1207 const uint32_t valid_end = (1 << 24) - addr_offset;
1208
1209 addr = writearr[1] << 16 | writearr[2] << 8 | writearr[3];
1210 const uint32_t addr_end = addr + count;
1211
1212 if (addr < valid_base ||
1213 addr_end < addr || /* integer overflow check */
1214 addr_end > valid_end) {
1215 msg_perr("%s: Addressed region 0x%06x-0x%06x not in allowed range 0x%06x-0x%06x\n",
1216 __func__, addr, addr_end - 1, valid_base, valid_end - 1);
1217 return SPI_INVALID_ADDRESS;
1218 }
1219 addr += addr_offset;
1220 }
1221
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001222 result = run_opcode(flash, *opcode, addr, count, data);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001223 if (result) {
Stefan Tauner8ed29342011-04-29 23:53:09 +00001224 msg_pdbg("Running OPCODE 0x%02x failed ", opcode->opcode);
1225 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1226 (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS)) {
1227 msg_pdbg("at address 0x%06x ", addr);
1228 }
1229 msg_pdbg("(payload length was %d).\n", count);
1230
1231 /* Print out the data array if it contains data to write.
1232 * Errors are detected before the received data is read back into
1233 * the array so it won't make sense to print it then. */
1234 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1235 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) {
1236 int i;
1237 msg_pspew("The data was:\n");
Stefan Taunerf382e352011-11-08 11:55:24 +00001238 for (i = 0; i < count; i++){
Stefan Tauner8ed29342011-04-29 23:53:09 +00001239 msg_pspew("%3d: 0x%02x\n", i, data[i]);
1240 }
1241 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001242 }
1243
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001244 return result;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001245}
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001246
Stefan Tauner50e7c602011-11-08 10:55:54 +00001247static struct hwseq_data {
1248 uint32_t size_comp0;
1249 uint32_t size_comp1;
Nico Huberd54e4f42017-03-23 23:45:47 +01001250 uint32_t addr_mask;
1251 bool only_4k;
1252 uint32_t hsfc_fcycle;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001253} hwseq_data;
1254
Nico Huberd54e4f42017-03-23 23:45:47 +01001255/* Sets FLA in FADDR to (addr & hwseq_data.addr_mask) without touching other bits. */
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001256static void ich_hwseq_set_addr(uint32_t addr)
1257{
Nico Huberd54e4f42017-03-23 23:45:47 +01001258 uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~hwseq_data.addr_mask;
1259 REGWRITE32(ICH9_REG_FADDR, (addr & hwseq_data.addr_mask) | addr_old);
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001260}
1261
1262/* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes
1263 * of the block containing this address. May return nonsense if the address is
1264 * not valid. The erase block size for a specific address depends on the flash
1265 * partition layout as specified by FPB and the partition properties as defined
1266 * by UVSCC and LVSCC respectively. An alternative to implement this method
1267 * would be by querying FPB and the respective VSCC register directly.
1268 */
1269static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr)
1270{
Elyes HAOUAS29e46d02019-06-09 17:38:25 +02001271 uint8_t enc_berase;
1272 static const uint32_t dec_berase[4] = {
1273 256,
1274 4 * 1024,
1275 8 * 1024,
1276 64 * 1024
1277 };
1278
Nico Huberd54e4f42017-03-23 23:45:47 +01001279 if (hwseq_data.only_4k) {
1280 return 4 * 1024;
Nico Huberd54e4f42017-03-23 23:45:47 +01001281 }
Elyes HAOUAS29e46d02019-06-09 17:38:25 +02001282
1283 ich_hwseq_set_addr(addr);
1284 enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >> HSFS_BERASE_OFF;
1285 return dec_berase[enc_berase];
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001286}
1287
1288/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
1289 Resets all error flags in HSFS.
1290 Returns 0 if the cycle completes successfully without errors within
1291 timeout us, 1 on errors. */
Subrata Banik7cb43952022-03-16 20:40:42 +05301292static int ich_hwseq_wait_for_cycle_complete(unsigned int len)
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001293{
Subrata Banik7cb43952022-03-16 20:40:42 +05301294 /*
1295 * The SPI bus may be busy due to performing operations from other masters, hence
1296 * introduce the long timeout of 30s to cover the worst case scenarios as well.
1297 */
1298 unsigned int timeout_us = 30 * 1000 * 1000;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001299 uint16_t hsfs;
1300 uint32_t addr;
1301
Subrata Banik7cb43952022-03-16 20:40:42 +05301302 timeout_us /= 8; /* scale timeout duration to counter */
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001303 while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) &
1304 (HSFS_FDONE | HSFS_FCERR)) == 0) &&
Subrata Banik7cb43952022-03-16 20:40:42 +05301305 --timeout_us) {
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001306 programmer_delay(8);
1307 }
1308 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
Subrata Banik7cb43952022-03-16 20:40:42 +05301309 if (!timeout_us) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001310 addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001311 msg_perr("Timeout error between offset 0x%08x and "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001312 "0x%08x (= 0x%08x + %d)!\n",
1313 addr, addr + len - 1, addr, len - 1);
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001314 prettyprint_ich9_reg_hsfs(hsfs);
1315 prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC));
1316 return 1;
1317 }
1318
1319 if (hsfs & HSFS_FCERR) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001320 addr = REGREAD32(ICH9_REG_FADDR) & hwseq_data.addr_mask;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001321 msg_perr("Transaction error between offset 0x%08x and "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001322 "0x%08x (= 0x%08x + %d)!\n",
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001323 addr, addr + len - 1, addr, len - 1);
1324 prettyprint_ich9_reg_hsfs(hsfs);
1325 prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC));
1326 return 1;
1327 }
1328 return 0;
1329}
Stefan Tauner50e7c602011-11-08 10:55:54 +00001330
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001331static int ich_hwseq_probe(struct flashctx *flash)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001332{
1333 uint32_t total_size, boundary;
1334 uint32_t erase_size_low, size_low, erase_size_high, size_high;
1335 struct block_eraser *eraser;
1336
1337 total_size = hwseq_data.size_comp0 + hwseq_data.size_comp1;
Stefan Tauner5c316f92015-02-08 21:57:52 +00001338 msg_cdbg("Hardware sequencing reports %d attached SPI flash chip",
Stefan Tauner50e7c602011-11-08 10:55:54 +00001339 (hwseq_data.size_comp1 != 0) ? 2 : 1);
1340 if (hwseq_data.size_comp1 != 0)
1341 msg_cdbg("s with a combined");
1342 else
1343 msg_cdbg(" with a");
1344 msg_cdbg(" density of %d kB.\n", total_size / 1024);
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001345 flash->chip->total_size = total_size / 1024;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001346
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001347 eraser = &(flash->chip->block_erasers[0]);
Nico Huberd54e4f42017-03-23 23:45:47 +01001348 if (!hwseq_data.only_4k)
1349 boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12;
1350 else
1351 boundary = 0;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001352 size_high = total_size - boundary;
1353 erase_size_high = ich_hwseq_get_erase_block_size(boundary);
1354
1355 if (boundary == 0) {
Stefan Tauner5c316f92015-02-08 21:57:52 +00001356 msg_cdbg2("There is only one partition containing the whole "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001357 "address space (0x%06x - 0x%06x).\n", 0, size_high-1);
1358 eraser->eraseblocks[0].size = erase_size_high;
1359 eraser->eraseblocks[0].count = size_high / erase_size_high;
Stefan Tauner5c316f92015-02-08 21:57:52 +00001360 msg_cdbg2("There are %d erase blocks with %d B each.\n",
Stefan Tauner50e7c602011-11-08 10:55:54 +00001361 size_high / erase_size_high, erase_size_high);
1362 } else {
Stefan Tauner5c316f92015-02-08 21:57:52 +00001363 msg_cdbg2("The flash address space (0x%06x - 0x%06x) is divided "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001364 "at address 0x%06x in two partitions.\n",
Stefan Taunerdbac46c2013-08-13 22:10:41 +00001365 0, total_size-1, boundary);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001366 size_low = total_size - size_high;
1367 erase_size_low = ich_hwseq_get_erase_block_size(0);
1368
1369 eraser->eraseblocks[0].size = erase_size_low;
1370 eraser->eraseblocks[0].count = size_low / erase_size_low;
1371 msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n",
1372 0, size_low-1);
1373 msg_cdbg("In that range are %d erase blocks with %d B each.\n",
1374 size_low / erase_size_low, erase_size_low);
1375
1376 eraser->eraseblocks[1].size = erase_size_high;
1377 eraser->eraseblocks[1].count = size_high / erase_size_high;
1378 msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n",
Stefan Taunerdbac46c2013-08-13 22:10:41 +00001379 boundary, total_size-1);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001380 msg_cdbg("In that range are %d erase blocks with %d B each.\n",
1381 size_high / erase_size_high, erase_size_high);
1382 }
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001383 flash->chip->tested = TEST_OK_PREW;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001384 return 1;
1385}
1386
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001387static int ich_hwseq_block_erase(struct flashctx *flash, unsigned int addr,
1388 unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001389{
1390 uint32_t erase_block;
1391 uint16_t hsfc;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001392
1393 erase_block = ich_hwseq_get_erase_block_size(addr);
1394 if (len != erase_block) {
1395 msg_cerr("Erase block size for address 0x%06x is %d B, "
1396 "but requested erase block size is %d B. "
1397 "Not erasing anything.\n", addr, erase_block, len);
1398 return -1;
1399 }
1400
1401 /* Although the hardware supports this (it would erase the whole block
1402 * containing the address) we play safe here. */
1403 if (addr % erase_block != 0) {
1404 msg_cerr("Erase address 0x%06x is not aligned to the erase "
1405 "block boundary (any multiple of %d). "
1406 "Not erasing anything.\n", addr, erase_block);
1407 return -1;
1408 }
1409
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001410 if (addr + len > flash->chip->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001411 msg_perr("Request to erase some inaccessible memory address(es)"
1412 " (addr=0x%x, len=%d). "
1413 "Not erasing anything.\n", addr, len);
1414 return -1;
1415 }
1416
1417 msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr);
Stefan Tauner7608d362014-08-05 23:28:47 +00001418 ich_hwseq_set_addr(addr);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001419
1420 /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
1421 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1422
1423 hsfc = REGREAD16(ICH9_REG_HSFC);
Nico Huberd54e4f42017-03-23 23:45:47 +01001424 hsfc &= ~hwseq_data.hsfc_fcycle; /* clear operation */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001425 hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
1426 hsfc |= HSFC_FGO; /* start */
1427 msg_pdbg("HSFC used for block erasing: ");
1428 prettyprint_ich9_reg_hsfc(hsfc);
1429 REGWRITE16(ICH9_REG_HSFC, hsfc);
1430
Subrata Banik7cb43952022-03-16 20:40:42 +05301431 if (ich_hwseq_wait_for_cycle_complete(len))
Stefan Tauner50e7c602011-11-08 10:55:54 +00001432 return -1;
1433 return 0;
1434}
1435
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001436static int ich_hwseq_read(struct flashctx *flash, uint8_t *buf,
1437 unsigned int addr, unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001438{
1439 uint16_t hsfc;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001440 uint8_t block_len;
1441
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001442 if (addr + len > flash->chip->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001443 msg_perr("Request to read from an inaccessible memory address "
1444 "(addr=0x%x, len=%d).\n", addr, len);
1445 return -1;
1446 }
1447
1448 msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr);
1449 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
1450 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1451
1452 while (len > 0) {
Stefan Tauner7608d362014-08-05 23:28:47 +00001453 /* Obey programmer limit... */
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001454 block_len = min(len, flash->mst->opaque.max_data_read);
Stefan Tauner7608d362014-08-05 23:28:47 +00001455 /* as well as flash chip page borders as demanded in the Intel datasheets. */
1456 block_len = min(block_len, 256 - (addr & 0xFF));
1457
Stefan Tauner50e7c602011-11-08 10:55:54 +00001458 ich_hwseq_set_addr(addr);
1459 hsfc = REGREAD16(ICH9_REG_HSFC);
Nico Huberd54e4f42017-03-23 23:45:47 +01001460 hsfc &= ~hwseq_data.hsfc_fcycle; /* set read operation */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001461 hsfc &= ~HSFC_FDBC; /* clear byte count */
1462 /* set byte count */
1463 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
1464 hsfc |= HSFC_FGO; /* start */
1465 REGWRITE16(ICH9_REG_HSFC, hsfc);
1466
Subrata Banik7cb43952022-03-16 20:40:42 +05301467 if (ich_hwseq_wait_for_cycle_complete(block_len))
Stefan Tauner50e7c602011-11-08 10:55:54 +00001468 return 1;
1469 ich_read_data(buf, block_len, ICH9_REG_FDATA0);
1470 addr += block_len;
1471 buf += block_len;
1472 len -= block_len;
1473 }
1474 return 0;
1475}
1476
Mark Marshallf20b7be2014-05-09 21:16:21 +00001477static int ich_hwseq_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001478{
1479 uint16_t hsfc;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001480 uint8_t block_len;
1481
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001482 if (addr + len > flash->chip->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001483 msg_perr("Request to write to an inaccessible memory address "
1484 "(addr=0x%x, len=%d).\n", addr, len);
1485 return -1;
1486 }
1487
1488 msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr);
1489 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
1490 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1491
1492 while (len > 0) {
1493 ich_hwseq_set_addr(addr);
Stefan Tauner7608d362014-08-05 23:28:47 +00001494 /* Obey programmer limit... */
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001495 block_len = min(len, flash->mst->opaque.max_data_write);
Stefan Tauner7608d362014-08-05 23:28:47 +00001496 /* as well as flash chip page borders as demanded in the Intel datasheets. */
1497 block_len = min(block_len, 256 - (addr & 0xFF));
Stefan Tauner50e7c602011-11-08 10:55:54 +00001498 ich_fill_data(buf, block_len, ICH9_REG_FDATA0);
1499 hsfc = REGREAD16(ICH9_REG_HSFC);
Nico Huberd54e4f42017-03-23 23:45:47 +01001500 hsfc &= ~hwseq_data.hsfc_fcycle; /* clear operation */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001501 hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */
1502 hsfc &= ~HSFC_FDBC; /* clear byte count */
1503 /* set byte count */
1504 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
1505 hsfc |= HSFC_FGO; /* start */
1506 REGWRITE16(ICH9_REG_HSFC, hsfc);
1507
Subrata Banik7cb43952022-03-16 20:40:42 +05301508 if (ich_hwseq_wait_for_cycle_complete(block_len))
Stefan Tauner50e7c602011-11-08 10:55:54 +00001509 return -1;
1510 addr += block_len;
1511 buf += block_len;
1512 len -= block_len;
1513 }
1514 return 0;
1515}
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001516
Edward O'Callaghan5eca4272020-04-12 17:27:53 +10001517static int ich_spi_send_multicommand(const struct flashctx *flash,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001518 struct spi_command *cmds)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001519{
1520 int ret = 0;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001521 int i;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001522 int oppos, preoppos;
1523 for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) {
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001524 if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001525 /* Next command is valid. */
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001526 preoppos = find_preop(curopcodes, cmds->writearr[0]);
1527 oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001528 if ((oppos == -1) && (preoppos != -1)) {
1529 /* Current command is listed as preopcode in
1530 * ICH struct OPCODES, but next command is not
1531 * listed as opcode in that struct.
1532 * Check for command sanity, then
1533 * try to reprogram the ICH opcode list.
1534 */
1535 if (find_preop(curopcodes,
1536 (cmds + 1)->writearr[0]) != -1) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001537 msg_perr("%s: Two subsequent "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001538 "preopcodes 0x%02x and 0x%02x, "
1539 "ignoring the first.\n",
1540 __func__, cmds->writearr[0],
1541 (cmds + 1)->writearr[0]);
1542 continue;
1543 }
1544 /* If the chipset is locked down, we'll fail
1545 * during execution of the next command anyway.
1546 * No need to bother with fixups.
1547 */
1548 if (!ichspi_lock) {
Helge Wagner738e2522010-10-05 22:06:05 +00001549 oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt);
1550 if (oppos == -1)
1551 continue;
1552 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001553 continue;
1554 }
1555 }
1556 if ((oppos != -1) && (preoppos != -1)) {
1557 /* Current command is listed as preopcode in
1558 * ICH struct OPCODES and next command is listed
1559 * as opcode in that struct. Match them up.
1560 */
1561 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001562 continue;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001563 }
1564 /* If none of the above if-statements about oppos or
1565 * preoppos matched, this is a normal opcode.
1566 */
1567 }
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001568 ret = ich_spi_send_command(flash, cmds->writecnt, cmds->readcnt,
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001569 cmds->writearr, cmds->readarr);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001570 /* Reset the type of all opcodes to non-atomic. */
1571 for (i = 0; i < 8; i++)
1572 curopcodes->opcode[i].atomic = 0;
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001573 }
1574 return ret;
1575}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001576
Michael Karchera4448d92010-07-22 18:04:15 +00001577#define ICH_BMWAG(x) ((x >> 24) & 0xff)
1578#define ICH_BMRAG(x) ((x >> 16) & 0xff)
1579#define ICH_BRWA(x) ((x >> 8) & 0xff)
1580#define ICH_BRRA(x) ((x >> 0) & 0xff)
1581
Nico Huber7590d1a2016-05-03 13:38:28 +02001582static const enum ich_access_protection access_perms_to_protection[] = {
1583 LOCKED, WRITE_PROT, READ_PROT, NO_PROT
1584};
1585static const char *const access_names[] = {
1586 "locked", "read-only", "write-only", "read-write"
1587};
1588
Nico Huber519be662018-12-23 20:03:35 +01001589static enum ich_access_protection ich9_handle_frap(uint32_t frap, unsigned int i)
Michael Karchera4448d92010-07-22 18:04:15 +00001590{
Nico Huberaa91d5c2017-08-19 17:04:21 +02001591 const int rwperms_unknown = ARRAY_SIZE(access_names);
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001592 static const char *const region_names[] = {
Michael Karchera4448d92010-07-22 18:04:15 +00001593 "Flash Descriptor", "BIOS", "Management Engine",
Nico Huberd2d39932019-01-18 16:49:37 +01001594 "Gigabit Ethernet", "Platform Data", "Device Expansion",
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001595 "BIOS2", "unknown", "EC/BMC",
Michael Karchera4448d92010-07-22 18:04:15 +00001596 };
Nico Huberd54e4f42017-03-23 23:45:47 +01001597 const char *const region_name = i < ARRAY_SIZE(region_names) ? region_names[i] : "unknown";
1598
Michael Karchera4448d92010-07-22 18:04:15 +00001599 uint32_t base, limit;
Nico Huberaa91d5c2017-08-19 17:04:21 +02001600 int rwperms;
Nico Huberd2d39932019-01-18 16:49:37 +01001601 const int offset = i < 12
1602 ? ICH9_REG_FREG0 + i * 4
1603 : APL_REG_FREG12 + (i - 12) * 4;
Michael Karchera4448d92010-07-22 18:04:15 +00001604 uint32_t freg = mmio_readl(ich_spibar + offset);
1605
Nico Huberaa91d5c2017-08-19 17:04:21 +02001606 if (i < 8) {
1607 rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) |
1608 (((ICH_BRRA(frap) >> i) & 1) << 0);
1609 } else {
1610 /* Datasheets don't define any access bits for regions > 7. We
1611 can't rely on the actual descriptor settings either as there
1612 are several overrides for them (those by other masters are
1613 not even readable by us, *shrug*). */
1614 rwperms = rwperms_unknown;
1615 }
1616
Michael Karchera4448d92010-07-22 18:04:15 +00001617 base = ICH_FREG_BASE(freg);
1618 limit = ICH_FREG_LIMIT(freg);
Stefan Taunere3adea02012-08-27 15:12:36 +00001619 if (base > limit || (freg == 0 && i > 0)) {
Michael Karchera4448d92010-07-22 18:04:15 +00001620 /* this FREG is disabled */
Nico Huber519be662018-12-23 20:03:35 +01001621 msg_pdbg2("0x%02X: 0x%08x FREG%u: %s region is unused.\n",
Nico Huberd54e4f42017-03-23 23:45:47 +01001622 offset, freg, i, region_name);
Nico Huber7590d1a2016-05-03 13:38:28 +02001623 return NO_PROT;
Stefan Tauner5210e722012-02-16 01:13:00 +00001624 }
1625 msg_pdbg("0x%02X: 0x%08x ", offset, freg);
1626 if (rwperms == 0x3) {
Nico Huber519be662018-12-23 20:03:35 +01001627 msg_pdbg("FREG%u: %s region (0x%08x-0x%08x) is %s.\n", i,
Nico Huber0bb3f712017-03-29 16:44:33 +02001628 region_name, base, limit, access_names[rwperms]);
Nico Huber7590d1a2016-05-03 13:38:28 +02001629 return NO_PROT;
Michael Karchera4448d92010-07-22 18:04:15 +00001630 }
Nico Huberaa91d5c2017-08-19 17:04:21 +02001631 if (rwperms == rwperms_unknown) {
Nico Huber519be662018-12-23 20:03:35 +01001632 msg_pdbg("FREG%u: %s region (0x%08x-0x%08x) has unknown permissions.\n",
Nico Huberaa91d5c2017-08-19 17:04:21 +02001633 i, region_name, base, limit);
Nico Huber7590d1a2016-05-03 13:38:28 +02001634 return NO_PROT;
Nico Huberaa91d5c2017-08-19 17:04:21 +02001635 }
Michael Karchera4448d92010-07-22 18:04:15 +00001636
Nico Huber519be662018-12-23 20:03:35 +01001637 msg_pinfo("FREG%u: %s region (0x%08x-0x%08x) is %s.\n", i,
Nico Huber0bb3f712017-03-29 16:44:33 +02001638 region_name, base, limit, access_names[rwperms]);
Nico Huber7590d1a2016-05-03 13:38:28 +02001639 return access_perms_to_protection[rwperms];
Michael Karchera4448d92010-07-22 18:04:15 +00001640}
1641
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001642 /* In contrast to FRAP and the master section of the descriptor the bits
1643 * in the PR registers have an inverted meaning. The bits in FRAP
1644 * indicate read and write access _grant_. Here they indicate read
1645 * and write _protection_ respectively. If both bits are 0 the address
1646 * bits are ignored.
1647 */
1648#define ICH_PR_PERMS(pr) (((~((pr) >> PR_RP_OFF) & 1) << 0) | \
1649 ((~((pr) >> PR_WP_OFF) & 1) << 1))
1650
Nico Huber519be662018-12-23 20:03:35 +01001651static enum ich_access_protection ich9_handle_pr(const size_t reg_pr0, unsigned int i)
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001652{
Nico Huberd54e4f42017-03-23 23:45:47 +01001653 uint8_t off = reg_pr0 + (i * 4);
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001654 uint32_t pr = mmio_readl(ich_spibar + off);
Stefan Tauner5210e722012-02-16 01:13:00 +00001655 unsigned int rwperms = ICH_PR_PERMS(pr);
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001656
Nico Huberd54e4f42017-03-23 23:45:47 +01001657 /* From 5 on we have GPR registers and start from 0 again. */
1658 const char *const prefix = i >= 5 ? "G" : "";
1659 if (i >= 5)
1660 i -= 5;
1661
Stefan Tauner5210e722012-02-16 01:13:00 +00001662 if (rwperms == 0x3) {
Nico Huberd54e4f42017-03-23 23:45:47 +01001663 msg_pdbg2("0x%02X: 0x%08x (%sPR%u is unused)\n", off, pr, prefix, i);
Nico Huber7590d1a2016-05-03 13:38:28 +02001664 return NO_PROT;
Stefan Tauner5210e722012-02-16 01:13:00 +00001665 }
1666
1667 msg_pdbg("0x%02X: 0x%08x ", off, pr);
Nico Huberd54e4f42017-03-23 23:45:47 +01001668 msg_pwarn("%sPR%u: Warning: 0x%08x-0x%08x is %s.\n", prefix, i, ICH_FREG_BASE(pr),
Nico Huber0bb3f712017-03-29 16:44:33 +02001669 ICH_FREG_LIMIT(pr), access_names[rwperms]);
Nico Huber7590d1a2016-05-03 13:38:28 +02001670 return access_perms_to_protection[rwperms];
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001671}
1672
Stefan Tauner75da80c2011-09-17 22:21:55 +00001673/* Set/Clear the read and write protection enable bits of PR register @i
1674 * according to @read_prot and @write_prot. */
Nico Huberd54e4f42017-03-23 23:45:47 +01001675static void ich9_set_pr(const size_t reg_pr0, int i, int read_prot, int write_prot)
Stefan Tauner75da80c2011-09-17 22:21:55 +00001676{
Nico Huberd54e4f42017-03-23 23:45:47 +01001677 void *addr = ich_spibar + reg_pr0 + (i * 4);
Stefan Tauner75da80c2011-09-17 22:21:55 +00001678 uint32_t old = mmio_readl(addr);
1679 uint32_t new;
1680
1681 msg_gspew("PR%u is 0x%08x", i, old);
1682 new = old & ~((1 << PR_RP_OFF) | (1 << PR_WP_OFF));
1683 if (read_prot)
1684 new |= (1 << PR_RP_OFF);
1685 if (write_prot)
1686 new |= (1 << PR_WP_OFF);
1687 if (old == new) {
1688 msg_gspew(" already.\n");
1689 return;
1690 }
1691 msg_gspew(", trying to set it to 0x%08x ", new);
1692 rmmio_writel(new, addr);
1693 msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr));
1694}
1695
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001696static const struct spi_master spi_master_ich7 = {
Thomas Heijligen43040f22022-06-23 14:38:35 +02001697 .max_data_read = 64,
1698 .max_data_write = 64,
1699 .command = ich_spi_send_command,
1700 .multicommand = ich_spi_send_multicommand,
1701 .read = default_spi_read,
1702 .write_256 = default_spi_write_256,
1703 .write_aai = default_spi_write_aai,
Michael Karcherb9dbe482011-05-11 17:07:07 +00001704};
1705
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001706static const struct spi_master spi_master_ich9 = {
Thomas Heijligen43040f22022-06-23 14:38:35 +02001707 .max_data_read = 64,
1708 .max_data_write = 64,
1709 .command = ich_spi_send_command,
1710 .multicommand = ich_spi_send_multicommand,
1711 .read = default_spi_read,
1712 .write_256 = default_spi_write_256,
1713 .write_aai = default_spi_write_aai,
Michael Karcherb9dbe482011-05-11 17:07:07 +00001714};
1715
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001716static const struct opaque_master opaque_master_ich_hwseq = {
Thomas Heijligen43040f22022-06-23 14:38:35 +02001717 .max_data_read = 64,
1718 .max_data_write = 64,
1719 .probe = ich_hwseq_probe,
1720 .read = ich_hwseq_read,
1721 .write = ich_hwseq_write,
1722 .erase = ich_hwseq_block_erase,
Stefan Tauner50e7c602011-11-08 10:55:54 +00001723};
1724
Nico Huber560111e2017-04-26 12:27:17 +02001725int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
Michael Karchera4448d92010-07-22 18:04:15 +00001726{
Nico Huber519be662018-12-23 20:03:35 +01001727 unsigned int i;
Stefan Tauner92d6a862013-10-25 00:33:37 +00001728 uint16_t tmp2;
Michael Karchera4448d92010-07-22 18:04:15 +00001729 uint32_t tmp;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001730 char *arg;
Stefan Tauner5210e722012-02-16 01:13:00 +00001731 int ich_spi_rw_restricted = 0;
Felix Singer8cfc7372022-08-19 03:10:29 +02001732 bool desc_valid = false;
Angel Pons7e134562021-06-07 13:29:13 +02001733 struct ich_descriptors desc = { 0 };
Stefan Tauner50e7c602011-11-08 10:55:54 +00001734 enum ich_spi_mode {
1735 ich_auto,
1736 ich_hwseq,
1737 ich_swseq
1738 } ich_spi_mode = ich_auto;
Nico Huberd54e4f42017-03-23 23:45:47 +01001739 size_t num_freg, num_pr, reg_pr0;
Michael Karchera4448d92010-07-22 18:04:15 +00001740
Stefan Taunera8d838d2011-11-06 23:51:09 +00001741 ich_generation = ich_gen;
Stefan Tauner92d6a862013-10-25 00:33:37 +00001742 ich_spibar = spibar;
Michael Karchera4448d92010-07-22 18:04:15 +00001743
Nico Huberd54e4f42017-03-23 23:45:47 +01001744 /* Moving registers / bits */
Nico Huberd2d39932019-01-18 16:49:37 +01001745 switch (ich_generation) {
1746 case CHIPSET_100_SERIES_SUNRISE_POINT:
1747 case CHIPSET_C620_SERIES_LEWISBURG:
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001748 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +02001749 case CHIPSET_500_SERIES_TIGER_POINT:
Nico Huberd2d39932019-01-18 16:49:37 +01001750 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +02001751 case CHIPSET_GEMINI_LAKE:
Werner Zehe57d4e42022-01-03 09:44:29 +01001752 case CHIPSET_ELKHART_LAKE:
David Hendricksa5216362017-08-08 20:02:22 -07001753 num_pr = 6; /* Includes GPR0 */
1754 reg_pr0 = PCH100_REG_FPR0;
1755 swseq_data.reg_ssfsc = PCH100_REG_SSFSC;
1756 swseq_data.reg_preop = PCH100_REG_PREOP;
1757 swseq_data.reg_optype = PCH100_REG_OPTYPE;
1758 swseq_data.reg_opmenu = PCH100_REG_OPMENU;
1759 hwseq_data.addr_mask = PCH100_FADDR_FLA;
1760 hwseq_data.only_4k = true;
1761 hwseq_data.hsfc_fcycle = PCH100_HSFC_FCYCLE;
Nico Huberd2d39932019-01-18 16:49:37 +01001762 break;
1763 default:
Nico Huberd54e4f42017-03-23 23:45:47 +01001764 num_pr = 5;
1765 reg_pr0 = ICH9_REG_PR0;
1766 swseq_data.reg_ssfsc = ICH9_REG_SSFS;
1767 swseq_data.reg_preop = ICH9_REG_PREOP;
1768 swseq_data.reg_optype = ICH9_REG_OPTYPE;
1769 swseq_data.reg_opmenu = ICH9_REG_OPMENU;
1770 hwseq_data.addr_mask = ICH9_FADDR_FLA;
1771 hwseq_data.only_4k = false;
1772 hwseq_data.hsfc_fcycle = HSFC_FCYCLE;
Nico Huberd2d39932019-01-18 16:49:37 +01001773 break;
1774 }
1775 switch (ich_generation) {
1776 case CHIPSET_100_SERIES_SUNRISE_POINT:
1777 num_freg = 10;
1778 break;
1779 case CHIPSET_C620_SERIES_LEWISBURG:
1780 num_freg = 12; /* 12 MMIO regs, but 16 regions in FD spec */
1781 break;
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001782 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +02001783 case CHIPSET_500_SERIES_TIGER_POINT:
Nico Huberd2d39932019-01-18 16:49:37 +01001784 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +02001785 case CHIPSET_GEMINI_LAKE:
Werner Zehe57d4e42022-01-03 09:44:29 +01001786 case CHIPSET_ELKHART_LAKE:
Nico Huberd2d39932019-01-18 16:49:37 +01001787 num_freg = 16;
1788 break;
1789 default:
1790 num_freg = 5;
1791 break;
Nico Huberd54e4f42017-03-23 23:45:47 +01001792 }
1793
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001794 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +00001795 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +00001796 case CHIPSET_TUNNEL_CREEK:
1797 case CHIPSET_CENTERTON:
Michael Karchera4448d92010-07-22 18:04:15 +00001798 msg_pdbg("0x00: 0x%04x (SPIS)\n",
1799 mmio_readw(ich_spibar + 0));
1800 msg_pdbg("0x02: 0x%04x (SPIC)\n",
1801 mmio_readw(ich_spibar + 2));
1802 msg_pdbg("0x04: 0x%08x (SPIA)\n",
1803 mmio_readl(ich_spibar + 4));
Michael Karchera4448d92010-07-22 18:04:15 +00001804 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
1805 msg_pdbg("0x50: 0x%08x (BBAR)\n",
1806 ichspi_bbar);
1807 msg_pdbg("0x54: 0x%04x (PREOP)\n",
1808 mmio_readw(ich_spibar + 0x54));
1809 msg_pdbg("0x56: 0x%04x (OPTYPE)\n",
1810 mmio_readw(ich_spibar + 0x56));
1811 msg_pdbg("0x58: 0x%08x (OPMENU)\n",
1812 mmio_readl(ich_spibar + 0x58));
1813 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n",
1814 mmio_readl(ich_spibar + 0x5c));
Stefan Tauner122dd122011-07-24 15:34:56 +00001815 for (i = 0; i < 3; i++) {
Michael Karchera4448d92010-07-22 18:04:15 +00001816 int offs;
1817 offs = 0x60 + (i * 4);
Nico Huber519be662018-12-23 20:03:35 +01001818 msg_pdbg("0x%02x: 0x%08x (PBR%u)\n", offs,
Michael Karchera4448d92010-07-22 18:04:15 +00001819 mmio_readl(ich_spibar + offs), i);
1820 }
Michael Karchera4448d92010-07-22 18:04:15 +00001821 if (mmio_readw(ich_spibar) & (1 << 15)) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00001822 msg_pwarn("WARNING: SPI Configuration Lockdown activated.\n");
Felix Singer8cfc7372022-08-19 03:10:29 +02001823 ichspi_lock = true;
Michael Karchera4448d92010-07-22 18:04:15 +00001824 }
Stefan Tauner745f6bb2011-11-13 15:17:10 +00001825 ich_init_opcodes();
Stefan Taunera8d838d2011-11-06 23:51:09 +00001826 ich_set_bbar(0);
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001827 register_spi_master(&spi_master_ich7);
Michael Karchera4448d92010-07-22 18:04:15 +00001828 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +00001829 case CHIPSET_ICH8:
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001830 default: /* Future version might behave the same */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001831 arg = extract_programmer_param("ich_spi_mode");
1832 if (arg && !strcmp(arg, "hwseq")) {
1833 ich_spi_mode = ich_hwseq;
1834 msg_pspew("user selected hwseq\n");
1835 } else if (arg && !strcmp(arg, "swseq")) {
1836 ich_spi_mode = ich_swseq;
1837 msg_pspew("user selected swseq\n");
1838 } else if (arg && !strcmp(arg, "auto")) {
1839 msg_pspew("user selected auto\n");
1840 ich_spi_mode = ich_auto;
1841 } else if (arg && !strlen(arg)) {
1842 msg_perr("Missing argument for ich_spi_mode.\n");
1843 free(arg);
1844 return ERROR_FATAL;
1845 } else if (arg) {
1846 msg_perr("Unknown argument for ich_spi_mode: %s\n",
1847 arg);
1848 free(arg);
1849 return ERROR_FATAL;
1850 }
1851 free(arg);
1852
Stefan Tauner29c80832011-06-12 08:14:10 +00001853 tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS);
Michael Karchera4448d92010-07-22 18:04:15 +00001854 msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2);
Stefan Tauner55206942011-06-11 09:53:22 +00001855 prettyprint_ich9_reg_hsfs(tmp2);
Stefan Tauner29c80832011-06-12 08:14:10 +00001856 if (tmp2 & HSFS_FLOCKDN) {
Nico Huber7590d1a2016-05-03 13:38:28 +02001857 msg_pinfo("SPI Configuration is locked down.\n");
Felix Singer8cfc7372022-08-19 03:10:29 +02001858 ichspi_lock = true;
Stefan Tauner55206942011-06-11 09:53:22 +00001859 }
Stefan Tauner1e146392011-09-15 23:52:55 +00001860 if (tmp2 & HSFS_FDV)
Felix Singer8cfc7372022-08-19 03:10:29 +02001861 desc_valid = true;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001862 if (!(tmp2 & HSFS_FDOPSS) && desc_valid)
Stefan Taunerd7d423b2012-10-20 09:13:16 +00001863 msg_pinfo("The Flash Descriptor Override Strap-Pin is set. Restrictions implied by\n"
1864 "the Master Section of the flash descriptor are NOT in effect. Please note\n"
1865 "that Protected Range (PR) restrictions still apply.\n");
Stefan Tauner745f6bb2011-11-13 15:17:10 +00001866 ich_init_opcodes();
Stefan Tauner55206942011-06-11 09:53:22 +00001867
Stefan Taunerf382e352011-11-08 11:55:24 +00001868 if (desc_valid) {
1869 tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC);
1870 msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2);
1871 prettyprint_ich9_reg_hsfc(tmp2);
1872 }
Michael Karchera4448d92010-07-22 18:04:15 +00001873
Stefan Tauner5ffe65b2011-07-07 04:10:57 +00001874 tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR);
Stefan Taunereb582572012-09-21 12:52:50 +00001875 msg_pdbg2("0x08: 0x%08x (FADDR)\n", tmp);
Michael Karchera4448d92010-07-22 18:04:15 +00001876
Nico Huberd2d39932019-01-18 16:49:37 +01001877 switch (ich_gen) {
1878 case CHIPSET_100_SERIES_SUNRISE_POINT:
1879 case CHIPSET_C620_SERIES_LEWISBURG:
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001880 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +02001881 case CHIPSET_500_SERIES_TIGER_POINT:
Nico Huberd2d39932019-01-18 16:49:37 +01001882 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +02001883 case CHIPSET_GEMINI_LAKE:
Werner Zehe57d4e42022-01-03 09:44:29 +01001884 case CHIPSET_ELKHART_LAKE:
Nico Huberd2d39932019-01-18 16:49:37 +01001885 tmp = mmio_readl(ich_spibar + PCH100_REG_DLOCK);
1886 msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp);
1887 prettyprint_pch100_reg_dlock(tmp);
1888 break;
1889 default:
1890 break;
Nico Huberd54e4f42017-03-23 23:45:47 +01001891 }
1892
Stefan Taunerf382e352011-11-08 11:55:24 +00001893 if (desc_valid) {
1894 tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP);
1895 msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp);
1896 msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp));
1897 msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp));
1898 msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp));
1899 msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp));
1900
Stefan Tauner5210e722012-02-16 01:13:00 +00001901 /* Handle FREGx and FRAP registers */
Nico Huberd54e4f42017-03-23 23:45:47 +01001902 for (i = 0; i < num_freg; i++)
Stefan Tauner5210e722012-02-16 01:13:00 +00001903 ich_spi_rw_restricted |= ich9_handle_frap(tmp, i);
Stefan Tauner27cb34b2013-06-01 00:06:12 +00001904 if (ich_spi_rw_restricted)
Nico Huber7590d1a2016-05-03 13:38:28 +02001905 msg_pinfo("Not all flash regions are freely accessible by flashrom. This is "
Stefan Tauner4c723152016-01-14 22:47:55 +00001906 "most likely\ndue to an active ME. Please see "
1907 "https://flashrom.org/ME for details.\n");
Stefan Taunerf382e352011-11-08 11:55:24 +00001908 }
Michael Karchera4448d92010-07-22 18:04:15 +00001909
Stefan Taunereb582572012-09-21 12:52:50 +00001910 /* Handle PR registers */
Nico Huberd54e4f42017-03-23 23:45:47 +01001911 for (i = 0; i < num_pr; i++) {
Stefan Tauner5210e722012-02-16 01:13:00 +00001912 /* if not locked down try to disable PR locks first */
1913 if (!ichspi_lock)
Nico Huberd54e4f42017-03-23 23:45:47 +01001914 ich9_set_pr(reg_pr0, i, 0, 0);
1915 ich_spi_rw_restricted |= ich9_handle_pr(reg_pr0, i);
Stefan Tauner5210e722012-02-16 01:13:00 +00001916 }
1917
Nico Huber7590d1a2016-05-03 13:38:28 +02001918 switch (ich_spi_rw_restricted) {
1919 case WRITE_PROT:
1920 msg_pwarn("At least some flash regions are write protected. For write operations,\n"
1921 "you should use a flash layout and include only writable regions. See\n"
1922 "manpage for more details.\n");
1923 break;
1924 case READ_PROT:
1925 case LOCKED:
1926 msg_pwarn("At least some flash regions are read protected. You have to use a flash\n"
1927 "layout and include only accessible regions. For write operations, you'll\n"
1928 "additionally need the --noverify-all switch. See manpage for more details.\n"
1929 );
1930 break;
Stefan Tauner5210e722012-02-16 01:13:00 +00001931 }
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001932
Nico Huberd54e4f42017-03-23 23:45:47 +01001933 tmp = mmio_readl(ich_spibar + swseq_data.reg_ssfsc);
1934 msg_pdbg("0x%zx: 0x%02x (SSFS)\n", swseq_data.reg_ssfsc, tmp & 0xff);
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001935 prettyprint_ich9_reg_ssfs(tmp);
Stefan Tauner29c80832011-06-12 08:14:10 +00001936 if (tmp & SSFS_FCERR) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001937 msg_pdbg("Clearing SSFS.FCERR\n");
Nico Huberd54e4f42017-03-23 23:45:47 +01001938 mmio_writeb(SSFS_FCERR, ich_spibar + swseq_data.reg_ssfsc);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001939 }
Nico Huberd54e4f42017-03-23 23:45:47 +01001940 msg_pdbg("0x%zx: 0x%06x (SSFC)\n", swseq_data.reg_ssfsc + 1, tmp >> 8);
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001941 prettyprint_ich9_reg_ssfc(tmp);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001942
Nico Huberd54e4f42017-03-23 23:45:47 +01001943 msg_pdbg("0x%zx: 0x%04x (PREOP)\n",
1944 swseq_data.reg_preop, mmio_readw(ich_spibar + swseq_data.reg_preop));
1945 msg_pdbg("0x%zx: 0x%04x (OPTYPE)\n",
1946 swseq_data.reg_optype, mmio_readw(ich_spibar + swseq_data.reg_optype));
1947 msg_pdbg("0x%zx: 0x%08x (OPMENU)\n",
1948 swseq_data.reg_opmenu, mmio_readl(ich_spibar + swseq_data.reg_opmenu));
1949 msg_pdbg("0x%zx: 0x%08x (OPMENU+4)\n",
1950 swseq_data.reg_opmenu + 4, mmio_readl(ich_spibar + swseq_data.reg_opmenu + 4));
Nico Huberd2d39932019-01-18 16:49:37 +01001951
1952 if (desc_valid) {
1953 switch (ich_gen) {
1954 case CHIPSET_ICH8:
1955 case CHIPSET_100_SERIES_SUNRISE_POINT:
1956 case CHIPSET_C620_SERIES_LEWISBURG:
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001957 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +02001958 case CHIPSET_500_SERIES_TIGER_POINT:
Nico Huberd2d39932019-01-18 16:49:37 +01001959 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +02001960 case CHIPSET_GEMINI_LAKE:
Werner Zehe57d4e42022-01-03 09:44:29 +01001961 case CHIPSET_ELKHART_LAKE:
Nico Huberd2d39932019-01-18 16:49:37 +01001962 case CHIPSET_BAYTRAIL:
1963 break;
1964 default:
Duncan Laurie4095ed72014-08-20 15:39:32 +00001965 ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR);
Nico Huberd2d39932019-01-18 16:49:37 +01001966 msg_pdbg("0x%x: 0x%08x (BBAR)\n", ICH9_REG_BBAR, ichspi_bbar);
Duncan Laurie4095ed72014-08-20 15:39:32 +00001967 ich_set_bbar(0);
Nico Huberd2d39932019-01-18 16:49:37 +01001968 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +00001969 }
Stefan Taunerbd649e42011-07-01 00:39:16 +00001970
Nico Huberd2d39932019-01-18 16:49:37 +01001971 if (ich_gen == CHIPSET_ICH8) {
1972 tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC);
1973 msg_pdbg("0x%x: 0x%08x (VSCC)\n", ICH8_REG_VSCC, tmp);
1974 msg_pdbg("VSCC: ");
1975 prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true);
1976 } else {
Stefan Taunerf382e352011-11-08 11:55:24 +00001977 tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC);
Nico Huberd2d39932019-01-18 16:49:37 +01001978 msg_pdbg("0x%x: 0x%08x (LVSCC)\n", ICH9_REG_LVSCC, tmp);
Stefan Taunerf382e352011-11-08 11:55:24 +00001979 msg_pdbg("LVSCC: ");
Nico Huberd152fb92017-06-19 12:57:10 +02001980 prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, true);
Stefan Tauner1e146392011-09-15 23:52:55 +00001981
Stefan Taunerf382e352011-11-08 11:55:24 +00001982 tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC);
Nico Huberd2d39932019-01-18 16:49:37 +01001983 msg_pdbg("0x%x: 0x%08x (UVSCC)\n", ICH9_REG_UVSCC, tmp);
Stefan Taunerf382e352011-11-08 11:55:24 +00001984 msg_pdbg("UVSCC: ");
Nico Huberd152fb92017-06-19 12:57:10 +02001985 prettyprint_ich_reg_vscc(tmp, FLASHROM_MSG_DEBUG, false);
Stefan Taunerf382e352011-11-08 11:55:24 +00001986 }
Stefan Tauner1e146392011-09-15 23:52:55 +00001987
Nico Huberd2d39932019-01-18 16:49:37 +01001988 switch (ich_gen) {
1989 case CHIPSET_ICH8:
1990 case CHIPSET_100_SERIES_SUNRISE_POINT:
1991 case CHIPSET_C620_SERIES_LEWISBURG:
Nico Huber2a5dfaf2019-07-04 16:01:51 +02001992 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +02001993 case CHIPSET_500_SERIES_TIGER_POINT:
Nico Huberd2d39932019-01-18 16:49:37 +01001994 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +02001995 case CHIPSET_GEMINI_LAKE:
Werner Zehe57d4e42022-01-03 09:44:29 +01001996 case CHIPSET_ELKHART_LAKE:
Nico Huberd2d39932019-01-18 16:49:37 +01001997 break;
1998 default:
1999 tmp = mmio_readl(ich_spibar + ICH9_REG_FPB);
2000 msg_pdbg("0x%x: 0x%08x (FPB)\n", ICH9_REG_FPB, tmp);
2001 break;
2002 }
2003
Nico Huberd54e4f42017-03-23 23:45:47 +01002004 if (read_ich_descriptors_via_fdo(ich_gen, ich_spibar, &desc) == ICH_RET_OK)
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +00002005 prettyprint_ich_descriptors(ich_gen, &desc);
2006
Stefan Tauner50e7c602011-11-08 10:55:54 +00002007 /* If the descriptor is valid and indicates multiple
2008 * flash devices we need to use hwseq to be able to
2009 * access the second flash device.
2010 */
2011 if (ich_spi_mode == ich_auto && desc.content.NC != 0) {
2012 msg_pinfo("Enabling hardware sequencing due to "
2013 "multiple flash chips detected.\n");
2014 ich_spi_mode = ich_hwseq;
2015 }
Stefan Tauner1e146392011-09-15 23:52:55 +00002016 }
Stefan Tauner50e7c602011-11-08 10:55:54 +00002017
2018 if (ich_spi_mode == ich_auto && ichspi_lock &&
2019 ich_missing_opcodes()) {
2020 msg_pinfo("Enabling hardware sequencing because "
2021 "some important opcode is locked.\n");
2022 ich_spi_mode = ich_hwseq;
2023 }
2024
Nico Huber2a5dfaf2019-07-04 16:01:51 +02002025 if (ich_spi_mode == ich_auto &&
2026 (ich_gen == CHIPSET_100_SERIES_SUNRISE_POINT ||
Michał Żygowski5c9f5422021-06-16 15:13:54 +02002027 ich_gen == CHIPSET_300_SERIES_CANNON_POINT ||
2028 ich_gen == CHIPSET_500_SERIES_TIGER_POINT)) {
Nico Huber2a5dfaf2019-07-04 16:01:51 +02002029 msg_pdbg("Enabling hardware sequencing by default for 100+ series PCH.\n");
Nico Huber22f2dc52017-08-31 16:14:22 +02002030 ich_spi_mode = ich_hwseq;
2031 }
2032
Angel Pons4db0fdf2020-07-10 17:04:10 +02002033 if (ich_spi_mode == ich_auto &&
2034 (ich_gen == CHIPSET_APOLLO_LAKE ||
Werner Zehe57d4e42022-01-03 09:44:29 +01002035 ich_gen == CHIPSET_GEMINI_LAKE ||
2036 ich_gen == CHIPSET_ELKHART_LAKE)) {
2037 msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini/Elkhart Lake.\n");
Nico Huberd2d39932019-01-18 16:49:37 +01002038 ich_spi_mode = ich_hwseq;
2039 }
2040
Stefan Tauner50e7c602011-11-08 10:55:54 +00002041 if (ich_spi_mode == ich_hwseq) {
2042 if (!desc_valid) {
2043 msg_perr("Hardware sequencing was requested "
2044 "but the flash descriptor is not "
2045 "valid. Aborting.\n");
2046 return ERROR_FATAL;
2047 }
Stefan Tauner2ba9f6e2014-08-20 15:39:19 +00002048
2049 int tmpi = getFCBA_component_density(ich_generation, &desc, 0);
2050 if (tmpi < 0) {
2051 msg_perr("Could not determine density of flash component %d.\n", 0);
2052 return ERROR_FATAL;
2053 }
2054 hwseq_data.size_comp0 = tmpi;
2055
2056 tmpi = getFCBA_component_density(ich_generation, &desc, 1);
2057 if (tmpi < 0) {
2058 msg_perr("Could not determine density of flash component %d.\n", 1);
2059 return ERROR_FATAL;
2060 }
2061 hwseq_data.size_comp1 = tmpi;
2062
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00002063 register_opaque_master(&opaque_master_ich_hwseq);
Stefan Tauner50e7c602011-11-08 10:55:54 +00002064 } else {
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00002065 register_spi_master(&spi_master_ich9);
Stefan Tauner50e7c602011-11-08 10:55:54 +00002066 }
Michael Karchera4448d92010-07-22 18:04:15 +00002067 break;
Michael Karchera4448d92010-07-22 18:04:15 +00002068 }
2069
Michael Karchera4448d92010-07-22 18:04:15 +00002070 return 0;
2071}
2072
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00002073static const struct spi_master spi_master_via = {
Thomas Heijligen43040f22022-06-23 14:38:35 +02002074 .max_data_read = 16,
2075 .max_data_write = 16,
2076 .command = ich_spi_send_command,
2077 .multicommand = ich_spi_send_multicommand,
2078 .read = default_spi_read,
2079 .write_256 = default_spi_write_256,
2080 .write_aai = default_spi_write_aai,
Michael Karcherb9dbe482011-05-11 17:07:07 +00002081};
2082
Nico Huber560111e2017-04-26 12:27:17 +02002083int via_init_spi(uint32_t mmio_base)
Michael Karchera4448d92010-07-22 18:04:15 +00002084{
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00002085 int i;
Michael Karchera4448d92010-07-22 18:04:15 +00002086
Stefan Tauner7fb5aa02013-08-14 15:48:44 +00002087 ich_spibar = rphysmap("VIA SPI MMIO registers", mmio_base, 0x70);
2088 if (ich_spibar == ERROR_PTR)
2089 return ERROR_FATAL;
Helge Wagnerdd73d832012-08-24 23:03:46 +00002090 /* Do we really need no write enable? Like the LPC one at D17F0 0x40 */
Michael Karchera4448d92010-07-22 18:04:15 +00002091
Michael Karchera4448d92010-07-22 18:04:15 +00002092 /* Not sure if it speaks all these bus protocols. */
Nico Huber2e50cdc2018-09-23 20:20:26 +02002093 internal_buses_supported &= BUS_LPC | BUS_FWH;
Stefan Taunera8d838d2011-11-06 23:51:09 +00002094 ich_generation = CHIPSET_ICH7;
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00002095 register_spi_master(&spi_master_via);
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00002096
2097 msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0));
2098 msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2));
2099 msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(ich_spibar + 4));
2100 for (i = 0; i < 2; i++) {
2101 int offs;
2102 offs = 8 + (i * 8);
2103 msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs,
2104 mmio_readl(ich_spibar + offs), i);
2105 msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
2106 mmio_readl(ich_spibar + offs + 4), i);
2107 }
2108 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
2109 msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar);
2110 msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x54));
2111 msg_pdbg("0x56: 0x%04x (OPTYPE)\n", mmio_readw(ich_spibar + 0x56));
2112 msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(ich_spibar + 0x58));
2113 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + 0x5c));
2114 for (i = 0; i < 3; i++) {
2115 int offs;
2116 offs = 0x60 + (i * 4);
2117 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
2118 mmio_readl(ich_spibar + offs), i);
2119 }
2120 msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n",
2121 mmio_readw(ich_spibar + 0x6c));
2122 if (mmio_readw(ich_spibar) & (1 << 15)) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00002123 msg_pwarn("Warning: SPI Configuration Lockdown activated.\n");
Felix Singer8cfc7372022-08-19 03:10:29 +02002124 ichspi_lock = true;
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00002125 }
2126
Stefan Taunera8d838d2011-11-06 23:51:09 +00002127 ich_set_bbar(0);
Michael Karchera4448d92010-07-22 18:04:15 +00002128 ich_init_opcodes();
2129
2130 return 0;
2131}
2132
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002133#endif