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Ollie Lho184a4042005-11-26 21:55:36 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ollie Lho184a4042005-11-26 21:55:36 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Stefan Reinauer8fa64812009-08-12 09:27:45 +00005 * Copyright (C) 2005-2009 coresystems GmbH
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00007 * Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger
Adam Jurkowskie4984102009-12-21 15:30:46 +00008 * Copyright (C) 2009 Kontron Modular Computers GmbH
Helge Wagnerdd73d832012-08-24 23:03:46 +00009 * Copyright (C) 2011, 2012 Stefan Tauner
Nico Huber93c30692017-03-20 14:25:09 +010010 * Copyright (C) 2017 secunet Security Networks AG
11 * (Written by Nico Huber <nico.huber@secunet.com> for secunet)
Ollie Lho184a4042005-11-26 21:55:36 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
Ollie Lho184a4042005-11-26 21:55:36 +000016 *
Uwe Hermannd1107642007-08-29 17:52:32 +000017 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
Uwe Hermannd1107642007-08-29 17:52:32 +000021 */
22
23/*
24 * Contains the chipset specific flash enables.
Ollie Lho184a4042005-11-26 21:55:36 +000025 */
26
Lane Brooksd54958a2007-11-13 16:45:22 +000027#define _LARGEFILE64_SOURCE
28
Felix Singer980d6b82022-08-19 02:48:15 +020029#include <stdbool.h>
Ollie Lhocbbf1252004-03-17 22:22:08 +000030#include <stdlib.h>
Uwe Hermanne8ba5382009-05-22 11:37:27 +000031#include <string.h>
Carl-Daniel Hailfingerdcef67e2010-06-21 23:20:15 +000032#include <unistd.h>
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +000033#include <inttypes.h>
34#include <errno.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000035#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000036#include "programmer.h"
Thomas Heijligen74b4aa02021-12-14 17:52:30 +010037#include "hwaccess_physmap.h"
Thomas Heijligend96c97c2021-11-02 21:03:00 +010038#include "platform/pci.h"
Stefan Reinauer86de2832006-03-31 11:26:55 +000039
Michael Karcher89bed6d2010-06-13 10:16:12 +000040#define NOT_DONE_YET 1
41
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +000042#if defined(__i386__) || defined(__x86_64__)
43
Peter Marheinedf3672d2022-01-19 17:11:09 +110044#include "hwaccess_x86_io.h"
45#include "hwaccess_x86_msr.h"
46
Uwe Hermann372eeb52007-12-04 21:49:06 +000047static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
Luc Verhaegen6b141752007-05-20 16:16:13 +000048{
49 uint8_t tmp;
50
Uwe Hermann372eeb52007-12-04 21:49:06 +000051 /*
52 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
53 * 0xFFFE0000-0xFFFFFFFF ROM select enable.
54 */
Luc Verhaegen6b141752007-05-20 16:16:13 +000055 tmp = pci_read_byte(dev, 0x47);
56 tmp |= 0x46;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000057 rpci_write_byte(dev, 0x47, tmp);
Luc Verhaegen6b141752007-05-20 16:16:13 +000058
59 return 0;
60}
61
Rudolf Marek23907d82012-02-07 21:29:48 +000062static int enable_flash_rdc_r8610(struct pci_dev *dev, const char *name)
63{
64 uint8_t tmp;
65
66 /* enable ROMCS for writes */
67 tmp = pci_read_byte(dev, 0x43);
68 tmp |= 0x80;
69 pci_write_byte(dev, 0x43, tmp);
70
71 /* read the bootstrapping register */
72 tmp = pci_read_byte(dev, 0x40) & 0x3;
73 switch (tmp) {
74 case 3:
Nico Huber2e50cdc2018-09-23 20:20:26 +020075 internal_buses_supported &= BUS_FWH;
Rudolf Marek23907d82012-02-07 21:29:48 +000076 break;
77 case 2:
Nico Huber2e50cdc2018-09-23 20:20:26 +020078 internal_buses_supported &= BUS_LPC;
Rudolf Marek23907d82012-02-07 21:29:48 +000079 break;
80 default:
Nico Huber2e50cdc2018-09-23 20:20:26 +020081 internal_buses_supported &= BUS_PARALLEL;
Rudolf Marek23907d82012-02-07 21:29:48 +000082 break;
83 }
84
85 return 0;
86}
87
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000088static int enable_flash_sis85c496(struct pci_dev *dev, const char *name)
89{
90 uint8_t tmp;
91
92 tmp = pci_read_byte(dev, 0xd0);
93 tmp |= 0xf8;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000094 rpci_write_byte(dev, 0xd0, tmp);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000095
96 return 0;
97}
98
99static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name)
100{
Stefan Taunere34e3e82013-01-01 00:06:51 +0000101 #define SIS_MAPREG 0x40
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000102 uint8_t new, newer;
103
104 /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
105 /* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
Stefan Taunere34e3e82013-01-01 00:06:51 +0000106 new = pci_read_byte(dev, SIS_MAPREG);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000107 new &= (~0x04); /* No idea why we clear bit 2. */
108 new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */
Stefan Taunere34e3e82013-01-01 00:06:51 +0000109 rpci_write_byte(dev, SIS_MAPREG, new);
110 newer = pci_read_byte(dev, SIS_MAPREG);
111 if (newer != new) { /* FIXME: share this with other code? */
112 msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
113 SIS_MAPREG, new, name);
114 msg_pinfo("Stuck at 0x%02x.\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000115 return -1;
116 }
117 return 0;
118}
119
120static struct pci_dev *find_southbridge(uint16_t vendor, const char *name)
121{
122 struct pci_dev *sbdev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000123
Edward O'Callaghan48a94662022-02-26 11:36:17 +1100124 sbdev = pcidev_find_vendorclass(vendor, 0x0601);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000125 if (!sbdev)
Edward O'Callaghan48a94662022-02-26 11:36:17 +1100126 sbdev = pcidev_find_vendorclass(vendor, 0x0680);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000127 if (!sbdev)
Edward O'Callaghan48a94662022-02-26 11:36:17 +1100128 sbdev = pcidev_find_vendorclass(vendor, 0x0000);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000129 if (!sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +0000130 msg_perr("No southbridge found for %s!\n", name);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000131 if (sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +0000132 msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000133 sbdev->vendor_id, sbdev->device_id,
134 sbdev->bus, sbdev->dev, sbdev->func);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000135 return sbdev;
136}
137
138static int enable_flash_sis501(struct pci_dev *dev, const char *name)
139{
140 uint8_t tmp;
141 int ret = 0;
142 struct pci_dev *sbdev;
143
144 sbdev = find_southbridge(dev->vendor_id, name);
145 if (!sbdev)
146 return -1;
147
148 ret = enable_flash_sis_mapping(sbdev, name);
149
150 tmp = sio_read(0x22, 0x80);
151 tmp &= (~0x20);
152 tmp |= 0x4;
153 sio_write(0x22, 0x80, tmp);
154
155 tmp = sio_read(0x22, 0x70);
156 tmp &= (~0x20);
157 tmp |= 0x4;
158 sio_write(0x22, 0x70, tmp);
Elyes HAOUAS2f1d0072018-10-04 10:42:42 +0200159
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000160 return ret;
161}
162
163static int enable_flash_sis5511(struct pci_dev *dev, const char *name)
164{
165 uint8_t tmp;
166 int ret = 0;
167 struct pci_dev *sbdev;
168
169 sbdev = find_southbridge(dev->vendor_id, name);
170 if (!sbdev)
171 return -1;
172
173 ret = enable_flash_sis_mapping(sbdev, name);
174
175 tmp = sio_read(0x22, 0x50);
176 tmp &= (~0x20);
177 tmp |= 0x4;
178 sio_write(0x22, 0x50, tmp);
179
180 return ret;
181}
182
Stefan Taunere34e3e82013-01-01 00:06:51 +0000183static int enable_flash_sis5x0(struct pci_dev *dev, const char *name, uint8_t dis_mask, uint8_t en_mask)
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000184{
Stefan Taunere34e3e82013-01-01 00:06:51 +0000185 #define SIS_REG 0x45
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000186 uint8_t new, newer;
187 int ret = 0;
188 struct pci_dev *sbdev;
189
190 sbdev = find_southbridge(dev->vendor_id, name);
191 if (!sbdev)
192 return -1;
193
194 ret = enable_flash_sis_mapping(sbdev, name);
195
Stefan Taunere34e3e82013-01-01 00:06:51 +0000196 new = pci_read_byte(sbdev, SIS_REG);
197 new &= (~dis_mask);
198 new |= en_mask;
199 rpci_write_byte(sbdev, SIS_REG, new);
200 newer = pci_read_byte(sbdev, SIS_REG);
201 if (newer != new) { /* FIXME: share this with other code? */
202 msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", SIS_REG, new, name);
203 msg_pinfo("Stuck at 0x%02x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000204 ret = -1;
205 }
206
207 return ret;
208}
209
Stefan Taunere34e3e82013-01-01 00:06:51 +0000210static int enable_flash_sis530(struct pci_dev *dev, const char *name)
211{
212 return enable_flash_sis5x0(dev, name, 0x20, 0x04);
213}
214
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000215static int enable_flash_sis540(struct pci_dev *dev, const char *name)
216{
Stefan Taunere34e3e82013-01-01 00:06:51 +0000217 return enable_flash_sis5x0(dev, name, 0x80, 0x40);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000218}
219
Uwe Hermann987942d2006-11-07 11:16:21 +0000220/* Datasheet:
221 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
222 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
223 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
224 * - Order Number: 290562-001
225 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000226static int enable_flash_piix4(struct pci_dev *dev, const char *name)
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000227{
228 uint16_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000229 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000230
Nico Huber2e50cdc2018-09-23 20:20:26 +0200231 internal_buses_supported &= BUS_PARALLEL;
Maciej Pijankaa661e152009-12-08 17:26:24 +0000232
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000233 old = pci_read_word(dev, xbcs);
234
235 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
Uwe Hermanna7e05482007-05-09 10:17:44 +0000236 * FFF00000-FFF7FFFF are forwarded to ISA).
Uwe Hermannc556d322008-10-28 11:50:05 +0000237 * Note: This bit is reserved on PIIX/PIIX3/MPIIX.
Uwe Hermanna7e05482007-05-09 10:17:44 +0000238 * Set bit 7: Extended BIOS Enable (PCI master accesses to
239 * FFF80000-FFFDFFFF are forwarded to ISA).
240 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
241 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
242 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
243 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
244 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
245 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
246 */
Uwe Hermannc556d322008-10-28 11:50:05 +0000247 if (dev->device_id == 0x122e || dev->device_id == 0x7000
248 || dev->device_id == 0x1234)
249 new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
Uwe Hermann87203452008-10-26 18:40:42 +0000250 else
251 new = old | 0x02c4;
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000252
253 if (new == old)
254 return 0;
255
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000256 rpci_write_word(dev, xbcs, new);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000257
Stefan Taunere34e3e82013-01-01 00:06:51 +0000258 if (pci_read_word(dev, xbcs) != new) { /* FIXME: share this with other code? */
259 msg_pinfo("Setting register 0x%04x to 0x%04x on %s failed (WARNING ONLY).\n", xbcs, new, name);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000260 return -1;
261 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000262
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000263 return 0;
264}
265
Duncan Laurie4095ed72014-08-20 15:39:32 +0000266/* Handle BIOS_CNTL (aka. BCR). Disable locks and enable writes. The register can either be in PCI config space
267 * at the offset given by 'bios_cntl' or at the memory-mapped address 'addr'.
268 *
269 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, in Poulsbo, Tunnel Creek and other Atom
Stefan Tauner92d6a862013-10-25 00:33:37 +0000270 * chipsets/SoCs it is even 32b, but just treating it as 8 bit wide seems to work fine in practice. */
Duncan Laurie4095ed72014-08-20 15:39:32 +0000271static int enable_flash_ich_bios_cntl_common(enum ich_chipset ich_generation, void *addr,
272 struct pci_dev *dev, uint8_t bios_cntl)
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000273{
Stefan Taunerd5c4ab42011-09-09 12:46:32 +0000274 uint8_t old, new, wanted;
Stefan Reinauereb366472006-09-06 15:48:48 +0000275
Stefan Tauner92d6a862013-10-25 00:33:37 +0000276 switch (ich_generation) {
277 case CHIPSET_ICH_UNKNOWN:
278 return ERROR_FATAL;
279 /* Non-SPI-capable */
280 case CHIPSET_ICH:
281 case CHIPSET_ICH2345:
282 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000283 /* Some Atom chipsets are special: The second byte of BIOS_CNTL (D9h) contains a prefetch bit similar to
284 * what other SPI-capable chipsets have at DCh. Others like Bay Trail use a memmapped register.
Stefan Tauner92d6a862013-10-25 00:33:37 +0000285 * The Tunnel Creek datasheet contains a lot of details about the SPI controller, among other things it
286 * mentions that the prefetching and caching does only happen for direct memory reads.
287 * Therefore - at least for Tunnel Creek - it should not matter to flashrom because we use the
288 * programmed access only and not memory mapping. */
289 case CHIPSET_TUNNEL_CREEK:
290 case CHIPSET_POULSBO:
291 case CHIPSET_CENTERTON:
292 old = pci_read_byte(dev, bios_cntl + 1);
293 msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis");
294 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000295 case CHIPSET_BAYTRAIL:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000296 case CHIPSET_ICH7:
297 default: /* Future version might behave the same */
Duncan Laurie4095ed72014-08-20 15:39:32 +0000298 if (ich_generation == CHIPSET_BAYTRAIL)
299 old = (mmio_readl(addr) >> 2) & 0x3;
300 else
301 old = (pci_read_byte(dev, bios_cntl) >> 2) & 0x3;
Stefan Tauner92d6a862013-10-25 00:33:37 +0000302 msg_pdbg("SPI Read Configuration: ");
303 if (old == 3)
304 msg_pdbg("invalid prefetching/caching settings, ");
305 else
306 msg_pdbg("prefetching %sabled, caching %sabled, ",
307 (old & 0x2) ? "en" : "dis",
308 (old & 0x1) ? "dis" : "en");
309 }
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000310
Duncan Laurie4095ed72014-08-20 15:39:32 +0000311 if (ich_generation == CHIPSET_BAYTRAIL)
312 wanted = old = mmio_readl(addr);
313 else
314 wanted = old = pci_read_byte(dev, bios_cntl);
315
Stefan Taunerf9a8da52011-06-11 18:16:50 +0000316 /*
317 * Quote from the 6 Series datasheet (Document Number: 324645-004):
318 * "Bit 5: SMM BIOS Write Protect Disable (SMM_BWP)
319 * 1 = BIOS region SMM protection is enabled.
320 * The BIOS Region is not writable unless all processors are in SMM."
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000321 * In earlier chipsets this bit is reserved.
Stefan Reinauer62218c32012-08-26 02:35:13 +0000322 *
323 * Try to unset it in any case.
324 * It won't hurt and makes sense in some cases according to Stefan Reinauer.
Stefan Tauner92d6a862013-10-25 00:33:37 +0000325 *
326 * At least in Centerton aforementioned bit is located at bit 7. It is unspecified in all other Atom
327 * and Desktop chipsets before Ibex Peak/5 Series, but we reset bit 5 anyway.
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000328 */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000329 int smm_bwp_bit;
330 if (ich_generation == CHIPSET_CENTERTON)
331 smm_bwp_bit = 7;
332 else
333 smm_bwp_bit = 5;
334 wanted &= ~(1 << smm_bwp_bit);
Stefan Reinauer62218c32012-08-26 02:35:13 +0000335
Stefan Tauner92d6a862013-10-25 00:33:37 +0000336 /* Tunnel Creek has a cache disable at bit 2 of the lowest BIOS_CNTL byte. */
337 if (ich_generation == CHIPSET_TUNNEL_CREEK)
338 wanted |= (1 << 2);
339
340 wanted |= (1 << 0); /* Set BIOS Write Enable */
341 wanted &= ~(1 << 1); /* Disable lock (futile) */
Stefan Reinauer62218c32012-08-26 02:35:13 +0000342
343 /* Only write the register if it's necessary */
344 if (wanted != old) {
Duncan Laurie4095ed72014-08-20 15:39:32 +0000345 if (ich_generation == CHIPSET_BAYTRAIL) {
346 rmmio_writel(wanted, addr);
347 new = mmio_readl(addr);
348 } else {
349 rpci_write_byte(dev, bios_cntl, wanted);
350 new = pci_read_byte(dev, bios_cntl);
351 }
Stefan Reinauer62218c32012-08-26 02:35:13 +0000352 } else
353 new = old;
354
355 msg_pdbg("\nBIOS_CNTL = 0x%02x: ", new);
356 msg_pdbg("BIOS Lock Enable: %sabled, ", (new & (1 << 1)) ? "en" : "dis");
357 msg_pdbg("BIOS Write Enable: %sabled\n", (new & (1 << 0)) ? "en" : "dis");
Stefan Tauner92d6a862013-10-25 00:33:37 +0000358 if (new & (1 << smm_bwp_bit))
Stefan Taunerc6fa32d2013-01-04 22:54:07 +0000359 msg_pwarn("Warning: BIOS region SMM protection is enabled!\n");
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000360
Stefan Reinauer62218c32012-08-26 02:35:13 +0000361 if (new != wanted)
Angel Ponsabefc462020-04-29 15:23:59 +0200362 msg_pwarn("Warning: Setting BIOS Control at 0x%x from 0x%02x to 0x%02x failed.\n"
Stefan Tauner92d6a862013-10-25 00:33:37 +0000363 "New value is 0x%02x.\n", bios_cntl, old, wanted, new);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000364
Stefan Tauner92d6a862013-10-25 00:33:37 +0000365 /* Return an error if we could not set the write enable only. */
Stefan Reinauer62218c32012-08-26 02:35:13 +0000366 if (!(new & (1 << 0)))
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000367 return -1;
Uwe Hermannffec5f32007-08-23 16:08:21 +0000368
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000369 return 0;
370}
371
Duncan Laurie4095ed72014-08-20 15:39:32 +0000372static int enable_flash_ich_bios_cntl_config_space(struct pci_dev *dev, enum ich_chipset ich_generation,
373 uint8_t bios_cntl)
374{
375 return enable_flash_ich_bios_cntl_common(ich_generation, NULL, dev, bios_cntl);
376}
377
378static int enable_flash_ich_bios_cntl_memmapped(enum ich_chipset ich_generation, void *addr)
379{
380 return enable_flash_ich_bios_cntl_common(ich_generation, addr, NULL, 0);
381}
382
Stefan Tauner92d6a862013-10-25 00:33:37 +0000383static int enable_flash_ich_fwh_decode(struct pci_dev *dev, enum ich_chipset ich_generation)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000384{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000385 uint8_t fwh_sel1 = 0, fwh_sel2 = 0, fwh_dec_en_lo = 0, fwh_dec_en_hi = 0; /* silence compilers */
386 bool implemented = 0;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000387 void *ilb = NULL; /* Only for Baytrail */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000388 switch (ich_generation) {
389 case CHIPSET_ICH:
390 /* FIXME: Unlike later chipsets, ICH and ICH-0 do only support mapping of the top-most 4MB
391 * and therefore do only feature FWH_DEC_EN (E3h, different default too) and FWH_SEL (E8h). */
392 break;
393 case CHIPSET_ICH2345:
Kyösti Mälkki88ee0402013-09-14 23:37:01 +0000394 fwh_sel1 = 0xe8;
395 fwh_sel2 = 0xee;
396 fwh_dec_en_lo = 0xf0;
397 fwh_dec_en_hi = 0xe3;
Stefan Tauner92d6a862013-10-25 00:33:37 +0000398 implemented = 1;
399 break;
400 case CHIPSET_POULSBO:
401 case CHIPSET_TUNNEL_CREEK:
402 /* FIXME: Similar to ICH and ICH-0, Tunnel Creek and Poulsbo do only feature one register each,
403 * FWH_DEC_EN (D7h) and FWH_SEL (D0h). */
404 break;
405 case CHIPSET_CENTERTON:
406 /* FIXME: Similar to above FWH_DEC_EN (D4h) and FWH_SEL (D0h). */
407 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000408 case CHIPSET_BAYTRAIL: {
409 uint32_t ilb_base = pci_read_long(dev, 0x50) & 0xfffffe00; /* bits 31:9 */
410 if (ilb_base == 0) {
411 msg_perr("Error: Invalid ILB_BASE_ADDRESS\n");
412 return ERROR_FATAL;
413 }
414 ilb = rphysmap("BYT IBASE", ilb_base, 512);
415 fwh_sel1 = 0x18;
416 fwh_dec_en_lo = 0xd8;
417 fwh_dec_en_hi = 0xd9;
418 implemented = 1;
419 break;
420 }
Stefan Tauner92d6a862013-10-25 00:33:37 +0000421 case CHIPSET_ICH6:
422 case CHIPSET_ICH7:
423 default: /* Future version might behave the same */
424 fwh_sel1 = 0xd0;
425 fwh_sel2 = 0xd4;
426 fwh_dec_en_lo = 0xd8;
427 fwh_dec_en_hi = 0xd9;
428 implemented = 1;
429 break;
Kyösti Mälkki88ee0402013-09-14 23:37:01 +0000430 }
Kyösti Mälkki743babc2013-09-14 23:36:53 +0000431
Stefan Tauner92d6a862013-10-25 00:33:37 +0000432 char *idsel = extract_programmer_param("fwh_idsel");
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000433 if (idsel && strlen(idsel)) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000434 if (!implemented) {
435 msg_perr("Error: fwh_idsel= specified, but (yet) unsupported on this chipset.\n");
436 goto idsel_garbage_out;
437 }
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000438 errno = 0;
439 /* Base 16, nothing else makes sense. */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000440 uint64_t fwh_idsel = (uint64_t)strtoull(idsel, NULL, 16);
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000441 if (errno) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000442 msg_perr("Error: fwh_idsel= specified, but value could not be converted.\n");
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000443 goto idsel_garbage_out;
444 }
Duncan Laurie4095ed72014-08-20 15:39:32 +0000445 uint64_t fwh_mask = 0xffffffff;
446 if (fwh_sel2 > 0)
447 fwh_mask |= (0xffffULL << 32);
448 if (fwh_idsel & ~fwh_mask) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000449 msg_perr("Error: fwh_idsel= specified, but value had unused bits set.\n");
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000450 goto idsel_garbage_out;
451 }
Duncan Laurie4095ed72014-08-20 15:39:32 +0000452 uint64_t fwh_idsel_old;
453 if (ich_generation == CHIPSET_BAYTRAIL) {
454 fwh_idsel_old = mmio_readl(ilb + fwh_sel1);
455 rmmio_writel(fwh_idsel, ilb + fwh_sel1);
456 } else {
Stefan Tauner5c316f92015-02-08 21:57:52 +0000457 fwh_idsel_old = (uint64_t)pci_read_long(dev, fwh_sel1) << 16;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000458 rpci_write_long(dev, fwh_sel1, (fwh_idsel >> 16) & 0xffffffff);
459 if (fwh_sel2 > 0) {
460 fwh_idsel_old |= pci_read_word(dev, fwh_sel2);
461 rpci_write_word(dev, fwh_sel2, fwh_idsel & 0xffff);
462 }
463 }
Stefan Taunereff156e2014-07-13 17:06:11 +0000464 msg_pdbg("Setting IDSEL from 0x%012" PRIx64 " to 0x%012" PRIx64 " for top 16 MB.\n",
Stefan Tauner92d6a862013-10-25 00:33:37 +0000465 fwh_idsel_old, fwh_idsel);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000466 /* FIXME: Decode settings are not changed. */
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000467 } else if (idsel) {
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000468 msg_perr("Error: fwh_idsel= specified, but no value given.\n");
Sylvain "ythier" Hitier3093f8f2011-09-03 11:22:27 +0000469idsel_garbage_out:
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000470 free(idsel);
Tadas Slotkus0e3f1cf2011-09-06 18:49:31 +0000471 return ERROR_FATAL;
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000472 }
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000473 free(idsel);
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000474
Stefan Tauner92d6a862013-10-25 00:33:37 +0000475 if (!implemented) {
Stefan Taunereff156e2014-07-13 17:06:11 +0000476 msg_pdbg2("FWH IDSEL handling is not implemented on this chipset.\n");
Stefan Tauner92d6a862013-10-25 00:33:37 +0000477 return 0;
478 }
479
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000480 /* Ignore all legacy ranges below 1 MB.
481 * We currently only support flashing the chip which responds to
482 * IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations
483 * have to be adjusted.
484 */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000485 int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0;
486 bool contiguous = 1;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000487 uint32_t fwh_conf;
488 if (ich_generation == CHIPSET_BAYTRAIL)
489 fwh_conf = mmio_readl(ilb + fwh_sel1);
490 else
491 fwh_conf = pci_read_long(dev, fwh_sel1);
492
Stefan Tauner92d6a862013-10-25 00:33:37 +0000493 int i;
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000494 /* FWH_SEL1 */
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000495 for (i = 7; i >= 0; i--) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000496 int tmp = (fwh_conf >> (i * 4)) & 0xf;
Stefan Taunereff156e2014-07-13 17:06:11 +0000497 msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000498 (0x1ff8 + i) * 0x80000,
499 (0x1ff0 + i) * 0x80000,
500 tmp);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000501 if ((tmp == 0) && contiguous) {
502 max_decode_fwh_idsel = (8 - i) * 0x80000;
503 } else {
504 contiguous = 0;
505 }
506 }
Duncan Laurie4095ed72014-08-20 15:39:32 +0000507 if (fwh_sel2 > 0) {
508 /* FWH_SEL2 */
509 fwh_conf = pci_read_word(dev, fwh_sel2);
510 for (i = 3; i >= 0; i--) {
511 int tmp = (fwh_conf >> (i * 4)) & 0xf;
512 msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n",
513 (0xff4 + i) * 0x100000,
514 (0xff0 + i) * 0x100000,
515 tmp);
516 if ((tmp == 0) && contiguous) {
517 max_decode_fwh_idsel = (8 - i) * 0x100000;
518 } else {
519 contiguous = 0;
520 }
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000521 }
522 }
523 contiguous = 1;
524 /* FWH_DEC_EN1 */
Kyösti Mälkki743babc2013-09-14 23:36:53 +0000525 fwh_conf = pci_read_byte(dev, fwh_dec_en_hi);
526 fwh_conf <<= 8;
527 fwh_conf |= pci_read_byte(dev, fwh_dec_en_lo);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000528 for (i = 7; i >= 0; i--) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000529 int tmp = (fwh_conf >> (i + 0x8)) & 0x1;
Stefan Taunereff156e2014-07-13 17:06:11 +0000530 msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000531 (0x1ff8 + i) * 0x80000,
532 (0x1ff0 + i) * 0x80000,
533 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000534 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000535 max_decode_fwh_decode = (8 - i) * 0x80000;
536 } else {
537 contiguous = 0;
538 }
539 }
540 for (i = 3; i >= 0; i--) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000541 int tmp = (fwh_conf >> i) & 0x1;
Stefan Taunereff156e2014-07-13 17:06:11 +0000542 msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000543 (0xff4 + i) * 0x100000,
544 (0xff0 + i) * 0x100000,
545 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000546 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000547 max_decode_fwh_decode = (8 - i) * 0x100000;
548 } else {
549 contiguous = 0;
550 }
551 }
552 max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode);
Stefan Taunereff156e2014-07-13 17:06:11 +0000553 msg_pdbg("Maximum FWH chip size: 0x%x bytes\n", max_rom_decode.fwh);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000554
Kyösti Mälkki743babc2013-09-14 23:36:53 +0000555 return 0;
556}
557
Stefan Tauner92d6a862013-10-25 00:33:37 +0000558static int enable_flash_ich_fwh(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl)
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000559{
Kyösti Mälkki88ee0402013-09-14 23:37:01 +0000560 int err;
561
562 /* Configure FWH IDSEL decoder maps. */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000563 if ((err = enable_flash_ich_fwh_decode(dev, ich_generation)) != 0)
Kyösti Mälkki88ee0402013-09-14 23:37:01 +0000564 return err;
565
Nico Huber2e50cdc2018-09-23 20:20:26 +0200566 internal_buses_supported &= BUS_FWH;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000567 return enable_flash_ich_bios_cntl_config_space(dev, ich_generation, bios_cntl);
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000568}
569
Stefan Tauner92d6a862013-10-25 00:33:37 +0000570static int enable_flash_ich0(struct pci_dev *dev, const char *name)
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000571{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000572 return enable_flash_ich_fwh(dev, CHIPSET_ICH, 0x4e);
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000573}
574
Stefan Tauner92d6a862013-10-25 00:33:37 +0000575static int enable_flash_ich2345(struct pci_dev *dev, const char *name)
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000576{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000577 return enable_flash_ich_fwh(dev, CHIPSET_ICH2345, 0x4e);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000578}
579
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000580static int enable_flash_ich6(struct pci_dev *dev, const char *name)
581{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000582 return enable_flash_ich_fwh(dev, CHIPSET_ICH6, 0xdc);
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000583}
584
Adam Jurkowskie4984102009-12-21 15:30:46 +0000585static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
586{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000587 return enable_flash_ich_fwh(dev, CHIPSET_POULSBO, 0xd8);
Adam Jurkowskie4984102009-12-21 15:30:46 +0000588}
589
Nico Huber2e50cdc2018-09-23 20:20:26 +0200590static enum chipbustype enable_flash_ich_report_gcs(
591 struct pci_dev *const dev, const enum ich_chipset ich_generation, const uint8_t *const rcrb)
Ingo Feldschmiddadc0a62011-09-07 19:18:25 +0000592{
Nico Huber0ea99f52017-03-17 17:22:53 +0100593 uint32_t gcs;
Nico Huber93c30692017-03-20 14:25:09 +0100594 const char *reg_name;
595 bool bild, top_swap;
Nico Huber0ea99f52017-03-17 17:22:53 +0100596
597 switch (ich_generation) {
598 case CHIPSET_BAYTRAIL:
Nico Huber93c30692017-03-20 14:25:09 +0100599 reg_name = "GCS";
Nico Huber0ea99f52017-03-17 17:22:53 +0100600 gcs = mmio_readl(rcrb + 0);
Nico Huber93c30692017-03-20 14:25:09 +0100601 bild = gcs & 1;
Nico Huber0ea99f52017-03-17 17:22:53 +0100602 top_swap = (gcs & 2) >> 1;
603 break;
Nico Huber93c30692017-03-20 14:25:09 +0100604 case CHIPSET_100_SERIES_SUNRISE_POINT:
David Hendricksa5216362017-08-08 20:02:22 -0700605 case CHIPSET_C620_SERIES_LEWISBURG:
Thomas Heijligen5ec84b32019-03-19 17:00:03 +0100606 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200607 case CHIPSET_500_SERIES_TIGER_POINT:
Werner Zehe57d4e42022-01-03 09:44:29 +0100608 case CHIPSET_ELKHART_LAKE:
Nico Huber37509862019-01-18 14:23:02 +0100609 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +0200610 case CHIPSET_GEMINI_LAKE:
Nico Huber93c30692017-03-20 14:25:09 +0100611 reg_name = "BIOS_SPI_BC";
612 gcs = pci_read_long(dev, 0xdc);
613 bild = (gcs >> 7) & 1;
614 top_swap = (gcs >> 4) & 1;
615 break;
Nico Huber0ea99f52017-03-17 17:22:53 +0100616 default:
Nico Huber93c30692017-03-20 14:25:09 +0100617 reg_name = "GCS";
Nico Huber0ea99f52017-03-17 17:22:53 +0100618 gcs = mmio_readl(rcrb + 0x3410);
Nico Huber93c30692017-03-20 14:25:09 +0100619 bild = gcs & 1;
Nico Huber0ea99f52017-03-17 17:22:53 +0100620 top_swap = mmio_readb(rcrb + 0x3414) & 1;
621 break;
622 }
623
Nico Huber93c30692017-03-20 14:25:09 +0100624 msg_pdbg("%s = 0x%x: ", reg_name, gcs);
625 msg_pdbg("BIOS Interface Lock-Down: %sabled, ", bild ? "en" : "dis");
Duncan Laurie4095ed72014-08-20 15:39:32 +0000626
Nico Huber2e50cdc2018-09-23 20:20:26 +0200627 struct boot_straps {
628 const char *name;
629 enum chipbustype bus;
630 };
631 static const struct boot_straps boot_straps_EP80579[] =
632 { { "SPI", BUS_SPI },
Nico Hubera508ca02019-07-24 19:34:43 +0200633 { "reserved", BUS_NONE },
634 { "reserved", BUS_NONE },
Nico Huber2e50cdc2018-09-23 20:20:26 +0200635 { "LPC", BUS_LPC | BUS_FWH } };
636 static const struct boot_straps boot_straps_ich7_nm10[] =
Nico Hubera508ca02019-07-24 19:34:43 +0200637 { { "reserved", BUS_NONE },
Nico Huber2e50cdc2018-09-23 20:20:26 +0200638 { "SPI", BUS_SPI },
Nico Hubera508ca02019-07-24 19:34:43 +0200639 { "PCI", BUS_NONE },
Nico Huber2e50cdc2018-09-23 20:20:26 +0200640 { "LPC", BUS_LPC | BUS_FWH } };
641 static const struct boot_straps boot_straps_tunnel_creek[] =
642 { { "SPI", BUS_SPI },
643 { "LPC", BUS_LPC | BUS_FWH } };
644 static const struct boot_straps boot_straps_ich8910[] =
645 { { "SPI", BUS_SPI },
646 { "SPI", BUS_SPI },
Nico Hubera508ca02019-07-24 19:34:43 +0200647 { "PCI", BUS_NONE },
Nico Huber2e50cdc2018-09-23 20:20:26 +0200648 { "LPC", BUS_LPC | BUS_FWH } };
649 static const struct boot_straps boot_straps_pch567[] =
650 { { "LPC", BUS_LPC | BUS_FWH },
Nico Hubera508ca02019-07-24 19:34:43 +0200651 { "reserved", BUS_NONE },
652 { "PCI", BUS_NONE },
Nico Huber2e50cdc2018-09-23 20:20:26 +0200653 { "SPI", BUS_SPI } };
654 static const struct boot_straps boot_straps_pch89_baytrail[] =
655 { { "LPC", BUS_LPC | BUS_FWH },
Nico Hubera508ca02019-07-24 19:34:43 +0200656 { "reserved", BUS_NONE },
657 { "reserved", BUS_NONE },
Nico Huber2e50cdc2018-09-23 20:20:26 +0200658 { "SPI", BUS_SPI } };
659 static const struct boot_straps boot_straps_pch8_lp[] =
660 { { "SPI", BUS_SPI },
661 { "LPC", BUS_LPC | BUS_FWH } };
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200662 static const struct boot_straps boot_straps_pch500[] =
663 { { "SPI", BUS_SPI },
664 { "eSPI", BUS_NONE } };
Nico Huber37509862019-01-18 14:23:02 +0100665 static const struct boot_straps boot_straps_apl[] =
666 { { "SPI", BUS_SPI },
Nico Hubera508ca02019-07-24 19:34:43 +0200667 { "reserved", BUS_NONE } };
Nico Huber2e50cdc2018-09-23 20:20:26 +0200668 static const struct boot_straps boot_straps_unknown[] =
Nico Hubera508ca02019-07-24 19:34:43 +0200669 { { "unknown", BUS_NONE },
670 { "unknown", BUS_NONE },
671 { "unknown", BUS_NONE },
672 { "unknown", BUS_NONE } };
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000673
Nico Huber2e50cdc2018-09-23 20:20:26 +0200674 const struct boot_straps *boot_straps;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000675 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +0000676 case CHIPSET_ICH7:
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000677 /* EP80579 may need further changes, but this is the least
678 * intrusive way to get correct BOOT Strap printing without
679 * changing the rest of its code path). */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000680 if (dev->device_id == 0x5031)
Nico Huber2e50cdc2018-09-23 20:20:26 +0200681 boot_straps = boot_straps_EP80579;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000682 else
Nico Huber2e50cdc2018-09-23 20:20:26 +0200683 boot_straps = boot_straps_ich7_nm10;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000684 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000685 case CHIPSET_ICH8:
686 case CHIPSET_ICH9:
687 case CHIPSET_ICH10:
Nico Huber2e50cdc2018-09-23 20:20:26 +0200688 boot_straps = boot_straps_ich8910;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000689 break;
Stefan Tauner92d6a862013-10-25 00:33:37 +0000690 case CHIPSET_TUNNEL_CREEK:
Nico Huber2e50cdc2018-09-23 20:20:26 +0200691 boot_straps = boot_straps_tunnel_creek;
Stefan Tauner92d6a862013-10-25 00:33:37 +0000692 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000693 case CHIPSET_5_SERIES_IBEX_PEAK:
694 case CHIPSET_6_SERIES_COUGAR_POINT:
Helge Wagnera0fce5f2012-07-24 16:33:55 +0000695 case CHIPSET_7_SERIES_PANTHER_POINT:
Nico Huber2e50cdc2018-09-23 20:20:26 +0200696 boot_straps = boot_straps_pch567;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000697 break;
Duncan Laurie90eb2262013-03-15 03:12:29 +0000698 case CHIPSET_8_SERIES_LYNX_POINT:
Duncan Laurie823096e2014-08-20 15:39:38 +0000699 case CHIPSET_9_SERIES_WILDCAT_POINT:
Duncan Laurie4095ed72014-08-20 15:39:32 +0000700 case CHIPSET_BAYTRAIL:
Nico Huber2e50cdc2018-09-23 20:20:26 +0200701 boot_straps = boot_straps_pch89_baytrail;
Duncan Laurie90eb2262013-03-15 03:12:29 +0000702 break;
703 case CHIPSET_8_SERIES_LYNX_POINT_LP:
Nico Huber51205912017-03-17 17:59:54 +0100704 case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
Nico Huber93c30692017-03-20 14:25:09 +0100705 case CHIPSET_100_SERIES_SUNRISE_POINT:
David Hendricksa5216362017-08-08 20:02:22 -0700706 case CHIPSET_C620_SERIES_LEWISBURG:
Thomas Heijligen5ec84b32019-03-19 17:00:03 +0100707 case CHIPSET_300_SERIES_CANNON_POINT:
Nico Huber2e50cdc2018-09-23 20:20:26 +0200708 boot_straps = boot_straps_pch8_lp;
Duncan Laurie90eb2262013-03-15 03:12:29 +0000709 break;
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200710 case CHIPSET_500_SERIES_TIGER_POINT:
711 boot_straps = boot_straps_pch500;
712 break;
Nico Huber37509862019-01-18 14:23:02 +0100713 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +0200714 case CHIPSET_GEMINI_LAKE:
Werner Zehe57d4e42022-01-03 09:44:29 +0100715 case CHIPSET_ELKHART_LAKE:
Nico Huber37509862019-01-18 14:23:02 +0100716 boot_straps = boot_straps_apl;
717 break;
Duncan Laurie90eb2262013-03-15 03:12:29 +0000718 case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
Stefan Tauner92d6a862013-10-25 00:33:37 +0000719 case CHIPSET_CENTERTON: // FIXME: Datasheet does not mention GCS at all
Nico Huber2e50cdc2018-09-23 20:20:26 +0200720 boot_straps = boot_straps_unknown;
Duncan Laurie90eb2262013-03-15 03:12:29 +0000721 break;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000722 default:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000723 msg_gerr("%s: unknown ICH generation. Please report!\n", __func__);
Nico Huber2e50cdc2018-09-23 20:20:26 +0200724 boot_straps = boot_straps_unknown;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000725 break;
726 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000727
Duncan Laurie4095ed72014-08-20 15:39:32 +0000728 uint8_t bbs;
729 switch (ich_generation) {
730 case CHIPSET_TUNNEL_CREEK:
731 bbs = (gcs >> 1) & 0x1;
732 break;
733 case CHIPSET_8_SERIES_LYNX_POINT_LP:
Nico Huber51205912017-03-17 17:59:54 +0100734 case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
735 /* LP PCHs use a single bit for BBS */
Duncan Laurie4095ed72014-08-20 15:39:32 +0000736 bbs = (gcs >> 10) & 0x1;
737 break;
Nico Huber93c30692017-03-20 14:25:09 +0100738 case CHIPSET_100_SERIES_SUNRISE_POINT:
David Hendricksa5216362017-08-08 20:02:22 -0700739 case CHIPSET_C620_SERIES_LEWISBURG:
Thomas Heijligen5ec84b32019-03-19 17:00:03 +0100740 case CHIPSET_300_SERIES_CANNON_POINT:
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200741 case CHIPSET_500_SERIES_TIGER_POINT:
Nico Huber37509862019-01-18 14:23:02 +0100742 case CHIPSET_APOLLO_LAKE:
Angel Pons4db0fdf2020-07-10 17:04:10 +0200743 case CHIPSET_GEMINI_LAKE:
Werner Zehe57d4e42022-01-03 09:44:29 +0100744 case CHIPSET_ELKHART_LAKE:
Nico Huber93c30692017-03-20 14:25:09 +0100745 bbs = (gcs >> 6) & 0x1;
746 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000747 default:
748 /* Other chipsets use two bits for BBS */
749 bbs = (gcs >> 10) & 0x3;
750 break;
751 }
Nico Huber2e50cdc2018-09-23 20:20:26 +0200752 msg_pdbg("Boot BIOS Straps: 0x%x (%s)\n", bbs, boot_straps[bbs].name);
Duncan Laurie4095ed72014-08-20 15:39:32 +0000753
754 /* Centerton has its TS bit in [GPE0BLK] + 0x30 while the exact location for Tunnel Creek is unknown. */
755 if (ich_generation != CHIPSET_TUNNEL_CREEK && ich_generation != CHIPSET_CENTERTON)
756 msg_pdbg("Top Swap: %s\n", (top_swap) ? "enabled (A16(+) inverted)" : "not enabled");
Nico Huber2e50cdc2018-09-23 20:20:26 +0200757
758 return boot_straps[bbs].bus;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000759}
760
761static int enable_flash_ich_spi(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl)
762{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000763 /* Get physical address of Root Complex Register Block */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000764 uint32_t rcra = pci_read_long(dev, 0xf0) & 0xffffc000;
765 msg_pdbg("Root Complex Register Block address = 0x%x\n", rcra);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000766
767 /* Map RCBA to virtual memory */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000768 void *rcrb = rphysmap("ICH RCRB", rcra, 0x4000);
Stefan Tauner7fb5aa02013-08-14 15:48:44 +0000769 if (rcrb == ERROR_PTR)
Niklas Söderlund5d307202013-09-14 09:02:27 +0000770 return ERROR_FATAL;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000771
Nico Huber2e50cdc2018-09-23 20:20:26 +0200772 const enum chipbustype boot_buses = enable_flash_ich_report_gcs(dev, ich_generation, rcrb);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000773
Stefan Tauner92d6a862013-10-25 00:33:37 +0000774 /* Handle FWH-related parameters and initialization */
775 int ret_fwh = enable_flash_ich_fwh(dev, ich_generation, bios_cntl);
776 if (ret_fwh == ERROR_FATAL)
777 return ret_fwh;
778
Angel Pons399a4dd2020-04-15 12:59:42 +0200779 /*
780 * It seems that the ICH7 does not support SPI and LPC chips at the same time. When booted
781 * from LPC, the SCIP bit will never clear, which causes long delays and many error messages.
782 * To avoid this, we will not enable SPI on ICH7 when the southbridge is strapped to LPC.
783 */
784 if (ich_generation == CHIPSET_ICH7 && (boot_buses & BUS_LPC))
785 return 0;
786
Stefan Tauner92d6a862013-10-25 00:33:37 +0000787 /* SPIBAR is at RCRB+0x3020 for ICH[78], Tunnel Creek and Centerton, and RCRB+0x3800 for ICH9. */
788 uint16_t spibar_offset;
789 switch (ich_generation) {
Duncan Laurie4095ed72014-08-20 15:39:32 +0000790 case CHIPSET_BAYTRAIL:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000791 case CHIPSET_ICH_UNKNOWN:
792 return ERROR_FATAL;
793 case CHIPSET_ICH7:
794 case CHIPSET_ICH8:
795 case CHIPSET_TUNNEL_CREEK:
796 case CHIPSET_CENTERTON:
797 spibar_offset = 0x3020;
798 break;
799 case CHIPSET_ICH9:
800 default: /* Future version might behave the same */
801 spibar_offset = 0x3800;
802 break;
803 }
804 msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " + 0x%04x\n", PRIxPTR_WIDTH, (uintptr_t)rcrb, spibar_offset);
805 void *spibar = rcrb + spibar_offset;
806
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000807 /* This adds BUS_SPI */
Nico Huber560111e2017-04-26 12:27:17 +0200808 int ret_spi = ich_init_spi(spibar, ich_generation);
Stefan Tauner50e7c602011-11-08 10:55:54 +0000809 if (ret_spi == ERROR_FATAL)
810 return ret_spi;
Elyes HAOUAS0cacb112019-02-04 12:16:38 +0100811
Nico Huber2e50cdc2018-09-23 20:20:26 +0200812 if (((boot_buses & BUS_FWH) && ret_fwh) || ((boot_buses & BUS_SPI) && ret_spi))
Stefan Tauner92d6a862013-10-25 00:33:37 +0000813 return ERROR_NONFATAL;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000814
Nico Huber2e50cdc2018-09-23 20:20:26 +0200815 /* Suppress unknown laptop warning if we booted from SPI. */
816 if (boot_buses & BUS_SPI)
Felix Singerd1ab7d22022-08-19 03:03:47 +0200817 laptop_ok = true;
Nico Huber2e50cdc2018-09-23 20:20:26 +0200818
Stefan Tauner92d6a862013-10-25 00:33:37 +0000819 return 0;
820}
821
822static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name)
823{
824 return enable_flash_ich_spi(dev, CHIPSET_TUNNEL_CREEK, 0xd8);
825}
826
827static int enable_flash_s12x0(struct pci_dev *dev, const char *name)
828{
829 return enable_flash_ich_spi(dev, CHIPSET_CENTERTON, 0xd8);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000830}
Stefan Reinauera9424d52008-06-27 16:28:34 +0000831
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000832static int enable_flash_ich7(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000833{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000834 return enable_flash_ich_spi(dev, CHIPSET_ICH7, 0xdc);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000835}
836
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000837static int enable_flash_ich8(struct pci_dev *dev, const char *name)
838{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000839 return enable_flash_ich_spi(dev, CHIPSET_ICH8, 0xdc);
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000840}
841
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000842static int enable_flash_ich9(struct pci_dev *dev, const char *name)
843{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000844 return enable_flash_ich_spi(dev, CHIPSET_ICH9, 0xdc);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000845}
846
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000847static int enable_flash_ich10(struct pci_dev *dev, const char *name)
848{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000849 return enable_flash_ich_spi(dev, CHIPSET_ICH10, 0xdc);
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000850}
851
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000852/* Ibex Peak aka. 5 series & 3400 series */
853static int enable_flash_pch5(struct pci_dev *dev, const char *name)
854{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000855 return enable_flash_ich_spi(dev, CHIPSET_5_SERIES_IBEX_PEAK, 0xdc);
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000856}
857
858/* Cougar Point aka. 6 series & c200 series */
859static int enable_flash_pch6(struct pci_dev *dev, const char *name)
860{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000861 return enable_flash_ich_spi(dev, CHIPSET_6_SERIES_COUGAR_POINT, 0xdc);
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000862}
863
Stefan Tauner2abab942012-04-27 20:41:23 +0000864/* Panther Point aka. 7 series */
865static int enable_flash_pch7(struct pci_dev *dev, const char *name)
866{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000867 return enable_flash_ich_spi(dev, CHIPSET_7_SERIES_PANTHER_POINT, 0xdc);
Stefan Tauner2abab942012-04-27 20:41:23 +0000868}
869
870/* Lynx Point aka. 8 series */
871static int enable_flash_pch8(struct pci_dev *dev, const char *name)
872{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000873 return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT, 0xdc);
Stefan Tauner2abab942012-04-27 20:41:23 +0000874}
875
Stefan Tauner92d6a862013-10-25 00:33:37 +0000876/* Lynx Point LP aka. 8 series low-power */
Duncan Laurie90eb2262013-03-15 03:12:29 +0000877static int enable_flash_pch8_lp(struct pci_dev *dev, const char *name)
878{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000879 return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT_LP, 0xdc);
Duncan Laurie90eb2262013-03-15 03:12:29 +0000880}
881
882/* Wellsburg (for Haswell-EP Xeons) */
883static int enable_flash_pch8_wb(struct pci_dev *dev, const char *name)
884{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000885 return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_WELLSBURG, 0xdc);
Duncan Laurie90eb2262013-03-15 03:12:29 +0000886}
887
Duncan Laurie823096e2014-08-20 15:39:38 +0000888/* Wildcat Point */
889static int enable_flash_pch9(struct pci_dev *dev, const char *name)
890{
891 return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc);
892}
893
Nico Huber51205912017-03-17 17:59:54 +0100894/* Wildcat Point LP */
895static int enable_flash_pch9_lp(struct pci_dev *dev, const char *name)
896{
897 return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT_LP, 0xdc);
898}
899
Nico Huber93c30692017-03-20 14:25:09 +0100900/* Sunrise Point */
901static int enable_flash_pch100_shutdown(void *const pci_acc)
902{
903 pci_cleanup(pci_acc);
904 return 0;
905}
906
Nico Huber37509862019-01-18 14:23:02 +0100907static int enable_flash_pch100_or_c620(
908 struct pci_dev *const dev, const char *const name,
909 const int slot, const int func, const enum ich_chipset pch_generation)
Nico Huber93c30692017-03-20 14:25:09 +0100910{
Nico Huber93c30692017-03-20 14:25:09 +0100911 int ret = ERROR_FATAL;
912
913 /*
914 * The SPI PCI device is usually hidden (by hiding PCI vendor
915 * and device IDs). So we need a PCI access method that works
916 * even when the OS doesn't know the PCI device. We can't use
917 * this method globally since it would bring along other con-
918 * straints (e.g. on PCI domains, extended PCIe config space).
919 */
920 struct pci_access *const pci_acc = pci_alloc();
Youness Alaouia54ceb12017-07-26 18:03:36 -0400921 struct pci_access *const saved_pacc = pacc;
Nico Huber93c30692017-03-20 14:25:09 +0100922 if (!pci_acc) {
923 msg_perr("Can't allocate PCI accessor.\n");
924 return ret;
925 }
926 pci_acc->method = PCI_ACCESS_I386_TYPE1;
927 pci_init(pci_acc);
928 register_shutdown(enable_flash_pch100_shutdown, pci_acc);
929
Nico Huber37509862019-01-18 14:23:02 +0100930 struct pci_dev *const spi_dev = pci_get_dev(pci_acc, dev->domain, dev->bus, slot, func);
Nico Huber93c30692017-03-20 14:25:09 +0100931 if (!spi_dev) {
932 msg_perr("Can't allocate PCI device.\n");
933 return ret;
934 }
935
Youness Alaouia54ceb12017-07-26 18:03:36 -0400936 /* Modify pacc so the rpci_write can register the undo callback with a
937 * device using the correct pci_access */
938 pacc = pci_acc;
Nico Huber2e50cdc2018-09-23 20:20:26 +0200939 const enum chipbustype boot_buses = enable_flash_ich_report_gcs(spi_dev, pch_generation, NULL);
Nico Huber93c30692017-03-20 14:25:09 +0100940
941 const int ret_bc = enable_flash_ich_bios_cntl_config_space(spi_dev, pch_generation, 0xdc);
942 if (ret_bc == ERROR_FATAL)
943 goto _freepci_ret;
944
945 const uint32_t phys_spibar = pci_read_long(spi_dev, PCI_BASE_ADDRESS_0) & 0xfffff000;
946 void *const spibar = rphysmap("SPIBAR", phys_spibar, 0x1000);
947 if (spibar == ERROR_PTR)
948 goto _freepci_ret;
949 msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " (phys = 0x%08x)\n", PRIxPTR_WIDTH, (uintptr_t)spibar, phys_spibar);
950
951 /* This adds BUS_SPI */
952 const int ret_spi = ich_init_spi(spibar, pch_generation);
953 if (ret_spi != ERROR_FATAL) {
954 if (ret_bc || ret_spi)
955 ret = ERROR_NONFATAL;
956 else
957 ret = 0;
958 }
959
Nico Huber2e50cdc2018-09-23 20:20:26 +0200960 /* Suppress unknown laptop warning if we booted from SPI. */
961 if (!ret && (boot_buses & BUS_SPI))
Felix Singerd1ab7d22022-08-19 03:03:47 +0200962 laptop_ok = true;
Nico Huber2e50cdc2018-09-23 20:20:26 +0200963
Nico Huber93c30692017-03-20 14:25:09 +0100964_freepci_ret:
965 pci_free_dev(spi_dev);
Youness Alaouia54ceb12017-07-26 18:03:36 -0400966 pacc = saved_pacc;
Nico Huber93c30692017-03-20 14:25:09 +0100967 return ret;
968}
969
David Hendricksa5216362017-08-08 20:02:22 -0700970static int enable_flash_pch100(struct pci_dev *const dev, const char *const name)
971{
Nico Huber37509862019-01-18 14:23:02 +0100972 return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_100_SERIES_SUNRISE_POINT);
David Hendricksa5216362017-08-08 20:02:22 -0700973}
974
975static int enable_flash_c620(struct pci_dev *const dev, const char *const name)
976{
Nico Huber37509862019-01-18 14:23:02 +0100977 return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_C620_SERIES_LEWISBURG);
978}
979
Thomas Heijligen5ec84b32019-03-19 17:00:03 +0100980static int enable_flash_pch300(struct pci_dev *const dev, const char *const name)
981{
982 return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_300_SERIES_CANNON_POINT);
983}
984
Michał Żygowski5c9f5422021-06-16 15:13:54 +0200985static int enable_flash_pch500(struct pci_dev *const dev, const char *const name)
986{
987 return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_500_SERIES_TIGER_POINT);
988}
989
Werner Zehe57d4e42022-01-03 09:44:29 +0100990static int enable_flash_mcc(struct pci_dev *const dev, const char *const name)
991{
992 return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_ELKHART_LAKE);
993}
994
Nico Huber37509862019-01-18 14:23:02 +0100995static int enable_flash_apl(struct pci_dev *const dev, const char *const name)
996{
997 return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE);
David Hendricksa5216362017-08-08 20:02:22 -0700998}
999
Angel Pons4db0fdf2020-07-10 17:04:10 +02001000static int enable_flash_glk(struct pci_dev *const dev, const char *const name)
1001{
1002 return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_GEMINI_LAKE);
1003}
1004
Duncan Laurie4095ed72014-08-20 15:39:32 +00001005/* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley.
1006 * These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately.
1007 *
1008 * Differences include:
1009 * - RCBA at LPC config 0xF0 too but mapped range is only 4 B long instead of 16 kB.
1010 * - GCS at [RCRB] + 0 (instead of [RCRB] + 0x3410).
1011 * - TS (Top Swap) in GCS (instead of [RCRB] + 0x3414).
1012 * - SPIBAR (coined SBASE) at LPC config 0x54 (instead of [RCRB] + 0x3800).
1013 * - BIOS_CNTL (coined BCR) at [SPIBAR] + 0xFC (instead of LPC config 0xDC).
1014 */
1015static int enable_flash_silvermont(struct pci_dev *dev, const char *name)
1016{
1017 enum ich_chipset ich_generation = CHIPSET_BAYTRAIL;
1018
1019 /* Get physical address of Root Complex Register Block */
1020 uint32_t rcba = pci_read_long(dev, 0xf0) & 0xfffffc00;
1021 msg_pdbg("Root Complex Register Block address = 0x%x\n", rcba);
1022
1023 /* Handle GCS (in RCRB) */
1024 void *rcrb = physmap("BYT RCRB", rcba, 4);
Edward O'Callaghan2e3e1062020-12-02 13:17:46 +11001025 if (rcrb == ERROR_PTR)
1026 return ERROR_FATAL;
Nico Huber2e50cdc2018-09-23 20:20:26 +02001027 const enum chipbustype boot_buses = enable_flash_ich_report_gcs(dev, ich_generation, rcrb);
Duncan Laurie4095ed72014-08-20 15:39:32 +00001028 physunmap(rcrb, 4);
1029
1030 /* Handle fwh_idsel parameter */
1031 int ret_fwh = enable_flash_ich_fwh_decode(dev, ich_generation);
1032 if (ret_fwh == ERROR_FATAL)
1033 return ret_fwh;
1034
Nico Huber2e50cdc2018-09-23 20:20:26 +02001035 internal_buses_supported &= BUS_FWH;
Duncan Laurie4095ed72014-08-20 15:39:32 +00001036
1037 /* Get physical address of SPI Base Address and map it */
1038 uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00;
1039 msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase);
1040 void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */
Edward O'Callaghaneaf701d2020-10-15 19:19:05 +11001041 if (spibar == ERROR_PTR)
1042 return ERROR_FATAL;
Duncan Laurie4095ed72014-08-20 15:39:32 +00001043
1044 /* Enable Flash Writes.
1045 * Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C).
1046 */
1047 enable_flash_ich_bios_cntl_memmapped(ich_generation, spibar + 0xFC);
1048
Nico Huber560111e2017-04-26 12:27:17 +02001049 int ret_spi = ich_init_spi(spibar, ich_generation);
Duncan Laurie4095ed72014-08-20 15:39:32 +00001050 if (ret_spi == ERROR_FATAL)
1051 return ret_spi;
1052
Nico Huber2e50cdc2018-09-23 20:20:26 +02001053 if (((boot_buses & BUS_FWH) && ret_fwh) || ((boot_buses & BUS_SPI) && ret_spi))
Duncan Laurie4095ed72014-08-20 15:39:32 +00001054 return ERROR_NONFATAL;
1055
Nico Huber2e50cdc2018-09-23 20:20:26 +02001056 /* Suppress unknown laptop warning if we booted from SPI. */
1057 if (boot_buses & BUS_SPI)
Felix Singerd1ab7d22022-08-19 03:03:47 +02001058 laptop_ok = true;
Nico Huber2e50cdc2018-09-23 20:20:26 +02001059
Duncan Laurie4095ed72014-08-20 15:39:32 +00001060 return 0;
1061}
1062
Michael Karcher89bed6d2010-06-13 10:16:12 +00001063static int via_no_byte_merge(struct pci_dev *dev, const char *name)
1064{
1065 uint8_t val;
1066
1067 val = pci_read_byte(dev, 0x71);
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001068 if (val & 0x40) {
Michael Karcher89bed6d2010-06-13 10:16:12 +00001069 msg_pdbg("Disabling byte merging\n");
1070 val &= ~0x40;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001071 rpci_write_byte(dev, 0x71, val);
Michael Karcher89bed6d2010-06-13 10:16:12 +00001072 }
1073 return NOT_DONE_YET; /* need to find south bridge, too */
1074}
1075
Uwe Hermann372eeb52007-12-04 21:49:06 +00001076static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001077{
Ollie Lho184a4042005-11-26 21:55:36 +00001078 uint8_t val;
Ollie Lho761bf1b2004-03-20 16:46:10 +00001079
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001080 /* Enable ROM decode range (1MB) FFC00000 - FFFFFFFF. */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001081 rpci_write_byte(dev, 0x41, 0x7f);
Bari Ari9477c4e2008-04-29 13:46:38 +00001082
Uwe Hermannffec5f32007-08-23 16:08:21 +00001083 /* ROM write enable */
Ollie Lhocbbf1252004-03-17 22:22:08 +00001084 val = pci_read_byte(dev, 0x40);
1085 val |= 0x10;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001086 rpci_write_byte(dev, 0x40, val);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001087
1088 if (pci_read_byte(dev, 0x40) != val) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00001089 msg_pwarn("\nWarning: Failed to enable flash write on \"%s\"\n", name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001090 return -1;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001091 }
Luc Verhaegen6382b442007-03-02 22:16:38 +00001092
Helge Wagnerdd73d832012-08-24 23:03:46 +00001093 if (dev->device_id == 0x3227) { /* VT8237/VT8237R */
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001094 /* All memory cycles, not just ROM ones, go to LPC. */
1095 val = pci_read_byte(dev, 0x59);
1096 val &= ~0x80;
1097 rpci_write_byte(dev, 0x59, val);
Luc Verhaegen73d21192009-12-23 00:54:26 +00001098 }
1099
Uwe Hermanna7e05482007-05-09 10:17:44 +00001100 return 0;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001101}
1102
Helge Wagnerdd73d832012-08-24 23:03:46 +00001103static int enable_flash_vt_vx(struct pci_dev *dev, const char *name)
1104{
Edward O'Callaghan19ce50d2021-11-13 17:59:18 +11001105 struct pci_dev *south_north = pcidev_find(0x1106, 0xa353);
Helge Wagnerdd73d832012-08-24 23:03:46 +00001106 if (south_north == NULL) {
1107 msg_perr("Could not find South-North Module Interface Control device!\n");
1108 return ERROR_FATAL;
1109 }
1110
1111 msg_pdbg("Strapped to ");
1112 if ((pci_read_byte(south_north, 0x56) & 0x01) == 0) {
1113 msg_pdbg("LPC.\n");
1114 return enable_flash_vt823x(dev, name);
1115 }
1116 msg_pdbg("SPI.\n");
1117
1118 uint32_t mmio_base;
1119 void *mmio_base_physmapped;
1120 uint32_t spi_cntl;
1121 #define SPI_CNTL_LEN 0x08
1122 uint32_t spi0_mm_base = 0;
1123 switch(dev->device_id) {
1124 case 0x8353: /* VX800/VX820 */
1125 spi0_mm_base = pci_read_long(dev, 0xbc) << 8;
Lubomir Rinteld0803c82017-10-30 07:57:53 +01001126 if (spi0_mm_base == 0x0) {
1127 msg_pdbg ("MMIO not enabled!\n");
1128 return ERROR_FATAL;
1129 }
Helge Wagnerdd73d832012-08-24 23:03:46 +00001130 break;
1131 case 0x8409: /* VX855/VX875 */
1132 case 0x8410: /* VX900 */
1133 mmio_base = pci_read_long(dev, 0xbc) << 8;
Lubomir Rinteld0803c82017-10-30 07:57:53 +01001134 if (mmio_base == 0x0) {
1135 msg_pdbg ("MMIO not enabled!\n");
1136 return ERROR_FATAL;
1137 }
Helge Wagnerdd73d832012-08-24 23:03:46 +00001138 mmio_base_physmapped = physmap("VIA VX MMIO register", mmio_base, SPI_CNTL_LEN);
Stefan Tauner7fb5aa02013-08-14 15:48:44 +00001139 if (mmio_base_physmapped == ERROR_PTR)
Helge Wagnerdd73d832012-08-24 23:03:46 +00001140 return ERROR_FATAL;
Helge Wagnerdd73d832012-08-24 23:03:46 +00001141
1142 /* Offset 0 - Bit 0 holds SPI Bus0 Enable Bit. */
1143 spi_cntl = mmio_readl(mmio_base_physmapped) + 0x00;
1144 if ((spi_cntl & 0x01) == 0) {
1145 msg_pdbg ("SPI Bus0 disabled!\n");
1146 physunmap(mmio_base_physmapped, SPI_CNTL_LEN);
1147 return ERROR_FATAL;
1148 }
1149 /* Offset 1-3 has SPI Bus Memory Map Base Address: */
1150 spi0_mm_base = spi_cntl & 0xFFFFFF00;
1151
1152 /* Offset 4 - Bit 0 holds SPI Bus1 Enable Bit. */
1153 spi_cntl = mmio_readl(mmio_base_physmapped) + 0x04;
1154 if ((spi_cntl & 0x01) == 1)
1155 msg_pdbg2("SPI Bus1 is enabled too.\n");
1156
1157 physunmap(mmio_base_physmapped, SPI_CNTL_LEN);
1158 break;
1159 default:
1160 msg_perr("%s: Unsupported chipset %x:%x!\n", __func__, dev->vendor_id, dev->device_id);
1161 return ERROR_FATAL;
1162 }
1163
Nico Huber560111e2017-04-26 12:27:17 +02001164 return via_init_spi(spi0_mm_base);
Helge Wagnerdd73d832012-08-24 23:03:46 +00001165}
1166
1167static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
1168{
Nico Huber560111e2017-04-26 12:27:17 +02001169 return via_init_spi(pci_read_long(dev, 0xbc) << 8);
Helge Wagnerdd73d832012-08-24 23:03:46 +00001170}
1171
Uwe Hermann372eeb52007-12-04 21:49:06 +00001172static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001173{
Uwe Hermannf4a673b2007-06-06 21:35:45 +00001174 uint8_t reg8;
Ollie Lho761bf1b2004-03-20 16:46:10 +00001175
Uwe Hermann394131e2008-10-18 21:14:13 +00001176#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
1177#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00001178#define CS5530_RESET_CONTROL_REG 0x44 /* F0 index 0x44 */
1179#define CS5530_USB_SHADOW_REG 0x43 /* F0 index 0x43 */
Ollie Lhocbbf1252004-03-17 22:22:08 +00001180
Uwe Hermann394131e2008-10-18 21:14:13 +00001181#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
1182#define ROM_WRITE_ENABLE (1 << 1)
1183#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
1184#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00001185#define CS5530_ISA_MASTER (1 << 7)
1186#define CS5530_ENABLE_SA2320 (1 << 2)
1187#define CS5530_ENABLE_SA20 (1 << 6)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001188
Nico Huber2e50cdc2018-09-23 20:20:26 +02001189 internal_buses_supported &= BUS_PARALLEL;
Stefan Taunerc0aaf952011-05-19 02:58:17 +00001190 /* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and
1191 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB.
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00001192 * FIXME: Should we really touch the low mapping below 1 MB? Flashrom
1193 * ignores that region completely.
Uwe Hermannf4a673b2007-06-06 21:35:45 +00001194 * Make the configured ROM areas writable.
1195 */
1196 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
1197 reg8 |= LOWER_ROM_ADDRESS_RANGE;
1198 reg8 |= UPPER_ROM_ADDRESS_RANGE;
1199 reg8 |= ROM_WRITE_ENABLE;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001200 rpci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001201
Uwe Hermannf4a673b2007-06-06 21:35:45 +00001202 /* Set positive decode on ROM. */
1203 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
1204 reg8 |= BIOS_ROM_POSITIVE_DECODE;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001205 rpci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001206
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00001207 reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG);
1208 if (reg8 & CS5530_ISA_MASTER) {
1209 /* We have A0-A23 available. */
1210 max_rom_decode.parallel = 16 * 1024 * 1024;
1211 } else {
1212 reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG);
1213 if (reg8 & CS5530_ENABLE_SA2320) {
1214 /* We have A0-19, A20-A23 available. */
1215 max_rom_decode.parallel = 16 * 1024 * 1024;
1216 } else if (reg8 & CS5530_ENABLE_SA20) {
1217 /* We have A0-19, A20 available. */
1218 max_rom_decode.parallel = 2 * 1024 * 1024;
1219 } else {
1220 /* A20 and above are not active. */
1221 max_rom_decode.parallel = 1024 * 1024;
1222 }
1223 }
1224
Ollie Lhocbbf1252004-03-17 22:22:08 +00001225 return 0;
1226}
1227
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001228/*
Mart Raudseppe1344da2008-02-08 10:10:57 +00001229 * Geode systems write protect the BIOS via RCONFs (cache settings similar
Elyes HAOUAS124ef382018-03-27 12:15:09 +02001230 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
Mart Raudseppe1344da2008-02-08 10:10:57 +00001231 *
1232 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
1233 * To enable write to NOR Boot flash for the benefit of systems that have such
1234 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
Mart Raudseppe1344da2008-02-08 10:10:57 +00001235 */
Uwe Hermann372eeb52007-12-04 21:49:06 +00001236static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
Lane Brooksd54958a2007-11-13 16:45:22 +00001237{
Uwe Hermann394131e2008-10-18 21:14:13 +00001238#define MSR_RCONF_DEFAULT 0x1808
1239#define MSR_NORF_CTL 0x51400018
Mart Raudsepp0514a5f2008-02-08 09:59:58 +00001240
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001241 msr_t msr;
Lane Brooksd54958a2007-11-13 16:45:22 +00001242
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001243 /* Geode only has a single core */
Thomas Heijligenf8d9a272022-03-16 09:19:19 +01001244 if (msr_setup(0))
Lane Brooksd54958a2007-11-13 16:45:22 +00001245 return -1;
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001246
Thomas Heijligenf8d9a272022-03-16 09:19:19 +01001247 msr = msr_read(MSR_RCONF_DEFAULT);
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001248 if ((msr.hi >> 24) != 0x22) {
1249 msr.hi &= 0xfbffffff;
Thomas Heijligenf8d9a272022-03-16 09:19:19 +01001250 msr_write(MSR_RCONF_DEFAULT, msr);
Lane Brooksd54958a2007-11-13 16:45:22 +00001251 }
Mart Raudseppe1344da2008-02-08 10:10:57 +00001252
Thomas Heijligenf8d9a272022-03-16 09:19:19 +01001253 msr = msr_read(MSR_NORF_CTL);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +00001254 /* Raise WE_CS3 bit. */
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001255 msr.lo |= 0x08;
Thomas Heijligenf8d9a272022-03-16 09:19:19 +01001256 msr_write(MSR_NORF_CTL, msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +00001257
Thomas Heijligenf8d9a272022-03-16 09:19:19 +01001258 msr_cleanup();
Mart Raudsepp0514a5f2008-02-08 09:59:58 +00001259
Uwe Hermann394131e2008-10-18 21:14:13 +00001260#undef MSR_RCONF_DEFAULT
1261#undef MSR_NORF_CTL
Lane Brooksd54958a2007-11-13 16:45:22 +00001262 return 0;
1263}
1264
Uwe Hermann372eeb52007-12-04 21:49:06 +00001265static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001266{
Stefan Taunere34e3e82013-01-01 00:06:51 +00001267 #define SC_REG 0x52
Ollie Lho184a4042005-11-26 21:55:36 +00001268 uint8_t new;
Ollie Lho761bf1b2004-03-20 16:46:10 +00001269
Stefan Taunere34e3e82013-01-01 00:06:51 +00001270 rpci_write_byte(dev, SC_REG, 0xee);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001271
Stefan Taunere34e3e82013-01-01 00:06:51 +00001272 new = pci_read_byte(dev, SC_REG);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001273
Stefan Taunere34e3e82013-01-01 00:06:51 +00001274 if (new != 0xee) { /* FIXME: share this with other code? */
1275 msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", SC_REG, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001276 return -1;
1277 }
Uwe Hermannffec5f32007-08-23 16:08:21 +00001278
Ollie Lhocbbf1252004-03-17 22:22:08 +00001279 return 0;
1280}
1281
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001282/* Works for AMD-768, AMD-8111, VIA VT82C586A/B, VIA VT82C596, VIA VT82C686A/B.
1283 *
1284 * ROM decode control register matrix
Elyes HAOUASac01baa2018-05-28 16:52:21 +02001285 * AMD-768 AMD-8111 VT82C586A/B VT82C596 VT82C686A/B
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001286 * 7 FFC0_0000h–FFFF_FFFFh <- FFFE0000h-FFFEFFFFh <- <-
1287 * 6 FFB0_0000h–FFBF_FFFFh <- FFF80000h-FFFDFFFFh <- <-
1288 * 5 00E8... <- <- FFF00000h-FFF7FFFFh <-
1289 */
1290static int enable_flash_amd_via(struct pci_dev *dev, const char *name, uint8_t decode_val)
Ollie Lho761bf1b2004-03-20 16:46:10 +00001291{
Stefan Taunere34e3e82013-01-01 00:06:51 +00001292 #define AMD_MAPREG 0x43
1293 #define AMD_ENREG 0x40
Ollie Lho184a4042005-11-26 21:55:36 +00001294 uint8_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001295
Stefan Taunere34e3e82013-01-01 00:06:51 +00001296 old = pci_read_byte(dev, AMD_MAPREG);
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001297 new = old | decode_val;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001298 if (new != old) {
Stefan Taunere34e3e82013-01-01 00:06:51 +00001299 rpci_write_byte(dev, AMD_MAPREG, new);
1300 if (pci_read_byte(dev, AMD_MAPREG) != new) {
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001301 msg_pwarn("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
Stefan Taunere34e3e82013-01-01 00:06:51 +00001302 AMD_MAPREG, new, name);
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001303 } else
1304 msg_pdbg("Changed ROM decode range to 0x%02x successfully.\n", new);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001305 }
1306
Uwe Hermann190f8492008-10-25 18:03:50 +00001307 /* Enable 'ROM write' bit. */
Stefan Taunere34e3e82013-01-01 00:06:51 +00001308 old = pci_read_byte(dev, AMD_ENREG);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001309 new = old | 0x01;
1310 if (new == old)
1311 return 0;
Stefan Taunere34e3e82013-01-01 00:06:51 +00001312 rpci_write_byte(dev, AMD_ENREG, new);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001313
Stefan Taunere34e3e82013-01-01 00:06:51 +00001314 if (pci_read_byte(dev, AMD_ENREG) != new) {
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001315 msg_pwarn("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
Stefan Taunere34e3e82013-01-01 00:06:51 +00001316 AMD_ENREG, new, name);
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001317 return ERROR_NONFATAL;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001318 }
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001319 msg_pdbg2("Set ROM enable bit successfully.\n");
Uwe Hermannffec5f32007-08-23 16:08:21 +00001320
Ollie Lhocbbf1252004-03-17 22:22:08 +00001321 return 0;
1322}
1323
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001324static int enable_flash_amd_768_8111(struct pci_dev *dev, const char *name)
1325{
1326 /* Enable decoding of 0xFFB00000 to 0xFFFFFFFF (5 MB). */
1327 max_rom_decode.lpc = 5 * 1024 * 1024;
1328 return enable_flash_amd_via(dev, name, 0xC0);
1329}
1330
1331static int enable_flash_vt82c586(struct pci_dev *dev, const char *name)
1332{
1333 /* Enable decoding of 0xFFF80000 to 0xFFFFFFFF. (512 kB) */
1334 max_rom_decode.parallel = 512 * 1024;
1335 return enable_flash_amd_via(dev, name, 0xC0);
1336}
1337
1338/* Works for VT82C686A/B too. */
1339static int enable_flash_vt82c596(struct pci_dev *dev, const char *name)
1340{
Stefan Taunerc2eec2c2014-05-03 21:33:01 +00001341 /* Enable decoding of 0xFFF00000 to 0xFFFFFFFF. (1 MB) */
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001342 max_rom_decode.parallel = 1024 * 1024;
1343 return enable_flash_amd_via(dev, name, 0xE0);
1344}
1345
Marc Jones3af487d2008-10-15 17:50:29 +00001346static int enable_flash_sb600(struct pci_dev *dev, const char *name)
1347{
Michael Karcherb05b9e12010-07-22 18:04:19 +00001348 uint32_t prot;
Marc Jones3af487d2008-10-15 17:50:29 +00001349 uint8_t reg;
Michael Karcherb05b9e12010-07-22 18:04:19 +00001350 int ret;
Marc Jones3af487d2008-10-15 17:50:29 +00001351
Jason Wanga3f04be2008-11-28 21:36:51 +00001352 /* Clear ROM protect 0-3. */
1353 for (reg = 0x50; reg < 0x60; reg += 4) {
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001354 prot = pci_read_long(dev, reg);
1355 /* No protection flags for this region?*/
1356 if ((prot & 0x3) == 0)
1357 continue;
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001358 msg_pdbg("Chipset %s%sprotected flash from 0x%08x to 0x%08x, unlocking...",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001359 (prot & 0x2) ? "read " : "",
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001360 (prot & 0x1) ? "write " : "",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001361 (prot & 0xfffff800),
1362 (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001363 prot &= 0xfffffffc;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001364 rpci_write_byte(dev, reg, prot);
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001365 prot = pci_read_long(dev, reg);
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001366 if ((prot & 0x3) != 0) {
1367 msg_perr("Disabling %s%sprotection of flash addresses from 0x%08x to 0x%08x failed.\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001368 (prot & 0x2) ? "read " : "",
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001369 (prot & 0x1) ? "write " : "",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001370 (prot & 0xfffff800),
1371 (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001372 continue;
1373 }
1374 msg_pdbg("done.\n");
Jason Wanga3f04be2008-11-28 21:36:51 +00001375 }
1376
Nico Huber2e50cdc2018-09-23 20:20:26 +02001377 internal_buses_supported &= BUS_LPC | BUS_FWH;
Michael Karcherb05b9e12010-07-22 18:04:19 +00001378
1379 ret = sb600_probe_spi(dev);
Jason Wanga3f04be2008-11-28 21:36:51 +00001380
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001381 /* Read ROM strap override register. */
1382 OUTB(0x8f, 0xcd6);
1383 reg = INB(0xcd7);
1384 reg &= 0x0e;
Sean Nelson316a29f2010-05-07 20:09:04 +00001385 msg_pdbg("ROM strap override is %sactive", (reg & 0x02) ? "" : "not ");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001386 if (reg & 0x02) {
1387 switch ((reg & 0x0c) >> 2) {
1388 case 0x00:
Sean Nelson316a29f2010-05-07 20:09:04 +00001389 msg_pdbg(": LPC");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001390 break;
1391 case 0x01:
Sean Nelson316a29f2010-05-07 20:09:04 +00001392 msg_pdbg(": PCI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001393 break;
1394 case 0x02:
Sean Nelson316a29f2010-05-07 20:09:04 +00001395 msg_pdbg(": FWH");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001396 break;
1397 case 0x03:
Sean Nelson316a29f2010-05-07 20:09:04 +00001398 msg_pdbg(": SPI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001399 break;
1400 }
1401 }
Sean Nelson316a29f2010-05-07 20:09:04 +00001402 msg_pdbg("\n");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001403
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001404 /* Force enable SPI ROM in SB600 PM register.
1405 * If we enable SPI ROM here, we have to disable it after we leave.
Zheng Bao284a6002009-05-04 22:33:50 +00001406 * But how can we know which ROM we are going to handle? So we have
1407 * to trade off. We only access LPC ROM if we boot via LPC ROM. And
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001408 * only SPI ROM if we boot via SPI ROM. If you want to access SPI on
1409 * boards with LPC straps, you have to use the code below.
Zheng Bao284a6002009-05-04 22:33:50 +00001410 */
1411 /*
Jason Wanga3f04be2008-11-28 21:36:51 +00001412 OUTB(0x8f, 0xcd6);
1413 OUTB(0x0e, 0xcd7);
Zheng Bao284a6002009-05-04 22:33:50 +00001414 */
Marc Jones3af487d2008-10-15 17:50:29 +00001415
Michael Karcherb05b9e12010-07-22 18:04:19 +00001416 return ret;
Marc Jones3af487d2008-10-15 17:50:29 +00001417}
1418
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001419/* sets bit 0 in 0x6d */
1420static int enable_flash_nvidia_common(struct pci_dev *dev, const char *name)
1421{
1422 uint8_t old, new;
1423
1424 old = pci_read_byte(dev, 0x6d);
1425 new = old | 0x01;
1426 if (new == old)
1427 return 0;
1428
1429 rpci_write_byte(dev, 0x6d, new);
1430 if (pci_read_byte(dev, 0x6d) != new) {
1431 msg_pinfo("Setting register 0x6d to 0x%02x on %s failed.\n", new, name);
1432 return 1;
1433 }
1434 return 0;
1435}
1436
Luc Verhaegen90e8e612009-05-26 09:48:28 +00001437static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name)
1438{
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001439 rpci_write_byte(dev, 0x92, 0);
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001440 if (enable_flash_nvidia_common(dev, name))
1441 return ERROR_NONFATAL;
1442 else
1443 return 0;
Luc Verhaegen90e8e612009-05-26 09:48:28 +00001444}
1445
Uwe Hermann372eeb52007-12-04 21:49:06 +00001446static int enable_flash_ck804(struct pci_dev *dev, const char *name)
Yinghai Lu952dfce2005-07-06 17:13:46 +00001447{
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001448 uint32_t segctrl;
1449 uint8_t reg, old, new;
1450 unsigned int err = 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +00001451
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001452 /* 0x8A is special: it is a single byte and only one nibble is touched. */
1453 reg = 0x8A;
1454 segctrl = pci_read_byte(dev, reg);
1455 if ((segctrl & 0x3) != 0x0) {
1456 if ((segctrl & 0xC) != 0x0) {
1457 msg_pinfo("Can not unlock existing protection in register 0x%02x.\n", reg);
1458 err++;
1459 } else {
1460 msg_pdbg("Unlocking protection in register 0x%02x... ", reg);
1461 rpci_write_byte(dev, reg, segctrl & 0xF0);
1462
1463 segctrl = pci_read_byte(dev, reg);
1464 if ((segctrl & 0x3) != 0x0) {
1465 msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%x).\n",
1466 reg, segctrl);
1467 err++;
1468 } else
1469 msg_pdbg("OK\n");
1470 }
Jonathan Kollasch9ce498e2011-08-06 12:45:21 +00001471 }
1472
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001473 for (reg = 0x8C; reg <= 0x94; reg += 4) {
1474 segctrl = pci_read_long(dev, reg);
1475 if ((segctrl & 0x33333333) == 0x00000000) {
1476 /* reads and writes are unlocked */
1477 continue;
1478 }
1479 if ((segctrl & 0xCCCCCCCC) != 0x00000000) {
1480 msg_pinfo("Can not unlock existing protection in register 0x%02x.\n", reg);
1481 err++;
1482 continue;
1483 }
1484 msg_pdbg("Unlocking protection in register 0x%02x... ", reg);
1485 rpci_write_long(dev, reg, 0x00000000);
1486
1487 segctrl = pci_read_long(dev, reg);
1488 if ((segctrl & 0x33333333) != 0x00000000) {
1489 msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%08x).\n",
1490 reg, segctrl);
1491 err++;
1492 } else
1493 msg_pdbg("OK\n");
1494 }
1495
1496 if (err > 0) {
1497 msg_pinfo("%d locks could not be disabled, disabling writes (reads may also fail).\n", err);
Felix Singer980d6b82022-08-19 02:48:15 +02001498 programmer_may_write = false;
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001499 }
1500
1501 reg = 0x88;
1502 old = pci_read_byte(dev, reg);
1503 new = old | 0xC0;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001504 if (new != old) {
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001505 rpci_write_byte(dev, reg, new);
Stefan Taunere34e3e82013-01-01 00:06:51 +00001506 if (pci_read_byte(dev, reg) != new) { /* FIXME: share this with other code? */
1507 msg_pinfo("Setting register 0x%02x to 0x%02x on %s failed.\n", reg, new, name);
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001508 err++;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001509 }
1510 }
Yinghai Lu952dfce2005-07-06 17:13:46 +00001511
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001512 if (enable_flash_nvidia_common(dev, name))
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001513 err++;
1514
1515 if (err > 0)
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001516 return ERROR_NONFATAL;
1517 else
Uwe Hermanna7e05482007-05-09 10:17:44 +00001518 return 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +00001519}
1520
Joshua Roys85835d82010-09-15 14:47:56 +00001521static int enable_flash_osb4(struct pci_dev *dev, const char *name)
1522{
1523 uint8_t tmp;
1524
Nico Huber2e50cdc2018-09-23 20:20:26 +02001525 internal_buses_supported &= BUS_PARALLEL;
Joshua Roys85835d82010-09-15 14:47:56 +00001526
1527 tmp = INB(0xc06);
1528 tmp |= 0x1;
1529 OUTB(tmp, 0xc06);
1530
1531 tmp = INB(0xc6f);
1532 tmp |= 0x40;
1533 OUTB(tmp, 0xc6f);
1534
1535 return 0;
1536}
1537
Uwe Hermann372eeb52007-12-04 21:49:06 +00001538/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
1539static int enable_flash_sb400(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +00001540{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001541 uint8_t tmp;
Stefan Reinauer86de2832006-03-31 11:26:55 +00001542 struct pci_dev *smbusdev;
1543
Uwe Hermann372eeb52007-12-04 21:49:06 +00001544 /* Look for the SMBus device. */
Edward O'Callaghan19ce50d2021-11-13 17:59:18 +11001545 smbusdev = pcidev_find(0x1002, 0x4372);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001546
Uwe Hermanna7e05482007-05-09 10:17:44 +00001547 if (!smbusdev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001548 msg_perr("ERROR: SMBus device not found. Aborting.\n");
Tadas Slotkus0e3f1cf2011-09-06 18:49:31 +00001549 return ERROR_FATAL;
Stefan Reinauer86de2832006-03-31 11:26:55 +00001550 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001551
Uwe Hermann372eeb52007-12-04 21:49:06 +00001552 /* Enable some SMBus stuff. */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001553 tmp = pci_read_byte(smbusdev, 0x79);
1554 tmp |= 0x01;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001555 rpci_write_byte(smbusdev, 0x79, tmp);
Stefan Reinauer86de2832006-03-31 11:26:55 +00001556
Uwe Hermann372eeb52007-12-04 21:49:06 +00001557 /* Change southbridge. */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001558 tmp = pci_read_byte(dev, 0x48);
1559 tmp |= 0x21;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001560 rpci_write_byte(dev, 0x48, tmp);
Stefan Reinauer86de2832006-03-31 11:26:55 +00001561
Uwe Hermann372eeb52007-12-04 21:49:06 +00001562 /* Now become a bit silly. */
Andriy Gapon65c1b862008-05-22 13:22:45 +00001563 tmp = INB(0xc6f);
1564 OUTB(tmp, 0xeb);
1565 OUTB(tmp, 0xeb);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001566 tmp |= 0x40;
Andriy Gapon65c1b862008-05-22 13:22:45 +00001567 OUTB(tmp, 0xc6f);
1568 OUTB(tmp, 0xeb);
1569 OUTB(tmp, 0xeb);
Stefan Reinauer86de2832006-03-31 11:26:55 +00001570
1571 return 0;
1572}
1573
Uwe Hermann372eeb52007-12-04 21:49:06 +00001574static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
Yinghai Luca782972007-01-22 20:21:17 +00001575{
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001576 uint8_t val;
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001577 uint16_t wordval;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001578
Uwe Hermann372eeb52007-12-04 21:49:06 +00001579 /* Set the 0-16 MB enable bits. */
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001580 val = pci_read_byte(dev, 0x88);
1581 val |= 0xff; /* 256K */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001582 rpci_write_byte(dev, 0x88, val);
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001583 val = pci_read_byte(dev, 0x8c);
1584 val |= 0xff; /* 1M */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001585 rpci_write_byte(dev, 0x8c, val);
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001586 wordval = pci_read_word(dev, 0x90);
1587 wordval |= 0x7fff; /* 16M */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001588 rpci_write_word(dev, 0x90, wordval);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001589
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001590 if (enable_flash_nvidia_common(dev, name))
1591 return ERROR_NONFATAL;
1592 else
Uwe Hermanna7e05482007-05-09 10:17:44 +00001593 return 0;
Yinghai Luca782972007-01-22 20:21:17 +00001594}
1595
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001596/*
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001597 * The MCP6x/MCP7x code is based on cleanroom reverse engineering.
1598 * It is assumed that LPC chips need the MCP55 code and SPI chips need the
1599 * code provided in enable_flash_mcp6x_7x_common.
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001600 */
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001601static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001602{
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001603 int ret = 0, want_spi = 0;
Michael Karchercfa674f2010-02-25 11:38:23 +00001604 uint8_t val;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001605
1606 /* dev is the ISA bridge. No idea what the stuff below does. */
Michael Karchercfa674f2010-02-25 11:38:23 +00001607 val = pci_read_byte(dev, 0x8a);
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001608 msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 "
Michael Karchercfa674f2010-02-25 11:38:23 +00001609 "is %i\n", val, (val >> 6) & 0x1, (val >> 5) & 0x1);
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001610
Michael Karchercfa674f2010-02-25 11:38:23 +00001611 switch ((val >> 5) & 0x3) {
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001612 case 0x0:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001613 ret = enable_flash_mcp55(dev, name);
Nico Huber2e50cdc2018-09-23 20:20:26 +02001614 internal_buses_supported &= BUS_LPC;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001615 msg_pdbg("Flash bus type is LPC\n");
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001616 break;
1617 case 0x2:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001618 want_spi = 1;
1619 /* SPI is added in mcp6x_spi_init if it works.
1620 * Do we really want to disable LPC in this case?
1621 */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001622 internal_buses_supported = BUS_NONE;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001623 msg_pdbg("Flash bus type is SPI\n");
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001624 break;
1625 default:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001626 /* Should not happen. */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001627 internal_buses_supported = BUS_NONE;
Stefan Tauner7ba3d6c2014-06-12 21:07:03 +00001628 msg_pwarn("Flash bus type is unknown (none)\n");
Elyes HAOUASac01baa2018-05-28 16:52:21 +02001629 msg_pinfo("Please send the log files created by \"flashrom -p internal -o logfile\" to\n"
Nico Huberac90af62022-12-18 00:22:47 +00001630 "flashrom-stable@flashrom.org with \"your board name: flashrom -V\" as the subject\n"
1631 "to help us finish support for your chipset. Thanks.\n");
Stefan Tauner7ba3d6c2014-06-12 21:07:03 +00001632 return ERROR_NONFATAL;
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001633 }
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001634
1635 /* Force enable SPI and disable LPC? Not a good idea. */
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001636#if 0
Michael Karchercfa674f2010-02-25 11:38:23 +00001637 val |= (1 << 6);
1638 val &= ~(1 << 5);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001639 rpci_write_byte(dev, 0x8a, val);
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001640#endif
1641
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001642 if (mcp6x_spi_init(want_spi))
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001643 ret = 1;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001644
Nico Huber2e50cdc2018-09-23 20:20:26 +02001645 /* Suppress unknown laptop warning if we booted from SPI. */
1646 if (!ret && want_spi)
Felix Singerd1ab7d22022-08-19 03:03:47 +02001647 laptop_ok = true;
Nico Huber2e50cdc2018-09-23 20:20:26 +02001648
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001649 return ret;
1650}
1651
Uwe Hermann372eeb52007-12-04 21:49:06 +00001652static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001653{
Michael Karchercfa674f2010-02-25 11:38:23 +00001654 uint8_t val;
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001655
Uwe Hermanne823ee02007-06-05 15:02:18 +00001656 /* Set the 4MB enable bit. */
Michael Karchercfa674f2010-02-25 11:38:23 +00001657 val = pci_read_byte(dev, 0x41);
1658 val |= 0x0e;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001659 rpci_write_byte(dev, 0x41, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001660
Michael Karchercfa674f2010-02-25 11:38:23 +00001661 val = pci_read_byte(dev, 0x43);
1662 val |= (1 << 4);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001663 rpci_write_byte(dev, 0x43, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001664
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001665 return 0;
1666}
1667
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001668/*
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001669 * Usually on the x86 architectures (and on other PC-like platforms like some
1670 * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
1671 * Elan SC520 only a small piece of the system flash is mapped there, but the
1672 * complete flash is mapped somewhere below 1G. The position can be determined
1673 * by the BOOTCS PAR register.
1674 */
1675static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
1676{
1677 int i, bootcs_found = 0;
1678 uint32_t parx = 0;
1679 void *mmcr;
1680
1681 /* 1. Map MMCR */
Stefan Reinauer0593f212009-01-26 01:10:48 +00001682 mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize());
Niklas Söderlund5d307202013-09-14 09:02:27 +00001683 if (mmcr == ERROR_PTR)
1684 return ERROR_FATAL;
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001685
1686 /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for
1687 * BOOTCS region (PARx[31:29] = 100b)e
1688 */
1689 for (i = 0x88; i <= 0xc4; i += 4) {
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +00001690 parx = mmio_readl(mmcr + i);
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001691 if ((parx >> 29) == 4) {
1692 bootcs_found = 1;
1693 break; /* BOOTCS found */
1694 }
1695 }
1696
1697 /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0]
1698 * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0]
1699 */
1700 if (bootcs_found) {
1701 if (parx & (1 << 25)) {
1702 parx &= (1 << 14) - 1; /* Mask [13:0] */
1703 flashbase = parx << 16;
1704 } else {
1705 parx &= (1 << 18) - 1; /* Mask [17:0] */
1706 flashbase = parx << 12;
1707 }
1708 } else {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001709 msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. "
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001710 "Assuming flash at 4G.\n");
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001711 }
1712
1713 /* 4. Clean up */
Carl-Daniel Hailfingerbe726812009-08-09 12:44:08 +00001714 physunmap(mmcr, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001715 return 0;
1716}
1717
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001718#endif
1719
Nico Huber2e50cdc2018-09-23 20:20:26 +02001720#define B_P (BUS_PARALLEL)
1721#define B_PFL (BUS_NONSPI)
1722#define B_PFLS (BUS_NONSPI | BUS_SPI)
1723#define B_FL (BUS_FWH | BUS_LPC)
1724#define B_FLS (BUS_FWH | BUS_LPC | BUS_SPI)
1725#define B_FS (BUS_FWH | BUS_SPI)
1726#define B_L (BUS_LPC)
1727#define B_LS (BUS_LPC | BUS_SPI)
1728#define B_S (BUS_SPI)
1729
Idwer Vollering326a0602011-06-18 18:45:41 +00001730/* Please keep this list numerically sorted by vendor/device ID. */
Uwe Hermann05fab752009-05-16 23:42:17 +00001731const struct penable chipset_enables[] = {
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001732#if defined(__i386__) || defined(__x86_64__)
Nico Huber2e50cdc2018-09-23 20:20:26 +02001733 {0x1002, 0x4377, B_PFL, OK, "ATI", "SB400", enable_flash_sb400},
1734 {0x1002, 0x438d, B_FLS, OK, "AMD", "SB600", enable_flash_sb600},
1735 {0x1002, 0x439d, B_FLS, OK, "AMD", "SB7x0/SB8x0/SB9x0", enable_flash_sb600},
1736 {0x100b, 0x0510, B_PFL, NT, "AMD", "SC1100", enable_flash_sc1100},
1737 {0x1022, 0x2080, B_PFL, OK, "AMD", "CS5536", enable_flash_cs5536},
1738 {0x1022, 0x2090, B_PFL, OK, "AMD", "CS5536", enable_flash_cs5536},
1739 {0x1022, 0x3000, B_PFL, OK, "AMD", "Elan SC520", get_flashbase_sc520},
1740 {0x1022, 0x7440, B_PFL, OK, "AMD", "AMD-768", enable_flash_amd_768_8111},
1741 {0x1022, 0x7468, B_PFL, OK, "AMD", "AMD-8111", enable_flash_amd_768_8111},
1742 {0x1022, 0x780e, B_FLS, OK, "AMD", "FCH", enable_flash_sb600},
1743 {0x1022, 0x790e, B_FLS, OK, "AMD", "FP4", enable_flash_sb600},
1744 {0x1039, 0x0406, B_PFL, NT, "SiS", "501/5101/5501", enable_flash_sis501},
1745 {0x1039, 0x0496, B_PFL, NT, "SiS", "85C496+497", enable_flash_sis85c496},
1746 {0x1039, 0x0530, B_PFL, OK, "SiS", "530", enable_flash_sis530},
1747 {0x1039, 0x0540, B_PFL, NT, "SiS", "540", enable_flash_sis540},
1748 {0x1039, 0x0620, B_PFL, NT, "SiS", "620", enable_flash_sis530},
1749 {0x1039, 0x0630, B_PFL, OK, "SiS", "630", enable_flash_sis540},
1750 {0x1039, 0x0635, B_PFL, NT, "SiS", "635", enable_flash_sis540},
1751 {0x1039, 0x0640, B_PFL, NT, "SiS", "640", enable_flash_sis540},
1752 {0x1039, 0x0645, B_PFL, NT, "SiS", "645", enable_flash_sis540},
1753 {0x1039, 0x0646, B_PFL, OK, "SiS", "645DX", enable_flash_sis540},
1754 {0x1039, 0x0648, B_PFL, OK, "SiS", "648", enable_flash_sis540},
1755 {0x1039, 0x0650, B_PFL, OK, "SiS", "650", enable_flash_sis540},
1756 {0x1039, 0x0651, B_PFL, OK, "SiS", "651", enable_flash_sis540},
1757 {0x1039, 0x0655, B_PFL, NT, "SiS", "655", enable_flash_sis540},
1758 {0x1039, 0x0661, B_PFL, OK, "SiS", "661", enable_flash_sis540},
1759 {0x1039, 0x0730, B_PFL, OK, "SiS", "730", enable_flash_sis540},
1760 {0x1039, 0x0733, B_PFL, NT, "SiS", "733", enable_flash_sis540},
1761 {0x1039, 0x0735, B_PFL, OK, "SiS", "735", enable_flash_sis540},
1762 {0x1039, 0x0740, B_PFL, NT, "SiS", "740", enable_flash_sis540},
1763 {0x1039, 0x0741, B_PFL, OK, "SiS", "741", enable_flash_sis540},
1764 {0x1039, 0x0745, B_PFL, OK, "SiS", "745", enable_flash_sis540},
1765 {0x1039, 0x0746, B_PFL, NT, "SiS", "746", enable_flash_sis540},
1766 {0x1039, 0x0748, B_PFL, NT, "SiS", "748", enable_flash_sis540},
1767 {0x1039, 0x0755, B_PFL, OK, "SiS", "755", enable_flash_sis540},
1768 {0x1039, 0x5511, B_PFL, NT, "SiS", "5511", enable_flash_sis5511},
1769 {0x1039, 0x5571, B_PFL, NT, "SiS", "5571", enable_flash_sis530},
1770 {0x1039, 0x5591, B_PFL, NT, "SiS", "5591/5592", enable_flash_sis530},
1771 {0x1039, 0x5596, B_PFL, NT, "SiS", "5596", enable_flash_sis5511},
1772 {0x1039, 0x5597, B_PFL, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530},
1773 {0x1039, 0x5600, B_PFL, NT, "SiS", "600", enable_flash_sis530},
1774 {0x1078, 0x0100, B_P, OK, "AMD", "CS5530(A)", enable_flash_cs5530},
1775 {0x10b9, 0x1533, B_PFL, OK, "ALi", "M1533", enable_flash_ali_m1533},
1776 {0x10de, 0x0030, B_PFL, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2},
1777 {0x10de, 0x0050, B_PFL, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */
1778 {0x10de, 0x0051, B_PFL, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */
1779 {0x10de, 0x0060, B_PFL, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2},
1780 {0x10de, 0x00e0, B_PFL, OK, "NVIDIA", "NForce3", enable_flash_nvidia_nforce2},
Uwe Hermanneac10162008-03-13 18:52:51 +00001781 /* Slave, should not be here, to fix known bug for A01. */
Nico Huber2e50cdc2018-09-23 20:20:26 +02001782 {0x10de, 0x00d3, B_PFL, OK, "NVIDIA", "CK804", enable_flash_ck804},
1783 {0x10de, 0x0260, B_PFL, OK, "NVIDIA", "MCP51", enable_flash_ck804},
1784 {0x10de, 0x0261, B_PFL, OK, "NVIDIA", "MCP51", enable_flash_ck804},
1785 {0x10de, 0x0262, B_PFL, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1786 {0x10de, 0x0263, B_PFL, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1787 {0x10de, 0x0360, B_L, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/
Carl-Daniel Hailfinger33d7b6a2010-05-22 07:27:16 +00001788 /* 10de:0361 is present in Tyan S2915 OEM systems, but not connected to
1789 * the flash chip. Instead, 10de:0364 is connected to the flash chip.
1790 * Until we have PCI device class matching or some fallback mechanism,
1791 * this is needed to get flashrom working on Tyan S2915 and maybe other
1792 * dual-MCP55 boards.
1793 */
1794#if 0
Nico Huber2e50cdc2018-09-23 20:20:26 +02001795 {0x10de, 0x0361, B_L, NT, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
Carl-Daniel Hailfinger33d7b6a2010-05-22 07:27:16 +00001796#endif
Nico Huber2e50cdc2018-09-23 20:20:26 +02001797 {0x10de, 0x0362, B_L, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1798 {0x10de, 0x0363, B_L, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1799 {0x10de, 0x0364, B_L, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1800 {0x10de, 0x0365, B_L, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1801 {0x10de, 0x0366, B_L, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1802 {0x10de, 0x0367, B_L, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */
1803 {0x10de, 0x03e0, B_LS, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1804 {0x10de, 0x03e1, B_LS, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1805 {0x10de, 0x03e3, B_LS, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1806 {0x10de, 0x0440, B_LS, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1807 {0x10de, 0x0441, B_LS, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1808 {0x10de, 0x0442, B_LS, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1809 {0x10de, 0x0443, B_LS, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1810 {0x10de, 0x0548, B_LS, OK, "NVIDIA", "MCP67", enable_flash_mcp6x_7x},
1811 {0x10de, 0x075c, B_LS, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x},
1812 {0x10de, 0x075d, B_LS, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x},
1813 {0x10de, 0x07d7, B_LS, OK, "NVIDIA", "MCP73", enable_flash_mcp6x_7x},
1814 {0x10de, 0x0aac, B_LS, OK, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1815 {0x10de, 0x0aad, B_LS, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1816 {0x10de, 0x0aae, B_LS, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1817 {0x10de, 0x0aaf, B_LS, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1818 {0x10de, 0x0d80, B_LS, NT, "NVIDIA", "MCP89", enable_flash_mcp6x_7x},
Michael Karcher89bed6d2010-06-13 10:16:12 +00001819 /* VIA northbridges */
Nico Huber2e50cdc2018-09-23 20:20:26 +02001820 {0x1106, 0x0585, B_PFLS, NT, "VIA", "VT82C585VPX", via_no_byte_merge},
1821 {0x1106, 0x0595, B_PFLS, NT, "VIA", "VT82C595", via_no_byte_merge},
1822 {0x1106, 0x0597, B_PFLS, NT, "VIA", "VT82C597", via_no_byte_merge},
1823 {0x1106, 0x0601, B_PFLS, NT, "VIA", "VT8601/VT8601A", via_no_byte_merge},
1824 {0x1106, 0x0691, B_PFLS, OK, "VIA", "VT82C69x", via_no_byte_merge},
1825 {0x1106, 0x8601, B_PFLS, NT, "VIA", "VT8601T", via_no_byte_merge},
Michael Karcher89bed6d2010-06-13 10:16:12 +00001826 /* VIA southbridges */
Nico Huber2e50cdc2018-09-23 20:20:26 +02001827 {0x1106, 0x0586, B_PFL, OK, "VIA", "VT82C586A/B", enable_flash_vt82c586},
1828 {0x1106, 0x0596, B_PFL, OK, "VIA", "VT82C596", enable_flash_vt82c596},
1829 {0x1106, 0x0686, B_PFL, OK, "VIA", "VT82C686A/B", enable_flash_vt82c596},
1830 {0x1106, 0x3074, B_FL, OK, "VIA", "VT8233", enable_flash_vt823x},
1831 {0x1106, 0x3147, B_FL, OK, "VIA", "VT8233A", enable_flash_vt823x},
1832 {0x1106, 0x3177, B_FL, OK, "VIA", "VT8235", enable_flash_vt823x},
1833 {0x1106, 0x3227, B_FL, OK, "VIA", "VT8237(R)", enable_flash_vt823x},
1834 {0x1106, 0x3287, B_FL, OK, "VIA", "VT8251", enable_flash_vt823x},
1835 {0x1106, 0x3337, B_FL, OK, "VIA", "VT8237A", enable_flash_vt823x},
1836 {0x1106, 0x3372, B_LS, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi},
1837 {0x1106, 0x8231, B_FL, NT, "VIA", "VT8231", enable_flash_vt823x},
1838 {0x1106, 0x8324, B_FL, OK, "VIA", "CX700", enable_flash_vt823x},
1839 {0x1106, 0x8353, B_FLS, NT, "VIA", "VX800/VX820", enable_flash_vt_vx},
1840 {0x1106, 0x8409, B_FLS, OK, "VIA", "VX855/VX875", enable_flash_vt_vx},
1841 {0x1106, 0x8410, B_FLS, OK, "VIA", "VX900", enable_flash_vt_vx},
1842 {0x1166, 0x0200, B_P, OK, "Broadcom", "OSB4", enable_flash_osb4},
1843 {0x1166, 0x0205, B_PFL, OK, "Broadcom", "HT-1000", enable_flash_ht1000},
1844 {0x17f3, 0x6030, B_PFL, OK, "RDC", "R8610/R3210", enable_flash_rdc_r8610},
1845 {0x8086, 0x0c60, B_FS, NT, "Intel", "S12x0", enable_flash_s12x0},
1846 {0x8086, 0x0f1c, B_FS, OK, "Intel", "Bay Trail", enable_flash_silvermont},
1847 {0x8086, 0x0f1d, B_FS, NT, "Intel", "Bay Trail", enable_flash_silvermont},
1848 {0x8086, 0x0f1e, B_FS, NT, "Intel", "Bay Trail", enable_flash_silvermont},
1849 {0x8086, 0x0f1f, B_FS, NT, "Intel", "Bay Trail", enable_flash_silvermont},
1850 {0x8086, 0x122e, B_P, OK, "Intel", "PIIX", enable_flash_piix4},
1851 {0x8086, 0x1234, B_P, NT, "Intel", "MPIIX", enable_flash_piix4},
1852 {0x8086, 0x1c44, B_FS, DEP, "Intel", "Z68", enable_flash_pch6},
1853 {0x8086, 0x1c46, B_FS, DEP, "Intel", "P67", enable_flash_pch6},
1854 {0x8086, 0x1c47, B_FS, NT, "Intel", "UM67", enable_flash_pch6},
1855 {0x8086, 0x1c49, B_FS, DEP, "Intel", "HM65", enable_flash_pch6},
1856 {0x8086, 0x1c4a, B_FS, DEP, "Intel", "H67", enable_flash_pch6},
1857 {0x8086, 0x1c4b, B_FS, NT, "Intel", "HM67", enable_flash_pch6},
1858 {0x8086, 0x1c4c, B_FS, NT, "Intel", "Q65", enable_flash_pch6},
Evgeny Zinovievd493baa2021-03-06 21:14:39 +03001859 {0x8086, 0x1c4d, B_FS, DEP, "Intel", "QS67", enable_flash_pch6},
Angel Pons3b3fc932020-11-20 10:05:29 +01001860 {0x8086, 0x1c4e, B_FS, DEP, "Intel", "Q67", enable_flash_pch6},
Nico Huber2e50cdc2018-09-23 20:20:26 +02001861 {0x8086, 0x1c4f, B_FS, DEP, "Intel", "QM67", enable_flash_pch6},
1862 {0x8086, 0x1c50, B_FS, NT, "Intel", "B65", enable_flash_pch6},
1863 {0x8086, 0x1c52, B_FS, NT, "Intel", "C202", enable_flash_pch6},
1864 {0x8086, 0x1c54, B_FS, DEP, "Intel", "C204", enable_flash_pch6},
1865 {0x8086, 0x1c56, B_FS, NT, "Intel", "C206", enable_flash_pch6},
1866 {0x8086, 0x1c5c, B_FS, DEP, "Intel", "H61", enable_flash_pch6},
1867 {0x8086, 0x1d40, B_FS, DEP, "Intel", "C60x/X79", enable_flash_pch6},
1868 {0x8086, 0x1d41, B_FS, DEP, "Intel", "C60x/X79", enable_flash_pch6},
Edward O'Callaghan55f65642020-11-02 14:43:10 +11001869 {0x8086, 0x1e41, B_FS, DEP, "Intel", "Desktop Sample", enable_flash_pch7},
1870 {0x8086, 0x1e42, B_FS, DEP, "Intel", "Mobile Sample", enable_flash_pch7},
1871 {0x8086, 0x1e43, B_FS, DEP, "Intel", "SFF Sample", enable_flash_pch7},
Nico Huber2e50cdc2018-09-23 20:20:26 +02001872 {0x8086, 0x1e44, B_FS, DEP, "Intel", "Z77", enable_flash_pch7},
1873 {0x8086, 0x1e46, B_FS, NT, "Intel", "Z75", enable_flash_pch7},
Jacob Garber1592fe52020-08-28 12:48:32 -06001874 {0x8086, 0x1e47, B_FS, DEP, "Intel", "Q77", enable_flash_pch7},
Angel Ponsd58128e2019-10-06 21:07:44 +02001875 {0x8086, 0x1e48, B_FS, DEP, "Intel", "Q75", enable_flash_pch7},
Nico Huber2e50cdc2018-09-23 20:20:26 +02001876 {0x8086, 0x1e49, B_FS, DEP, "Intel", "B75", enable_flash_pch7},
1877 {0x8086, 0x1e4a, B_FS, DEP, "Intel", "H77", enable_flash_pch7},
Jacob Garber198bef32021-02-20 10:51:56 -07001878 {0x8086, 0x1e53, B_FS, DEP, "Intel", "C216", enable_flash_pch7},
Nico Huber2e50cdc2018-09-23 20:20:26 +02001879 {0x8086, 0x1e55, B_FS, DEP, "Intel", "QM77", enable_flash_pch7},
1880 {0x8086, 0x1e56, B_FS, DEP, "Intel", "QS77", enable_flash_pch7},
1881 {0x8086, 0x1e57, B_FS, DEP, "Intel", "HM77", enable_flash_pch7},
1882 {0x8086, 0x1e58, B_FS, NT, "Intel", "UM77", enable_flash_pch7},
Angel Pons728062f2019-12-18 00:26:15 +01001883 {0x8086, 0x1e59, B_FS, DEP, "Intel", "HM76", enable_flash_pch7},
Evgeny Zinovieva9335cc2020-03-09 03:05:42 +03001884 {0x8086, 0x1e5d, B_FS, DEP, "Intel", "HM75", enable_flash_pch7},
Nico Huber2e50cdc2018-09-23 20:20:26 +02001885 {0x8086, 0x1e5e, B_FS, NT, "Intel", "HM70", enable_flash_pch7},
1886 {0x8086, 0x1e5f, B_FS, DEP, "Intel", "NM70", enable_flash_pch7},
1887 {0x8086, 0x1f38, B_FS, DEP, "Intel", "Avoton/Rangeley", enable_flash_silvermont},
1888 {0x8086, 0x1f39, B_FS, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont},
1889 {0x8086, 0x1f3a, B_FS, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont},
1890 {0x8086, 0x1f3b, B_FS, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont},
1891 {0x8086, 0x229c, B_FS, OK, "Intel", "Braswell", enable_flash_silvermont},
1892 {0x8086, 0x2310, B_FS, NT, "Intel", "DH89xxCC (Cave Creek)", enable_flash_pch7},
1893 {0x8086, 0x2390, B_FS, NT, "Intel", "Coleto Creek", enable_flash_pch7},
1894 {0x8086, 0x2410, B_FL, OK, "Intel", "ICH", enable_flash_ich0},
1895 {0x8086, 0x2420, B_FL, OK, "Intel", "ICH0", enable_flash_ich0},
1896 {0x8086, 0x2440, B_FL, OK, "Intel", "ICH2", enable_flash_ich2345},
1897 {0x8086, 0x244c, B_FL, OK, "Intel", "ICH2-M", enable_flash_ich2345},
1898 {0x8086, 0x2450, B_FL, NT, "Intel", "C-ICH", enable_flash_ich2345},
1899 {0x8086, 0x2480, B_FL, OK, "Intel", "ICH3-S", enable_flash_ich2345},
1900 {0x8086, 0x248c, B_FL, OK, "Intel", "ICH3-M", enable_flash_ich2345},
1901 {0x8086, 0x24c0, B_FL, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich2345},
1902 {0x8086, 0x24cc, B_FL, OK, "Intel", "ICH4-M", enable_flash_ich2345},
1903 {0x8086, 0x24d0, B_FL, OK, "Intel", "ICH5/ICH5R", enable_flash_ich2345},
1904 {0x8086, 0x25a1, B_FL, OK, "Intel", "6300ESB", enable_flash_ich2345},
1905 {0x8086, 0x2640, B_FL, OK, "Intel", "ICH6/ICH6R", enable_flash_ich6},
1906 {0x8086, 0x2641, B_FL, OK, "Intel", "ICH6-M", enable_flash_ich6},
1907 {0x8086, 0x2642, B_FL, NT, "Intel", "ICH6W/ICH6RW", enable_flash_ich6},
1908 {0x8086, 0x2670, B_FL, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich6},
1909 {0x8086, 0x27b0, B_FS, OK, "Intel", "ICH7DH", enable_flash_ich7},
1910 {0x8086, 0x27b8, B_FS, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7},
1911 {0x8086, 0x27b9, B_FS, OK, "Intel", "ICH7M", enable_flash_ich7},
1912 {0x8086, 0x27bc, B_FS, OK, "Intel", "NM10", enable_flash_ich7},
1913 {0x8086, 0x27bd, B_FS, OK, "Intel", "ICH7MDH", enable_flash_ich7},
1914 {0x8086, 0x2810, B_FS, DEP, "Intel", "ICH8/ICH8R", enable_flash_ich8},
1915 {0x8086, 0x2811, B_FS, DEP, "Intel", "ICH8M-E", enable_flash_ich8},
1916 {0x8086, 0x2812, B_FS, DEP, "Intel", "ICH8DH", enable_flash_ich8},
1917 {0x8086, 0x2814, B_FS, DEP, "Intel", "ICH8DO", enable_flash_ich8},
1918 {0x8086, 0x2815, B_FS, DEP, "Intel", "ICH8M", enable_flash_ich8},
1919 {0x8086, 0x2910, B_FS, DEP, "Intel", "ICH9 Eng. Sample", enable_flash_ich9},
1920 {0x8086, 0x2912, B_FS, DEP, "Intel", "ICH9DH", enable_flash_ich9},
1921 {0x8086, 0x2914, B_FS, DEP, "Intel", "ICH9DO", enable_flash_ich9},
1922 {0x8086, 0x2916, B_FS, DEP, "Intel", "ICH9R", enable_flash_ich9},
1923 {0x8086, 0x2917, B_FS, DEP, "Intel", "ICH9M-E", enable_flash_ich9},
1924 {0x8086, 0x2918, B_FS, DEP, "Intel", "ICH9", enable_flash_ich9},
1925 {0x8086, 0x2919, B_FS, DEP, "Intel", "ICH9M", enable_flash_ich9},
1926 {0x8086, 0x3a10, B_FS, NT, "Intel", "ICH10R Eng. Sample", enable_flash_ich10},
1927 {0x8086, 0x3a14, B_FS, DEP, "Intel", "ICH10DO", enable_flash_ich10},
1928 {0x8086, 0x3a16, B_FS, DEP, "Intel", "ICH10R", enable_flash_ich10},
1929 {0x8086, 0x3a18, B_FS, DEP, "Intel", "ICH10", enable_flash_ich10},
1930 {0x8086, 0x3a1a, B_FS, DEP, "Intel", "ICH10D", enable_flash_ich10},
1931 {0x8086, 0x3a1e, B_FS, NT, "Intel", "ICH10 Eng. Sample", enable_flash_ich10},
1932 {0x8086, 0x3b00, B_FS, NT, "Intel", "3400 Desktop", enable_flash_pch5},
1933 {0x8086, 0x3b01, B_FS, NT, "Intel", "3400 Mobile", enable_flash_pch5},
1934 {0x8086, 0x3b02, B_FS, NT, "Intel", "P55", enable_flash_pch5},
1935 {0x8086, 0x3b03, B_FS, DEP, "Intel", "PM55", enable_flash_pch5},
1936 {0x8086, 0x3b06, B_FS, DEP, "Intel", "H55", enable_flash_pch5},
1937 {0x8086, 0x3b07, B_FS, DEP, "Intel", "QM57", enable_flash_pch5},
1938 {0x8086, 0x3b08, B_FS, NT, "Intel", "H57", enable_flash_pch5},
1939 {0x8086, 0x3b09, B_FS, DEP, "Intel", "HM55", enable_flash_pch5},
1940 {0x8086, 0x3b0a, B_FS, NT, "Intel", "Q57", enable_flash_pch5},
1941 {0x8086, 0x3b0b, B_FS, NT, "Intel", "HM57", enable_flash_pch5},
1942 {0x8086, 0x3b0d, B_FS, NT, "Intel", "3400 Mobile SFF", enable_flash_pch5},
1943 {0x8086, 0x3b0e, B_FS, NT, "Intel", "B55", enable_flash_pch5},
1944 {0x8086, 0x3b0f, B_FS, DEP, "Intel", "QS57", enable_flash_pch5},
1945 {0x8086, 0x3b12, B_FS, NT, "Intel", "3400", enable_flash_pch5},
1946 {0x8086, 0x3b14, B_FS, DEP, "Intel", "3420", enable_flash_pch5},
1947 {0x8086, 0x3b16, B_FS, NT, "Intel", "3450", enable_flash_pch5},
1948 {0x8086, 0x3b1e, B_FS, NT, "Intel", "B55", enable_flash_pch5},
1949 {0x8086, 0x5031, B_FS, OK, "Intel", "EP80579", enable_flash_ich7},
1950 {0x8086, 0x7000, B_P, OK, "Intel", "PIIX3", enable_flash_piix4},
1951 {0x8086, 0x7110, B_P, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4},
1952 {0x8086, 0x7198, B_P, OK, "Intel", "440MX", enable_flash_piix4},
1953 {0x8086, 0x8119, B_FL, OK, "Intel", "SCH Poulsbo", enable_flash_poulsbo},
1954 {0x8086, 0x8186, B_FS, OK, "Intel", "Atom E6xx(T) (Tunnel Creek)", enable_flash_tunnelcreek},
1955 {0x8086, 0x8c40, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1956 {0x8086, 0x8c41, B_FS, NT, "Intel", "Lynx Point Mobile Eng. Sample", enable_flash_pch8},
1957 {0x8086, 0x8c42, B_FS, NT, "Intel", "Lynx Point Desktop Eng. Sample",enable_flash_pch8},
1958 {0x8086, 0x8c43, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1959 {0x8086, 0x8c44, B_FS, DEP, "Intel", "Z87", enable_flash_pch8},
1960 {0x8086, 0x8c45, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1961 {0x8086, 0x8c46, B_FS, NT, "Intel", "Z85", enable_flash_pch8},
1962 {0x8086, 0x8c47, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1963 {0x8086, 0x8c48, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1964 {0x8086, 0x8c49, B_FS, NT, "Intel", "HM86", enable_flash_pch8},
1965 {0x8086, 0x8c4a, B_FS, DEP, "Intel", "H87", enable_flash_pch8},
1966 {0x8086, 0x8c4b, B_FS, DEP, "Intel", "HM87", enable_flash_pch8},
1967 {0x8086, 0x8c4c, B_FS, NT, "Intel", "Q85", enable_flash_pch8},
1968 {0x8086, 0x8c4d, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1969 {0x8086, 0x8c4e, B_FS, NT, "Intel", "Q87", enable_flash_pch8},
1970 {0x8086, 0x8c4f, B_FS, NT, "Intel", "QM87", enable_flash_pch8},
1971 {0x8086, 0x8c50, B_FS, DEP, "Intel", "B85", enable_flash_pch8},
1972 {0x8086, 0x8c51, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1973 {0x8086, 0x8c52, B_FS, NT, "Intel", "C222", enable_flash_pch8},
1974 {0x8086, 0x8c53, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1975 {0x8086, 0x8c54, B_FS, DEP, "Intel", "C224", enable_flash_pch8},
1976 {0x8086, 0x8c55, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1977 {0x8086, 0x8c56, B_FS, NT, "Intel", "C226", enable_flash_pch8},
1978 {0x8086, 0x8c57, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1979 {0x8086, 0x8c58, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1980 {0x8086, 0x8c59, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1981 {0x8086, 0x8c5a, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1982 {0x8086, 0x8c5b, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1983 {0x8086, 0x8c5c, B_FS, DEP, "Intel", "H81", enable_flash_pch8},
1984 {0x8086, 0x8c5d, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1985 {0x8086, 0x8c5e, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1986 {0x8086, 0x8c5f, B_FS, NT, "Intel", "Lynx Point", enable_flash_pch8},
1987 {0x8086, 0x8cc1, B_FS, NT, "Intel", "9 Series", enable_flash_pch9},
1988 {0x8086, 0x8cc2, B_FS, NT, "Intel", "9 Series Engineering Sample", enable_flash_pch9},
1989 {0x8086, 0x8cc3, B_FS, NT, "Intel", "9 Series", enable_flash_pch9},
Sophie van Soesteec477f2021-07-04 13:54:26 +02001990 {0x8086, 0x8cc4, B_FS, DEP, "Intel", "Z97", enable_flash_pch9},
Nico Huber2e50cdc2018-09-23 20:20:26 +02001991 {0x8086, 0x8cc6, B_FS, NT, "Intel", "H97", enable_flash_pch9},
1992 {0x8086, 0x8d40, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1993 {0x8086, 0x8d41, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1994 {0x8086, 0x8d42, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1995 {0x8086, 0x8d43, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1996 {0x8086, 0x8d44, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1997 {0x8086, 0x8d45, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1998 {0x8086, 0x8d46, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1999 {0x8086, 0x8d47, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2000 {0x8086, 0x8d48, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2001 {0x8086, 0x8d49, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2002 {0x8086, 0x8d4a, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2003 {0x8086, 0x8d4b, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2004 {0x8086, 0x8d4c, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2005 {0x8086, 0x8d4d, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2006 {0x8086, 0x8d4e, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2007 {0x8086, 0x8d4f, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2008 {0x8086, 0x8d50, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2009 {0x8086, 0x8d51, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2010 {0x8086, 0x8d52, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2011 {0x8086, 0x8d53, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2012 {0x8086, 0x8d54, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2013 {0x8086, 0x8d55, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2014 {0x8086, 0x8d56, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2015 {0x8086, 0x8d57, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2016 {0x8086, 0x8d58, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2017 {0x8086, 0x8d59, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2018 {0x8086, 0x8d5a, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2019 {0x8086, 0x8d5b, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2020 {0x8086, 0x8d5c, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2021 {0x8086, 0x8d5d, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2022 {0x8086, 0x8d5e, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2023 {0x8086, 0x8d5f, B_FS, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
2024 {0x8086, 0x9c41, B_FS, NT, "Intel", "Lynx Point LP Eng. Sample", enable_flash_pch8_lp},
2025 {0x8086, 0x9c43, B_FS, NT, "Intel", "Lynx Point LP Premium", enable_flash_pch8_lp},
2026 {0x8086, 0x9c45, B_FS, NT, "Intel", "Lynx Point LP Mainstream", enable_flash_pch8_lp},
2027 {0x8086, 0x9c47, B_FS, NT, "Intel", "Lynx Point LP Value", enable_flash_pch8_lp},
2028 {0x8086, 0x9cc1, B_FS, NT, "Intel", "Haswell U Sample", enable_flash_pch9_lp},
2029 {0x8086, 0x9cc2, B_FS, NT, "Intel", "Broadwell U Sample", enable_flash_pch9_lp},
2030 {0x8086, 0x9cc3, B_FS, DEP, "Intel", "Broadwell U Premium", enable_flash_pch9_lp},
Nikolai Artemiev2bb67922020-11-03 17:19:52 +11002031 {0x8086, 0x9cc5, B_FS, DEP, "Intel", "Broadwell U Base", enable_flash_pch9_lp},
Nico Huber2e50cdc2018-09-23 20:20:26 +02002032 {0x8086, 0x9cc6, B_FS, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9_lp},
2033 {0x8086, 0x9cc7, B_FS, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9_lp},
2034 {0x8086, 0x9cc9, B_FS, NT, "Intel", "Broadwell Y Base", enable_flash_pch9_lp},
2035 {0x8086, 0x9ccb, B_FS, NT, "Intel", "Broadwell H", enable_flash_pch9},
2036 {0x8086, 0x9d41, B_S, NT, "Intel", "Skylake / Kaby Lake Sample", enable_flash_pch100},
2037 {0x8086, 0x9d43, B_S, NT, "Intel", "Skylake U Base", enable_flash_pch100},
2038 {0x8086, 0x9d46, B_S, NT, "Intel", "Skylake Y Premium", enable_flash_pch100},
Angel Pons7113d172020-02-29 23:13:43 +01002039 {0x8086, 0x9d48, B_S, DEP, "Intel", "Skylake U Premium", enable_flash_pch100},
Nico Huber2e50cdc2018-09-23 20:20:26 +02002040 {0x8086, 0x9d4b, B_S, NT, "Intel", "Kaby Lake Y w/ iHDCP2.2 Prem.", enable_flash_pch100},
Wim Vervoorn3799a1c2020-01-20 15:01:54 +01002041 {0x8086, 0x9d4e, B_S, DEP, "Intel", "Kaby Lake U w/ iHDCP2.2 Prem.", enable_flash_pch100},
Nico Huber2e50cdc2018-09-23 20:20:26 +02002042 {0x8086, 0x9d50, B_S, NT, "Intel", "Kaby Lake U w/ iHDCP2.2 Base", enable_flash_pch100},
2043 {0x8086, 0x9d51, B_S, NT, "Intel", "Kabe Lake w/ iHDCP2.2 Sample", enable_flash_pch100},
2044 {0x8086, 0x9d53, B_S, NT, "Intel", "Kaby Lake U Base", enable_flash_pch100},
2045 {0x8086, 0x9d56, B_S, NT, "Intel", "Kaby Lake Y Premium", enable_flash_pch100},
2046 {0x8086, 0x9d58, B_S, NT, "Intel", "Kaby Lake U Premium", enable_flash_pch100},
Matt DeVillierbde44a12019-07-04 17:52:40 -05002047 {0x8086, 0x9d84, B_S, DEP, "Intel", "Cannon Lake U Premium", enable_flash_pch300},
Matt DeVillier4f29bb72020-08-12 12:48:06 -05002048 {0x8086, 0x0284, B_S, DEP, "Intel", "Comet Lake U Premium", enable_flash_pch300},
Sam McNally76303902021-03-11 11:41:46 +11002049 {0x8086, 0x0285, B_S, DEP, "Intel", "Comet Lake U Base", enable_flash_pch300},
Michał Żygowski5c9f5422021-06-16 15:13:54 +02002050 {0x8086, 0xa082, B_S, DEP, "Intel", "Tiger Lake U Premium", enable_flash_pch500},
Nico Huber2e50cdc2018-09-23 20:20:26 +02002051 {0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100},
2052 {0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100},
Angel Ponsabb34fe2020-12-06 23:09:13 +01002053 {0x8086, 0xa143, B_S, DEP, "Intel", "H110", enable_flash_pch100},
Nico Huber2e50cdc2018-09-23 20:20:26 +02002054 {0x8086, 0xa144, B_S, NT, "Intel", "H170", enable_flash_pch100},
2055 {0x8086, 0xa145, B_S, NT, "Intel", "Z170", enable_flash_pch100},
2056 {0x8086, 0xa146, B_S, NT, "Intel", "Q170", enable_flash_pch100},
2057 {0x8086, 0xa147, B_S, NT, "Intel", "Q150", enable_flash_pch100},
2058 {0x8086, 0xa148, B_S, NT, "Intel", "B150", enable_flash_pch100},
2059 {0x8086, 0xa149, B_S, NT, "Intel", "C236", enable_flash_pch100},
2060 {0x8086, 0xa14a, B_S, NT, "Intel", "C232", enable_flash_pch100},
2061 {0x8086, 0xa14b, B_S, NT, "Intel", "Sunrise Point Server Sample", enable_flash_pch100},
2062 {0x8086, 0xa14d, B_S, NT, "Intel", "QM170", enable_flash_pch100},
2063 {0x8086, 0xa14e, B_S, NT, "Intel", "HM170", enable_flash_pch100},
Nico Huberea0c0932019-07-04 17:34:16 +02002064 {0x8086, 0xa150, B_S, DEP, "Intel", "CM236", enable_flash_pch100},
Nico Huber2e50cdc2018-09-23 20:20:26 +02002065 {0x8086, 0xa151, B_S, NT, "Intel", "QMS180", enable_flash_pch100},
2066 {0x8086, 0xa152, B_S, NT, "Intel", "HM175", enable_flash_pch100},
2067 {0x8086, 0xa153, B_S, NT, "Intel", "QM175", enable_flash_pch100},
2068 {0x8086, 0xa154, B_S, NT, "Intel", "CM238", enable_flash_pch100},
2069 {0x8086, 0xa155, B_S, NT, "Intel", "QMU185", enable_flash_pch100},
Luka Kovacic9f064192020-07-30 13:31:15 +02002070 {0x8086, 0xa1a4, B_S, DEP, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620},
Angel Pons77a2a6e2020-03-23 16:05:07 +01002071 {0x8086, 0xa1c0, B_S, NT, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620},
Nico Huber2e50cdc2018-09-23 20:20:26 +02002072 {0x8086, 0xa1c1, B_S, NT, "Intel", "C621 Series Chipset (QS/PRQ)", enable_flash_c620},
2073 {0x8086, 0xa1c2, B_S, NT, "Intel", "C622 Series Chipset (QS/PRQ)", enable_flash_c620},
2074 {0x8086, 0xa1c3, B_S, NT, "Intel", "C624 Series Chipset (QS/PRQ)", enable_flash_c620},
2075 {0x8086, 0xa1c4, B_S, NT, "Intel", "C625 Series Chipset (QS/PRQ)", enable_flash_c620},
2076 {0x8086, 0xa1c5, B_S, NT, "Intel", "C626 Series Chipset (QS/PRQ)", enable_flash_c620},
2077 {0x8086, 0xa1c6, B_S, NT, "Intel", "C627 Series Chipset (QS/PRQ)", enable_flash_c620},
2078 {0x8086, 0xa1c7, B_S, NT, "Intel", "C628 Series Chipset (QS/PRQ)", enable_flash_c620},
Angel Pons77a2a6e2020-03-23 16:05:07 +01002079 {0x8086, 0xa1c8, B_S, NT, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620},
2080 {0x8086, 0xa1c9, B_S, NT, "Intel", "C620 Series Chipset (QS/PRQ)", enable_flash_c620},
2081 {0x8086, 0xa1ca, B_S, NT, "Intel", "C629 Series Chipset (QS/PRQ)", enable_flash_c620},
Jonathan Zhangc218a052020-08-19 12:16:40 -07002082 {0x8086, 0xa1cb, B_S, NT, "Intel", "C621A Series Chipset (QS/PRQ)", enable_flash_c620},
2083 {0x8086, 0xa1cc, B_S, NT, "Intel", "C627A Series Chipset (QS/PRQ)", enable_flash_c620},
2084 {0x8086, 0xa1cd, B_S, NT, "Intel", "C629A Series Chipset (QS/PRQ)", enable_flash_c620},
Angel Pons77a2a6e2020-03-23 16:05:07 +01002085 {0x8086, 0xa240, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620},
2086 {0x8086, 0xa241, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620},
Nico Huber2e50cdc2018-09-23 20:20:26 +02002087 {0x8086, 0xa242, B_S, NT, "Intel", "C624 Series Chipset Supersku", enable_flash_c620},
2088 {0x8086, 0xa243, B_S, NT, "Intel", "C627 Series Chipset Supersku", enable_flash_c620},
2089 {0x8086, 0xa244, B_S, NT, "Intel", "C621 Series Chipset Supersku", enable_flash_c620},
2090 {0x8086, 0xa245, B_S, NT, "Intel", "C627 Series Chipset Supersku", enable_flash_c620},
2091 {0x8086, 0xa246, B_S, NT, "Intel", "C628 Series Chipset Supersku", enable_flash_c620},
2092 {0x8086, 0xa247, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620},
Angel Pons77a2a6e2020-03-23 16:05:07 +01002093 {0x8086, 0xa248, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620},
2094 {0x8086, 0xa249, B_S, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620},
Jonathan Zhang3bf7cfb2021-08-30 23:25:06 -07002095 {0x8086, 0x1bca, B_S, NT, "Intel", "Emmitsburg Chipset SKU", enable_flash_c620},
Nico Huber2e50cdc2018-09-23 20:20:26 +02002096 {0x8086, 0xa2c4, B_S, NT, "Intel", "H270", enable_flash_pch100},
2097 {0x8086, 0xa2c5, B_S, NT, "Intel", "Z270", enable_flash_pch100},
2098 {0x8086, 0xa2c6, B_S, NT, "Intel", "Q270", enable_flash_pch100},
2099 {0x8086, 0xa2c7, B_S, NT, "Intel", "Q250", enable_flash_pch100},
2100 {0x8086, 0xa2c8, B_S, NT, "Intel", "B250", enable_flash_pch100},
2101 {0x8086, 0xa2c9, B_S, NT, "Intel", "Z370", enable_flash_pch100},
Angel Ponsb499b672021-04-22 17:08:00 +02002102 {0x8086, 0xa2ca, B_S, DEP, "Intel", "H310C", enable_flash_pch100},
2103 {0x8086, 0xa2cc, B_S, DEP, "Intel", "B365", enable_flash_pch100},
Nico Huber2e50cdc2018-09-23 20:20:26 +02002104 {0x8086, 0xa2d2, B_S, NT, "Intel", "X299", enable_flash_pch100},
Nico Huberd2d39932019-01-18 16:49:37 +01002105 {0x8086, 0x5ae8, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl},
Jan Samek1f967c82020-01-08 12:35:14 +01002106 {0x8086, 0x5af0, B_S, DEP, "Intel", "Apollo Lake", enable_flash_apl},
Angel Pons1c7297f2021-05-17 10:50:40 +02002107 {0x8086, 0x3197, B_S, NT, "Intel", "Gemini Lake", enable_flash_glk},
Angel Pons4db0fdf2020-07-10 17:04:10 +02002108 {0x8086, 0x31e8, B_S, DEP, "Intel", "Gemini Lake", enable_flash_glk},
Werner Zehe57d4e42022-01-03 09:44:29 +01002109 {0x8086, 0x4b24, B_S, DEP, "Intel", "Elkhart Lake", enable_flash_mcc},
Nico Huber2a5dfaf2019-07-04 16:01:51 +02002110 {0x8086, 0xa303, B_S, NT, "Intel", "H310", enable_flash_pch300},
2111 {0x8086, 0xa304, B_S, NT, "Intel", "H370", enable_flash_pch300},
melvyn269c324a2021-10-30 16:02:22 -07002112 {0x8086, 0xa305, B_S, DEP, "Intel", "Z390", enable_flash_pch300},
Nico Huber2a5dfaf2019-07-04 16:01:51 +02002113 {0x8086, 0xa306, B_S, NT, "Intel", "Q370", enable_flash_pch300},
2114 {0x8086, 0xa308, B_S, NT, "Intel", "B360", enable_flash_pch300},
Angel Pons0c8221b2022-10-20 21:23:33 +02002115 {0x8086, 0xa309, B_S, DEP, "Intel", "C246", enable_flash_pch300},
Nico Huber2a5dfaf2019-07-04 16:01:51 +02002116 {0x8086, 0xa30a, B_S, NT, "Intel", "C242", enable_flash_pch300},
2117 {0x8086, 0xa30c, B_S, NT, "Intel", "QM370", enable_flash_pch300},
2118 {0x8086, 0xa30d, B_S, NT, "Intel", "HM370", enable_flash_pch300},
Nico Huberea0c0932019-07-04 17:34:16 +02002119 {0x8086, 0xa30e, B_S, DEP, "Intel", "CM246", enable_flash_pch300},
Johanna Schanderb5433b72019-12-29 15:16:14 +01002120 {0x8086, 0x3482, B_S, DEP, "Intel", "Ice Lake U Premium", enable_flash_pch300},
Gaggery Tsaibc0285c2019-12-12 11:52:03 -08002121 {0x8086, 0x0684, B_S, NT, "Intel", "H470", enable_flash_pch300},
2122 {0x8086, 0x0685, B_S, NT, "Intel", "Z490", enable_flash_pch300},
2123 {0x8086, 0x0687, B_S, NT, "Intel", "Q470", enable_flash_pch300},
2124 {0x8086, 0x068c, B_S, NT, "Intel", "QM480", enable_flash_pch300},
2125 {0x8086, 0x068d, B_S, NT, "Intel", "HM470", enable_flash_pch300},
2126 {0x8086, 0x068e, B_S, NT, "Intel", "WM490", enable_flash_pch300},
2127 {0x8086, 0x0697, B_S, NT, "Intel", "W480", enable_flash_pch300},
Nico Huber756b6b32022-12-21 17:15:13 +00002128 {0x8086, 0x4da4, B_S, NT, "Intel", "Jasper Lake", enable_flash_pch300},
Tim Crawfordfafc3d82021-11-17 06:23:25 -07002129 {0x8086, 0x4384, B_S, NT, "Intel", "Q570", enable_flash_pch500},
2130 {0x8086, 0x4385, B_S, NT, "Intel", "Z590", enable_flash_pch500},
2131 {0x8086, 0x4386, B_S, NT, "Intel", "H570", enable_flash_pch500},
2132 {0x8086, 0x4387, B_S, NT, "Intel", "B560", enable_flash_pch500},
2133 {0x8086, 0x4388, B_S, NT, "Intel", "H510", enable_flash_pch500},
2134 {0x8086, 0x438f, B_S, NT, "Intel", "W580", enable_flash_pch500},
2135 {0x8086, 0x4389, B_S, NT, "Intel", "WM590", enable_flash_pch500},
2136 {0x8086, 0x438a, B_S, NT, "Intel", "QM580", enable_flash_pch500},
2137 {0x8086, 0x438b, B_S, DEP, "Intel", "HM570", enable_flash_pch500},
Nico Huber29c23dd2022-12-21 15:25:09 +00002138 {0x8086, 0x51a4, B_S, DEP, "Intel", "Alder Lake-P", enable_flash_pch500},
2139 {0x8086, 0x54a4, B_S, DEP, "Intel", "Alder Lake-N", enable_flash_pch500},
2140 {0x8086, 0x7aa4, B_S, NT, "Intel", "Alder Lake-S", enable_flash_pch500},
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002141#endif
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +00002142 {0},
Ollie Lhocbbf1252004-03-17 22:22:08 +00002143};
Ollie Lho761bf1b2004-03-20 16:46:10 +00002144
Uwe Hermanna7e05482007-05-09 10:17:44 +00002145int chipset_flash_enable(void)
Ollie Lhocbbf1252004-03-17 22:22:08 +00002146{
Peter Huewe73f8ec82011-01-24 19:15:51 +00002147 struct pci_dev *dev = NULL;
Uwe Hermann372eeb52007-12-04 21:49:06 +00002148 int ret = -2; /* Nothing! */
Uwe Hermanna7e05482007-05-09 10:17:44 +00002149 int i;
Ollie Lhocbbf1252004-03-17 22:22:08 +00002150
Uwe Hermann372eeb52007-12-04 21:49:06 +00002151 /* Now let's try to find the chipset we have... */
Uwe Hermann05fab752009-05-16 23:42:17 +00002152 for (i = 0; chipset_enables[i].vendor_name != NULL; i++) {
Edward O'Callaghan19ce50d2021-11-13 17:59:18 +11002153 dev = pcidev_find(chipset_enables[i].vendor_id,
Uwe Hermann05fab752009-05-16 23:42:17 +00002154 chipset_enables[i].device_id);
Michael Karcher89bed6d2010-06-13 10:16:12 +00002155 if (!dev)
2156 continue;
2157 if (ret != -2) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00002158 msg_pwarn("Warning: unexpected second chipset match: "
Paul Menzelab6328f2010-10-08 11:03:02 +00002159 "\"%s %s\"\n"
2160 "ignoring, please report lspci and board URL "
Nico Huberac90af62022-12-18 00:22:47 +00002161 "to flashrom-stable@flashrom.org\n"
Stefan Reinauerbf282b12011-03-29 21:41:41 +00002162 "with \'CHIPSET: your board name\' in the "
Paul Menzelab6328f2010-10-08 11:03:02 +00002163 "subject line.\n",
Michael Karcher89bed6d2010-06-13 10:16:12 +00002164 chipset_enables[i].vendor_name,
2165 chipset_enables[i].device_name);
2166 continue;
2167 }
Stefan Taunerec8c2482011-07-21 19:59:34 +00002168 msg_pinfo("Found chipset \"%s %s\"",
2169 chipset_enables[i].vendor_name,
2170 chipset_enables[i].device_name);
Stefan Tauner716e0982011-07-25 20:38:52 +00002171 msg_pdbg(" with PCI ID %04x:%04x",
Carl-Daniel Hailfingerf469c272010-05-22 07:31:50 +00002172 chipset_enables[i].vendor_id,
2173 chipset_enables[i].device_id);
Stefan Tauner5c316f92015-02-08 21:57:52 +00002174 msg_pinfo(".\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00002175
Stefan Tauner23e10b82016-01-23 16:16:49 +00002176 if (chipset_enables[i].status == BAD) {
2177 msg_perr("ERROR: This chipset is not supported yet.\n");
2178 return ERROR_FATAL;
2179 }
Stefan Taunerec8c2482011-07-21 19:59:34 +00002180 if (chipset_enables[i].status == NT) {
Stefan Tauner5c316f92015-02-08 21:57:52 +00002181 msg_pinfo("This chipset is marked as untested. If "
Stefan Taunerec8c2482011-07-21 19:59:34 +00002182 "you are using an up-to-date version\nof "
Stefan Tauner2abab942012-04-27 20:41:23 +00002183 "flashrom *and* were (not) able to "
2184 "successfully update your firmware with it,\n"
2185 "then please email a report to "
Nico Huberac90af62022-12-18 00:22:47 +00002186 "flashrom-stable@flashrom.org including a\n"
2187 "verbose (-V) log.\nThank you!\n");
Stefan Taunerec8c2482011-07-21 19:59:34 +00002188 }
Nico Huber2e50cdc2018-09-23 20:20:26 +02002189 if (!(chipset_enables[i].buses & (internal_buses_supported | BUS_SPI))) {
2190 msg_pdbg("Skipping chipset enable: No supported buses enabled.\n");
2191 continue;
2192 }
Stefan Taunerec8c2482011-07-21 19:59:34 +00002193 msg_pinfo("Enabling flash write... ");
Stefan Tauner23e10b82016-01-23 16:16:49 +00002194 ret = chipset_enables[i].doit(dev, chipset_enables[i].device_name);
Michael Karcher89bed6d2010-06-13 10:16:12 +00002195 if (ret == NOT_DONE_YET) {
2196 ret = -2;
2197 msg_pinfo("OK - searching further chips.\n");
2198 } else if (ret < 0)
Sean Nelson316a29f2010-05-07 20:09:04 +00002199 msg_pinfo("FAILED!\n");
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002200 else if (ret == 0)
Sean Nelson316a29f2010-05-07 20:09:04 +00002201 msg_pinfo("OK.\n");
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002202 else if (ret == ERROR_NONFATAL)
Michael Karchera4448d92010-07-22 18:04:15 +00002203 msg_pinfo("PROBLEMS, continuing anyway\n");
Tadas Slotkusad470342011-09-03 17:15:00 +00002204 if (ret == ERROR_FATAL) {
2205 msg_perr("FATAL ERROR!\n");
2206 return ret;
2207 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00002208 }
Michael Karcher89bed6d2010-06-13 10:16:12 +00002209
Uwe Hermanna7e05482007-05-09 10:17:44 +00002210 return ret;
Ollie Lhocbbf1252004-03-17 22:22:08 +00002211}