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review.sourcearcade.org / libgfxinit / refs/heads/main / . / common / hw-gfx-gma-registers.ads
blob: 498cb533a71e674d19f23ab62f59ee5dc493c226 [file] [log] [blame]
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1--
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]2-- Copyright (C) 2015-2017 secunet Security Networks AG
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +0200[diff] [blame]6-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]8--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
15with System;
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]16with HW.GFX.GMA.Config;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]17
18private package HW.GFX.GMA.Registers
19with
20 Abstract_State =>
21 ((Address_State with Part_Of => GMA.State),
22 (Register_State with External, Part_Of => GMA.Device_State),
23 (GTT_State with External, Part_Of => GMA.Device_State)),
24 Initializes => Address_State
25is
Nico Huber0b2329a2018-06-09 21:14:27 +0200[diff] [blame]26
27 MMIO_GTT_32_Size : constant := 16#20_0000#;
28 MMIO_GTT_32_Offset : constant := 16#20_0000#;
29
30 -- Limit Broadwell+ to 4MiB to have a stable
31 -- interface (i.e. same number of entries):
32 MMIO_GTT_64_Size : constant := 16#40_0000#;
33 MMIO_GTT_64_Offset : constant := 16#80_0000#;
34
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]35 type Registers_Invalid_Index is
36 (Invalid_Register, -- Allow a placeholder when access is not acceptable
37
38 RCS_RING_BUFFER_TAIL,
39 RCS_RING_BUFFER_HEAD,
40 RCS_RING_BUFFER_STRT,
41 RCS_RING_BUFFER_CTL,
42 QUIRK_02084,
43 QUIRK_02090,
44 HWSTAM,
45 MI_MODE,
46 INSTPM,
47 GT_MODE,
48 CACHE_MODE_0,
49 CTX_SIZE,
50 PP_DCLV_HIGH,
51 PP_DCLV_LOW,
52 GFX_MODE,
53 ARB_MODE,
54 HWS_PGA,
55 GAM_ECOCHK,
Arthur Heymans229ed1c2018-03-28 16:45:43 +0200[diff] [blame]56 GMCH_GMBUS0,
57 GMCH_GMBUS1,
58 GMCH_GMBUS2,
59 GMCH_GMBUS3,
60 GMCH_GMBUS4,
61 GMCH_GMBUS5,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]62 GMCH_DPLL_A,
63 GMCH_DPLL_B,
64 GMCH_FPA0,
65 GMCH_FPA1,
66 GMCH_FPB0,
67 GMCH_FPB1,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]68 MBCTL,
69 UCGCTL1,
70 UCGCTL2,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]71 GMCH_CLKCFG,
Nico Huberb47a5c42019-09-29 00:07:21 +0200[diff] [blame]72 GMCH_HPLLVCO_MOBILE,
73 GMCH_HPLLVCO,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]74 VCS_RING_BUFFER_TAIL,
75 VCS_RING_BUFFER_HEAD,
76 VCS_RING_BUFFER_STRT,
77 VCS_RING_BUFFER_CTL,
78 SLEEP_PSMI_CONTROL,
79 VCS_HWSTAM,
80 VCS_PP_DCLV_HIGH,
81 VCS_PP_DCLV_LOW,
82 GAC_ECO_BITS,
83 BCS_RING_BUFFER_TAIL,
84 BCS_RING_BUFFER_HEAD,
85 BCS_RING_BUFFER_STRT,
86 BCS_RING_BUFFER_CTL,
87 BCS_HWSTAM,
88 BCS_PP_DCLV_HIGH,
89 BCS_PP_DCLV_LOW,
90 GAB_CTL_REG,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]91 CPU_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]92 FUSE_STATUS,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]93 ILK_DISPLAY_CHICKEN2,
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]94 FUSE_STRAP,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]95 DSPCLK_GATE_D,
96 FBA_CFB_BASE,
97 FBC_CTL,
98 IPS_CTL,
99 DEISR,
100 DEIMR,
101 DEIIR,
102 DEIER,
103 GTISR,
104 GTIMR,
105 GTIIR,
106 GTIER,
107 IIR,
108 HOTPLUG_CTL,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]109 TC_HOTPLUG_CTL,
110 DISPLAY_ERR_FATAL_MASK,
111 DBUF_CTL_S2,
112 DBUF_CTL_S3,
113 MBUS_CTL,
114 GEN11_DE_HPD_ISR,
115 DBUF_CTL_S1,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]116 ARB_CTL,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]117 DBUF_CTL_S0,
118 MBUS_ABOX_CTL,
119 MBUS_ABOX1_CTL,
120 MBUS_ABOX2_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]121 WM_PIPE_A,
122 WM_PIPE_B,
123 WM1_LP_ILK,
124 WM2_LP_ILK,
125 WM3_LP_ILK,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]126 BW_BUDDY1_CTL,
127 BW_BUDDY1_PAGE_MASK,
128 BW_BUDDY2_CTL,
129 BW_BUDDY2_PAGE_MASK,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]130 WM_PIPE_C,
131 WM_LINETIME_A,
132 WM_LINETIME_B,
133 WM_LINETIME_C,
134 PWR_WELL_CTL_BIOS,
135 PWR_WELL_CTL_DRIVER,
136 PWR_WELL_CTL_KVMR,
137 PWR_WELL_CTL_DEBUG,
138 PWR_WELL_CTL5,
139 PWR_WELL_CTL6,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]140 PWR_AUX_CTL_BIOS,
141 PWR_AUX_CTL_DRIVER,
142 PWR_DDI_CTL_BIOS,
143 PWR_DDI_CTL_DRIVER,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]144 CDCLK_CTL,
145 LCPLL1_CTL,
146 LCPLL2_CTL,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]147 DPLL_4_ENABLE,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]148 SPLL_CTL,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]149 MGPLL1_ENABLE,
150 MGPLL2_ENABLE,
151 MGPLL3_ENABLE,
152 MGPLL4_ENABLE,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]153 WRPLL_CTL_1,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]154 MGPLL6_ENABLE,
155 PORTTC3_PLL1_ENABLE,
156 PORTTC4_PLL0_ENABLE,
157 PORTTC4_PLL1_ENABLE,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]158 WRPLL_CTL_2,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]159 BXT_DE_PLL_ENABLE,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]160 BXT_PORT_PLL_ENABLE_A,
161 BXT_PORT_PLL_ENABLE_B,
162 BXT_PORT_PLL_ENABLE_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]163 PORT_CLK_SEL_DDIA,
164 PORT_CLK_SEL_DDIB,
165 PORT_CLK_SEL_DDIC,
166 PORT_CLK_SEL_DDID,
167 PORT_CLK_SEL_DDIE,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]168 DDI_CLK_SEL_USBC3,
169 DDI_CLK_SEL_USBC4,
170 DDI_CLK_SEL_USBC5,
171 DDI_CLK_SEL_USBC6,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]172 TRANSA_CLK_SEL,
173 TRANSB_CLK_SEL,
174 TRANSC_CLK_SEL,
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]175 CDCLK_FREQ,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]176 NDE_RSTWRN_OPT,
Angel Ponsae186bd2020-10-21 21:37:34 +0200[diff] [blame]177 GEN8_CHICKEN_DCPR_1,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]178 GEN11_CHICKEN_DCPR_2,
179 GEN9_CLKGATE_DIS_0,
180 GEN9_CHICKEN_DPCR_3,
181 GEN9_CLKGATE_DIS_5,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]182 BLC_PWM_CPU_CTL2,
183 BLC_PWM_CPU_CTL,
Nico Huber6b4678d2019-09-22 21:31:52 +0200[diff] [blame]184 DFSM,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]185 DSSM,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]186 HTOTAL_A,
187 HBLANK_A,
188 HSYNC_A,
189 VTOTAL_A,
190 VBLANK_A,
191 VSYNC_A,
192 PIPEASRC,
193 PIPE_VSYNCSHIFT_A,
194 PIPEA_DATA_M1,
195 PIPEA_DATA_N1,
196 PIPEA_LINK_M1,
197 PIPEA_LINK_N1,
198 FDI_TX_CTL_A,
199 PIPEA_DDI_FUNC_CTL,
200 PIPEA_MSA_MISC,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]201 TGL_DP_TP_CTL_A,
202 TGL_DP_TP_STATUS_A,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]203 SRD_CTL_A,
204 SRD_STATUS_A,
205 HTOTAL_B,
206 HBLANK_B,
207 HSYNC_B,
208 VTOTAL_B,
209 VBLANK_B,
210 VSYNC_B,
211 PIPEBSRC,
212 PIPE_VSYNCSHIFT_B,
213 PIPEB_DATA_M1,
214 PIPEB_DATA_N1,
215 PIPEB_LINK_M1,
216 PIPEB_LINK_N1,
217 FDI_TX_CTL_B,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]218 PORT_HOTPLUG_EN,
219 PORT_HOTPLUG_STAT,
220 GMCH_SDVOB,
221 GMCH_SDVOC,
222 GMCH_LVDS,
Arthur Heymanse87d0d12018-03-28 17:02:49 +0200[diff] [blame]223 GMCH_PP_STATUS,
224 GMCH_PP_CONTROL,
225 GMCH_PP_ON_DELAYS,
226 GMCH_PP_OFF_DELAYS,
227 GMCH_PP_DIVISOR,
Arthur Heymansd5198442018-03-28 17:05:12 +0200[diff] [blame]228 GMCH_PFIT_CONTROL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]229 PIPEB_DDI_FUNC_CTL,
230 PIPEB_MSA_MISC,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]231 TGL_DP_TP_CTL_B,
232 TGL_DP_TP_STATUS_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]233 SRD_CTL_B,
234 SRD_STATUS_B,
235 HTOTAL_C,
236 HBLANK_C,
237 HSYNC_C,
238 VTOTAL_C,
239 VBLANK_C,
240 VSYNC_C,
241 PIPECSRC,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]242 G4X_AUD_VID_DID,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]243 PIPE_VSYNCSHIFT_C,
244 PIPEC_DATA_M1,
245 PIPEC_DATA_N1,
246 PIPEC_LINK_M1,
247 PIPEC_LINK_N1,
248 FDI_TX_CTL_C,
249 PIPEC_DDI_FUNC_CTL,
250 PIPEC_MSA_MISC,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]251 TGL_DP_TP_CTL_C,
252 TGL_DP_TP_STATUS_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]253 SRD_CTL_C,
254 SRD_STATUS_C,
255 DDI_BUF_CTL_A,
256 DDI_AUX_CTL_A,
257 DDI_AUX_DATA_A_1,
258 DDI_AUX_DATA_A_2,
259 DDI_AUX_DATA_A_3,
260 DDI_AUX_DATA_A_4,
261 DDI_AUX_DATA_A_5,
262 DDI_AUX_MUTEX_A,
263 DP_TP_CTL_A,
264 DDI_BUF_CTL_B,
265 DDI_AUX_CTL_B,
266 DDI_AUX_DATA_B_1,
267 DDI_AUX_DATA_B_2,
268 DDI_AUX_DATA_B_3,
269 DDI_AUX_DATA_B_4,
270 DDI_AUX_DATA_B_5,
271 DDI_AUX_MUTEX_B,
272 DP_TP_CTL_B,
273 DP_TP_STATUS_B,
274 DDI_BUF_CTL_C,
275 DDI_AUX_CTL_C,
276 DDI_AUX_DATA_C_1,
277 DDI_AUX_DATA_C_2,
278 DDI_AUX_DATA_C_3,
279 DDI_AUX_DATA_C_4,
280 DDI_AUX_DATA_C_5,
281 DDI_AUX_MUTEX_C,
282 DP_TP_CTL_C,
283 DP_TP_STATUS_C,
284 DDI_BUF_CTL_D,
285 DDI_AUX_CTL_D,
286 DDI_AUX_DATA_D_1,
287 DDI_AUX_DATA_D_2,
288 DDI_AUX_DATA_D_3,
289 DDI_AUX_DATA_D_4,
290 DDI_AUX_DATA_D_5,
291 DDI_AUX_MUTEX_D,
292 DP_TP_CTL_D,
293 DP_TP_STATUS_D,
294 DDI_BUF_CTL_E,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]295 DDI_AUX_CTL_USBC2,
296 DDI_AUX_DATA_USBC2_1,
297 DDI_AUX_DATA_USBC2_2,
298 DDI_AUX_DATA_USBC2_3,
299 DDI_AUX_DATA_USBC2_4,
300 DDI_AUX_DATA_USBC2_5,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]301 DP_TP_CTL_E,
302 DP_TP_STATUS_E,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]303 DDI_BUF_CTL_USBC3,
304 DDI_AUX_CTL_USBC3,
305 DDI_AUX_DATA_USBC3_1,
306 DDI_AUX_DATA_USBC3_2,
307 DDI_AUX_DATA_USBC3_3,
308 DDI_AUX_DATA_USBC3_4,
309 DDI_AUX_DATA_USBC3_5,
310 DDI_BUF_CTL_USBC4,
311 DDI_AUX_CTL_USBC4,
312 DDI_AUX_DATA_USBC4_1,
313 DDI_AUX_DATA_USBC4_2,
314 DDI_AUX_DATA_USBC4_3,
315 DDI_AUX_DATA_USBC4_4,
316 DDI_AUX_DATA_USBC4_5,
317 DDI_BUF_CTL_USBC5,
318 DDI_AUX_CTL_USBC5,
319 DDI_AUX_DATA_USBC5_1,
320 DDI_AUX_DATA_USBC5_2,
321 DDI_AUX_DATA_USBC5_3,
322 DDI_AUX_DATA_USBC5_4,
323 DDI_AUX_DATA_USBC5_5,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]324 SRD_CTL,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]325 DDI_AUX_CTL_USBC6,
326 DDI_AUX_DATA_USBC6_1,
327 DDI_AUX_DATA_USBC6_2,
328 DDI_AUX_DATA_USBC6_3,
329 DDI_AUX_DATA_USBC6_4,
330 DDI_AUX_DATA_USBC6_5,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]331 SRD_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]332 BXT_PHY_CTL_A,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]333 PHY_MISC_B,
334 PHY_MISC_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]335 BXT_PHY_CTL_B,
336 BXT_PHY_CTL_C,
337 BXT_PHY_CTL_FAM_EDP,
338 BXT_PHY_CTL_FAM_DDI,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]339 DDI_BUF_TRANS_A_S0T1,
340 DDI_BUF_TRANS_A_S0T2,
341 DDI_BUF_TRANS_A_S1T1,
342 DDI_BUF_TRANS_A_S1T2,
343 DDI_BUF_TRANS_A_S2T1,
344 DDI_BUF_TRANS_A_S2T2,
345 DDI_BUF_TRANS_A_S3T1,
346 DDI_BUF_TRANS_A_S3T2,
347 DDI_BUF_TRANS_A_S4T1,
348 DDI_BUF_TRANS_A_S4T2,
349 DDI_BUF_TRANS_A_S5T1,
350 DDI_BUF_TRANS_A_S5T2,
351 DDI_BUF_TRANS_A_S6T1,
352 DDI_BUF_TRANS_A_S6T2,
353 DDI_BUF_TRANS_A_S7T1,
354 DDI_BUF_TRANS_A_S7T2,
355 DDI_BUF_TRANS_A_S8T1,
356 DDI_BUF_TRANS_A_S8T2,
357 DDI_BUF_TRANS_A_S9T1,
358 DDI_BUF_TRANS_A_S9T2,
359 DDI_BUF_TRANS_B_S0T1,
360 DDI_BUF_TRANS_B_S0T2,
361 DDI_BUF_TRANS_B_S1T1,
362 DDI_BUF_TRANS_B_S1T2,
363 DDI_BUF_TRANS_B_S2T1,
364 DDI_BUF_TRANS_B_S2T2,
365 DDI_BUF_TRANS_B_S3T1,
366 DDI_BUF_TRANS_B_S3T2,
367 DDI_BUF_TRANS_B_S4T1,
368 DDI_BUF_TRANS_B_S4T2,
369 DDI_BUF_TRANS_B_S5T1,
370 DDI_BUF_TRANS_B_S5T2,
371 DDI_BUF_TRANS_B_S6T1,
372 DDI_BUF_TRANS_B_S6T2,
373 DDI_BUF_TRANS_B_S7T1,
374 DDI_BUF_TRANS_B_S7T2,
375 DDI_BUF_TRANS_B_S8T1,
376 DDI_BUF_TRANS_B_S8T2,
377 DDI_BUF_TRANS_B_S9T1,
378 DDI_BUF_TRANS_B_S9T2,
379 DDI_BUF_TRANS_C_S0T1,
380 DDI_BUF_TRANS_C_S0T2,
381 DDI_BUF_TRANS_C_S1T1,
382 DDI_BUF_TRANS_C_S1T2,
383 DDI_BUF_TRANS_C_S2T1,
384 DDI_BUF_TRANS_C_S2T2,
385 DDI_BUF_TRANS_C_S3T1,
386 DDI_BUF_TRANS_C_S3T2,
387 DDI_BUF_TRANS_C_S4T1,
388 DDI_BUF_TRANS_C_S4T2,
389 DDI_BUF_TRANS_C_S5T1,
390 DDI_BUF_TRANS_C_S5T2,
391 DDI_BUF_TRANS_C_S6T1,
392 DDI_BUF_TRANS_C_S6T2,
393 DDI_BUF_TRANS_C_S7T1,
394 DDI_BUF_TRANS_C_S7T2,
395 DDI_BUF_TRANS_C_S8T1,
396 DDI_BUF_TRANS_C_S8T2,
397 DDI_BUF_TRANS_C_S9T1,
398 DDI_BUF_TRANS_C_S9T2,
399 DDI_BUF_TRANS_D_S0T1,
400 DDI_BUF_TRANS_D_S0T2,
401 DDI_BUF_TRANS_D_S1T1,
402 DDI_BUF_TRANS_D_S1T2,
403 DDI_BUF_TRANS_D_S2T1,
404 DDI_BUF_TRANS_D_S2T2,
405 DDI_BUF_TRANS_D_S3T1,
406 DDI_BUF_TRANS_D_S3T2,
407 DDI_BUF_TRANS_D_S4T1,
408 DDI_BUF_TRANS_D_S4T2,
409 DDI_BUF_TRANS_D_S5T1,
410 DDI_BUF_TRANS_D_S5T2,
411 DDI_BUF_TRANS_D_S6T1,
412 DDI_BUF_TRANS_D_S6T2,
413 DDI_BUF_TRANS_D_S7T1,
414 DDI_BUF_TRANS_D_S7T2,
415 DDI_BUF_TRANS_D_S8T1,
416 DDI_BUF_TRANS_D_S8T2,
417 DDI_BUF_TRANS_D_S9T1,
418 DDI_BUF_TRANS_D_S9T2,
419 DDI_BUF_TRANS_E_S0T1,
420 DDI_BUF_TRANS_E_S0T2,
421 DDI_BUF_TRANS_E_S1T1,
422 DDI_BUF_TRANS_E_S1T2,
423 DDI_BUF_TRANS_E_S2T1,
424 DDI_BUF_TRANS_E_S2T2,
425 DDI_BUF_TRANS_E_S3T1,
426 DDI_BUF_TRANS_E_S3T2,
427 DDI_BUF_TRANS_E_S4T1,
428 DDI_BUF_TRANS_E_S4T2,
429 DDI_BUF_TRANS_E_S5T1,
430 DDI_BUF_TRANS_E_S5T2,
431 DDI_BUF_TRANS_E_S6T1,
432 DDI_BUF_TRANS_E_S6T2,
433 DDI_BUF_TRANS_E_S7T1,
434 DDI_BUF_TRANS_E_S7T2,
435 DDI_BUF_TRANS_E_S8T1,
436 DDI_BUF_TRANS_E_S8T2,
437 DDI_BUF_TRANS_E_S9T1,
438 DDI_BUF_TRANS_E_S9T2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]439 AUD_VID_DID,
440 PFA_WIN_POS,
441 PFA_WIN_SZ,
442 PFA_CTL_1,
443 PS_WIN_POS_1_A,
444 PS_WIN_SZ_1_A,
445 PS_CTRL_1_A,
446 PS_WIN_POS_2_A,
447 PS_WIN_SZ_2_A,
448 PS_CTRL_2_A,
449 PFB_WIN_POS,
450 PFB_WIN_SZ,
451 PFB_CTL_1,
452 PS_WIN_POS_1_B,
453 PS_WIN_SZ_1_B,
454 PS_CTRL_1_B,
455 PS_WIN_POS_2_B,
456 PS_WIN_SZ_2_B,
457 PS_CTRL_2_B,
458 PFC_WIN_POS,
459 PFC_WIN_SZ,
460 PFC_CTL_1,
461 PS_WIN_POS_1_C,
462 PS_WIN_SZ_1_C,
463 PS_CTRL_1_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]464 BXT_PORT_CL1CM_DW0_BC,
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]465 DISPIO_CR_TX_BMU_CR0,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]466 PORT_CL_DW5_B,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]467 BXT_PORT_CL1CM_DW9_BC,
468 BXT_PORT_CL1CM_DW10_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]469 BXT_PORT_PLL_EBB_0_B,
470 BXT_PORT_PLL_EBB_4_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]471 DPLL1_CFGR1,
472 DPLL1_CFGR2,
473 DPLL2_CFGR1,
474 DPLL2_CFGR2,
475 DPLL3_CFGR1,
476 DPLL3_CFGR2,
477 DPLL_CTRL1,
478 DPLL_CTRL2,
479 DPLL_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]480 BXT_PORT_CL1CM_DW28_BC,
481 BXT_PORT_CL1CM_DW30_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]482 BXT_PORT_PLL_0_B,
483 BXT_PORT_PLL_1_B,
484 BXT_PORT_PLL_2_B,
485 BXT_PORT_PLL_3_B,
486 BXT_PORT_PLL_6_B,
487 BXT_PORT_PLL_8_B,
488 BXT_PORT_PLL_9_B,
489 BXT_PORT_PLL_10_B,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]490 BXT_PORT_REF_DW3_BC,
491 BXT_PORT_REF_DW6_BC,
492 BXT_PORT_REF_DW8_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]493 BXT_PORT_PLL_EBB_0_C,
494 BXT_PORT_PLL_EBB_4_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]495 BXT_PORT_CL2CM_DW6_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]496 BXT_PORT_PLL_0_C,
497 BXT_PORT_PLL_1_C,
498 BXT_PORT_PLL_2_C,
499 BXT_PORT_PLL_3_C,
500 BXT_PORT_PLL_6_C,
501 BXT_PORT_PLL_8_C,
502 BXT_PORT_PLL_9_C,
503 BXT_PORT_PLL_10_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]504 BXT_PORT_PCS_DW10_01_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]505 BXT_PORT_PCS_DW12_01_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]506 BXT_PORT_TX_DW2_LN0_B,
507 BXT_PORT_TX_DW3_LN0_B,
508 BXT_PORT_TX_DW4_LN0_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]509 BXT_PORT_TX_DW14_LN0_B,
510 BXT_PORT_TX_DW14_LN1_B,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]511 PORT_PCS_DW1_GRP_B,
512 PORT_TX_DW2_GRP_B,
513 PORT_TX_DW4_GRP_B,
514 PORT_TX_DW5_GRP_B,
515 PORT_TX_DW7_GRP_B,
516 PORT_TX_DW8_GRP_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]517 BXT_PORT_TX_DW14_LN2_B,
518 BXT_PORT_TX_DW14_LN3_B,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]519 PORT_PCS_DW1_LN0_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]520 BXT_PORT_PCS_DW10_01_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]521 BXT_PORT_PCS_DW12_01_C,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]522 PORT_TX_DW2_LN0_B,
523 PORT_TX_DW4_LN0_B,
524 PORT_TX_DW5_LN0_B,
525 PORT_TX_DW7_LN0_B,
526 PORT_TX_DW8_LN0_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]527 BXT_PORT_TX_DW2_LN0_C,
528 BXT_PORT_TX_DW3_LN0_C,
529 BXT_PORT_TX_DW4_LN0_C,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]530 BXT_PORT_TX_DW14_LN0_C,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]531 PORT_TX_DW4_LN1_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]532 BXT_PORT_TX_DW14_LN1_C,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]533 PORT_TX_DW4_LN2_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]534 BXT_PORT_TX_DW14_LN2_C,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]535 PORT_TX_DW4_LN3_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]536 BXT_PORT_TX_DW14_LN3_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]537 BXT_PORT_PCS_DW10_GRP_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]538 BXT_PORT_PCS_DW12_GRP_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]539 BXT_PORT_TX_DW2_GRP_B,
540 BXT_PORT_TX_DW3_GRP_B,
541 BXT_PORT_TX_DW4_GRP_B,
542 BXT_PORT_PCS_DW10_GRP_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]543 BXT_PORT_PCS_DW12_GRP_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]544 BXT_PORT_TX_DW2_GRP_C,
545 BXT_PORT_TX_DW3_GRP_C,
546 BXT_PORT_TX_DW4_GRP_C,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]547 BXT_DE_PLL_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]548 HTOTAL_EDP,
549 HBLANK_EDP,
550 HSYNC_EDP,
551 VTOTAL_EDP,
552 VBLANK_EDP,
553 VSYNC_EDP,
554 PIPE_EDP_DATA_M1,
555 PIPE_EDP_DATA_N1,
556 PIPE_EDP_LINK_M1,
557 PIPE_EDP_LINK_N1,
558 PIPE_EDP_DDI_FUNC_CTL,
559 PIPE_EDP_MSA_MISC,
560 SRD_CTL_EDP,
561 SRD_STATUS_EDP,
562 PIPE_SCANLINE_A,
563 PIPEACONF,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]564 PIPEA_ARB_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]565 PIPEAMISC,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]566 PIPEA_CHICKEN,
567 PIPE_MBUS_DBOX_CTL_A,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]568 PIPE_FRMCNT_A,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]569 PIPEA_GMCH_DATA_M,
570 PIPEA_GMCH_DATA_N,
571 PIPEA_GMCH_LINK_M,
572 PIPEA_GMCH_LINK_N,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]573 CUR_CTL_A,
574 CUR_BASE_A,
575 CUR_POS_A,
576 CUR_FBC_CTL_A,
Nico Huber75a707f2018-06-18 16:28:33 +0200[diff] [blame]577 CURBCNTR,
578 CURBBASE,
579 CURBPOS,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]580 CUR_WM_A_0,
581 CUR_WM_A_1,
582 CUR_WM_A_2,
583 CUR_WM_A_3,
584 CUR_WM_A_4,
585 CUR_WM_A_5,
586 CUR_WM_A_6,
587 CUR_WM_A_7,
588 CUR_BUF_CFG_A,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]589 DSPACNTR,
590 DSPALINOFF,
591 DSPASTRIDE,
592 PLANE_POS_1_A,
593 PLANE_SIZE_1_A,
594 DSPASURF,
595 DSPATILEOFF,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]596 PLANE_AUX_DIST_1_A,
597 PLANE_COLOR_CTL_1_A,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]598 PLANE_WM_1_A_0,
599 PLANE_WM_1_A_1,
600 PLANE_WM_1_A_2,
601 PLANE_WM_1_A_3,
602 PLANE_WM_1_A_4,
603 PLANE_WM_1_A_5,
604 PLANE_WM_1_A_6,
605 PLANE_WM_1_A_7,
606 PLANE_BUF_CFG_1_A,
607 SPACNTR,
608 PIPE_SCANLINE_B,
609 PIPEBCONF,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]610 PIPEB_ARB_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]611 PIPEBMISC,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]612 PIPEB_CHICKEN,
613 PIPE_MBUS_DBOX_CTL_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]614 PIPE_FRMCNT_B,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]615 PIPEB_GMCH_DATA_M,
616 PIPEB_GMCH_DATA_N,
617 PIPEB_GMCH_LINK_M,
618 PIPEB_GMCH_LINK_N,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]619 CUR_CTL_B,
620 CUR_BASE_B,
621 CUR_POS_B,
622 CUR_FBC_CTL_B,
623 CUR_WM_B_0,
624 CUR_WM_B_1,
625 CUR_WM_B_2,
626 CUR_WM_B_3,
627 CUR_WM_B_4,
628 CUR_WM_B_5,
629 CUR_WM_B_6,
630 CUR_WM_B_7,
631 CUR_BUF_CFG_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]632 DSPBCNTR,
633 DSPBLINOFF,
634 DSPBSTRIDE,
635 PLANE_POS_1_B,
636 PLANE_SIZE_1_B,
637 DSPBSURF,
638 DSPBTILEOFF,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]639 PLANE_AUX_DIST_1_B,
640 PLANE_COLOR_CTL_1_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]641 PLANE_WM_1_B_0,
642 PLANE_WM_1_B_1,
643 PLANE_WM_1_B_2,
644 PLANE_WM_1_B_3,
645 PLANE_WM_1_B_4,
646 PLANE_WM_1_B_5,
647 PLANE_WM_1_B_6,
648 PLANE_WM_1_B_7,
649 PLANE_BUF_CFG_1_B,
650 SPBCNTR,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]651 GMCH_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]652 PIPE_SCANLINE_C,
653 PIPECCONF,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]654 PIPEC_ARB_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]655 PIPECMISC,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]656 PIPEC_CHICKEN,
657 PIPE_MBUS_DBOX_CTL_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]658 PIPE_FRMCNT_C,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]659 CUR_CTL_C,
660 CUR_BASE_C,
661 CUR_POS_C,
662 CUR_FBC_CTL_C,
663 CUR_WM_C_0,
664 CUR_WM_C_1,
665 CUR_WM_C_2,
666 CUR_WM_C_3,
667 CUR_WM_C_4,
668 CUR_WM_C_5,
669 CUR_WM_C_6,
670 CUR_WM_C_7,
671 CUR_BUF_CFG_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]672 DSPCCNTR,
673 DSPCLINOFF,
674 DSPCSTRIDE,
675 PLANE_POS_1_C,
676 PLANE_SIZE_1_C,
677 DSPCSURF,
678 DSPCTILEOFF,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]679 PLANE_AUX_DIST_1_C,
680 PLANE_COLOR_CTL_1_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]681 PLANE_WM_1_C_0,
682 PLANE_WM_1_C_1,
683 PLANE_WM_1_C_2,
684 PLANE_WM_1_C_3,
685 PLANE_WM_1_C_4,
686 PLANE_WM_1_C_5,
687 PLANE_WM_1_C_6,
688 PLANE_WM_1_C_7,
689 PLANE_BUF_CFG_1_C,
690 SPCCNTR,
691 PIPE_EDP_CONF,
692 PCH_FDI_CHICKEN_B_C,
693 QUIRK_C2004,
694 SFUSE_STRAP,
695 PCH_DSPCLK_GATE_D,
696 SDEISR,
697 SDEIMR,
698 SDEIIR,
699 SDEIER,
700 SHOTPLUG_CTL,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]701 SHOTPLUG_CTL_TC,
702 SHPD_FILTER_CNT,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]703 PCH_GMBUS0,
704 PCH_GMBUS1,
705 PCH_GMBUS2,
706 PCH_GMBUS3,
707 PCH_GMBUS4,
708 PCH_GMBUS5,
709 SBI_ADDR,
710 SBI_DATA,
711 SBI_CTL_STAT,
712 PCH_DPLL_A,
713 PCH_DPLL_B,
714 PCH_PIXCLK_GATE,
715 PCH_FPA0,
716 PCH_FPA1,
717 PCH_FPB0,
718 PCH_FPB1,
719 PCH_DREF_CONTROL,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]720 PCH_RAWCLK_FREQ,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]721 PCH_DPLL_SEL,
722 PCH_PP_STATUS,
723 PCH_PP_CONTROL,
724 PCH_PP_ON_DELAYS,
725 PCH_PP_OFF_DELAYS,
726 PCH_PP_DIVISOR,
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]727 BXT_PP_STATUS_2,
728 BXT_PP_CONTROL_2,
729 BXT_PP_ON_DELAYS_2,
730 BXT_PP_OFF_DELAYS_2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]731 BLC_PWM_PCH_CTL1,
732 BLC_PWM_PCH_CTL2,
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]733 BXT_BLC_PWM_DUTY_1,
734 BXT_BLC_PWM_CTL_2,
735 BXT_BLC_PWM_FREQ_2,
736 BXT_BLC_PWM_DUTY_2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]737 TRANS_HTOTAL_A,
738 TRANS_HBLANK_A,
739 TRANS_HSYNC_A,
740 TRANS_VTOTAL_A,
741 TRANS_VBLANK_A,
742 TRANS_VSYNC_A,
743 TRANS_VSYNCSHIFT_A,
744 TRANSA_DATA_M1,
745 TRANSA_DATA_N1,
746 TRANSA_DP_LINK_M1,
747 TRANSA_DP_LINK_N1,
748 TRANS_DP_CTL_A,
749 TRANS_HTOTAL_B,
750 TRANS_HBLANK_B,
751 TRANS_HSYNC_B,
752 TRANS_VTOTAL_B,
753 TRANS_VBLANK_B,
754 TRANS_VSYNC_B,
755 TRANS_VSYNCSHIFT_B,
756 TRANSB_DATA_M1,
757 TRANSB_DATA_N1,
758 TRANSB_DP_LINK_M1,
759 TRANSB_DP_LINK_N1,
760 PCH_ADPA,
761 PCH_HDMIB,
762 PCH_HDMIC,
763 PCH_HDMID,
764 PCH_LVDS,
765 TRANS_DP_CTL_B,
766 TRANS_HTOTAL_C,
767 TRANS_HBLANK_C,
768 TRANS_HSYNC_C,
769 TRANS_VTOTAL_C,
770 TRANS_VBLANK_C,
771 TRANS_VSYNC_C,
772 TRANS_VSYNCSHIFT_C,
773 TRANSC_DATA_M1,
774 TRANSC_DATA_N1,
775 TRANSC_DP_LINK_M1,
776 TRANSC_DP_LINK_N1,
777 TRANS_DP_CTL_C,
778 PCH_DP_B,
779 PCH_DP_AUX_CTL_B,
780 PCH_DP_AUX_DATA_B_1,
781 PCH_DP_AUX_DATA_B_2,
782 PCH_DP_AUX_DATA_B_3,
783 PCH_DP_AUX_DATA_B_4,
784 PCH_DP_AUX_DATA_B_5,
785 PCH_DP_C,
786 PCH_DP_AUX_CTL_C,
787 PCH_DP_AUX_DATA_C_1,
788 PCH_DP_AUX_DATA_C_2,
789 PCH_DP_AUX_DATA_C_3,
790 PCH_DP_AUX_DATA_C_4,
791 PCH_DP_AUX_DATA_C_5,
792 PCH_DP_D,
793 PCH_DP_AUX_CTL_D,
794 PCH_DP_AUX_DATA_D_1,
795 PCH_DP_AUX_DATA_D_2,
796 PCH_DP_AUX_DATA_D_3,
797 PCH_DP_AUX_DATA_D_4,
798 PCH_DP_AUX_DATA_D_5,
799 AUD_CONFIG_A,
800 PCH_AUD_VID_DID,
801 AUD_HDMIW_HDMIEDID_A,
802 AUD_CNTL_ST_A,
803 AUD_CNTRL_ST2,
804 AUD_CONFIG_B,
805 AUD_HDMIW_HDMIEDID_B,
806 AUD_CNTL_ST_B,
807 AUD_CONFIG_C,
808 AUD_HDMIW_HDMIEDID_C,
809 AUD_CNTL_ST_C,
810 TRANSACONF,
811 FDI_RXA_CTL,
812 FDI_RX_MISC_A,
813 FDI_RXA_IIR,
814 FDI_RXA_IMR,
815 FDI_RXA_TUSIZE1,
816 QUIRK_F0060,
817 TRANSA_CHICKEN2,
818 TRANSBCONF,
819 FDI_RXB_CTL,
820 FDI_RX_MISC_B,
821 FDI_RXB_IIR,
822 FDI_RXB_IMR,
823 FDI_RXB_TUSIZE1,
824 QUIRK_F1060,
825 TRANSB_CHICKEN2,
826 TRANSCCONF,
827 FDI_RXC_CTL,
828 FDI_RX_MISC_C,
829 FDI_RXC_IIR,
830 FDI_RXC_IMR,
831 FDI_RXC_TUSIZE1,
832 QUIRK_F2060,
833 TRANSC_CHICKEN2,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]834 HIP_INDEX_REG0,
835 HIP_INDEX_REG1,
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]836 LCPLL_CTL,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]837 BXT_P_CR_GT_DISP_PWRON,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]838 GT_MAILBOX,
839 GT_MAILBOX_DATA,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]840 GT_MAILBOX_DATA_1,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]841 PORT_CL_DW5_C,
842 PORT_CL_DW10_C,
843 PORT_COMP_DW0_C,
844 PORT_COMP_DW1_C,
845 PORT_COMP_DW3_C,
846 PORT_COMP_DW8_C,
847 PORT_COMP_DW9_C,
848 PORT_COMP_DW10_C,
849 PORT_PCS_DW1_GRP_C,
850 PORT_TX_DW2_GRP_C,
851 PORT_TX_DW4_GRP_C,
852 PORT_TX_DW5_GRP_C,
853 PORT_TX_DW7_GRP_C,
854 PORT_TX_DW8_GRP_C,
855 PORT_PCS_DW1_LN0_C,
856 PORT_TX_DW2_LN0_C,
857 PORT_TX_DW4_LN0_C,
858 PORT_TX_DW5_LN0_C,
859 PORT_TX_DW7_LN0_C,
860 PORT_TX_DW8_LN0_C,
861 PORT_TX_DW4_LN1_C,
862 PORT_TX_DW4_LN2_C,
863 PORT_TX_DW4_LN3_C,
864 TCSS_DDI_STATUS_1,
865 TCSS_DDI_STATUS_2,
866 TCSS_DDI_STATUS_3,
867 TCSS_DDI_STATUS_4,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]868 BXT_PORT_CL1CM_DW0_A,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]869 PORT_CL_DW5_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]870 BXT_PORT_CL1CM_DW9_A,
871 BXT_PORT_CL1CM_DW10_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]872 BXT_PORT_PLL_EBB_0_A,
873 BXT_PORT_PLL_EBB_4_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]874 BXT_PORT_CL1CM_DW28_A,
875 BXT_PORT_CL1CM_DW30_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]876 BXT_PORT_PLL_0_A,
877 BXT_PORT_PLL_1_A,
878 BXT_PORT_PLL_2_A,
879 BXT_PORT_PLL_3_A,
880 BXT_PORT_PLL_6_A,
881 BXT_PORT_PLL_8_A,
882 BXT_PORT_PLL_9_A,
883 BXT_PORT_PLL_10_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]884 BXT_PORT_REF_DW3_A,
885 BXT_PORT_REF_DW6_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]886 BXT_PORT_REF_DW8_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]887 BXT_PORT_PCS_DW10_01_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]888 BXT_PORT_PCS_DW12_01_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]889 BXT_PORT_TX_DW2_LN0_A,
890 BXT_PORT_TX_DW3_LN0_A,
891 BXT_PORT_TX_DW4_LN0_A,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]892 BXT_PORT_TX_DW14_LN0_A,
893 BXT_PORT_TX_DW14_LN1_A,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]894 PORT_PCS_DW1_GRP_A,
895 PORT_TX_DW2_GRP_A,
896 PORT_TX_DW4_GRP_A,
897 PORT_TX_DW5_GRP_A,
898 PORT_TX_DW7_GRP_A,
899 PORT_TX_DW8_GRP_A,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]900 BXT_PORT_TX_DW14_LN2_A,
901 BXT_PORT_TX_DW14_LN3_A,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]902 PORT_PCS_DW1_LN0_A,
903 PORT_TX_DW2_LN0_A,
904 PORT_TX_DW4_LN0_A,
905 PORT_TX_DW5_LN0_A,
906 PORT_TX_DW7_LN0_A,
907 PORT_TX_DW8_LN0_A,
908 PORT_TX_DW4_LN1_A,
909 PORT_TX_DW4_LN2_A,
910 PORT_TX_DW4_LN3_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]911 BXT_PORT_PCS_DW10_GRP_A,
912 BXT_PORT_PCS_DW12_GRP_A,
913 BXT_PORT_TX_DW2_GRP_A,
914 BXT_PORT_TX_DW3_GRP_A,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]915 BXT_PORT_TX_DW4_GRP_A,
916 PORT_TX_DFLEXPA1_FIA1,
917 PORT_TX_DFLEXDPPMS_FIA1,
918 PORT_TX_DFLEXDPCSSS_FIA1,
919 PORT_TX_DFLEXDPSP_FIA1,
920 PORT_TX_DFLEXDPMLE1_FIA1,
921 DPCLKA_CFGCR0,
922 DPLL_0_CFGCR0,
923 DPLL_0_CFGCR1,
924 DPLL_1_CFGCR0,
925 DPLL_1_CFGCR1,
926 DPLL_4_CFGCR0,
927 DPLL_4_CFGCR1,
928 DPLL_0_SSC,
929 DPLL_1_SSC,
930 DPLL_4_SSC,
931 DKL_PCS_DW5_1,
932 DKL_DP_MODE_1,
933 DKL_CLKTOP2_HSCC_1,
934 DKL_CLKTOP2_CCC1_1,
935 DKL_REFCLKIN_CTL_1,
936 DKL_PLL_DIV0_1,
937 DKL_PLL_DIV1_1,
938 DKL_PLL_SSC_1,
939 DKL_PLL_BIAS_1,
940 DKL_PLL_COLDST_BIAS_1,
941 DKL_TX_DPCNTL0_1,
942 DKL_TX_DPCNTL1_1,
943 DKL_TX_DPCNTL2_1,
944 DKL_CMN_UC_DW_27_1,
945 DKL_TX_PMD_LANE_SUS_1,
946 DKL_PCS_DW5_2,
947 DKL_DP_MODE_2,
948 DKL_CLKTOP2_HSCC_2,
949 DKL_CLKTOP2_CCC1_2,
950 DKL_REFCLKIN_CTL_2,
951 DKL_PLL_DIV0_2,
952 DKL_PLL_DIV1_2,
953 DKL_PLL_SSC_2,
954 DKL_PLL_BIAS_2,
955 DKL_PLL_COLDST_BIAS_2,
956 DKL_TX_DPCNTL0_2,
957 DKL_TX_DPCNTL1_2,
958 DKL_TX_DPCNTL2_2,
959 DKL_CMN_UC_DW_27_2,
960 DKL_TX_PMD_LANE_SUS_2,
961 DKL_PCS_DW5_3,
962 DKL_DP_MODE_3,
963 DKL_CLKTOP2_HSCC_3,
964 DKL_CLKTOP2_CCC1_3,
965 DKL_REFCLKIN_CTL_3,
966 DKL_PLL_DIV0_3,
967 DKL_PLL_DIV1_3,
968 DKL_PLL_SSC_3,
969 DKL_PLL_BIAS_3,
970 DKL_PLL_COLDST_BIAS_3,
971 DKL_TX_DPCNTL0_3,
972 DKL_TX_DPCNTL1_3,
973 DKL_TX_DPCNTL2_3,
974 DKL_CMN_UC_DW_27_3,
975 DKL_TX_PMD_LANE_SUS_3,
976 DKL_PCS_DW5_4,
977 DKL_DP_MODE_4,
978 DKL_CLKTOP2_HSCC_4,
979 DKL_CLKTOP2_CCC1_4,
980 DKL_REFCLKIN_CTL_4,
981 DKL_PLL_DIV0_4,
982 DKL_PLL_DIV1_4,
983 DKL_PLL_SSC_4,
984 DKL_PLL_BIAS_4,
985 DKL_PLL_COLDST_BIAS_4,
986 DKL_TX_DPCNTL0_4,
987 DKL_TX_DPCNTL1_4,
988 DKL_TX_DPCNTL2_4,
989 DKL_CMN_UC_DW_27_4,
990 DKL_TX_PMD_LANE_SUS_4,
991 DKL_DP_MODE_5,
992 DKL_CLKTOP2_HSCC_5,
993 DKL_CLKTOP2_CCC1_5,
994 DKL_REFCLKIN_CTL_5,
995 DKL_PLL_DIV0_5,
996 DKL_PLL_DIV1_5,
997 DKL_PLL_SSC_5,
998 DKL_PLL_BIAS_5,
999 DKL_PLL_COLDST_BIAS_5,
1000 DKL_TX_DPCNTL0_5,
1001 DKL_TX_DPCNTL1_5,
1002 DKL_TX_DPCNTL2_5,
1003 DKL_CMN_UC_DW_27_5,
1004 DKL_TX_PMD_LANE_SUS_5,
1005 DKL_DP_MODE_6,
1006 DKL_CLKTOP2_HSCC_6,
1007 DKL_CLKTOP2_CCC1_6,
1008 DKL_REFCLKIN_CTL_6,
1009 DKL_PLL_DIV0_6,
1010 DKL_PLL_DIV1_6,
1011 DKL_PLL_SSC_6,
1012 DKL_PLL_BIAS_6,
1013 DKL_PLL_COLDST_BIAS_6,
1014 DKL_TX_DPCNTL0_6,
1015 DKL_TX_DPCNTL1_6,
1016 DKL_TX_DPCNTL2_6,
1017 DKL_CMN_UC_DW_27_6,
1018 DKL_TX_PMD_LANE_SUS_6,
1019 PORT_TX_DFLEXPA1_FIA2,
1020 PORT_TX_DFLEXDPPMS_FIA2,
1021 PORT_TX_DFLEXDPCSSS_FIA2,
1022 PORT_TX_DFLEXDPSP_FIA2,
1023 PORT_TX_DFLEXDPMLE1_FIA2,
1024 PORT_TX_DFLEXPA1_FIA3,
1025 PORT_TX_DFLEXDPPMS_FIA3,
1026 PORT_TX_DFLEXDPCSSS_FIA3,
1027 PORT_TX_DFLEXDPSP_FIA3,
1028 PORT_TX_DFLEXDPMLE1_FIA3);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1029 pragma Warnings
1030 (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)",
1031 Reason => "TODO: Should it matter?");
1032 pragma Keep_Names (Registers_Invalid_Index);
1033 pragma Warnings
1034 (GNATprove, On, "pragma ""KEEP_NAMES"" ignored *(not yet supported)");
1035
1036 Register_Width : constant := 4;
1037
1038 for Registers_Invalid_Index use
1039 (Invalid_Register => 0,
1040
1041 ---------------------------------------------------------------------------
1042 -- Pipe A registers
1043 ---------------------------------------------------------------------------
1044
1045 -- pipe timing registers
1046
1047 HTOTAL_A => 16#06_0000# / Register_Width,
1048 HBLANK_A => 16#06_0004# / Register_Width,
1049 HSYNC_A => 16#06_0008# / Register_Width,
1050 VTOTAL_A => 16#06_000c# / Register_Width,
1051 VBLANK_A => 16#06_0010# / Register_Width,
1052 VSYNC_A => 16#06_0014# / Register_Width,
1053 PIPEASRC => 16#06_001c# / Register_Width,
1054 PIPEACONF => 16#07_0008# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1055 PIPEA_ARB_CTL => 16#07_0028# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1056 PIPEAMISC => 16#07_0030# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1057 PIPEA_CHICKEN => 16#07_0038# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1058 TRANS_HTOTAL_A => 16#0e_0000# / Register_Width,
1059 TRANS_HBLANK_A => 16#0e_0004# / Register_Width,
1060 TRANS_HSYNC_A => 16#0e_0008# / Register_Width,
1061 TRANS_VTOTAL_A => 16#0e_000c# / Register_Width,
1062 TRANS_VBLANK_A => 16#0e_0010# / Register_Width,
1063 TRANS_VSYNC_A => 16#0e_0014# / Register_Width,
1064 TRANSA_DATA_M1 => 16#0e_0030# / Register_Width,
1065 TRANSA_DATA_N1 => 16#0e_0034# / Register_Width,
1066 TRANSA_DP_LINK_M1 => 16#0e_0040# / Register_Width,
1067 TRANSA_DP_LINK_N1 => 16#0e_0044# / Register_Width,
1068 PIPEA_DATA_M1 => 16#06_0030# / Register_Width,
1069 PIPEA_DATA_N1 => 16#06_0034# / Register_Width,
1070 PIPEA_LINK_M1 => 16#06_0040# / Register_Width,
1071 PIPEA_LINK_N1 => 16#06_0044# / Register_Width,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]1072 PIPEA_GMCH_DATA_M => 16#07_0050# / Register_Width,
1073 PIPEA_GMCH_DATA_N => 16#07_0054# / Register_Width,
1074 PIPEA_GMCH_LINK_M => 16#07_0060# / Register_Width,
1075 PIPEA_GMCH_LINK_N => 16#07_0064# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1076 PIPEA_DDI_FUNC_CTL => 16#06_0400# / Register_Width,
1077 PIPEA_MSA_MISC => 16#06_0410# / Register_Width,
1078
1079 -- PCH sideband interface registers
1080 SBI_ADDR => 16#0c_6000# / Register_Width,
1081 SBI_DATA => 16#0c_6004# / Register_Width,
1082 SBI_CTL_STAT => 16#0c_6008# / Register_Width,
1083
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1084 -- GMCH clock registers
1085 GMCH_DPLL_A => 16#00_6014# / Register_Width,
1086 GMCH_FPA0 => 16#00_6040# / Register_Width,
1087 GMCH_FPA1 => 16#00_6044# / Register_Width,
1088
1089 -- PCH clock registers
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1090 PCH_DPLL_A => 16#0c_6014# / Register_Width,
1091 PCH_PIXCLK_GATE => 16#0c_6020# / Register_Width,
1092 PCH_FPA0 => 16#0c_6040# / Register_Width,
1093 PCH_FPA1 => 16#0c_6044# / Register_Width,
1094
1095 -- panel fitter
1096 PFA_CTL_1 => 16#06_8080# / Register_Width,
1097 PFA_WIN_POS => 16#06_8070# / Register_Width,
1098 PFA_WIN_SZ => 16#06_8074# / Register_Width,
1099 PS_WIN_POS_1_A => 16#06_8170# / Register_Width,
1100 PS_WIN_SZ_1_A => 16#06_8174# / Register_Width,
1101 PS_CTRL_1_A => 16#06_8180# / Register_Width,
1102 PS_WIN_POS_2_A => 16#06_8270# / Register_Width,
1103 PS_WIN_SZ_2_A => 16#06_8274# / Register_Width,
1104 PS_CTRL_2_A => 16#06_8280# / Register_Width,
1105
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1106 -- cursor control
1107 CUR_CTL_A => 16#07_0080# / Register_Width,
1108 CUR_BASE_A => 16#07_0084# / Register_Width,
1109 CUR_POS_A => 16#07_0088# / Register_Width,
1110 CUR_FBC_CTL_A => 16#07_00a0# / Register_Width,
1111
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1112 -- display control
1113 DSPACNTR => 16#07_0180# / Register_Width,
1114 DSPALINOFF => 16#07_0184# / Register_Width,
1115 DSPASTRIDE => 16#07_0188# / Register_Width,
1116 PLANE_POS_1_A => 16#07_018c# / Register_Width,
1117 PLANE_SIZE_1_A => 16#07_0190# / Register_Width,
1118 DSPASURF => 16#07_019c# / Register_Width,
1119 DSPATILEOFF => 16#07_01a4# / Register_Width,
1120
1121 -- sprite control
1122 SPACNTR => 16#07_0280# / Register_Width,
1123
1124 -- FDI and PCH transcoder control
1125 FDI_TX_CTL_A => 16#06_0100# / Register_Width,
1126 FDI_RXA_CTL => 16#0f_000c# / Register_Width,
1127 FDI_RX_MISC_A => 16#0f_0010# / Register_Width,
1128 FDI_RXA_IIR => 16#0f_0014# / Register_Width,
1129 FDI_RXA_IMR => 16#0f_0018# / Register_Width,
1130 FDI_RXA_TUSIZE1 => 16#0f_0030# / Register_Width,
1131 TRANSACONF => 16#0f_0008# / Register_Width,
1132 TRANSA_CHICKEN2 => 16#0f_0064# / Register_Width,
1133
1134 -- watermark registers
1135 WM_LINETIME_A => 16#04_5270# / Register_Width,
1136 PLANE_WM_1_A_0 => 16#07_0240# / Register_Width,
1137 PLANE_WM_1_A_1 => 16#07_0244# / Register_Width,
1138 PLANE_WM_1_A_2 => 16#07_0248# / Register_Width,
1139 PLANE_WM_1_A_3 => 16#07_024c# / Register_Width,
1140 PLANE_WM_1_A_4 => 16#07_0250# / Register_Width,
1141 PLANE_WM_1_A_5 => 16#07_0254# / Register_Width,
1142 PLANE_WM_1_A_6 => 16#07_0258# / Register_Width,
1143 PLANE_WM_1_A_7 => 16#07_025c# / Register_Width,
1144 PLANE_BUF_CFG_1_A => 16#07_027c# / Register_Width,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1145 CUR_WM_A_0 => 16#07_0140# / Register_Width,
1146 CUR_WM_A_1 => 16#07_0144# / Register_Width,
1147 CUR_WM_A_2 => 16#07_0148# / Register_Width,
1148 CUR_WM_A_3 => 16#07_014c# / Register_Width,
1149 CUR_WM_A_4 => 16#07_0150# / Register_Width,
1150 CUR_WM_A_5 => 16#07_0154# / Register_Width,
1151 CUR_WM_A_6 => 16#07_0158# / Register_Width,
1152 CUR_WM_A_7 => 16#07_015c# / Register_Width,
1153 CUR_BUF_CFG_A => 16#07_017c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1154
1155 -- CPU transcoder clock select
1156 TRANSA_CLK_SEL => 16#04_6140# / Register_Width,
1157
1158 ---------------------------------------------------------------------------
1159 -- Pipe B registers
1160 ---------------------------------------------------------------------------
1161
1162 -- pipe timing registers
1163
1164 HTOTAL_B => 16#06_1000# / Register_Width,
1165 HBLANK_B => 16#06_1004# / Register_Width,
1166 HSYNC_B => 16#06_1008# / Register_Width,
1167 VTOTAL_B => 16#06_100c# / Register_Width,
1168 VBLANK_B => 16#06_1010# / Register_Width,
1169 VSYNC_B => 16#06_1014# / Register_Width,
1170 PIPEBSRC => 16#06_101c# / Register_Width,
1171 PIPEBCONF => 16#07_1008# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1172 PIPEB_ARB_CTL => 16#07_1028# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1173 PIPEBMISC => 16#07_1030# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1174 PIPEB_CHICKEN => 16#07_1038# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1175 TRANS_HTOTAL_B => 16#0e_1000# / Register_Width,
1176 TRANS_HBLANK_B => 16#0e_1004# / Register_Width,
1177 TRANS_HSYNC_B => 16#0e_1008# / Register_Width,
1178 TRANS_VTOTAL_B => 16#0e_100c# / Register_Width,
1179 TRANS_VBLANK_B => 16#0e_1010# / Register_Width,
1180 TRANS_VSYNC_B => 16#0e_1014# / Register_Width,
1181 TRANSB_DATA_M1 => 16#0e_1030# / Register_Width,
1182 TRANSB_DATA_N1 => 16#0e_1034# / Register_Width,
1183 TRANSB_DP_LINK_M1 => 16#0e_1040# / Register_Width,
1184 TRANSB_DP_LINK_N1 => 16#0e_1044# / Register_Width,
1185 PIPEB_DATA_M1 => 16#06_1030# / Register_Width,
1186 PIPEB_DATA_N1 => 16#06_1034# / Register_Width,
1187 PIPEB_LINK_M1 => 16#06_1040# / Register_Width,
1188 PIPEB_LINK_N1 => 16#06_1044# / Register_Width,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]1189 PIPEB_GMCH_DATA_M => 16#07_1050# / Register_Width,
1190 PIPEB_GMCH_DATA_N => 16#07_1054# / Register_Width,
1191 PIPEB_GMCH_LINK_M => 16#07_1060# / Register_Width,
1192 PIPEB_GMCH_LINK_N => 16#07_1064# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1193 PIPEB_DDI_FUNC_CTL => 16#06_1400# / Register_Width,
1194 PIPEB_MSA_MISC => 16#06_1410# / Register_Width,
1195
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1196 -- GMCH clock registers
1197 GMCH_DPLL_B => 16#00_6018# / Register_Width,
1198 GMCH_FPB0 => 16#00_6048# / Register_Width,
1199 GMCH_FPB1 => 16#00_604c# / Register_Width,
1200
1201 -- PCH clock registers
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1202 PCH_DPLL_B => 16#0c_6018# / Register_Width,
1203 PCH_FPB0 => 16#0c_6048# / Register_Width,
1204 PCH_FPB1 => 16#0c_604c# / Register_Width,
1205
1206 -- panel fitter
1207 PFB_CTL_1 => 16#06_8880# / Register_Width,
1208 PFB_WIN_POS => 16#06_8870# / Register_Width,
1209 PFB_WIN_SZ => 16#06_8874# / Register_Width,
1210 PS_WIN_POS_1_B => 16#06_8970# / Register_Width,
1211 PS_WIN_SZ_1_B => 16#06_8974# / Register_Width,
1212 PS_CTRL_1_B => 16#06_8980# / Register_Width,
1213 PS_WIN_POS_2_B => 16#06_8a70# / Register_Width,
1214 PS_WIN_SZ_2_B => 16#06_8a74# / Register_Width,
1215 PS_CTRL_2_B => 16#06_8a80# / Register_Width,
1216
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1217 -- cursor control
Nico Huber75a707f2018-06-18 16:28:33 +0200[diff] [blame]1218 CURBCNTR => 16#07_00c0# / Register_Width, -- <= SNB
1219 CURBBASE => 16#07_00c4# / Register_Width, -- <= SNB
1220 CURBPOS => 16#07_00c8# / Register_Width, -- <= SNB
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1221 CUR_CTL_B => 16#07_1080# / Register_Width,
1222 CUR_BASE_B => 16#07_1084# / Register_Width,
1223 CUR_POS_B => 16#07_1088# / Register_Width,
1224 CUR_FBC_CTL_B => 16#07_10a0# / Register_Width,
1225
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1226 -- display control
1227 DSPBCNTR => 16#07_1180# / Register_Width,
1228 DSPBLINOFF => 16#07_1184# / Register_Width,
1229 DSPBSTRIDE => 16#07_1188# / Register_Width,
1230 PLANE_POS_1_B => 16#07_118c# / Register_Width,
1231 PLANE_SIZE_1_B => 16#07_1190# / Register_Width,
1232 DSPBSURF => 16#07_119c# / Register_Width,
1233 DSPBTILEOFF => 16#07_11a4# / Register_Width,
1234
1235 -- sprite control
1236 SPBCNTR => 16#07_1280# / Register_Width,
1237
1238 -- FDI and PCH transcoder control
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1239 FDI_TX_CTL_B => 16#06_1100# / Register_Width, -- aliased by GMCH_ADPA
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1240 FDI_RXB_CTL => 16#0f_100c# / Register_Width,
1241 FDI_RX_MISC_B => 16#0f_1010# / Register_Width,
1242 FDI_RXB_IIR => 16#0f_1014# / Register_Width,
1243 FDI_RXB_IMR => 16#0f_1018# / Register_Width,
1244 FDI_RXB_TUSIZE1 => 16#0f_1030# / Register_Width,
1245 TRANSBCONF => 16#0f_1008# / Register_Width,
1246 TRANSB_CHICKEN2 => 16#0f_1064# / Register_Width,
1247
1248 -- watermark registers
1249 WM_LINETIME_B => 16#04_5274# / Register_Width,
1250 PLANE_WM_1_B_0 => 16#07_1240# / Register_Width,
1251 PLANE_WM_1_B_1 => 16#07_1244# / Register_Width,
1252 PLANE_WM_1_B_2 => 16#07_1248# / Register_Width,
1253 PLANE_WM_1_B_3 => 16#07_124c# / Register_Width,
1254 PLANE_WM_1_B_4 => 16#07_1250# / Register_Width,
1255 PLANE_WM_1_B_5 => 16#07_1254# / Register_Width,
1256 PLANE_WM_1_B_6 => 16#07_1258# / Register_Width,
1257 PLANE_WM_1_B_7 => 16#07_125c# / Register_Width,
1258 PLANE_BUF_CFG_1_B => 16#07_127c# / Register_Width,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1259 CUR_WM_B_0 => 16#07_1140# / Register_Width,
1260 CUR_WM_B_1 => 16#07_1144# / Register_Width,
1261 CUR_WM_B_2 => 16#07_1148# / Register_Width,
1262 CUR_WM_B_3 => 16#07_114c# / Register_Width,
1263 CUR_WM_B_4 => 16#07_1150# / Register_Width,
1264 CUR_WM_B_5 => 16#07_1154# / Register_Width,
1265 CUR_WM_B_6 => 16#07_1158# / Register_Width,
1266 CUR_WM_B_7 => 16#07_115c# / Register_Width,
1267 CUR_BUF_CFG_B => 16#07_117c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1268
1269 -- CPU transcoder clock select
1270 TRANSB_CLK_SEL => 16#04_6144# / Register_Width,
1271
1272 ---------------------------------------------------------------------------
1273 -- Pipe C registers
1274 ---------------------------------------------------------------------------
1275
1276 -- pipe timing registers
1277
1278 HTOTAL_C => 16#06_2000# / Register_Width,
1279 HBLANK_C => 16#06_2004# / Register_Width,
1280 HSYNC_C => 16#06_2008# / Register_Width,
1281 VTOTAL_C => 16#06_200c# / Register_Width,
1282 VBLANK_C => 16#06_2010# / Register_Width,
1283 VSYNC_C => 16#06_2014# / Register_Width,
1284 PIPECSRC => 16#06_201c# / Register_Width,
1285 PIPECCONF => 16#07_2008# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1286 PIPEC_ARB_CTL => 16#07_2028# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1287 PIPECMISC => 16#07_2030# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1288 PIPEC_CHICKEN => 16#07_2038# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1289 TRANS_HTOTAL_C => 16#0e_2000# / Register_Width,
1290 TRANS_HBLANK_C => 16#0e_2004# / Register_Width,
1291 TRANS_HSYNC_C => 16#0e_2008# / Register_Width,
1292 TRANS_VTOTAL_C => 16#0e_200c# / Register_Width,
1293 TRANS_VBLANK_C => 16#0e_2010# / Register_Width,
1294 TRANS_VSYNC_C => 16#0e_2014# / Register_Width,
1295 TRANSC_DATA_M1 => 16#0e_2030# / Register_Width,
1296 TRANSC_DATA_N1 => 16#0e_2034# / Register_Width,
1297 TRANSC_DP_LINK_M1 => 16#0e_2040# / Register_Width,
1298 TRANSC_DP_LINK_N1 => 16#0e_2044# / Register_Width,
1299 PIPEC_DATA_M1 => 16#06_2030# / Register_Width,
1300 PIPEC_DATA_N1 => 16#06_2034# / Register_Width,
1301 PIPEC_LINK_M1 => 16#06_2040# / Register_Width,
1302 PIPEC_LINK_N1 => 16#06_2044# / Register_Width,
1303 PIPEC_DDI_FUNC_CTL => 16#06_2400# / Register_Width,
1304 PIPEC_MSA_MISC => 16#06_2410# / Register_Width,
1305
1306 -- panel fitter
1307 PFC_CTL_1 => 16#06_9080# / Register_Width,
1308 PFC_WIN_POS => 16#06_9070# / Register_Width,
1309 PFC_WIN_SZ => 16#06_9074# / Register_Width,
1310 PS_WIN_POS_1_C => 16#06_9170# / Register_Width,
1311 PS_WIN_SZ_1_C => 16#06_9174# / Register_Width,
1312 PS_CTRL_1_C => 16#06_9180# / Register_Width,
1313
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1314 -- cursor control
1315 CUR_CTL_C => 16#07_2080# / Register_Width,
1316 CUR_BASE_C => 16#07_2084# / Register_Width,
1317 CUR_POS_C => 16#07_2088# / Register_Width,
1318 CUR_FBC_CTL_C => 16#07_20a0# / Register_Width,
1319
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1320 -- display control
1321 DSPCCNTR => 16#07_2180# / Register_Width,
1322 DSPCLINOFF => 16#07_2184# / Register_Width,
1323 DSPCSTRIDE => 16#07_2188# / Register_Width,
1324 PLANE_POS_1_C => 16#07_218c# / Register_Width,
1325 PLANE_SIZE_1_C => 16#07_2190# / Register_Width,
1326 DSPCSURF => 16#07_219c# / Register_Width,
1327 DSPCTILEOFF => 16#07_21a4# / Register_Width,
1328
1329 -- sprite control
1330 SPCCNTR => 16#07_2280# / Register_Width,
1331
1332 -- PCH transcoder control
1333 FDI_TX_CTL_C => 16#06_2100# / Register_Width,
1334 FDI_RXC_CTL => 16#0f_200c# / Register_Width,
1335 FDI_RX_MISC_C => 16#0f_2010# / Register_Width,
1336 FDI_RXC_IIR => 16#0f_2014# / Register_Width,
1337 FDI_RXC_IMR => 16#0f_2018# / Register_Width,
1338 FDI_RXC_TUSIZE1 => 16#0f_2030# / Register_Width,
1339 TRANSCCONF => 16#0f_2008# / Register_Width,
1340 TRANSC_CHICKEN2 => 16#0f_2064# / Register_Width,
1341
1342 -- watermark registers
1343 WM_LINETIME_C => 16#04_5278# / Register_Width,
1344 PLANE_WM_1_C_0 => 16#07_2240# / Register_Width,
1345 PLANE_WM_1_C_1 => 16#07_2244# / Register_Width,
1346 PLANE_WM_1_C_2 => 16#07_2248# / Register_Width,
1347 PLANE_WM_1_C_3 => 16#07_224c# / Register_Width,
1348 PLANE_WM_1_C_4 => 16#07_2250# / Register_Width,
1349 PLANE_WM_1_C_5 => 16#07_2254# / Register_Width,
1350 PLANE_WM_1_C_6 => 16#07_2258# / Register_Width,
1351 PLANE_WM_1_C_7 => 16#07_225c# / Register_Width,
1352 PLANE_BUF_CFG_1_C => 16#07_227c# / Register_Width,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1353 CUR_WM_C_0 => 16#07_2140# / Register_Width,
1354 CUR_WM_C_1 => 16#07_2144# / Register_Width,
1355 CUR_WM_C_2 => 16#07_2148# / Register_Width,
1356 CUR_WM_C_3 => 16#07_214c# / Register_Width,
1357 CUR_WM_C_4 => 16#07_2150# / Register_Width,
1358 CUR_WM_C_5 => 16#07_2154# / Register_Width,
1359 CUR_WM_C_6 => 16#07_2158# / Register_Width,
1360 CUR_WM_C_7 => 16#07_215c# / Register_Width,
1361 CUR_BUF_CFG_C => 16#07_217c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1362
1363 -- CPU transcoder clock select
1364 TRANSC_CLK_SEL => 16#04_6148# / Register_Width,
1365
1366 ---------------------------------------------------------------------------
1367 -- Pipe EDP registers
1368 ---------------------------------------------------------------------------
1369
1370 -- pipe timing registers
1371
1372 HTOTAL_EDP => 16#06_f000# / Register_Width,
1373 HBLANK_EDP => 16#06_f004# / Register_Width,
1374 HSYNC_EDP => 16#06_f008# / Register_Width,
1375 VTOTAL_EDP => 16#06_f00c# / Register_Width,
1376 VBLANK_EDP => 16#06_f010# / Register_Width,
1377 VSYNC_EDP => 16#06_f014# / Register_Width,
1378 PIPE_EDP_CONF => 16#07_f008# / Register_Width,
1379 PIPE_EDP_DATA_M1 => 16#06_f030# / Register_Width,
1380 PIPE_EDP_DATA_N1 => 16#06_f034# / Register_Width,
1381 PIPE_EDP_LINK_M1 => 16#06_f040# / Register_Width,
1382 PIPE_EDP_LINK_N1 => 16#06_f044# / Register_Width,
1383 PIPE_EDP_DDI_FUNC_CTL => 16#06_f400# / Register_Width,
1384 PIPE_EDP_MSA_MISC => 16#06_f410# / Register_Width,
1385
1386 -- PSR registers
1387 SRD_CTL => 16#06_4800# / Register_Width,
1388 SRD_CTL_A => 16#06_0800# / Register_Width,
1389 SRD_CTL_B => 16#06_1800# / Register_Width,
1390 SRD_CTL_C => 16#06_2800# / Register_Width,
1391 SRD_CTL_EDP => 16#06_f800# / Register_Width,
1392 SRD_STATUS => 16#06_4840# / Register_Width,
1393 SRD_STATUS_A => 16#06_0840# / Register_Width,
1394 SRD_STATUS_B => 16#06_1840# / Register_Width,
1395 SRD_STATUS_C => 16#06_2840# / Register_Width,
1396 SRD_STATUS_EDP => 16#06_f840# / Register_Width,
1397
1398 -- DDI registers
1399 DDI_BUF_CTL_A => 16#06_4000# / Register_Width, -- aliased by DP_CTL_A
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1400 DDI_BUF_TRANS_A_S0T1 => 16#06_4e00# / Register_Width,
1401 DDI_BUF_TRANS_A_S0T2 => 16#06_4e04# / Register_Width,
1402 DDI_BUF_TRANS_A_S1T1 => 16#06_4e08# / Register_Width,
1403 DDI_BUF_TRANS_A_S1T2 => 16#06_4e0c# / Register_Width,
1404 DDI_BUF_TRANS_A_S2T1 => 16#06_4e10# / Register_Width,
1405 DDI_BUF_TRANS_A_S2T2 => 16#06_4e14# / Register_Width,
1406 DDI_BUF_TRANS_A_S3T1 => 16#06_4e18# / Register_Width,
1407 DDI_BUF_TRANS_A_S3T2 => 16#06_4e1c# / Register_Width,
1408 DDI_BUF_TRANS_A_S4T1 => 16#06_4e20# / Register_Width,
1409 DDI_BUF_TRANS_A_S4T2 => 16#06_4e24# / Register_Width,
1410 DDI_BUF_TRANS_A_S5T1 => 16#06_4e28# / Register_Width,
1411 DDI_BUF_TRANS_A_S5T2 => 16#06_4e2c# / Register_Width,
1412 DDI_BUF_TRANS_A_S6T1 => 16#06_4e30# / Register_Width,
1413 DDI_BUF_TRANS_A_S6T2 => 16#06_4e34# / Register_Width,
1414 DDI_BUF_TRANS_A_S7T1 => 16#06_4e38# / Register_Width,
1415 DDI_BUF_TRANS_A_S7T2 => 16#06_4e3c# / Register_Width,
1416 DDI_BUF_TRANS_A_S8T1 => 16#06_4e40# / Register_Width,
1417 DDI_BUF_TRANS_A_S8T2 => 16#06_4e44# / Register_Width,
1418 DDI_BUF_TRANS_A_S9T1 => 16#06_4e48# / Register_Width,
1419 DDI_BUF_TRANS_A_S9T2 => 16#06_4e4c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1420 DDI_AUX_CTL_A => 16#06_4010# / Register_Width, -- aliased by DP_AUX_CTL_A
1421 DDI_AUX_DATA_A_1 => 16#06_4014# / Register_Width, -- aliased by DP_AUX_DATA_A_1
1422 DDI_AUX_DATA_A_2 => 16#06_4018# / Register_Width, -- aliased by DP_AUX_DATA_A_2
1423 DDI_AUX_DATA_A_3 => 16#06_401c# / Register_Width, -- aliased by DP_AUX_DATA_A_3
1424 DDI_AUX_DATA_A_4 => 16#06_4020# / Register_Width, -- aliased by DP_AUX_DATA_A_4
1425 DDI_AUX_DATA_A_5 => 16#06_4024# / Register_Width, -- aliased by DP_AUX_DATA_A_5
1426 DDI_AUX_MUTEX_A => 16#06_402c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1427
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1428 DDI_BUF_CTL_B => 16#06_4100# / Register_Width, -- aliased by GMCH_DP_B
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1429 DDI_BUF_TRANS_B_S0T1 => 16#06_4e60# / Register_Width,
1430 DDI_BUF_TRANS_B_S0T2 => 16#06_4e64# / Register_Width,
1431 DDI_BUF_TRANS_B_S1T1 => 16#06_4e68# / Register_Width,
1432 DDI_BUF_TRANS_B_S1T2 => 16#06_4e6c# / Register_Width,
1433 DDI_BUF_TRANS_B_S2T1 => 16#06_4e70# / Register_Width,
1434 DDI_BUF_TRANS_B_S2T2 => 16#06_4e74# / Register_Width,
1435 DDI_BUF_TRANS_B_S3T1 => 16#06_4e78# / Register_Width,
1436 DDI_BUF_TRANS_B_S3T2 => 16#06_4e7c# / Register_Width,
1437 DDI_BUF_TRANS_B_S4T1 => 16#06_4e80# / Register_Width,
1438 DDI_BUF_TRANS_B_S4T2 => 16#06_4e84# / Register_Width,
1439 DDI_BUF_TRANS_B_S5T1 => 16#06_4e88# / Register_Width,
1440 DDI_BUF_TRANS_B_S5T2 => 16#06_4e8c# / Register_Width,
1441 DDI_BUF_TRANS_B_S6T1 => 16#06_4e90# / Register_Width,
1442 DDI_BUF_TRANS_B_S6T2 => 16#06_4e94# / Register_Width,
1443 DDI_BUF_TRANS_B_S7T1 => 16#06_4e98# / Register_Width,
1444 DDI_BUF_TRANS_B_S7T2 => 16#06_4e9c# / Register_Width,
1445 DDI_BUF_TRANS_B_S8T1 => 16#06_4ea0# / Register_Width,
1446 DDI_BUF_TRANS_B_S8T2 => 16#06_4ea4# / Register_Width,
1447 DDI_BUF_TRANS_B_S9T1 => 16#06_4ea8# / Register_Width,
1448 DDI_BUF_TRANS_B_S9T2 => 16#06_4eac# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1449 DDI_AUX_CTL_B => 16#06_4110# / Register_Width,
1450 DDI_AUX_DATA_B_1 => 16#06_4114# / Register_Width,
1451 DDI_AUX_DATA_B_2 => 16#06_4118# / Register_Width,
1452 DDI_AUX_DATA_B_3 => 16#06_411c# / Register_Width,
1453 DDI_AUX_DATA_B_4 => 16#06_4120# / Register_Width,
1454 DDI_AUX_DATA_B_5 => 16#06_4124# / Register_Width,
1455 DDI_AUX_MUTEX_B => 16#06_412c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1456
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1457 DDI_BUF_CTL_C => 16#06_4200# / Register_Width, -- aliased by GMCH_DP_C
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1458 DDI_BUF_TRANS_C_S0T1 => 16#06_4ec0# / Register_Width,
1459 DDI_BUF_TRANS_C_S0T2 => 16#06_4ec4# / Register_Width,
1460 DDI_BUF_TRANS_C_S1T1 => 16#06_4ec8# / Register_Width,
1461 DDI_BUF_TRANS_C_S1T2 => 16#06_4ecc# / Register_Width,
1462 DDI_BUF_TRANS_C_S2T1 => 16#06_4ed0# / Register_Width,
1463 DDI_BUF_TRANS_C_S2T2 => 16#06_4ed4# / Register_Width,
1464 DDI_BUF_TRANS_C_S3T1 => 16#06_4ed8# / Register_Width,
1465 DDI_BUF_TRANS_C_S3T2 => 16#06_4edc# / Register_Width,
1466 DDI_BUF_TRANS_C_S4T1 => 16#06_4ee0# / Register_Width,
1467 DDI_BUF_TRANS_C_S4T2 => 16#06_4ee4# / Register_Width,
1468 DDI_BUF_TRANS_C_S5T1 => 16#06_4ee8# / Register_Width,
1469 DDI_BUF_TRANS_C_S5T2 => 16#06_4eec# / Register_Width,
1470 DDI_BUF_TRANS_C_S6T1 => 16#06_4ef0# / Register_Width,
1471 DDI_BUF_TRANS_C_S6T2 => 16#06_4ef4# / Register_Width,
1472 DDI_BUF_TRANS_C_S7T1 => 16#06_4ef8# / Register_Width,
1473 DDI_BUF_TRANS_C_S7T2 => 16#06_4efc# / Register_Width,
1474 DDI_BUF_TRANS_C_S8T1 => 16#06_4f00# / Register_Width,
1475 DDI_BUF_TRANS_C_S8T2 => 16#06_4f04# / Register_Width,
1476 DDI_BUF_TRANS_C_S9T1 => 16#06_4f08# / Register_Width,
1477 DDI_BUF_TRANS_C_S9T2 => 16#06_4f0c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1478 DDI_AUX_CTL_C => 16#06_4210# / Register_Width,
1479 DDI_AUX_DATA_C_1 => 16#06_4214# / Register_Width,
1480 DDI_AUX_DATA_C_2 => 16#06_4218# / Register_Width,
1481 DDI_AUX_DATA_C_3 => 16#06_421c# / Register_Width,
1482 DDI_AUX_DATA_C_4 => 16#06_4220# / Register_Width,
1483 DDI_AUX_DATA_C_5 => 16#06_4224# / Register_Width,
1484 DDI_AUX_MUTEX_C => 16#06_422c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1485
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1486 DDI_BUF_CTL_D => 16#06_4300# / Register_Width, -- aliased by GMCH_DP_D
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1487 DDI_BUF_TRANS_D_S0T1 => 16#06_4f20# / Register_Width,
1488 DDI_BUF_TRANS_D_S0T2 => 16#06_4f24# / Register_Width,
1489 DDI_BUF_TRANS_D_S1T1 => 16#06_4f28# / Register_Width,
1490 DDI_BUF_TRANS_D_S1T2 => 16#06_4f2c# / Register_Width,
1491 DDI_BUF_TRANS_D_S2T1 => 16#06_4f30# / Register_Width,
1492 DDI_BUF_TRANS_D_S2T2 => 16#06_4f34# / Register_Width,
1493 DDI_BUF_TRANS_D_S3T1 => 16#06_4f38# / Register_Width,
1494 DDI_BUF_TRANS_D_S3T2 => 16#06_4f3c# / Register_Width,
1495 DDI_BUF_TRANS_D_S4T1 => 16#06_4f40# / Register_Width,
1496 DDI_BUF_TRANS_D_S4T2 => 16#06_4f44# / Register_Width,
1497 DDI_BUF_TRANS_D_S5T1 => 16#06_4f48# / Register_Width,
1498 DDI_BUF_TRANS_D_S5T2 => 16#06_4f4c# / Register_Width,
1499 DDI_BUF_TRANS_D_S6T1 => 16#06_4f50# / Register_Width,
1500 DDI_BUF_TRANS_D_S6T2 => 16#06_4f54# / Register_Width,
1501 DDI_BUF_TRANS_D_S7T1 => 16#06_4f58# / Register_Width,
1502 DDI_BUF_TRANS_D_S7T2 => 16#06_4f5c# / Register_Width,
1503 DDI_BUF_TRANS_D_S8T1 => 16#06_4f60# / Register_Width,
1504 DDI_BUF_TRANS_D_S8T2 => 16#06_4f64# / Register_Width,
1505 DDI_BUF_TRANS_D_S9T1 => 16#06_4f68# / Register_Width,
1506 DDI_BUF_TRANS_D_S9T2 => 16#06_4f6c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1507 DDI_AUX_CTL_D => 16#06_4310# / Register_Width,
1508 DDI_AUX_DATA_D_1 => 16#06_4314# / Register_Width,
1509 DDI_AUX_DATA_D_2 => 16#06_4318# / Register_Width,
1510 DDI_AUX_DATA_D_3 => 16#06_431c# / Register_Width,
1511 DDI_AUX_DATA_D_4 => 16#06_4320# / Register_Width,
1512 DDI_AUX_DATA_D_5 => 16#06_4324# / Register_Width,
1513 DDI_AUX_MUTEX_D => 16#06_432c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1514
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1515 -- USB-C AUX control and data
1516 DDI_AUX_CTL_USBC2 => 16#06_4410# / Register_Width,
1517 DDI_AUX_DATA_USBC2_1 => 16#06_4414# / Register_Width,
1518 DDI_AUX_DATA_USBC2_2 => 16#06_4418# / Register_Width,
1519 DDI_AUX_DATA_USBC2_3 => 16#06_441c# / Register_Width,
1520 DDI_AUX_DATA_USBC2_4 => 16#06_4420# / Register_Width,
1521 DDI_AUX_DATA_USBC2_5 => 16#06_4424# / Register_Width,
1522 DDI_AUX_CTL_USBC3 => 16#06_4510# / Register_Width,
1523 DDI_AUX_DATA_USBC3_1 => 16#06_4514# / Register_Width,
1524 DDI_AUX_DATA_USBC3_2 => 16#06_4518# / Register_Width,
1525 DDI_AUX_DATA_USBC3_3 => 16#06_451c# / Register_Width,
1526 DDI_AUX_DATA_USBC3_4 => 16#06_4520# / Register_Width,
1527 DDI_AUX_DATA_USBC3_5 => 16#06_4524# / Register_Width,
1528 DDI_AUX_CTL_USBC4 => 16#06_4610# / Register_Width,
1529 DDI_AUX_DATA_USBC4_1 => 16#06_4614# / Register_Width,
1530 DDI_AUX_DATA_USBC4_2 => 16#06_4618# / Register_Width,
1531 DDI_AUX_DATA_USBC4_3 => 16#06_461c# / Register_Width,
1532 DDI_AUX_DATA_USBC4_4 => 16#06_4620# / Register_Width,
1533 DDI_AUX_DATA_USBC4_5 => 16#06_4624# / Register_Width,
1534 DDI_AUX_CTL_USBC5 => 16#06_4710# / Register_Width,
1535 DDI_AUX_DATA_USBC5_1 => 16#06_4714# / Register_Width,
1536 DDI_AUX_DATA_USBC5_2 => 16#06_4718# / Register_Width,
1537 DDI_AUX_DATA_USBC5_3 => 16#06_471c# / Register_Width,
1538 DDI_AUX_DATA_USBC5_4 => 16#06_4720# / Register_Width,
1539 DDI_AUX_DATA_USBC5_5 => 16#06_4724# / Register_Width,
1540 DDI_AUX_CTL_USBC6 => 16#06_4810# / Register_Width,
1541 DDI_AUX_DATA_USBC6_1 => 16#06_4814# / Register_Width,
1542 DDI_AUX_DATA_USBC6_2 => 16#06_4818# / Register_Width,
1543 DDI_AUX_DATA_USBC6_3 => 16#06_481c# / Register_Width,
1544 DDI_AUX_DATA_USBC6_4 => 16#06_4820# / Register_Width,
1545 DDI_AUX_DATA_USBC6_5 => 16#06_4824# / Register_Width,
1546
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1547 DDI_BUF_CTL_E => 16#06_4400# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1548 DDI_BUF_TRANS_E_S0T1 => 16#06_4f80# / Register_Width,
1549 DDI_BUF_TRANS_E_S0T2 => 16#06_4f84# / Register_Width,
1550 DDI_BUF_TRANS_E_S1T1 => 16#06_4f88# / Register_Width,
1551 DDI_BUF_TRANS_E_S1T2 => 16#06_4f8c# / Register_Width,
1552 DDI_BUF_TRANS_E_S2T1 => 16#06_4f90# / Register_Width,
1553 DDI_BUF_TRANS_E_S2T2 => 16#06_4f94# / Register_Width,
1554 DDI_BUF_TRANS_E_S3T1 => 16#06_4f98# / Register_Width,
1555 DDI_BUF_TRANS_E_S3T2 => 16#06_4f9c# / Register_Width,
1556 DDI_BUF_TRANS_E_S4T1 => 16#06_4fa0# / Register_Width,
1557 DDI_BUF_TRANS_E_S4T2 => 16#06_4fa4# / Register_Width,
1558 DDI_BUF_TRANS_E_S5T1 => 16#06_4fa8# / Register_Width,
1559 DDI_BUF_TRANS_E_S5T2 => 16#06_4fac# / Register_Width,
1560 DDI_BUF_TRANS_E_S6T1 => 16#06_4fb0# / Register_Width,
1561 DDI_BUF_TRANS_E_S6T2 => 16#06_4fb4# / Register_Width,
1562 DDI_BUF_TRANS_E_S7T1 => 16#06_4fb8# / Register_Width,
1563 DDI_BUF_TRANS_E_S7T2 => 16#06_4fbc# / Register_Width,
1564 DDI_BUF_TRANS_E_S8T1 => 16#06_4fc0# / Register_Width,
1565 DDI_BUF_TRANS_E_S8T2 => 16#06_4fc4# / Register_Width,
1566 DDI_BUF_TRANS_E_S9T1 => 16#06_4fc8# / Register_Width,
1567 DDI_BUF_TRANS_E_S9T2 => 16#06_4fcc# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1568 DP_TP_CTL_A => 16#06_4040# / Register_Width,
1569 DP_TP_CTL_B => 16#06_4140# / Register_Width,
1570 DP_TP_CTL_C => 16#06_4240# / Register_Width,
1571 DP_TP_CTL_D => 16#06_4340# / Register_Width,
1572 DP_TP_CTL_E => 16#06_4440# / Register_Width,
1573 DP_TP_STATUS_B => 16#06_4144# / Register_Width,
1574 DP_TP_STATUS_C => 16#06_4244# / Register_Width,
1575 DP_TP_STATUS_D => 16#06_4344# / Register_Width,
1576 DP_TP_STATUS_E => 16#06_4444# / Register_Width,
1577 PORT_CLK_SEL_DDIA => 16#04_6100# / Register_Width,
1578 PORT_CLK_SEL_DDIB => 16#04_6104# / Register_Width,
1579 PORT_CLK_SEL_DDIC => 16#04_6108# / Register_Width,
1580 PORT_CLK_SEL_DDID => 16#04_610c# / Register_Width,
1581 PORT_CLK_SEL_DDIE => 16#04_6110# / Register_Width,
1582
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]1583 -- Haswell LCPLL registers
1584 LCPLL_CTL => 16#13_0040# / Register_Width,
1585
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]1586 -- Skylake I_boost configuration
1587 DISPIO_CR_TX_BMU_CR0 => 16#06_c00c# / Register_Width,
1588
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1589 -- Skylake DPLL registers
1590 DPLL1_CFGR1 => 16#06_c040# / Register_Width,
1591 DPLL1_CFGR2 => 16#06_c044# / Register_Width,
1592 DPLL2_CFGR1 => 16#06_c048# / Register_Width,
1593 DPLL2_CFGR2 => 16#06_c04c# / Register_Width,
1594 DPLL3_CFGR1 => 16#06_c050# / Register_Width,
1595 DPLL3_CFGR2 => 16#06_c054# / Register_Width,
1596 DPLL_CTRL1 => 16#06_c058# / Register_Width,
1597 DPLL_CTRL2 => 16#06_c05c# / Register_Width,
1598 DPLL_STATUS => 16#06_c060# / Register_Width,
1599
1600 -- CD CLK register
1601 CDCLK_CTL => 16#04_6000# / Register_Width,
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]1602 CDCLK_FREQ => 16#04_6200# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1603
1604 -- Skylake LCPLL registers
1605 LCPLL1_CTL => 16#04_6010# / Register_Width,
1606 LCPLL2_CTL => 16#04_6014# / Register_Width,
1607
1608 -- SPLL register
1609 SPLL_CTL => 16#04_6020# / Register_Width,
1610
1611 -- WRPLL registers
1612 WRPLL_CTL_1 => 16#04_6040# / Register_Width,
1613 WRPLL_CTL_2 => 16#04_6060# / Register_Width,
1614
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]1615 -- Broxton Display Engine PLL registers
1616 BXT_DE_PLL_CTL => 16#06_d000# / Register_Width,
1617 BXT_DE_PLL_ENABLE => 16#04_6070# / Register_Width,
1618
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1619 -- Broxton DDI PHY PLL registers
1620 BXT_PORT_PLL_ENABLE_A => 16#04_6074# / Register_Width,
1621 BXT_PORT_PLL_ENABLE_B => 16#04_6078# / Register_Width,
1622 BXT_PORT_PLL_ENABLE_C => 16#04_607c# / Register_Width,
1623 BXT_PORT_PLL_EBB_0_A => 16#16_2034# / Register_Width,
1624 BXT_PORT_PLL_EBB_4_A => 16#16_2038# / Register_Width,
1625 BXT_PORT_PLL_0_A => 16#16_2100# / Register_Width,
1626 BXT_PORT_PLL_1_A => 16#16_2104# / Register_Width,
1627 BXT_PORT_PLL_2_A => 16#16_2108# / Register_Width,
1628 BXT_PORT_PLL_3_A => 16#16_210c# / Register_Width,
1629 BXT_PORT_PLL_6_A => 16#16_2118# / Register_Width,
1630 BXT_PORT_PLL_8_A => 16#16_2120# / Register_Width,
1631 BXT_PORT_PLL_9_A => 16#16_2124# / Register_Width,
1632 BXT_PORT_PLL_10_A => 16#16_2128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1633 BXT_PORT_PLL_EBB_0_B => 16#06_c034# / Register_Width,
1634 BXT_PORT_PLL_EBB_4_B => 16#06_c038# / Register_Width,
1635 BXT_PORT_PLL_0_B => 16#06_c100# / Register_Width,
1636 BXT_PORT_PLL_1_B => 16#06_c104# / Register_Width,
1637 BXT_PORT_PLL_2_B => 16#06_c108# / Register_Width,
1638 BXT_PORT_PLL_3_B => 16#06_c10c# / Register_Width,
1639 BXT_PORT_PLL_6_B => 16#06_c118# / Register_Width,
1640 BXT_PORT_PLL_8_B => 16#06_c120# / Register_Width,
1641 BXT_PORT_PLL_9_B => 16#06_c124# / Register_Width,
1642 BXT_PORT_PLL_10_B => 16#06_c128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1643 BXT_PORT_PLL_EBB_0_C => 16#06_c340# / Register_Width,
1644 BXT_PORT_PLL_EBB_4_C => 16#06_c344# / Register_Width,
1645 BXT_PORT_PLL_0_C => 16#06_c380# / Register_Width,
1646 BXT_PORT_PLL_1_C => 16#06_c384# / Register_Width,
1647 BXT_PORT_PLL_2_C => 16#06_c388# / Register_Width,
1648 BXT_PORT_PLL_3_C => 16#06_c38c# / Register_Width,
1649 BXT_PORT_PLL_6_C => 16#06_c398# / Register_Width,
1650 BXT_PORT_PLL_8_C => 16#06_c3a0# / Register_Width,
1651 BXT_PORT_PLL_9_C => 16#06_c3a4# / Register_Width,
1652 BXT_PORT_PLL_10_C => 16#06_c3a8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1653
1654 -- Broxton DDI PHY PCS? registers
1655 BXT_PORT_PCS_DW10_01_A => 16#16_2428# / Register_Width,
1656 BXT_PORT_PCS_DW12_01_A => 16#16_2430# / Register_Width,
1657 BXT_PORT_PCS_DW10_GRP_A => 16#16_2c28# / Register_Width,
1658 BXT_PORT_PCS_DW12_GRP_A => 16#16_2c30# / Register_Width,
1659 BXT_PORT_PCS_DW10_01_B => 16#06_c428# / Register_Width,
1660 BXT_PORT_PCS_DW12_01_B => 16#06_c430# / Register_Width,
1661 BXT_PORT_PCS_DW10_01_C => 16#06_c828# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1662 BXT_PORT_PCS_DW12_01_C => 16#06_c830# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1663 BXT_PORT_PCS_DW10_GRP_B => 16#06_cc28# / Register_Width,
1664 BXT_PORT_PCS_DW12_GRP_B => 16#06_cc30# / Register_Width,
1665 BXT_PORT_PCS_DW10_GRP_C => 16#06_ce28# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1666 BXT_PORT_PCS_DW12_GRP_C => 16#06_ce30# / Register_Width,
1667
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1668 -- Broxton DDI PHY registers
1669 BXT_P_CR_GT_DISP_PWRON => 16#13_8090# / Register_Width,
1670 BXT_PHY_CTL_A => 16#06_4c00# / Register_Width,
1671 BXT_PHY_CTL_B => 16#06_4c10# / Register_Width,
1672 BXT_PHY_CTL_C => 16#06_4c20# / Register_Width,
1673 BXT_PHY_CTL_FAM_EDP => 16#06_4c80# / Register_Width,
1674 BXT_PHY_CTL_FAM_DDI => 16#06_4c90# / Register_Width,
1675
1676 -- Broxton DDI PHY common lane registers
1677 BXT_PORT_CL1CM_DW0_A => 16#16_2000# / Register_Width,
1678 BXT_PORT_CL1CM_DW0_BC => 16#06_c000# / Register_Width,
1679 BXT_PORT_CL1CM_DW9_A => 16#16_2024# / Register_Width,
1680 BXT_PORT_CL1CM_DW9_BC => 16#06_c024# / Register_Width,
1681 BXT_PORT_CL1CM_DW10_A => 16#16_2028# / Register_Width,
1682 BXT_PORT_CL1CM_DW10_BC => 16#06_c028# / Register_Width,
1683 BXT_PORT_CL1CM_DW28_A => 16#16_2070# / Register_Width,
1684 BXT_PORT_CL1CM_DW28_BC => 16#06_c070# / Register_Width,
1685 BXT_PORT_CL1CM_DW30_A => 16#16_2078# / Register_Width,
1686 BXT_PORT_CL1CM_DW30_BC => 16#06_c078# / Register_Width,
1687 BXT_PORT_CL2CM_DW6_BC => 16#06_c358# / Register_Width,
1688
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1689 -- Broxton DDI PHY TX lane registers
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1690 BXT_PORT_TX_DW2_LN0_A => 16#16_2508# / Register_Width,
1691 BXT_PORT_TX_DW3_LN0_A => 16#16_250c# / Register_Width,
1692 BXT_PORT_TX_DW4_LN0_A => 16#16_2510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1693 BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width,
1694 BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width,
1695 BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width,
1696 BXT_PORT_TX_DW14_LN3_A => 16#16_27b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1697 BXT_PORT_TX_DW2_GRP_A => 16#16_2d08# / Register_Width,
1698 BXT_PORT_TX_DW3_GRP_A => 16#16_2d0c# / Register_Width,
1699 BXT_PORT_TX_DW4_GRP_A => 16#16_2d10# / Register_Width,
1700 BXT_PORT_TX_DW2_LN0_B => 16#06_c508# / Register_Width,
1701 BXT_PORT_TX_DW3_LN0_B => 16#06_c50c# / Register_Width,
1702 BXT_PORT_TX_DW4_LN0_B => 16#06_c510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1703 BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width,
1704 BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width,
1705 BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width,
1706 BXT_PORT_TX_DW14_LN3_B => 16#06_c7b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1707 BXT_PORT_TX_DW2_GRP_B => 16#06_cd08# / Register_Width,
1708 BXT_PORT_TX_DW3_GRP_B => 16#06_cd0c# / Register_Width,
1709 BXT_PORT_TX_DW4_GRP_B => 16#06_cd10# / Register_Width,
1710 BXT_PORT_TX_DW2_LN0_C => 16#06_c908# / Register_Width,
1711 BXT_PORT_TX_DW3_LN0_C => 16#06_c90c# / Register_Width,
1712 BXT_PORT_TX_DW4_LN0_C => 16#06_c910# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1713 BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width,
1714 BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width,
1715 BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width,
1716 BXT_PORT_TX_DW14_LN3_C => 16#06_cbb8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1717 BXT_PORT_TX_DW2_GRP_C => 16#06_cf08# / Register_Width,
1718 BXT_PORT_TX_DW3_GRP_C => 16#06_cf0c# / Register_Width,
1719 BXT_PORT_TX_DW4_GRP_C => 16#06_cf10# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1720
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1721 -- Broxton DDI PHY ref registers
1722 BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width,
1723 BXT_PORT_REF_DW3_BC => 16#06_c18c# / Register_Width,
1724 BXT_PORT_REF_DW6_A => 16#16_2198# / Register_Width,
1725 BXT_PORT_REF_DW6_BC => 16#06_c198# / Register_Width,
1726 BXT_PORT_REF_DW8_A => 16#16_21a0# / Register_Width,
1727 BXT_PORT_REF_DW8_BC => 16#06_c1a0# / Register_Width,
1728
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1729 -- Power Down Well registers
1730 PWR_WELL_CTL_BIOS => 16#04_5400# / Register_Width,
1731 PWR_WELL_CTL_DRIVER => 16#04_5404# / Register_Width,
1732 PWR_WELL_CTL_KVMR => 16#04_5408# / Register_Width,
1733 PWR_WELL_CTL_DEBUG => 16#04_540c# / Register_Width,
1734 PWR_WELL_CTL5 => 16#04_5410# / Register_Width,
1735 PWR_WELL_CTL6 => 16#04_5414# / Register_Width,
1736
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1737 PWR_AUX_CTL_BIOS => 16#04_5440# / Register_Width,
1738 PWR_AUX_CTL_DRIVER => 16#04_5444# / Register_Width,
1739 PWR_DDI_CTL_BIOS => 16#04_5450# / Register_Width,
1740 PWR_DDI_CTL_DRIVER => 16#04_5454# / Register_Width,
1741
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1742 -- class Panel registers
Arthur Heymanse87d0d12018-03-28 17:02:49 +0200[diff] [blame]1743 GMCH_PP_STATUS => 16#06_1200# / Register_Width,
1744 GMCH_PP_CONTROL => 16#06_1204# / Register_Width,
1745 GMCH_PP_ON_DELAYS => 16#06_1208# / Register_Width,
1746 GMCH_PP_OFF_DELAYS => 16#06_120c# / Register_Width,
1747 GMCH_PP_DIVISOR => 16#06_1210# / Register_Width,
Arthur Heymansd5198442018-03-28 17:05:12 +0200[diff] [blame]1748 GMCH_PFIT_CONTROL => 16#06_1230# / Register_Width,
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]1749 PCH_PP_STATUS => 16#0c_7200# / Register_Width, -- aliased with BXT_PP_STATUS_1
1750 PCH_PP_CONTROL => 16#0c_7204# / Register_Width, -- aliased with BXT_PP_CONTROL_1
1751 PCH_PP_ON_DELAYS => 16#0c_7208# / Register_Width, -- aliased with BXT_PP_ON_DELAYS_1
1752 PCH_PP_OFF_DELAYS => 16#0c_720c# / Register_Width, -- aliased with BXT_PP_OFF_DELAYS_1
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1753 PCH_PP_DIVISOR => 16#0c_7210# / Register_Width,
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]1754 BXT_PP_STATUS_2 => 16#0c_7300# / Register_Width,
1755 BXT_PP_CONTROL_2 => 16#0c_7304# / Register_Width,
1756 BXT_PP_ON_DELAYS_2 => 16#0c_7308# / Register_Width,
1757 BXT_PP_OFF_DELAYS_2 => 16#0c_730c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1758 BLC_PWM_CPU_CTL => 16#04_8254# / Register_Width,
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]1759 BLC_PWM_CPU_CTL2 => 16#04_8250# / Register_Width,
1760 BLC_PWM_PCH_CTL1 => 16#0c_8250# / Register_Width, -- aliased with BXT_BLC_PWM_CTL_1
1761 BLC_PWM_PCH_CTL2 => 16#0c_8254# / Register_Width, -- aliased with BXT_BLC_PWM_FREQ_1
1762 BXT_BLC_PWM_DUTY_1 => 16#0c_8258# / Register_Width,
1763 BXT_BLC_PWM_CTL_2 => 16#0c_8350# / Register_Width,
1764 BXT_BLC_PWM_FREQ_2 => 16#0c_8354# / Register_Width,
1765 BXT_BLC_PWM_DUTY_2 => 16#0c_8358# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1766
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1767 -- GMCH LVDS Connector Registers
1768 GMCH_LVDS => 16#06_1180# / Register_Width,
1769
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1770 -- PCH LVDS Connector Registers
1771 PCH_LVDS => 16#0e_1180# / Register_Width,
1772
1773 -- PCH ADPA Connector Registers
1774 PCH_ADPA => 16#0e_1100# / Register_Width,
1775
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1776 -- GMCH DVOB Connector Registers
1777 GMCH_SDVOB => 16#06_1140# / Register_Width,
1778
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1779 -- PCH HDMIB Connector Registers
1780 PCH_HDMIB => 16#0e_1140# / Register_Width,
1781
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1782 -- GMCH DVOC Connector Registers
1783 GMCH_SDVOC => 16#06_1160# / Register_Width,
1784
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1785 -- PCH HDMIC Connector Registers
1786 PCH_HDMIC => 16#0e_1150# / Register_Width,
1787
1788 -- PCH HDMID Connector Registers
1789 PCH_HDMID => 16#0e_1160# / Register_Width,
1790
1791 -- Intel Registers
Nico Huber6b4678d2019-09-22 21:31:52 +0200[diff] [blame]1792 DFSM => 16#05_1000# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1793 DSSM => 16#05_1004# / Register_Width,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]1794 CPU_VGACNTRL => 16#04_1000# / Register_Width,
1795 GMCH_VGACNTRL => 16#07_1400# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1796 FUSE_STATUS => 16#04_2000# / Register_Width,
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]1797 FUSE_STRAP => 16#04_2014# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1798 FBA_CFB_BASE => 16#04_3200# / Register_Width,
1799 IPS_CTL => 16#04_3408# / Register_Width,
1800 ARB_CTL => 16#04_5000# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1801 DBUF_CTL_S0 => 16#04_5008# / Register_Width,
1802 DBUF_CTL_S1 => 16#04_4fe8# / Register_Width,
1803 DBUF_CTL_S2 => 16#04_4300# / Register_Width,
1804 DBUF_CTL_S3 => 16#04_4304# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1805 NDE_RSTWRN_OPT => 16#04_6408# / Register_Width,
Angel Ponsae186bd2020-10-21 21:37:34 +0200[diff] [blame]1806 GEN8_CHICKEN_DCPR_1 => 16#04_6430# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1807 GEN11_CHICKEN_DCPR_2 => 16#04_6434# / Register_Width,
1808 GEN9_CLKGATE_DIS_0 => 16#04_6530# / Register_Width,
1809 GEN9_CLKGATE_DIS_5 => 16#04_6540# / Register_Width,
1810 GEN9_CHICKEN_DPCR_3 => 16#04_6538# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1811 PCH_DREF_CONTROL => 16#0c_6200# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1812 PCH_DPLL_SEL => 16#0c_7000# / Register_Width,
1813 GT_MAILBOX => 16#13_8124# / Register_Width,
1814 GT_MAILBOX_DATA => 16#13_8128# / Register_Width,
1815 GT_MAILBOX_DATA_1 => 16#13_812c# / Register_Width,
1816
1817 PCH_DP_B => 16#0e_4100# / Register_Width,
1818 PCH_DP_AUX_CTL_B => 16#0e_4110# / Register_Width,
1819 PCH_DP_AUX_DATA_B_1 => 16#0e_4114# / Register_Width,
1820 PCH_DP_AUX_DATA_B_2 => 16#0e_4118# / Register_Width,
1821 PCH_DP_AUX_DATA_B_3 => 16#0e_411c# / Register_Width,
1822 PCH_DP_AUX_DATA_B_4 => 16#0e_4120# / Register_Width,
1823 PCH_DP_AUX_DATA_B_5 => 16#0e_4124# / Register_Width,
1824 PCH_DP_C => 16#0e_4200# / Register_Width,
1825 PCH_DP_AUX_CTL_C => 16#0e_4210# / Register_Width,
1826 PCH_DP_AUX_DATA_C_1 => 16#0e_4214# / Register_Width,
1827 PCH_DP_AUX_DATA_C_2 => 16#0e_4218# / Register_Width,
1828 PCH_DP_AUX_DATA_C_3 => 16#0e_421c# / Register_Width,
1829 PCH_DP_AUX_DATA_C_4 => 16#0e_4220# / Register_Width,
1830 PCH_DP_AUX_DATA_C_5 => 16#0e_4224# / Register_Width,
1831 PCH_DP_D => 16#0e_4300# / Register_Width,
1832 PCH_DP_AUX_CTL_D => 16#0e_4310# / Register_Width,
1833 PCH_DP_AUX_DATA_D_1 => 16#0e_4314# / Register_Width,
1834 PCH_DP_AUX_DATA_D_2 => 16#0e_4318# / Register_Width,
1835 PCH_DP_AUX_DATA_D_3 => 16#0e_431c# / Register_Width,
1836 PCH_DP_AUX_DATA_D_4 => 16#0e_4320# / Register_Width,
1837 PCH_DP_AUX_DATA_D_5 => 16#0e_4324# / Register_Width,
1838
1839 -- watermark registers
1840 WM1_LP_ILK => 16#04_5108# / Register_Width,
1841 WM2_LP_ILK => 16#04_510c# / Register_Width,
1842 WM3_LP_ILK => 16#04_5110# / Register_Width,
1843
1844 -- audio VID/DID
1845 AUD_VID_DID => 16#06_5020# / Register_Width,
1846 PCH_AUD_VID_DID => 16#0e_5020# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1847 G4X_AUD_VID_DID => 16#06_2020# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1848
1849 -- interrupt registers
1850 DEISR => 16#04_4000# / Register_Width,
1851 DEIMR => 16#04_4004# / Register_Width,
1852 DEIIR => 16#04_4008# / Register_Width,
1853 DEIER => 16#04_400c# / Register_Width,
1854 GTISR => 16#04_4010# / Register_Width,
1855 GTIMR => 16#04_4014# / Register_Width,
1856 GTIIR => 16#04_4018# / Register_Width,
1857 GTIER => 16#04_401c# / Register_Width,
1858 SDEISR => 16#0c_4000# / Register_Width,
1859 SDEIMR => 16#0c_4004# / Register_Width,
1860 SDEIIR => 16#0c_4008# / Register_Width,
1861 SDEIER => 16#0c_400c# / Register_Width,
1862
1863 -- I2C stuff
Arthur Heymans229ed1c2018-03-28 16:45:43 +0200[diff] [blame]1864 GMCH_GMBUS0 => 16#00_5100# / Register_Width,
1865 GMCH_GMBUS1 => 16#00_5104# / Register_Width,
1866 GMCH_GMBUS2 => 16#00_5108# / Register_Width,
1867 GMCH_GMBUS3 => 16#00_510c# / Register_Width,
1868 GMCH_GMBUS4 => 16#00_5110# / Register_Width,
1869 GMCH_GMBUS5 => 16#00_5120# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1870 PCH_GMBUS0 => 16#0c_5100# / Register_Width,
1871 PCH_GMBUS1 => 16#0c_5104# / Register_Width,
1872 PCH_GMBUS2 => 16#0c_5108# / Register_Width,
1873 PCH_GMBUS3 => 16#0c_510c# / Register_Width,
1874 PCH_GMBUS4 => 16#0c_5110# / Register_Width,
1875 PCH_GMBUS5 => 16#0c_5120# / Register_Width,
1876
1877 -- clock gating -- maybe have to touch this
1878 DSPCLK_GATE_D => 16#04_2020# / Register_Width,
1879 PCH_FDI_CHICKEN_B_C => 16#0c_2000# / Register_Width,
1880 PCH_DSPCLK_GATE_D => 16#0c_2020# / Register_Width,
1881
1882 -- hotplug and initial detection
1883 HOTPLUG_CTL => 16#04_4030# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1884 TC_HOTPLUG_CTL => 16#04_4038# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1885 PORT_HOTPLUG_EN => 16#06_1110# / Register_Width,
1886 PORT_HOTPLUG_STAT => 16#06_1114# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1887 SHOTPLUG_CTL => 16#0c_4030# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1888 SHOTPLUG_CTL_TC => 16#0c_4034# / Register_Width,
1889 SHPD_FILTER_CNT => 16#0c_4038# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1890 SFUSE_STRAP => 16#0c_2014# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1891 GEN11_DE_HPD_ISR => 16#04_4470# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1892
1893 -- Render Engine Command Streamer
1894 ARB_MODE => 16#00_4030# / Register_Width,
1895 HWS_PGA => 16#00_4080# / Register_Width,
1896 RCS_RING_BUFFER_TAIL => 16#00_2030# / Register_Width,
1897 VCS_RING_BUFFER_TAIL => 16#01_2030# / Register_Width,
1898 BCS_RING_BUFFER_TAIL => 16#02_2030# / Register_Width,
1899 RCS_RING_BUFFER_HEAD => 16#00_2034# / Register_Width,
1900 VCS_RING_BUFFER_HEAD => 16#01_2034# / Register_Width,
1901 BCS_RING_BUFFER_HEAD => 16#02_2034# / Register_Width,
1902 RCS_RING_BUFFER_STRT => 16#00_2038# / Register_Width,
1903 VCS_RING_BUFFER_STRT => 16#01_2038# / Register_Width,
1904 BCS_RING_BUFFER_STRT => 16#02_2038# / Register_Width,
1905 RCS_RING_BUFFER_CTL => 16#00_203c# / Register_Width,
1906 VCS_RING_BUFFER_CTL => 16#01_203c# / Register_Width,
1907 BCS_RING_BUFFER_CTL => 16#02_203c# / Register_Width,
1908 MI_MODE => 16#00_209c# / Register_Width,
1909 INSTPM => 16#00_20c0# / Register_Width,
1910 GAB_CTL_REG => 16#02_4000# / Register_Width,
1911 PP_DCLV_HIGH => 16#00_2220# / Register_Width,
1912 PP_DCLV_LOW => 16#00_2228# / Register_Width,
1913 VCS_PP_DCLV_HIGH => 16#01_2220# / Register_Width,
1914 VCS_PP_DCLV_LOW => 16#01_2228# / Register_Width,
1915 BCS_PP_DCLV_HIGH => 16#02_2220# / Register_Width,
1916 BCS_PP_DCLV_LOW => 16#02_2228# / Register_Width,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1917 ILK_DISPLAY_CHICKEN2 => 16#04_2004# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1918 UCGCTL1 => 16#00_9400# / Register_Width,
1919 UCGCTL2 => 16#00_9404# / Register_Width,
1920 MBCTL => 16#00_907c# / Register_Width,
1921 HWSTAM => 16#00_2098# / Register_Width,
1922 VCS_HWSTAM => 16#01_2098# / Register_Width,
1923 BCS_HWSTAM => 16#02_2098# / Register_Width,
1924 IIR => 16#04_4028# / Register_Width,
1925 PIPE_FRMCNT_A => 16#07_0040# / Register_Width,
1926 PIPE_FRMCNT_B => 16#07_1040# / Register_Width,
1927 PIPE_FRMCNT_C => 16#07_2040# / Register_Width,
1928 FBC_CTL => 16#04_3208# / Register_Width,
1929 PIPE_VSYNCSHIFT_A => 16#06_0028# / Register_Width,
1930 PIPE_VSYNCSHIFT_B => 16#06_1028# / Register_Width,
1931 PIPE_VSYNCSHIFT_C => 16#06_2028# / Register_Width,
1932 WM_PIPE_A => 16#04_5100# / Register_Width,
1933 WM_PIPE_B => 16#04_5104# / Register_Width,
1934 WM_PIPE_C => 16#04_5200# / Register_Width,
1935 PIPE_SCANLINE_A => 16#07_0000# / Register_Width,
1936 PIPE_SCANLINE_B => 16#07_1000# / Register_Width,
1937 PIPE_SCANLINE_C => 16#07_2000# / Register_Width,
1938 GFX_MODE => 16#00_2520# / Register_Width,
1939 CACHE_MODE_0 => 16#00_2120# / Register_Width,
1940 SLEEP_PSMI_CONTROL => 16#01_2050# / Register_Width,
1941 CTX_SIZE => 16#00_21a0# / Register_Width,
1942 GAC_ECO_BITS => 16#01_4090# / Register_Width,
1943 GAM_ECOCHK => 16#00_4090# / Register_Width,
1944 QUIRK_02084 => 16#00_2084# / Register_Width,
1945 QUIRK_02090 => 16#00_2090# / Register_Width,
1946 GT_MODE => 16#00_20d0# / Register_Width,
1947 QUIRK_F0060 => 16#0f_0060# / Register_Width,
1948 QUIRK_F1060 => 16#0f_1060# / Register_Width,
1949 QUIRK_F2060 => 16#0f_2060# / Register_Width,
1950 AUD_CNTRL_ST2 => 16#0e_50c0# / Register_Width,
1951 AUD_CNTL_ST_A => 16#0e_50b4# / Register_Width,
1952 AUD_CNTL_ST_B => 16#0e_51b4# / Register_Width,
1953 AUD_CNTL_ST_C => 16#0e_52b4# / Register_Width,
1954 AUD_HDMIW_HDMIEDID_A => 16#0e_5050# / Register_Width,
1955 AUD_HDMIW_HDMIEDID_B => 16#0e_5150# / Register_Width,
1956 AUD_HDMIW_HDMIEDID_C => 16#0e_5250# / Register_Width,
1957 AUD_CONFIG_A => 16#0e_5000# / Register_Width,
1958 AUD_CONFIG_B => 16#0e_5100# / Register_Width,
1959 AUD_CONFIG_C => 16#0e_5200# / Register_Width,
1960 TRANS_DP_CTL_A => 16#0e_0300# / Register_Width,
1961 TRANS_DP_CTL_B => 16#0e_1300# / Register_Width,
1962 TRANS_DP_CTL_C => 16#0e_2300# / Register_Width,
1963 TRANS_VSYNCSHIFT_A => 16#0e_0028# / Register_Width,
1964 TRANS_VSYNCSHIFT_B => 16#0e_1028# / Register_Width,
1965 TRANS_VSYNCSHIFT_C => 16#0e_2028# / Register_Width,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]1966 PCH_RAWCLK_FREQ => 16#0c_6204# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1967 QUIRK_C2004 => 16#0c_2004# / Register_Width,
1968
1969 -- MCHBAR Mirror
1970
Nico Huberb47a5c42019-09-29 00:07:21 +0200[diff] [blame]1971 GMCH_CLKCFG => 16#01_0c00# / Register_Width,
1972 GMCH_HPLLVCO_MOBILE => 16#01_0c0f# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1973 GMCH_HPLLVCO => 16#01_0c38# / Register_Width,
1974
1975 -- Combo Phy Registers (Tigerlake on)
1976
1977 PHY_MISC_B => 16#06_4c04# / Register_Width,
1978 PHY_MISC_C => 16#06_4c08# / Register_Width,
1979 PORT_CL_DW5_A => 16#16_2014# / Register_Width,
1980 PORT_CL_DW5_B => 16#06_c014# / Register_Width,
1981 PORT_CL_DW5_C => 16#16_0014# / Register_Width,
1982 PORT_COMP_DW0_C => 16#16_0100# / Register_Width,
1983 PORT_COMP_DW1_C => 16#16_0104# / Register_Width,
1984 PORT_COMP_DW3_C => 16#16_010c# / Register_Width,
1985 PORT_COMP_DW8_C => 16#16_0120# / Register_Width,
1986 PORT_COMP_DW9_C => 16#16_0124# / Register_Width,
1987 PORT_COMP_DW10_C => 16#16_0128# / Register_Width,
1988 PORT_TX_DW8_LN0_A => 16#16_28a0# / Register_Width,
1989 PORT_TX_DW8_LN0_B => 16#06_c8a0# / Register_Width,
1990 PORT_TX_DW8_LN0_C => 16#16_08a0# / Register_Width,
1991 PORT_TX_DW8_GRP_A => 16#16_26a0# / Register_Width,
1992 PORT_TX_DW8_GRP_B => 16#06_c6a0# / Register_Width,
1993 PORT_TX_DW8_GRP_C => 16#16_06a0# / Register_Width,
1994 PORT_PCS_DW1_LN0_A => 16#16_2804# / Register_Width,
1995 PORT_PCS_DW1_LN0_B => 16#06_c804# / Register_Width,
1996 PORT_PCS_DW1_LN0_C => 16#16_0804# / Register_Width,
1997 PORT_PCS_DW1_GRP_A => 16#16_2604# / Register_Width,
1998 PORT_PCS_DW1_GRP_B => 16#06_c604# / Register_Width,
1999 PORT_PCS_DW1_GRP_C => 16#16_0604# / Register_Width,
2000 MBUS_ABOX_CTL => 16#04_5038# / Register_Width,
2001 MBUS_ABOX1_CTL => 16#04_5048# / Register_Width,
2002 MBUS_ABOX2_CTL => 16#04_504c# / Register_Width,
2003 BW_BUDDY1_PAGE_MASK => 16#04_5144# / Register_Width,
2004 BW_BUDDY2_PAGE_MASK => 16#04_5154# / Register_Width,
2005 BW_BUDDY1_CTL => 16#04_5140# / Register_Width,
2006 BW_BUDDY2_CTL => 16#04_5150# / Register_Width,
2007
2008 -- TGL DKL PHY registers
2009 HIP_INDEX_REG0 => 16#10_10a0# / Register_Width,
2010 HIP_INDEX_REG1 => 16#10_10a4# / Register_Width,
2011 -- Each type-C port PHY is addressed through a 4KB
2012 -- aperture. Each PHY has more than 4KB of register space, so a
2013 -- separate index is programmed in HIP_INDEX_REG0 or
2014 -- HIP_INDEX_REG1, based on the port number, to set the upper 2
2015 -- address bits that point the 4KB window into the full PHY
2016 -- register space.
2017 -- The registers below assumes index 2 has been programmed.
2018
2019 -- 16_8*** registers for DKL PHY 1
2020 DKL_CLKTOP2_HSCC_1 => 16#16_80d4# / Register_Width,
2021 DKL_CLKTOP2_CCC1_1 => 16#16_80d8# / Register_Width,
2022 DKL_REFCLKIN_CTL_1 => 16#16_812c# / Register_Width,
2023 DKL_PLL_DIV0_1 => 16#16_8200# / Register_Width,
2024 DKL_PLL_DIV1_1 => 16#16_8204# / Register_Width,
2025 DKL_PLL_SSC_1 => 16#16_8210# / Register_Width,
2026 DKL_PLL_BIAS_1 => 16#16_8214# / Register_Width,
2027 DKL_PLL_COLDST_BIAS_1 => 16#16_8218# / Register_Width,
2028 DKL_CMN_UC_DW_27_1 => 16#16_836c# / Register_Width,
2029 DKL_DP_MODE_1 => 16#16_80a0# / Register_Width,
2030 -- 16_9*** registers for DKL PHY 2
2031 DKL_CLKTOP2_HSCC_2 => 16#16_90d4# / Register_Width,
2032 DKL_CLKTOP2_CCC1_2 => 16#16_90d8# / Register_Width,
2033 DKL_REFCLKIN_CTL_2 => 16#16_912c# / Register_Width,
2034 DKL_PLL_DIV0_2 => 16#16_9200# / Register_Width,
2035 DKL_PLL_DIV1_2 => 16#16_9204# / Register_Width,
2036 DKL_PLL_SSC_2 => 16#16_9210# / Register_Width,
2037 DKL_PLL_BIAS_2 => 16#16_9214# / Register_Width,
2038 DKL_PLL_COLDST_BIAS_2 => 16#16_9218# / Register_Width,
2039 DKL_CMN_UC_DW_27_2 => 16#16_936c# / Register_Width,
2040 DKL_DP_MODE_2 => 16#16_90a0# / Register_Width,
2041 -- 16_a*** registers for DKL PHY 3
2042 DKL_CLKTOP2_HSCC_3 => 16#16_a0d4# / Register_Width,
2043 DKL_CLKTOP2_CCC1_3 => 16#16_a0d8# / Register_Width,
2044 DKL_REFCLKIN_CTL_3 => 16#16_a12c# / Register_Width,
2045 DKL_PLL_DIV0_3 => 16#16_a200# / Register_Width,
2046 DKL_PLL_DIV1_3 => 16#16_a204# / Register_Width,
2047 DKL_PLL_SSC_3 => 16#16_a210# / Register_Width,
2048 DKL_PLL_BIAS_3 => 16#16_a214# / Register_Width,
2049 DKL_PLL_COLDST_BIAS_3 => 16#16_a218# / Register_Width,
2050 DKL_CMN_UC_DW_27_3 => 16#16_a36c# / Register_Width,
2051 DKL_DP_MODE_3 => 16#16_a0a0# / Register_Width,
2052 -- 16_b*** registers for DKL PHY 4
2053 DKL_CLKTOP2_HSCC_4 => 16#16_b0d4# / Register_Width,
2054 DKL_CLKTOP2_CCC1_4 => 16#16_b0d8# / Register_Width,
2055 DKL_REFCLKIN_CTL_4 => 16#16_b12c# / Register_Width,
2056 DKL_PLL_DIV0_4 => 16#16_b200# / Register_Width,
2057 DKL_PLL_DIV1_4 => 16#16_b204# / Register_Width,
2058 DKL_PLL_SSC_4 => 16#16_b210# / Register_Width,
2059 DKL_PLL_BIAS_4 => 16#16_b214# / Register_Width,
2060 DKL_PLL_COLDST_BIAS_4 => 16#16_b218# / Register_Width,
2061 DKL_CMN_UC_DW_27_4 => 16#16_b36c# / Register_Width,
2062 DKL_DP_MODE_4 => 16#16_b0a0# / Register_Width,
2063 -- 16_c*** registers for DKL PHY 5
2064 DKL_CLKTOP2_HSCC_5 => 16#16_c0d4# / Register_Width,
2065 DKL_CLKTOP2_CCC1_5 => 16#16_c0d8# / Register_Width,
2066 DKL_REFCLKIN_CTL_5 => 16#16_c12c# / Register_Width,
2067 DKL_PLL_DIV0_5 => 16#16_c200# / Register_Width,
2068 DKL_PLL_DIV1_5 => 16#16_c204# / Register_Width,
2069 DKL_PLL_SSC_5 => 16#16_c210# / Register_Width,
2070 DKL_PLL_BIAS_5 => 16#16_c214# / Register_Width,
2071 DKL_PLL_COLDST_BIAS_5 => 16#16_c218# / Register_Width,
2072 DKL_CMN_UC_DW_27_5 => 16#16_c36c# / Register_Width,
2073 DKL_DP_MODE_5 => 16#16_c0a0# / Register_Width,
2074 -- 16_d*** registers for DKL PHY 6
2075 DKL_CLKTOP2_HSCC_6 => 16#16_d0d4# / Register_Width,
2076 DKL_CLKTOP2_CCC1_6 => 16#16_d0d8# / Register_Width,
2077 DKL_REFCLKIN_CTL_6 => 16#16_d12c# / Register_Width,
2078 DKL_PLL_DIV0_6 => 16#16_d200# / Register_Width,
2079 DKL_PLL_DIV1_6 => 16#16_d204# / Register_Width,
2080 DKL_PLL_SSC_6 => 16#16_d210# / Register_Width,
2081 DKL_PLL_BIAS_6 => 16#16_d214# / Register_Width,
2082 DKL_PLL_COLDST_BIAS_6 => 16#16_d218# / Register_Width,
2083 DKL_CMN_UC_DW_27_6 => 16#16_d36c# / Register_Width,
2084 DKL_DP_MODE_6 => 16#16_d0a0# / Register_Width,
2085
2086 -- TGL DPLL registers
2087 DPLL_4_ENABLE => 16#04_6018# / Register_Width,
2088 DPLL_0_CFGCR0 => 16#16_4284# / Register_Width,
2089 DPLL_0_CFGCR1 => 16#16_4288# / Register_Width,
2090 DPLL_1_CFGCR0 => 16#16_428c# / Register_Width,
2091 DPLL_1_CFGCR1 => 16#16_4290# / Register_Width,
2092 DPLL_4_CFGCR0 => 16#16_4294# / Register_Width,
2093 DPLL_4_CFGCR1 => 16#16_4298# / Register_Width,
2094 DPLL_0_SSC => 16#16_4b10# / Register_Width,
2095 DPLL_1_SSC => 16#16_4c10# / Register_Width,
2096 DPLL_4_SSC => 16#16_4e10# / Register_Width,
2097
2098 -- TGL DDI registers (some aliases too)
2099 DDI_BUF_CTL_USBC3 => 16#06_4500# / Register_Width,
2100 DDI_BUF_CTL_USBC4 => 16#06_4600# / Register_Width,
2101 DDI_BUF_CTL_USBC5 => 16#06_4700# / Register_Width,
2102 PORT_TX_DW2_LN0_A => 16#16_2888# / Register_Width,
2103 PORT_TX_DW2_LN0_B => 16#06_c888# / Register_Width,
2104 PORT_TX_DW2_LN0_C => 16#16_0888# / Register_Width,
2105 PORT_TX_DW2_GRP_A => 16#16_2688# / Register_Width,
2106 PORT_TX_DW2_GRP_B => 16#06_c688# / Register_Width,
2107 PORT_TX_DW2_GRP_C => 16#16_0688# / Register_Width,
2108 PORT_TX_DW4_LN0_A => 16#16_2890# / Register_Width,
2109 PORT_TX_DW4_LN1_A => 16#16_2990# / Register_Width,
2110 PORT_TX_DW4_LN2_A => 16#16_2a90# / Register_Width,
2111 PORT_TX_DW4_LN3_A => 16#16_2b90# / Register_Width,
2112 PORT_TX_DW4_LN0_B => 16#06_c890# / Register_Width,
2113 PORT_TX_DW4_LN1_B => 16#06_c990# / Register_Width,
2114 PORT_TX_DW4_LN2_B => 16#06_ca90# / Register_Width,
2115 PORT_TX_DW4_LN3_B => 16#06_cb90# / Register_Width,
2116 PORT_TX_DW4_LN0_C => 16#16_0890# / Register_Width,
2117 PORT_TX_DW4_LN1_C => 16#16_0990# / Register_Width,
2118 PORT_TX_DW4_LN2_C => 16#16_0a90# / Register_Width,
2119 PORT_TX_DW4_LN3_C => 16#16_0b90# / Register_Width,
2120 PORT_TX_DW4_GRP_A => 16#16_2690# / Register_Width,
2121 PORT_TX_DW4_GRP_B => 16#06_c690# / Register_Width,
2122 PORT_TX_DW4_GRP_C => 16#16_0690# / Register_Width,
2123 PORT_TX_DW5_LN0_A => 16#16_2894# / Register_Width,
2124 PORT_TX_DW5_LN0_B => 16#06_c894# / Register_Width,
2125 PORT_TX_DW5_LN0_C => 16#16_0894# / Register_Width,
2126 PORT_TX_DW5_GRP_A => 16#16_2694# / Register_Width,
2127 PORT_TX_DW5_GRP_B => 16#06_c694# / Register_Width,
2128 PORT_TX_DW5_GRP_C => 16#16_0694# / Register_Width,
2129 PORT_TX_DW7_LN0_A => 16#16_289c# / Register_Width,
2130 PORT_TX_DW7_LN0_B => 16#06_c89c# / Register_Width,
2131 PORT_TX_DW7_LN0_C => 16#16_089c# / Register_Width,
2132 PORT_TX_DW7_GRP_A => 16#16_269c# / Register_Width,
2133 PORT_TX_DW7_GRP_B => 16#06_c69c# / Register_Width,
2134 PORT_TX_DW7_GRP_C => 16#16_069c# / Register_Width,
2135
2136 -- TGL DisplayPort transport
2137 TGL_DP_TP_CTL_A => 16#06_0540# / Register_Width,
2138 TGL_DP_TP_CTL_B => 16#06_1540# / Register_Width,
2139 TGL_DP_TP_CTL_C => 16#06_2540# / Register_Width,
2140 TGL_DP_TP_STATUS_A => 16#06_0544# / Register_Width,
2141 TGL_DP_TP_STATUS_B => 16#06_1544# / Register_Width,
2142 TGL_DP_TP_STATUS_C => 16#06_2544# / Register_Width,
2143 DPCLKA_CFGCR0 => 16#16_4280# / Register_Width,
2144 PORT_CL_DW10_C => 16#16_0028# / Register_Width,
2145
2146 -- MBUS DBOX
2147 PIPE_MBUS_DBOX_CTL_A => 16#07_003c# / Register_Width,
2148 PIPE_MBUS_DBOX_CTL_B => 16#07_103c# / Register_Width,
2149 PIPE_MBUS_DBOX_CTL_C => 16#07_203c# / Register_Width,
2150
2151 -- TGL+ new plane control registers
2152 PLANE_AUX_DIST_1_A => 16#07_01c0# / Register_Width,
2153 PLANE_AUX_DIST_1_B => 16#07_11c0# / Register_Width,
2154 PLANE_AUX_DIST_1_C => 16#07_21c0# / Register_Width,
2155 PLANE_COLOR_CTL_1_A => 16#07_01cc# / Register_Width,
2156 PLANE_COLOR_CTL_1_B => 16#07_11cc# / Register_Width,
2157 PLANE_COLOR_CTL_1_C => 16#07_21cc# / Register_Width,
2158
2159 -- TGL FIA registers
2160 PORT_TX_DFLEXDPCSSS_FIA1 => 16#16_3894# / Register_Width,
2161 PORT_TX_DFLEXDPMLE1_FIA1 => 16#16_38c0# / Register_Width,
2162 PORT_TX_DFLEXDPPMS_FIA1 => 16#16_3890# / Register_Width,
2163 PORT_TX_DFLEXDPSP_FIA1 => 16#16_38a0# / Register_Width,
2164 PORT_TX_DFLEXPA1_FIA1 => 16#16_3880# / Register_Width,
2165 PORT_TX_DFLEXDPCSSS_FIA2 => 16#16_e894# / Register_Width,
2166 PORT_TX_DFLEXDPMLE1_FIA2 => 16#16_e8c0# / Register_Width,
2167 PORT_TX_DFLEXDPPMS_FIA2 => 16#16_e890# / Register_Width,
2168 PORT_TX_DFLEXDPSP_FIA2 => 16#16_e8a0# / Register_Width,
2169 PORT_TX_DFLEXPA1_FIA2 => 16#16_e880# / Register_Width,
2170 PORT_TX_DFLEXDPCSSS_FIA3 => 16#16_f894# / Register_Width,
2171 PORT_TX_DFLEXDPMLE1_FIA3 => 16#16_f8c0# / Register_Width,
2172 PORT_TX_DFLEXDPPMS_FIA3 => 16#16_f890# / Register_Width,
2173 PORT_TX_DFLEXDPSP_FIA3 => 16#16_f8a0# / Register_Width,
2174 PORT_TX_DFLEXPA1_FIA3 => 16#16_f880# / Register_Width,
2175
2176 -- TGL DDI clock select
2177 DDI_CLK_SEL_USBC3 => 16#04_6114# / Register_Width,
2178 DDI_CLK_SEL_USBC4 => 16#04_6118# / Register_Width,
2179 DDI_CLK_SEL_USBC5 => 16#04_611c# / Register_Width,
2180 DDI_CLK_SEL_USBC6 => 16#04_6120# / Register_Width,
2181
2182 -- TGL DKL PLLs
2183 MGPLL1_ENABLE => 16#04_6030# / Register_Width,
2184 MGPLL2_ENABLE => 16#04_6034# / Register_Width,
2185 MGPLL3_ENABLE => 16#04_6038# / Register_Width,
2186 MGPLL4_ENABLE => 16#04_603c# / Register_Width,
2187 MGPLL6_ENABLE => 16#04_6044# / Register_Width,
2188
2189 -- ADL-P DKL PLLs
2190 PORTTC3_PLL1_ENABLE => 16#04_6048# / Register_Width,
2191 PORTTC4_PLL0_ENABLE => 16#04_604c# / Register_Width,
2192 PORTTC4_PLL1_ENABLE => 16#04_6050# / Register_Width,
2193
2194 -- TGL DKL Vswing
2195 DKL_TX_PMD_LANE_SUS_1 => 16#16_8d00# / Register_Width,
2196 DKL_TX_PMD_LANE_SUS_2 => 16#16_9d00# / Register_Width,
2197 DKL_TX_PMD_LANE_SUS_3 => 16#16_ad00# / Register_Width,
2198 DKL_TX_PMD_LANE_SUS_4 => 16#16_bd00# / Register_Width,
2199 DKL_TX_PMD_LANE_SUS_5 => 16#16_cd00# / Register_Width,
2200 DKL_TX_PMD_LANE_SUS_6 => 16#16_dd00# / Register_Width,
2201 DKL_TX_DPCNTL0_1 => 16#16_82c0# / Register_Width,
2202 DKL_TX_DPCNTL0_2 => 16#16_92c0# / Register_Width,
2203 DKL_TX_DPCNTL0_3 => 16#16_a2c0# / Register_Width,
2204 DKL_TX_DPCNTL0_4 => 16#16_b2c0# / Register_Width,
2205 DKL_TX_DPCNTL0_5 => 16#16_c2c0# / Register_Width,
2206 DKL_TX_DPCNTL0_6 => 16#16_d2c0# / Register_Width,
2207 DKL_TX_DPCNTL1_1 => 16#16_82c4# / Register_Width,
2208 DKL_TX_DPCNTL1_2 => 16#16_92c4# / Register_Width,
2209 DKL_TX_DPCNTL1_3 => 16#16_a2c4# / Register_Width,
2210 DKL_TX_DPCNTL1_4 => 16#16_b2c4# / Register_Width,
2211 DKL_TX_DPCNTL1_5 => 16#16_c2c4# / Register_Width,
2212 DKL_TX_DPCNTL1_6 => 16#16_d2c4# / Register_Width,
2213 DKL_TX_DPCNTL2_1 => 16#16_82c8# / Register_Width,
2214 DKL_TX_DPCNTL2_2 => 16#16_92c8# / Register_Width,
2215 DKL_TX_DPCNTL2_3 => 16#16_a2c8# / Register_Width,
2216 DKL_TX_DPCNTL2_4 => 16#16_b2c8# / Register_Width,
2217 DKL_TX_DPCNTL2_5 => 16#16_c2c8# / Register_Width,
2218 DKL_TX_DPCNTL2_6 => 16#16_d2c8# / Register_Width,
2219
2220 -- ADL-P DKL registers
2221 DKL_PCS_DW5_1 => 16#16_8014# / Register_Width,
2222 DKL_PCS_DW5_2 => 16#16_9014# / Register_Width,
2223 DKL_PCS_DW5_3 => 16#16_a014# / Register_Width,
2224 DKL_PCS_DW5_4 => 16#16_b014# / Register_Width,
2225
2226 -- ADL-P DDI status
2227 TCSS_DDI_STATUS_1 => 16#16_1500# / Register_Width,
2228 TCSS_DDI_STATUS_2 => 16#16_1504# / Register_Width,
2229 TCSS_DDI_STATUS_3 => 16#16_1508# / Register_Width,
2230 TCSS_DDI_STATUS_4 => 16#16_150c# / Register_Width,
2231
2232 DISPLAY_ERR_FATAL_MASK => 16#04_421c# / Register_Width,
2233 MBUS_CTL => 16#04_438c# / Register_Width);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2234
2235 subtype Registers_Index is Registers_Invalid_Index range
2236 Registers_Invalid_Index'Succ (Invalid_Register) ..
2237 Registers_Invalid_Index'Last;
2238
2239 -- aliased registers
2240 DP_CTL_A : constant Registers_Index := DDI_BUF_CTL_A;
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]2241 GMCH_DP_B : constant Registers_Index := DDI_BUF_CTL_B;
2242 GMCH_DP_C : constant Registers_Index := DDI_BUF_CTL_C;
2243 GMCH_DP_D : constant Registers_Index := DDI_BUF_CTL_D;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2244 DP_AUX_CTL_A : constant Registers_Index := DDI_AUX_CTL_A;
2245 DP_AUX_DATA_A_1 : constant Registers_Index := DDI_AUX_DATA_A_1;
2246 DP_AUX_DATA_A_2 : constant Registers_Index := DDI_AUX_DATA_A_2;
2247 DP_AUX_DATA_A_3 : constant Registers_Index := DDI_AUX_DATA_A_3;
2248 DP_AUX_DATA_A_4 : constant Registers_Index := DDI_AUX_DATA_A_4;
2249 DP_AUX_DATA_A_5 : constant Registers_Index := DDI_AUX_DATA_A_5;
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]2250 ILK_DISPLAY_CHICKEN1 : constant Registers_Index := FUSE_STATUS;
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]2251 GMCH_ADPA : constant Registers_Index := FDI_TX_CTL_B;
2252 GMCH_HDMIB : constant Registers_Index := GMCH_SDVOB;
2253 GMCH_HDMIC : constant Registers_Index := GMCH_SDVOC;
Nico Huber75a707f2018-06-18 16:28:33 +0200[diff] [blame]2254 CURACNTR : constant Registers_Index := CUR_CTL_A;
2255 CURABASE : constant Registers_Index := CUR_BASE_A;
2256 CURAPOS : constant Registers_Index := CUR_POS_A;
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]2257 BXT_BLC_PWM_CTL_1 : constant Registers_Index := BLC_PWM_PCH_CTL1;
2258 BXT_BLC_PWM_FREQ_1 : constant Registers_Index := BLC_PWM_PCH_CTL2;
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]2259 PHY_MISC_A : constant Registers_Index := BXT_PHY_CTL_A;
2260 PORT_COMP_DW0_B : constant Registers_Index := BXT_PORT_PLL_0_B;
2261 PORT_COMP_DW1_B : constant Registers_Index := BXT_PORT_PLL_1_B;
2262 PORT_COMP_DW3_B : constant Registers_Index := BXT_PORT_PLL_3_B;
2263 PORT_COMP_DW0_A : constant Registers_Index := BXT_PORT_PLL_0_A;
2264 PORT_COMP_DW1_A : constant Registers_Index := BXT_PORT_PLL_1_A;
2265 PORT_COMP_DW3_A : constant Registers_Index := BXT_PORT_PLL_3_A;
2266 PORT_COMP_DW9_A : constant Registers_Index := BXT_PORT_PLL_9_A;
2267 PORT_COMP_DW9_B : constant Registers_Index := BXT_PORT_PLL_9_B;
2268 PORT_COMP_DW8_A : constant Registers_Index := BXT_PORT_PLL_8_A;
2269 PORT_COMP_DW8_B : constant Registers_Index := BXT_PORT_PLL_8_B;
2270 PORT_COMP_DW10_A : constant Registers_Index := BXT_PORT_PLL_10_A;
2271 PORT_COMP_DW10_B : constant Registers_Index := BXT_PORT_PLL_10_B;
2272 CDCLK_PLL_ENABLE : constant Registers_Index := BXT_DE_PLL_ENABLE;
2273 DDI_AUX_CTL_USBC1 : constant Registers_Index := DDI_AUX_CTL_D;
2274 DDI_AUX_DATA_USBC1_1 : constant Registers_Index := DDI_AUX_DATA_D_1;
2275 DDI_AUX_DATA_USBC1_2 : constant Registers_Index := DDI_AUX_DATA_D_2;
2276 DDI_AUX_DATA_USBC1_3 : constant Registers_Index := DDI_AUX_DATA_D_3;
2277 DDI_AUX_DATA_USBC1_4 : constant Registers_Index := DDI_AUX_DATA_D_4;
2278 DDI_AUX_DATA_USBC1_5 : constant Registers_Index := DDI_AUX_DATA_D_5;
2279 DPLL_0_ENABLE : constant Registers_Index := LCPLL1_CTL;
2280 DPLL_1_ENABLE : constant Registers_Index := LCPLL2_CTL;
2281 PORT_CL_DW10_A : constant Registers_Index := BXT_PORT_CL1CM_DW10_A;
2282 PORT_CL_DW10_B : constant Registers_Index := BXT_PORT_CL1CM_DW10_BC;
2283 DDI_CLK_SEL_USBC1 : constant Registers_Index := PORT_CLK_SEL_DDID;
2284 DDI_CLK_SEL_USBC2 : constant Registers_Index := PORT_CLK_SEL_DDIE;
2285 MGPLL5_ENABLE : constant Registers_Index := WRPLL_CTL_1;
2286 DDI_BUF_CTL_USBC1 : constant Registers_Index := DDI_BUF_CTL_D;
2287 DDI_BUF_CTL_USBC2 : constant Registers_Index := DDI_BUF_CTL_E;
2288 DDI_BUF_CTL_USBC6 : constant Registers_Index := SRD_CTL;
2289 PORTTC1_PLL0_ENABLE : constant Registers_Index := MGPLL2_ENABLE;
2290 PORTTC1_PLL1_ENABLE : constant Registers_Index := MGPLL3_ENABLE;
2291 PORTTC2_PLL0_ENABLE : constant Registers_Index := MGPLL4_ENABLE;
2292 PORTTC2_PLL1_ENABLE : constant Registers_Index := WRPLL_CTL_1;
2293 PORTTC3_PLL0_ENABLE : constant Registers_Index := MGPLL6_ENABLE;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2294
2295 ---------------------------------------------------------------------------
2296
2297 Default_Timeout_MS : constant := 10;
2298
2299 ---------------------------------------------------------------------------
2300
2301 procedure Posting_Read
2302 (Register : in Registers_Index)
2303 with
2304 Global => (In_Out => Register_State),
2305 Depends => (Register_State =>+ (Register)),
2306 Pre => True,
2307 Post => True;
2308
2309 pragma Warnings (GNATprove, Off, "unused variable ""Verbose""",
2310 Reason => "Only used on debugging path");
2311 procedure Read
2312 (Register : in Registers_Index;
2313 Value : out Word32;
2314 Verbose : in Boolean := True)
2315 with
2316 Global => (In_Out => Register_State),
2317 Depends => ((Value, Register_State) => (Register, Register_State),
2318 null => Verbose),
2319 Pre => True,
2320 Post => True;
2321 pragma Warnings (GNATprove, On, "unused variable ""Verbose""");
2322
2323 procedure Write
2324 (Register : Registers_Index;
2325 Value : Word32)
2326 with
2327 Global => (In_Out => Register_State),
2328 Depends => (Register_State => (Register, Register_State, Value)),
2329 Pre => True,
2330 Post => True;
2331
2332 procedure Is_Set_Mask
2333 (Register : in Registers_Index;
2334 Mask : in Word32;
2335 Result : out Boolean);
2336
2337 pragma Warnings (GNATprove, Off, "unused initial value of ""Verbose""",
2338 Reason => "Only used on debugging path");
Nico Huberbcb2c472017-02-02 16:39:26 +0100[diff] [blame]2339 procedure Wait
Nico Huber82ca09f2019-09-28 02:37:50 +0200[diff] [blame]2340 (Register : in Registers_Index;
2341 Mask : in Word32;
2342 Value : in Word32;
2343 TOut_MS : in Natural := Default_Timeout_MS;
2344 Verbose : in Boolean := False;
2345 Success : out Boolean);
2346 procedure Wait
Nico Huberbcb2c472017-02-02 16:39:26 +0100[diff] [blame]2347 (Register : Registers_Index;
2348 Mask : Word32;
2349 Value : Word32;
2350 TOut_MS : Natural := Default_Timeout_MS;
2351 Verbose : Boolean := False);
2352
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2353 procedure Wait_Set_Mask
Nico Huber82ca09f2019-09-28 02:37:50 +0200[diff] [blame]2354 (Register : in Registers_Index;
2355 Mask : in Word32;
2356 TOut_MS : in Natural := Default_Timeout_MS;
2357 Verbose : in Boolean := False;
2358 Success : out Boolean);
2359 procedure Wait_Set_Mask
2360 (Register : Registers_Index;
2361 Mask : Word32;
2362 TOut_MS : Natural := Default_Timeout_MS;
2363 Verbose : Boolean := False);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2364
2365 procedure Wait_Unset_Mask
Nico Huber82ca09f2019-09-28 02:37:50 +0200[diff] [blame]2366 (Register : in Registers_Index;
2367 Mask : in Word32;
2368 TOut_MS : in Natural := Default_Timeout_MS;
2369 Verbose : in Boolean := False;
2370 Success : out Boolean);
2371 procedure Wait_Unset_Mask
2372 (Register : Registers_Index;
2373 Mask : Word32;
2374 TOut_MS : Natural := Default_Timeout_MS;
2375 Verbose : Boolean := False);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2376 pragma Warnings (GNATprove, On, "unused initial value of ""Verbose""");
2377
2378 procedure Set_Mask
2379 (Register : Registers_Index;
2380 Mask : Word32);
2381
2382 procedure Unset_Mask
2383 (Register : Registers_Index;
2384 Mask : Word32);
2385
2386 procedure Unset_And_Set_Mask
2387 (Register : Registers_Index;
2388 Mask_Unset : Word32;
2389 Mask_Set : Word32);
2390
Nico Huber17d64b62017-07-15 20:51:25 +0200[diff] [blame]2391 procedure Clear_Fences;
2392
Nico Huberb03c8f12017-08-25 13:29:08 +0200[diff] [blame]2393 procedure Add_Fence
2394 (First_Page : in GTT_Range;
2395 Last_Page : in GTT_Range;
2396 Tiling : in XY_Tiling;
2397 Pitch : in Natural;
2398 Success : out Boolean);
2399
2400 procedure Remove_Fence (First_Page, Last_Page : GTT_Range);
2401
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]2402 pragma Warnings (GNATprove, Off, "no check message justified by this",
2403 Reason => "see Annotate aspects.");
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2404 procedure Write_GTT
2405 (GTT_Page : GTT_Range;
2406 Device_Address : GTT_Address_Type;
2407 Valid : Boolean)
2408 with
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]2409 Global =>
2410 (Input => Config.Variable,
2411 In_Out => GTT_State),
2412 Depends =>
2413 (GTT_State =>+ (Config.Variable, GTT_Page, Device_Address, Valid)),
2414 Annotate =>
2415 (GNATprove, Intentional,
Nico Hubere317e9c2019-09-29 03:03:18 +0200[diff] [blame]2416 """GMA.State"" of ""Write_GTT"" not read",
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]2417 "Reading of Config_State depends on the platform configuration.");
Nico Huberceda17d2018-06-09 22:00:29 +0200[diff] [blame]2418
2419 procedure Read_GTT
2420 (Device_Address : out GTT_Address_Type;
2421 Valid : out Boolean;
2422 GTT_Page : in GTT_Range)
2423 with
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]2424 Global =>
2425 (Input => Config.Variable,
2426 In_Out => GTT_State),
2427 Depends =>
2428 ((Device_Address, Valid, GTT_State) =>
2429 (Config.Variable, GTT_State, GTT_Page)),
2430 Annotate =>
2431 (GNATprove, Intentional,
Nico Hubere317e9c2019-09-29 03:03:18 +0200[diff] [blame]2432 """GMA.State"" of ""Read_GTT"" not read",
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]2433 "Reading of Config_State depends on the platform configuration.");
2434 pragma Warnings (GNATprove, On, "no check message justified by this");
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2435
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]2436 procedure Set_Register_Base (Base : Word64; GTT_Base : Word64 := 0)
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2437 with
2438 Global => (Output => Address_State),
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]2439 Depends => (Address_State => (Base, GTT_Base)),
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2440 Pre => True,
2441 Post => True;
2442
2443end HW.GFX.GMA.Registers;