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review.sourcearcade.org / libgfxinit / 902d803fa6c629f8aa1c31ca96aa460235cccd01 / . / common / hw-gfx-gma-registers.ads
blob: 025c5b5bef8441240e77fdf338105faca435b654 [file] [log] [blame]
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1--
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]2-- Copyright (C) 2015-2017 secunet Security Networks AG
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +0200[diff] [blame]6-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]8--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
15with System;
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]16with HW.GFX.GMA.Config;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]17
18private package HW.GFX.GMA.Registers
19with
20 Abstract_State =>
21 ((Address_State with Part_Of => GMA.State),
22 (Register_State with External, Part_Of => GMA.Device_State),
23 (GTT_State with External, Part_Of => GMA.Device_State)),
24 Initializes => Address_State
25is
Nico Huber0b2329a2018-06-09 21:14:27 +0200[diff] [blame]26
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]27 type Registers_Invalid_Index is
28 (Invalid_Register, -- Allow a placeholder when access is not acceptable
29
30 RCS_RING_BUFFER_TAIL,
31 RCS_RING_BUFFER_HEAD,
32 RCS_RING_BUFFER_STRT,
33 RCS_RING_BUFFER_CTL,
34 QUIRK_02084,
35 QUIRK_02090,
36 HWSTAM,
37 MI_MODE,
38 INSTPM,
39 GT_MODE,
40 CACHE_MODE_0,
41 CTX_SIZE,
42 PP_DCLV_HIGH,
43 PP_DCLV_LOW,
44 GFX_MODE,
45 ARB_MODE,
46 HWS_PGA,
47 GAM_ECOCHK,
Arthur Heymans229ed1c2018-03-28 16:45:43 +0200[diff] [blame]48 GMCH_GMBUS0,
49 GMCH_GMBUS1,
50 GMCH_GMBUS2,
51 GMCH_GMBUS3,
52 GMCH_GMBUS4,
53 GMCH_GMBUS5,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]54 GMCH_DPLL_A,
55 GMCH_DPLL_B,
56 GMCH_FPA0,
57 GMCH_FPA1,
58 GMCH_FPB0,
59 GMCH_FPB1,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]60 MBCTL,
61 UCGCTL1,
62 UCGCTL2,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]63 GMCH_CLKCFG,
Nico Huberb47a5c42019-09-29 00:07:21 +0200[diff] [blame]64 GMCH_HPLLVCO_MOBILE,
65 GMCH_HPLLVCO,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]66 VCS_RING_BUFFER_TAIL,
67 VCS_RING_BUFFER_HEAD,
68 VCS_RING_BUFFER_STRT,
69 VCS_RING_BUFFER_CTL,
70 SLEEP_PSMI_CONTROL,
71 VCS_HWSTAM,
72 VCS_PP_DCLV_HIGH,
73 VCS_PP_DCLV_LOW,
74 GAC_ECO_BITS,
75 BCS_RING_BUFFER_TAIL,
76 BCS_RING_BUFFER_HEAD,
77 BCS_RING_BUFFER_STRT,
78 BCS_RING_BUFFER_CTL,
79 BCS_HWSTAM,
80 BCS_PP_DCLV_HIGH,
81 BCS_PP_DCLV_LOW,
82 GAB_CTL_REG,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]83 CPU_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]84 FUSE_STATUS,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]85 ILK_DISPLAY_CHICKEN2,
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]86 FUSE_STRAP,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]87 DSPCLK_GATE_D,
88 FBA_CFB_BASE,
89 FBC_CTL,
90 IPS_CTL,
91 DEISR,
92 DEIMR,
93 DEIIR,
94 DEIER,
95 GTISR,
96 GTIMR,
97 GTIIR,
98 GTIER,
99 IIR,
100 HOTPLUG_CTL,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]101 TC_HOTPLUG_CTL,
102 DISPLAY_ERR_FATAL_MASK,
103 DBUF_CTL_S2,
104 DBUF_CTL_S3,
105 MBUS_CTL,
106 GEN11_DE_HPD_ISR,
107 DBUF_CTL_S1,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]108 ARB_CTL,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]109 DBUF_CTL_S0,
110 MBUS_ABOX_CTL,
111 MBUS_ABOX1_CTL,
112 MBUS_ABOX2_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]113 WM_PIPE_A,
114 WM_PIPE_B,
115 WM1_LP_ILK,
116 WM2_LP_ILK,
117 WM3_LP_ILK,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]118 BW_BUDDY1_CTL,
119 BW_BUDDY1_PAGE_MASK,
120 BW_BUDDY2_CTL,
121 BW_BUDDY2_PAGE_MASK,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]122 WM_PIPE_C,
123 WM_LINETIME_A,
124 WM_LINETIME_B,
125 WM_LINETIME_C,
126 PWR_WELL_CTL_BIOS,
127 PWR_WELL_CTL_DRIVER,
128 PWR_WELL_CTL_KVMR,
129 PWR_WELL_CTL_DEBUG,
130 PWR_WELL_CTL5,
131 PWR_WELL_CTL6,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]132 PWR_AUX_CTL_BIOS,
133 PWR_AUX_CTL_DRIVER,
134 PWR_DDI_CTL_BIOS,
135 PWR_DDI_CTL_DRIVER,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]136 CDCLK_CTL,
137 LCPLL1_CTL,
138 LCPLL2_CTL,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]139 DPLL_4_ENABLE,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]140 SPLL_CTL,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]141 MGPLL1_ENABLE,
142 MGPLL2_ENABLE,
143 MGPLL3_ENABLE,
144 MGPLL4_ENABLE,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]145 WRPLL_CTL_1,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]146 MGPLL6_ENABLE,
147 PORTTC3_PLL1_ENABLE,
148 PORTTC4_PLL0_ENABLE,
149 PORTTC4_PLL1_ENABLE,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]150 WRPLL_CTL_2,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]151 BXT_DE_PLL_ENABLE,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]152 BXT_PORT_PLL_ENABLE_A,
153 BXT_PORT_PLL_ENABLE_B,
154 BXT_PORT_PLL_ENABLE_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]155 PORT_CLK_SEL_DDIA,
156 PORT_CLK_SEL_DDIB,
157 PORT_CLK_SEL_DDIC,
158 PORT_CLK_SEL_DDID,
159 PORT_CLK_SEL_DDIE,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]160 DDI_CLK_SEL_USBC3,
161 DDI_CLK_SEL_USBC4,
162 DDI_CLK_SEL_USBC5,
163 DDI_CLK_SEL_USBC6,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]164 TRANSA_CLK_SEL,
165 TRANSB_CLK_SEL,
166 TRANSC_CLK_SEL,
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]167 CDCLK_FREQ,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]168 NDE_RSTWRN_OPT,
Angel Ponsae186bd2020-10-21 21:37:34 +0200[diff] [blame]169 GEN8_CHICKEN_DCPR_1,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]170 GEN11_CHICKEN_DCPR_2,
171 GEN9_CLKGATE_DIS_0,
172 GEN9_CHICKEN_DPCR_3,
173 GEN9_CLKGATE_DIS_5,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]174 BLC_PWM_CPU_CTL2,
175 BLC_PWM_CPU_CTL,
Nico Huber6b4678d2019-09-22 21:31:52 +0200[diff] [blame]176 DFSM,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]177 DSSM,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]178 HTOTAL_A,
179 HBLANK_A,
180 HSYNC_A,
181 VTOTAL_A,
182 VBLANK_A,
183 VSYNC_A,
184 PIPEASRC,
185 PIPE_VSYNCSHIFT_A,
186 PIPEA_DATA_M1,
187 PIPEA_DATA_N1,
188 PIPEA_LINK_M1,
189 PIPEA_LINK_N1,
190 FDI_TX_CTL_A,
191 PIPEA_DDI_FUNC_CTL,
192 PIPEA_MSA_MISC,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]193 TGL_DP_TP_CTL_A,
194 TGL_DP_TP_STATUS_A,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]195 SRD_CTL_A,
196 SRD_STATUS_A,
197 HTOTAL_B,
198 HBLANK_B,
199 HSYNC_B,
200 VTOTAL_B,
201 VBLANK_B,
202 VSYNC_B,
203 PIPEBSRC,
204 PIPE_VSYNCSHIFT_B,
205 PIPEB_DATA_M1,
206 PIPEB_DATA_N1,
207 PIPEB_LINK_M1,
208 PIPEB_LINK_N1,
209 FDI_TX_CTL_B,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]210 PORT_HOTPLUG_EN,
211 PORT_HOTPLUG_STAT,
212 GMCH_SDVOB,
213 GMCH_SDVOC,
214 GMCH_LVDS,
Arthur Heymanse87d0d12018-03-28 17:02:49 +0200[diff] [blame]215 GMCH_PP_STATUS,
216 GMCH_PP_CONTROL,
217 GMCH_PP_ON_DELAYS,
218 GMCH_PP_OFF_DELAYS,
219 GMCH_PP_DIVISOR,
Arthur Heymansd5198442018-03-28 17:05:12 +0200[diff] [blame]220 GMCH_PFIT_CONTROL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]221 PIPEB_DDI_FUNC_CTL,
222 PIPEB_MSA_MISC,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]223 TGL_DP_TP_CTL_B,
224 TGL_DP_TP_STATUS_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]225 SRD_CTL_B,
226 SRD_STATUS_B,
227 HTOTAL_C,
228 HBLANK_C,
229 HSYNC_C,
230 VTOTAL_C,
231 VBLANK_C,
232 VSYNC_C,
233 PIPECSRC,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]234 G4X_AUD_VID_DID,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]235 PIPE_VSYNCSHIFT_C,
236 PIPEC_DATA_M1,
237 PIPEC_DATA_N1,
238 PIPEC_LINK_M1,
239 PIPEC_LINK_N1,
240 FDI_TX_CTL_C,
241 PIPEC_DDI_FUNC_CTL,
242 PIPEC_MSA_MISC,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]243 TGL_DP_TP_CTL_C,
244 TGL_DP_TP_STATUS_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]245 SRD_CTL_C,
246 SRD_STATUS_C,
247 DDI_BUF_CTL_A,
248 DDI_AUX_CTL_A,
249 DDI_AUX_DATA_A_1,
250 DDI_AUX_DATA_A_2,
251 DDI_AUX_DATA_A_3,
252 DDI_AUX_DATA_A_4,
253 DDI_AUX_DATA_A_5,
254 DDI_AUX_MUTEX_A,
255 DP_TP_CTL_A,
256 DDI_BUF_CTL_B,
257 DDI_AUX_CTL_B,
258 DDI_AUX_DATA_B_1,
259 DDI_AUX_DATA_B_2,
260 DDI_AUX_DATA_B_3,
261 DDI_AUX_DATA_B_4,
262 DDI_AUX_DATA_B_5,
263 DDI_AUX_MUTEX_B,
264 DP_TP_CTL_B,
265 DP_TP_STATUS_B,
266 DDI_BUF_CTL_C,
267 DDI_AUX_CTL_C,
268 DDI_AUX_DATA_C_1,
269 DDI_AUX_DATA_C_2,
270 DDI_AUX_DATA_C_3,
271 DDI_AUX_DATA_C_4,
272 DDI_AUX_DATA_C_5,
273 DDI_AUX_MUTEX_C,
274 DP_TP_CTL_C,
275 DP_TP_STATUS_C,
276 DDI_BUF_CTL_D,
277 DDI_AUX_CTL_D,
278 DDI_AUX_DATA_D_1,
279 DDI_AUX_DATA_D_2,
280 DDI_AUX_DATA_D_3,
281 DDI_AUX_DATA_D_4,
282 DDI_AUX_DATA_D_5,
283 DDI_AUX_MUTEX_D,
284 DP_TP_CTL_D,
285 DP_TP_STATUS_D,
286 DDI_BUF_CTL_E,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]287 DDI_AUX_CTL_USBC2,
288 DDI_AUX_DATA_USBC2_1,
289 DDI_AUX_DATA_USBC2_2,
290 DDI_AUX_DATA_USBC2_3,
291 DDI_AUX_DATA_USBC2_4,
292 DDI_AUX_DATA_USBC2_5,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]293 DP_TP_CTL_E,
294 DP_TP_STATUS_E,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]295 DDI_BUF_CTL_USBC3,
296 DDI_AUX_CTL_USBC3,
297 DDI_AUX_DATA_USBC3_1,
298 DDI_AUX_DATA_USBC3_2,
299 DDI_AUX_DATA_USBC3_3,
300 DDI_AUX_DATA_USBC3_4,
301 DDI_AUX_DATA_USBC3_5,
302 DDI_BUF_CTL_USBC4,
303 DDI_AUX_CTL_USBC4,
304 DDI_AUX_DATA_USBC4_1,
305 DDI_AUX_DATA_USBC4_2,
306 DDI_AUX_DATA_USBC4_3,
307 DDI_AUX_DATA_USBC4_4,
308 DDI_AUX_DATA_USBC4_5,
309 DDI_BUF_CTL_USBC5,
310 DDI_AUX_CTL_USBC5,
311 DDI_AUX_DATA_USBC5_1,
312 DDI_AUX_DATA_USBC5_2,
313 DDI_AUX_DATA_USBC5_3,
314 DDI_AUX_DATA_USBC5_4,
315 DDI_AUX_DATA_USBC5_5,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]316 SRD_CTL,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]317 DDI_AUX_CTL_USBC6,
318 DDI_AUX_DATA_USBC6_1,
319 DDI_AUX_DATA_USBC6_2,
320 DDI_AUX_DATA_USBC6_3,
321 DDI_AUX_DATA_USBC6_4,
322 DDI_AUX_DATA_USBC6_5,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]323 SRD_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]324 BXT_PHY_CTL_A,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]325 PHY_MISC_B,
326 PHY_MISC_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]327 BXT_PHY_CTL_B,
328 BXT_PHY_CTL_C,
329 BXT_PHY_CTL_FAM_EDP,
330 BXT_PHY_CTL_FAM_DDI,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]331 DDI_BUF_TRANS_A_S0T1,
332 DDI_BUF_TRANS_A_S0T2,
333 DDI_BUF_TRANS_A_S1T1,
334 DDI_BUF_TRANS_A_S1T2,
335 DDI_BUF_TRANS_A_S2T1,
336 DDI_BUF_TRANS_A_S2T2,
337 DDI_BUF_TRANS_A_S3T1,
338 DDI_BUF_TRANS_A_S3T2,
339 DDI_BUF_TRANS_A_S4T1,
340 DDI_BUF_TRANS_A_S4T2,
341 DDI_BUF_TRANS_A_S5T1,
342 DDI_BUF_TRANS_A_S5T2,
343 DDI_BUF_TRANS_A_S6T1,
344 DDI_BUF_TRANS_A_S6T2,
345 DDI_BUF_TRANS_A_S7T1,
346 DDI_BUF_TRANS_A_S7T2,
347 DDI_BUF_TRANS_A_S8T1,
348 DDI_BUF_TRANS_A_S8T2,
349 DDI_BUF_TRANS_A_S9T1,
350 DDI_BUF_TRANS_A_S9T2,
351 DDI_BUF_TRANS_B_S0T1,
352 DDI_BUF_TRANS_B_S0T2,
353 DDI_BUF_TRANS_B_S1T1,
354 DDI_BUF_TRANS_B_S1T2,
355 DDI_BUF_TRANS_B_S2T1,
356 DDI_BUF_TRANS_B_S2T2,
357 DDI_BUF_TRANS_B_S3T1,
358 DDI_BUF_TRANS_B_S3T2,
359 DDI_BUF_TRANS_B_S4T1,
360 DDI_BUF_TRANS_B_S4T2,
361 DDI_BUF_TRANS_B_S5T1,
362 DDI_BUF_TRANS_B_S5T2,
363 DDI_BUF_TRANS_B_S6T1,
364 DDI_BUF_TRANS_B_S6T2,
365 DDI_BUF_TRANS_B_S7T1,
366 DDI_BUF_TRANS_B_S7T2,
367 DDI_BUF_TRANS_B_S8T1,
368 DDI_BUF_TRANS_B_S8T2,
369 DDI_BUF_TRANS_B_S9T1,
370 DDI_BUF_TRANS_B_S9T2,
371 DDI_BUF_TRANS_C_S0T1,
372 DDI_BUF_TRANS_C_S0T2,
373 DDI_BUF_TRANS_C_S1T1,
374 DDI_BUF_TRANS_C_S1T2,
375 DDI_BUF_TRANS_C_S2T1,
376 DDI_BUF_TRANS_C_S2T2,
377 DDI_BUF_TRANS_C_S3T1,
378 DDI_BUF_TRANS_C_S3T2,
379 DDI_BUF_TRANS_C_S4T1,
380 DDI_BUF_TRANS_C_S4T2,
381 DDI_BUF_TRANS_C_S5T1,
382 DDI_BUF_TRANS_C_S5T2,
383 DDI_BUF_TRANS_C_S6T1,
384 DDI_BUF_TRANS_C_S6T2,
385 DDI_BUF_TRANS_C_S7T1,
386 DDI_BUF_TRANS_C_S7T2,
387 DDI_BUF_TRANS_C_S8T1,
388 DDI_BUF_TRANS_C_S8T2,
389 DDI_BUF_TRANS_C_S9T1,
390 DDI_BUF_TRANS_C_S9T2,
391 DDI_BUF_TRANS_D_S0T1,
392 DDI_BUF_TRANS_D_S0T2,
393 DDI_BUF_TRANS_D_S1T1,
394 DDI_BUF_TRANS_D_S1T2,
395 DDI_BUF_TRANS_D_S2T1,
396 DDI_BUF_TRANS_D_S2T2,
397 DDI_BUF_TRANS_D_S3T1,
398 DDI_BUF_TRANS_D_S3T2,
399 DDI_BUF_TRANS_D_S4T1,
400 DDI_BUF_TRANS_D_S4T2,
401 DDI_BUF_TRANS_D_S5T1,
402 DDI_BUF_TRANS_D_S5T2,
403 DDI_BUF_TRANS_D_S6T1,
404 DDI_BUF_TRANS_D_S6T2,
405 DDI_BUF_TRANS_D_S7T1,
406 DDI_BUF_TRANS_D_S7T2,
407 DDI_BUF_TRANS_D_S8T1,
408 DDI_BUF_TRANS_D_S8T2,
409 DDI_BUF_TRANS_D_S9T1,
410 DDI_BUF_TRANS_D_S9T2,
411 DDI_BUF_TRANS_E_S0T1,
412 DDI_BUF_TRANS_E_S0T2,
413 DDI_BUF_TRANS_E_S1T1,
414 DDI_BUF_TRANS_E_S1T2,
415 DDI_BUF_TRANS_E_S2T1,
416 DDI_BUF_TRANS_E_S2T2,
417 DDI_BUF_TRANS_E_S3T1,
418 DDI_BUF_TRANS_E_S3T2,
419 DDI_BUF_TRANS_E_S4T1,
420 DDI_BUF_TRANS_E_S4T2,
421 DDI_BUF_TRANS_E_S5T1,
422 DDI_BUF_TRANS_E_S5T2,
423 DDI_BUF_TRANS_E_S6T1,
424 DDI_BUF_TRANS_E_S6T2,
425 DDI_BUF_TRANS_E_S7T1,
426 DDI_BUF_TRANS_E_S7T2,
427 DDI_BUF_TRANS_E_S8T1,
428 DDI_BUF_TRANS_E_S8T2,
429 DDI_BUF_TRANS_E_S9T1,
430 DDI_BUF_TRANS_E_S9T2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]431 AUD_VID_DID,
432 PFA_WIN_POS,
433 PFA_WIN_SZ,
434 PFA_CTL_1,
435 PS_WIN_POS_1_A,
436 PS_WIN_SZ_1_A,
437 PS_CTRL_1_A,
438 PS_WIN_POS_2_A,
439 PS_WIN_SZ_2_A,
440 PS_CTRL_2_A,
441 PFB_WIN_POS,
442 PFB_WIN_SZ,
443 PFB_CTL_1,
444 PS_WIN_POS_1_B,
445 PS_WIN_SZ_1_B,
446 PS_CTRL_1_B,
447 PS_WIN_POS_2_B,
448 PS_WIN_SZ_2_B,
449 PS_CTRL_2_B,
450 PFC_WIN_POS,
451 PFC_WIN_SZ,
452 PFC_CTL_1,
453 PS_WIN_POS_1_C,
454 PS_WIN_SZ_1_C,
455 PS_CTRL_1_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]456 BXT_PORT_CL1CM_DW0_BC,
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]457 DISPIO_CR_TX_BMU_CR0,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]458 PORT_CL_DW5_B,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]459 BXT_PORT_CL1CM_DW9_BC,
460 BXT_PORT_CL1CM_DW10_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]461 BXT_PORT_PLL_EBB_0_B,
462 BXT_PORT_PLL_EBB_4_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]463 DPLL1_CFGR1,
464 DPLL1_CFGR2,
465 DPLL2_CFGR1,
466 DPLL2_CFGR2,
467 DPLL3_CFGR1,
468 DPLL3_CFGR2,
469 DPLL_CTRL1,
470 DPLL_CTRL2,
471 DPLL_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]472 BXT_PORT_CL1CM_DW28_BC,
473 BXT_PORT_CL1CM_DW30_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]474 BXT_PORT_PLL_0_B,
475 BXT_PORT_PLL_1_B,
476 BXT_PORT_PLL_2_B,
477 BXT_PORT_PLL_3_B,
478 BXT_PORT_PLL_6_B,
479 BXT_PORT_PLL_8_B,
480 BXT_PORT_PLL_9_B,
481 BXT_PORT_PLL_10_B,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]482 BXT_PORT_REF_DW3_BC,
483 BXT_PORT_REF_DW6_BC,
484 BXT_PORT_REF_DW8_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]485 BXT_PORT_PLL_EBB_0_C,
486 BXT_PORT_PLL_EBB_4_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]487 BXT_PORT_CL2CM_DW6_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]488 BXT_PORT_PLL_0_C,
489 BXT_PORT_PLL_1_C,
490 BXT_PORT_PLL_2_C,
491 BXT_PORT_PLL_3_C,
492 BXT_PORT_PLL_6_C,
493 BXT_PORT_PLL_8_C,
494 BXT_PORT_PLL_9_C,
495 BXT_PORT_PLL_10_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]496 BXT_PORT_PCS_DW10_01_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]497 BXT_PORT_PCS_DW12_01_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]498 BXT_PORT_TX_DW2_LN0_B,
499 BXT_PORT_TX_DW3_LN0_B,
500 BXT_PORT_TX_DW4_LN0_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]501 BXT_PORT_TX_DW14_LN0_B,
502 BXT_PORT_TX_DW14_LN1_B,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]503 PORT_PCS_DW1_GRP_B,
504 PORT_TX_DW2_GRP_B,
505 PORT_TX_DW4_GRP_B,
506 PORT_TX_DW5_GRP_B,
507 PORT_TX_DW7_GRP_B,
508 PORT_TX_DW8_GRP_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]509 BXT_PORT_TX_DW14_LN2_B,
510 BXT_PORT_TX_DW14_LN3_B,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]511 PORT_PCS_DW1_LN0_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]512 BXT_PORT_PCS_DW10_01_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]513 BXT_PORT_PCS_DW12_01_C,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]514 PORT_TX_DW2_LN0_B,
515 PORT_TX_DW4_LN0_B,
516 PORT_TX_DW5_LN0_B,
517 PORT_TX_DW7_LN0_B,
518 PORT_TX_DW8_LN0_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]519 BXT_PORT_TX_DW2_LN0_C,
520 BXT_PORT_TX_DW3_LN0_C,
521 BXT_PORT_TX_DW4_LN0_C,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]522 BXT_PORT_TX_DW14_LN0_C,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]523 PORT_TX_DW4_LN1_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]524 BXT_PORT_TX_DW14_LN1_C,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]525 PORT_TX_DW4_LN2_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]526 BXT_PORT_TX_DW14_LN2_C,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]527 PORT_TX_DW4_LN3_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]528 BXT_PORT_TX_DW14_LN3_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]529 BXT_PORT_PCS_DW10_GRP_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]530 BXT_PORT_PCS_DW12_GRP_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]531 BXT_PORT_TX_DW2_GRP_B,
532 BXT_PORT_TX_DW3_GRP_B,
533 BXT_PORT_TX_DW4_GRP_B,
534 BXT_PORT_PCS_DW10_GRP_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]535 BXT_PORT_PCS_DW12_GRP_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]536 BXT_PORT_TX_DW2_GRP_C,
537 BXT_PORT_TX_DW3_GRP_C,
538 BXT_PORT_TX_DW4_GRP_C,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]539 BXT_DE_PLL_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]540 HTOTAL_EDP,
541 HBLANK_EDP,
542 HSYNC_EDP,
543 VTOTAL_EDP,
544 VBLANK_EDP,
545 VSYNC_EDP,
546 PIPE_EDP_DATA_M1,
547 PIPE_EDP_DATA_N1,
548 PIPE_EDP_LINK_M1,
549 PIPE_EDP_LINK_N1,
550 PIPE_EDP_DDI_FUNC_CTL,
551 PIPE_EDP_MSA_MISC,
552 SRD_CTL_EDP,
553 SRD_STATUS_EDP,
554 PIPE_SCANLINE_A,
555 PIPEACONF,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]556 PIPEA_ARB_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]557 PIPEAMISC,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]558 PIPEA_CHICKEN,
559 PIPE_MBUS_DBOX_CTL_A,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]560 PIPE_FRMCNT_A,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]561 PIPEA_GMCH_DATA_M,
562 PIPEA_GMCH_DATA_N,
563 PIPEA_GMCH_LINK_M,
564 PIPEA_GMCH_LINK_N,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]565 CUR_CTL_A,
566 CUR_BASE_A,
567 CUR_POS_A,
568 CUR_FBC_CTL_A,
Nico Huber75a707f2018-06-18 16:28:33 +0200[diff] [blame]569 CURBCNTR,
570 CURBBASE,
571 CURBPOS,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]572 CUR_WM_A_0,
573 CUR_WM_A_1,
574 CUR_WM_A_2,
575 CUR_WM_A_3,
576 CUR_WM_A_4,
577 CUR_WM_A_5,
578 CUR_WM_A_6,
579 CUR_WM_A_7,
580 CUR_BUF_CFG_A,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]581 DSPACNTR,
582 DSPALINOFF,
583 DSPASTRIDE,
584 PLANE_POS_1_A,
585 PLANE_SIZE_1_A,
586 DSPASURF,
587 DSPATILEOFF,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]588 PLANE_AUX_DIST_1_A,
589 PLANE_COLOR_CTL_1_A,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]590 PLANE_WM_1_A_0,
591 PLANE_WM_1_A_1,
592 PLANE_WM_1_A_2,
593 PLANE_WM_1_A_3,
594 PLANE_WM_1_A_4,
595 PLANE_WM_1_A_5,
596 PLANE_WM_1_A_6,
597 PLANE_WM_1_A_7,
598 PLANE_BUF_CFG_1_A,
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]599 PLANE_CTL_2_A,
600 PLANE_STRIDE_2_A,
601 PLANE_POS_2_A,
602 PLANE_SIZE_2_A,
603 PLANE_SURF_2_A,
604 PLANE_OFFSET_2_A,
605 PLANE_COLOR_CTL_2_A,
606 PLANE_WM_2_A_0,
607 PLANE_WM_2_A_1,
608 PLANE_WM_2_A_2,
609 PLANE_WM_2_A_3,
610 PLANE_WM_2_A_4,
611 PLANE_WM_2_A_5,
612 PLANE_WM_2_A_6,
613 PLANE_WM_2_A_7,
614 PLANE_BUF_CFG_2_A,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]615 PIPE_SCANLINE_B,
616 PIPEBCONF,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]617 PIPEB_ARB_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]618 PIPEBMISC,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]619 PIPEB_CHICKEN,
620 PIPE_MBUS_DBOX_CTL_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]621 PIPE_FRMCNT_B,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]622 PIPEB_GMCH_DATA_M,
623 PIPEB_GMCH_DATA_N,
624 PIPEB_GMCH_LINK_M,
625 PIPEB_GMCH_LINK_N,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]626 CUR_CTL_B,
627 CUR_BASE_B,
628 CUR_POS_B,
629 CUR_FBC_CTL_B,
630 CUR_WM_B_0,
631 CUR_WM_B_1,
632 CUR_WM_B_2,
633 CUR_WM_B_3,
634 CUR_WM_B_4,
635 CUR_WM_B_5,
636 CUR_WM_B_6,
637 CUR_WM_B_7,
638 CUR_BUF_CFG_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]639 DSPBCNTR,
640 DSPBLINOFF,
641 DSPBSTRIDE,
642 PLANE_POS_1_B,
643 PLANE_SIZE_1_B,
644 DSPBSURF,
645 DSPBTILEOFF,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]646 PLANE_AUX_DIST_1_B,
647 PLANE_COLOR_CTL_1_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]648 PLANE_WM_1_B_0,
649 PLANE_WM_1_B_1,
650 PLANE_WM_1_B_2,
651 PLANE_WM_1_B_3,
652 PLANE_WM_1_B_4,
653 PLANE_WM_1_B_5,
654 PLANE_WM_1_B_6,
655 PLANE_WM_1_B_7,
656 PLANE_BUF_CFG_1_B,
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]657 PLANE_CTL_2_B,
658 PLANE_STRIDE_2_B,
659 PLANE_POS_2_B,
660 PLANE_SIZE_2_B,
661 PLANE_SURF_2_B,
662 PLANE_OFFSET_2_B,
663 PLANE_COLOR_CTL_2_B,
664 PLANE_WM_2_B_0,
665 PLANE_WM_2_B_1,
666 PLANE_WM_2_B_2,
667 PLANE_WM_2_B_3,
668 PLANE_WM_2_B_4,
669 PLANE_WM_2_B_5,
670 PLANE_WM_2_B_6,
671 PLANE_WM_2_B_7,
672 PLANE_BUF_CFG_2_B,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]673 GMCH_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]674 PIPE_SCANLINE_C,
675 PIPECCONF,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]676 PIPEC_ARB_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]677 PIPECMISC,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]678 PIPEC_CHICKEN,
679 PIPE_MBUS_DBOX_CTL_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]680 PIPE_FRMCNT_C,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]681 CUR_CTL_C,
682 CUR_BASE_C,
683 CUR_POS_C,
684 CUR_FBC_CTL_C,
685 CUR_WM_C_0,
686 CUR_WM_C_1,
687 CUR_WM_C_2,
688 CUR_WM_C_3,
689 CUR_WM_C_4,
690 CUR_WM_C_5,
691 CUR_WM_C_6,
692 CUR_WM_C_7,
693 CUR_BUF_CFG_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]694 DSPCCNTR,
695 DSPCLINOFF,
696 DSPCSTRIDE,
697 PLANE_POS_1_C,
698 PLANE_SIZE_1_C,
699 DSPCSURF,
700 DSPCTILEOFF,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]701 PLANE_AUX_DIST_1_C,
702 PLANE_COLOR_CTL_1_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]703 PLANE_WM_1_C_0,
704 PLANE_WM_1_C_1,
705 PLANE_WM_1_C_2,
706 PLANE_WM_1_C_3,
707 PLANE_WM_1_C_4,
708 PLANE_WM_1_C_5,
709 PLANE_WM_1_C_6,
710 PLANE_WM_1_C_7,
711 PLANE_BUF_CFG_1_C,
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]712 PLANE_CTL_2_C,
713 PLANE_STRIDE_2_C,
714 PLANE_POS_2_C,
715 PLANE_SIZE_2_C,
716 PLANE_SURF_2_C,
717 PLANE_OFFSET_2_C,
718 PLANE_COLOR_CTL_2_C,
719 PLANE_WM_2_C_0,
720 PLANE_WM_2_C_1,
721 PLANE_WM_2_C_2,
722 PLANE_WM_2_C_3,
723 PLANE_WM_2_C_4,
724 PLANE_WM_2_C_5,
725 PLANE_WM_2_C_6,
726 PLANE_WM_2_C_7,
727 PLANE_BUF_CFG_2_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]728 PIPE_EDP_CONF,
729 PCH_FDI_CHICKEN_B_C,
730 QUIRK_C2004,
731 SFUSE_STRAP,
732 PCH_DSPCLK_GATE_D,
733 SDEISR,
734 SDEIMR,
735 SDEIIR,
736 SDEIER,
737 SHOTPLUG_CTL,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]738 SHOTPLUG_CTL_TC,
739 SHPD_FILTER_CNT,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]740 PCH_GMBUS0,
741 PCH_GMBUS1,
742 PCH_GMBUS2,
743 PCH_GMBUS3,
744 PCH_GMBUS4,
745 PCH_GMBUS5,
746 SBI_ADDR,
747 SBI_DATA,
748 SBI_CTL_STAT,
749 PCH_DPLL_A,
750 PCH_DPLL_B,
751 PCH_PIXCLK_GATE,
752 PCH_FPA0,
753 PCH_FPA1,
754 PCH_FPB0,
755 PCH_FPB1,
756 PCH_DREF_CONTROL,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]757 PCH_RAWCLK_FREQ,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]758 PCH_DPLL_SEL,
759 PCH_PP_STATUS,
760 PCH_PP_CONTROL,
761 PCH_PP_ON_DELAYS,
762 PCH_PP_OFF_DELAYS,
763 PCH_PP_DIVISOR,
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]764 BXT_PP_STATUS_2,
765 BXT_PP_CONTROL_2,
766 BXT_PP_ON_DELAYS_2,
767 BXT_PP_OFF_DELAYS_2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]768 BLC_PWM_PCH_CTL1,
769 BLC_PWM_PCH_CTL2,
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]770 BXT_BLC_PWM_DUTY_1,
771 BXT_BLC_PWM_CTL_2,
772 BXT_BLC_PWM_FREQ_2,
773 BXT_BLC_PWM_DUTY_2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]774 TRANS_HTOTAL_A,
775 TRANS_HBLANK_A,
776 TRANS_HSYNC_A,
777 TRANS_VTOTAL_A,
778 TRANS_VBLANK_A,
779 TRANS_VSYNC_A,
780 TRANS_VSYNCSHIFT_A,
781 TRANSA_DATA_M1,
782 TRANSA_DATA_N1,
783 TRANSA_DP_LINK_M1,
784 TRANSA_DP_LINK_N1,
785 TRANS_DP_CTL_A,
786 TRANS_HTOTAL_B,
787 TRANS_HBLANK_B,
788 TRANS_HSYNC_B,
789 TRANS_VTOTAL_B,
790 TRANS_VBLANK_B,
791 TRANS_VSYNC_B,
792 TRANS_VSYNCSHIFT_B,
793 TRANSB_DATA_M1,
794 TRANSB_DATA_N1,
795 TRANSB_DP_LINK_M1,
796 TRANSB_DP_LINK_N1,
797 PCH_ADPA,
798 PCH_HDMIB,
799 PCH_HDMIC,
800 PCH_HDMID,
801 PCH_LVDS,
802 TRANS_DP_CTL_B,
803 TRANS_HTOTAL_C,
804 TRANS_HBLANK_C,
805 TRANS_HSYNC_C,
806 TRANS_VTOTAL_C,
807 TRANS_VBLANK_C,
808 TRANS_VSYNC_C,
809 TRANS_VSYNCSHIFT_C,
810 TRANSC_DATA_M1,
811 TRANSC_DATA_N1,
812 TRANSC_DP_LINK_M1,
813 TRANSC_DP_LINK_N1,
814 TRANS_DP_CTL_C,
815 PCH_DP_B,
816 PCH_DP_AUX_CTL_B,
817 PCH_DP_AUX_DATA_B_1,
818 PCH_DP_AUX_DATA_B_2,
819 PCH_DP_AUX_DATA_B_3,
820 PCH_DP_AUX_DATA_B_4,
821 PCH_DP_AUX_DATA_B_5,
822 PCH_DP_C,
823 PCH_DP_AUX_CTL_C,
824 PCH_DP_AUX_DATA_C_1,
825 PCH_DP_AUX_DATA_C_2,
826 PCH_DP_AUX_DATA_C_3,
827 PCH_DP_AUX_DATA_C_4,
828 PCH_DP_AUX_DATA_C_5,
829 PCH_DP_D,
830 PCH_DP_AUX_CTL_D,
831 PCH_DP_AUX_DATA_D_1,
832 PCH_DP_AUX_DATA_D_2,
833 PCH_DP_AUX_DATA_D_3,
834 PCH_DP_AUX_DATA_D_4,
835 PCH_DP_AUX_DATA_D_5,
836 AUD_CONFIG_A,
837 PCH_AUD_VID_DID,
838 AUD_HDMIW_HDMIEDID_A,
839 AUD_CNTL_ST_A,
840 AUD_CNTRL_ST2,
841 AUD_CONFIG_B,
842 AUD_HDMIW_HDMIEDID_B,
843 AUD_CNTL_ST_B,
844 AUD_CONFIG_C,
845 AUD_HDMIW_HDMIEDID_C,
846 AUD_CNTL_ST_C,
847 TRANSACONF,
848 FDI_RXA_CTL,
849 FDI_RX_MISC_A,
850 FDI_RXA_IIR,
851 FDI_RXA_IMR,
852 FDI_RXA_TUSIZE1,
853 QUIRK_F0060,
854 TRANSA_CHICKEN2,
855 TRANSBCONF,
856 FDI_RXB_CTL,
857 FDI_RX_MISC_B,
858 FDI_RXB_IIR,
859 FDI_RXB_IMR,
860 FDI_RXB_TUSIZE1,
861 QUIRK_F1060,
862 TRANSB_CHICKEN2,
863 TRANSCCONF,
864 FDI_RXC_CTL,
865 FDI_RX_MISC_C,
866 FDI_RXC_IIR,
867 FDI_RXC_IMR,
868 FDI_RXC_TUSIZE1,
869 QUIRK_F2060,
870 TRANSC_CHICKEN2,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]871 HIP_INDEX_REG0,
872 HIP_INDEX_REG1,
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]873 LCPLL_CTL,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]874 BXT_P_CR_GT_DISP_PWRON,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]875 GT_MAILBOX,
876 GT_MAILBOX_DATA,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]877 GT_MAILBOX_DATA_1,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]878 PORT_CL_DW5_C,
879 PORT_CL_DW10_C,
880 PORT_COMP_DW0_C,
881 PORT_COMP_DW1_C,
882 PORT_COMP_DW3_C,
883 PORT_COMP_DW8_C,
884 PORT_COMP_DW9_C,
885 PORT_COMP_DW10_C,
886 PORT_PCS_DW1_GRP_C,
887 PORT_TX_DW2_GRP_C,
888 PORT_TX_DW4_GRP_C,
889 PORT_TX_DW5_GRP_C,
890 PORT_TX_DW7_GRP_C,
891 PORT_TX_DW8_GRP_C,
892 PORT_PCS_DW1_LN0_C,
893 PORT_TX_DW2_LN0_C,
894 PORT_TX_DW4_LN0_C,
895 PORT_TX_DW5_LN0_C,
896 PORT_TX_DW7_LN0_C,
897 PORT_TX_DW8_LN0_C,
898 PORT_TX_DW4_LN1_C,
899 PORT_TX_DW4_LN2_C,
900 PORT_TX_DW4_LN3_C,
901 TCSS_DDI_STATUS_1,
902 TCSS_DDI_STATUS_2,
903 TCSS_DDI_STATUS_3,
904 TCSS_DDI_STATUS_4,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]905 BXT_PORT_CL1CM_DW0_A,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]906 PORT_CL_DW5_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]907 BXT_PORT_CL1CM_DW9_A,
908 BXT_PORT_CL1CM_DW10_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]909 BXT_PORT_PLL_EBB_0_A,
910 BXT_PORT_PLL_EBB_4_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]911 BXT_PORT_CL1CM_DW28_A,
912 BXT_PORT_CL1CM_DW30_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]913 BXT_PORT_PLL_0_A,
914 BXT_PORT_PLL_1_A,
915 BXT_PORT_PLL_2_A,
916 BXT_PORT_PLL_3_A,
917 BXT_PORT_PLL_6_A,
918 BXT_PORT_PLL_8_A,
919 BXT_PORT_PLL_9_A,
920 BXT_PORT_PLL_10_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]921 BXT_PORT_REF_DW3_A,
922 BXT_PORT_REF_DW6_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]923 BXT_PORT_REF_DW8_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]924 BXT_PORT_PCS_DW10_01_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]925 BXT_PORT_PCS_DW12_01_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]926 BXT_PORT_TX_DW2_LN0_A,
927 BXT_PORT_TX_DW3_LN0_A,
928 BXT_PORT_TX_DW4_LN0_A,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]929 BXT_PORT_TX_DW14_LN0_A,
930 BXT_PORT_TX_DW14_LN1_A,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]931 PORT_PCS_DW1_GRP_A,
932 PORT_TX_DW2_GRP_A,
933 PORT_TX_DW4_GRP_A,
934 PORT_TX_DW5_GRP_A,
935 PORT_TX_DW7_GRP_A,
936 PORT_TX_DW8_GRP_A,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]937 BXT_PORT_TX_DW14_LN2_A,
938 BXT_PORT_TX_DW14_LN3_A,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]939 PORT_PCS_DW1_LN0_A,
940 PORT_TX_DW2_LN0_A,
941 PORT_TX_DW4_LN0_A,
942 PORT_TX_DW5_LN0_A,
943 PORT_TX_DW7_LN0_A,
944 PORT_TX_DW8_LN0_A,
945 PORT_TX_DW4_LN1_A,
946 PORT_TX_DW4_LN2_A,
947 PORT_TX_DW4_LN3_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]948 BXT_PORT_PCS_DW10_GRP_A,
949 BXT_PORT_PCS_DW12_GRP_A,
950 BXT_PORT_TX_DW2_GRP_A,
951 BXT_PORT_TX_DW3_GRP_A,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]952 BXT_PORT_TX_DW4_GRP_A,
953 PORT_TX_DFLEXPA1_FIA1,
954 PORT_TX_DFLEXDPPMS_FIA1,
955 PORT_TX_DFLEXDPCSSS_FIA1,
956 PORT_TX_DFLEXDPSP_FIA1,
957 PORT_TX_DFLEXDPMLE1_FIA1,
958 DPCLKA_CFGCR0,
959 DPLL_0_CFGCR0,
960 DPLL_0_CFGCR1,
961 DPLL_1_CFGCR0,
962 DPLL_1_CFGCR1,
963 DPLL_4_CFGCR0,
964 DPLL_4_CFGCR1,
965 DPLL_0_SSC,
966 DPLL_1_SSC,
967 DPLL_4_SSC,
968 DKL_PCS_DW5_1,
969 DKL_DP_MODE_1,
970 DKL_CLKTOP2_HSCC_1,
971 DKL_CLKTOP2_CCC1_1,
972 DKL_REFCLKIN_CTL_1,
973 DKL_PLL_DIV0_1,
974 DKL_PLL_DIV1_1,
975 DKL_PLL_SSC_1,
976 DKL_PLL_BIAS_1,
977 DKL_PLL_COLDST_BIAS_1,
978 DKL_TX_DPCNTL0_1,
979 DKL_TX_DPCNTL1_1,
980 DKL_TX_DPCNTL2_1,
981 DKL_CMN_UC_DW_27_1,
982 DKL_TX_PMD_LANE_SUS_1,
983 DKL_PCS_DW5_2,
984 DKL_DP_MODE_2,
985 DKL_CLKTOP2_HSCC_2,
986 DKL_CLKTOP2_CCC1_2,
987 DKL_REFCLKIN_CTL_2,
988 DKL_PLL_DIV0_2,
989 DKL_PLL_DIV1_2,
990 DKL_PLL_SSC_2,
991 DKL_PLL_BIAS_2,
992 DKL_PLL_COLDST_BIAS_2,
993 DKL_TX_DPCNTL0_2,
994 DKL_TX_DPCNTL1_2,
995 DKL_TX_DPCNTL2_2,
996 DKL_CMN_UC_DW_27_2,
997 DKL_TX_PMD_LANE_SUS_2,
998 DKL_PCS_DW5_3,
999 DKL_DP_MODE_3,
1000 DKL_CLKTOP2_HSCC_3,
1001 DKL_CLKTOP2_CCC1_3,
1002 DKL_REFCLKIN_CTL_3,
1003 DKL_PLL_DIV0_3,
1004 DKL_PLL_DIV1_3,
1005 DKL_PLL_SSC_3,
1006 DKL_PLL_BIAS_3,
1007 DKL_PLL_COLDST_BIAS_3,
1008 DKL_TX_DPCNTL0_3,
1009 DKL_TX_DPCNTL1_3,
1010 DKL_TX_DPCNTL2_3,
1011 DKL_CMN_UC_DW_27_3,
1012 DKL_TX_PMD_LANE_SUS_3,
1013 DKL_PCS_DW5_4,
1014 DKL_DP_MODE_4,
1015 DKL_CLKTOP2_HSCC_4,
1016 DKL_CLKTOP2_CCC1_4,
1017 DKL_REFCLKIN_CTL_4,
1018 DKL_PLL_DIV0_4,
1019 DKL_PLL_DIV1_4,
1020 DKL_PLL_SSC_4,
1021 DKL_PLL_BIAS_4,
1022 DKL_PLL_COLDST_BIAS_4,
1023 DKL_TX_DPCNTL0_4,
1024 DKL_TX_DPCNTL1_4,
1025 DKL_TX_DPCNTL2_4,
1026 DKL_CMN_UC_DW_27_4,
1027 DKL_TX_PMD_LANE_SUS_4,
1028 DKL_DP_MODE_5,
1029 DKL_CLKTOP2_HSCC_5,
1030 DKL_CLKTOP2_CCC1_5,
1031 DKL_REFCLKIN_CTL_5,
1032 DKL_PLL_DIV0_5,
1033 DKL_PLL_DIV1_5,
1034 DKL_PLL_SSC_5,
1035 DKL_PLL_BIAS_5,
1036 DKL_PLL_COLDST_BIAS_5,
1037 DKL_TX_DPCNTL0_5,
1038 DKL_TX_DPCNTL1_5,
1039 DKL_TX_DPCNTL2_5,
1040 DKL_CMN_UC_DW_27_5,
1041 DKL_TX_PMD_LANE_SUS_5,
1042 DKL_DP_MODE_6,
1043 DKL_CLKTOP2_HSCC_6,
1044 DKL_CLKTOP2_CCC1_6,
1045 DKL_REFCLKIN_CTL_6,
1046 DKL_PLL_DIV0_6,
1047 DKL_PLL_DIV1_6,
1048 DKL_PLL_SSC_6,
1049 DKL_PLL_BIAS_6,
1050 DKL_PLL_COLDST_BIAS_6,
1051 DKL_TX_DPCNTL0_6,
1052 DKL_TX_DPCNTL1_6,
1053 DKL_TX_DPCNTL2_6,
1054 DKL_CMN_UC_DW_27_6,
1055 DKL_TX_PMD_LANE_SUS_6,
1056 PORT_TX_DFLEXPA1_FIA2,
1057 PORT_TX_DFLEXDPPMS_FIA2,
1058 PORT_TX_DFLEXDPCSSS_FIA2,
1059 PORT_TX_DFLEXDPSP_FIA2,
1060 PORT_TX_DFLEXDPMLE1_FIA2,
1061 PORT_TX_DFLEXPA1_FIA3,
1062 PORT_TX_DFLEXDPPMS_FIA3,
1063 PORT_TX_DFLEXDPCSSS_FIA3,
1064 PORT_TX_DFLEXDPSP_FIA3,
1065 PORT_TX_DFLEXDPMLE1_FIA3);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1066 pragma Warnings
1067 (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)",
1068 Reason => "TODO: Should it matter?");
1069 pragma Keep_Names (Registers_Invalid_Index);
1070 pragma Warnings
1071 (GNATprove, On, "pragma ""KEEP_NAMES"" ignored *(not yet supported)");
1072
1073 Register_Width : constant := 4;
1074
1075 for Registers_Invalid_Index use
1076 (Invalid_Register => 0,
1077
1078 ---------------------------------------------------------------------------
1079 -- Pipe A registers
1080 ---------------------------------------------------------------------------
1081
1082 -- pipe timing registers
1083
1084 HTOTAL_A => 16#06_0000# / Register_Width,
1085 HBLANK_A => 16#06_0004# / Register_Width,
1086 HSYNC_A => 16#06_0008# / Register_Width,
1087 VTOTAL_A => 16#06_000c# / Register_Width,
1088 VBLANK_A => 16#06_0010# / Register_Width,
1089 VSYNC_A => 16#06_0014# / Register_Width,
1090 PIPEASRC => 16#06_001c# / Register_Width,
1091 PIPEACONF => 16#07_0008# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1092 PIPEA_ARB_CTL => 16#07_0028# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1093 PIPEAMISC => 16#07_0030# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1094 PIPEA_CHICKEN => 16#07_0038# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1095 TRANS_HTOTAL_A => 16#0e_0000# / Register_Width,
1096 TRANS_HBLANK_A => 16#0e_0004# / Register_Width,
1097 TRANS_HSYNC_A => 16#0e_0008# / Register_Width,
1098 TRANS_VTOTAL_A => 16#0e_000c# / Register_Width,
1099 TRANS_VBLANK_A => 16#0e_0010# / Register_Width,
1100 TRANS_VSYNC_A => 16#0e_0014# / Register_Width,
1101 TRANSA_DATA_M1 => 16#0e_0030# / Register_Width,
1102 TRANSA_DATA_N1 => 16#0e_0034# / Register_Width,
1103 TRANSA_DP_LINK_M1 => 16#0e_0040# / Register_Width,
1104 TRANSA_DP_LINK_N1 => 16#0e_0044# / Register_Width,
1105 PIPEA_DATA_M1 => 16#06_0030# / Register_Width,
1106 PIPEA_DATA_N1 => 16#06_0034# / Register_Width,
1107 PIPEA_LINK_M1 => 16#06_0040# / Register_Width,
1108 PIPEA_LINK_N1 => 16#06_0044# / Register_Width,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]1109 PIPEA_GMCH_DATA_M => 16#07_0050# / Register_Width,
1110 PIPEA_GMCH_DATA_N => 16#07_0054# / Register_Width,
1111 PIPEA_GMCH_LINK_M => 16#07_0060# / Register_Width,
1112 PIPEA_GMCH_LINK_N => 16#07_0064# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1113 PIPEA_DDI_FUNC_CTL => 16#06_0400# / Register_Width,
1114 PIPEA_MSA_MISC => 16#06_0410# / Register_Width,
1115
1116 -- PCH sideband interface registers
1117 SBI_ADDR => 16#0c_6000# / Register_Width,
1118 SBI_DATA => 16#0c_6004# / Register_Width,
1119 SBI_CTL_STAT => 16#0c_6008# / Register_Width,
1120
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1121 -- GMCH clock registers
1122 GMCH_DPLL_A => 16#00_6014# / Register_Width,
1123 GMCH_FPA0 => 16#00_6040# / Register_Width,
1124 GMCH_FPA1 => 16#00_6044# / Register_Width,
1125
1126 -- PCH clock registers
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1127 PCH_DPLL_A => 16#0c_6014# / Register_Width,
1128 PCH_PIXCLK_GATE => 16#0c_6020# / Register_Width,
1129 PCH_FPA0 => 16#0c_6040# / Register_Width,
1130 PCH_FPA1 => 16#0c_6044# / Register_Width,
1131
1132 -- panel fitter
1133 PFA_CTL_1 => 16#06_8080# / Register_Width,
1134 PFA_WIN_POS => 16#06_8070# / Register_Width,
1135 PFA_WIN_SZ => 16#06_8074# / Register_Width,
1136 PS_WIN_POS_1_A => 16#06_8170# / Register_Width,
1137 PS_WIN_SZ_1_A => 16#06_8174# / Register_Width,
1138 PS_CTRL_1_A => 16#06_8180# / Register_Width,
1139 PS_WIN_POS_2_A => 16#06_8270# / Register_Width,
1140 PS_WIN_SZ_2_A => 16#06_8274# / Register_Width,
1141 PS_CTRL_2_A => 16#06_8280# / Register_Width,
1142
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1143 -- cursor control
1144 CUR_CTL_A => 16#07_0080# / Register_Width,
1145 CUR_BASE_A => 16#07_0084# / Register_Width,
1146 CUR_POS_A => 16#07_0088# / Register_Width,
1147 CUR_FBC_CTL_A => 16#07_00a0# / Register_Width,
1148
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1149 -- display control
1150 DSPACNTR => 16#07_0180# / Register_Width,
1151 DSPALINOFF => 16#07_0184# / Register_Width,
1152 DSPASTRIDE => 16#07_0188# / Register_Width,
1153 PLANE_POS_1_A => 16#07_018c# / Register_Width,
1154 PLANE_SIZE_1_A => 16#07_0190# / Register_Width,
1155 DSPASURF => 16#07_019c# / Register_Width,
1156 DSPATILEOFF => 16#07_01a4# / Register_Width,
1157
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]1158 -- sprite / second plane control
1159 PLANE_CTL_2_A => 16#07_0280# / Register_Width,
1160 PLANE_STRIDE_2_A => 16#07_0288# / Register_Width,
1161 PLANE_POS_2_A => 16#07_028c# / Register_Width,
1162 PLANE_SIZE_2_A => 16#07_0290# / Register_Width,
1163 PLANE_SURF_2_A => 16#07_029c# / Register_Width,
1164 PLANE_OFFSET_2_A => 16#07_02a4# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1165
1166 -- FDI and PCH transcoder control
1167 FDI_TX_CTL_A => 16#06_0100# / Register_Width,
1168 FDI_RXA_CTL => 16#0f_000c# / Register_Width,
1169 FDI_RX_MISC_A => 16#0f_0010# / Register_Width,
1170 FDI_RXA_IIR => 16#0f_0014# / Register_Width,
1171 FDI_RXA_IMR => 16#0f_0018# / Register_Width,
1172 FDI_RXA_TUSIZE1 => 16#0f_0030# / Register_Width,
1173 TRANSACONF => 16#0f_0008# / Register_Width,
1174 TRANSA_CHICKEN2 => 16#0f_0064# / Register_Width,
1175
1176 -- watermark registers
1177 WM_LINETIME_A => 16#04_5270# / Register_Width,
1178 PLANE_WM_1_A_0 => 16#07_0240# / Register_Width,
1179 PLANE_WM_1_A_1 => 16#07_0244# / Register_Width,
1180 PLANE_WM_1_A_2 => 16#07_0248# / Register_Width,
1181 PLANE_WM_1_A_3 => 16#07_024c# / Register_Width,
1182 PLANE_WM_1_A_4 => 16#07_0250# / Register_Width,
1183 PLANE_WM_1_A_5 => 16#07_0254# / Register_Width,
1184 PLANE_WM_1_A_6 => 16#07_0258# / Register_Width,
1185 PLANE_WM_1_A_7 => 16#07_025c# / Register_Width,
1186 PLANE_BUF_CFG_1_A => 16#07_027c# / Register_Width,
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]1187 PLANE_WM_2_A_0 => 16#07_0340# / Register_Width,
1188 PLANE_WM_2_A_1 => 16#07_0344# / Register_Width,
1189 PLANE_WM_2_A_2 => 16#07_0348# / Register_Width,
1190 PLANE_WM_2_A_3 => 16#07_034c# / Register_Width,
1191 PLANE_WM_2_A_4 => 16#07_0350# / Register_Width,
1192 PLANE_WM_2_A_5 => 16#07_0354# / Register_Width,
1193 PLANE_WM_2_A_6 => 16#07_0358# / Register_Width,
1194 PLANE_WM_2_A_7 => 16#07_035c# / Register_Width,
1195 PLANE_BUF_CFG_2_A => 16#07_037c# / Register_Width,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1196 CUR_WM_A_0 => 16#07_0140# / Register_Width,
1197 CUR_WM_A_1 => 16#07_0144# / Register_Width,
1198 CUR_WM_A_2 => 16#07_0148# / Register_Width,
1199 CUR_WM_A_3 => 16#07_014c# / Register_Width,
1200 CUR_WM_A_4 => 16#07_0150# / Register_Width,
1201 CUR_WM_A_5 => 16#07_0154# / Register_Width,
1202 CUR_WM_A_6 => 16#07_0158# / Register_Width,
1203 CUR_WM_A_7 => 16#07_015c# / Register_Width,
1204 CUR_BUF_CFG_A => 16#07_017c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1205
1206 -- CPU transcoder clock select
1207 TRANSA_CLK_SEL => 16#04_6140# / Register_Width,
1208
1209 ---------------------------------------------------------------------------
1210 -- Pipe B registers
1211 ---------------------------------------------------------------------------
1212
1213 -- pipe timing registers
1214
1215 HTOTAL_B => 16#06_1000# / Register_Width,
1216 HBLANK_B => 16#06_1004# / Register_Width,
1217 HSYNC_B => 16#06_1008# / Register_Width,
1218 VTOTAL_B => 16#06_100c# / Register_Width,
1219 VBLANK_B => 16#06_1010# / Register_Width,
1220 VSYNC_B => 16#06_1014# / Register_Width,
1221 PIPEBSRC => 16#06_101c# / Register_Width,
1222 PIPEBCONF => 16#07_1008# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1223 PIPEB_ARB_CTL => 16#07_1028# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1224 PIPEBMISC => 16#07_1030# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1225 PIPEB_CHICKEN => 16#07_1038# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1226 TRANS_HTOTAL_B => 16#0e_1000# / Register_Width,
1227 TRANS_HBLANK_B => 16#0e_1004# / Register_Width,
1228 TRANS_HSYNC_B => 16#0e_1008# / Register_Width,
1229 TRANS_VTOTAL_B => 16#0e_100c# / Register_Width,
1230 TRANS_VBLANK_B => 16#0e_1010# / Register_Width,
1231 TRANS_VSYNC_B => 16#0e_1014# / Register_Width,
1232 TRANSB_DATA_M1 => 16#0e_1030# / Register_Width,
1233 TRANSB_DATA_N1 => 16#0e_1034# / Register_Width,
1234 TRANSB_DP_LINK_M1 => 16#0e_1040# / Register_Width,
1235 TRANSB_DP_LINK_N1 => 16#0e_1044# / Register_Width,
1236 PIPEB_DATA_M1 => 16#06_1030# / Register_Width,
1237 PIPEB_DATA_N1 => 16#06_1034# / Register_Width,
1238 PIPEB_LINK_M1 => 16#06_1040# / Register_Width,
1239 PIPEB_LINK_N1 => 16#06_1044# / Register_Width,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]1240 PIPEB_GMCH_DATA_M => 16#07_1050# / Register_Width,
1241 PIPEB_GMCH_DATA_N => 16#07_1054# / Register_Width,
1242 PIPEB_GMCH_LINK_M => 16#07_1060# / Register_Width,
1243 PIPEB_GMCH_LINK_N => 16#07_1064# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1244 PIPEB_DDI_FUNC_CTL => 16#06_1400# / Register_Width,
1245 PIPEB_MSA_MISC => 16#06_1410# / Register_Width,
1246
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1247 -- GMCH clock registers
1248 GMCH_DPLL_B => 16#00_6018# / Register_Width,
1249 GMCH_FPB0 => 16#00_6048# / Register_Width,
1250 GMCH_FPB1 => 16#00_604c# / Register_Width,
1251
1252 -- PCH clock registers
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1253 PCH_DPLL_B => 16#0c_6018# / Register_Width,
1254 PCH_FPB0 => 16#0c_6048# / Register_Width,
1255 PCH_FPB1 => 16#0c_604c# / Register_Width,
1256
1257 -- panel fitter
1258 PFB_CTL_1 => 16#06_8880# / Register_Width,
1259 PFB_WIN_POS => 16#06_8870# / Register_Width,
1260 PFB_WIN_SZ => 16#06_8874# / Register_Width,
1261 PS_WIN_POS_1_B => 16#06_8970# / Register_Width,
1262 PS_WIN_SZ_1_B => 16#06_8974# / Register_Width,
1263 PS_CTRL_1_B => 16#06_8980# / Register_Width,
1264 PS_WIN_POS_2_B => 16#06_8a70# / Register_Width,
1265 PS_WIN_SZ_2_B => 16#06_8a74# / Register_Width,
1266 PS_CTRL_2_B => 16#06_8a80# / Register_Width,
1267
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1268 -- cursor control
Nico Huber75a707f2018-06-18 16:28:33 +0200[diff] [blame]1269 CURBCNTR => 16#07_00c0# / Register_Width, -- <= SNB
1270 CURBBASE => 16#07_00c4# / Register_Width, -- <= SNB
1271 CURBPOS => 16#07_00c8# / Register_Width, -- <= SNB
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1272 CUR_CTL_B => 16#07_1080# / Register_Width,
1273 CUR_BASE_B => 16#07_1084# / Register_Width,
1274 CUR_POS_B => 16#07_1088# / Register_Width,
1275 CUR_FBC_CTL_B => 16#07_10a0# / Register_Width,
1276
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1277 -- display control
1278 DSPBCNTR => 16#07_1180# / Register_Width,
1279 DSPBLINOFF => 16#07_1184# / Register_Width,
1280 DSPBSTRIDE => 16#07_1188# / Register_Width,
1281 PLANE_POS_1_B => 16#07_118c# / Register_Width,
1282 PLANE_SIZE_1_B => 16#07_1190# / Register_Width,
1283 DSPBSURF => 16#07_119c# / Register_Width,
1284 DSPBTILEOFF => 16#07_11a4# / Register_Width,
1285
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]1286 -- sprite / second plane control
1287 PLANE_CTL_2_B => 16#07_1280# / Register_Width,
1288 PLANE_STRIDE_2_B => 16#07_1288# / Register_Width,
1289 PLANE_POS_2_B => 16#07_128c# / Register_Width,
1290 PLANE_SIZE_2_B => 16#07_1290# / Register_Width,
1291 PLANE_SURF_2_B => 16#07_129c# / Register_Width,
1292 PLANE_OFFSET_2_B => 16#07_12a4# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1293
1294 -- FDI and PCH transcoder control
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1295 FDI_TX_CTL_B => 16#06_1100# / Register_Width, -- aliased by GMCH_ADPA
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1296 FDI_RXB_CTL => 16#0f_100c# / Register_Width,
1297 FDI_RX_MISC_B => 16#0f_1010# / Register_Width,
1298 FDI_RXB_IIR => 16#0f_1014# / Register_Width,
1299 FDI_RXB_IMR => 16#0f_1018# / Register_Width,
1300 FDI_RXB_TUSIZE1 => 16#0f_1030# / Register_Width,
1301 TRANSBCONF => 16#0f_1008# / Register_Width,
1302 TRANSB_CHICKEN2 => 16#0f_1064# / Register_Width,
1303
1304 -- watermark registers
1305 WM_LINETIME_B => 16#04_5274# / Register_Width,
1306 PLANE_WM_1_B_0 => 16#07_1240# / Register_Width,
1307 PLANE_WM_1_B_1 => 16#07_1244# / Register_Width,
1308 PLANE_WM_1_B_2 => 16#07_1248# / Register_Width,
1309 PLANE_WM_1_B_3 => 16#07_124c# / Register_Width,
1310 PLANE_WM_1_B_4 => 16#07_1250# / Register_Width,
1311 PLANE_WM_1_B_5 => 16#07_1254# / Register_Width,
1312 PLANE_WM_1_B_6 => 16#07_1258# / Register_Width,
1313 PLANE_WM_1_B_7 => 16#07_125c# / Register_Width,
1314 PLANE_BUF_CFG_1_B => 16#07_127c# / Register_Width,
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]1315 PLANE_WM_2_B_0 => 16#07_1340# / Register_Width,
1316 PLANE_WM_2_B_1 => 16#07_1344# / Register_Width,
1317 PLANE_WM_2_B_2 => 16#07_1348# / Register_Width,
1318 PLANE_WM_2_B_3 => 16#07_134c# / Register_Width,
1319 PLANE_WM_2_B_4 => 16#07_1350# / Register_Width,
1320 PLANE_WM_2_B_5 => 16#07_1354# / Register_Width,
1321 PLANE_WM_2_B_6 => 16#07_1358# / Register_Width,
1322 PLANE_WM_2_B_7 => 16#07_135c# / Register_Width,
1323 PLANE_BUF_CFG_2_B => 16#07_137c# / Register_Width,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1324 CUR_WM_B_0 => 16#07_1140# / Register_Width,
1325 CUR_WM_B_1 => 16#07_1144# / Register_Width,
1326 CUR_WM_B_2 => 16#07_1148# / Register_Width,
1327 CUR_WM_B_3 => 16#07_114c# / Register_Width,
1328 CUR_WM_B_4 => 16#07_1150# / Register_Width,
1329 CUR_WM_B_5 => 16#07_1154# / Register_Width,
1330 CUR_WM_B_6 => 16#07_1158# / Register_Width,
1331 CUR_WM_B_7 => 16#07_115c# / Register_Width,
1332 CUR_BUF_CFG_B => 16#07_117c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1333
1334 -- CPU transcoder clock select
1335 TRANSB_CLK_SEL => 16#04_6144# / Register_Width,
1336
1337 ---------------------------------------------------------------------------
1338 -- Pipe C registers
1339 ---------------------------------------------------------------------------
1340
1341 -- pipe timing registers
1342
1343 HTOTAL_C => 16#06_2000# / Register_Width,
1344 HBLANK_C => 16#06_2004# / Register_Width,
1345 HSYNC_C => 16#06_2008# / Register_Width,
1346 VTOTAL_C => 16#06_200c# / Register_Width,
1347 VBLANK_C => 16#06_2010# / Register_Width,
1348 VSYNC_C => 16#06_2014# / Register_Width,
1349 PIPECSRC => 16#06_201c# / Register_Width,
1350 PIPECCONF => 16#07_2008# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1351 PIPEC_ARB_CTL => 16#07_2028# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1352 PIPECMISC => 16#07_2030# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1353 PIPEC_CHICKEN => 16#07_2038# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1354 TRANS_HTOTAL_C => 16#0e_2000# / Register_Width,
1355 TRANS_HBLANK_C => 16#0e_2004# / Register_Width,
1356 TRANS_HSYNC_C => 16#0e_2008# / Register_Width,
1357 TRANS_VTOTAL_C => 16#0e_200c# / Register_Width,
1358 TRANS_VBLANK_C => 16#0e_2010# / Register_Width,
1359 TRANS_VSYNC_C => 16#0e_2014# / Register_Width,
1360 TRANSC_DATA_M1 => 16#0e_2030# / Register_Width,
1361 TRANSC_DATA_N1 => 16#0e_2034# / Register_Width,
1362 TRANSC_DP_LINK_M1 => 16#0e_2040# / Register_Width,
1363 TRANSC_DP_LINK_N1 => 16#0e_2044# / Register_Width,
1364 PIPEC_DATA_M1 => 16#06_2030# / Register_Width,
1365 PIPEC_DATA_N1 => 16#06_2034# / Register_Width,
1366 PIPEC_LINK_M1 => 16#06_2040# / Register_Width,
1367 PIPEC_LINK_N1 => 16#06_2044# / Register_Width,
1368 PIPEC_DDI_FUNC_CTL => 16#06_2400# / Register_Width,
1369 PIPEC_MSA_MISC => 16#06_2410# / Register_Width,
1370
1371 -- panel fitter
1372 PFC_CTL_1 => 16#06_9080# / Register_Width,
1373 PFC_WIN_POS => 16#06_9070# / Register_Width,
1374 PFC_WIN_SZ => 16#06_9074# / Register_Width,
1375 PS_WIN_POS_1_C => 16#06_9170# / Register_Width,
1376 PS_WIN_SZ_1_C => 16#06_9174# / Register_Width,
1377 PS_CTRL_1_C => 16#06_9180# / Register_Width,
1378
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1379 -- cursor control
1380 CUR_CTL_C => 16#07_2080# / Register_Width,
1381 CUR_BASE_C => 16#07_2084# / Register_Width,
1382 CUR_POS_C => 16#07_2088# / Register_Width,
1383 CUR_FBC_CTL_C => 16#07_20a0# / Register_Width,
1384
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1385 -- display control
1386 DSPCCNTR => 16#07_2180# / Register_Width,
1387 DSPCLINOFF => 16#07_2184# / Register_Width,
1388 DSPCSTRIDE => 16#07_2188# / Register_Width,
1389 PLANE_POS_1_C => 16#07_218c# / Register_Width,
1390 PLANE_SIZE_1_C => 16#07_2190# / Register_Width,
1391 DSPCSURF => 16#07_219c# / Register_Width,
1392 DSPCTILEOFF => 16#07_21a4# / Register_Width,
1393
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]1394 -- sprite / second plane control
1395 PLANE_CTL_2_C => 16#07_2280# / Register_Width,
1396 PLANE_STRIDE_2_C => 16#07_2288# / Register_Width,
1397 PLANE_POS_2_C => 16#07_228c# / Register_Width,
1398 PLANE_SIZE_2_C => 16#07_2290# / Register_Width,
1399 PLANE_SURF_2_C => 16#07_229c# / Register_Width,
1400 PLANE_OFFSET_2_C => 16#07_22a4# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1401
1402 -- PCH transcoder control
1403 FDI_TX_CTL_C => 16#06_2100# / Register_Width,
1404 FDI_RXC_CTL => 16#0f_200c# / Register_Width,
1405 FDI_RX_MISC_C => 16#0f_2010# / Register_Width,
1406 FDI_RXC_IIR => 16#0f_2014# / Register_Width,
1407 FDI_RXC_IMR => 16#0f_2018# / Register_Width,
1408 FDI_RXC_TUSIZE1 => 16#0f_2030# / Register_Width,
1409 TRANSCCONF => 16#0f_2008# / Register_Width,
1410 TRANSC_CHICKEN2 => 16#0f_2064# / Register_Width,
1411
1412 -- watermark registers
1413 WM_LINETIME_C => 16#04_5278# / Register_Width,
1414 PLANE_WM_1_C_0 => 16#07_2240# / Register_Width,
1415 PLANE_WM_1_C_1 => 16#07_2244# / Register_Width,
1416 PLANE_WM_1_C_2 => 16#07_2248# / Register_Width,
1417 PLANE_WM_1_C_3 => 16#07_224c# / Register_Width,
1418 PLANE_WM_1_C_4 => 16#07_2250# / Register_Width,
1419 PLANE_WM_1_C_5 => 16#07_2254# / Register_Width,
1420 PLANE_WM_1_C_6 => 16#07_2258# / Register_Width,
1421 PLANE_WM_1_C_7 => 16#07_225c# / Register_Width,
1422 PLANE_BUF_CFG_1_C => 16#07_227c# / Register_Width,
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]1423 PLANE_WM_2_C_0 => 16#07_2340# / Register_Width,
1424 PLANE_WM_2_C_1 => 16#07_2344# / Register_Width,
1425 PLANE_WM_2_C_2 => 16#07_2348# / Register_Width,
1426 PLANE_WM_2_C_3 => 16#07_234c# / Register_Width,
1427 PLANE_WM_2_C_4 => 16#07_2350# / Register_Width,
1428 PLANE_WM_2_C_5 => 16#07_2354# / Register_Width,
1429 PLANE_WM_2_C_6 => 16#07_2358# / Register_Width,
1430 PLANE_WM_2_C_7 => 16#07_235c# / Register_Width,
1431 PLANE_BUF_CFG_2_C => 16#07_237c# / Register_Width,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1432 CUR_WM_C_0 => 16#07_2140# / Register_Width,
1433 CUR_WM_C_1 => 16#07_2144# / Register_Width,
1434 CUR_WM_C_2 => 16#07_2148# / Register_Width,
1435 CUR_WM_C_3 => 16#07_214c# / Register_Width,
1436 CUR_WM_C_4 => 16#07_2150# / Register_Width,
1437 CUR_WM_C_5 => 16#07_2154# / Register_Width,
1438 CUR_WM_C_6 => 16#07_2158# / Register_Width,
1439 CUR_WM_C_7 => 16#07_215c# / Register_Width,
1440 CUR_BUF_CFG_C => 16#07_217c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1441
1442 -- CPU transcoder clock select
1443 TRANSC_CLK_SEL => 16#04_6148# / Register_Width,
1444
1445 ---------------------------------------------------------------------------
1446 -- Pipe EDP registers
1447 ---------------------------------------------------------------------------
1448
1449 -- pipe timing registers
1450
1451 HTOTAL_EDP => 16#06_f000# / Register_Width,
1452 HBLANK_EDP => 16#06_f004# / Register_Width,
1453 HSYNC_EDP => 16#06_f008# / Register_Width,
1454 VTOTAL_EDP => 16#06_f00c# / Register_Width,
1455 VBLANK_EDP => 16#06_f010# / Register_Width,
1456 VSYNC_EDP => 16#06_f014# / Register_Width,
1457 PIPE_EDP_CONF => 16#07_f008# / Register_Width,
1458 PIPE_EDP_DATA_M1 => 16#06_f030# / Register_Width,
1459 PIPE_EDP_DATA_N1 => 16#06_f034# / Register_Width,
1460 PIPE_EDP_LINK_M1 => 16#06_f040# / Register_Width,
1461 PIPE_EDP_LINK_N1 => 16#06_f044# / Register_Width,
1462 PIPE_EDP_DDI_FUNC_CTL => 16#06_f400# / Register_Width,
1463 PIPE_EDP_MSA_MISC => 16#06_f410# / Register_Width,
1464
1465 -- PSR registers
1466 SRD_CTL => 16#06_4800# / Register_Width,
1467 SRD_CTL_A => 16#06_0800# / Register_Width,
1468 SRD_CTL_B => 16#06_1800# / Register_Width,
1469 SRD_CTL_C => 16#06_2800# / Register_Width,
1470 SRD_CTL_EDP => 16#06_f800# / Register_Width,
1471 SRD_STATUS => 16#06_4840# / Register_Width,
1472 SRD_STATUS_A => 16#06_0840# / Register_Width,
1473 SRD_STATUS_B => 16#06_1840# / Register_Width,
1474 SRD_STATUS_C => 16#06_2840# / Register_Width,
1475 SRD_STATUS_EDP => 16#06_f840# / Register_Width,
1476
1477 -- DDI registers
1478 DDI_BUF_CTL_A => 16#06_4000# / Register_Width, -- aliased by DP_CTL_A
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1479 DDI_BUF_TRANS_A_S0T1 => 16#06_4e00# / Register_Width,
1480 DDI_BUF_TRANS_A_S0T2 => 16#06_4e04# / Register_Width,
1481 DDI_BUF_TRANS_A_S1T1 => 16#06_4e08# / Register_Width,
1482 DDI_BUF_TRANS_A_S1T2 => 16#06_4e0c# / Register_Width,
1483 DDI_BUF_TRANS_A_S2T1 => 16#06_4e10# / Register_Width,
1484 DDI_BUF_TRANS_A_S2T2 => 16#06_4e14# / Register_Width,
1485 DDI_BUF_TRANS_A_S3T1 => 16#06_4e18# / Register_Width,
1486 DDI_BUF_TRANS_A_S3T2 => 16#06_4e1c# / Register_Width,
1487 DDI_BUF_TRANS_A_S4T1 => 16#06_4e20# / Register_Width,
1488 DDI_BUF_TRANS_A_S4T2 => 16#06_4e24# / Register_Width,
1489 DDI_BUF_TRANS_A_S5T1 => 16#06_4e28# / Register_Width,
1490 DDI_BUF_TRANS_A_S5T2 => 16#06_4e2c# / Register_Width,
1491 DDI_BUF_TRANS_A_S6T1 => 16#06_4e30# / Register_Width,
1492 DDI_BUF_TRANS_A_S6T2 => 16#06_4e34# / Register_Width,
1493 DDI_BUF_TRANS_A_S7T1 => 16#06_4e38# / Register_Width,
1494 DDI_BUF_TRANS_A_S7T2 => 16#06_4e3c# / Register_Width,
1495 DDI_BUF_TRANS_A_S8T1 => 16#06_4e40# / Register_Width,
1496 DDI_BUF_TRANS_A_S8T2 => 16#06_4e44# / Register_Width,
1497 DDI_BUF_TRANS_A_S9T1 => 16#06_4e48# / Register_Width,
1498 DDI_BUF_TRANS_A_S9T2 => 16#06_4e4c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1499 DDI_AUX_CTL_A => 16#06_4010# / Register_Width, -- aliased by DP_AUX_CTL_A
1500 DDI_AUX_DATA_A_1 => 16#06_4014# / Register_Width, -- aliased by DP_AUX_DATA_A_1
1501 DDI_AUX_DATA_A_2 => 16#06_4018# / Register_Width, -- aliased by DP_AUX_DATA_A_2
1502 DDI_AUX_DATA_A_3 => 16#06_401c# / Register_Width, -- aliased by DP_AUX_DATA_A_3
1503 DDI_AUX_DATA_A_4 => 16#06_4020# / Register_Width, -- aliased by DP_AUX_DATA_A_4
1504 DDI_AUX_DATA_A_5 => 16#06_4024# / Register_Width, -- aliased by DP_AUX_DATA_A_5
1505 DDI_AUX_MUTEX_A => 16#06_402c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1506
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1507 DDI_BUF_CTL_B => 16#06_4100# / Register_Width, -- aliased by GMCH_DP_B
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1508 DDI_BUF_TRANS_B_S0T1 => 16#06_4e60# / Register_Width,
1509 DDI_BUF_TRANS_B_S0T2 => 16#06_4e64# / Register_Width,
1510 DDI_BUF_TRANS_B_S1T1 => 16#06_4e68# / Register_Width,
1511 DDI_BUF_TRANS_B_S1T2 => 16#06_4e6c# / Register_Width,
1512 DDI_BUF_TRANS_B_S2T1 => 16#06_4e70# / Register_Width,
1513 DDI_BUF_TRANS_B_S2T2 => 16#06_4e74# / Register_Width,
1514 DDI_BUF_TRANS_B_S3T1 => 16#06_4e78# / Register_Width,
1515 DDI_BUF_TRANS_B_S3T2 => 16#06_4e7c# / Register_Width,
1516 DDI_BUF_TRANS_B_S4T1 => 16#06_4e80# / Register_Width,
1517 DDI_BUF_TRANS_B_S4T2 => 16#06_4e84# / Register_Width,
1518 DDI_BUF_TRANS_B_S5T1 => 16#06_4e88# / Register_Width,
1519 DDI_BUF_TRANS_B_S5T2 => 16#06_4e8c# / Register_Width,
1520 DDI_BUF_TRANS_B_S6T1 => 16#06_4e90# / Register_Width,
1521 DDI_BUF_TRANS_B_S6T2 => 16#06_4e94# / Register_Width,
1522 DDI_BUF_TRANS_B_S7T1 => 16#06_4e98# / Register_Width,
1523 DDI_BUF_TRANS_B_S7T2 => 16#06_4e9c# / Register_Width,
1524 DDI_BUF_TRANS_B_S8T1 => 16#06_4ea0# / Register_Width,
1525 DDI_BUF_TRANS_B_S8T2 => 16#06_4ea4# / Register_Width,
1526 DDI_BUF_TRANS_B_S9T1 => 16#06_4ea8# / Register_Width,
1527 DDI_BUF_TRANS_B_S9T2 => 16#06_4eac# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1528 DDI_AUX_CTL_B => 16#06_4110# / Register_Width,
1529 DDI_AUX_DATA_B_1 => 16#06_4114# / Register_Width,
1530 DDI_AUX_DATA_B_2 => 16#06_4118# / Register_Width,
1531 DDI_AUX_DATA_B_3 => 16#06_411c# / Register_Width,
1532 DDI_AUX_DATA_B_4 => 16#06_4120# / Register_Width,
1533 DDI_AUX_DATA_B_5 => 16#06_4124# / Register_Width,
1534 DDI_AUX_MUTEX_B => 16#06_412c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1535
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1536 DDI_BUF_CTL_C => 16#06_4200# / Register_Width, -- aliased by GMCH_DP_C
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1537 DDI_BUF_TRANS_C_S0T1 => 16#06_4ec0# / Register_Width,
1538 DDI_BUF_TRANS_C_S0T2 => 16#06_4ec4# / Register_Width,
1539 DDI_BUF_TRANS_C_S1T1 => 16#06_4ec8# / Register_Width,
1540 DDI_BUF_TRANS_C_S1T2 => 16#06_4ecc# / Register_Width,
1541 DDI_BUF_TRANS_C_S2T1 => 16#06_4ed0# / Register_Width,
1542 DDI_BUF_TRANS_C_S2T2 => 16#06_4ed4# / Register_Width,
1543 DDI_BUF_TRANS_C_S3T1 => 16#06_4ed8# / Register_Width,
1544 DDI_BUF_TRANS_C_S3T2 => 16#06_4edc# / Register_Width,
1545 DDI_BUF_TRANS_C_S4T1 => 16#06_4ee0# / Register_Width,
1546 DDI_BUF_TRANS_C_S4T2 => 16#06_4ee4# / Register_Width,
1547 DDI_BUF_TRANS_C_S5T1 => 16#06_4ee8# / Register_Width,
1548 DDI_BUF_TRANS_C_S5T2 => 16#06_4eec# / Register_Width,
1549 DDI_BUF_TRANS_C_S6T1 => 16#06_4ef0# / Register_Width,
1550 DDI_BUF_TRANS_C_S6T2 => 16#06_4ef4# / Register_Width,
1551 DDI_BUF_TRANS_C_S7T1 => 16#06_4ef8# / Register_Width,
1552 DDI_BUF_TRANS_C_S7T2 => 16#06_4efc# / Register_Width,
1553 DDI_BUF_TRANS_C_S8T1 => 16#06_4f00# / Register_Width,
1554 DDI_BUF_TRANS_C_S8T2 => 16#06_4f04# / Register_Width,
1555 DDI_BUF_TRANS_C_S9T1 => 16#06_4f08# / Register_Width,
1556 DDI_BUF_TRANS_C_S9T2 => 16#06_4f0c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1557 DDI_AUX_CTL_C => 16#06_4210# / Register_Width,
1558 DDI_AUX_DATA_C_1 => 16#06_4214# / Register_Width,
1559 DDI_AUX_DATA_C_2 => 16#06_4218# / Register_Width,
1560 DDI_AUX_DATA_C_3 => 16#06_421c# / Register_Width,
1561 DDI_AUX_DATA_C_4 => 16#06_4220# / Register_Width,
1562 DDI_AUX_DATA_C_5 => 16#06_4224# / Register_Width,
1563 DDI_AUX_MUTEX_C => 16#06_422c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1564
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1565 DDI_BUF_CTL_D => 16#06_4300# / Register_Width, -- aliased by GMCH_DP_D
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1566 DDI_BUF_TRANS_D_S0T1 => 16#06_4f20# / Register_Width,
1567 DDI_BUF_TRANS_D_S0T2 => 16#06_4f24# / Register_Width,
1568 DDI_BUF_TRANS_D_S1T1 => 16#06_4f28# / Register_Width,
1569 DDI_BUF_TRANS_D_S1T2 => 16#06_4f2c# / Register_Width,
1570 DDI_BUF_TRANS_D_S2T1 => 16#06_4f30# / Register_Width,
1571 DDI_BUF_TRANS_D_S2T2 => 16#06_4f34# / Register_Width,
1572 DDI_BUF_TRANS_D_S3T1 => 16#06_4f38# / Register_Width,
1573 DDI_BUF_TRANS_D_S3T2 => 16#06_4f3c# / Register_Width,
1574 DDI_BUF_TRANS_D_S4T1 => 16#06_4f40# / Register_Width,
1575 DDI_BUF_TRANS_D_S4T2 => 16#06_4f44# / Register_Width,
1576 DDI_BUF_TRANS_D_S5T1 => 16#06_4f48# / Register_Width,
1577 DDI_BUF_TRANS_D_S5T2 => 16#06_4f4c# / Register_Width,
1578 DDI_BUF_TRANS_D_S6T1 => 16#06_4f50# / Register_Width,
1579 DDI_BUF_TRANS_D_S6T2 => 16#06_4f54# / Register_Width,
1580 DDI_BUF_TRANS_D_S7T1 => 16#06_4f58# / Register_Width,
1581 DDI_BUF_TRANS_D_S7T2 => 16#06_4f5c# / Register_Width,
1582 DDI_BUF_TRANS_D_S8T1 => 16#06_4f60# / Register_Width,
1583 DDI_BUF_TRANS_D_S8T2 => 16#06_4f64# / Register_Width,
1584 DDI_BUF_TRANS_D_S9T1 => 16#06_4f68# / Register_Width,
1585 DDI_BUF_TRANS_D_S9T2 => 16#06_4f6c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1586 DDI_AUX_CTL_D => 16#06_4310# / Register_Width,
1587 DDI_AUX_DATA_D_1 => 16#06_4314# / Register_Width,
1588 DDI_AUX_DATA_D_2 => 16#06_4318# / Register_Width,
1589 DDI_AUX_DATA_D_3 => 16#06_431c# / Register_Width,
1590 DDI_AUX_DATA_D_4 => 16#06_4320# / Register_Width,
1591 DDI_AUX_DATA_D_5 => 16#06_4324# / Register_Width,
1592 DDI_AUX_MUTEX_D => 16#06_432c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1593
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1594 -- USB-C AUX control and data
1595 DDI_AUX_CTL_USBC2 => 16#06_4410# / Register_Width,
1596 DDI_AUX_DATA_USBC2_1 => 16#06_4414# / Register_Width,
1597 DDI_AUX_DATA_USBC2_2 => 16#06_4418# / Register_Width,
1598 DDI_AUX_DATA_USBC2_3 => 16#06_441c# / Register_Width,
1599 DDI_AUX_DATA_USBC2_4 => 16#06_4420# / Register_Width,
1600 DDI_AUX_DATA_USBC2_5 => 16#06_4424# / Register_Width,
1601 DDI_AUX_CTL_USBC3 => 16#06_4510# / Register_Width,
1602 DDI_AUX_DATA_USBC3_1 => 16#06_4514# / Register_Width,
1603 DDI_AUX_DATA_USBC3_2 => 16#06_4518# / Register_Width,
1604 DDI_AUX_DATA_USBC3_3 => 16#06_451c# / Register_Width,
1605 DDI_AUX_DATA_USBC3_4 => 16#06_4520# / Register_Width,
1606 DDI_AUX_DATA_USBC3_5 => 16#06_4524# / Register_Width,
1607 DDI_AUX_CTL_USBC4 => 16#06_4610# / Register_Width,
1608 DDI_AUX_DATA_USBC4_1 => 16#06_4614# / Register_Width,
1609 DDI_AUX_DATA_USBC4_2 => 16#06_4618# / Register_Width,
1610 DDI_AUX_DATA_USBC4_3 => 16#06_461c# / Register_Width,
1611 DDI_AUX_DATA_USBC4_4 => 16#06_4620# / Register_Width,
1612 DDI_AUX_DATA_USBC4_5 => 16#06_4624# / Register_Width,
1613 DDI_AUX_CTL_USBC5 => 16#06_4710# / Register_Width,
1614 DDI_AUX_DATA_USBC5_1 => 16#06_4714# / Register_Width,
1615 DDI_AUX_DATA_USBC5_2 => 16#06_4718# / Register_Width,
1616 DDI_AUX_DATA_USBC5_3 => 16#06_471c# / Register_Width,
1617 DDI_AUX_DATA_USBC5_4 => 16#06_4720# / Register_Width,
1618 DDI_AUX_DATA_USBC5_5 => 16#06_4724# / Register_Width,
1619 DDI_AUX_CTL_USBC6 => 16#06_4810# / Register_Width,
1620 DDI_AUX_DATA_USBC6_1 => 16#06_4814# / Register_Width,
1621 DDI_AUX_DATA_USBC6_2 => 16#06_4818# / Register_Width,
1622 DDI_AUX_DATA_USBC6_3 => 16#06_481c# / Register_Width,
1623 DDI_AUX_DATA_USBC6_4 => 16#06_4820# / Register_Width,
1624 DDI_AUX_DATA_USBC6_5 => 16#06_4824# / Register_Width,
1625
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1626 DDI_BUF_CTL_E => 16#06_4400# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1627 DDI_BUF_TRANS_E_S0T1 => 16#06_4f80# / Register_Width,
1628 DDI_BUF_TRANS_E_S0T2 => 16#06_4f84# / Register_Width,
1629 DDI_BUF_TRANS_E_S1T1 => 16#06_4f88# / Register_Width,
1630 DDI_BUF_TRANS_E_S1T2 => 16#06_4f8c# / Register_Width,
1631 DDI_BUF_TRANS_E_S2T1 => 16#06_4f90# / Register_Width,
1632 DDI_BUF_TRANS_E_S2T2 => 16#06_4f94# / Register_Width,
1633 DDI_BUF_TRANS_E_S3T1 => 16#06_4f98# / Register_Width,
1634 DDI_BUF_TRANS_E_S3T2 => 16#06_4f9c# / Register_Width,
1635 DDI_BUF_TRANS_E_S4T1 => 16#06_4fa0# / Register_Width,
1636 DDI_BUF_TRANS_E_S4T2 => 16#06_4fa4# / Register_Width,
1637 DDI_BUF_TRANS_E_S5T1 => 16#06_4fa8# / Register_Width,
1638 DDI_BUF_TRANS_E_S5T2 => 16#06_4fac# / Register_Width,
1639 DDI_BUF_TRANS_E_S6T1 => 16#06_4fb0# / Register_Width,
1640 DDI_BUF_TRANS_E_S6T2 => 16#06_4fb4# / Register_Width,
1641 DDI_BUF_TRANS_E_S7T1 => 16#06_4fb8# / Register_Width,
1642 DDI_BUF_TRANS_E_S7T2 => 16#06_4fbc# / Register_Width,
1643 DDI_BUF_TRANS_E_S8T1 => 16#06_4fc0# / Register_Width,
1644 DDI_BUF_TRANS_E_S8T2 => 16#06_4fc4# / Register_Width,
1645 DDI_BUF_TRANS_E_S9T1 => 16#06_4fc8# / Register_Width,
1646 DDI_BUF_TRANS_E_S9T2 => 16#06_4fcc# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1647 DP_TP_CTL_A => 16#06_4040# / Register_Width,
1648 DP_TP_CTL_B => 16#06_4140# / Register_Width,
1649 DP_TP_CTL_C => 16#06_4240# / Register_Width,
1650 DP_TP_CTL_D => 16#06_4340# / Register_Width,
1651 DP_TP_CTL_E => 16#06_4440# / Register_Width,
1652 DP_TP_STATUS_B => 16#06_4144# / Register_Width,
1653 DP_TP_STATUS_C => 16#06_4244# / Register_Width,
1654 DP_TP_STATUS_D => 16#06_4344# / Register_Width,
1655 DP_TP_STATUS_E => 16#06_4444# / Register_Width,
1656 PORT_CLK_SEL_DDIA => 16#04_6100# / Register_Width,
1657 PORT_CLK_SEL_DDIB => 16#04_6104# / Register_Width,
1658 PORT_CLK_SEL_DDIC => 16#04_6108# / Register_Width,
1659 PORT_CLK_SEL_DDID => 16#04_610c# / Register_Width,
1660 PORT_CLK_SEL_DDIE => 16#04_6110# / Register_Width,
1661
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]1662 -- Haswell LCPLL registers
1663 LCPLL_CTL => 16#13_0040# / Register_Width,
1664
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]1665 -- Skylake I_boost configuration
1666 DISPIO_CR_TX_BMU_CR0 => 16#06_c00c# / Register_Width,
1667
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1668 -- Skylake DPLL registers
1669 DPLL1_CFGR1 => 16#06_c040# / Register_Width,
1670 DPLL1_CFGR2 => 16#06_c044# / Register_Width,
1671 DPLL2_CFGR1 => 16#06_c048# / Register_Width,
1672 DPLL2_CFGR2 => 16#06_c04c# / Register_Width,
1673 DPLL3_CFGR1 => 16#06_c050# / Register_Width,
1674 DPLL3_CFGR2 => 16#06_c054# / Register_Width,
1675 DPLL_CTRL1 => 16#06_c058# / Register_Width,
1676 DPLL_CTRL2 => 16#06_c05c# / Register_Width,
1677 DPLL_STATUS => 16#06_c060# / Register_Width,
1678
1679 -- CD CLK register
1680 CDCLK_CTL => 16#04_6000# / Register_Width,
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]1681 CDCLK_FREQ => 16#04_6200# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1682
1683 -- Skylake LCPLL registers
1684 LCPLL1_CTL => 16#04_6010# / Register_Width,
1685 LCPLL2_CTL => 16#04_6014# / Register_Width,
1686
1687 -- SPLL register
1688 SPLL_CTL => 16#04_6020# / Register_Width,
1689
1690 -- WRPLL registers
1691 WRPLL_CTL_1 => 16#04_6040# / Register_Width,
1692 WRPLL_CTL_2 => 16#04_6060# / Register_Width,
1693
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]1694 -- Broxton Display Engine PLL registers
1695 BXT_DE_PLL_CTL => 16#06_d000# / Register_Width,
1696 BXT_DE_PLL_ENABLE => 16#04_6070# / Register_Width,
1697
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1698 -- Broxton DDI PHY PLL registers
1699 BXT_PORT_PLL_ENABLE_A => 16#04_6074# / Register_Width,
1700 BXT_PORT_PLL_ENABLE_B => 16#04_6078# / Register_Width,
1701 BXT_PORT_PLL_ENABLE_C => 16#04_607c# / Register_Width,
1702 BXT_PORT_PLL_EBB_0_A => 16#16_2034# / Register_Width,
1703 BXT_PORT_PLL_EBB_4_A => 16#16_2038# / Register_Width,
1704 BXT_PORT_PLL_0_A => 16#16_2100# / Register_Width,
1705 BXT_PORT_PLL_1_A => 16#16_2104# / Register_Width,
1706 BXT_PORT_PLL_2_A => 16#16_2108# / Register_Width,
1707 BXT_PORT_PLL_3_A => 16#16_210c# / Register_Width,
1708 BXT_PORT_PLL_6_A => 16#16_2118# / Register_Width,
1709 BXT_PORT_PLL_8_A => 16#16_2120# / Register_Width,
1710 BXT_PORT_PLL_9_A => 16#16_2124# / Register_Width,
1711 BXT_PORT_PLL_10_A => 16#16_2128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1712 BXT_PORT_PLL_EBB_0_B => 16#06_c034# / Register_Width,
1713 BXT_PORT_PLL_EBB_4_B => 16#06_c038# / Register_Width,
1714 BXT_PORT_PLL_0_B => 16#06_c100# / Register_Width,
1715 BXT_PORT_PLL_1_B => 16#06_c104# / Register_Width,
1716 BXT_PORT_PLL_2_B => 16#06_c108# / Register_Width,
1717 BXT_PORT_PLL_3_B => 16#06_c10c# / Register_Width,
1718 BXT_PORT_PLL_6_B => 16#06_c118# / Register_Width,
1719 BXT_PORT_PLL_8_B => 16#06_c120# / Register_Width,
1720 BXT_PORT_PLL_9_B => 16#06_c124# / Register_Width,
1721 BXT_PORT_PLL_10_B => 16#06_c128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1722 BXT_PORT_PLL_EBB_0_C => 16#06_c340# / Register_Width,
1723 BXT_PORT_PLL_EBB_4_C => 16#06_c344# / Register_Width,
1724 BXT_PORT_PLL_0_C => 16#06_c380# / Register_Width,
1725 BXT_PORT_PLL_1_C => 16#06_c384# / Register_Width,
1726 BXT_PORT_PLL_2_C => 16#06_c388# / Register_Width,
1727 BXT_PORT_PLL_3_C => 16#06_c38c# / Register_Width,
1728 BXT_PORT_PLL_6_C => 16#06_c398# / Register_Width,
1729 BXT_PORT_PLL_8_C => 16#06_c3a0# / Register_Width,
1730 BXT_PORT_PLL_9_C => 16#06_c3a4# / Register_Width,
1731 BXT_PORT_PLL_10_C => 16#06_c3a8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1732
1733 -- Broxton DDI PHY PCS? registers
1734 BXT_PORT_PCS_DW10_01_A => 16#16_2428# / Register_Width,
1735 BXT_PORT_PCS_DW12_01_A => 16#16_2430# / Register_Width,
1736 BXT_PORT_PCS_DW10_GRP_A => 16#16_2c28# / Register_Width,
1737 BXT_PORT_PCS_DW12_GRP_A => 16#16_2c30# / Register_Width,
1738 BXT_PORT_PCS_DW10_01_B => 16#06_c428# / Register_Width,
1739 BXT_PORT_PCS_DW12_01_B => 16#06_c430# / Register_Width,
1740 BXT_PORT_PCS_DW10_01_C => 16#06_c828# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1741 BXT_PORT_PCS_DW12_01_C => 16#06_c830# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1742 BXT_PORT_PCS_DW10_GRP_B => 16#06_cc28# / Register_Width,
1743 BXT_PORT_PCS_DW12_GRP_B => 16#06_cc30# / Register_Width,
1744 BXT_PORT_PCS_DW10_GRP_C => 16#06_ce28# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1745 BXT_PORT_PCS_DW12_GRP_C => 16#06_ce30# / Register_Width,
1746
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1747 -- Broxton DDI PHY registers
1748 BXT_P_CR_GT_DISP_PWRON => 16#13_8090# / Register_Width,
1749 BXT_PHY_CTL_A => 16#06_4c00# / Register_Width,
1750 BXT_PHY_CTL_B => 16#06_4c10# / Register_Width,
1751 BXT_PHY_CTL_C => 16#06_4c20# / Register_Width,
1752 BXT_PHY_CTL_FAM_EDP => 16#06_4c80# / Register_Width,
1753 BXT_PHY_CTL_FAM_DDI => 16#06_4c90# / Register_Width,
1754
1755 -- Broxton DDI PHY common lane registers
1756 BXT_PORT_CL1CM_DW0_A => 16#16_2000# / Register_Width,
1757 BXT_PORT_CL1CM_DW0_BC => 16#06_c000# / Register_Width,
1758 BXT_PORT_CL1CM_DW9_A => 16#16_2024# / Register_Width,
1759 BXT_PORT_CL1CM_DW9_BC => 16#06_c024# / Register_Width,
1760 BXT_PORT_CL1CM_DW10_A => 16#16_2028# / Register_Width,
1761 BXT_PORT_CL1CM_DW10_BC => 16#06_c028# / Register_Width,
1762 BXT_PORT_CL1CM_DW28_A => 16#16_2070# / Register_Width,
1763 BXT_PORT_CL1CM_DW28_BC => 16#06_c070# / Register_Width,
1764 BXT_PORT_CL1CM_DW30_A => 16#16_2078# / Register_Width,
1765 BXT_PORT_CL1CM_DW30_BC => 16#06_c078# / Register_Width,
1766 BXT_PORT_CL2CM_DW6_BC => 16#06_c358# / Register_Width,
1767
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1768 -- Broxton DDI PHY TX lane registers
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1769 BXT_PORT_TX_DW2_LN0_A => 16#16_2508# / Register_Width,
1770 BXT_PORT_TX_DW3_LN0_A => 16#16_250c# / Register_Width,
1771 BXT_PORT_TX_DW4_LN0_A => 16#16_2510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1772 BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width,
1773 BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width,
1774 BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width,
1775 BXT_PORT_TX_DW14_LN3_A => 16#16_27b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1776 BXT_PORT_TX_DW2_GRP_A => 16#16_2d08# / Register_Width,
1777 BXT_PORT_TX_DW3_GRP_A => 16#16_2d0c# / Register_Width,
1778 BXT_PORT_TX_DW4_GRP_A => 16#16_2d10# / Register_Width,
1779 BXT_PORT_TX_DW2_LN0_B => 16#06_c508# / Register_Width,
1780 BXT_PORT_TX_DW3_LN0_B => 16#06_c50c# / Register_Width,
1781 BXT_PORT_TX_DW4_LN0_B => 16#06_c510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1782 BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width,
1783 BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width,
1784 BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width,
1785 BXT_PORT_TX_DW14_LN3_B => 16#06_c7b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1786 BXT_PORT_TX_DW2_GRP_B => 16#06_cd08# / Register_Width,
1787 BXT_PORT_TX_DW3_GRP_B => 16#06_cd0c# / Register_Width,
1788 BXT_PORT_TX_DW4_GRP_B => 16#06_cd10# / Register_Width,
1789 BXT_PORT_TX_DW2_LN0_C => 16#06_c908# / Register_Width,
1790 BXT_PORT_TX_DW3_LN0_C => 16#06_c90c# / Register_Width,
1791 BXT_PORT_TX_DW4_LN0_C => 16#06_c910# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1792 BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width,
1793 BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width,
1794 BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width,
1795 BXT_PORT_TX_DW14_LN3_C => 16#06_cbb8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1796 BXT_PORT_TX_DW2_GRP_C => 16#06_cf08# / Register_Width,
1797 BXT_PORT_TX_DW3_GRP_C => 16#06_cf0c# / Register_Width,
1798 BXT_PORT_TX_DW4_GRP_C => 16#06_cf10# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1799
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1800 -- Broxton DDI PHY ref registers
1801 BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width,
1802 BXT_PORT_REF_DW3_BC => 16#06_c18c# / Register_Width,
1803 BXT_PORT_REF_DW6_A => 16#16_2198# / Register_Width,
1804 BXT_PORT_REF_DW6_BC => 16#06_c198# / Register_Width,
1805 BXT_PORT_REF_DW8_A => 16#16_21a0# / Register_Width,
1806 BXT_PORT_REF_DW8_BC => 16#06_c1a0# / Register_Width,
1807
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1808 -- Power Down Well registers
1809 PWR_WELL_CTL_BIOS => 16#04_5400# / Register_Width,
1810 PWR_WELL_CTL_DRIVER => 16#04_5404# / Register_Width,
1811 PWR_WELL_CTL_KVMR => 16#04_5408# / Register_Width,
1812 PWR_WELL_CTL_DEBUG => 16#04_540c# / Register_Width,
1813 PWR_WELL_CTL5 => 16#04_5410# / Register_Width,
1814 PWR_WELL_CTL6 => 16#04_5414# / Register_Width,
1815
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1816 PWR_AUX_CTL_BIOS => 16#04_5440# / Register_Width,
1817 PWR_AUX_CTL_DRIVER => 16#04_5444# / Register_Width,
1818 PWR_DDI_CTL_BIOS => 16#04_5450# / Register_Width,
1819 PWR_DDI_CTL_DRIVER => 16#04_5454# / Register_Width,
1820
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1821 -- class Panel registers
Arthur Heymanse87d0d12018-03-28 17:02:49 +0200[diff] [blame]1822 GMCH_PP_STATUS => 16#06_1200# / Register_Width,
1823 GMCH_PP_CONTROL => 16#06_1204# / Register_Width,
1824 GMCH_PP_ON_DELAYS => 16#06_1208# / Register_Width,
1825 GMCH_PP_OFF_DELAYS => 16#06_120c# / Register_Width,
1826 GMCH_PP_DIVISOR => 16#06_1210# / Register_Width,
Arthur Heymansd5198442018-03-28 17:05:12 +0200[diff] [blame]1827 GMCH_PFIT_CONTROL => 16#06_1230# / Register_Width,
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]1828 PCH_PP_STATUS => 16#0c_7200# / Register_Width, -- aliased with BXT_PP_STATUS_1
1829 PCH_PP_CONTROL => 16#0c_7204# / Register_Width, -- aliased with BXT_PP_CONTROL_1
1830 PCH_PP_ON_DELAYS => 16#0c_7208# / Register_Width, -- aliased with BXT_PP_ON_DELAYS_1
1831 PCH_PP_OFF_DELAYS => 16#0c_720c# / Register_Width, -- aliased with BXT_PP_OFF_DELAYS_1
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1832 PCH_PP_DIVISOR => 16#0c_7210# / Register_Width,
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]1833 BXT_PP_STATUS_2 => 16#0c_7300# / Register_Width,
1834 BXT_PP_CONTROL_2 => 16#0c_7304# / Register_Width,
1835 BXT_PP_ON_DELAYS_2 => 16#0c_7308# / Register_Width,
1836 BXT_PP_OFF_DELAYS_2 => 16#0c_730c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1837 BLC_PWM_CPU_CTL => 16#04_8254# / Register_Width,
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]1838 BLC_PWM_CPU_CTL2 => 16#04_8250# / Register_Width,
1839 BLC_PWM_PCH_CTL1 => 16#0c_8250# / Register_Width, -- aliased with BXT_BLC_PWM_CTL_1
1840 BLC_PWM_PCH_CTL2 => 16#0c_8254# / Register_Width, -- aliased with BXT_BLC_PWM_FREQ_1
1841 BXT_BLC_PWM_DUTY_1 => 16#0c_8258# / Register_Width,
1842 BXT_BLC_PWM_CTL_2 => 16#0c_8350# / Register_Width,
1843 BXT_BLC_PWM_FREQ_2 => 16#0c_8354# / Register_Width,
1844 BXT_BLC_PWM_DUTY_2 => 16#0c_8358# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1845
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1846 -- GMCH LVDS Connector Registers
1847 GMCH_LVDS => 16#06_1180# / Register_Width,
1848
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1849 -- PCH LVDS Connector Registers
1850 PCH_LVDS => 16#0e_1180# / Register_Width,
1851
1852 -- PCH ADPA Connector Registers
1853 PCH_ADPA => 16#0e_1100# / Register_Width,
1854
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1855 -- GMCH DVOB Connector Registers
1856 GMCH_SDVOB => 16#06_1140# / Register_Width,
1857
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1858 -- PCH HDMIB Connector Registers
1859 PCH_HDMIB => 16#0e_1140# / Register_Width,
1860
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1861 -- GMCH DVOC Connector Registers
1862 GMCH_SDVOC => 16#06_1160# / Register_Width,
1863
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1864 -- PCH HDMIC Connector Registers
1865 PCH_HDMIC => 16#0e_1150# / Register_Width,
1866
1867 -- PCH HDMID Connector Registers
1868 PCH_HDMID => 16#0e_1160# / Register_Width,
1869
1870 -- Intel Registers
Nico Huber6b4678d2019-09-22 21:31:52 +0200[diff] [blame]1871 DFSM => 16#05_1000# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1872 DSSM => 16#05_1004# / Register_Width,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]1873 CPU_VGACNTRL => 16#04_1000# / Register_Width,
1874 GMCH_VGACNTRL => 16#07_1400# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1875 FUSE_STATUS => 16#04_2000# / Register_Width,
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]1876 FUSE_STRAP => 16#04_2014# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1877 FBA_CFB_BASE => 16#04_3200# / Register_Width,
1878 IPS_CTL => 16#04_3408# / Register_Width,
1879 ARB_CTL => 16#04_5000# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1880 DBUF_CTL_S0 => 16#04_5008# / Register_Width,
1881 DBUF_CTL_S1 => 16#04_4fe8# / Register_Width,
1882 DBUF_CTL_S2 => 16#04_4300# / Register_Width,
1883 DBUF_CTL_S3 => 16#04_4304# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1884 NDE_RSTWRN_OPT => 16#04_6408# / Register_Width,
Angel Ponsae186bd2020-10-21 21:37:34 +0200[diff] [blame]1885 GEN8_CHICKEN_DCPR_1 => 16#04_6430# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1886 GEN11_CHICKEN_DCPR_2 => 16#04_6434# / Register_Width,
1887 GEN9_CLKGATE_DIS_0 => 16#04_6530# / Register_Width,
1888 GEN9_CLKGATE_DIS_5 => 16#04_6540# / Register_Width,
1889 GEN9_CHICKEN_DPCR_3 => 16#04_6538# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1890 PCH_DREF_CONTROL => 16#0c_6200# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1891 PCH_DPLL_SEL => 16#0c_7000# / Register_Width,
1892 GT_MAILBOX => 16#13_8124# / Register_Width,
1893 GT_MAILBOX_DATA => 16#13_8128# / Register_Width,
1894 GT_MAILBOX_DATA_1 => 16#13_812c# / Register_Width,
1895
1896 PCH_DP_B => 16#0e_4100# / Register_Width,
1897 PCH_DP_AUX_CTL_B => 16#0e_4110# / Register_Width,
1898 PCH_DP_AUX_DATA_B_1 => 16#0e_4114# / Register_Width,
1899 PCH_DP_AUX_DATA_B_2 => 16#0e_4118# / Register_Width,
1900 PCH_DP_AUX_DATA_B_3 => 16#0e_411c# / Register_Width,
1901 PCH_DP_AUX_DATA_B_4 => 16#0e_4120# / Register_Width,
1902 PCH_DP_AUX_DATA_B_5 => 16#0e_4124# / Register_Width,
1903 PCH_DP_C => 16#0e_4200# / Register_Width,
1904 PCH_DP_AUX_CTL_C => 16#0e_4210# / Register_Width,
1905 PCH_DP_AUX_DATA_C_1 => 16#0e_4214# / Register_Width,
1906 PCH_DP_AUX_DATA_C_2 => 16#0e_4218# / Register_Width,
1907 PCH_DP_AUX_DATA_C_3 => 16#0e_421c# / Register_Width,
1908 PCH_DP_AUX_DATA_C_4 => 16#0e_4220# / Register_Width,
1909 PCH_DP_AUX_DATA_C_5 => 16#0e_4224# / Register_Width,
1910 PCH_DP_D => 16#0e_4300# / Register_Width,
1911 PCH_DP_AUX_CTL_D => 16#0e_4310# / Register_Width,
1912 PCH_DP_AUX_DATA_D_1 => 16#0e_4314# / Register_Width,
1913 PCH_DP_AUX_DATA_D_2 => 16#0e_4318# / Register_Width,
1914 PCH_DP_AUX_DATA_D_3 => 16#0e_431c# / Register_Width,
1915 PCH_DP_AUX_DATA_D_4 => 16#0e_4320# / Register_Width,
1916 PCH_DP_AUX_DATA_D_5 => 16#0e_4324# / Register_Width,
1917
1918 -- watermark registers
1919 WM1_LP_ILK => 16#04_5108# / Register_Width,
1920 WM2_LP_ILK => 16#04_510c# / Register_Width,
1921 WM3_LP_ILK => 16#04_5110# / Register_Width,
1922
1923 -- audio VID/DID
1924 AUD_VID_DID => 16#06_5020# / Register_Width,
1925 PCH_AUD_VID_DID => 16#0e_5020# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1926 G4X_AUD_VID_DID => 16#06_2020# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1927
1928 -- interrupt registers
1929 DEISR => 16#04_4000# / Register_Width,
1930 DEIMR => 16#04_4004# / Register_Width,
1931 DEIIR => 16#04_4008# / Register_Width,
1932 DEIER => 16#04_400c# / Register_Width,
1933 GTISR => 16#04_4010# / Register_Width,
1934 GTIMR => 16#04_4014# / Register_Width,
1935 GTIIR => 16#04_4018# / Register_Width,
1936 GTIER => 16#04_401c# / Register_Width,
1937 SDEISR => 16#0c_4000# / Register_Width,
1938 SDEIMR => 16#0c_4004# / Register_Width,
1939 SDEIIR => 16#0c_4008# / Register_Width,
1940 SDEIER => 16#0c_400c# / Register_Width,
1941
1942 -- I2C stuff
Arthur Heymans229ed1c2018-03-28 16:45:43 +0200[diff] [blame]1943 GMCH_GMBUS0 => 16#00_5100# / Register_Width,
1944 GMCH_GMBUS1 => 16#00_5104# / Register_Width,
1945 GMCH_GMBUS2 => 16#00_5108# / Register_Width,
1946 GMCH_GMBUS3 => 16#00_510c# / Register_Width,
1947 GMCH_GMBUS4 => 16#00_5110# / Register_Width,
1948 GMCH_GMBUS5 => 16#00_5120# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1949 PCH_GMBUS0 => 16#0c_5100# / Register_Width,
1950 PCH_GMBUS1 => 16#0c_5104# / Register_Width,
1951 PCH_GMBUS2 => 16#0c_5108# / Register_Width,
1952 PCH_GMBUS3 => 16#0c_510c# / Register_Width,
1953 PCH_GMBUS4 => 16#0c_5110# / Register_Width,
1954 PCH_GMBUS5 => 16#0c_5120# / Register_Width,
1955
1956 -- clock gating -- maybe have to touch this
1957 DSPCLK_GATE_D => 16#04_2020# / Register_Width,
1958 PCH_FDI_CHICKEN_B_C => 16#0c_2000# / Register_Width,
1959 PCH_DSPCLK_GATE_D => 16#0c_2020# / Register_Width,
1960
1961 -- hotplug and initial detection
1962 HOTPLUG_CTL => 16#04_4030# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1963 TC_HOTPLUG_CTL => 16#04_4038# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1964 PORT_HOTPLUG_EN => 16#06_1110# / Register_Width,
1965 PORT_HOTPLUG_STAT => 16#06_1114# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1966 SHOTPLUG_CTL => 16#0c_4030# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1967 SHOTPLUG_CTL_TC => 16#0c_4034# / Register_Width,
1968 SHPD_FILTER_CNT => 16#0c_4038# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1969 SFUSE_STRAP => 16#0c_2014# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1970 GEN11_DE_HPD_ISR => 16#04_4470# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1971
1972 -- Render Engine Command Streamer
1973 ARB_MODE => 16#00_4030# / Register_Width,
1974 HWS_PGA => 16#00_4080# / Register_Width,
1975 RCS_RING_BUFFER_TAIL => 16#00_2030# / Register_Width,
1976 VCS_RING_BUFFER_TAIL => 16#01_2030# / Register_Width,
1977 BCS_RING_BUFFER_TAIL => 16#02_2030# / Register_Width,
1978 RCS_RING_BUFFER_HEAD => 16#00_2034# / Register_Width,
1979 VCS_RING_BUFFER_HEAD => 16#01_2034# / Register_Width,
1980 BCS_RING_BUFFER_HEAD => 16#02_2034# / Register_Width,
1981 RCS_RING_BUFFER_STRT => 16#00_2038# / Register_Width,
1982 VCS_RING_BUFFER_STRT => 16#01_2038# / Register_Width,
1983 BCS_RING_BUFFER_STRT => 16#02_2038# / Register_Width,
1984 RCS_RING_BUFFER_CTL => 16#00_203c# / Register_Width,
1985 VCS_RING_BUFFER_CTL => 16#01_203c# / Register_Width,
1986 BCS_RING_BUFFER_CTL => 16#02_203c# / Register_Width,
1987 MI_MODE => 16#00_209c# / Register_Width,
1988 INSTPM => 16#00_20c0# / Register_Width,
1989 GAB_CTL_REG => 16#02_4000# / Register_Width,
1990 PP_DCLV_HIGH => 16#00_2220# / Register_Width,
1991 PP_DCLV_LOW => 16#00_2228# / Register_Width,
1992 VCS_PP_DCLV_HIGH => 16#01_2220# / Register_Width,
1993 VCS_PP_DCLV_LOW => 16#01_2228# / Register_Width,
1994 BCS_PP_DCLV_HIGH => 16#02_2220# / Register_Width,
1995 BCS_PP_DCLV_LOW => 16#02_2228# / Register_Width,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1996 ILK_DISPLAY_CHICKEN2 => 16#04_2004# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1997 UCGCTL1 => 16#00_9400# / Register_Width,
1998 UCGCTL2 => 16#00_9404# / Register_Width,
1999 MBCTL => 16#00_907c# / Register_Width,
2000 HWSTAM => 16#00_2098# / Register_Width,
2001 VCS_HWSTAM => 16#01_2098# / Register_Width,
2002 BCS_HWSTAM => 16#02_2098# / Register_Width,
2003 IIR => 16#04_4028# / Register_Width,
2004 PIPE_FRMCNT_A => 16#07_0040# / Register_Width,
2005 PIPE_FRMCNT_B => 16#07_1040# / Register_Width,
2006 PIPE_FRMCNT_C => 16#07_2040# / Register_Width,
2007 FBC_CTL => 16#04_3208# / Register_Width,
2008 PIPE_VSYNCSHIFT_A => 16#06_0028# / Register_Width,
2009 PIPE_VSYNCSHIFT_B => 16#06_1028# / Register_Width,
2010 PIPE_VSYNCSHIFT_C => 16#06_2028# / Register_Width,
2011 WM_PIPE_A => 16#04_5100# / Register_Width,
2012 WM_PIPE_B => 16#04_5104# / Register_Width,
2013 WM_PIPE_C => 16#04_5200# / Register_Width,
2014 PIPE_SCANLINE_A => 16#07_0000# / Register_Width,
2015 PIPE_SCANLINE_B => 16#07_1000# / Register_Width,
2016 PIPE_SCANLINE_C => 16#07_2000# / Register_Width,
2017 GFX_MODE => 16#00_2520# / Register_Width,
2018 CACHE_MODE_0 => 16#00_2120# / Register_Width,
2019 SLEEP_PSMI_CONTROL => 16#01_2050# / Register_Width,
2020 CTX_SIZE => 16#00_21a0# / Register_Width,
2021 GAC_ECO_BITS => 16#01_4090# / Register_Width,
2022 GAM_ECOCHK => 16#00_4090# / Register_Width,
2023 QUIRK_02084 => 16#00_2084# / Register_Width,
2024 QUIRK_02090 => 16#00_2090# / Register_Width,
2025 GT_MODE => 16#00_20d0# / Register_Width,
2026 QUIRK_F0060 => 16#0f_0060# / Register_Width,
2027 QUIRK_F1060 => 16#0f_1060# / Register_Width,
2028 QUIRK_F2060 => 16#0f_2060# / Register_Width,
2029 AUD_CNTRL_ST2 => 16#0e_50c0# / Register_Width,
2030 AUD_CNTL_ST_A => 16#0e_50b4# / Register_Width,
2031 AUD_CNTL_ST_B => 16#0e_51b4# / Register_Width,
2032 AUD_CNTL_ST_C => 16#0e_52b4# / Register_Width,
2033 AUD_HDMIW_HDMIEDID_A => 16#0e_5050# / Register_Width,
2034 AUD_HDMIW_HDMIEDID_B => 16#0e_5150# / Register_Width,
2035 AUD_HDMIW_HDMIEDID_C => 16#0e_5250# / Register_Width,
2036 AUD_CONFIG_A => 16#0e_5000# / Register_Width,
2037 AUD_CONFIG_B => 16#0e_5100# / Register_Width,
2038 AUD_CONFIG_C => 16#0e_5200# / Register_Width,
2039 TRANS_DP_CTL_A => 16#0e_0300# / Register_Width,
2040 TRANS_DP_CTL_B => 16#0e_1300# / Register_Width,
2041 TRANS_DP_CTL_C => 16#0e_2300# / Register_Width,
2042 TRANS_VSYNCSHIFT_A => 16#0e_0028# / Register_Width,
2043 TRANS_VSYNCSHIFT_B => 16#0e_1028# / Register_Width,
2044 TRANS_VSYNCSHIFT_C => 16#0e_2028# / Register_Width,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]2045 PCH_RAWCLK_FREQ => 16#0c_6204# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]2046 QUIRK_C2004 => 16#0c_2004# / Register_Width,
2047
2048 -- MCHBAR Mirror
2049
Nico Huberb47a5c42019-09-29 00:07:21 +0200[diff] [blame]2050 GMCH_CLKCFG => 16#01_0c00# / Register_Width,
2051 GMCH_HPLLVCO_MOBILE => 16#01_0c0f# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]2052 GMCH_HPLLVCO => 16#01_0c38# / Register_Width,
2053
2054 -- Combo Phy Registers (Tigerlake on)
2055
2056 PHY_MISC_B => 16#06_4c04# / Register_Width,
2057 PHY_MISC_C => 16#06_4c08# / Register_Width,
2058 PORT_CL_DW5_A => 16#16_2014# / Register_Width,
2059 PORT_CL_DW5_B => 16#06_c014# / Register_Width,
2060 PORT_CL_DW5_C => 16#16_0014# / Register_Width,
2061 PORT_COMP_DW0_C => 16#16_0100# / Register_Width,
2062 PORT_COMP_DW1_C => 16#16_0104# / Register_Width,
2063 PORT_COMP_DW3_C => 16#16_010c# / Register_Width,
2064 PORT_COMP_DW8_C => 16#16_0120# / Register_Width,
2065 PORT_COMP_DW9_C => 16#16_0124# / Register_Width,
2066 PORT_COMP_DW10_C => 16#16_0128# / Register_Width,
2067 PORT_TX_DW8_LN0_A => 16#16_28a0# / Register_Width,
2068 PORT_TX_DW8_LN0_B => 16#06_c8a0# / Register_Width,
2069 PORT_TX_DW8_LN0_C => 16#16_08a0# / Register_Width,
2070 PORT_TX_DW8_GRP_A => 16#16_26a0# / Register_Width,
2071 PORT_TX_DW8_GRP_B => 16#06_c6a0# / Register_Width,
2072 PORT_TX_DW8_GRP_C => 16#16_06a0# / Register_Width,
2073 PORT_PCS_DW1_LN0_A => 16#16_2804# / Register_Width,
2074 PORT_PCS_DW1_LN0_B => 16#06_c804# / Register_Width,
2075 PORT_PCS_DW1_LN0_C => 16#16_0804# / Register_Width,
2076 PORT_PCS_DW1_GRP_A => 16#16_2604# / Register_Width,
2077 PORT_PCS_DW1_GRP_B => 16#06_c604# / Register_Width,
2078 PORT_PCS_DW1_GRP_C => 16#16_0604# / Register_Width,
2079 MBUS_ABOX_CTL => 16#04_5038# / Register_Width,
2080 MBUS_ABOX1_CTL => 16#04_5048# / Register_Width,
2081 MBUS_ABOX2_CTL => 16#04_504c# / Register_Width,
2082 BW_BUDDY1_PAGE_MASK => 16#04_5144# / Register_Width,
2083 BW_BUDDY2_PAGE_MASK => 16#04_5154# / Register_Width,
2084 BW_BUDDY1_CTL => 16#04_5140# / Register_Width,
2085 BW_BUDDY2_CTL => 16#04_5150# / Register_Width,
2086
2087 -- TGL DKL PHY registers
2088 HIP_INDEX_REG0 => 16#10_10a0# / Register_Width,
2089 HIP_INDEX_REG1 => 16#10_10a4# / Register_Width,
2090 -- Each type-C port PHY is addressed through a 4KB
2091 -- aperture. Each PHY has more than 4KB of register space, so a
2092 -- separate index is programmed in HIP_INDEX_REG0 or
2093 -- HIP_INDEX_REG1, based on the port number, to set the upper 2
2094 -- address bits that point the 4KB window into the full PHY
2095 -- register space.
2096 -- The registers below assumes index 2 has been programmed.
2097
2098 -- 16_8*** registers for DKL PHY 1
2099 DKL_CLKTOP2_HSCC_1 => 16#16_80d4# / Register_Width,
2100 DKL_CLKTOP2_CCC1_1 => 16#16_80d8# / Register_Width,
2101 DKL_REFCLKIN_CTL_1 => 16#16_812c# / Register_Width,
2102 DKL_PLL_DIV0_1 => 16#16_8200# / Register_Width,
2103 DKL_PLL_DIV1_1 => 16#16_8204# / Register_Width,
2104 DKL_PLL_SSC_1 => 16#16_8210# / Register_Width,
2105 DKL_PLL_BIAS_1 => 16#16_8214# / Register_Width,
2106 DKL_PLL_COLDST_BIAS_1 => 16#16_8218# / Register_Width,
2107 DKL_CMN_UC_DW_27_1 => 16#16_836c# / Register_Width,
2108 DKL_DP_MODE_1 => 16#16_80a0# / Register_Width,
2109 -- 16_9*** registers for DKL PHY 2
2110 DKL_CLKTOP2_HSCC_2 => 16#16_90d4# / Register_Width,
2111 DKL_CLKTOP2_CCC1_2 => 16#16_90d8# / Register_Width,
2112 DKL_REFCLKIN_CTL_2 => 16#16_912c# / Register_Width,
2113 DKL_PLL_DIV0_2 => 16#16_9200# / Register_Width,
2114 DKL_PLL_DIV1_2 => 16#16_9204# / Register_Width,
2115 DKL_PLL_SSC_2 => 16#16_9210# / Register_Width,
2116 DKL_PLL_BIAS_2 => 16#16_9214# / Register_Width,
2117 DKL_PLL_COLDST_BIAS_2 => 16#16_9218# / Register_Width,
2118 DKL_CMN_UC_DW_27_2 => 16#16_936c# / Register_Width,
2119 DKL_DP_MODE_2 => 16#16_90a0# / Register_Width,
2120 -- 16_a*** registers for DKL PHY 3
2121 DKL_CLKTOP2_HSCC_3 => 16#16_a0d4# / Register_Width,
2122 DKL_CLKTOP2_CCC1_3 => 16#16_a0d8# / Register_Width,
2123 DKL_REFCLKIN_CTL_3 => 16#16_a12c# / Register_Width,
2124 DKL_PLL_DIV0_3 => 16#16_a200# / Register_Width,
2125 DKL_PLL_DIV1_3 => 16#16_a204# / Register_Width,
2126 DKL_PLL_SSC_3 => 16#16_a210# / Register_Width,
2127 DKL_PLL_BIAS_3 => 16#16_a214# / Register_Width,
2128 DKL_PLL_COLDST_BIAS_3 => 16#16_a218# / Register_Width,
2129 DKL_CMN_UC_DW_27_3 => 16#16_a36c# / Register_Width,
2130 DKL_DP_MODE_3 => 16#16_a0a0# / Register_Width,
2131 -- 16_b*** registers for DKL PHY 4
2132 DKL_CLKTOP2_HSCC_4 => 16#16_b0d4# / Register_Width,
2133 DKL_CLKTOP2_CCC1_4 => 16#16_b0d8# / Register_Width,
2134 DKL_REFCLKIN_CTL_4 => 16#16_b12c# / Register_Width,
2135 DKL_PLL_DIV0_4 => 16#16_b200# / Register_Width,
2136 DKL_PLL_DIV1_4 => 16#16_b204# / Register_Width,
2137 DKL_PLL_SSC_4 => 16#16_b210# / Register_Width,
2138 DKL_PLL_BIAS_4 => 16#16_b214# / Register_Width,
2139 DKL_PLL_COLDST_BIAS_4 => 16#16_b218# / Register_Width,
2140 DKL_CMN_UC_DW_27_4 => 16#16_b36c# / Register_Width,
2141 DKL_DP_MODE_4 => 16#16_b0a0# / Register_Width,
2142 -- 16_c*** registers for DKL PHY 5
2143 DKL_CLKTOP2_HSCC_5 => 16#16_c0d4# / Register_Width,
2144 DKL_CLKTOP2_CCC1_5 => 16#16_c0d8# / Register_Width,
2145 DKL_REFCLKIN_CTL_5 => 16#16_c12c# / Register_Width,
2146 DKL_PLL_DIV0_5 => 16#16_c200# / Register_Width,
2147 DKL_PLL_DIV1_5 => 16#16_c204# / Register_Width,
2148 DKL_PLL_SSC_5 => 16#16_c210# / Register_Width,
2149 DKL_PLL_BIAS_5 => 16#16_c214# / Register_Width,
2150 DKL_PLL_COLDST_BIAS_5 => 16#16_c218# / Register_Width,
2151 DKL_CMN_UC_DW_27_5 => 16#16_c36c# / Register_Width,
2152 DKL_DP_MODE_5 => 16#16_c0a0# / Register_Width,
2153 -- 16_d*** registers for DKL PHY 6
2154 DKL_CLKTOP2_HSCC_6 => 16#16_d0d4# / Register_Width,
2155 DKL_CLKTOP2_CCC1_6 => 16#16_d0d8# / Register_Width,
2156 DKL_REFCLKIN_CTL_6 => 16#16_d12c# / Register_Width,
2157 DKL_PLL_DIV0_6 => 16#16_d200# / Register_Width,
2158 DKL_PLL_DIV1_6 => 16#16_d204# / Register_Width,
2159 DKL_PLL_SSC_6 => 16#16_d210# / Register_Width,
2160 DKL_PLL_BIAS_6 => 16#16_d214# / Register_Width,
2161 DKL_PLL_COLDST_BIAS_6 => 16#16_d218# / Register_Width,
2162 DKL_CMN_UC_DW_27_6 => 16#16_d36c# / Register_Width,
2163 DKL_DP_MODE_6 => 16#16_d0a0# / Register_Width,
2164
2165 -- TGL DPLL registers
2166 DPLL_4_ENABLE => 16#04_6018# / Register_Width,
2167 DPLL_0_CFGCR0 => 16#16_4284# / Register_Width,
2168 DPLL_0_CFGCR1 => 16#16_4288# / Register_Width,
2169 DPLL_1_CFGCR0 => 16#16_428c# / Register_Width,
2170 DPLL_1_CFGCR1 => 16#16_4290# / Register_Width,
2171 DPLL_4_CFGCR0 => 16#16_4294# / Register_Width,
2172 DPLL_4_CFGCR1 => 16#16_4298# / Register_Width,
2173 DPLL_0_SSC => 16#16_4b10# / Register_Width,
2174 DPLL_1_SSC => 16#16_4c10# / Register_Width,
2175 DPLL_4_SSC => 16#16_4e10# / Register_Width,
2176
2177 -- TGL DDI registers (some aliases too)
2178 DDI_BUF_CTL_USBC3 => 16#06_4500# / Register_Width,
2179 DDI_BUF_CTL_USBC4 => 16#06_4600# / Register_Width,
2180 DDI_BUF_CTL_USBC5 => 16#06_4700# / Register_Width,
2181 PORT_TX_DW2_LN0_A => 16#16_2888# / Register_Width,
2182 PORT_TX_DW2_LN0_B => 16#06_c888# / Register_Width,
2183 PORT_TX_DW2_LN0_C => 16#16_0888# / Register_Width,
2184 PORT_TX_DW2_GRP_A => 16#16_2688# / Register_Width,
2185 PORT_TX_DW2_GRP_B => 16#06_c688# / Register_Width,
2186 PORT_TX_DW2_GRP_C => 16#16_0688# / Register_Width,
2187 PORT_TX_DW4_LN0_A => 16#16_2890# / Register_Width,
2188 PORT_TX_DW4_LN1_A => 16#16_2990# / Register_Width,
2189 PORT_TX_DW4_LN2_A => 16#16_2a90# / Register_Width,
2190 PORT_TX_DW4_LN3_A => 16#16_2b90# / Register_Width,
2191 PORT_TX_DW4_LN0_B => 16#06_c890# / Register_Width,
2192 PORT_TX_DW4_LN1_B => 16#06_c990# / Register_Width,
2193 PORT_TX_DW4_LN2_B => 16#06_ca90# / Register_Width,
2194 PORT_TX_DW4_LN3_B => 16#06_cb90# / Register_Width,
2195 PORT_TX_DW4_LN0_C => 16#16_0890# / Register_Width,
2196 PORT_TX_DW4_LN1_C => 16#16_0990# / Register_Width,
2197 PORT_TX_DW4_LN2_C => 16#16_0a90# / Register_Width,
2198 PORT_TX_DW4_LN3_C => 16#16_0b90# / Register_Width,
2199 PORT_TX_DW4_GRP_A => 16#16_2690# / Register_Width,
2200 PORT_TX_DW4_GRP_B => 16#06_c690# / Register_Width,
2201 PORT_TX_DW4_GRP_C => 16#16_0690# / Register_Width,
2202 PORT_TX_DW5_LN0_A => 16#16_2894# / Register_Width,
2203 PORT_TX_DW5_LN0_B => 16#06_c894# / Register_Width,
2204 PORT_TX_DW5_LN0_C => 16#16_0894# / Register_Width,
2205 PORT_TX_DW5_GRP_A => 16#16_2694# / Register_Width,
2206 PORT_TX_DW5_GRP_B => 16#06_c694# / Register_Width,
2207 PORT_TX_DW5_GRP_C => 16#16_0694# / Register_Width,
2208 PORT_TX_DW7_LN0_A => 16#16_289c# / Register_Width,
2209 PORT_TX_DW7_LN0_B => 16#06_c89c# / Register_Width,
2210 PORT_TX_DW7_LN0_C => 16#16_089c# / Register_Width,
2211 PORT_TX_DW7_GRP_A => 16#16_269c# / Register_Width,
2212 PORT_TX_DW7_GRP_B => 16#06_c69c# / Register_Width,
2213 PORT_TX_DW7_GRP_C => 16#16_069c# / Register_Width,
2214
2215 -- TGL DisplayPort transport
2216 TGL_DP_TP_CTL_A => 16#06_0540# / Register_Width,
2217 TGL_DP_TP_CTL_B => 16#06_1540# / Register_Width,
2218 TGL_DP_TP_CTL_C => 16#06_2540# / Register_Width,
2219 TGL_DP_TP_STATUS_A => 16#06_0544# / Register_Width,
2220 TGL_DP_TP_STATUS_B => 16#06_1544# / Register_Width,
2221 TGL_DP_TP_STATUS_C => 16#06_2544# / Register_Width,
2222 DPCLKA_CFGCR0 => 16#16_4280# / Register_Width,
2223 PORT_CL_DW10_C => 16#16_0028# / Register_Width,
2224
2225 -- MBUS DBOX
2226 PIPE_MBUS_DBOX_CTL_A => 16#07_003c# / Register_Width,
2227 PIPE_MBUS_DBOX_CTL_B => 16#07_103c# / Register_Width,
2228 PIPE_MBUS_DBOX_CTL_C => 16#07_203c# / Register_Width,
2229
2230 -- TGL+ new plane control registers
2231 PLANE_AUX_DIST_1_A => 16#07_01c0# / Register_Width,
2232 PLANE_AUX_DIST_1_B => 16#07_11c0# / Register_Width,
2233 PLANE_AUX_DIST_1_C => 16#07_21c0# / Register_Width,
2234 PLANE_COLOR_CTL_1_A => 16#07_01cc# / Register_Width,
2235 PLANE_COLOR_CTL_1_B => 16#07_11cc# / Register_Width,
2236 PLANE_COLOR_CTL_1_C => 16#07_21cc# / Register_Width,
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]2237 PLANE_COLOR_CTL_2_A => 16#07_02cc# / Register_Width,
2238 PLANE_COLOR_CTL_2_B => 16#07_12cc# / Register_Width,
2239 PLANE_COLOR_CTL_2_C => 16#07_22cc# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]2240
2241 -- TGL FIA registers
2242 PORT_TX_DFLEXDPCSSS_FIA1 => 16#16_3894# / Register_Width,
2243 PORT_TX_DFLEXDPMLE1_FIA1 => 16#16_38c0# / Register_Width,
2244 PORT_TX_DFLEXDPPMS_FIA1 => 16#16_3890# / Register_Width,
2245 PORT_TX_DFLEXDPSP_FIA1 => 16#16_38a0# / Register_Width,
2246 PORT_TX_DFLEXPA1_FIA1 => 16#16_3880# / Register_Width,
2247 PORT_TX_DFLEXDPCSSS_FIA2 => 16#16_e894# / Register_Width,
2248 PORT_TX_DFLEXDPMLE1_FIA2 => 16#16_e8c0# / Register_Width,
2249 PORT_TX_DFLEXDPPMS_FIA2 => 16#16_e890# / Register_Width,
2250 PORT_TX_DFLEXDPSP_FIA2 => 16#16_e8a0# / Register_Width,
2251 PORT_TX_DFLEXPA1_FIA2 => 16#16_e880# / Register_Width,
2252 PORT_TX_DFLEXDPCSSS_FIA3 => 16#16_f894# / Register_Width,
2253 PORT_TX_DFLEXDPMLE1_FIA3 => 16#16_f8c0# / Register_Width,
2254 PORT_TX_DFLEXDPPMS_FIA3 => 16#16_f890# / Register_Width,
2255 PORT_TX_DFLEXDPSP_FIA3 => 16#16_f8a0# / Register_Width,
2256 PORT_TX_DFLEXPA1_FIA3 => 16#16_f880# / Register_Width,
2257
2258 -- TGL DDI clock select
2259 DDI_CLK_SEL_USBC3 => 16#04_6114# / Register_Width,
2260 DDI_CLK_SEL_USBC4 => 16#04_6118# / Register_Width,
2261 DDI_CLK_SEL_USBC5 => 16#04_611c# / Register_Width,
2262 DDI_CLK_SEL_USBC6 => 16#04_6120# / Register_Width,
2263
2264 -- TGL DKL PLLs
2265 MGPLL1_ENABLE => 16#04_6030# / Register_Width,
2266 MGPLL2_ENABLE => 16#04_6034# / Register_Width,
2267 MGPLL3_ENABLE => 16#04_6038# / Register_Width,
2268 MGPLL4_ENABLE => 16#04_603c# / Register_Width,
2269 MGPLL6_ENABLE => 16#04_6044# / Register_Width,
2270
2271 -- ADL-P DKL PLLs
2272 PORTTC3_PLL1_ENABLE => 16#04_6048# / Register_Width,
2273 PORTTC4_PLL0_ENABLE => 16#04_604c# / Register_Width,
2274 PORTTC4_PLL1_ENABLE => 16#04_6050# / Register_Width,
2275
2276 -- TGL DKL Vswing
2277 DKL_TX_PMD_LANE_SUS_1 => 16#16_8d00# / Register_Width,
2278 DKL_TX_PMD_LANE_SUS_2 => 16#16_9d00# / Register_Width,
2279 DKL_TX_PMD_LANE_SUS_3 => 16#16_ad00# / Register_Width,
2280 DKL_TX_PMD_LANE_SUS_4 => 16#16_bd00# / Register_Width,
2281 DKL_TX_PMD_LANE_SUS_5 => 16#16_cd00# / Register_Width,
2282 DKL_TX_PMD_LANE_SUS_6 => 16#16_dd00# / Register_Width,
2283 DKL_TX_DPCNTL0_1 => 16#16_82c0# / Register_Width,
2284 DKL_TX_DPCNTL0_2 => 16#16_92c0# / Register_Width,
2285 DKL_TX_DPCNTL0_3 => 16#16_a2c0# / Register_Width,
2286 DKL_TX_DPCNTL0_4 => 16#16_b2c0# / Register_Width,
2287 DKL_TX_DPCNTL0_5 => 16#16_c2c0# / Register_Width,
2288 DKL_TX_DPCNTL0_6 => 16#16_d2c0# / Register_Width,
2289 DKL_TX_DPCNTL1_1 => 16#16_82c4# / Register_Width,
2290 DKL_TX_DPCNTL1_2 => 16#16_92c4# / Register_Width,
2291 DKL_TX_DPCNTL1_3 => 16#16_a2c4# / Register_Width,
2292 DKL_TX_DPCNTL1_4 => 16#16_b2c4# / Register_Width,
2293 DKL_TX_DPCNTL1_5 => 16#16_c2c4# / Register_Width,
2294 DKL_TX_DPCNTL1_6 => 16#16_d2c4# / Register_Width,
2295 DKL_TX_DPCNTL2_1 => 16#16_82c8# / Register_Width,
2296 DKL_TX_DPCNTL2_2 => 16#16_92c8# / Register_Width,
2297 DKL_TX_DPCNTL2_3 => 16#16_a2c8# / Register_Width,
2298 DKL_TX_DPCNTL2_4 => 16#16_b2c8# / Register_Width,
2299 DKL_TX_DPCNTL2_5 => 16#16_c2c8# / Register_Width,
2300 DKL_TX_DPCNTL2_6 => 16#16_d2c8# / Register_Width,
2301
2302 -- ADL-P DKL registers
2303 DKL_PCS_DW5_1 => 16#16_8014# / Register_Width,
2304 DKL_PCS_DW5_2 => 16#16_9014# / Register_Width,
2305 DKL_PCS_DW5_3 => 16#16_a014# / Register_Width,
2306 DKL_PCS_DW5_4 => 16#16_b014# / Register_Width,
2307
2308 -- ADL-P DDI status
2309 TCSS_DDI_STATUS_1 => 16#16_1500# / Register_Width,
2310 TCSS_DDI_STATUS_2 => 16#16_1504# / Register_Width,
2311 TCSS_DDI_STATUS_3 => 16#16_1508# / Register_Width,
2312 TCSS_DDI_STATUS_4 => 16#16_150c# / Register_Width,
2313
2314 DISPLAY_ERR_FATAL_MASK => 16#04_421c# / Register_Width,
2315 MBUS_CTL => 16#04_438c# / Register_Width);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2316
2317 subtype Registers_Index is Registers_Invalid_Index range
2318 Registers_Invalid_Index'Succ (Invalid_Register) ..
2319 Registers_Invalid_Index'Last;
2320
2321 -- aliased registers
2322 DP_CTL_A : constant Registers_Index := DDI_BUF_CTL_A;
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]2323 GMCH_DP_B : constant Registers_Index := DDI_BUF_CTL_B;
2324 GMCH_DP_C : constant Registers_Index := DDI_BUF_CTL_C;
2325 GMCH_DP_D : constant Registers_Index := DDI_BUF_CTL_D;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2326 DP_AUX_CTL_A : constant Registers_Index := DDI_AUX_CTL_A;
2327 DP_AUX_DATA_A_1 : constant Registers_Index := DDI_AUX_DATA_A_1;
2328 DP_AUX_DATA_A_2 : constant Registers_Index := DDI_AUX_DATA_A_2;
2329 DP_AUX_DATA_A_3 : constant Registers_Index := DDI_AUX_DATA_A_3;
2330 DP_AUX_DATA_A_4 : constant Registers_Index := DDI_AUX_DATA_A_4;
2331 DP_AUX_DATA_A_5 : constant Registers_Index := DDI_AUX_DATA_A_5;
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]2332 ILK_DISPLAY_CHICKEN1 : constant Registers_Index := FUSE_STATUS;
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]2333 GMCH_ADPA : constant Registers_Index := FDI_TX_CTL_B;
2334 GMCH_HDMIB : constant Registers_Index := GMCH_SDVOB;
2335 GMCH_HDMIC : constant Registers_Index := GMCH_SDVOC;
Nico Huber75a707f2018-06-18 16:28:33 +0200[diff] [blame]2336 CURACNTR : constant Registers_Index := CUR_CTL_A;
2337 CURABASE : constant Registers_Index := CUR_BASE_A;
2338 CURAPOS : constant Registers_Index := CUR_POS_A;
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]2339 SPACNTR : constant Registers_Index := PLANE_CTL_2_A;
2340 SPBCNTR : constant Registers_Index := PLANE_CTL_2_B;
2341 SPCCNTR : constant Registers_Index := PLANE_CTL_2_C;
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]2342 BXT_BLC_PWM_CTL_1 : constant Registers_Index := BLC_PWM_PCH_CTL1;
2343 BXT_BLC_PWM_FREQ_1 : constant Registers_Index := BLC_PWM_PCH_CTL2;
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]2344 PHY_MISC_A : constant Registers_Index := BXT_PHY_CTL_A;
2345 PORT_COMP_DW0_B : constant Registers_Index := BXT_PORT_PLL_0_B;
2346 PORT_COMP_DW1_B : constant Registers_Index := BXT_PORT_PLL_1_B;
2347 PORT_COMP_DW3_B : constant Registers_Index := BXT_PORT_PLL_3_B;
2348 PORT_COMP_DW0_A : constant Registers_Index := BXT_PORT_PLL_0_A;
2349 PORT_COMP_DW1_A : constant Registers_Index := BXT_PORT_PLL_1_A;
2350 PORT_COMP_DW3_A : constant Registers_Index := BXT_PORT_PLL_3_A;
2351 PORT_COMP_DW9_A : constant Registers_Index := BXT_PORT_PLL_9_A;
2352 PORT_COMP_DW9_B : constant Registers_Index := BXT_PORT_PLL_9_B;
2353 PORT_COMP_DW8_A : constant Registers_Index := BXT_PORT_PLL_8_A;
2354 PORT_COMP_DW8_B : constant Registers_Index := BXT_PORT_PLL_8_B;
2355 PORT_COMP_DW10_A : constant Registers_Index := BXT_PORT_PLL_10_A;
2356 PORT_COMP_DW10_B : constant Registers_Index := BXT_PORT_PLL_10_B;
2357 CDCLK_PLL_ENABLE : constant Registers_Index := BXT_DE_PLL_ENABLE;
2358 DDI_AUX_CTL_USBC1 : constant Registers_Index := DDI_AUX_CTL_D;
2359 DDI_AUX_DATA_USBC1_1 : constant Registers_Index := DDI_AUX_DATA_D_1;
2360 DDI_AUX_DATA_USBC1_2 : constant Registers_Index := DDI_AUX_DATA_D_2;
2361 DDI_AUX_DATA_USBC1_3 : constant Registers_Index := DDI_AUX_DATA_D_3;
2362 DDI_AUX_DATA_USBC1_4 : constant Registers_Index := DDI_AUX_DATA_D_4;
2363 DDI_AUX_DATA_USBC1_5 : constant Registers_Index := DDI_AUX_DATA_D_5;
2364 DPLL_0_ENABLE : constant Registers_Index := LCPLL1_CTL;
2365 DPLL_1_ENABLE : constant Registers_Index := LCPLL2_CTL;
2366 PORT_CL_DW10_A : constant Registers_Index := BXT_PORT_CL1CM_DW10_A;
2367 PORT_CL_DW10_B : constant Registers_Index := BXT_PORT_CL1CM_DW10_BC;
2368 DDI_CLK_SEL_USBC1 : constant Registers_Index := PORT_CLK_SEL_DDID;
2369 DDI_CLK_SEL_USBC2 : constant Registers_Index := PORT_CLK_SEL_DDIE;
2370 MGPLL5_ENABLE : constant Registers_Index := WRPLL_CTL_1;
2371 DDI_BUF_CTL_USBC1 : constant Registers_Index := DDI_BUF_CTL_D;
2372 DDI_BUF_CTL_USBC2 : constant Registers_Index := DDI_BUF_CTL_E;
2373 DDI_BUF_CTL_USBC6 : constant Registers_Index := SRD_CTL;
2374 PORTTC1_PLL0_ENABLE : constant Registers_Index := MGPLL2_ENABLE;
2375 PORTTC1_PLL1_ENABLE : constant Registers_Index := MGPLL3_ENABLE;
2376 PORTTC2_PLL0_ENABLE : constant Registers_Index := MGPLL4_ENABLE;
2377 PORTTC2_PLL1_ENABLE : constant Registers_Index := WRPLL_CTL_1;
2378 PORTTC3_PLL0_ENABLE : constant Registers_Index := MGPLL6_ENABLE;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2379
2380 ---------------------------------------------------------------------------
2381
2382 Default_Timeout_MS : constant := 10;
2383
2384 ---------------------------------------------------------------------------
2385
2386 procedure Posting_Read
2387 (Register : in Registers_Index)
2388 with
2389 Global => (In_Out => Register_State),
2390 Depends => (Register_State =>+ (Register)),
2391 Pre => True,
2392 Post => True;
2393
2394 pragma Warnings (GNATprove, Off, "unused variable ""Verbose""",
2395 Reason => "Only used on debugging path");
2396 procedure Read
2397 (Register : in Registers_Index;
2398 Value : out Word32;
2399 Verbose : in Boolean := True)
2400 with
2401 Global => (In_Out => Register_State),
2402 Depends => ((Value, Register_State) => (Register, Register_State),
2403 null => Verbose),
2404 Pre => True,
2405 Post => True;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2406
2407 procedure Write
2408 (Register : Registers_Index;
Nico Huberaae8a352020-06-15 13:09:29 +0200[diff] [blame]2409 Value : Word32;
2410 Verbose : Boolean := True)
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2411 with
2412 Global => (In_Out => Register_State),
Nico Huberaae8a352020-06-15 13:09:29 +0200[diff] [blame]2413 Depends => (Register_State => (Register, Register_State, Value),
2414 null => Verbose),
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2415 Pre => True,
2416 Post => True;
Nico Huberaae8a352020-06-15 13:09:29 +0200[diff] [blame]2417 pragma Warnings (GNATprove, On, "unused variable ""Verbose""");
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2418
2419 procedure Is_Set_Mask
2420 (Register : in Registers_Index;
2421 Mask : in Word32;
2422 Result : out Boolean);
2423
2424 pragma Warnings (GNATprove, Off, "unused initial value of ""Verbose""",
2425 Reason => "Only used on debugging path");
Nico Huberbcb2c472017-02-02 16:39:26 +0100[diff] [blame]2426 procedure Wait
Nico Huber82ca09f2019-09-28 02:37:50 +0200[diff] [blame]2427 (Register : in Registers_Index;
2428 Mask : in Word32;
2429 Value : in Word32;
2430 TOut_MS : in Natural := Default_Timeout_MS;
2431 Verbose : in Boolean := False;
2432 Success : out Boolean);
2433 procedure Wait
Nico Huberbcb2c472017-02-02 16:39:26 +0100[diff] [blame]2434 (Register : Registers_Index;
2435 Mask : Word32;
2436 Value : Word32;
2437 TOut_MS : Natural := Default_Timeout_MS;
2438 Verbose : Boolean := False);
2439
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2440 procedure Wait_Set_Mask
Nico Huber82ca09f2019-09-28 02:37:50 +0200[diff] [blame]2441 (Register : in Registers_Index;
2442 Mask : in Word32;
2443 TOut_MS : in Natural := Default_Timeout_MS;
2444 Verbose : in Boolean := False;
2445 Success : out Boolean);
2446 procedure Wait_Set_Mask
2447 (Register : Registers_Index;
2448 Mask : Word32;
2449 TOut_MS : Natural := Default_Timeout_MS;
2450 Verbose : Boolean := False);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2451
2452 procedure Wait_Unset_Mask
Nico Huber82ca09f2019-09-28 02:37:50 +0200[diff] [blame]2453 (Register : in Registers_Index;
2454 Mask : in Word32;
2455 TOut_MS : in Natural := Default_Timeout_MS;
2456 Verbose : in Boolean := False;
2457 Success : out Boolean);
2458 procedure Wait_Unset_Mask
2459 (Register : Registers_Index;
2460 Mask : Word32;
2461 TOut_MS : Natural := Default_Timeout_MS;
2462 Verbose : Boolean := False);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2463 pragma Warnings (GNATprove, On, "unused initial value of ""Verbose""");
2464
2465 procedure Set_Mask
2466 (Register : Registers_Index;
2467 Mask : Word32);
2468
2469 procedure Unset_Mask
2470 (Register : Registers_Index;
2471 Mask : Word32);
2472
2473 procedure Unset_And_Set_Mask
2474 (Register : Registers_Index;
2475 Mask_Unset : Word32;
2476 Mask_Set : Word32);
2477
Nico Huber17d64b62017-07-15 20:51:25 +0200[diff] [blame]2478 procedure Clear_Fences;
2479
Nico Huberb03c8f12017-08-25 13:29:08 +0200[diff] [blame]2480 procedure Add_Fence
2481 (First_Page : in GTT_Range;
2482 Last_Page : in GTT_Range;
2483 Tiling : in XY_Tiling;
2484 Pitch : in Natural;
Arthur Heymans960e2392026-03-03 19:45:24 +0100[diff] [blame]2485 Success : out Boolean)
2486 with
2487 Pre => Last_Page >= First_Page;
Nico Huberb03c8f12017-08-25 13:29:08 +0200[diff] [blame]2488
2489 procedure Remove_Fence (First_Page, Last_Page : GTT_Range);
2490
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]2491 pragma Warnings (GNATprove, Off, "no check message justified by this",
2492 Reason => "see Annotate aspects.");
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2493 procedure Write_GTT
2494 (GTT_Page : GTT_Range;
2495 Device_Address : GTT_Address_Type;
2496 Valid : Boolean)
2497 with
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]2498 Global =>
2499 (Input => Config.Variable,
2500 In_Out => GTT_State),
2501 Depends =>
2502 (GTT_State =>+ (Config.Variable, GTT_Page, Device_Address, Valid)),
2503 Annotate =>
2504 (GNATprove, Intentional,
Nico Hubere317e9c2019-09-29 03:03:18 +0200[diff] [blame]2505 """GMA.State"" of ""Write_GTT"" not read",
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]2506 "Reading of Config_State depends on the platform configuration.");
Nico Huberceda17d2018-06-09 22:00:29 +0200[diff] [blame]2507
2508 procedure Read_GTT
2509 (Device_Address : out GTT_Address_Type;
2510 Valid : out Boolean;
2511 GTT_Page : in GTT_Range)
2512 with
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]2513 Global =>
2514 (Input => Config.Variable,
2515 In_Out => GTT_State),
2516 Depends =>
2517 ((Device_Address, Valid, GTT_State) =>
2518 (Config.Variable, GTT_State, GTT_Page)),
2519 Annotate =>
2520 (GNATprove, Intentional,
Nico Hubere317e9c2019-09-29 03:03:18 +0200[diff] [blame]2521 """GMA.State"" of ""Read_GTT"" not read",
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]2522 "Reading of Config_State depends on the platform configuration.");
2523 pragma Warnings (GNATprove, On, "no check message justified by this");
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2524
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]2525 procedure Set_Register_Base (Base : Word64; GTT_Base : Word64 := 0)
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2526 with
2527 Global => (Output => Address_State),
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]2528 Depends => (Address_State => (Base, GTT_Base)),
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2529 Pre => True,
2530 Post => True;
2531
2532end HW.GFX.GMA.Registers;