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review.sourcearcade.org / libgfxinit / 0947273288ec221c752ebf641e70c44ee7241e28 / . / common / hw-gfx-gma-registers.ads
blob: 02e75201e6a7f9d5af370624dc8d4fe6870c487d [file] [log] [blame]
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1--
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]2-- Copyright (C) 2015-2017 secunet Security Networks AG
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +0200[diff] [blame]6-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]8--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
15with System;
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]16with HW.GFX.GMA.Config;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]17
18private package HW.GFX.GMA.Registers
19with
20 Abstract_State =>
21 ((Address_State with Part_Of => GMA.State),
22 (Register_State with External, Part_Of => GMA.Device_State),
23 (GTT_State with External, Part_Of => GMA.Device_State)),
24 Initializes => Address_State
25is
Nico Huber0b2329a2018-06-09 21:14:27 +0200[diff] [blame]26
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]27 type Registers_Invalid_Index is
28 (Invalid_Register, -- Allow a placeholder when access is not acceptable
29
30 RCS_RING_BUFFER_TAIL,
31 RCS_RING_BUFFER_HEAD,
32 RCS_RING_BUFFER_STRT,
33 RCS_RING_BUFFER_CTL,
34 QUIRK_02084,
35 QUIRK_02090,
36 HWSTAM,
37 MI_MODE,
38 INSTPM,
39 GT_MODE,
40 CACHE_MODE_0,
41 CTX_SIZE,
42 PP_DCLV_HIGH,
43 PP_DCLV_LOW,
44 GFX_MODE,
45 ARB_MODE,
46 HWS_PGA,
47 GAM_ECOCHK,
Arthur Heymans229ed1c2018-03-28 16:45:43 +0200[diff] [blame]48 GMCH_GMBUS0,
49 GMCH_GMBUS1,
50 GMCH_GMBUS2,
51 GMCH_GMBUS3,
52 GMCH_GMBUS4,
53 GMCH_GMBUS5,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]54 GMCH_DPLL_A,
55 GMCH_DPLL_B,
56 GMCH_FPA0,
57 GMCH_FPA1,
58 GMCH_FPB0,
59 GMCH_FPB1,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]60 MBCTL,
61 UCGCTL1,
62 UCGCTL2,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]63 GMCH_CLKCFG,
Nico Huberb47a5c42019-09-29 00:07:21 +0200[diff] [blame]64 GMCH_HPLLVCO_MOBILE,
65 GMCH_HPLLVCO,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]66 VCS_RING_BUFFER_TAIL,
67 VCS_RING_BUFFER_HEAD,
68 VCS_RING_BUFFER_STRT,
69 VCS_RING_BUFFER_CTL,
70 SLEEP_PSMI_CONTROL,
71 VCS_HWSTAM,
72 VCS_PP_DCLV_HIGH,
73 VCS_PP_DCLV_LOW,
74 GAC_ECO_BITS,
75 BCS_RING_BUFFER_TAIL,
76 BCS_RING_BUFFER_HEAD,
77 BCS_RING_BUFFER_STRT,
78 BCS_RING_BUFFER_CTL,
79 BCS_HWSTAM,
80 BCS_PP_DCLV_HIGH,
81 BCS_PP_DCLV_LOW,
82 GAB_CTL_REG,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]83 CPU_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]84 FUSE_STATUS,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]85 ILK_DISPLAY_CHICKEN2,
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]86 FUSE_STRAP,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]87 DSPCLK_GATE_D,
88 FBA_CFB_BASE,
89 FBC_CTL,
90 IPS_CTL,
91 DEISR,
92 DEIMR,
93 DEIIR,
94 DEIER,
95 GTISR,
96 GTIMR,
97 GTIIR,
98 GTIER,
99 IIR,
100 HOTPLUG_CTL,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]101 TC_HOTPLUG_CTL,
102 DISPLAY_ERR_FATAL_MASK,
103 DBUF_CTL_S2,
104 DBUF_CTL_S3,
105 MBUS_CTL,
106 GEN11_DE_HPD_ISR,
107 DBUF_CTL_S1,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]108 ARB_CTL,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]109 DBUF_CTL_S0,
110 MBUS_ABOX_CTL,
111 MBUS_ABOX1_CTL,
112 MBUS_ABOX2_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]113 WM_PIPE_A,
114 WM_PIPE_B,
115 WM1_LP_ILK,
116 WM2_LP_ILK,
117 WM3_LP_ILK,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]118 BW_BUDDY1_CTL,
119 BW_BUDDY1_PAGE_MASK,
120 BW_BUDDY2_CTL,
121 BW_BUDDY2_PAGE_MASK,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]122 WM_PIPE_C,
123 WM_LINETIME_A,
124 WM_LINETIME_B,
125 WM_LINETIME_C,
126 PWR_WELL_CTL_BIOS,
127 PWR_WELL_CTL_DRIVER,
128 PWR_WELL_CTL_KVMR,
129 PWR_WELL_CTL_DEBUG,
130 PWR_WELL_CTL5,
131 PWR_WELL_CTL6,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]132 PWR_AUX_CTL_BIOS,
133 PWR_AUX_CTL_DRIVER,
134 PWR_DDI_CTL_BIOS,
135 PWR_DDI_CTL_DRIVER,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]136 CDCLK_CTL,
137 LCPLL1_CTL,
138 LCPLL2_CTL,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]139 DPLL_4_ENABLE,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]140 SPLL_CTL,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]141 MGPLL1_ENABLE,
142 MGPLL2_ENABLE,
143 MGPLL3_ENABLE,
144 MGPLL4_ENABLE,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]145 WRPLL_CTL_1,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]146 MGPLL6_ENABLE,
147 PORTTC3_PLL1_ENABLE,
148 PORTTC4_PLL0_ENABLE,
149 PORTTC4_PLL1_ENABLE,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]150 WRPLL_CTL_2,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]151 BXT_DE_PLL_ENABLE,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]152 BXT_PORT_PLL_ENABLE_A,
153 BXT_PORT_PLL_ENABLE_B,
154 BXT_PORT_PLL_ENABLE_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]155 PORT_CLK_SEL_DDIA,
156 PORT_CLK_SEL_DDIB,
157 PORT_CLK_SEL_DDIC,
158 PORT_CLK_SEL_DDID,
159 PORT_CLK_SEL_DDIE,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]160 DDI_CLK_SEL_USBC3,
161 DDI_CLK_SEL_USBC4,
162 DDI_CLK_SEL_USBC5,
163 DDI_CLK_SEL_USBC6,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]164 TRANSA_CLK_SEL,
165 TRANSB_CLK_SEL,
166 TRANSC_CLK_SEL,
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]167 CDCLK_FREQ,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]168 NDE_RSTWRN_OPT,
Angel Ponsae186bd2020-10-21 21:37:34 +0200[diff] [blame]169 GEN8_CHICKEN_DCPR_1,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]170 GEN11_CHICKEN_DCPR_2,
171 GEN9_CLKGATE_DIS_0,
172 GEN9_CHICKEN_DPCR_3,
173 GEN9_CLKGATE_DIS_5,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]174 BLC_PWM_CPU_CTL2,
175 BLC_PWM_CPU_CTL,
Nico Huber6b4678d2019-09-22 21:31:52 +0200[diff] [blame]176 DFSM,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]177 DSSM,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]178 HTOTAL_A,
179 HBLANK_A,
180 HSYNC_A,
181 VTOTAL_A,
182 VBLANK_A,
183 VSYNC_A,
184 PIPEASRC,
185 PIPE_VSYNCSHIFT_A,
186 PIPEA_DATA_M1,
187 PIPEA_DATA_N1,
188 PIPEA_LINK_M1,
189 PIPEA_LINK_N1,
190 FDI_TX_CTL_A,
191 PIPEA_DDI_FUNC_CTL,
192 PIPEA_MSA_MISC,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]193 TGL_DP_TP_CTL_A,
194 TGL_DP_TP_STATUS_A,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]195 SRD_CTL_A,
196 SRD_STATUS_A,
197 HTOTAL_B,
198 HBLANK_B,
199 HSYNC_B,
200 VTOTAL_B,
201 VBLANK_B,
202 VSYNC_B,
203 PIPEBSRC,
204 PIPE_VSYNCSHIFT_B,
205 PIPEB_DATA_M1,
206 PIPEB_DATA_N1,
207 PIPEB_LINK_M1,
208 PIPEB_LINK_N1,
209 FDI_TX_CTL_B,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]210 PORT_HOTPLUG_EN,
211 PORT_HOTPLUG_STAT,
212 GMCH_SDVOB,
213 GMCH_SDVOC,
214 GMCH_LVDS,
Arthur Heymanse87d0d12018-03-28 17:02:49 +0200[diff] [blame]215 GMCH_PP_STATUS,
216 GMCH_PP_CONTROL,
217 GMCH_PP_ON_DELAYS,
218 GMCH_PP_OFF_DELAYS,
219 GMCH_PP_DIVISOR,
Arthur Heymansd5198442018-03-28 17:05:12 +0200[diff] [blame]220 GMCH_PFIT_CONTROL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]221 PIPEB_DDI_FUNC_CTL,
222 PIPEB_MSA_MISC,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]223 TGL_DP_TP_CTL_B,
224 TGL_DP_TP_STATUS_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]225 SRD_CTL_B,
226 SRD_STATUS_B,
227 HTOTAL_C,
228 HBLANK_C,
229 HSYNC_C,
230 VTOTAL_C,
231 VBLANK_C,
232 VSYNC_C,
233 PIPECSRC,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]234 G4X_AUD_VID_DID,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]235 PIPE_VSYNCSHIFT_C,
236 PIPEC_DATA_M1,
237 PIPEC_DATA_N1,
238 PIPEC_LINK_M1,
239 PIPEC_LINK_N1,
240 FDI_TX_CTL_C,
241 PIPEC_DDI_FUNC_CTL,
242 PIPEC_MSA_MISC,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]243 TGL_DP_TP_CTL_C,
244 TGL_DP_TP_STATUS_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]245 SRD_CTL_C,
246 SRD_STATUS_C,
247 DDI_BUF_CTL_A,
248 DDI_AUX_CTL_A,
249 DDI_AUX_DATA_A_1,
250 DDI_AUX_DATA_A_2,
251 DDI_AUX_DATA_A_3,
252 DDI_AUX_DATA_A_4,
253 DDI_AUX_DATA_A_5,
254 DDI_AUX_MUTEX_A,
255 DP_TP_CTL_A,
256 DDI_BUF_CTL_B,
257 DDI_AUX_CTL_B,
258 DDI_AUX_DATA_B_1,
259 DDI_AUX_DATA_B_2,
260 DDI_AUX_DATA_B_3,
261 DDI_AUX_DATA_B_4,
262 DDI_AUX_DATA_B_5,
263 DDI_AUX_MUTEX_B,
264 DP_TP_CTL_B,
265 DP_TP_STATUS_B,
266 DDI_BUF_CTL_C,
267 DDI_AUX_CTL_C,
268 DDI_AUX_DATA_C_1,
269 DDI_AUX_DATA_C_2,
270 DDI_AUX_DATA_C_3,
271 DDI_AUX_DATA_C_4,
272 DDI_AUX_DATA_C_5,
273 DDI_AUX_MUTEX_C,
274 DP_TP_CTL_C,
275 DP_TP_STATUS_C,
276 DDI_BUF_CTL_D,
277 DDI_AUX_CTL_D,
278 DDI_AUX_DATA_D_1,
279 DDI_AUX_DATA_D_2,
280 DDI_AUX_DATA_D_3,
281 DDI_AUX_DATA_D_4,
282 DDI_AUX_DATA_D_5,
283 DDI_AUX_MUTEX_D,
284 DP_TP_CTL_D,
285 DP_TP_STATUS_D,
286 DDI_BUF_CTL_E,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]287 DDI_AUX_CTL_USBC2,
288 DDI_AUX_DATA_USBC2_1,
289 DDI_AUX_DATA_USBC2_2,
290 DDI_AUX_DATA_USBC2_3,
291 DDI_AUX_DATA_USBC2_4,
292 DDI_AUX_DATA_USBC2_5,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]293 DP_TP_CTL_E,
294 DP_TP_STATUS_E,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]295 DDI_BUF_CTL_USBC3,
296 DDI_AUX_CTL_USBC3,
297 DDI_AUX_DATA_USBC3_1,
298 DDI_AUX_DATA_USBC3_2,
299 DDI_AUX_DATA_USBC3_3,
300 DDI_AUX_DATA_USBC3_4,
301 DDI_AUX_DATA_USBC3_5,
302 DDI_BUF_CTL_USBC4,
303 DDI_AUX_CTL_USBC4,
304 DDI_AUX_DATA_USBC4_1,
305 DDI_AUX_DATA_USBC4_2,
306 DDI_AUX_DATA_USBC4_3,
307 DDI_AUX_DATA_USBC4_4,
308 DDI_AUX_DATA_USBC4_5,
309 DDI_BUF_CTL_USBC5,
310 DDI_AUX_CTL_USBC5,
311 DDI_AUX_DATA_USBC5_1,
312 DDI_AUX_DATA_USBC5_2,
313 DDI_AUX_DATA_USBC5_3,
314 DDI_AUX_DATA_USBC5_4,
315 DDI_AUX_DATA_USBC5_5,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]316 SRD_CTL,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]317 DDI_AUX_CTL_USBC6,
318 DDI_AUX_DATA_USBC6_1,
319 DDI_AUX_DATA_USBC6_2,
320 DDI_AUX_DATA_USBC6_3,
321 DDI_AUX_DATA_USBC6_4,
322 DDI_AUX_DATA_USBC6_5,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]323 SRD_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]324 BXT_PHY_CTL_A,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]325 PHY_MISC_B,
326 PHY_MISC_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]327 BXT_PHY_CTL_B,
328 BXT_PHY_CTL_C,
329 BXT_PHY_CTL_FAM_EDP,
330 BXT_PHY_CTL_FAM_DDI,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]331 DDI_BUF_TRANS_A_S0T1,
332 DDI_BUF_TRANS_A_S0T2,
333 DDI_BUF_TRANS_A_S1T1,
334 DDI_BUF_TRANS_A_S1T2,
335 DDI_BUF_TRANS_A_S2T1,
336 DDI_BUF_TRANS_A_S2T2,
337 DDI_BUF_TRANS_A_S3T1,
338 DDI_BUF_TRANS_A_S3T2,
339 DDI_BUF_TRANS_A_S4T1,
340 DDI_BUF_TRANS_A_S4T2,
341 DDI_BUF_TRANS_A_S5T1,
342 DDI_BUF_TRANS_A_S5T2,
343 DDI_BUF_TRANS_A_S6T1,
344 DDI_BUF_TRANS_A_S6T2,
345 DDI_BUF_TRANS_A_S7T1,
346 DDI_BUF_TRANS_A_S7T2,
347 DDI_BUF_TRANS_A_S8T1,
348 DDI_BUF_TRANS_A_S8T2,
349 DDI_BUF_TRANS_A_S9T1,
350 DDI_BUF_TRANS_A_S9T2,
351 DDI_BUF_TRANS_B_S0T1,
352 DDI_BUF_TRANS_B_S0T2,
353 DDI_BUF_TRANS_B_S1T1,
354 DDI_BUF_TRANS_B_S1T2,
355 DDI_BUF_TRANS_B_S2T1,
356 DDI_BUF_TRANS_B_S2T2,
357 DDI_BUF_TRANS_B_S3T1,
358 DDI_BUF_TRANS_B_S3T2,
359 DDI_BUF_TRANS_B_S4T1,
360 DDI_BUF_TRANS_B_S4T2,
361 DDI_BUF_TRANS_B_S5T1,
362 DDI_BUF_TRANS_B_S5T2,
363 DDI_BUF_TRANS_B_S6T1,
364 DDI_BUF_TRANS_B_S6T2,
365 DDI_BUF_TRANS_B_S7T1,
366 DDI_BUF_TRANS_B_S7T2,
367 DDI_BUF_TRANS_B_S8T1,
368 DDI_BUF_TRANS_B_S8T2,
369 DDI_BUF_TRANS_B_S9T1,
370 DDI_BUF_TRANS_B_S9T2,
371 DDI_BUF_TRANS_C_S0T1,
372 DDI_BUF_TRANS_C_S0T2,
373 DDI_BUF_TRANS_C_S1T1,
374 DDI_BUF_TRANS_C_S1T2,
375 DDI_BUF_TRANS_C_S2T1,
376 DDI_BUF_TRANS_C_S2T2,
377 DDI_BUF_TRANS_C_S3T1,
378 DDI_BUF_TRANS_C_S3T2,
379 DDI_BUF_TRANS_C_S4T1,
380 DDI_BUF_TRANS_C_S4T2,
381 DDI_BUF_TRANS_C_S5T1,
382 DDI_BUF_TRANS_C_S5T2,
383 DDI_BUF_TRANS_C_S6T1,
384 DDI_BUF_TRANS_C_S6T2,
385 DDI_BUF_TRANS_C_S7T1,
386 DDI_BUF_TRANS_C_S7T2,
387 DDI_BUF_TRANS_C_S8T1,
388 DDI_BUF_TRANS_C_S8T2,
389 DDI_BUF_TRANS_C_S9T1,
390 DDI_BUF_TRANS_C_S9T2,
391 DDI_BUF_TRANS_D_S0T1,
392 DDI_BUF_TRANS_D_S0T2,
393 DDI_BUF_TRANS_D_S1T1,
394 DDI_BUF_TRANS_D_S1T2,
395 DDI_BUF_TRANS_D_S2T1,
396 DDI_BUF_TRANS_D_S2T2,
397 DDI_BUF_TRANS_D_S3T1,
398 DDI_BUF_TRANS_D_S3T2,
399 DDI_BUF_TRANS_D_S4T1,
400 DDI_BUF_TRANS_D_S4T2,
401 DDI_BUF_TRANS_D_S5T1,
402 DDI_BUF_TRANS_D_S5T2,
403 DDI_BUF_TRANS_D_S6T1,
404 DDI_BUF_TRANS_D_S6T2,
405 DDI_BUF_TRANS_D_S7T1,
406 DDI_BUF_TRANS_D_S7T2,
407 DDI_BUF_TRANS_D_S8T1,
408 DDI_BUF_TRANS_D_S8T2,
409 DDI_BUF_TRANS_D_S9T1,
410 DDI_BUF_TRANS_D_S9T2,
411 DDI_BUF_TRANS_E_S0T1,
412 DDI_BUF_TRANS_E_S0T2,
413 DDI_BUF_TRANS_E_S1T1,
414 DDI_BUF_TRANS_E_S1T2,
415 DDI_BUF_TRANS_E_S2T1,
416 DDI_BUF_TRANS_E_S2T2,
417 DDI_BUF_TRANS_E_S3T1,
418 DDI_BUF_TRANS_E_S3T2,
419 DDI_BUF_TRANS_E_S4T1,
420 DDI_BUF_TRANS_E_S4T2,
421 DDI_BUF_TRANS_E_S5T1,
422 DDI_BUF_TRANS_E_S5T2,
423 DDI_BUF_TRANS_E_S6T1,
424 DDI_BUF_TRANS_E_S6T2,
425 DDI_BUF_TRANS_E_S7T1,
426 DDI_BUF_TRANS_E_S7T2,
427 DDI_BUF_TRANS_E_S8T1,
428 DDI_BUF_TRANS_E_S8T2,
429 DDI_BUF_TRANS_E_S9T1,
430 DDI_BUF_TRANS_E_S9T2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]431 AUD_VID_DID,
432 PFA_WIN_POS,
433 PFA_WIN_SZ,
434 PFA_CTL_1,
435 PS_WIN_POS_1_A,
436 PS_WIN_SZ_1_A,
437 PS_CTRL_1_A,
438 PS_WIN_POS_2_A,
439 PS_WIN_SZ_2_A,
440 PS_CTRL_2_A,
441 PFB_WIN_POS,
442 PFB_WIN_SZ,
443 PFB_CTL_1,
444 PS_WIN_POS_1_B,
445 PS_WIN_SZ_1_B,
446 PS_CTRL_1_B,
447 PS_WIN_POS_2_B,
448 PS_WIN_SZ_2_B,
449 PS_CTRL_2_B,
450 PFC_WIN_POS,
451 PFC_WIN_SZ,
452 PFC_CTL_1,
453 PS_WIN_POS_1_C,
454 PS_WIN_SZ_1_C,
455 PS_CTRL_1_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]456 BXT_PORT_CL1CM_DW0_BC,
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]457 DISPIO_CR_TX_BMU_CR0,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]458 PORT_CL_DW5_B,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]459 BXT_PORT_CL1CM_DW9_BC,
460 BXT_PORT_CL1CM_DW10_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]461 BXT_PORT_PLL_EBB_0_B,
462 BXT_PORT_PLL_EBB_4_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]463 DPLL1_CFGR1,
464 DPLL1_CFGR2,
465 DPLL2_CFGR1,
466 DPLL2_CFGR2,
467 DPLL3_CFGR1,
468 DPLL3_CFGR2,
469 DPLL_CTRL1,
470 DPLL_CTRL2,
471 DPLL_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]472 BXT_PORT_CL1CM_DW28_BC,
473 BXT_PORT_CL1CM_DW30_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]474 BXT_PORT_PLL_0_B,
475 BXT_PORT_PLL_1_B,
476 BXT_PORT_PLL_2_B,
477 BXT_PORT_PLL_3_B,
478 BXT_PORT_PLL_6_B,
479 BXT_PORT_PLL_8_B,
480 BXT_PORT_PLL_9_B,
481 BXT_PORT_PLL_10_B,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]482 BXT_PORT_REF_DW3_BC,
483 BXT_PORT_REF_DW6_BC,
484 BXT_PORT_REF_DW8_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]485 BXT_PORT_PLL_EBB_0_C,
486 BXT_PORT_PLL_EBB_4_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]487 BXT_PORT_CL2CM_DW6_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]488 BXT_PORT_PLL_0_C,
489 BXT_PORT_PLL_1_C,
490 BXT_PORT_PLL_2_C,
491 BXT_PORT_PLL_3_C,
492 BXT_PORT_PLL_6_C,
493 BXT_PORT_PLL_8_C,
494 BXT_PORT_PLL_9_C,
495 BXT_PORT_PLL_10_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]496 BXT_PORT_PCS_DW10_01_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]497 BXT_PORT_PCS_DW12_01_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]498 BXT_PORT_TX_DW2_LN0_B,
499 BXT_PORT_TX_DW3_LN0_B,
500 BXT_PORT_TX_DW4_LN0_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]501 BXT_PORT_TX_DW14_LN0_B,
502 BXT_PORT_TX_DW14_LN1_B,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]503 PORT_PCS_DW1_GRP_B,
504 PORT_TX_DW2_GRP_B,
505 PORT_TX_DW4_GRP_B,
506 PORT_TX_DW5_GRP_B,
507 PORT_TX_DW7_GRP_B,
508 PORT_TX_DW8_GRP_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]509 BXT_PORT_TX_DW14_LN2_B,
510 BXT_PORT_TX_DW14_LN3_B,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]511 PORT_PCS_DW1_LN0_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]512 BXT_PORT_PCS_DW10_01_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]513 BXT_PORT_PCS_DW12_01_C,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]514 PORT_TX_DW2_LN0_B,
515 PORT_TX_DW4_LN0_B,
516 PORT_TX_DW5_LN0_B,
517 PORT_TX_DW7_LN0_B,
518 PORT_TX_DW8_LN0_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]519 BXT_PORT_TX_DW2_LN0_C,
520 BXT_PORT_TX_DW3_LN0_C,
521 BXT_PORT_TX_DW4_LN0_C,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]522 BXT_PORT_TX_DW14_LN0_C,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]523 PORT_TX_DW4_LN1_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]524 BXT_PORT_TX_DW14_LN1_C,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]525 PORT_TX_DW4_LN2_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]526 BXT_PORT_TX_DW14_LN2_C,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]527 PORT_TX_DW4_LN3_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]528 BXT_PORT_TX_DW14_LN3_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]529 BXT_PORT_PCS_DW10_GRP_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]530 BXT_PORT_PCS_DW12_GRP_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]531 BXT_PORT_TX_DW2_GRP_B,
532 BXT_PORT_TX_DW3_GRP_B,
533 BXT_PORT_TX_DW4_GRP_B,
534 BXT_PORT_PCS_DW10_GRP_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]535 BXT_PORT_PCS_DW12_GRP_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]536 BXT_PORT_TX_DW2_GRP_C,
537 BXT_PORT_TX_DW3_GRP_C,
538 BXT_PORT_TX_DW4_GRP_C,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]539 BXT_DE_PLL_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]540 HTOTAL_EDP,
541 HBLANK_EDP,
542 HSYNC_EDP,
543 VTOTAL_EDP,
544 VBLANK_EDP,
545 VSYNC_EDP,
546 PIPE_EDP_DATA_M1,
547 PIPE_EDP_DATA_N1,
548 PIPE_EDP_LINK_M1,
549 PIPE_EDP_LINK_N1,
550 PIPE_EDP_DDI_FUNC_CTL,
551 PIPE_EDP_MSA_MISC,
552 SRD_CTL_EDP,
553 SRD_STATUS_EDP,
554 PIPE_SCANLINE_A,
555 PIPEACONF,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]556 PIPEA_ARB_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]557 PIPEAMISC,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]558 PIPEA_CHICKEN,
559 PIPE_MBUS_DBOX_CTL_A,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]560 PIPE_FRMCNT_A,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]561 PIPEA_GMCH_DATA_M,
562 PIPEA_GMCH_DATA_N,
563 PIPEA_GMCH_LINK_M,
564 PIPEA_GMCH_LINK_N,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]565 CUR_CTL_A,
566 CUR_BASE_A,
567 CUR_POS_A,
568 CUR_FBC_CTL_A,
Nico Huber75a707f2018-06-18 16:28:33 +0200[diff] [blame]569 CURBCNTR,
570 CURBBASE,
571 CURBPOS,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]572 CUR_WM_A_0,
573 CUR_WM_A_1,
574 CUR_WM_A_2,
575 CUR_WM_A_3,
576 CUR_WM_A_4,
577 CUR_WM_A_5,
578 CUR_WM_A_6,
579 CUR_WM_A_7,
580 CUR_BUF_CFG_A,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]581 DSPACNTR,
582 DSPALINOFF,
583 DSPASTRIDE,
584 PLANE_POS_1_A,
585 PLANE_SIZE_1_A,
Nico Huberf7a644b2020-10-20 15:26:01 +0200[diff] [blame]586 PLANE_KEYVAL_1_A,
587 PLANE_KEYMSK_1_A,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]588 DSPASURF,
589 DSPATILEOFF,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]590 PLANE_AUX_DIST_1_A,
591 PLANE_COLOR_CTL_1_A,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]592 PLANE_WM_1_A_0,
593 PLANE_WM_1_A_1,
594 PLANE_WM_1_A_2,
595 PLANE_WM_1_A_3,
596 PLANE_WM_1_A_4,
597 PLANE_WM_1_A_5,
598 PLANE_WM_1_A_6,
599 PLANE_WM_1_A_7,
600 PLANE_BUF_CFG_1_A,
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]601 PLANE_CTL_2_A,
602 PLANE_STRIDE_2_A,
603 PLANE_POS_2_A,
604 PLANE_SIZE_2_A,
Nico Huberf7a644b2020-10-20 15:26:01 +0200[diff] [blame]605 PLANE_KEYVAL_2_A,
606 PLANE_KEYMSK_2_A,
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]607 PLANE_SURF_2_A,
608 PLANE_OFFSET_2_A,
609 PLANE_COLOR_CTL_2_A,
610 PLANE_WM_2_A_0,
611 PLANE_WM_2_A_1,
612 PLANE_WM_2_A_2,
613 PLANE_WM_2_A_3,
614 PLANE_WM_2_A_4,
615 PLANE_WM_2_A_5,
616 PLANE_WM_2_A_6,
617 PLANE_WM_2_A_7,
618 PLANE_BUF_CFG_2_A,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]619 PIPE_SCANLINE_B,
620 PIPEBCONF,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]621 PIPEB_ARB_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]622 PIPEBMISC,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]623 PIPEB_CHICKEN,
624 PIPE_MBUS_DBOX_CTL_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]625 PIPE_FRMCNT_B,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]626 PIPEB_GMCH_DATA_M,
627 PIPEB_GMCH_DATA_N,
628 PIPEB_GMCH_LINK_M,
629 PIPEB_GMCH_LINK_N,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]630 CUR_CTL_B,
631 CUR_BASE_B,
632 CUR_POS_B,
633 CUR_FBC_CTL_B,
634 CUR_WM_B_0,
635 CUR_WM_B_1,
636 CUR_WM_B_2,
637 CUR_WM_B_3,
638 CUR_WM_B_4,
639 CUR_WM_B_5,
640 CUR_WM_B_6,
641 CUR_WM_B_7,
642 CUR_BUF_CFG_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]643 DSPBCNTR,
644 DSPBLINOFF,
645 DSPBSTRIDE,
646 PLANE_POS_1_B,
647 PLANE_SIZE_1_B,
Nico Huberf7a644b2020-10-20 15:26:01 +0200[diff] [blame]648 PLANE_KEYVAL_1_B,
649 PLANE_KEYMSK_1_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]650 DSPBSURF,
651 DSPBTILEOFF,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]652 PLANE_AUX_DIST_1_B,
653 PLANE_COLOR_CTL_1_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]654 PLANE_WM_1_B_0,
655 PLANE_WM_1_B_1,
656 PLANE_WM_1_B_2,
657 PLANE_WM_1_B_3,
658 PLANE_WM_1_B_4,
659 PLANE_WM_1_B_5,
660 PLANE_WM_1_B_6,
661 PLANE_WM_1_B_7,
662 PLANE_BUF_CFG_1_B,
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]663 PLANE_CTL_2_B,
664 PLANE_STRIDE_2_B,
665 PLANE_POS_2_B,
666 PLANE_SIZE_2_B,
Nico Huberf7a644b2020-10-20 15:26:01 +0200[diff] [blame]667 PLANE_KEYVAL_2_B,
668 PLANE_KEYMSK_2_B,
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]669 PLANE_SURF_2_B,
670 PLANE_OFFSET_2_B,
671 PLANE_COLOR_CTL_2_B,
672 PLANE_WM_2_B_0,
673 PLANE_WM_2_B_1,
674 PLANE_WM_2_B_2,
675 PLANE_WM_2_B_3,
676 PLANE_WM_2_B_4,
677 PLANE_WM_2_B_5,
678 PLANE_WM_2_B_6,
679 PLANE_WM_2_B_7,
680 PLANE_BUF_CFG_2_B,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]681 GMCH_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]682 PIPE_SCANLINE_C,
683 PIPECCONF,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]684 PIPEC_ARB_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]685 PIPECMISC,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]686 PIPEC_CHICKEN,
687 PIPE_MBUS_DBOX_CTL_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]688 PIPE_FRMCNT_C,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]689 CUR_CTL_C,
690 CUR_BASE_C,
691 CUR_POS_C,
692 CUR_FBC_CTL_C,
693 CUR_WM_C_0,
694 CUR_WM_C_1,
695 CUR_WM_C_2,
696 CUR_WM_C_3,
697 CUR_WM_C_4,
698 CUR_WM_C_5,
699 CUR_WM_C_6,
700 CUR_WM_C_7,
701 CUR_BUF_CFG_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]702 DSPCCNTR,
703 DSPCLINOFF,
704 DSPCSTRIDE,
705 PLANE_POS_1_C,
706 PLANE_SIZE_1_C,
Nico Huberf7a644b2020-10-20 15:26:01 +0200[diff] [blame]707 PLANE_KEYVAL_1_C,
708 PLANE_KEYMSK_1_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]709 DSPCSURF,
710 DSPCTILEOFF,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]711 PLANE_AUX_DIST_1_C,
712 PLANE_COLOR_CTL_1_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]713 PLANE_WM_1_C_0,
714 PLANE_WM_1_C_1,
715 PLANE_WM_1_C_2,
716 PLANE_WM_1_C_3,
717 PLANE_WM_1_C_4,
718 PLANE_WM_1_C_5,
719 PLANE_WM_1_C_6,
720 PLANE_WM_1_C_7,
721 PLANE_BUF_CFG_1_C,
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]722 PLANE_CTL_2_C,
723 PLANE_STRIDE_2_C,
724 PLANE_POS_2_C,
725 PLANE_SIZE_2_C,
Nico Huberf7a644b2020-10-20 15:26:01 +0200[diff] [blame]726 PLANE_KEYVAL_2_C,
727 PLANE_KEYMSK_2_C,
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]728 PLANE_SURF_2_C,
729 PLANE_OFFSET_2_C,
730 PLANE_COLOR_CTL_2_C,
731 PLANE_WM_2_C_0,
732 PLANE_WM_2_C_1,
733 PLANE_WM_2_C_2,
734 PLANE_WM_2_C_3,
735 PLANE_WM_2_C_4,
736 PLANE_WM_2_C_5,
737 PLANE_WM_2_C_6,
738 PLANE_WM_2_C_7,
739 PLANE_BUF_CFG_2_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]740 PIPE_EDP_CONF,
741 PCH_FDI_CHICKEN_B_C,
742 QUIRK_C2004,
743 SFUSE_STRAP,
744 PCH_DSPCLK_GATE_D,
745 SDEISR,
746 SDEIMR,
747 SDEIIR,
748 SDEIER,
749 SHOTPLUG_CTL,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]750 SHOTPLUG_CTL_TC,
751 SHPD_FILTER_CNT,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]752 PCH_GMBUS0,
753 PCH_GMBUS1,
754 PCH_GMBUS2,
755 PCH_GMBUS3,
756 PCH_GMBUS4,
757 PCH_GMBUS5,
758 SBI_ADDR,
759 SBI_DATA,
760 SBI_CTL_STAT,
761 PCH_DPLL_A,
762 PCH_DPLL_B,
763 PCH_PIXCLK_GATE,
764 PCH_FPA0,
765 PCH_FPA1,
766 PCH_FPB0,
767 PCH_FPB1,
768 PCH_DREF_CONTROL,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]769 PCH_RAWCLK_FREQ,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]770 PCH_DPLL_SEL,
771 PCH_PP_STATUS,
772 PCH_PP_CONTROL,
773 PCH_PP_ON_DELAYS,
774 PCH_PP_OFF_DELAYS,
775 PCH_PP_DIVISOR,
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]776 BXT_PP_STATUS_2,
777 BXT_PP_CONTROL_2,
778 BXT_PP_ON_DELAYS_2,
779 BXT_PP_OFF_DELAYS_2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]780 BLC_PWM_PCH_CTL1,
781 BLC_PWM_PCH_CTL2,
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]782 BXT_BLC_PWM_DUTY_1,
783 BXT_BLC_PWM_CTL_2,
784 BXT_BLC_PWM_FREQ_2,
785 BXT_BLC_PWM_DUTY_2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]786 TRANS_HTOTAL_A,
787 TRANS_HBLANK_A,
788 TRANS_HSYNC_A,
789 TRANS_VTOTAL_A,
790 TRANS_VBLANK_A,
791 TRANS_VSYNC_A,
792 TRANS_VSYNCSHIFT_A,
793 TRANSA_DATA_M1,
794 TRANSA_DATA_N1,
795 TRANSA_DP_LINK_M1,
796 TRANSA_DP_LINK_N1,
797 TRANS_DP_CTL_A,
798 TRANS_HTOTAL_B,
799 TRANS_HBLANK_B,
800 TRANS_HSYNC_B,
801 TRANS_VTOTAL_B,
802 TRANS_VBLANK_B,
803 TRANS_VSYNC_B,
804 TRANS_VSYNCSHIFT_B,
805 TRANSB_DATA_M1,
806 TRANSB_DATA_N1,
807 TRANSB_DP_LINK_M1,
808 TRANSB_DP_LINK_N1,
809 PCH_ADPA,
810 PCH_HDMIB,
811 PCH_HDMIC,
812 PCH_HDMID,
813 PCH_LVDS,
814 TRANS_DP_CTL_B,
815 TRANS_HTOTAL_C,
816 TRANS_HBLANK_C,
817 TRANS_HSYNC_C,
818 TRANS_VTOTAL_C,
819 TRANS_VBLANK_C,
820 TRANS_VSYNC_C,
821 TRANS_VSYNCSHIFT_C,
822 TRANSC_DATA_M1,
823 TRANSC_DATA_N1,
824 TRANSC_DP_LINK_M1,
825 TRANSC_DP_LINK_N1,
826 TRANS_DP_CTL_C,
827 PCH_DP_B,
828 PCH_DP_AUX_CTL_B,
829 PCH_DP_AUX_DATA_B_1,
830 PCH_DP_AUX_DATA_B_2,
831 PCH_DP_AUX_DATA_B_3,
832 PCH_DP_AUX_DATA_B_4,
833 PCH_DP_AUX_DATA_B_5,
834 PCH_DP_C,
835 PCH_DP_AUX_CTL_C,
836 PCH_DP_AUX_DATA_C_1,
837 PCH_DP_AUX_DATA_C_2,
838 PCH_DP_AUX_DATA_C_3,
839 PCH_DP_AUX_DATA_C_4,
840 PCH_DP_AUX_DATA_C_5,
841 PCH_DP_D,
842 PCH_DP_AUX_CTL_D,
843 PCH_DP_AUX_DATA_D_1,
844 PCH_DP_AUX_DATA_D_2,
845 PCH_DP_AUX_DATA_D_3,
846 PCH_DP_AUX_DATA_D_4,
847 PCH_DP_AUX_DATA_D_5,
848 AUD_CONFIG_A,
849 PCH_AUD_VID_DID,
850 AUD_HDMIW_HDMIEDID_A,
851 AUD_CNTL_ST_A,
852 AUD_CNTRL_ST2,
853 AUD_CONFIG_B,
854 AUD_HDMIW_HDMIEDID_B,
855 AUD_CNTL_ST_B,
856 AUD_CONFIG_C,
857 AUD_HDMIW_HDMIEDID_C,
858 AUD_CNTL_ST_C,
859 TRANSACONF,
860 FDI_RXA_CTL,
861 FDI_RX_MISC_A,
862 FDI_RXA_IIR,
863 FDI_RXA_IMR,
864 FDI_RXA_TUSIZE1,
865 QUIRK_F0060,
866 TRANSA_CHICKEN2,
867 TRANSBCONF,
868 FDI_RXB_CTL,
869 FDI_RX_MISC_B,
870 FDI_RXB_IIR,
871 FDI_RXB_IMR,
872 FDI_RXB_TUSIZE1,
873 QUIRK_F1060,
874 TRANSB_CHICKEN2,
875 TRANSCCONF,
876 FDI_RXC_CTL,
877 FDI_RX_MISC_C,
878 FDI_RXC_IIR,
879 FDI_RXC_IMR,
880 FDI_RXC_TUSIZE1,
881 QUIRK_F2060,
882 TRANSC_CHICKEN2,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]883 HIP_INDEX_REG0,
884 HIP_INDEX_REG1,
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]885 LCPLL_CTL,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]886 BXT_P_CR_GT_DISP_PWRON,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]887 GT_MAILBOX,
888 GT_MAILBOX_DATA,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]889 GT_MAILBOX_DATA_1,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]890 PORT_CL_DW5_C,
891 PORT_CL_DW10_C,
892 PORT_COMP_DW0_C,
893 PORT_COMP_DW1_C,
894 PORT_COMP_DW3_C,
895 PORT_COMP_DW8_C,
896 PORT_COMP_DW9_C,
897 PORT_COMP_DW10_C,
898 PORT_PCS_DW1_GRP_C,
899 PORT_TX_DW2_GRP_C,
900 PORT_TX_DW4_GRP_C,
901 PORT_TX_DW5_GRP_C,
902 PORT_TX_DW7_GRP_C,
903 PORT_TX_DW8_GRP_C,
904 PORT_PCS_DW1_LN0_C,
905 PORT_TX_DW2_LN0_C,
906 PORT_TX_DW4_LN0_C,
907 PORT_TX_DW5_LN0_C,
908 PORT_TX_DW7_LN0_C,
909 PORT_TX_DW8_LN0_C,
910 PORT_TX_DW4_LN1_C,
911 PORT_TX_DW4_LN2_C,
912 PORT_TX_DW4_LN3_C,
913 TCSS_DDI_STATUS_1,
914 TCSS_DDI_STATUS_2,
915 TCSS_DDI_STATUS_3,
916 TCSS_DDI_STATUS_4,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]917 BXT_PORT_CL1CM_DW0_A,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]918 PORT_CL_DW5_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]919 BXT_PORT_CL1CM_DW9_A,
920 BXT_PORT_CL1CM_DW10_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]921 BXT_PORT_PLL_EBB_0_A,
922 BXT_PORT_PLL_EBB_4_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]923 BXT_PORT_CL1CM_DW28_A,
924 BXT_PORT_CL1CM_DW30_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]925 BXT_PORT_PLL_0_A,
926 BXT_PORT_PLL_1_A,
927 BXT_PORT_PLL_2_A,
928 BXT_PORT_PLL_3_A,
929 BXT_PORT_PLL_6_A,
930 BXT_PORT_PLL_8_A,
931 BXT_PORT_PLL_9_A,
932 BXT_PORT_PLL_10_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]933 BXT_PORT_REF_DW3_A,
934 BXT_PORT_REF_DW6_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]935 BXT_PORT_REF_DW8_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]936 BXT_PORT_PCS_DW10_01_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]937 BXT_PORT_PCS_DW12_01_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]938 BXT_PORT_TX_DW2_LN0_A,
939 BXT_PORT_TX_DW3_LN0_A,
940 BXT_PORT_TX_DW4_LN0_A,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]941 BXT_PORT_TX_DW14_LN0_A,
942 BXT_PORT_TX_DW14_LN1_A,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]943 PORT_PCS_DW1_GRP_A,
944 PORT_TX_DW2_GRP_A,
945 PORT_TX_DW4_GRP_A,
946 PORT_TX_DW5_GRP_A,
947 PORT_TX_DW7_GRP_A,
948 PORT_TX_DW8_GRP_A,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]949 BXT_PORT_TX_DW14_LN2_A,
950 BXT_PORT_TX_DW14_LN3_A,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]951 PORT_PCS_DW1_LN0_A,
952 PORT_TX_DW2_LN0_A,
953 PORT_TX_DW4_LN0_A,
954 PORT_TX_DW5_LN0_A,
955 PORT_TX_DW7_LN0_A,
956 PORT_TX_DW8_LN0_A,
957 PORT_TX_DW4_LN1_A,
958 PORT_TX_DW4_LN2_A,
959 PORT_TX_DW4_LN3_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]960 BXT_PORT_PCS_DW10_GRP_A,
961 BXT_PORT_PCS_DW12_GRP_A,
962 BXT_PORT_TX_DW2_GRP_A,
963 BXT_PORT_TX_DW3_GRP_A,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]964 BXT_PORT_TX_DW4_GRP_A,
965 PORT_TX_DFLEXPA1_FIA1,
966 PORT_TX_DFLEXDPPMS_FIA1,
967 PORT_TX_DFLEXDPCSSS_FIA1,
968 PORT_TX_DFLEXDPSP_FIA1,
969 PORT_TX_DFLEXDPMLE1_FIA1,
970 DPCLKA_CFGCR0,
971 DPLL_0_CFGCR0,
972 DPLL_0_CFGCR1,
973 DPLL_1_CFGCR0,
974 DPLL_1_CFGCR1,
975 DPLL_4_CFGCR0,
976 DPLL_4_CFGCR1,
977 DPLL_0_SSC,
978 DPLL_1_SSC,
979 DPLL_4_SSC,
980 DKL_PCS_DW5_1,
981 DKL_DP_MODE_1,
982 DKL_CLKTOP2_HSCC_1,
983 DKL_CLKTOP2_CCC1_1,
984 DKL_REFCLKIN_CTL_1,
985 DKL_PLL_DIV0_1,
986 DKL_PLL_DIV1_1,
987 DKL_PLL_SSC_1,
988 DKL_PLL_BIAS_1,
989 DKL_PLL_COLDST_BIAS_1,
990 DKL_TX_DPCNTL0_1,
991 DKL_TX_DPCNTL1_1,
992 DKL_TX_DPCNTL2_1,
993 DKL_CMN_UC_DW_27_1,
994 DKL_TX_PMD_LANE_SUS_1,
995 DKL_PCS_DW5_2,
996 DKL_DP_MODE_2,
997 DKL_CLKTOP2_HSCC_2,
998 DKL_CLKTOP2_CCC1_2,
999 DKL_REFCLKIN_CTL_2,
1000 DKL_PLL_DIV0_2,
1001 DKL_PLL_DIV1_2,
1002 DKL_PLL_SSC_2,
1003 DKL_PLL_BIAS_2,
1004 DKL_PLL_COLDST_BIAS_2,
1005 DKL_TX_DPCNTL0_2,
1006 DKL_TX_DPCNTL1_2,
1007 DKL_TX_DPCNTL2_2,
1008 DKL_CMN_UC_DW_27_2,
1009 DKL_TX_PMD_LANE_SUS_2,
1010 DKL_PCS_DW5_3,
1011 DKL_DP_MODE_3,
1012 DKL_CLKTOP2_HSCC_3,
1013 DKL_CLKTOP2_CCC1_3,
1014 DKL_REFCLKIN_CTL_3,
1015 DKL_PLL_DIV0_3,
1016 DKL_PLL_DIV1_3,
1017 DKL_PLL_SSC_3,
1018 DKL_PLL_BIAS_3,
1019 DKL_PLL_COLDST_BIAS_3,
1020 DKL_TX_DPCNTL0_3,
1021 DKL_TX_DPCNTL1_3,
1022 DKL_TX_DPCNTL2_3,
1023 DKL_CMN_UC_DW_27_3,
1024 DKL_TX_PMD_LANE_SUS_3,
1025 DKL_PCS_DW5_4,
1026 DKL_DP_MODE_4,
1027 DKL_CLKTOP2_HSCC_4,
1028 DKL_CLKTOP2_CCC1_4,
1029 DKL_REFCLKIN_CTL_4,
1030 DKL_PLL_DIV0_4,
1031 DKL_PLL_DIV1_4,
1032 DKL_PLL_SSC_4,
1033 DKL_PLL_BIAS_4,
1034 DKL_PLL_COLDST_BIAS_4,
1035 DKL_TX_DPCNTL0_4,
1036 DKL_TX_DPCNTL1_4,
1037 DKL_TX_DPCNTL2_4,
1038 DKL_CMN_UC_DW_27_4,
1039 DKL_TX_PMD_LANE_SUS_4,
1040 DKL_DP_MODE_5,
1041 DKL_CLKTOP2_HSCC_5,
1042 DKL_CLKTOP2_CCC1_5,
1043 DKL_REFCLKIN_CTL_5,
1044 DKL_PLL_DIV0_5,
1045 DKL_PLL_DIV1_5,
1046 DKL_PLL_SSC_5,
1047 DKL_PLL_BIAS_5,
1048 DKL_PLL_COLDST_BIAS_5,
1049 DKL_TX_DPCNTL0_5,
1050 DKL_TX_DPCNTL1_5,
1051 DKL_TX_DPCNTL2_5,
1052 DKL_CMN_UC_DW_27_5,
1053 DKL_TX_PMD_LANE_SUS_5,
1054 DKL_DP_MODE_6,
1055 DKL_CLKTOP2_HSCC_6,
1056 DKL_CLKTOP2_CCC1_6,
1057 DKL_REFCLKIN_CTL_6,
1058 DKL_PLL_DIV0_6,
1059 DKL_PLL_DIV1_6,
1060 DKL_PLL_SSC_6,
1061 DKL_PLL_BIAS_6,
1062 DKL_PLL_COLDST_BIAS_6,
1063 DKL_TX_DPCNTL0_6,
1064 DKL_TX_DPCNTL1_6,
1065 DKL_TX_DPCNTL2_6,
1066 DKL_CMN_UC_DW_27_6,
1067 DKL_TX_PMD_LANE_SUS_6,
1068 PORT_TX_DFLEXPA1_FIA2,
1069 PORT_TX_DFLEXDPPMS_FIA2,
1070 PORT_TX_DFLEXDPCSSS_FIA2,
1071 PORT_TX_DFLEXDPSP_FIA2,
1072 PORT_TX_DFLEXDPMLE1_FIA2,
1073 PORT_TX_DFLEXPA1_FIA3,
1074 PORT_TX_DFLEXDPPMS_FIA3,
1075 PORT_TX_DFLEXDPCSSS_FIA3,
1076 PORT_TX_DFLEXDPSP_FIA3,
1077 PORT_TX_DFLEXDPMLE1_FIA3);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1078 pragma Warnings
1079 (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)",
1080 Reason => "TODO: Should it matter?");
1081 pragma Keep_Names (Registers_Invalid_Index);
1082 pragma Warnings
1083 (GNATprove, On, "pragma ""KEEP_NAMES"" ignored *(not yet supported)");
1084
1085 Register_Width : constant := 4;
1086
1087 for Registers_Invalid_Index use
1088 (Invalid_Register => 0,
1089
1090 ---------------------------------------------------------------------------
1091 -- Pipe A registers
1092 ---------------------------------------------------------------------------
1093
1094 -- pipe timing registers
1095
1096 HTOTAL_A => 16#06_0000# / Register_Width,
1097 HBLANK_A => 16#06_0004# / Register_Width,
1098 HSYNC_A => 16#06_0008# / Register_Width,
1099 VTOTAL_A => 16#06_000c# / Register_Width,
1100 VBLANK_A => 16#06_0010# / Register_Width,
1101 VSYNC_A => 16#06_0014# / Register_Width,
1102 PIPEASRC => 16#06_001c# / Register_Width,
1103 PIPEACONF => 16#07_0008# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1104 PIPEA_ARB_CTL => 16#07_0028# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1105 PIPEAMISC => 16#07_0030# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1106 PIPEA_CHICKEN => 16#07_0038# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1107 TRANS_HTOTAL_A => 16#0e_0000# / Register_Width,
1108 TRANS_HBLANK_A => 16#0e_0004# / Register_Width,
1109 TRANS_HSYNC_A => 16#0e_0008# / Register_Width,
1110 TRANS_VTOTAL_A => 16#0e_000c# / Register_Width,
1111 TRANS_VBLANK_A => 16#0e_0010# / Register_Width,
1112 TRANS_VSYNC_A => 16#0e_0014# / Register_Width,
1113 TRANSA_DATA_M1 => 16#0e_0030# / Register_Width,
1114 TRANSA_DATA_N1 => 16#0e_0034# / Register_Width,
1115 TRANSA_DP_LINK_M1 => 16#0e_0040# / Register_Width,
1116 TRANSA_DP_LINK_N1 => 16#0e_0044# / Register_Width,
1117 PIPEA_DATA_M1 => 16#06_0030# / Register_Width,
1118 PIPEA_DATA_N1 => 16#06_0034# / Register_Width,
1119 PIPEA_LINK_M1 => 16#06_0040# / Register_Width,
1120 PIPEA_LINK_N1 => 16#06_0044# / Register_Width,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]1121 PIPEA_GMCH_DATA_M => 16#07_0050# / Register_Width,
1122 PIPEA_GMCH_DATA_N => 16#07_0054# / Register_Width,
1123 PIPEA_GMCH_LINK_M => 16#07_0060# / Register_Width,
1124 PIPEA_GMCH_LINK_N => 16#07_0064# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1125 PIPEA_DDI_FUNC_CTL => 16#06_0400# / Register_Width,
1126 PIPEA_MSA_MISC => 16#06_0410# / Register_Width,
1127
1128 -- PCH sideband interface registers
1129 SBI_ADDR => 16#0c_6000# / Register_Width,
1130 SBI_DATA => 16#0c_6004# / Register_Width,
1131 SBI_CTL_STAT => 16#0c_6008# / Register_Width,
1132
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1133 -- GMCH clock registers
1134 GMCH_DPLL_A => 16#00_6014# / Register_Width,
1135 GMCH_FPA0 => 16#00_6040# / Register_Width,
1136 GMCH_FPA1 => 16#00_6044# / Register_Width,
1137
1138 -- PCH clock registers
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1139 PCH_DPLL_A => 16#0c_6014# / Register_Width,
1140 PCH_PIXCLK_GATE => 16#0c_6020# / Register_Width,
1141 PCH_FPA0 => 16#0c_6040# / Register_Width,
1142 PCH_FPA1 => 16#0c_6044# / Register_Width,
1143
1144 -- panel fitter
1145 PFA_CTL_1 => 16#06_8080# / Register_Width,
1146 PFA_WIN_POS => 16#06_8070# / Register_Width,
1147 PFA_WIN_SZ => 16#06_8074# / Register_Width,
1148 PS_WIN_POS_1_A => 16#06_8170# / Register_Width,
1149 PS_WIN_SZ_1_A => 16#06_8174# / Register_Width,
1150 PS_CTRL_1_A => 16#06_8180# / Register_Width,
1151 PS_WIN_POS_2_A => 16#06_8270# / Register_Width,
1152 PS_WIN_SZ_2_A => 16#06_8274# / Register_Width,
1153 PS_CTRL_2_A => 16#06_8280# / Register_Width,
1154
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1155 -- cursor control
1156 CUR_CTL_A => 16#07_0080# / Register_Width,
1157 CUR_BASE_A => 16#07_0084# / Register_Width,
1158 CUR_POS_A => 16#07_0088# / Register_Width,
1159 CUR_FBC_CTL_A => 16#07_00a0# / Register_Width,
1160
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1161 -- display control
1162 DSPACNTR => 16#07_0180# / Register_Width,
1163 DSPALINOFF => 16#07_0184# / Register_Width,
1164 DSPASTRIDE => 16#07_0188# / Register_Width,
1165 PLANE_POS_1_A => 16#07_018c# / Register_Width,
1166 PLANE_SIZE_1_A => 16#07_0190# / Register_Width,
Nico Huberf7a644b2020-10-20 15:26:01 +0200[diff] [blame]1167 PLANE_KEYVAL_1_A => 16#07_0194# / Register_Width,
1168 PLANE_KEYMSK_1_A => 16#07_0198# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1169 DSPASURF => 16#07_019c# / Register_Width,
1170 DSPATILEOFF => 16#07_01a4# / Register_Width,
1171
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]1172 -- sprite / second plane control
1173 PLANE_CTL_2_A => 16#07_0280# / Register_Width,
1174 PLANE_STRIDE_2_A => 16#07_0288# / Register_Width,
1175 PLANE_POS_2_A => 16#07_028c# / Register_Width,
1176 PLANE_SIZE_2_A => 16#07_0290# / Register_Width,
Nico Huberf7a644b2020-10-20 15:26:01 +0200[diff] [blame]1177 PLANE_KEYVAL_2_A => 16#07_0294# / Register_Width,
1178 PLANE_KEYMSK_2_A => 16#07_0298# / Register_Width,
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]1179 PLANE_SURF_2_A => 16#07_029c# / Register_Width,
1180 PLANE_OFFSET_2_A => 16#07_02a4# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1181
1182 -- FDI and PCH transcoder control
1183 FDI_TX_CTL_A => 16#06_0100# / Register_Width,
1184 FDI_RXA_CTL => 16#0f_000c# / Register_Width,
1185 FDI_RX_MISC_A => 16#0f_0010# / Register_Width,
1186 FDI_RXA_IIR => 16#0f_0014# / Register_Width,
1187 FDI_RXA_IMR => 16#0f_0018# / Register_Width,
1188 FDI_RXA_TUSIZE1 => 16#0f_0030# / Register_Width,
1189 TRANSACONF => 16#0f_0008# / Register_Width,
1190 TRANSA_CHICKEN2 => 16#0f_0064# / Register_Width,
1191
1192 -- watermark registers
1193 WM_LINETIME_A => 16#04_5270# / Register_Width,
1194 PLANE_WM_1_A_0 => 16#07_0240# / Register_Width,
1195 PLANE_WM_1_A_1 => 16#07_0244# / Register_Width,
1196 PLANE_WM_1_A_2 => 16#07_0248# / Register_Width,
1197 PLANE_WM_1_A_3 => 16#07_024c# / Register_Width,
1198 PLANE_WM_1_A_4 => 16#07_0250# / Register_Width,
1199 PLANE_WM_1_A_5 => 16#07_0254# / Register_Width,
1200 PLANE_WM_1_A_6 => 16#07_0258# / Register_Width,
1201 PLANE_WM_1_A_7 => 16#07_025c# / Register_Width,
1202 PLANE_BUF_CFG_1_A => 16#07_027c# / Register_Width,
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]1203 PLANE_WM_2_A_0 => 16#07_0340# / Register_Width,
1204 PLANE_WM_2_A_1 => 16#07_0344# / Register_Width,
1205 PLANE_WM_2_A_2 => 16#07_0348# / Register_Width,
1206 PLANE_WM_2_A_3 => 16#07_034c# / Register_Width,
1207 PLANE_WM_2_A_4 => 16#07_0350# / Register_Width,
1208 PLANE_WM_2_A_5 => 16#07_0354# / Register_Width,
1209 PLANE_WM_2_A_6 => 16#07_0358# / Register_Width,
1210 PLANE_WM_2_A_7 => 16#07_035c# / Register_Width,
1211 PLANE_BUF_CFG_2_A => 16#07_037c# / Register_Width,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1212 CUR_WM_A_0 => 16#07_0140# / Register_Width,
1213 CUR_WM_A_1 => 16#07_0144# / Register_Width,
1214 CUR_WM_A_2 => 16#07_0148# / Register_Width,
1215 CUR_WM_A_3 => 16#07_014c# / Register_Width,
1216 CUR_WM_A_4 => 16#07_0150# / Register_Width,
1217 CUR_WM_A_5 => 16#07_0154# / Register_Width,
1218 CUR_WM_A_6 => 16#07_0158# / Register_Width,
1219 CUR_WM_A_7 => 16#07_015c# / Register_Width,
1220 CUR_BUF_CFG_A => 16#07_017c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1221
1222 -- CPU transcoder clock select
1223 TRANSA_CLK_SEL => 16#04_6140# / Register_Width,
1224
1225 ---------------------------------------------------------------------------
1226 -- Pipe B registers
1227 ---------------------------------------------------------------------------
1228
1229 -- pipe timing registers
1230
1231 HTOTAL_B => 16#06_1000# / Register_Width,
1232 HBLANK_B => 16#06_1004# / Register_Width,
1233 HSYNC_B => 16#06_1008# / Register_Width,
1234 VTOTAL_B => 16#06_100c# / Register_Width,
1235 VBLANK_B => 16#06_1010# / Register_Width,
1236 VSYNC_B => 16#06_1014# / Register_Width,
1237 PIPEBSRC => 16#06_101c# / Register_Width,
1238 PIPEBCONF => 16#07_1008# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1239 PIPEB_ARB_CTL => 16#07_1028# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1240 PIPEBMISC => 16#07_1030# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1241 PIPEB_CHICKEN => 16#07_1038# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1242 TRANS_HTOTAL_B => 16#0e_1000# / Register_Width,
1243 TRANS_HBLANK_B => 16#0e_1004# / Register_Width,
1244 TRANS_HSYNC_B => 16#0e_1008# / Register_Width,
1245 TRANS_VTOTAL_B => 16#0e_100c# / Register_Width,
1246 TRANS_VBLANK_B => 16#0e_1010# / Register_Width,
1247 TRANS_VSYNC_B => 16#0e_1014# / Register_Width,
1248 TRANSB_DATA_M1 => 16#0e_1030# / Register_Width,
1249 TRANSB_DATA_N1 => 16#0e_1034# / Register_Width,
1250 TRANSB_DP_LINK_M1 => 16#0e_1040# / Register_Width,
1251 TRANSB_DP_LINK_N1 => 16#0e_1044# / Register_Width,
1252 PIPEB_DATA_M1 => 16#06_1030# / Register_Width,
1253 PIPEB_DATA_N1 => 16#06_1034# / Register_Width,
1254 PIPEB_LINK_M1 => 16#06_1040# / Register_Width,
1255 PIPEB_LINK_N1 => 16#06_1044# / Register_Width,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]1256 PIPEB_GMCH_DATA_M => 16#07_1050# / Register_Width,
1257 PIPEB_GMCH_DATA_N => 16#07_1054# / Register_Width,
1258 PIPEB_GMCH_LINK_M => 16#07_1060# / Register_Width,
1259 PIPEB_GMCH_LINK_N => 16#07_1064# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1260 PIPEB_DDI_FUNC_CTL => 16#06_1400# / Register_Width,
1261 PIPEB_MSA_MISC => 16#06_1410# / Register_Width,
1262
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1263 -- GMCH clock registers
1264 GMCH_DPLL_B => 16#00_6018# / Register_Width,
1265 GMCH_FPB0 => 16#00_6048# / Register_Width,
1266 GMCH_FPB1 => 16#00_604c# / Register_Width,
1267
1268 -- PCH clock registers
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1269 PCH_DPLL_B => 16#0c_6018# / Register_Width,
1270 PCH_FPB0 => 16#0c_6048# / Register_Width,
1271 PCH_FPB1 => 16#0c_604c# / Register_Width,
1272
1273 -- panel fitter
1274 PFB_CTL_1 => 16#06_8880# / Register_Width,
1275 PFB_WIN_POS => 16#06_8870# / Register_Width,
1276 PFB_WIN_SZ => 16#06_8874# / Register_Width,
1277 PS_WIN_POS_1_B => 16#06_8970# / Register_Width,
1278 PS_WIN_SZ_1_B => 16#06_8974# / Register_Width,
1279 PS_CTRL_1_B => 16#06_8980# / Register_Width,
1280 PS_WIN_POS_2_B => 16#06_8a70# / Register_Width,
1281 PS_WIN_SZ_2_B => 16#06_8a74# / Register_Width,
1282 PS_CTRL_2_B => 16#06_8a80# / Register_Width,
1283
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1284 -- cursor control
Nico Huber75a707f2018-06-18 16:28:33 +0200[diff] [blame]1285 CURBCNTR => 16#07_00c0# / Register_Width, -- <= SNB
1286 CURBBASE => 16#07_00c4# / Register_Width, -- <= SNB
1287 CURBPOS => 16#07_00c8# / Register_Width, -- <= SNB
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1288 CUR_CTL_B => 16#07_1080# / Register_Width,
1289 CUR_BASE_B => 16#07_1084# / Register_Width,
1290 CUR_POS_B => 16#07_1088# / Register_Width,
1291 CUR_FBC_CTL_B => 16#07_10a0# / Register_Width,
1292
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1293 -- display control
1294 DSPBCNTR => 16#07_1180# / Register_Width,
1295 DSPBLINOFF => 16#07_1184# / Register_Width,
1296 DSPBSTRIDE => 16#07_1188# / Register_Width,
1297 PLANE_POS_1_B => 16#07_118c# / Register_Width,
1298 PLANE_SIZE_1_B => 16#07_1190# / Register_Width,
Nico Huberf7a644b2020-10-20 15:26:01 +0200[diff] [blame]1299 PLANE_KEYVAL_1_B => 16#07_1194# / Register_Width,
1300 PLANE_KEYMSK_1_B => 16#07_1198# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1301 DSPBSURF => 16#07_119c# / Register_Width,
1302 DSPBTILEOFF => 16#07_11a4# / Register_Width,
1303
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]1304 -- sprite / second plane control
1305 PLANE_CTL_2_B => 16#07_1280# / Register_Width,
1306 PLANE_STRIDE_2_B => 16#07_1288# / Register_Width,
1307 PLANE_POS_2_B => 16#07_128c# / Register_Width,
1308 PLANE_SIZE_2_B => 16#07_1290# / Register_Width,
1309 PLANE_SURF_2_B => 16#07_129c# / Register_Width,
Nico Huberf7a644b2020-10-20 15:26:01 +0200[diff] [blame]1310 PLANE_KEYVAL_2_B => 16#07_1294# / Register_Width,
1311 PLANE_KEYMSK_2_B => 16#07_1298# / Register_Width,
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]1312 PLANE_OFFSET_2_B => 16#07_12a4# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1313
1314 -- FDI and PCH transcoder control
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1315 FDI_TX_CTL_B => 16#06_1100# / Register_Width, -- aliased by GMCH_ADPA
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1316 FDI_RXB_CTL => 16#0f_100c# / Register_Width,
1317 FDI_RX_MISC_B => 16#0f_1010# / Register_Width,
1318 FDI_RXB_IIR => 16#0f_1014# / Register_Width,
1319 FDI_RXB_IMR => 16#0f_1018# / Register_Width,
1320 FDI_RXB_TUSIZE1 => 16#0f_1030# / Register_Width,
1321 TRANSBCONF => 16#0f_1008# / Register_Width,
1322 TRANSB_CHICKEN2 => 16#0f_1064# / Register_Width,
1323
1324 -- watermark registers
1325 WM_LINETIME_B => 16#04_5274# / Register_Width,
1326 PLANE_WM_1_B_0 => 16#07_1240# / Register_Width,
1327 PLANE_WM_1_B_1 => 16#07_1244# / Register_Width,
1328 PLANE_WM_1_B_2 => 16#07_1248# / Register_Width,
1329 PLANE_WM_1_B_3 => 16#07_124c# / Register_Width,
1330 PLANE_WM_1_B_4 => 16#07_1250# / Register_Width,
1331 PLANE_WM_1_B_5 => 16#07_1254# / Register_Width,
1332 PLANE_WM_1_B_6 => 16#07_1258# / Register_Width,
1333 PLANE_WM_1_B_7 => 16#07_125c# / Register_Width,
1334 PLANE_BUF_CFG_1_B => 16#07_127c# / Register_Width,
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]1335 PLANE_WM_2_B_0 => 16#07_1340# / Register_Width,
1336 PLANE_WM_2_B_1 => 16#07_1344# / Register_Width,
1337 PLANE_WM_2_B_2 => 16#07_1348# / Register_Width,
1338 PLANE_WM_2_B_3 => 16#07_134c# / Register_Width,
1339 PLANE_WM_2_B_4 => 16#07_1350# / Register_Width,
1340 PLANE_WM_2_B_5 => 16#07_1354# / Register_Width,
1341 PLANE_WM_2_B_6 => 16#07_1358# / Register_Width,
1342 PLANE_WM_2_B_7 => 16#07_135c# / Register_Width,
1343 PLANE_BUF_CFG_2_B => 16#07_137c# / Register_Width,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1344 CUR_WM_B_0 => 16#07_1140# / Register_Width,
1345 CUR_WM_B_1 => 16#07_1144# / Register_Width,
1346 CUR_WM_B_2 => 16#07_1148# / Register_Width,
1347 CUR_WM_B_3 => 16#07_114c# / Register_Width,
1348 CUR_WM_B_4 => 16#07_1150# / Register_Width,
1349 CUR_WM_B_5 => 16#07_1154# / Register_Width,
1350 CUR_WM_B_6 => 16#07_1158# / Register_Width,
1351 CUR_WM_B_7 => 16#07_115c# / Register_Width,
1352 CUR_BUF_CFG_B => 16#07_117c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1353
1354 -- CPU transcoder clock select
1355 TRANSB_CLK_SEL => 16#04_6144# / Register_Width,
1356
1357 ---------------------------------------------------------------------------
1358 -- Pipe C registers
1359 ---------------------------------------------------------------------------
1360
1361 -- pipe timing registers
1362
1363 HTOTAL_C => 16#06_2000# / Register_Width,
1364 HBLANK_C => 16#06_2004# / Register_Width,
1365 HSYNC_C => 16#06_2008# / Register_Width,
1366 VTOTAL_C => 16#06_200c# / Register_Width,
1367 VBLANK_C => 16#06_2010# / Register_Width,
1368 VSYNC_C => 16#06_2014# / Register_Width,
1369 PIPECSRC => 16#06_201c# / Register_Width,
1370 PIPECCONF => 16#07_2008# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1371 PIPEC_ARB_CTL => 16#07_2028# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1372 PIPECMISC => 16#07_2030# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1373 PIPEC_CHICKEN => 16#07_2038# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1374 TRANS_HTOTAL_C => 16#0e_2000# / Register_Width,
1375 TRANS_HBLANK_C => 16#0e_2004# / Register_Width,
1376 TRANS_HSYNC_C => 16#0e_2008# / Register_Width,
1377 TRANS_VTOTAL_C => 16#0e_200c# / Register_Width,
1378 TRANS_VBLANK_C => 16#0e_2010# / Register_Width,
1379 TRANS_VSYNC_C => 16#0e_2014# / Register_Width,
1380 TRANSC_DATA_M1 => 16#0e_2030# / Register_Width,
1381 TRANSC_DATA_N1 => 16#0e_2034# / Register_Width,
1382 TRANSC_DP_LINK_M1 => 16#0e_2040# / Register_Width,
1383 TRANSC_DP_LINK_N1 => 16#0e_2044# / Register_Width,
1384 PIPEC_DATA_M1 => 16#06_2030# / Register_Width,
1385 PIPEC_DATA_N1 => 16#06_2034# / Register_Width,
1386 PIPEC_LINK_M1 => 16#06_2040# / Register_Width,
1387 PIPEC_LINK_N1 => 16#06_2044# / Register_Width,
1388 PIPEC_DDI_FUNC_CTL => 16#06_2400# / Register_Width,
1389 PIPEC_MSA_MISC => 16#06_2410# / Register_Width,
1390
1391 -- panel fitter
1392 PFC_CTL_1 => 16#06_9080# / Register_Width,
1393 PFC_WIN_POS => 16#06_9070# / Register_Width,
1394 PFC_WIN_SZ => 16#06_9074# / Register_Width,
1395 PS_WIN_POS_1_C => 16#06_9170# / Register_Width,
1396 PS_WIN_SZ_1_C => 16#06_9174# / Register_Width,
1397 PS_CTRL_1_C => 16#06_9180# / Register_Width,
1398
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1399 -- cursor control
1400 CUR_CTL_C => 16#07_2080# / Register_Width,
1401 CUR_BASE_C => 16#07_2084# / Register_Width,
1402 CUR_POS_C => 16#07_2088# / Register_Width,
1403 CUR_FBC_CTL_C => 16#07_20a0# / Register_Width,
1404
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1405 -- display control
1406 DSPCCNTR => 16#07_2180# / Register_Width,
1407 DSPCLINOFF => 16#07_2184# / Register_Width,
1408 DSPCSTRIDE => 16#07_2188# / Register_Width,
1409 PLANE_POS_1_C => 16#07_218c# / Register_Width,
1410 PLANE_SIZE_1_C => 16#07_2190# / Register_Width,
Nico Huberf7a644b2020-10-20 15:26:01 +0200[diff] [blame]1411 PLANE_KEYVAL_1_C => 16#07_2194# / Register_Width,
1412 PLANE_KEYMSK_1_C => 16#07_2198# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1413 DSPCSURF => 16#07_219c# / Register_Width,
1414 DSPCTILEOFF => 16#07_21a4# / Register_Width,
1415
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]1416 -- sprite / second plane control
1417 PLANE_CTL_2_C => 16#07_2280# / Register_Width,
1418 PLANE_STRIDE_2_C => 16#07_2288# / Register_Width,
1419 PLANE_POS_2_C => 16#07_228c# / Register_Width,
1420 PLANE_SIZE_2_C => 16#07_2290# / Register_Width,
Nico Huberf7a644b2020-10-20 15:26:01 +0200[diff] [blame]1421 PLANE_KEYVAL_2_C => 16#07_2294# / Register_Width,
1422 PLANE_KEYMSK_2_C => 16#07_2298# / Register_Width,
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]1423 PLANE_SURF_2_C => 16#07_229c# / Register_Width,
1424 PLANE_OFFSET_2_C => 16#07_22a4# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1425
1426 -- PCH transcoder control
1427 FDI_TX_CTL_C => 16#06_2100# / Register_Width,
1428 FDI_RXC_CTL => 16#0f_200c# / Register_Width,
1429 FDI_RX_MISC_C => 16#0f_2010# / Register_Width,
1430 FDI_RXC_IIR => 16#0f_2014# / Register_Width,
1431 FDI_RXC_IMR => 16#0f_2018# / Register_Width,
1432 FDI_RXC_TUSIZE1 => 16#0f_2030# / Register_Width,
1433 TRANSCCONF => 16#0f_2008# / Register_Width,
1434 TRANSC_CHICKEN2 => 16#0f_2064# / Register_Width,
1435
1436 -- watermark registers
1437 WM_LINETIME_C => 16#04_5278# / Register_Width,
1438 PLANE_WM_1_C_0 => 16#07_2240# / Register_Width,
1439 PLANE_WM_1_C_1 => 16#07_2244# / Register_Width,
1440 PLANE_WM_1_C_2 => 16#07_2248# / Register_Width,
1441 PLANE_WM_1_C_3 => 16#07_224c# / Register_Width,
1442 PLANE_WM_1_C_4 => 16#07_2250# / Register_Width,
1443 PLANE_WM_1_C_5 => 16#07_2254# / Register_Width,
1444 PLANE_WM_1_C_6 => 16#07_2258# / Register_Width,
1445 PLANE_WM_1_C_7 => 16#07_225c# / Register_Width,
1446 PLANE_BUF_CFG_1_C => 16#07_227c# / Register_Width,
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]1447 PLANE_WM_2_C_0 => 16#07_2340# / Register_Width,
1448 PLANE_WM_2_C_1 => 16#07_2344# / Register_Width,
1449 PLANE_WM_2_C_2 => 16#07_2348# / Register_Width,
1450 PLANE_WM_2_C_3 => 16#07_234c# / Register_Width,
1451 PLANE_WM_2_C_4 => 16#07_2350# / Register_Width,
1452 PLANE_WM_2_C_5 => 16#07_2354# / Register_Width,
1453 PLANE_WM_2_C_6 => 16#07_2358# / Register_Width,
1454 PLANE_WM_2_C_7 => 16#07_235c# / Register_Width,
1455 PLANE_BUF_CFG_2_C => 16#07_237c# / Register_Width,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1456 CUR_WM_C_0 => 16#07_2140# / Register_Width,
1457 CUR_WM_C_1 => 16#07_2144# / Register_Width,
1458 CUR_WM_C_2 => 16#07_2148# / Register_Width,
1459 CUR_WM_C_3 => 16#07_214c# / Register_Width,
1460 CUR_WM_C_4 => 16#07_2150# / Register_Width,
1461 CUR_WM_C_5 => 16#07_2154# / Register_Width,
1462 CUR_WM_C_6 => 16#07_2158# / Register_Width,
1463 CUR_WM_C_7 => 16#07_215c# / Register_Width,
1464 CUR_BUF_CFG_C => 16#07_217c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1465
1466 -- CPU transcoder clock select
1467 TRANSC_CLK_SEL => 16#04_6148# / Register_Width,
1468
1469 ---------------------------------------------------------------------------
1470 -- Pipe EDP registers
1471 ---------------------------------------------------------------------------
1472
1473 -- pipe timing registers
1474
1475 HTOTAL_EDP => 16#06_f000# / Register_Width,
1476 HBLANK_EDP => 16#06_f004# / Register_Width,
1477 HSYNC_EDP => 16#06_f008# / Register_Width,
1478 VTOTAL_EDP => 16#06_f00c# / Register_Width,
1479 VBLANK_EDP => 16#06_f010# / Register_Width,
1480 VSYNC_EDP => 16#06_f014# / Register_Width,
1481 PIPE_EDP_CONF => 16#07_f008# / Register_Width,
1482 PIPE_EDP_DATA_M1 => 16#06_f030# / Register_Width,
1483 PIPE_EDP_DATA_N1 => 16#06_f034# / Register_Width,
1484 PIPE_EDP_LINK_M1 => 16#06_f040# / Register_Width,
1485 PIPE_EDP_LINK_N1 => 16#06_f044# / Register_Width,
1486 PIPE_EDP_DDI_FUNC_CTL => 16#06_f400# / Register_Width,
1487 PIPE_EDP_MSA_MISC => 16#06_f410# / Register_Width,
1488
1489 -- PSR registers
1490 SRD_CTL => 16#06_4800# / Register_Width,
1491 SRD_CTL_A => 16#06_0800# / Register_Width,
1492 SRD_CTL_B => 16#06_1800# / Register_Width,
1493 SRD_CTL_C => 16#06_2800# / Register_Width,
1494 SRD_CTL_EDP => 16#06_f800# / Register_Width,
1495 SRD_STATUS => 16#06_4840# / Register_Width,
1496 SRD_STATUS_A => 16#06_0840# / Register_Width,
1497 SRD_STATUS_B => 16#06_1840# / Register_Width,
1498 SRD_STATUS_C => 16#06_2840# / Register_Width,
1499 SRD_STATUS_EDP => 16#06_f840# / Register_Width,
1500
1501 -- DDI registers
1502 DDI_BUF_CTL_A => 16#06_4000# / Register_Width, -- aliased by DP_CTL_A
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1503 DDI_BUF_TRANS_A_S0T1 => 16#06_4e00# / Register_Width,
1504 DDI_BUF_TRANS_A_S0T2 => 16#06_4e04# / Register_Width,
1505 DDI_BUF_TRANS_A_S1T1 => 16#06_4e08# / Register_Width,
1506 DDI_BUF_TRANS_A_S1T2 => 16#06_4e0c# / Register_Width,
1507 DDI_BUF_TRANS_A_S2T1 => 16#06_4e10# / Register_Width,
1508 DDI_BUF_TRANS_A_S2T2 => 16#06_4e14# / Register_Width,
1509 DDI_BUF_TRANS_A_S3T1 => 16#06_4e18# / Register_Width,
1510 DDI_BUF_TRANS_A_S3T2 => 16#06_4e1c# / Register_Width,
1511 DDI_BUF_TRANS_A_S4T1 => 16#06_4e20# / Register_Width,
1512 DDI_BUF_TRANS_A_S4T2 => 16#06_4e24# / Register_Width,
1513 DDI_BUF_TRANS_A_S5T1 => 16#06_4e28# / Register_Width,
1514 DDI_BUF_TRANS_A_S5T2 => 16#06_4e2c# / Register_Width,
1515 DDI_BUF_TRANS_A_S6T1 => 16#06_4e30# / Register_Width,
1516 DDI_BUF_TRANS_A_S6T2 => 16#06_4e34# / Register_Width,
1517 DDI_BUF_TRANS_A_S7T1 => 16#06_4e38# / Register_Width,
1518 DDI_BUF_TRANS_A_S7T2 => 16#06_4e3c# / Register_Width,
1519 DDI_BUF_TRANS_A_S8T1 => 16#06_4e40# / Register_Width,
1520 DDI_BUF_TRANS_A_S8T2 => 16#06_4e44# / Register_Width,
1521 DDI_BUF_TRANS_A_S9T1 => 16#06_4e48# / Register_Width,
1522 DDI_BUF_TRANS_A_S9T2 => 16#06_4e4c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1523 DDI_AUX_CTL_A => 16#06_4010# / Register_Width, -- aliased by DP_AUX_CTL_A
1524 DDI_AUX_DATA_A_1 => 16#06_4014# / Register_Width, -- aliased by DP_AUX_DATA_A_1
1525 DDI_AUX_DATA_A_2 => 16#06_4018# / Register_Width, -- aliased by DP_AUX_DATA_A_2
1526 DDI_AUX_DATA_A_3 => 16#06_401c# / Register_Width, -- aliased by DP_AUX_DATA_A_3
1527 DDI_AUX_DATA_A_4 => 16#06_4020# / Register_Width, -- aliased by DP_AUX_DATA_A_4
1528 DDI_AUX_DATA_A_5 => 16#06_4024# / Register_Width, -- aliased by DP_AUX_DATA_A_5
1529 DDI_AUX_MUTEX_A => 16#06_402c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1530
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1531 DDI_BUF_CTL_B => 16#06_4100# / Register_Width, -- aliased by GMCH_DP_B
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1532 DDI_BUF_TRANS_B_S0T1 => 16#06_4e60# / Register_Width,
1533 DDI_BUF_TRANS_B_S0T2 => 16#06_4e64# / Register_Width,
1534 DDI_BUF_TRANS_B_S1T1 => 16#06_4e68# / Register_Width,
1535 DDI_BUF_TRANS_B_S1T2 => 16#06_4e6c# / Register_Width,
1536 DDI_BUF_TRANS_B_S2T1 => 16#06_4e70# / Register_Width,
1537 DDI_BUF_TRANS_B_S2T2 => 16#06_4e74# / Register_Width,
1538 DDI_BUF_TRANS_B_S3T1 => 16#06_4e78# / Register_Width,
1539 DDI_BUF_TRANS_B_S3T2 => 16#06_4e7c# / Register_Width,
1540 DDI_BUF_TRANS_B_S4T1 => 16#06_4e80# / Register_Width,
1541 DDI_BUF_TRANS_B_S4T2 => 16#06_4e84# / Register_Width,
1542 DDI_BUF_TRANS_B_S5T1 => 16#06_4e88# / Register_Width,
1543 DDI_BUF_TRANS_B_S5T2 => 16#06_4e8c# / Register_Width,
1544 DDI_BUF_TRANS_B_S6T1 => 16#06_4e90# / Register_Width,
1545 DDI_BUF_TRANS_B_S6T2 => 16#06_4e94# / Register_Width,
1546 DDI_BUF_TRANS_B_S7T1 => 16#06_4e98# / Register_Width,
1547 DDI_BUF_TRANS_B_S7T2 => 16#06_4e9c# / Register_Width,
1548 DDI_BUF_TRANS_B_S8T1 => 16#06_4ea0# / Register_Width,
1549 DDI_BUF_TRANS_B_S8T2 => 16#06_4ea4# / Register_Width,
1550 DDI_BUF_TRANS_B_S9T1 => 16#06_4ea8# / Register_Width,
1551 DDI_BUF_TRANS_B_S9T2 => 16#06_4eac# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1552 DDI_AUX_CTL_B => 16#06_4110# / Register_Width,
1553 DDI_AUX_DATA_B_1 => 16#06_4114# / Register_Width,
1554 DDI_AUX_DATA_B_2 => 16#06_4118# / Register_Width,
1555 DDI_AUX_DATA_B_3 => 16#06_411c# / Register_Width,
1556 DDI_AUX_DATA_B_4 => 16#06_4120# / Register_Width,
1557 DDI_AUX_DATA_B_5 => 16#06_4124# / Register_Width,
1558 DDI_AUX_MUTEX_B => 16#06_412c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1559
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1560 DDI_BUF_CTL_C => 16#06_4200# / Register_Width, -- aliased by GMCH_DP_C
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1561 DDI_BUF_TRANS_C_S0T1 => 16#06_4ec0# / Register_Width,
1562 DDI_BUF_TRANS_C_S0T2 => 16#06_4ec4# / Register_Width,
1563 DDI_BUF_TRANS_C_S1T1 => 16#06_4ec8# / Register_Width,
1564 DDI_BUF_TRANS_C_S1T2 => 16#06_4ecc# / Register_Width,
1565 DDI_BUF_TRANS_C_S2T1 => 16#06_4ed0# / Register_Width,
1566 DDI_BUF_TRANS_C_S2T2 => 16#06_4ed4# / Register_Width,
1567 DDI_BUF_TRANS_C_S3T1 => 16#06_4ed8# / Register_Width,
1568 DDI_BUF_TRANS_C_S3T2 => 16#06_4edc# / Register_Width,
1569 DDI_BUF_TRANS_C_S4T1 => 16#06_4ee0# / Register_Width,
1570 DDI_BUF_TRANS_C_S4T2 => 16#06_4ee4# / Register_Width,
1571 DDI_BUF_TRANS_C_S5T1 => 16#06_4ee8# / Register_Width,
1572 DDI_BUF_TRANS_C_S5T2 => 16#06_4eec# / Register_Width,
1573 DDI_BUF_TRANS_C_S6T1 => 16#06_4ef0# / Register_Width,
1574 DDI_BUF_TRANS_C_S6T2 => 16#06_4ef4# / Register_Width,
1575 DDI_BUF_TRANS_C_S7T1 => 16#06_4ef8# / Register_Width,
1576 DDI_BUF_TRANS_C_S7T2 => 16#06_4efc# / Register_Width,
1577 DDI_BUF_TRANS_C_S8T1 => 16#06_4f00# / Register_Width,
1578 DDI_BUF_TRANS_C_S8T2 => 16#06_4f04# / Register_Width,
1579 DDI_BUF_TRANS_C_S9T1 => 16#06_4f08# / Register_Width,
1580 DDI_BUF_TRANS_C_S9T2 => 16#06_4f0c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1581 DDI_AUX_CTL_C => 16#06_4210# / Register_Width,
1582 DDI_AUX_DATA_C_1 => 16#06_4214# / Register_Width,
1583 DDI_AUX_DATA_C_2 => 16#06_4218# / Register_Width,
1584 DDI_AUX_DATA_C_3 => 16#06_421c# / Register_Width,
1585 DDI_AUX_DATA_C_4 => 16#06_4220# / Register_Width,
1586 DDI_AUX_DATA_C_5 => 16#06_4224# / Register_Width,
1587 DDI_AUX_MUTEX_C => 16#06_422c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1588
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1589 DDI_BUF_CTL_D => 16#06_4300# / Register_Width, -- aliased by GMCH_DP_D
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1590 DDI_BUF_TRANS_D_S0T1 => 16#06_4f20# / Register_Width,
1591 DDI_BUF_TRANS_D_S0T2 => 16#06_4f24# / Register_Width,
1592 DDI_BUF_TRANS_D_S1T1 => 16#06_4f28# / Register_Width,
1593 DDI_BUF_TRANS_D_S1T2 => 16#06_4f2c# / Register_Width,
1594 DDI_BUF_TRANS_D_S2T1 => 16#06_4f30# / Register_Width,
1595 DDI_BUF_TRANS_D_S2T2 => 16#06_4f34# / Register_Width,
1596 DDI_BUF_TRANS_D_S3T1 => 16#06_4f38# / Register_Width,
1597 DDI_BUF_TRANS_D_S3T2 => 16#06_4f3c# / Register_Width,
1598 DDI_BUF_TRANS_D_S4T1 => 16#06_4f40# / Register_Width,
1599 DDI_BUF_TRANS_D_S4T2 => 16#06_4f44# / Register_Width,
1600 DDI_BUF_TRANS_D_S5T1 => 16#06_4f48# / Register_Width,
1601 DDI_BUF_TRANS_D_S5T2 => 16#06_4f4c# / Register_Width,
1602 DDI_BUF_TRANS_D_S6T1 => 16#06_4f50# / Register_Width,
1603 DDI_BUF_TRANS_D_S6T2 => 16#06_4f54# / Register_Width,
1604 DDI_BUF_TRANS_D_S7T1 => 16#06_4f58# / Register_Width,
1605 DDI_BUF_TRANS_D_S7T2 => 16#06_4f5c# / Register_Width,
1606 DDI_BUF_TRANS_D_S8T1 => 16#06_4f60# / Register_Width,
1607 DDI_BUF_TRANS_D_S8T2 => 16#06_4f64# / Register_Width,
1608 DDI_BUF_TRANS_D_S9T1 => 16#06_4f68# / Register_Width,
1609 DDI_BUF_TRANS_D_S9T2 => 16#06_4f6c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1610 DDI_AUX_CTL_D => 16#06_4310# / Register_Width,
1611 DDI_AUX_DATA_D_1 => 16#06_4314# / Register_Width,
1612 DDI_AUX_DATA_D_2 => 16#06_4318# / Register_Width,
1613 DDI_AUX_DATA_D_3 => 16#06_431c# / Register_Width,
1614 DDI_AUX_DATA_D_4 => 16#06_4320# / Register_Width,
1615 DDI_AUX_DATA_D_5 => 16#06_4324# / Register_Width,
1616 DDI_AUX_MUTEX_D => 16#06_432c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1617
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1618 -- USB-C AUX control and data
1619 DDI_AUX_CTL_USBC2 => 16#06_4410# / Register_Width,
1620 DDI_AUX_DATA_USBC2_1 => 16#06_4414# / Register_Width,
1621 DDI_AUX_DATA_USBC2_2 => 16#06_4418# / Register_Width,
1622 DDI_AUX_DATA_USBC2_3 => 16#06_441c# / Register_Width,
1623 DDI_AUX_DATA_USBC2_4 => 16#06_4420# / Register_Width,
1624 DDI_AUX_DATA_USBC2_5 => 16#06_4424# / Register_Width,
1625 DDI_AUX_CTL_USBC3 => 16#06_4510# / Register_Width,
1626 DDI_AUX_DATA_USBC3_1 => 16#06_4514# / Register_Width,
1627 DDI_AUX_DATA_USBC3_2 => 16#06_4518# / Register_Width,
1628 DDI_AUX_DATA_USBC3_3 => 16#06_451c# / Register_Width,
1629 DDI_AUX_DATA_USBC3_4 => 16#06_4520# / Register_Width,
1630 DDI_AUX_DATA_USBC3_5 => 16#06_4524# / Register_Width,
1631 DDI_AUX_CTL_USBC4 => 16#06_4610# / Register_Width,
1632 DDI_AUX_DATA_USBC4_1 => 16#06_4614# / Register_Width,
1633 DDI_AUX_DATA_USBC4_2 => 16#06_4618# / Register_Width,
1634 DDI_AUX_DATA_USBC4_3 => 16#06_461c# / Register_Width,
1635 DDI_AUX_DATA_USBC4_4 => 16#06_4620# / Register_Width,
1636 DDI_AUX_DATA_USBC4_5 => 16#06_4624# / Register_Width,
1637 DDI_AUX_CTL_USBC5 => 16#06_4710# / Register_Width,
1638 DDI_AUX_DATA_USBC5_1 => 16#06_4714# / Register_Width,
1639 DDI_AUX_DATA_USBC5_2 => 16#06_4718# / Register_Width,
1640 DDI_AUX_DATA_USBC5_3 => 16#06_471c# / Register_Width,
1641 DDI_AUX_DATA_USBC5_4 => 16#06_4720# / Register_Width,
1642 DDI_AUX_DATA_USBC5_5 => 16#06_4724# / Register_Width,
1643 DDI_AUX_CTL_USBC6 => 16#06_4810# / Register_Width,
1644 DDI_AUX_DATA_USBC6_1 => 16#06_4814# / Register_Width,
1645 DDI_AUX_DATA_USBC6_2 => 16#06_4818# / Register_Width,
1646 DDI_AUX_DATA_USBC6_3 => 16#06_481c# / Register_Width,
1647 DDI_AUX_DATA_USBC6_4 => 16#06_4820# / Register_Width,
1648 DDI_AUX_DATA_USBC6_5 => 16#06_4824# / Register_Width,
1649
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1650 DDI_BUF_CTL_E => 16#06_4400# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1651 DDI_BUF_TRANS_E_S0T1 => 16#06_4f80# / Register_Width,
1652 DDI_BUF_TRANS_E_S0T2 => 16#06_4f84# / Register_Width,
1653 DDI_BUF_TRANS_E_S1T1 => 16#06_4f88# / Register_Width,
1654 DDI_BUF_TRANS_E_S1T2 => 16#06_4f8c# / Register_Width,
1655 DDI_BUF_TRANS_E_S2T1 => 16#06_4f90# / Register_Width,
1656 DDI_BUF_TRANS_E_S2T2 => 16#06_4f94# / Register_Width,
1657 DDI_BUF_TRANS_E_S3T1 => 16#06_4f98# / Register_Width,
1658 DDI_BUF_TRANS_E_S3T2 => 16#06_4f9c# / Register_Width,
1659 DDI_BUF_TRANS_E_S4T1 => 16#06_4fa0# / Register_Width,
1660 DDI_BUF_TRANS_E_S4T2 => 16#06_4fa4# / Register_Width,
1661 DDI_BUF_TRANS_E_S5T1 => 16#06_4fa8# / Register_Width,
1662 DDI_BUF_TRANS_E_S5T2 => 16#06_4fac# / Register_Width,
1663 DDI_BUF_TRANS_E_S6T1 => 16#06_4fb0# / Register_Width,
1664 DDI_BUF_TRANS_E_S6T2 => 16#06_4fb4# / Register_Width,
1665 DDI_BUF_TRANS_E_S7T1 => 16#06_4fb8# / Register_Width,
1666 DDI_BUF_TRANS_E_S7T2 => 16#06_4fbc# / Register_Width,
1667 DDI_BUF_TRANS_E_S8T1 => 16#06_4fc0# / Register_Width,
1668 DDI_BUF_TRANS_E_S8T2 => 16#06_4fc4# / Register_Width,
1669 DDI_BUF_TRANS_E_S9T1 => 16#06_4fc8# / Register_Width,
1670 DDI_BUF_TRANS_E_S9T2 => 16#06_4fcc# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1671 DP_TP_CTL_A => 16#06_4040# / Register_Width,
1672 DP_TP_CTL_B => 16#06_4140# / Register_Width,
1673 DP_TP_CTL_C => 16#06_4240# / Register_Width,
1674 DP_TP_CTL_D => 16#06_4340# / Register_Width,
1675 DP_TP_CTL_E => 16#06_4440# / Register_Width,
1676 DP_TP_STATUS_B => 16#06_4144# / Register_Width,
1677 DP_TP_STATUS_C => 16#06_4244# / Register_Width,
1678 DP_TP_STATUS_D => 16#06_4344# / Register_Width,
1679 DP_TP_STATUS_E => 16#06_4444# / Register_Width,
1680 PORT_CLK_SEL_DDIA => 16#04_6100# / Register_Width,
1681 PORT_CLK_SEL_DDIB => 16#04_6104# / Register_Width,
1682 PORT_CLK_SEL_DDIC => 16#04_6108# / Register_Width,
1683 PORT_CLK_SEL_DDID => 16#04_610c# / Register_Width,
1684 PORT_CLK_SEL_DDIE => 16#04_6110# / Register_Width,
1685
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]1686 -- Haswell LCPLL registers
1687 LCPLL_CTL => 16#13_0040# / Register_Width,
1688
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]1689 -- Skylake I_boost configuration
1690 DISPIO_CR_TX_BMU_CR0 => 16#06_c00c# / Register_Width,
1691
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1692 -- Skylake DPLL registers
1693 DPLL1_CFGR1 => 16#06_c040# / Register_Width,
1694 DPLL1_CFGR2 => 16#06_c044# / Register_Width,
1695 DPLL2_CFGR1 => 16#06_c048# / Register_Width,
1696 DPLL2_CFGR2 => 16#06_c04c# / Register_Width,
1697 DPLL3_CFGR1 => 16#06_c050# / Register_Width,
1698 DPLL3_CFGR2 => 16#06_c054# / Register_Width,
1699 DPLL_CTRL1 => 16#06_c058# / Register_Width,
1700 DPLL_CTRL2 => 16#06_c05c# / Register_Width,
1701 DPLL_STATUS => 16#06_c060# / Register_Width,
1702
1703 -- CD CLK register
1704 CDCLK_CTL => 16#04_6000# / Register_Width,
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]1705 CDCLK_FREQ => 16#04_6200# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1706
1707 -- Skylake LCPLL registers
1708 LCPLL1_CTL => 16#04_6010# / Register_Width,
1709 LCPLL2_CTL => 16#04_6014# / Register_Width,
1710
1711 -- SPLL register
1712 SPLL_CTL => 16#04_6020# / Register_Width,
1713
1714 -- WRPLL registers
1715 WRPLL_CTL_1 => 16#04_6040# / Register_Width,
1716 WRPLL_CTL_2 => 16#04_6060# / Register_Width,
1717
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]1718 -- Broxton Display Engine PLL registers
1719 BXT_DE_PLL_CTL => 16#06_d000# / Register_Width,
1720 BXT_DE_PLL_ENABLE => 16#04_6070# / Register_Width,
1721
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1722 -- Broxton DDI PHY PLL registers
1723 BXT_PORT_PLL_ENABLE_A => 16#04_6074# / Register_Width,
1724 BXT_PORT_PLL_ENABLE_B => 16#04_6078# / Register_Width,
1725 BXT_PORT_PLL_ENABLE_C => 16#04_607c# / Register_Width,
1726 BXT_PORT_PLL_EBB_0_A => 16#16_2034# / Register_Width,
1727 BXT_PORT_PLL_EBB_4_A => 16#16_2038# / Register_Width,
1728 BXT_PORT_PLL_0_A => 16#16_2100# / Register_Width,
1729 BXT_PORT_PLL_1_A => 16#16_2104# / Register_Width,
1730 BXT_PORT_PLL_2_A => 16#16_2108# / Register_Width,
1731 BXT_PORT_PLL_3_A => 16#16_210c# / Register_Width,
1732 BXT_PORT_PLL_6_A => 16#16_2118# / Register_Width,
1733 BXT_PORT_PLL_8_A => 16#16_2120# / Register_Width,
1734 BXT_PORT_PLL_9_A => 16#16_2124# / Register_Width,
1735 BXT_PORT_PLL_10_A => 16#16_2128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1736 BXT_PORT_PLL_EBB_0_B => 16#06_c034# / Register_Width,
1737 BXT_PORT_PLL_EBB_4_B => 16#06_c038# / Register_Width,
1738 BXT_PORT_PLL_0_B => 16#06_c100# / Register_Width,
1739 BXT_PORT_PLL_1_B => 16#06_c104# / Register_Width,
1740 BXT_PORT_PLL_2_B => 16#06_c108# / Register_Width,
1741 BXT_PORT_PLL_3_B => 16#06_c10c# / Register_Width,
1742 BXT_PORT_PLL_6_B => 16#06_c118# / Register_Width,
1743 BXT_PORT_PLL_8_B => 16#06_c120# / Register_Width,
1744 BXT_PORT_PLL_9_B => 16#06_c124# / Register_Width,
1745 BXT_PORT_PLL_10_B => 16#06_c128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1746 BXT_PORT_PLL_EBB_0_C => 16#06_c340# / Register_Width,
1747 BXT_PORT_PLL_EBB_4_C => 16#06_c344# / Register_Width,
1748 BXT_PORT_PLL_0_C => 16#06_c380# / Register_Width,
1749 BXT_PORT_PLL_1_C => 16#06_c384# / Register_Width,
1750 BXT_PORT_PLL_2_C => 16#06_c388# / Register_Width,
1751 BXT_PORT_PLL_3_C => 16#06_c38c# / Register_Width,
1752 BXT_PORT_PLL_6_C => 16#06_c398# / Register_Width,
1753 BXT_PORT_PLL_8_C => 16#06_c3a0# / Register_Width,
1754 BXT_PORT_PLL_9_C => 16#06_c3a4# / Register_Width,
1755 BXT_PORT_PLL_10_C => 16#06_c3a8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1756
1757 -- Broxton DDI PHY PCS? registers
1758 BXT_PORT_PCS_DW10_01_A => 16#16_2428# / Register_Width,
1759 BXT_PORT_PCS_DW12_01_A => 16#16_2430# / Register_Width,
1760 BXT_PORT_PCS_DW10_GRP_A => 16#16_2c28# / Register_Width,
1761 BXT_PORT_PCS_DW12_GRP_A => 16#16_2c30# / Register_Width,
1762 BXT_PORT_PCS_DW10_01_B => 16#06_c428# / Register_Width,
1763 BXT_PORT_PCS_DW12_01_B => 16#06_c430# / Register_Width,
1764 BXT_PORT_PCS_DW10_01_C => 16#06_c828# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1765 BXT_PORT_PCS_DW12_01_C => 16#06_c830# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1766 BXT_PORT_PCS_DW10_GRP_B => 16#06_cc28# / Register_Width,
1767 BXT_PORT_PCS_DW12_GRP_B => 16#06_cc30# / Register_Width,
1768 BXT_PORT_PCS_DW10_GRP_C => 16#06_ce28# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1769 BXT_PORT_PCS_DW12_GRP_C => 16#06_ce30# / Register_Width,
1770
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1771 -- Broxton DDI PHY registers
1772 BXT_P_CR_GT_DISP_PWRON => 16#13_8090# / Register_Width,
1773 BXT_PHY_CTL_A => 16#06_4c00# / Register_Width,
1774 BXT_PHY_CTL_B => 16#06_4c10# / Register_Width,
1775 BXT_PHY_CTL_C => 16#06_4c20# / Register_Width,
1776 BXT_PHY_CTL_FAM_EDP => 16#06_4c80# / Register_Width,
1777 BXT_PHY_CTL_FAM_DDI => 16#06_4c90# / Register_Width,
1778
1779 -- Broxton DDI PHY common lane registers
1780 BXT_PORT_CL1CM_DW0_A => 16#16_2000# / Register_Width,
1781 BXT_PORT_CL1CM_DW0_BC => 16#06_c000# / Register_Width,
1782 BXT_PORT_CL1CM_DW9_A => 16#16_2024# / Register_Width,
1783 BXT_PORT_CL1CM_DW9_BC => 16#06_c024# / Register_Width,
1784 BXT_PORT_CL1CM_DW10_A => 16#16_2028# / Register_Width,
1785 BXT_PORT_CL1CM_DW10_BC => 16#06_c028# / Register_Width,
1786 BXT_PORT_CL1CM_DW28_A => 16#16_2070# / Register_Width,
1787 BXT_PORT_CL1CM_DW28_BC => 16#06_c070# / Register_Width,
1788 BXT_PORT_CL1CM_DW30_A => 16#16_2078# / Register_Width,
1789 BXT_PORT_CL1CM_DW30_BC => 16#06_c078# / Register_Width,
1790 BXT_PORT_CL2CM_DW6_BC => 16#06_c358# / Register_Width,
1791
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1792 -- Broxton DDI PHY TX lane registers
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1793 BXT_PORT_TX_DW2_LN0_A => 16#16_2508# / Register_Width,
1794 BXT_PORT_TX_DW3_LN0_A => 16#16_250c# / Register_Width,
1795 BXT_PORT_TX_DW4_LN0_A => 16#16_2510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1796 BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width,
1797 BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width,
1798 BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width,
1799 BXT_PORT_TX_DW14_LN3_A => 16#16_27b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1800 BXT_PORT_TX_DW2_GRP_A => 16#16_2d08# / Register_Width,
1801 BXT_PORT_TX_DW3_GRP_A => 16#16_2d0c# / Register_Width,
1802 BXT_PORT_TX_DW4_GRP_A => 16#16_2d10# / Register_Width,
1803 BXT_PORT_TX_DW2_LN0_B => 16#06_c508# / Register_Width,
1804 BXT_PORT_TX_DW3_LN0_B => 16#06_c50c# / Register_Width,
1805 BXT_PORT_TX_DW4_LN0_B => 16#06_c510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1806 BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width,
1807 BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width,
1808 BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width,
1809 BXT_PORT_TX_DW14_LN3_B => 16#06_c7b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1810 BXT_PORT_TX_DW2_GRP_B => 16#06_cd08# / Register_Width,
1811 BXT_PORT_TX_DW3_GRP_B => 16#06_cd0c# / Register_Width,
1812 BXT_PORT_TX_DW4_GRP_B => 16#06_cd10# / Register_Width,
1813 BXT_PORT_TX_DW2_LN0_C => 16#06_c908# / Register_Width,
1814 BXT_PORT_TX_DW3_LN0_C => 16#06_c90c# / Register_Width,
1815 BXT_PORT_TX_DW4_LN0_C => 16#06_c910# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1816 BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width,
1817 BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width,
1818 BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width,
1819 BXT_PORT_TX_DW14_LN3_C => 16#06_cbb8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1820 BXT_PORT_TX_DW2_GRP_C => 16#06_cf08# / Register_Width,
1821 BXT_PORT_TX_DW3_GRP_C => 16#06_cf0c# / Register_Width,
1822 BXT_PORT_TX_DW4_GRP_C => 16#06_cf10# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1823
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1824 -- Broxton DDI PHY ref registers
1825 BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width,
1826 BXT_PORT_REF_DW3_BC => 16#06_c18c# / Register_Width,
1827 BXT_PORT_REF_DW6_A => 16#16_2198# / Register_Width,
1828 BXT_PORT_REF_DW6_BC => 16#06_c198# / Register_Width,
1829 BXT_PORT_REF_DW8_A => 16#16_21a0# / Register_Width,
1830 BXT_PORT_REF_DW8_BC => 16#06_c1a0# / Register_Width,
1831
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1832 -- Power Down Well registers
1833 PWR_WELL_CTL_BIOS => 16#04_5400# / Register_Width,
1834 PWR_WELL_CTL_DRIVER => 16#04_5404# / Register_Width,
1835 PWR_WELL_CTL_KVMR => 16#04_5408# / Register_Width,
1836 PWR_WELL_CTL_DEBUG => 16#04_540c# / Register_Width,
1837 PWR_WELL_CTL5 => 16#04_5410# / Register_Width,
1838 PWR_WELL_CTL6 => 16#04_5414# / Register_Width,
1839
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1840 PWR_AUX_CTL_BIOS => 16#04_5440# / Register_Width,
1841 PWR_AUX_CTL_DRIVER => 16#04_5444# / Register_Width,
1842 PWR_DDI_CTL_BIOS => 16#04_5450# / Register_Width,
1843 PWR_DDI_CTL_DRIVER => 16#04_5454# / Register_Width,
1844
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1845 -- class Panel registers
Arthur Heymanse87d0d12018-03-28 17:02:49 +0200[diff] [blame]1846 GMCH_PP_STATUS => 16#06_1200# / Register_Width,
1847 GMCH_PP_CONTROL => 16#06_1204# / Register_Width,
1848 GMCH_PP_ON_DELAYS => 16#06_1208# / Register_Width,
1849 GMCH_PP_OFF_DELAYS => 16#06_120c# / Register_Width,
1850 GMCH_PP_DIVISOR => 16#06_1210# / Register_Width,
Arthur Heymansd5198442018-03-28 17:05:12 +0200[diff] [blame]1851 GMCH_PFIT_CONTROL => 16#06_1230# / Register_Width,
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]1852 PCH_PP_STATUS => 16#0c_7200# / Register_Width, -- aliased with BXT_PP_STATUS_1
1853 PCH_PP_CONTROL => 16#0c_7204# / Register_Width, -- aliased with BXT_PP_CONTROL_1
1854 PCH_PP_ON_DELAYS => 16#0c_7208# / Register_Width, -- aliased with BXT_PP_ON_DELAYS_1
1855 PCH_PP_OFF_DELAYS => 16#0c_720c# / Register_Width, -- aliased with BXT_PP_OFF_DELAYS_1
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1856 PCH_PP_DIVISOR => 16#0c_7210# / Register_Width,
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]1857 BXT_PP_STATUS_2 => 16#0c_7300# / Register_Width,
1858 BXT_PP_CONTROL_2 => 16#0c_7304# / Register_Width,
1859 BXT_PP_ON_DELAYS_2 => 16#0c_7308# / Register_Width,
1860 BXT_PP_OFF_DELAYS_2 => 16#0c_730c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1861 BLC_PWM_CPU_CTL => 16#04_8254# / Register_Width,
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]1862 BLC_PWM_CPU_CTL2 => 16#04_8250# / Register_Width,
1863 BLC_PWM_PCH_CTL1 => 16#0c_8250# / Register_Width, -- aliased with BXT_BLC_PWM_CTL_1
1864 BLC_PWM_PCH_CTL2 => 16#0c_8254# / Register_Width, -- aliased with BXT_BLC_PWM_FREQ_1
1865 BXT_BLC_PWM_DUTY_1 => 16#0c_8258# / Register_Width,
1866 BXT_BLC_PWM_CTL_2 => 16#0c_8350# / Register_Width,
1867 BXT_BLC_PWM_FREQ_2 => 16#0c_8354# / Register_Width,
1868 BXT_BLC_PWM_DUTY_2 => 16#0c_8358# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1869
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1870 -- GMCH LVDS Connector Registers
1871 GMCH_LVDS => 16#06_1180# / Register_Width,
1872
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1873 -- PCH LVDS Connector Registers
1874 PCH_LVDS => 16#0e_1180# / Register_Width,
1875
1876 -- PCH ADPA Connector Registers
1877 PCH_ADPA => 16#0e_1100# / Register_Width,
1878
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1879 -- GMCH DVOB Connector Registers
1880 GMCH_SDVOB => 16#06_1140# / Register_Width,
1881
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1882 -- PCH HDMIB Connector Registers
1883 PCH_HDMIB => 16#0e_1140# / Register_Width,
1884
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1885 -- GMCH DVOC Connector Registers
1886 GMCH_SDVOC => 16#06_1160# / Register_Width,
1887
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1888 -- PCH HDMIC Connector Registers
1889 PCH_HDMIC => 16#0e_1150# / Register_Width,
1890
1891 -- PCH HDMID Connector Registers
1892 PCH_HDMID => 16#0e_1160# / Register_Width,
1893
1894 -- Intel Registers
Nico Huber6b4678d2019-09-22 21:31:52 +0200[diff] [blame]1895 DFSM => 16#05_1000# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1896 DSSM => 16#05_1004# / Register_Width,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]1897 CPU_VGACNTRL => 16#04_1000# / Register_Width,
1898 GMCH_VGACNTRL => 16#07_1400# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1899 FUSE_STATUS => 16#04_2000# / Register_Width,
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]1900 FUSE_STRAP => 16#04_2014# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1901 FBA_CFB_BASE => 16#04_3200# / Register_Width,
1902 IPS_CTL => 16#04_3408# / Register_Width,
1903 ARB_CTL => 16#04_5000# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1904 DBUF_CTL_S0 => 16#04_5008# / Register_Width,
1905 DBUF_CTL_S1 => 16#04_4fe8# / Register_Width,
1906 DBUF_CTL_S2 => 16#04_4300# / Register_Width,
1907 DBUF_CTL_S3 => 16#04_4304# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1908 NDE_RSTWRN_OPT => 16#04_6408# / Register_Width,
Angel Ponsae186bd2020-10-21 21:37:34 +0200[diff] [blame]1909 GEN8_CHICKEN_DCPR_1 => 16#04_6430# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1910 GEN11_CHICKEN_DCPR_2 => 16#04_6434# / Register_Width,
1911 GEN9_CLKGATE_DIS_0 => 16#04_6530# / Register_Width,
1912 GEN9_CLKGATE_DIS_5 => 16#04_6540# / Register_Width,
1913 GEN9_CHICKEN_DPCR_3 => 16#04_6538# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1914 PCH_DREF_CONTROL => 16#0c_6200# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1915 PCH_DPLL_SEL => 16#0c_7000# / Register_Width,
1916 GT_MAILBOX => 16#13_8124# / Register_Width,
1917 GT_MAILBOX_DATA => 16#13_8128# / Register_Width,
1918 GT_MAILBOX_DATA_1 => 16#13_812c# / Register_Width,
1919
1920 PCH_DP_B => 16#0e_4100# / Register_Width,
1921 PCH_DP_AUX_CTL_B => 16#0e_4110# / Register_Width,
1922 PCH_DP_AUX_DATA_B_1 => 16#0e_4114# / Register_Width,
1923 PCH_DP_AUX_DATA_B_2 => 16#0e_4118# / Register_Width,
1924 PCH_DP_AUX_DATA_B_3 => 16#0e_411c# / Register_Width,
1925 PCH_DP_AUX_DATA_B_4 => 16#0e_4120# / Register_Width,
1926 PCH_DP_AUX_DATA_B_5 => 16#0e_4124# / Register_Width,
1927 PCH_DP_C => 16#0e_4200# / Register_Width,
1928 PCH_DP_AUX_CTL_C => 16#0e_4210# / Register_Width,
1929 PCH_DP_AUX_DATA_C_1 => 16#0e_4214# / Register_Width,
1930 PCH_DP_AUX_DATA_C_2 => 16#0e_4218# / Register_Width,
1931 PCH_DP_AUX_DATA_C_3 => 16#0e_421c# / Register_Width,
1932 PCH_DP_AUX_DATA_C_4 => 16#0e_4220# / Register_Width,
1933 PCH_DP_AUX_DATA_C_5 => 16#0e_4224# / Register_Width,
1934 PCH_DP_D => 16#0e_4300# / Register_Width,
1935 PCH_DP_AUX_CTL_D => 16#0e_4310# / Register_Width,
1936 PCH_DP_AUX_DATA_D_1 => 16#0e_4314# / Register_Width,
1937 PCH_DP_AUX_DATA_D_2 => 16#0e_4318# / Register_Width,
1938 PCH_DP_AUX_DATA_D_3 => 16#0e_431c# / Register_Width,
1939 PCH_DP_AUX_DATA_D_4 => 16#0e_4320# / Register_Width,
1940 PCH_DP_AUX_DATA_D_5 => 16#0e_4324# / Register_Width,
1941
1942 -- watermark registers
1943 WM1_LP_ILK => 16#04_5108# / Register_Width,
1944 WM2_LP_ILK => 16#04_510c# / Register_Width,
1945 WM3_LP_ILK => 16#04_5110# / Register_Width,
1946
1947 -- audio VID/DID
1948 AUD_VID_DID => 16#06_5020# / Register_Width,
1949 PCH_AUD_VID_DID => 16#0e_5020# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1950 G4X_AUD_VID_DID => 16#06_2020# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1951
1952 -- interrupt registers
1953 DEISR => 16#04_4000# / Register_Width,
1954 DEIMR => 16#04_4004# / Register_Width,
1955 DEIIR => 16#04_4008# / Register_Width,
1956 DEIER => 16#04_400c# / Register_Width,
1957 GTISR => 16#04_4010# / Register_Width,
1958 GTIMR => 16#04_4014# / Register_Width,
1959 GTIIR => 16#04_4018# / Register_Width,
1960 GTIER => 16#04_401c# / Register_Width,
1961 SDEISR => 16#0c_4000# / Register_Width,
1962 SDEIMR => 16#0c_4004# / Register_Width,
1963 SDEIIR => 16#0c_4008# / Register_Width,
1964 SDEIER => 16#0c_400c# / Register_Width,
1965
1966 -- I2C stuff
Arthur Heymans229ed1c2018-03-28 16:45:43 +0200[diff] [blame]1967 GMCH_GMBUS0 => 16#00_5100# / Register_Width,
1968 GMCH_GMBUS1 => 16#00_5104# / Register_Width,
1969 GMCH_GMBUS2 => 16#00_5108# / Register_Width,
1970 GMCH_GMBUS3 => 16#00_510c# / Register_Width,
1971 GMCH_GMBUS4 => 16#00_5110# / Register_Width,
1972 GMCH_GMBUS5 => 16#00_5120# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1973 PCH_GMBUS0 => 16#0c_5100# / Register_Width,
1974 PCH_GMBUS1 => 16#0c_5104# / Register_Width,
1975 PCH_GMBUS2 => 16#0c_5108# / Register_Width,
1976 PCH_GMBUS3 => 16#0c_510c# / Register_Width,
1977 PCH_GMBUS4 => 16#0c_5110# / Register_Width,
1978 PCH_GMBUS5 => 16#0c_5120# / Register_Width,
1979
1980 -- clock gating -- maybe have to touch this
1981 DSPCLK_GATE_D => 16#04_2020# / Register_Width,
1982 PCH_FDI_CHICKEN_B_C => 16#0c_2000# / Register_Width,
1983 PCH_DSPCLK_GATE_D => 16#0c_2020# / Register_Width,
1984
1985 -- hotplug and initial detection
1986 HOTPLUG_CTL => 16#04_4030# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1987 TC_HOTPLUG_CTL => 16#04_4038# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1988 PORT_HOTPLUG_EN => 16#06_1110# / Register_Width,
1989 PORT_HOTPLUG_STAT => 16#06_1114# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1990 SHOTPLUG_CTL => 16#0c_4030# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1991 SHOTPLUG_CTL_TC => 16#0c_4034# / Register_Width,
1992 SHPD_FILTER_CNT => 16#0c_4038# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1993 SFUSE_STRAP => 16#0c_2014# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]1994 GEN11_DE_HPD_ISR => 16#04_4470# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1995
1996 -- Render Engine Command Streamer
1997 ARB_MODE => 16#00_4030# / Register_Width,
1998 HWS_PGA => 16#00_4080# / Register_Width,
1999 RCS_RING_BUFFER_TAIL => 16#00_2030# / Register_Width,
2000 VCS_RING_BUFFER_TAIL => 16#01_2030# / Register_Width,
2001 BCS_RING_BUFFER_TAIL => 16#02_2030# / Register_Width,
2002 RCS_RING_BUFFER_HEAD => 16#00_2034# / Register_Width,
2003 VCS_RING_BUFFER_HEAD => 16#01_2034# / Register_Width,
2004 BCS_RING_BUFFER_HEAD => 16#02_2034# / Register_Width,
2005 RCS_RING_BUFFER_STRT => 16#00_2038# / Register_Width,
2006 VCS_RING_BUFFER_STRT => 16#01_2038# / Register_Width,
2007 BCS_RING_BUFFER_STRT => 16#02_2038# / Register_Width,
2008 RCS_RING_BUFFER_CTL => 16#00_203c# / Register_Width,
2009 VCS_RING_BUFFER_CTL => 16#01_203c# / Register_Width,
2010 BCS_RING_BUFFER_CTL => 16#02_203c# / Register_Width,
2011 MI_MODE => 16#00_209c# / Register_Width,
2012 INSTPM => 16#00_20c0# / Register_Width,
2013 GAB_CTL_REG => 16#02_4000# / Register_Width,
2014 PP_DCLV_HIGH => 16#00_2220# / Register_Width,
2015 PP_DCLV_LOW => 16#00_2228# / Register_Width,
2016 VCS_PP_DCLV_HIGH => 16#01_2220# / Register_Width,
2017 VCS_PP_DCLV_LOW => 16#01_2228# / Register_Width,
2018 BCS_PP_DCLV_HIGH => 16#02_2220# / Register_Width,
2019 BCS_PP_DCLV_LOW => 16#02_2228# / Register_Width,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]2020 ILK_DISPLAY_CHICKEN2 => 16#04_2004# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2021 UCGCTL1 => 16#00_9400# / Register_Width,
2022 UCGCTL2 => 16#00_9404# / Register_Width,
2023 MBCTL => 16#00_907c# / Register_Width,
2024 HWSTAM => 16#00_2098# / Register_Width,
2025 VCS_HWSTAM => 16#01_2098# / Register_Width,
2026 BCS_HWSTAM => 16#02_2098# / Register_Width,
2027 IIR => 16#04_4028# / Register_Width,
2028 PIPE_FRMCNT_A => 16#07_0040# / Register_Width,
2029 PIPE_FRMCNT_B => 16#07_1040# / Register_Width,
2030 PIPE_FRMCNT_C => 16#07_2040# / Register_Width,
2031 FBC_CTL => 16#04_3208# / Register_Width,
2032 PIPE_VSYNCSHIFT_A => 16#06_0028# / Register_Width,
2033 PIPE_VSYNCSHIFT_B => 16#06_1028# / Register_Width,
2034 PIPE_VSYNCSHIFT_C => 16#06_2028# / Register_Width,
2035 WM_PIPE_A => 16#04_5100# / Register_Width,
2036 WM_PIPE_B => 16#04_5104# / Register_Width,
2037 WM_PIPE_C => 16#04_5200# / Register_Width,
2038 PIPE_SCANLINE_A => 16#07_0000# / Register_Width,
2039 PIPE_SCANLINE_B => 16#07_1000# / Register_Width,
2040 PIPE_SCANLINE_C => 16#07_2000# / Register_Width,
2041 GFX_MODE => 16#00_2520# / Register_Width,
2042 CACHE_MODE_0 => 16#00_2120# / Register_Width,
2043 SLEEP_PSMI_CONTROL => 16#01_2050# / Register_Width,
2044 CTX_SIZE => 16#00_21a0# / Register_Width,
2045 GAC_ECO_BITS => 16#01_4090# / Register_Width,
2046 GAM_ECOCHK => 16#00_4090# / Register_Width,
2047 QUIRK_02084 => 16#00_2084# / Register_Width,
2048 QUIRK_02090 => 16#00_2090# / Register_Width,
2049 GT_MODE => 16#00_20d0# / Register_Width,
2050 QUIRK_F0060 => 16#0f_0060# / Register_Width,
2051 QUIRK_F1060 => 16#0f_1060# / Register_Width,
2052 QUIRK_F2060 => 16#0f_2060# / Register_Width,
2053 AUD_CNTRL_ST2 => 16#0e_50c0# / Register_Width,
2054 AUD_CNTL_ST_A => 16#0e_50b4# / Register_Width,
2055 AUD_CNTL_ST_B => 16#0e_51b4# / Register_Width,
2056 AUD_CNTL_ST_C => 16#0e_52b4# / Register_Width,
2057 AUD_HDMIW_HDMIEDID_A => 16#0e_5050# / Register_Width,
2058 AUD_HDMIW_HDMIEDID_B => 16#0e_5150# / Register_Width,
2059 AUD_HDMIW_HDMIEDID_C => 16#0e_5250# / Register_Width,
2060 AUD_CONFIG_A => 16#0e_5000# / Register_Width,
2061 AUD_CONFIG_B => 16#0e_5100# / Register_Width,
2062 AUD_CONFIG_C => 16#0e_5200# / Register_Width,
2063 TRANS_DP_CTL_A => 16#0e_0300# / Register_Width,
2064 TRANS_DP_CTL_B => 16#0e_1300# / Register_Width,
2065 TRANS_DP_CTL_C => 16#0e_2300# / Register_Width,
2066 TRANS_VSYNCSHIFT_A => 16#0e_0028# / Register_Width,
2067 TRANS_VSYNCSHIFT_B => 16#0e_1028# / Register_Width,
2068 TRANS_VSYNCSHIFT_C => 16#0e_2028# / Register_Width,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]2069 PCH_RAWCLK_FREQ => 16#0c_6204# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]2070 QUIRK_C2004 => 16#0c_2004# / Register_Width,
2071
2072 -- MCHBAR Mirror
2073
Nico Huberb47a5c42019-09-29 00:07:21 +0200[diff] [blame]2074 GMCH_CLKCFG => 16#01_0c00# / Register_Width,
2075 GMCH_HPLLVCO_MOBILE => 16#01_0c0f# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]2076 GMCH_HPLLVCO => 16#01_0c38# / Register_Width,
2077
2078 -- Combo Phy Registers (Tigerlake on)
2079
2080 PHY_MISC_B => 16#06_4c04# / Register_Width,
2081 PHY_MISC_C => 16#06_4c08# / Register_Width,
2082 PORT_CL_DW5_A => 16#16_2014# / Register_Width,
2083 PORT_CL_DW5_B => 16#06_c014# / Register_Width,
2084 PORT_CL_DW5_C => 16#16_0014# / Register_Width,
2085 PORT_COMP_DW0_C => 16#16_0100# / Register_Width,
2086 PORT_COMP_DW1_C => 16#16_0104# / Register_Width,
2087 PORT_COMP_DW3_C => 16#16_010c# / Register_Width,
2088 PORT_COMP_DW8_C => 16#16_0120# / Register_Width,
2089 PORT_COMP_DW9_C => 16#16_0124# / Register_Width,
2090 PORT_COMP_DW10_C => 16#16_0128# / Register_Width,
2091 PORT_TX_DW8_LN0_A => 16#16_28a0# / Register_Width,
2092 PORT_TX_DW8_LN0_B => 16#06_c8a0# / Register_Width,
2093 PORT_TX_DW8_LN0_C => 16#16_08a0# / Register_Width,
2094 PORT_TX_DW8_GRP_A => 16#16_26a0# / Register_Width,
2095 PORT_TX_DW8_GRP_B => 16#06_c6a0# / Register_Width,
2096 PORT_TX_DW8_GRP_C => 16#16_06a0# / Register_Width,
2097 PORT_PCS_DW1_LN0_A => 16#16_2804# / Register_Width,
2098 PORT_PCS_DW1_LN0_B => 16#06_c804# / Register_Width,
2099 PORT_PCS_DW1_LN0_C => 16#16_0804# / Register_Width,
2100 PORT_PCS_DW1_GRP_A => 16#16_2604# / Register_Width,
2101 PORT_PCS_DW1_GRP_B => 16#06_c604# / Register_Width,
2102 PORT_PCS_DW1_GRP_C => 16#16_0604# / Register_Width,
2103 MBUS_ABOX_CTL => 16#04_5038# / Register_Width,
2104 MBUS_ABOX1_CTL => 16#04_5048# / Register_Width,
2105 MBUS_ABOX2_CTL => 16#04_504c# / Register_Width,
2106 BW_BUDDY1_PAGE_MASK => 16#04_5144# / Register_Width,
2107 BW_BUDDY2_PAGE_MASK => 16#04_5154# / Register_Width,
2108 BW_BUDDY1_CTL => 16#04_5140# / Register_Width,
2109 BW_BUDDY2_CTL => 16#04_5150# / Register_Width,
2110
2111 -- TGL DKL PHY registers
2112 HIP_INDEX_REG0 => 16#10_10a0# / Register_Width,
2113 HIP_INDEX_REG1 => 16#10_10a4# / Register_Width,
2114 -- Each type-C port PHY is addressed through a 4KB
2115 -- aperture. Each PHY has more than 4KB of register space, so a
2116 -- separate index is programmed in HIP_INDEX_REG0 or
2117 -- HIP_INDEX_REG1, based on the port number, to set the upper 2
2118 -- address bits that point the 4KB window into the full PHY
2119 -- register space.
2120 -- The registers below assumes index 2 has been programmed.
2121
2122 -- 16_8*** registers for DKL PHY 1
2123 DKL_CLKTOP2_HSCC_1 => 16#16_80d4# / Register_Width,
2124 DKL_CLKTOP2_CCC1_1 => 16#16_80d8# / Register_Width,
2125 DKL_REFCLKIN_CTL_1 => 16#16_812c# / Register_Width,
2126 DKL_PLL_DIV0_1 => 16#16_8200# / Register_Width,
2127 DKL_PLL_DIV1_1 => 16#16_8204# / Register_Width,
2128 DKL_PLL_SSC_1 => 16#16_8210# / Register_Width,
2129 DKL_PLL_BIAS_1 => 16#16_8214# / Register_Width,
2130 DKL_PLL_COLDST_BIAS_1 => 16#16_8218# / Register_Width,
2131 DKL_CMN_UC_DW_27_1 => 16#16_836c# / Register_Width,
2132 DKL_DP_MODE_1 => 16#16_80a0# / Register_Width,
2133 -- 16_9*** registers for DKL PHY 2
2134 DKL_CLKTOP2_HSCC_2 => 16#16_90d4# / Register_Width,
2135 DKL_CLKTOP2_CCC1_2 => 16#16_90d8# / Register_Width,
2136 DKL_REFCLKIN_CTL_2 => 16#16_912c# / Register_Width,
2137 DKL_PLL_DIV0_2 => 16#16_9200# / Register_Width,
2138 DKL_PLL_DIV1_2 => 16#16_9204# / Register_Width,
2139 DKL_PLL_SSC_2 => 16#16_9210# / Register_Width,
2140 DKL_PLL_BIAS_2 => 16#16_9214# / Register_Width,
2141 DKL_PLL_COLDST_BIAS_2 => 16#16_9218# / Register_Width,
2142 DKL_CMN_UC_DW_27_2 => 16#16_936c# / Register_Width,
2143 DKL_DP_MODE_2 => 16#16_90a0# / Register_Width,
2144 -- 16_a*** registers for DKL PHY 3
2145 DKL_CLKTOP2_HSCC_3 => 16#16_a0d4# / Register_Width,
2146 DKL_CLKTOP2_CCC1_3 => 16#16_a0d8# / Register_Width,
2147 DKL_REFCLKIN_CTL_3 => 16#16_a12c# / Register_Width,
2148 DKL_PLL_DIV0_3 => 16#16_a200# / Register_Width,
2149 DKL_PLL_DIV1_3 => 16#16_a204# / Register_Width,
2150 DKL_PLL_SSC_3 => 16#16_a210# / Register_Width,
2151 DKL_PLL_BIAS_3 => 16#16_a214# / Register_Width,
2152 DKL_PLL_COLDST_BIAS_3 => 16#16_a218# / Register_Width,
2153 DKL_CMN_UC_DW_27_3 => 16#16_a36c# / Register_Width,
2154 DKL_DP_MODE_3 => 16#16_a0a0# / Register_Width,
2155 -- 16_b*** registers for DKL PHY 4
2156 DKL_CLKTOP2_HSCC_4 => 16#16_b0d4# / Register_Width,
2157 DKL_CLKTOP2_CCC1_4 => 16#16_b0d8# / Register_Width,
2158 DKL_REFCLKIN_CTL_4 => 16#16_b12c# / Register_Width,
2159 DKL_PLL_DIV0_4 => 16#16_b200# / Register_Width,
2160 DKL_PLL_DIV1_4 => 16#16_b204# / Register_Width,
2161 DKL_PLL_SSC_4 => 16#16_b210# / Register_Width,
2162 DKL_PLL_BIAS_4 => 16#16_b214# / Register_Width,
2163 DKL_PLL_COLDST_BIAS_4 => 16#16_b218# / Register_Width,
2164 DKL_CMN_UC_DW_27_4 => 16#16_b36c# / Register_Width,
2165 DKL_DP_MODE_4 => 16#16_b0a0# / Register_Width,
2166 -- 16_c*** registers for DKL PHY 5
2167 DKL_CLKTOP2_HSCC_5 => 16#16_c0d4# / Register_Width,
2168 DKL_CLKTOP2_CCC1_5 => 16#16_c0d8# / Register_Width,
2169 DKL_REFCLKIN_CTL_5 => 16#16_c12c# / Register_Width,
2170 DKL_PLL_DIV0_5 => 16#16_c200# / Register_Width,
2171 DKL_PLL_DIV1_5 => 16#16_c204# / Register_Width,
2172 DKL_PLL_SSC_5 => 16#16_c210# / Register_Width,
2173 DKL_PLL_BIAS_5 => 16#16_c214# / Register_Width,
2174 DKL_PLL_COLDST_BIAS_5 => 16#16_c218# / Register_Width,
2175 DKL_CMN_UC_DW_27_5 => 16#16_c36c# / Register_Width,
2176 DKL_DP_MODE_5 => 16#16_c0a0# / Register_Width,
2177 -- 16_d*** registers for DKL PHY 6
2178 DKL_CLKTOP2_HSCC_6 => 16#16_d0d4# / Register_Width,
2179 DKL_CLKTOP2_CCC1_6 => 16#16_d0d8# / Register_Width,
2180 DKL_REFCLKIN_CTL_6 => 16#16_d12c# / Register_Width,
2181 DKL_PLL_DIV0_6 => 16#16_d200# / Register_Width,
2182 DKL_PLL_DIV1_6 => 16#16_d204# / Register_Width,
2183 DKL_PLL_SSC_6 => 16#16_d210# / Register_Width,
2184 DKL_PLL_BIAS_6 => 16#16_d214# / Register_Width,
2185 DKL_PLL_COLDST_BIAS_6 => 16#16_d218# / Register_Width,
2186 DKL_CMN_UC_DW_27_6 => 16#16_d36c# / Register_Width,
2187 DKL_DP_MODE_6 => 16#16_d0a0# / Register_Width,
2188
2189 -- TGL DPLL registers
2190 DPLL_4_ENABLE => 16#04_6018# / Register_Width,
2191 DPLL_0_CFGCR0 => 16#16_4284# / Register_Width,
2192 DPLL_0_CFGCR1 => 16#16_4288# / Register_Width,
2193 DPLL_1_CFGCR0 => 16#16_428c# / Register_Width,
2194 DPLL_1_CFGCR1 => 16#16_4290# / Register_Width,
2195 DPLL_4_CFGCR0 => 16#16_4294# / Register_Width,
2196 DPLL_4_CFGCR1 => 16#16_4298# / Register_Width,
2197 DPLL_0_SSC => 16#16_4b10# / Register_Width,
2198 DPLL_1_SSC => 16#16_4c10# / Register_Width,
2199 DPLL_4_SSC => 16#16_4e10# / Register_Width,
2200
2201 -- TGL DDI registers (some aliases too)
2202 DDI_BUF_CTL_USBC3 => 16#06_4500# / Register_Width,
2203 DDI_BUF_CTL_USBC4 => 16#06_4600# / Register_Width,
2204 DDI_BUF_CTL_USBC5 => 16#06_4700# / Register_Width,
2205 PORT_TX_DW2_LN0_A => 16#16_2888# / Register_Width,
2206 PORT_TX_DW2_LN0_B => 16#06_c888# / Register_Width,
2207 PORT_TX_DW2_LN0_C => 16#16_0888# / Register_Width,
2208 PORT_TX_DW2_GRP_A => 16#16_2688# / Register_Width,
2209 PORT_TX_DW2_GRP_B => 16#06_c688# / Register_Width,
2210 PORT_TX_DW2_GRP_C => 16#16_0688# / Register_Width,
2211 PORT_TX_DW4_LN0_A => 16#16_2890# / Register_Width,
2212 PORT_TX_DW4_LN1_A => 16#16_2990# / Register_Width,
2213 PORT_TX_DW4_LN2_A => 16#16_2a90# / Register_Width,
2214 PORT_TX_DW4_LN3_A => 16#16_2b90# / Register_Width,
2215 PORT_TX_DW4_LN0_B => 16#06_c890# / Register_Width,
2216 PORT_TX_DW4_LN1_B => 16#06_c990# / Register_Width,
2217 PORT_TX_DW4_LN2_B => 16#06_ca90# / Register_Width,
2218 PORT_TX_DW4_LN3_B => 16#06_cb90# / Register_Width,
2219 PORT_TX_DW4_LN0_C => 16#16_0890# / Register_Width,
2220 PORT_TX_DW4_LN1_C => 16#16_0990# / Register_Width,
2221 PORT_TX_DW4_LN2_C => 16#16_0a90# / Register_Width,
2222 PORT_TX_DW4_LN3_C => 16#16_0b90# / Register_Width,
2223 PORT_TX_DW4_GRP_A => 16#16_2690# / Register_Width,
2224 PORT_TX_DW4_GRP_B => 16#06_c690# / Register_Width,
2225 PORT_TX_DW4_GRP_C => 16#16_0690# / Register_Width,
2226 PORT_TX_DW5_LN0_A => 16#16_2894# / Register_Width,
2227 PORT_TX_DW5_LN0_B => 16#06_c894# / Register_Width,
2228 PORT_TX_DW5_LN0_C => 16#16_0894# / Register_Width,
2229 PORT_TX_DW5_GRP_A => 16#16_2694# / Register_Width,
2230 PORT_TX_DW5_GRP_B => 16#06_c694# / Register_Width,
2231 PORT_TX_DW5_GRP_C => 16#16_0694# / Register_Width,
2232 PORT_TX_DW7_LN0_A => 16#16_289c# / Register_Width,
2233 PORT_TX_DW7_LN0_B => 16#06_c89c# / Register_Width,
2234 PORT_TX_DW7_LN0_C => 16#16_089c# / Register_Width,
2235 PORT_TX_DW7_GRP_A => 16#16_269c# / Register_Width,
2236 PORT_TX_DW7_GRP_B => 16#06_c69c# / Register_Width,
2237 PORT_TX_DW7_GRP_C => 16#16_069c# / Register_Width,
2238
2239 -- TGL DisplayPort transport
2240 TGL_DP_TP_CTL_A => 16#06_0540# / Register_Width,
2241 TGL_DP_TP_CTL_B => 16#06_1540# / Register_Width,
2242 TGL_DP_TP_CTL_C => 16#06_2540# / Register_Width,
2243 TGL_DP_TP_STATUS_A => 16#06_0544# / Register_Width,
2244 TGL_DP_TP_STATUS_B => 16#06_1544# / Register_Width,
2245 TGL_DP_TP_STATUS_C => 16#06_2544# / Register_Width,
2246 DPCLKA_CFGCR0 => 16#16_4280# / Register_Width,
2247 PORT_CL_DW10_C => 16#16_0028# / Register_Width,
2248
2249 -- MBUS DBOX
2250 PIPE_MBUS_DBOX_CTL_A => 16#07_003c# / Register_Width,
2251 PIPE_MBUS_DBOX_CTL_B => 16#07_103c# / Register_Width,
2252 PIPE_MBUS_DBOX_CTL_C => 16#07_203c# / Register_Width,
2253
2254 -- TGL+ new plane control registers
2255 PLANE_AUX_DIST_1_A => 16#07_01c0# / Register_Width,
2256 PLANE_AUX_DIST_1_B => 16#07_11c0# / Register_Width,
2257 PLANE_AUX_DIST_1_C => 16#07_21c0# / Register_Width,
2258 PLANE_COLOR_CTL_1_A => 16#07_01cc# / Register_Width,
2259 PLANE_COLOR_CTL_1_B => 16#07_11cc# / Register_Width,
2260 PLANE_COLOR_CTL_1_C => 16#07_21cc# / Register_Width,
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]2261 PLANE_COLOR_CTL_2_A => 16#07_02cc# / Register_Width,
2262 PLANE_COLOR_CTL_2_B => 16#07_12cc# / Register_Width,
2263 PLANE_COLOR_CTL_2_C => 16#07_22cc# / Register_Width,
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]2264
2265 -- TGL FIA registers
2266 PORT_TX_DFLEXDPCSSS_FIA1 => 16#16_3894# / Register_Width,
2267 PORT_TX_DFLEXDPMLE1_FIA1 => 16#16_38c0# / Register_Width,
2268 PORT_TX_DFLEXDPPMS_FIA1 => 16#16_3890# / Register_Width,
2269 PORT_TX_DFLEXDPSP_FIA1 => 16#16_38a0# / Register_Width,
2270 PORT_TX_DFLEXPA1_FIA1 => 16#16_3880# / Register_Width,
2271 PORT_TX_DFLEXDPCSSS_FIA2 => 16#16_e894# / Register_Width,
2272 PORT_TX_DFLEXDPMLE1_FIA2 => 16#16_e8c0# / Register_Width,
2273 PORT_TX_DFLEXDPPMS_FIA2 => 16#16_e890# / Register_Width,
2274 PORT_TX_DFLEXDPSP_FIA2 => 16#16_e8a0# / Register_Width,
2275 PORT_TX_DFLEXPA1_FIA2 => 16#16_e880# / Register_Width,
2276 PORT_TX_DFLEXDPCSSS_FIA3 => 16#16_f894# / Register_Width,
2277 PORT_TX_DFLEXDPMLE1_FIA3 => 16#16_f8c0# / Register_Width,
2278 PORT_TX_DFLEXDPPMS_FIA3 => 16#16_f890# / Register_Width,
2279 PORT_TX_DFLEXDPSP_FIA3 => 16#16_f8a0# / Register_Width,
2280 PORT_TX_DFLEXPA1_FIA3 => 16#16_f880# / Register_Width,
2281
2282 -- TGL DDI clock select
2283 DDI_CLK_SEL_USBC3 => 16#04_6114# / Register_Width,
2284 DDI_CLK_SEL_USBC4 => 16#04_6118# / Register_Width,
2285 DDI_CLK_SEL_USBC5 => 16#04_611c# / Register_Width,
2286 DDI_CLK_SEL_USBC6 => 16#04_6120# / Register_Width,
2287
2288 -- TGL DKL PLLs
2289 MGPLL1_ENABLE => 16#04_6030# / Register_Width,
2290 MGPLL2_ENABLE => 16#04_6034# / Register_Width,
2291 MGPLL3_ENABLE => 16#04_6038# / Register_Width,
2292 MGPLL4_ENABLE => 16#04_603c# / Register_Width,
2293 MGPLL6_ENABLE => 16#04_6044# / Register_Width,
2294
2295 -- ADL-P DKL PLLs
2296 PORTTC3_PLL1_ENABLE => 16#04_6048# / Register_Width,
2297 PORTTC4_PLL0_ENABLE => 16#04_604c# / Register_Width,
2298 PORTTC4_PLL1_ENABLE => 16#04_6050# / Register_Width,
2299
2300 -- TGL DKL Vswing
2301 DKL_TX_PMD_LANE_SUS_1 => 16#16_8d00# / Register_Width,
2302 DKL_TX_PMD_LANE_SUS_2 => 16#16_9d00# / Register_Width,
2303 DKL_TX_PMD_LANE_SUS_3 => 16#16_ad00# / Register_Width,
2304 DKL_TX_PMD_LANE_SUS_4 => 16#16_bd00# / Register_Width,
2305 DKL_TX_PMD_LANE_SUS_5 => 16#16_cd00# / Register_Width,
2306 DKL_TX_PMD_LANE_SUS_6 => 16#16_dd00# / Register_Width,
2307 DKL_TX_DPCNTL0_1 => 16#16_82c0# / Register_Width,
2308 DKL_TX_DPCNTL0_2 => 16#16_92c0# / Register_Width,
2309 DKL_TX_DPCNTL0_3 => 16#16_a2c0# / Register_Width,
2310 DKL_TX_DPCNTL0_4 => 16#16_b2c0# / Register_Width,
2311 DKL_TX_DPCNTL0_5 => 16#16_c2c0# / Register_Width,
2312 DKL_TX_DPCNTL0_6 => 16#16_d2c0# / Register_Width,
2313 DKL_TX_DPCNTL1_1 => 16#16_82c4# / Register_Width,
2314 DKL_TX_DPCNTL1_2 => 16#16_92c4# / Register_Width,
2315 DKL_TX_DPCNTL1_3 => 16#16_a2c4# / Register_Width,
2316 DKL_TX_DPCNTL1_4 => 16#16_b2c4# / Register_Width,
2317 DKL_TX_DPCNTL1_5 => 16#16_c2c4# / Register_Width,
2318 DKL_TX_DPCNTL1_6 => 16#16_d2c4# / Register_Width,
2319 DKL_TX_DPCNTL2_1 => 16#16_82c8# / Register_Width,
2320 DKL_TX_DPCNTL2_2 => 16#16_92c8# / Register_Width,
2321 DKL_TX_DPCNTL2_3 => 16#16_a2c8# / Register_Width,
2322 DKL_TX_DPCNTL2_4 => 16#16_b2c8# / Register_Width,
2323 DKL_TX_DPCNTL2_5 => 16#16_c2c8# / Register_Width,
2324 DKL_TX_DPCNTL2_6 => 16#16_d2c8# / Register_Width,
2325
2326 -- ADL-P DKL registers
2327 DKL_PCS_DW5_1 => 16#16_8014# / Register_Width,
2328 DKL_PCS_DW5_2 => 16#16_9014# / Register_Width,
2329 DKL_PCS_DW5_3 => 16#16_a014# / Register_Width,
2330 DKL_PCS_DW5_4 => 16#16_b014# / Register_Width,
2331
2332 -- ADL-P DDI status
2333 TCSS_DDI_STATUS_1 => 16#16_1500# / Register_Width,
2334 TCSS_DDI_STATUS_2 => 16#16_1504# / Register_Width,
2335 TCSS_DDI_STATUS_3 => 16#16_1508# / Register_Width,
2336 TCSS_DDI_STATUS_4 => 16#16_150c# / Register_Width,
2337
2338 DISPLAY_ERR_FATAL_MASK => 16#04_421c# / Register_Width,
2339 MBUS_CTL => 16#04_438c# / Register_Width);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2340
2341 subtype Registers_Index is Registers_Invalid_Index range
2342 Registers_Invalid_Index'Succ (Invalid_Register) ..
2343 Registers_Invalid_Index'Last;
2344
2345 -- aliased registers
2346 DP_CTL_A : constant Registers_Index := DDI_BUF_CTL_A;
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]2347 GMCH_DP_B : constant Registers_Index := DDI_BUF_CTL_B;
2348 GMCH_DP_C : constant Registers_Index := DDI_BUF_CTL_C;
2349 GMCH_DP_D : constant Registers_Index := DDI_BUF_CTL_D;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2350 DP_AUX_CTL_A : constant Registers_Index := DDI_AUX_CTL_A;
2351 DP_AUX_DATA_A_1 : constant Registers_Index := DDI_AUX_DATA_A_1;
2352 DP_AUX_DATA_A_2 : constant Registers_Index := DDI_AUX_DATA_A_2;
2353 DP_AUX_DATA_A_3 : constant Registers_Index := DDI_AUX_DATA_A_3;
2354 DP_AUX_DATA_A_4 : constant Registers_Index := DDI_AUX_DATA_A_4;
2355 DP_AUX_DATA_A_5 : constant Registers_Index := DDI_AUX_DATA_A_5;
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]2356 ILK_DISPLAY_CHICKEN1 : constant Registers_Index := FUSE_STATUS;
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]2357 GMCH_ADPA : constant Registers_Index := FDI_TX_CTL_B;
2358 GMCH_HDMIB : constant Registers_Index := GMCH_SDVOB;
2359 GMCH_HDMIC : constant Registers_Index := GMCH_SDVOC;
Nico Huber75a707f2018-06-18 16:28:33 +0200[diff] [blame]2360 CURACNTR : constant Registers_Index := CUR_CTL_A;
2361 CURABASE : constant Registers_Index := CUR_BASE_A;
2362 CURAPOS : constant Registers_Index := CUR_POS_A;
Nico Huberc6c07352020-10-01 15:02:00 +0200[diff] [blame]2363 SPACNTR : constant Registers_Index := PLANE_CTL_2_A;
2364 SPBCNTR : constant Registers_Index := PLANE_CTL_2_B;
2365 SPCCNTR : constant Registers_Index := PLANE_CTL_2_C;
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]2366 BXT_BLC_PWM_CTL_1 : constant Registers_Index := BLC_PWM_PCH_CTL1;
2367 BXT_BLC_PWM_FREQ_1 : constant Registers_Index := BLC_PWM_PCH_CTL2;
Tim Wawrzynczakb6df6832022-09-09 11:47:27 -0600[diff] [blame]2368 PHY_MISC_A : constant Registers_Index := BXT_PHY_CTL_A;
2369 PORT_COMP_DW0_B : constant Registers_Index := BXT_PORT_PLL_0_B;
2370 PORT_COMP_DW1_B : constant Registers_Index := BXT_PORT_PLL_1_B;
2371 PORT_COMP_DW3_B : constant Registers_Index := BXT_PORT_PLL_3_B;
2372 PORT_COMP_DW0_A : constant Registers_Index := BXT_PORT_PLL_0_A;
2373 PORT_COMP_DW1_A : constant Registers_Index := BXT_PORT_PLL_1_A;
2374 PORT_COMP_DW3_A : constant Registers_Index := BXT_PORT_PLL_3_A;
2375 PORT_COMP_DW9_A : constant Registers_Index := BXT_PORT_PLL_9_A;
2376 PORT_COMP_DW9_B : constant Registers_Index := BXT_PORT_PLL_9_B;
2377 PORT_COMP_DW8_A : constant Registers_Index := BXT_PORT_PLL_8_A;
2378 PORT_COMP_DW8_B : constant Registers_Index := BXT_PORT_PLL_8_B;
2379 PORT_COMP_DW10_A : constant Registers_Index := BXT_PORT_PLL_10_A;
2380 PORT_COMP_DW10_B : constant Registers_Index := BXT_PORT_PLL_10_B;
2381 CDCLK_PLL_ENABLE : constant Registers_Index := BXT_DE_PLL_ENABLE;
2382 DDI_AUX_CTL_USBC1 : constant Registers_Index := DDI_AUX_CTL_D;
2383 DDI_AUX_DATA_USBC1_1 : constant Registers_Index := DDI_AUX_DATA_D_1;
2384 DDI_AUX_DATA_USBC1_2 : constant Registers_Index := DDI_AUX_DATA_D_2;
2385 DDI_AUX_DATA_USBC1_3 : constant Registers_Index := DDI_AUX_DATA_D_3;
2386 DDI_AUX_DATA_USBC1_4 : constant Registers_Index := DDI_AUX_DATA_D_4;
2387 DDI_AUX_DATA_USBC1_5 : constant Registers_Index := DDI_AUX_DATA_D_5;
2388 DPLL_0_ENABLE : constant Registers_Index := LCPLL1_CTL;
2389 DPLL_1_ENABLE : constant Registers_Index := LCPLL2_CTL;
2390 PORT_CL_DW10_A : constant Registers_Index := BXT_PORT_CL1CM_DW10_A;
2391 PORT_CL_DW10_B : constant Registers_Index := BXT_PORT_CL1CM_DW10_BC;
2392 DDI_CLK_SEL_USBC1 : constant Registers_Index := PORT_CLK_SEL_DDID;
2393 DDI_CLK_SEL_USBC2 : constant Registers_Index := PORT_CLK_SEL_DDIE;
2394 MGPLL5_ENABLE : constant Registers_Index := WRPLL_CTL_1;
2395 DDI_BUF_CTL_USBC1 : constant Registers_Index := DDI_BUF_CTL_D;
2396 DDI_BUF_CTL_USBC2 : constant Registers_Index := DDI_BUF_CTL_E;
2397 DDI_BUF_CTL_USBC6 : constant Registers_Index := SRD_CTL;
2398 PORTTC1_PLL0_ENABLE : constant Registers_Index := MGPLL2_ENABLE;
2399 PORTTC1_PLL1_ENABLE : constant Registers_Index := MGPLL3_ENABLE;
2400 PORTTC2_PLL0_ENABLE : constant Registers_Index := MGPLL4_ENABLE;
2401 PORTTC2_PLL1_ENABLE : constant Registers_Index := WRPLL_CTL_1;
2402 PORTTC3_PLL0_ENABLE : constant Registers_Index := MGPLL6_ENABLE;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2403
2404 ---------------------------------------------------------------------------
2405
2406 Default_Timeout_MS : constant := 10;
2407
2408 ---------------------------------------------------------------------------
2409
2410 procedure Posting_Read
2411 (Register : in Registers_Index)
2412 with
2413 Global => (In_Out => Register_State),
2414 Depends => (Register_State =>+ (Register)),
2415 Pre => True,
2416 Post => True;
2417
2418 pragma Warnings (GNATprove, Off, "unused variable ""Verbose""",
2419 Reason => "Only used on debugging path");
2420 procedure Read
2421 (Register : in Registers_Index;
2422 Value : out Word32;
2423 Verbose : in Boolean := True)
2424 with
2425 Global => (In_Out => Register_State),
2426 Depends => ((Value, Register_State) => (Register, Register_State),
2427 null => Verbose),
2428 Pre => True,
2429 Post => True;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2430
2431 procedure Write
2432 (Register : Registers_Index;
Nico Huberaae8a352020-06-15 13:09:29 +0200[diff] [blame]2433 Value : Word32;
2434 Verbose : Boolean := True)
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2435 with
2436 Global => (In_Out => Register_State),
Nico Huberaae8a352020-06-15 13:09:29 +0200[diff] [blame]2437 Depends => (Register_State => (Register, Register_State, Value),
2438 null => Verbose),
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2439 Pre => True,
2440 Post => True;
Nico Huberaae8a352020-06-15 13:09:29 +0200[diff] [blame]2441 pragma Warnings (GNATprove, On, "unused variable ""Verbose""");
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2442
2443 procedure Is_Set_Mask
2444 (Register : in Registers_Index;
2445 Mask : in Word32;
2446 Result : out Boolean);
2447
2448 pragma Warnings (GNATprove, Off, "unused initial value of ""Verbose""",
2449 Reason => "Only used on debugging path");
Nico Huberbcb2c472017-02-02 16:39:26 +0100[diff] [blame]2450 procedure Wait
Nico Huber82ca09f2019-09-28 02:37:50 +0200[diff] [blame]2451 (Register : in Registers_Index;
2452 Mask : in Word32;
2453 Value : in Word32;
2454 TOut_MS : in Natural := Default_Timeout_MS;
2455 Verbose : in Boolean := False;
2456 Success : out Boolean);
2457 procedure Wait
Nico Huberbcb2c472017-02-02 16:39:26 +0100[diff] [blame]2458 (Register : Registers_Index;
2459 Mask : Word32;
2460 Value : Word32;
2461 TOut_MS : Natural := Default_Timeout_MS;
2462 Verbose : Boolean := False);
2463
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2464 procedure Wait_Set_Mask
Nico Huber82ca09f2019-09-28 02:37:50 +0200[diff] [blame]2465 (Register : in Registers_Index;
2466 Mask : in Word32;
2467 TOut_MS : in Natural := Default_Timeout_MS;
2468 Verbose : in Boolean := False;
2469 Success : out Boolean);
2470 procedure Wait_Set_Mask
2471 (Register : Registers_Index;
2472 Mask : Word32;
2473 TOut_MS : Natural := Default_Timeout_MS;
2474 Verbose : Boolean := False);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2475
2476 procedure Wait_Unset_Mask
Nico Huber82ca09f2019-09-28 02:37:50 +0200[diff] [blame]2477 (Register : in Registers_Index;
2478 Mask : in Word32;
2479 TOut_MS : in Natural := Default_Timeout_MS;
2480 Verbose : in Boolean := False;
2481 Success : out Boolean);
2482 procedure Wait_Unset_Mask
2483 (Register : Registers_Index;
2484 Mask : Word32;
2485 TOut_MS : Natural := Default_Timeout_MS;
2486 Verbose : Boolean := False);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2487 pragma Warnings (GNATprove, On, "unused initial value of ""Verbose""");
2488
2489 procedure Set_Mask
2490 (Register : Registers_Index;
2491 Mask : Word32);
2492
2493 procedure Unset_Mask
2494 (Register : Registers_Index;
2495 Mask : Word32);
2496
2497 procedure Unset_And_Set_Mask
2498 (Register : Registers_Index;
2499 Mask_Unset : Word32;
2500 Mask_Set : Word32);
2501
Nico Huber17d64b62017-07-15 20:51:25 +0200[diff] [blame]2502 procedure Clear_Fences;
2503
Nico Huberb03c8f12017-08-25 13:29:08 +0200[diff] [blame]2504 procedure Add_Fence
2505 (First_Page : in GTT_Range;
2506 Last_Page : in GTT_Range;
2507 Tiling : in XY_Tiling;
2508 Pitch : in Natural;
Arthur Heymans960e2392026-03-03 19:45:24 +0100[diff] [blame]2509 Success : out Boolean)
2510 with
2511 Pre => Last_Page >= First_Page;
Nico Huberb03c8f12017-08-25 13:29:08 +0200[diff] [blame]2512
2513 procedure Remove_Fence (First_Page, Last_Page : GTT_Range);
2514
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]2515 pragma Warnings (GNATprove, Off, "no check message justified by this",
2516 Reason => "see Annotate aspects.");
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2517 procedure Write_GTT
2518 (GTT_Page : GTT_Range;
2519 Device_Address : GTT_Address_Type;
2520 Valid : Boolean)
2521 with
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]2522 Global =>
2523 (Input => Config.Variable,
2524 In_Out => GTT_State),
2525 Depends =>
2526 (GTT_State =>+ (Config.Variable, GTT_Page, Device_Address, Valid)),
2527 Annotate =>
2528 (GNATprove, Intentional,
Nico Hubere317e9c2019-09-29 03:03:18 +0200[diff] [blame]2529 """GMA.State"" of ""Write_GTT"" not read",
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]2530 "Reading of Config_State depends on the platform configuration.");
Nico Huberceda17d2018-06-09 22:00:29 +0200[diff] [blame]2531
2532 procedure Read_GTT
2533 (Device_Address : out GTT_Address_Type;
2534 Valid : out Boolean;
2535 GTT_Page : in GTT_Range)
2536 with
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]2537 Global =>
2538 (Input => Config.Variable,
2539 In_Out => GTT_State),
2540 Depends =>
2541 ((Device_Address, Valid, GTT_State) =>
2542 (Config.Variable, GTT_State, GTT_Page)),
2543 Annotate =>
2544 (GNATprove, Intentional,
Nico Hubere317e9c2019-09-29 03:03:18 +0200[diff] [blame]2545 """GMA.State"" of ""Read_GTT"" not read",
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]2546 "Reading of Config_State depends on the platform configuration.");
2547 pragma Warnings (GNATprove, On, "no check message justified by this");
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2548
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]2549 procedure Set_Register_Base (Base : Word64; GTT_Base : Word64 := 0)
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2550 with
2551 Global => (Output => Address_State),
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]2552 Depends => (Address_State => (Base, GTT_Base)),
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]2553 Pre => True,
2554 Post => True;
2555
2556end HW.GFX.GMA.Registers;