Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1 | /* |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 2 | * This file is part of the flashrom project. |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 3 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 4 | * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de> |
| 5 | * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de> |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 6 | * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be> |
Carl-Daniel Hailfinger | 9224262 | 2007-09-27 14:29:57 +0000 | [diff] [blame] | 7 | * Copyright (C) 2007 Carl-Daniel Hailfinger |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 8 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; version 2 of the License. |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 12 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 21 | */ |
| 22 | |
| 23 | /* |
| 24 | * Contains the board specific flash enables. |
| 25 | */ |
| 26 | |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 27 | #include <string.h> |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 28 | #include "flash.h" |
Carl-Daniel Hailfinger | 5b997c3 | 2010-07-27 22:41:39 +0000 | [diff] [blame] | 29 | #include "programmer.h" |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 30 | |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 31 | #if defined(__i386__) || defined(__x86_64__) |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 32 | /* |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 33 | * Helper functions for many Winbond Super I/Os of the W836xx range. |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 34 | */ |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 35 | /* Enter extended functions */ |
Peter Stuge | 9d9399c | 2009-01-26 02:34:51 +0000 | [diff] [blame] | 36 | void w836xx_ext_enter(uint16_t port) |
Mondrian Nuessle | aef1c7c | 2007-05-03 10:09:23 +0000 | [diff] [blame] | 37 | { |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 38 | OUTB(0x87, port); |
| 39 | OUTB(0x87, port); |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 40 | } |
Mondrian Nuessle | aef1c7c | 2007-05-03 10:09:23 +0000 | [diff] [blame] | 41 | |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 42 | /* Leave extended functions */ |
Peter Stuge | 9d9399c | 2009-01-26 02:34:51 +0000 | [diff] [blame] | 43 | void w836xx_ext_leave(uint16_t port) |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 44 | { |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 45 | OUTB(0xAA, port); |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 46 | } |
Mondrian Nuessle | aef1c7c | 2007-05-03 10:09:23 +0000 | [diff] [blame] | 47 | |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 48 | /* Generic Super I/O helper functions */ |
| 49 | uint8_t sio_read(uint16_t port, uint8_t reg) |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 50 | { |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 51 | OUTB(reg, port); |
| 52 | return INB(port + 1); |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 53 | } |
Mondrian Nuessle | aef1c7c | 2007-05-03 10:09:23 +0000 | [diff] [blame] | 54 | |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 55 | void sio_write(uint16_t port, uint8_t reg, uint8_t data) |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 56 | { |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 57 | OUTB(reg, port); |
| 58 | OUTB(data, port + 1); |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 59 | } |
Mondrian Nuessle | aef1c7c | 2007-05-03 10:09:23 +0000 | [diff] [blame] | 60 | |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 61 | void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask) |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 62 | { |
Ronald G. Minnich | fa49692 | 2007-10-12 21:22:40 +0000 | [diff] [blame] | 63 | uint8_t tmp; |
Mondrian Nuessle | aef1c7c | 2007-05-03 10:09:23 +0000 | [diff] [blame] | 64 | |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 65 | OUTB(reg, port); |
| 66 | tmp = INB(port + 1) & ~mask; |
| 67 | OUTB(tmp | (data & mask), port + 1); |
Mondrian Nuessle | aef1c7c | 2007-05-03 10:09:23 +0000 | [diff] [blame] | 68 | } |
| 69 | |
Carl-Daniel Hailfinger | 14e100c | 2009-12-22 23:42:04 +0000 | [diff] [blame] | 70 | /* Not used yet. */ |
| 71 | #if 0 |
| 72 | static int enable_flash_decode_superio(void) |
| 73 | { |
| 74 | int ret; |
| 75 | uint8_t tmp; |
| 76 | |
| 77 | switch (superio.vendor) { |
| 78 | case SUPERIO_VENDOR_NONE: |
| 79 | ret = -1; |
| 80 | break; |
| 81 | case SUPERIO_VENDOR_ITE: |
| 82 | enter_conf_mode_ite(superio.port); |
Uwe Hermann | 4395970 | 2010-03-13 17:28:29 +0000 | [diff] [blame] | 83 | /* Enable flash mapping. Works for most old ITE style Super I/O. */ |
Carl-Daniel Hailfinger | 14e100c | 2009-12-22 23:42:04 +0000 | [diff] [blame] | 84 | tmp = sio_read(superio.port, 0x24); |
| 85 | tmp |= 0xfc; |
| 86 | sio_write(superio.port, 0x24, tmp); |
| 87 | exit_conf_mode_ite(superio.port); |
| 88 | ret = 0; |
| 89 | break; |
| 90 | default: |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 91 | msg_pdbg("Unhandled Super I/O type!\n"); |
Carl-Daniel Hailfinger | 14e100c | 2009-12-22 23:42:04 +0000 | [diff] [blame] | 92 | ret = -1; |
| 93 | break; |
| 94 | } |
| 95 | return ret; |
| 96 | } |
| 97 | #endif |
| 98 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 99 | /* |
Michael Karcher | b3fe2fc | 2010-05-24 16:03:57 +0000 | [diff] [blame] | 100 | * SMSC FDC37B787: Raise GPIO50 |
| 101 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 102 | static int fdc37b787_gpio50_raise(uint16_t port) |
Michael Karcher | b3fe2fc | 2010-05-24 16:03:57 +0000 | [diff] [blame] | 103 | { |
| 104 | uint8_t id, val; |
| 105 | |
| 106 | OUTB(0x55, port); /* enter conf mode */ |
| 107 | id = sio_read(port, 0x20); |
| 108 | if (id != 0x44) { |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 109 | msg_perr("\nERROR: FDC37B787: Wrong ID 0x%02X.\n", id); |
Michael Karcher | b3fe2fc | 2010-05-24 16:03:57 +0000 | [diff] [blame] | 110 | OUTB(0xAA, port); /* leave conf mode */ |
| 111 | return -1; |
| 112 | } |
| 113 | |
| 114 | sio_write(port, 0x07, 0x08); /* Select Aux I/O subdevice */ |
| 115 | |
| 116 | val = sio_read(port, 0xC8); /* GP50 */ |
| 117 | if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */ |
| 118 | { |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 119 | msg_perr("\nERROR: GPIO50 mode 0x%02X unexpected.\n", val); |
Michael Karcher | b3fe2fc | 2010-05-24 16:03:57 +0000 | [diff] [blame] | 120 | OUTB(0xAA, port); |
| 121 | return -1; |
| 122 | } |
| 123 | |
| 124 | sio_mask(port, 0xF9, 0x01, 0x01); |
| 125 | |
| 126 | OUTB(0xAA, port); /* Leave conf mode */ |
| 127 | return 0; |
| 128 | } |
| 129 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 130 | /* |
| 131 | * Suited for: |
| 132 | * - Nokia IP530: Intel 440BX + PIIX4 + FDC37B787 |
Michael Karcher | b3fe2fc | 2010-05-24 16:03:57 +0000 | [diff] [blame] | 133 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 134 | static int fdc37b787_gpio50_raise_3f0(void) |
Michael Karcher | b3fe2fc | 2010-05-24 16:03:57 +0000 | [diff] [blame] | 135 | { |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 136 | return fdc37b787_gpio50_raise(0x3f0); |
Michael Karcher | b3fe2fc | 2010-05-24 16:03:57 +0000 | [diff] [blame] | 137 | } |
| 138 | |
Michael Karcher | bcd80cd | 2010-06-27 15:07:49 +0000 | [diff] [blame] | 139 | struct winbond_mux { |
| 140 | uint8_t reg; /* 0 if the corresponding pin is not muxed */ |
| 141 | uint8_t data; /* reg/data/mask may be directly ... */ |
| 142 | uint8_t mask; /* ... passed to sio_mask */ |
| 143 | }; |
| 144 | |
| 145 | struct winbond_port { |
| 146 | const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */ |
| 147 | uint8_t ldn; /* LDN this GPIO register is located in */ |
| 148 | uint8_t enable_bit; /* bit in 0x30 of that LDN to enable |
| 149 | the GPIO port */ |
| 150 | uint8_t base; /* base register in that LDN for the port */ |
| 151 | }; |
| 152 | |
| 153 | struct winbond_chip { |
| 154 | uint8_t device_id; /* reg 0x20 of the expected w83626x */ |
| 155 | uint8_t gpio_port_count; |
| 156 | const struct winbond_port *port; |
| 157 | }; |
| 158 | |
| 159 | |
| 160 | #define UNIMPLEMENTED_PORT {NULL, 0, 0, 0} |
| 161 | |
| 162 | enum winbond_id { |
| 163 | WINBOND_W83627HF_ID = 0x52, |
Michael Karcher | ea36c9c | 2010-06-27 15:07:52 +0000 | [diff] [blame] | 164 | WINBOND_W83627EHF_ID = 0x88, |
Michael Karcher | bcd80cd | 2010-06-27 15:07:49 +0000 | [diff] [blame] | 165 | WINBOND_W83627THF_ID = 0x82, |
| 166 | }; |
| 167 | |
| 168 | static const struct winbond_mux w83627hf_port2_mux[8] = { |
| 169 | {0x2A, 0x01, 0x01}, /* or MIDI */ |
| 170 | {0x2B, 0x80, 0x80}, /* or SPI */ |
| 171 | {0x2B, 0x40, 0x40}, /* or SPI */ |
| 172 | {0x2B, 0x20, 0x20}, /* or power LED */ |
| 173 | {0x2B, 0x10, 0x10}, /* or watchdog */ |
| 174 | {0x2B, 0x08, 0x08}, /* or infra red */ |
| 175 | {0x2B, 0x04, 0x04}, /* or infra red */ |
| 176 | {0x2B, 0x03, 0x03} /* or IRQ1 input */ |
| 177 | }; |
| 178 | |
| 179 | static const struct winbond_port w83627hf[3] = { |
| 180 | UNIMPLEMENTED_PORT, |
| 181 | {w83627hf_port2_mux, 0x08, 0, 0xF0}, |
| 182 | UNIMPLEMENTED_PORT |
| 183 | }; |
| 184 | |
Michael Karcher | ea36c9c | 2010-06-27 15:07:52 +0000 | [diff] [blame] | 185 | static const struct winbond_mux w83627ehf_port2_mux[8] = { |
| 186 | {0x29, 0x06, 0x02}, /* or MIDI */ |
| 187 | {0x29, 0x06, 0x02}, |
| 188 | {0x24, 0x02, 0x00}, /* or SPI ROM interface */ |
| 189 | {0x24, 0x02, 0x00}, |
| 190 | {0x2A, 0x01, 0x01}, /* or keyboard/mouse interface */ |
| 191 | {0x2A, 0x01, 0x01}, |
| 192 | {0x2A, 0x01, 0x01}, |
| 193 | {0x2A, 0x01, 0x01} |
| 194 | }; |
| 195 | |
| 196 | static const struct winbond_port w83627ehf[6] = { |
| 197 | UNIMPLEMENTED_PORT, |
| 198 | {w83627ehf_port2_mux, 0x09, 0, 0xE3}, |
| 199 | UNIMPLEMENTED_PORT, |
| 200 | UNIMPLEMENTED_PORT, |
| 201 | UNIMPLEMENTED_PORT, |
| 202 | UNIMPLEMENTED_PORT |
| 203 | }; |
| 204 | |
Michael Karcher | bcd80cd | 2010-06-27 15:07:49 +0000 | [diff] [blame] | 205 | static const struct winbond_mux w83627thf_port4_mux[8] = { |
| 206 | {0x2D, 0x01, 0x01}, /* or watchdog or VID level strap */ |
| 207 | {0x2D, 0x02, 0x02}, /* or resume reset */ |
| 208 | {0x2D, 0x04, 0x04}, /* or S3 input */ |
| 209 | {0x2D, 0x08, 0x08}, /* or PSON# */ |
| 210 | {0x2D, 0x10, 0x10}, /* or PWROK */ |
| 211 | {0x2D, 0x20, 0x20}, /* or suspend LED */ |
| 212 | {0x2D, 0x40, 0x40}, /* or panel switch input */ |
| 213 | {0x2D, 0x80, 0x80} /* or panel switch output */ |
| 214 | }; |
| 215 | |
| 216 | static const struct winbond_port w83627thf[5] = { |
| 217 | UNIMPLEMENTED_PORT, /* GPIO1 */ |
| 218 | UNIMPLEMENTED_PORT, /* GPIO2 */ |
| 219 | UNIMPLEMENTED_PORT, /* GPIO3 */ |
| 220 | {w83627thf_port4_mux, 0x09, 1, 0xF4}, |
| 221 | UNIMPLEMENTED_PORT /* GPIO5 */ |
| 222 | }; |
| 223 | |
| 224 | static const struct winbond_chip winbond_chips[] = { |
| 225 | {WINBOND_W83627HF_ID, ARRAY_SIZE(w83627hf), w83627hf }, |
Michael Karcher | ea36c9c | 2010-06-27 15:07:52 +0000 | [diff] [blame] | 226 | {WINBOND_W83627EHF_ID, ARRAY_SIZE(w83627ehf), w83627ehf}, |
Michael Karcher | bcd80cd | 2010-06-27 15:07:49 +0000 | [diff] [blame] | 227 | {WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf}, |
| 228 | }; |
| 229 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 230 | /* |
| 231 | * Detects which Winbond Super I/O is responding at the given base address, |
| 232 | * but takes no effort to make sure the chip is really a Winbond Super I/O. |
| 233 | */ |
| 234 | static const struct winbond_chip *winbond_superio_detect(uint16_t base) |
Michael Karcher | bcd80cd | 2010-06-27 15:07:49 +0000 | [diff] [blame] | 235 | { |
| 236 | uint8_t chipid; |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 237 | const struct winbond_chip *chip = NULL; |
Michael Karcher | bcd80cd | 2010-06-27 15:07:49 +0000 | [diff] [blame] | 238 | int i; |
| 239 | |
| 240 | w836xx_ext_enter(base); |
| 241 | chipid = sio_read(base, 0x20); |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 242 | |
| 243 | for (i = 0; i < ARRAY_SIZE(winbond_chips); i++) { |
| 244 | if (winbond_chips[i].device_id == chipid) { |
Michael Karcher | bcd80cd | 2010-06-27 15:07:49 +0000 | [diff] [blame] | 245 | chip = &winbond_chips[i]; |
| 246 | break; |
| 247 | } |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 248 | } |
| 249 | |
Michael Karcher | bcd80cd | 2010-06-27 15:07:49 +0000 | [diff] [blame] | 250 | w836xx_ext_leave(base); |
| 251 | return chip; |
| 252 | } |
| 253 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 254 | /* |
| 255 | * The chipid parameter goes away as soon as we have Super I/O matching in the |
| 256 | * board enable table. The call to winbond_superio_detect() goes away as |
| 257 | * soon as we have generic Super I/O detection code. |
| 258 | */ |
Michael Karcher | bcd80cd | 2010-06-27 15:07:49 +0000 | [diff] [blame] | 259 | static int winbond_gpio_set(uint16_t base, enum winbond_id chipid, |
| 260 | int pin, int raise) |
| 261 | { |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 262 | const struct winbond_chip *chip = NULL; |
| 263 | const struct winbond_port *gpio; |
Michael Karcher | bcd80cd | 2010-06-27 15:07:49 +0000 | [diff] [blame] | 264 | int port = pin / 10; |
| 265 | int bit = pin % 10; |
| 266 | |
| 267 | chip = winbond_superio_detect(base); |
| 268 | if (!chip) { |
| 269 | msg_perr("\nERROR: No supported Winbond Super I/O found\n"); |
| 270 | return -1; |
| 271 | } |
Michael Karcher | 979d925 | 2010-06-29 14:44:40 +0000 | [diff] [blame] | 272 | if (chip->device_id != chipid) { |
| 273 | msg_perr("\nERROR: Found Winbond chip with ID 0x%x, " |
| 274 | "expected %x\n", chip->device_id, chipid); |
| 275 | return -1; |
| 276 | } |
Michael Karcher | bcd80cd | 2010-06-27 15:07:49 +0000 | [diff] [blame] | 277 | if (bit >= 8 || port == 0 || port > chip->gpio_port_count) { |
| 278 | msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n", |
| 279 | pin); |
| 280 | return -1; |
| 281 | } |
| 282 | |
| 283 | gpio = &chip->port[port - 1]; |
| 284 | |
| 285 | if (gpio->ldn == 0) { |
| 286 | msg_perr("\nERROR: GPIO%d is not supported yet on this" |
| 287 | " winbond chip\n", port); |
| 288 | return -1; |
| 289 | } |
| 290 | |
| 291 | w836xx_ext_enter(base); |
| 292 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 293 | /* Select logical device. */ |
Michael Karcher | bcd80cd | 2010-06-27 15:07:49 +0000 | [diff] [blame] | 294 | sio_write(base, 0x07, gpio->ldn); |
| 295 | |
| 296 | /* Activate logical device. */ |
| 297 | sio_mask(base, 0x30, 1 << gpio->enable_bit, 1 << gpio->enable_bit); |
| 298 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 299 | /* Select GPIO function of that pin. */ |
Michael Karcher | bcd80cd | 2010-06-27 15:07:49 +0000 | [diff] [blame] | 300 | if (gpio->mux && gpio->mux[bit].reg) |
| 301 | sio_mask(base, gpio->mux[bit].reg, |
| 302 | gpio->mux[bit].data, gpio->mux[bit].mask); |
| 303 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 304 | sio_mask(base, gpio->base + 0, 0, 1 << bit); /* Make pin output */ |
Michael Karcher | bcd80cd | 2010-06-27 15:07:49 +0000 | [diff] [blame] | 305 | sio_mask(base, gpio->base + 2, 0, 1 << bit); /* Clear inversion */ |
| 306 | sio_mask(base, gpio->base + 1, raise << bit, 1 << bit); |
| 307 | |
| 308 | w836xx_ext_leave(base); |
| 309 | |
| 310 | return 0; |
| 311 | } |
| 312 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 313 | /* |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 314 | * Winbond W83627HF: Raise GPIO24. |
Luc Verhaegen | 7977f4e | 2007-05-04 04:47:04 +0000 | [diff] [blame] | 315 | * |
| 316 | * Suited for: |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 317 | * - Agami Aruma |
| 318 | * - IWILL DK8-HTX |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 319 | */ |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 320 | static int w83627hf_gpio24_raise_2e(void) |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 321 | { |
Michael Karcher | bcd80cd | 2010-06-27 15:07:49 +0000 | [diff] [blame] | 322 | return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1); |
Ronald G. Minnich | fa49692 | 2007-10-12 21:22:40 +0000 | [diff] [blame] | 323 | } |
| 324 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 325 | /* |
Joshua Roys | f280a38 | 2010-08-07 21:49:11 +0000 | [diff] [blame] | 326 | * Winbond W83627HF: Raise GPIO25. |
| 327 | * |
| 328 | * Suited for: |
| 329 | * - MSI MS-6577 |
| 330 | */ |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 331 | static int w83627hf_gpio25_raise_2e(void) |
Joshua Roys | f280a38 | 2010-08-07 21:49:11 +0000 | [diff] [blame] | 332 | { |
| 333 | return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 25, 1); |
| 334 | } |
| 335 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 336 | /* |
Michael Karcher | ea36c9c | 2010-06-27 15:07:52 +0000 | [diff] [blame] | 337 | * Winbond W83627EHF: Raise GPIO24. |
| 338 | * |
| 339 | * Suited for: |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 340 | * - ASUS A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51 |
Michael Karcher | ea36c9c | 2010-06-27 15:07:52 +0000 | [diff] [blame] | 341 | */ |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 342 | static int w83627ehf_gpio24_raise_2e(void) |
Michael Karcher | ea36c9c | 2010-06-27 15:07:52 +0000 | [diff] [blame] | 343 | { |
| 344 | return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 24, 1); |
| 345 | } |
| 346 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 347 | /* |
Michael Karcher | bcd80cd | 2010-06-27 15:07:49 +0000 | [diff] [blame] | 348 | * Winbond W83627THF: Raise GPIO 44. |
Ronald G. Minnich | fa49692 | 2007-10-12 21:22:40 +0000 | [diff] [blame] | 349 | * |
| 350 | * Suited for: |
Peter Stuge | cce2682 | 2008-07-21 17:48:40 +0000 | [diff] [blame] | 351 | * - MSI K8T Neo2-F |
Ronald G. Minnich | fa49692 | 2007-10-12 21:22:40 +0000 | [diff] [blame] | 352 | */ |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 353 | static int w83627thf_gpio44_raise_2e(void) |
Ronald G. Minnich | fa49692 | 2007-10-12 21:22:40 +0000 | [diff] [blame] | 354 | { |
Michael Karcher | bcd80cd | 2010-06-27 15:07:49 +0000 | [diff] [blame] | 355 | return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1); |
Ronald G. Minnich | fa49692 | 2007-10-12 21:22:40 +0000 | [diff] [blame] | 356 | } |
| 357 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 358 | /* |
Michael Karcher | bcd80cd | 2010-06-27 15:07:49 +0000 | [diff] [blame] | 359 | * Winbond W83627THF: Raise GPIO 44. |
| 360 | * |
| 361 | * Suited for: |
| 362 | * - MSI K8N Neo3 |
| 363 | */ |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 364 | static int w83627thf_gpio44_raise_4e(void) |
Peter Stuge | cce2682 | 2008-07-21 17:48:40 +0000 | [diff] [blame] | 365 | { |
Michael Karcher | bcd80cd | 2010-06-27 15:07:49 +0000 | [diff] [blame] | 366 | return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1); |
Ronald G. Minnich | fa49692 | 2007-10-12 21:22:40 +0000 | [diff] [blame] | 367 | } |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 368 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 369 | /* |
David Borg | b6417a6 | 2010-08-02 08:29:34 +0000 | [diff] [blame] | 370 | * Enable MEMW# and set ROM size to max. |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 371 | * Supported chips: W83L517D, W83697HF/F/HG, W83697SF/UF/UG |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 372 | */ |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 373 | static void w836xx_memw_enable(uint16_t port) |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 374 | { |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 375 | w836xx_ext_enter(port); |
| 376 | if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */ |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 377 | /* Enable MEMW# and set ROM size select to max. (4M). */ |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 378 | sio_mask(port, 0x24, 0x28, 0x28); |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 379 | } |
Carl-Daniel Hailfinger | 24c1a16 | 2009-05-25 23:26:50 +0000 | [diff] [blame] | 380 | w836xx_ext_leave(port); |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 381 | } |
| 382 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 383 | /* |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 384 | * Suited for: |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 385 | * - EPoX EP-8K5A2: VIA KT333 + VT8235 |
| 386 | * - Albatron PM266A Pro: VIA P4M266A + VT8235 |
| 387 | * - Shuttle AK31 (all versions): VIA KT266 + VT8233 |
| 388 | * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235 |
| 389 | * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237 |
Mattias Mattsson | e295eee | 2010-08-15 10:21:29 +0000 | [diff] [blame] | 390 | * - MSI KM4M-V and KM4AM-V: VIA KM400/KM400A + VT8237 |
Mattias Mattsson | e838824 | 2010-09-11 15:25:48 +0000 | [diff] [blame] | 391 | * - MSI MS-6561 (745 Ultra): SiS 745 + W83697HF |
Sergey A Lichack | f3a4bff | 2010-09-07 18:14:53 +0000 | [diff] [blame] | 392 | * - MSI MS-6787 (P4MAM-V/P4MAM-L): VIA P4M266 + VT8235 |
Uwe Hermann | 17da61e | 2010-10-05 21:48:43 +0000 | [diff] [blame] | 393 | * - ASRock K7S41: SiS 741 + SiS 963 + W83697HF |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 394 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 395 | static int w836xx_memw_enable_2e(void) |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 396 | { |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 397 | w836xx_memw_enable(0x2E); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 398 | |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 399 | return 0; |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 400 | } |
| 401 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 402 | /* |
Daniel Brandt | 4ad4c74 | 2010-03-21 13:36:20 +0000 | [diff] [blame] | 403 | * Suited for: |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 404 | * - Termtek TK-3370 (rev. 2.5b) |
Daniel Brandt | 4ad4c74 | 2010-03-21 13:36:20 +0000 | [diff] [blame] | 405 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 406 | static int w836xx_memw_enable_4e(void) |
Daniel Brandt | 4ad4c74 | 2010-03-21 13:36:20 +0000 | [diff] [blame] | 407 | { |
| 408 | w836xx_memw_enable(0x4E); |
| 409 | |
| 410 | return 0; |
| 411 | } |
| 412 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 413 | /* |
Carl-Daniel Hailfinger | 76d4b37 | 2010-07-10 16:56:32 +0000 | [diff] [blame] | 414 | * Suited for all boards with ITE IT8705F. |
| 415 | * The SIS950 Super I/O probably requires a similar flash write enable. |
Luc Verhaegen | 21f5496 | 2010-01-20 14:45:07 +0000 | [diff] [blame] | 416 | */ |
Carl-Daniel Hailfinger | 76d4b37 | 2010-07-10 16:56:32 +0000 | [diff] [blame] | 417 | int it8705f_write_enable(uint8_t port) |
Luc Verhaegen | 21f5496 | 2010-01-20 14:45:07 +0000 | [diff] [blame] | 418 | { |
Carl-Daniel Hailfinger | 76d4b37 | 2010-07-10 16:56:32 +0000 | [diff] [blame] | 419 | uint8_t tmp; |
| 420 | int ret = 0; |
| 421 | |
Luc Verhaegen | 21f5496 | 2010-01-20 14:45:07 +0000 | [diff] [blame] | 422 | enter_conf_mode_ite(port); |
Carl-Daniel Hailfinger | 76d4b37 | 2010-07-10 16:56:32 +0000 | [diff] [blame] | 423 | tmp = sio_read(port, 0x24); |
| 424 | /* Check if at least one flash segment is enabled. */ |
| 425 | if (tmp & 0xf0) { |
| 426 | /* The IT8705F will respond to LPC cycles and translate them. */ |
| 427 | buses_supported = CHIP_BUSTYPE_PARALLEL; |
| 428 | /* Flash ROM I/F Writes Enable */ |
| 429 | tmp |= 0x04; |
| 430 | msg_pdbg("Enabling IT8705F flash ROM interface write.\n"); |
| 431 | if (tmp & 0x02) { |
| 432 | /* The data sheet contradicts itself about max size. */ |
| 433 | max_rom_decode.parallel = 1024 * 1024; |
| 434 | msg_pinfo("IT8705F with very unusual settings. Please " |
| 435 | "send the output of \"flashrom -V\" to \n" |
Paul Menzel | ab6328f | 2010-10-08 11:03:02 +0000 | [diff] [blame] | 436 | "flashrom@flashrom.org with " |
| 437 | "IT8705: your board name: flashrom -V\n" |
| 438 | "as the subject to help us finish " |
Carl-Daniel Hailfinger | 76d4b37 | 2010-07-10 16:56:32 +0000 | [diff] [blame] | 439 | "support for your Super I/O. Thanks.\n"); |
| 440 | ret = 1; |
| 441 | } else if (tmp & 0x08) { |
| 442 | max_rom_decode.parallel = 512 * 1024; |
| 443 | } else { |
| 444 | max_rom_decode.parallel = 256 * 1024; |
| 445 | } |
| 446 | /* Safety checks. The data sheet is unclear here: Segments 1+3 |
| 447 | * overlap, no segment seems to cover top - 1MB to top - 512kB. |
| 448 | * We assume that certain combinations make no sense. |
| 449 | */ |
| 450 | if (((tmp & 0x02) && !(tmp & 0x08)) || /* 1 MB en, 512 kB dis */ |
| 451 | (!(tmp & 0x10)) || /* 128 kB dis */ |
| 452 | (!(tmp & 0x40))) { /* 256/512 kB dis */ |
| 453 | msg_perr("Inconsistent IT8705F decode size!\n"); |
| 454 | ret = 1; |
| 455 | } |
| 456 | if (sio_read(port, 0x25) != 0) { |
| 457 | msg_perr("IT8705F flash data pins disabled!\n"); |
| 458 | ret = 1; |
| 459 | } |
| 460 | if (sio_read(port, 0x26) != 0) { |
| 461 | msg_perr("IT8705F flash address pins 0-7 disabled!\n"); |
| 462 | ret = 1; |
| 463 | } |
| 464 | if (sio_read(port, 0x27) != 0) { |
| 465 | msg_perr("IT8705F flash address pins 8-15 disabled!\n"); |
| 466 | ret = 1; |
| 467 | } |
| 468 | if ((sio_read(port, 0x29) & 0x10) != 0) { |
| 469 | msg_perr("IT8705F flash write enable pin disabled!\n"); |
| 470 | ret = 1; |
| 471 | } |
| 472 | if ((sio_read(port, 0x29) & 0x08) != 0) { |
| 473 | msg_perr("IT8705F flash chip select pin disabled!\n"); |
| 474 | ret = 1; |
| 475 | } |
| 476 | if ((sio_read(port, 0x29) & 0x04) != 0) { |
| 477 | msg_perr("IT8705F flash read strobe pin disabled!\n"); |
| 478 | ret = 1; |
| 479 | } |
| 480 | if ((sio_read(port, 0x29) & 0x03) != 0) { |
| 481 | msg_perr("IT8705F flash address pins 16-17 disabled!\n"); |
| 482 | /* Not really an error if you use flash chips smaller |
| 483 | * than 256 kByte, but such a configuration is unlikely. |
| 484 | */ |
| 485 | ret = 1; |
| 486 | } |
| 487 | msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n", |
| 488 | max_rom_decode.parallel); |
| 489 | if (ret) { |
| 490 | msg_pinfo("Not enabling IT8705F flash write.\n"); |
| 491 | } else { |
| 492 | sio_write(port, 0x24, tmp); |
| 493 | } |
| 494 | } else { |
| 495 | msg_pdbg("No IT8705F flash segment enabled.\n"); |
| 496 | /* Not sure if this is an error or not. */ |
| 497 | ret = 0; |
| 498 | } |
Luc Verhaegen | 21f5496 | 2010-01-20 14:45:07 +0000 | [diff] [blame] | 499 | exit_conf_mode_ite(port); |
| 500 | |
Carl-Daniel Hailfinger | 76d4b37 | 2010-07-10 16:56:32 +0000 | [diff] [blame] | 501 | return ret; |
Luc Verhaegen | 21f5496 | 2010-01-20 14:45:07 +0000 | [diff] [blame] | 502 | } |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 503 | |
Mattias Mattsson | fb60cec | 2010-09-13 19:39:25 +0000 | [diff] [blame] | 504 | /* |
| 505 | * The ITE IT8707F is a custom chip made by ITE exclusively for ASUS. |
| 506 | * It uses the Winbond command sequence to enter extended configuration |
| 507 | * mode and the ITE sequence to exit. |
| 508 | * |
| 509 | * Registers seems similar to the ones on ITE IT8710F. |
| 510 | */ |
| 511 | static int it8707f_write_enable(uint8_t port) |
| 512 | { |
| 513 | uint8_t tmp; |
| 514 | |
| 515 | w836xx_ext_enter(port); |
| 516 | |
| 517 | /* Set bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A rw */ |
| 518 | tmp = sio_read(port, 0x23); |
| 519 | tmp |= (1 << 3); |
| 520 | sio_write(port, 0x23, tmp); |
| 521 | |
| 522 | /* Set bit 2 (FLASH_WE) and bit 3 (FLASH_IF_EN) of reg 0x24 */ |
| 523 | tmp = sio_read(port, 0x24); |
| 524 | tmp |= (1 << 2) | (1 << 3); |
| 525 | sio_write(port, 0x24, tmp); |
| 526 | |
| 527 | /* Clear bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A ro */ |
| 528 | tmp = sio_read(port, 0x23); |
| 529 | tmp &= ~(1 << 3); |
| 530 | sio_write(port, 0x23, tmp); |
| 531 | |
| 532 | exit_conf_mode_ite(port); |
| 533 | |
| 534 | return 0; |
| 535 | } |
| 536 | |
| 537 | /* |
| 538 | * Suited for: |
| 539 | * - ASUS P4SC-E: SiS 651 + 962 + ITE IT8707F |
| 540 | */ |
| 541 | static int it8707f_write_enable_2e(void) |
| 542 | { |
| 543 | return it8707f_write_enable(0x2e); |
| 544 | } |
| 545 | |
Michael Karcher | cba52de | 2011-03-06 12:07:19 +0000 | [diff] [blame] | 546 | #define PC87360_ID 0xE1 |
| 547 | #define PC87364_ID 0xE4 |
| 548 | |
| 549 | static int pc8736x_gpio_set(uint8_t chipid, uint8_t gpio, int raise) |
Michael Karcher | 5fbd18d | 2010-02-27 18:35:54 +0000 | [diff] [blame] | 550 | { |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 551 | static const int bankbase[] = {0, 4, 8, 10, 12}; |
| 552 | int gpio_bank = gpio / 8; |
| 553 | int gpio_pin = gpio % 8; |
| 554 | uint16_t baseport; |
| 555 | uint8_t id, val; |
Michael Karcher | 5fbd18d | 2010-02-27 18:35:54 +0000 | [diff] [blame] | 556 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 557 | if (gpio_bank > 4) { |
Michael Karcher | cba52de | 2011-03-06 12:07:19 +0000 | [diff] [blame] | 558 | msg_perr("PC8736x: Invalid GPIO %d\n", gpio); |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 559 | return -1; |
| 560 | } |
Michael Karcher | 5fbd18d | 2010-02-27 18:35:54 +0000 | [diff] [blame] | 561 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 562 | id = sio_read(0x2E, 0x20); |
Michael Karcher | cba52de | 2011-03-06 12:07:19 +0000 | [diff] [blame] | 563 | if (id != chipid) { |
| 564 | msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n", id, chipid); |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 565 | return -1; |
| 566 | } |
Michael Karcher | 5fbd18d | 2010-02-27 18:35:54 +0000 | [diff] [blame] | 567 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 568 | sio_write(0x2E, 0x07, 0x07); /* Select GPIO device. */ |
| 569 | baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61); |
| 570 | if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) { |
| 571 | msg_perr("PC87360: invalid GPIO base address %04x\n", |
| 572 | baseport); |
| 573 | return -1; |
| 574 | } |
| 575 | sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device. */ |
| 576 | sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin); |
| 577 | sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output. */ |
Michael Karcher | 5fbd18d | 2010-02-27 18:35:54 +0000 | [diff] [blame] | 578 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 579 | val = INB(baseport + bankbase[gpio_bank]); |
| 580 | if (raise) |
| 581 | val |= 1 << gpio_pin; |
| 582 | else |
| 583 | val &= ~(1 << gpio_pin); |
| 584 | OUTB(val, baseport + bankbase[gpio_bank]); |
Michael Karcher | 5fbd18d | 2010-02-27 18:35:54 +0000 | [diff] [blame] | 585 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 586 | return 0; |
Michael Karcher | 5fbd18d | 2010-02-27 18:35:54 +0000 | [diff] [blame] | 587 | } |
| 588 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 589 | /* |
| 590 | * VIA VT823x: Set one of the GPIO pins. |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 591 | */ |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 592 | static int via_vt823x_gpio_set(uint8_t gpio, int raise) |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 593 | { |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 594 | struct pci_dev *dev; |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 595 | uint16_t base; |
David Bartley | f58d364 | 2009-12-09 07:53:01 +0000 | [diff] [blame] | 596 | uint8_t val, bit, offset; |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 597 | |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 598 | dev = pci_dev_find_vendorclass(0x1106, 0x0601); |
| 599 | switch (dev->device_id) { |
| 600 | case 0x3177: /* VT8235 */ |
| 601 | case 0x3227: /* VT8237R */ |
| 602 | case 0x3337: /* VT8237A */ |
| 603 | break; |
| 604 | default: |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 605 | msg_perr("\nERROR: VT823x ISA bridge not found.\n"); |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 606 | return -1; |
| 607 | } |
| 608 | |
Jon Harrison | 2eeff4e | 2009-06-19 13:53:59 +0000 | [diff] [blame] | 609 | if ((gpio >= 12) && (gpio <= 15)) { |
| 610 | /* GPIO12-15 -> output */ |
| 611 | val = pci_read_byte(dev, 0xE4); |
| 612 | val |= 0x10; |
| 613 | pci_write_byte(dev, 0xE4, val); |
| 614 | } else if (gpio == 9) { |
| 615 | /* GPIO9 -> Output */ |
| 616 | val = pci_read_byte(dev, 0xE4); |
| 617 | val |= 0x20; |
| 618 | pci_write_byte(dev, 0xE4, val); |
David Bartley | f58d364 | 2009-12-09 07:53:01 +0000 | [diff] [blame] | 619 | } else if (gpio == 5) { |
| 620 | val = pci_read_byte(dev, 0xE4); |
| 621 | val |= 0x01; |
| 622 | pci_write_byte(dev, 0xE4, val); |
Jon Harrison | 2eeff4e | 2009-06-19 13:53:59 +0000 | [diff] [blame] | 623 | } else { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 624 | msg_perr("\nERROR: " |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 625 | "VT823x GPIO%02d is not implemented.\n", gpio); |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 626 | return -1; |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 627 | } |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 628 | |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 629 | /* We need the I/O Base Address for this board's flash enable. */ |
| 630 | base = pci_read_word(dev, 0x88) & 0xff80; |
| 631 | |
David Bartley | f58d364 | 2009-12-09 07:53:01 +0000 | [diff] [blame] | 632 | offset = 0x4C + gpio / 8; |
| 633 | bit = 0x01 << (gpio % 8); |
| 634 | |
| 635 | val = INB(base + offset); |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 636 | if (raise) |
| 637 | val |= bit; |
| 638 | else |
| 639 | val &= ~bit; |
David Bartley | f58d364 | 2009-12-09 07:53:01 +0000 | [diff] [blame] | 640 | OUTB(val, base + offset); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 641 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 642 | return 0; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 643 | } |
| 644 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 645 | /* |
| 646 | * Suited for: |
| 647 | * - ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 648 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 649 | static int via_vt823x_gpio5_raise(void) |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 650 | { |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 651 | /* On M2V-MX: GPO5 is connected to WP# and TBL#. */ |
| 652 | return via_vt823x_gpio_set(5, 1); |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 653 | } |
| 654 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 655 | /* |
| 656 | * Suited for: |
| 657 | * - VIA EPIA EK & N & NL |
Jon Harrison | 2eeff4e | 2009-06-19 13:53:59 +0000 | [diff] [blame] | 658 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 659 | static int via_vt823x_gpio9_raise(void) |
Jon Harrison | 2eeff4e | 2009-06-19 13:53:59 +0000 | [diff] [blame] | 660 | { |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 661 | return via_vt823x_gpio_set(9, 1); |
Jon Harrison | 2eeff4e | 2009-06-19 13:53:59 +0000 | [diff] [blame] | 662 | } |
| 663 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 664 | /* |
| 665 | * Suited for: |
| 666 | * - VIA EPIA M and MII (and maybe other CLE266 based EPIAs) |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 667 | * |
| 668 | * We don't need to do this for EPIA M when using coreboot, GPIO15 is never |
| 669 | * lowered there. |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 670 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 671 | static int via_vt823x_gpio15_raise(void) |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 672 | { |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 673 | return via_vt823x_gpio_set(15, 1); |
| 674 | } |
| 675 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 676 | /* |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 677 | * Winbond W83697HF Super I/O + VIA VT8235 southbridge |
| 678 | * |
| 679 | * Suited for: |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 680 | * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235 |
| 681 | * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235 |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 682 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 683 | static int board_msi_kt4v(void) |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 684 | { |
| 685 | int ret; |
| 686 | |
| 687 | ret = via_vt823x_gpio_set(12, 1); |
Luc Verhaegen | add6d9b | 2009-05-09 14:26:04 +0000 | [diff] [blame] | 688 | w836xx_memw_enable(0x2E); |
Luc Verhaegen | 9786608 | 2008-02-09 02:03:06 +0000 | [diff] [blame] | 689 | |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 690 | return ret; |
Luc Verhaegen | 9786608 | 2008-02-09 02:03:06 +0000 | [diff] [blame] | 691 | } |
| 692 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 693 | /* |
| 694 | * Suited for: |
| 695 | * - ASUS P5A |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 696 | * |
| 697 | * This is rather nasty code, but there's no way to do this cleanly. |
| 698 | * We're basically talking to some unknown device on SMBus, my guess |
| 699 | * is that it is the Winbond W83781D that lives near the DIP BIOS. |
| 700 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 701 | static int board_asus_p5a(void) |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 702 | { |
| 703 | uint8_t tmp; |
| 704 | int i; |
| 705 | |
| 706 | #define ASUSP5A_LOOP 5000 |
| 707 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 708 | OUTB(0x00, 0xE807); |
| 709 | OUTB(0xEF, 0xE803); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 710 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 711 | OUTB(0xFF, 0xE800); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 712 | |
| 713 | for (i = 0; i < ASUSP5A_LOOP; i++) { |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 714 | OUTB(0xE1, 0xFF); |
| 715 | if (INB(0xE800) & 0x04) |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 716 | break; |
| 717 | } |
| 718 | |
| 719 | if (i == ASUSP5A_LOOP) { |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 720 | msg_perr("Unable to contact device.\n"); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 721 | return -1; |
| 722 | } |
| 723 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 724 | OUTB(0x20, 0xE801); |
| 725 | OUTB(0x20, 0xE1); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 726 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 727 | OUTB(0xFF, 0xE802); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 728 | |
| 729 | for (i = 0; i < ASUSP5A_LOOP; i++) { |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 730 | tmp = INB(0xE800); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 731 | if (tmp & 0x70) |
| 732 | break; |
| 733 | } |
| 734 | |
| 735 | if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) { |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 736 | msg_perr("Failed to read device.\n"); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 737 | return -1; |
| 738 | } |
| 739 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 740 | tmp = INB(0xE804); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 741 | tmp &= ~0x02; |
| 742 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 743 | OUTB(0x00, 0xE807); |
| 744 | OUTB(0xEE, 0xE803); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 745 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 746 | OUTB(tmp, 0xE804); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 747 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 748 | OUTB(0xFF, 0xE800); |
| 749 | OUTB(0xE1, 0xFF); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 750 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 751 | OUTB(0x20, 0xE801); |
| 752 | OUTB(0x20, 0xE1); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 753 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 754 | OUTB(0xFF, 0xE802); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 755 | |
| 756 | for (i = 0; i < ASUSP5A_LOOP; i++) { |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 757 | tmp = INB(0xE800); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 758 | if (tmp & 0x70) |
| 759 | break; |
| 760 | } |
| 761 | |
| 762 | if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) { |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 763 | msg_perr("Failed to write to device.\n"); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 764 | return -1; |
| 765 | } |
| 766 | |
| 767 | return 0; |
| 768 | } |
| 769 | |
Luc Verhaegen | a7e3050 | 2009-12-09 11:39:02 +0000 | [diff] [blame] | 770 | /* |
| 771 | * Set GPIO lines in the Broadcom HT-1000 southbridge. |
| 772 | * |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 773 | * It's not a Super I/O but it uses the same index/data port method. |
Luc Verhaegen | a7e3050 | 2009-12-09 11:39:02 +0000 | [diff] [blame] | 774 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 775 | static int board_hp_dl145_g3_enable(void) |
Luc Verhaegen | a7e3050 | 2009-12-09 11:39:02 +0000 | [diff] [blame] | 776 | { |
| 777 | /* GPIO 0 reg from PM regs */ |
| 778 | /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */ |
| 779 | sio_mask(0xcd6, 0x44, 0x24, 0x24); |
| 780 | |
| 781 | return 0; |
| 782 | } |
| 783 | |
Arne Georg Gleditsch | b0bd386 | 2010-07-01 11:16:28 +0000 | [diff] [blame] | 784 | /* |
| 785 | * Set GPIO lines in the Broadcom HT-1000 southbridge. |
| 786 | * |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 787 | * It's not a Super I/O but it uses the same index/data port method. |
Arne Georg Gleditsch | b0bd386 | 2010-07-01 11:16:28 +0000 | [diff] [blame] | 788 | */ |
| 789 | static int board_hp_dl165_g6_enable(void) |
| 790 | { |
| 791 | /* Variant of DL145, with slightly different pin placement. */ |
| 792 | sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */ |
| 793 | sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */ |
| 794 | |
| 795 | return 0; |
| 796 | } |
| 797 | |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 798 | static int board_ibm_x3455(void) |
Stefan Reinauer | 1c283f4 | 2007-06-05 12:51:52 +0000 | [diff] [blame] | 799 | { |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 800 | /* Raise GPIO13. */ |
Carl-Daniel Hailfinger | 500b423 | 2009-06-01 21:30:42 +0000 | [diff] [blame] | 801 | sio_mask(0xcd6, 0x45, 0x20, 0x20); |
Stefan Reinauer | 1c283f4 | 2007-06-05 12:51:52 +0000 | [diff] [blame] | 802 | |
| 803 | return 0; |
| 804 | } |
| 805 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 806 | /* |
| 807 | * Suited for: |
| 808 | * - Shuttle FN25 (SN25P): AMD S939 + NVIDIA CK804 (nForce4) |
Luc Verhaegen | 20fdce1 | 2009-10-21 12:05:50 +0000 | [diff] [blame] | 809 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 810 | static int board_shuttle_fn25(void) |
Luc Verhaegen | 20fdce1 | 2009-10-21 12:05:50 +0000 | [diff] [blame] | 811 | { |
| 812 | struct pci_dev *dev; |
| 813 | |
| 814 | dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA Bridge. */ |
| 815 | if (!dev) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 816 | msg_perr("\nERROR: NVIDIA nForce4 ISA bridge not found.\n"); |
Luc Verhaegen | 20fdce1 | 2009-10-21 12:05:50 +0000 | [diff] [blame] | 817 | return -1; |
| 818 | } |
| 819 | |
| 820 | /* one of those bits seems to be connected to TBL#, but -ENOINFO. */ |
| 821 | pci_write_byte(dev, 0x92, 0); |
| 822 | |
| 823 | return 0; |
| 824 | } |
| 825 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 826 | /* |
Mattias Mattsson | f492516 | 2010-09-16 22:09:18 +0000 | [diff] [blame] | 827 | * Suited for: |
| 828 | * - Elitegroup GeForce6100SM-M: NVIDIA MCP61 + ITE IT8726F |
| 829 | */ |
Mattias Mattsson | f492516 | 2010-09-16 22:09:18 +0000 | [diff] [blame] | 830 | static int board_ecs_geforce6100sm_m(void) |
| 831 | { |
| 832 | struct pci_dev *dev; |
| 833 | uint32_t tmp; |
| 834 | |
| 835 | dev = pci_dev_find(0x10DE, 0x03EB); /* NVIDIA MCP61 SMBus. */ |
| 836 | if (!dev) { |
| 837 | msg_perr("\nERROR: NVIDIA MCP61 SMBus not found.\n"); |
| 838 | return -1; |
| 839 | } |
| 840 | |
| 841 | tmp = pci_read_byte(dev, 0xE0); |
| 842 | tmp &= ~(1 << 3); |
| 843 | pci_write_byte(dev, 0xE0, tmp); |
| 844 | |
| 845 | return 0; |
| 846 | } |
| 847 | |
| 848 | /* |
Luc Verhaegen | 96f88fb | 2009-12-03 12:25:34 +0000 | [diff] [blame] | 849 | * Very similar to AMD 8111 IO Hub. |
Luc Verhaegen | 8ff741e | 2009-10-05 16:07:00 +0000 | [diff] [blame] | 850 | */ |
Luc Verhaegen | 96f88fb | 2009-12-03 12:25:34 +0000 | [diff] [blame] | 851 | static int nvidia_mcp_gpio_set(int gpio, int raise) |
Luc Verhaegen | 8ff741e | 2009-10-05 16:07:00 +0000 | [diff] [blame] | 852 | { |
Luc Verhaegen | 96f88fb | 2009-12-03 12:25:34 +0000 | [diff] [blame] | 853 | struct pci_dev *dev; |
Luc Verhaegen | 8ff741e | 2009-10-05 16:07:00 +0000 | [diff] [blame] | 854 | uint16_t base; |
Michael Karcher | 2ead2e2 | 2010-06-01 16:09:06 +0000 | [diff] [blame] | 855 | uint16_t devclass; |
Luc Verhaegen | 8ff741e | 2009-10-05 16:07:00 +0000 | [diff] [blame] | 856 | uint8_t tmp; |
| 857 | |
Luc Verhaegen | 23ebd75 | 2009-12-22 13:04:13 +0000 | [diff] [blame] | 858 | if ((gpio < 0) || (gpio >= 0x40)) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 859 | msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio); |
Luc Verhaegen | 48f34c6 | 2009-06-03 07:50:39 +0000 | [diff] [blame] | 860 | return -1; |
| 861 | } |
| 862 | |
Luc Verhaegen | 23ebd75 | 2009-12-22 13:04:13 +0000 | [diff] [blame] | 863 | /* First, check the ISA Bridge */ |
| 864 | dev = pci_dev_find_vendorclass(0x10DE, 0x0601); |
Luc Verhaegen | 96f88fb | 2009-12-03 12:25:34 +0000 | [diff] [blame] | 865 | switch (dev->device_id) { |
| 866 | case 0x0030: /* CK804 */ |
| 867 | case 0x0050: /* MCP04 */ |
| 868 | case 0x0060: /* MCP2 */ |
Michael Karcher | 5f31ebe | 2010-06-12 23:07:26 +0000 | [diff] [blame] | 869 | case 0x00E0: /* CK8 */ |
Luc Verhaegen | 96f88fb | 2009-12-03 12:25:34 +0000 | [diff] [blame] | 870 | break; |
Michael Karcher | 2ead2e2 | 2010-06-01 16:09:06 +0000 | [diff] [blame] | 871 | case 0x0260: /* MCP51 */ |
Michael Karcher | 242efd4 | 2011-03-06 12:09:05 +0000 | [diff] [blame] | 872 | case 0x0261: /* MCP51 */ |
Michael Karcher | 2ead2e2 | 2010-06-01 16:09:06 +0000 | [diff] [blame] | 873 | case 0x0364: /* MCP55 */ |
| 874 | /* find SMBus controller on *this* southbridge */ |
| 875 | /* The infamous Tyan S2915-E has two south bridges; they are |
| 876 | easily told apart from each other by the class of the |
| 877 | LPC bridge, but have the same SMBus bridge IDs */ |
| 878 | if (dev->func != 0) { |
| 879 | msg_perr("MCP LPC bridge at unexpected function" |
| 880 | " number %d\n", dev->func); |
| 881 | return -1; |
| 882 | } |
| 883 | |
Carl-Daniel Hailfinger | 44cd9ab | 2010-07-17 22:28:05 +0000 | [diff] [blame] | 884 | #if PCI_LIB_VERSION >= 0x020200 |
Michael Karcher | 2ead2e2 | 2010-06-01 16:09:06 +0000 | [diff] [blame] | 885 | dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1); |
Carl-Daniel Hailfinger | 44cd9ab | 2010-07-17 22:28:05 +0000 | [diff] [blame] | 886 | #else |
| 887 | /* pciutils/libpci before version 2.2 is too old to support |
| 888 | * PCI domains. Such old machines usually don't have domains |
| 889 | * besides domain 0, so this is not a problem. |
| 890 | */ |
| 891 | dev = pci_get_dev(pacc, dev->bus, dev->dev, 1); |
| 892 | #endif |
Michael Karcher | 2ead2e2 | 2010-06-01 16:09:06 +0000 | [diff] [blame] | 893 | if (!dev) { |
| 894 | msg_perr("MCP SMBus controller could not be found\n"); |
| 895 | return -1; |
| 896 | } |
| 897 | devclass = pci_read_word(dev, PCI_CLASS_DEVICE); |
| 898 | if (devclass != 0x0C05) { |
| 899 | msg_perr("Unexpected device class %04x for SMBus" |
| 900 | " controller\n", devclass); |
| 901 | return -1; |
| 902 | } |
Luc Verhaegen | 23ebd75 | 2009-12-22 13:04:13 +0000 | [diff] [blame] | 903 | break; |
Michael Karcher | 2ead2e2 | 2010-06-01 16:09:06 +0000 | [diff] [blame] | 904 | default: |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 905 | msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n"); |
Luc Verhaegen | 96f88fb | 2009-12-03 12:25:34 +0000 | [diff] [blame] | 906 | return -1; |
| 907 | } |
| 908 | |
| 909 | base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */ |
| 910 | base += 0xC0; |
| 911 | |
| 912 | tmp = INB(base + gpio); |
| 913 | tmp &= ~0x0F; /* null lower nibble */ |
| 914 | tmp |= 0x04; /* gpio -> output. */ |
| 915 | if (raise) |
| 916 | tmp |= 0x01; |
| 917 | OUTB(tmp, base + gpio); |
Luc Verhaegen | 48f34c6 | 2009-06-03 07:50:39 +0000 | [diff] [blame] | 918 | |
| 919 | return 0; |
| 920 | } |
| 921 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 922 | /* |
| 923 | * Suited for: |
Sean Nelson | 0a24751 | 2010-08-15 14:36:18 +0000 | [diff] [blame] | 924 | * - ASUS A8N-LA (HP OEM "Nagami-GL8E"): NVIDIA MCP51 |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 925 | * - ASUS M2NBP-VM CSM: NVIDIA MCP51 |
Michael Karcher | b2184c1 | 2010-03-07 16:42:55 +0000 | [diff] [blame] | 926 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 927 | static int nvidia_mcp_gpio0_raise(void) |
Michael Karcher | b2184c1 | 2010-03-07 16:42:55 +0000 | [diff] [blame] | 928 | { |
| 929 | return nvidia_mcp_gpio_set(0x00, 1); |
| 930 | } |
| 931 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 932 | /* |
| 933 | * Suited for: |
| 934 | * - abit KN8 Ultra: NVIDIA CK804 |
Sean Nelson | 92bc6bd | 2010-03-19 22:37:29 +0000 | [diff] [blame] | 935 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 936 | static int nvidia_mcp_gpio2_lower(void) |
Sean Nelson | 92bc6bd | 2010-03-19 22:37:29 +0000 | [diff] [blame] | 937 | { |
| 938 | return nvidia_mcp_gpio_set(0x02, 0); |
| 939 | } |
| 940 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 941 | /* |
| 942 | * Suited for: |
Uwe Hermann | ead705f | 2010-08-15 15:26:30 +0000 | [diff] [blame] | 943 | * - MSI K8N Neo4: NVIDIA CK804. TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html. |
| 944 | * - MSI K8NGM2-L: NVIDIA MCP51 |
Luc Verhaegen | 6c5f733 | 2009-12-23 03:01:36 +0000 | [diff] [blame] | 945 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 946 | static int nvidia_mcp_gpio2_raise(void) |
Luc Verhaegen | 6c5f733 | 2009-12-23 03:01:36 +0000 | [diff] [blame] | 947 | { |
| 948 | return nvidia_mcp_gpio_set(0x02, 1); |
| 949 | } |
| 950 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 951 | /* |
| 952 | * Suited for: |
Uwe Hermann | 83d349a | 2010-10-18 22:32:03 +0000 | [diff] [blame] | 953 | * - EPoX EP-8NPA7I: Socket 754 + NVIDIA nForce4 4X |
Jonathan Kollasch | f8db959 | 2010-10-15 23:02:15 +0000 | [diff] [blame] | 954 | */ |
| 955 | static int nvidia_mcp_gpio4_raise(void) |
| 956 | { |
| 957 | return nvidia_mcp_gpio_set(0x04, 1); |
| 958 | } |
| 959 | |
| 960 | /* |
| 961 | * Suited for: |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 962 | * - HP xw9400 (Tyan S2915-E OEM): Dual(!) NVIDIA MCP55 |
| 963 | * |
| 964 | * Notes: a) There are two MCP55 chips, so also two SMBus bridges on that |
| 965 | * board. We can't tell the SMBus logical devices apart, but we |
| 966 | * can tell the LPC bridge functions apart. |
| 967 | * We need to choose the SMBus bridge next to the LPC bridge with |
| 968 | * ID 0x364 and the "LPC bridge" class. |
| 969 | * b) #TBL is hardwired on that board to a pull-down. It can be |
| 970 | * overridden by connecting the two solder points next to F2. |
Michael Karcher | 2ead2e2 | 2010-06-01 16:09:06 +0000 | [diff] [blame] | 971 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 972 | static int nvidia_mcp_gpio5_raise(void) |
Michael Karcher | 2ead2e2 | 2010-06-01 16:09:06 +0000 | [diff] [blame] | 973 | { |
| 974 | return nvidia_mcp_gpio_set(0x05, 1); |
| 975 | } |
| 976 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 977 | /* |
| 978 | * Suited for: |
| 979 | * - abit NF7-S: NVIDIA CK804 |
Michael Karcher | 8f10d24 | 2010-04-11 21:01:06 +0000 | [diff] [blame] | 980 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 981 | static int nvidia_mcp_gpio8_raise(void) |
Michael Karcher | 8f10d24 | 2010-04-11 21:01:06 +0000 | [diff] [blame] | 982 | { |
| 983 | return nvidia_mcp_gpio_set(0x08, 1); |
| 984 | } |
| 985 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 986 | /* |
| 987 | * Suited for: |
| 988 | * - MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + CK8 |
Michael Karcher | 5f31ebe | 2010-06-12 23:07:26 +0000 | [diff] [blame] | 989 | */ |
Michael Karcher | 5182508 | 2010-06-12 23:14:03 +0000 | [diff] [blame] | 990 | static int nvidia_mcp_gpio0c_raise(void) |
Michael Karcher | 5f31ebe | 2010-06-12 23:07:26 +0000 | [diff] [blame] | 991 | { |
| 992 | return nvidia_mcp_gpio_set(0x0c, 1); |
| 993 | } |
| 994 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 995 | /* |
| 996 | * Suited for: |
| 997 | * - abit NF-M2 nView: Socket AM2 + NVIDIA MCP51 |
Michael Karcher | efd8af3 | 2010-07-24 22:50:54 +0000 | [diff] [blame] | 998 | */ |
| 999 | static int nvidia_mcp_gpio4_lower(void) |
| 1000 | { |
| 1001 | return nvidia_mcp_gpio_set(0x04, 0); |
| 1002 | } |
| 1003 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1004 | /* |
| 1005 | * Suited for: |
| 1006 | * - ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04 |
Luc Verhaegen | 8ff741e | 2009-10-05 16:07:00 +0000 | [diff] [blame] | 1007 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 1008 | static int nvidia_mcp_gpio10_raise(void) |
Luc Verhaegen | 8ff741e | 2009-10-05 16:07:00 +0000 | [diff] [blame] | 1009 | { |
Luc Verhaegen | 96f88fb | 2009-12-03 12:25:34 +0000 | [diff] [blame] | 1010 | return nvidia_mcp_gpio_set(0x10, 1); |
| 1011 | } |
Luc Verhaegen | 8ff741e | 2009-10-05 16:07:00 +0000 | [diff] [blame] | 1012 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1013 | /* |
| 1014 | * Suited for: |
| 1015 | * - GIGABYTE GA-K8N-SLI: AMD socket 939 + NVIDIA CK804 + ITE IT8712F |
Luc Verhaegen | 96f88fb | 2009-12-03 12:25:34 +0000 | [diff] [blame] | 1016 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 1017 | static int nvidia_mcp_gpio21_raise(void) |
Luc Verhaegen | 96f88fb | 2009-12-03 12:25:34 +0000 | [diff] [blame] | 1018 | { |
| 1019 | return nvidia_mcp_gpio_set(0x21, 0x01); |
Luc Verhaegen | 8ff741e | 2009-10-05 16:07:00 +0000 | [diff] [blame] | 1020 | } |
| 1021 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1022 | /* |
| 1023 | * Suited for: |
| 1024 | * - EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2 |
Luc Verhaegen | 2c04fab | 2009-10-05 18:46:35 +0000 | [diff] [blame] | 1025 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 1026 | static int nvidia_mcp_gpio31_raise(void) |
Luc Verhaegen | 2c04fab | 2009-10-05 18:46:35 +0000 | [diff] [blame] | 1027 | { |
Luc Verhaegen | 96f88fb | 2009-12-03 12:25:34 +0000 | [diff] [blame] | 1028 | return nvidia_mcp_gpio_set(0x31, 0x01); |
Luc Verhaegen | 2c04fab | 2009-10-05 18:46:35 +0000 | [diff] [blame] | 1029 | } |
Luc Verhaegen | 8ff741e | 2009-10-05 16:07:00 +0000 | [diff] [blame] | 1030 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1031 | /* |
| 1032 | * Suited for: |
Michael Karcher | 242efd4 | 2011-03-06 12:09:05 +0000 | [diff] [blame] | 1033 | * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51 |
| 1034 | * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51 |
Joshua Roys | 2ee137f | 2010-09-07 17:52:09 +0000 | [diff] [blame] | 1035 | */ |
| 1036 | static int nvidia_mcp_gpio3b_raise(void) |
| 1037 | { |
| 1038 | return nvidia_mcp_gpio_set(0x3b, 1); |
| 1039 | } |
| 1040 | |
| 1041 | /* |
| 1042 | * Suited for: |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1043 | * - Artec Group DBE61 and DBE62 |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 1044 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 1045 | static int board_artecgroup_dbe6x(void) |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 1046 | { |
| 1047 | #define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015 |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1048 | #define DBE6x_PRI_BOOT_LOC_SHIFT 2 |
| 1049 | #define DBE6x_BOOT_OP_LATCHED_SHIFT 8 |
| 1050 | #define DBE6x_SEC_BOOT_LOC_SHIFT 10 |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 1051 | #define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT) |
| 1052 | #define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT) |
| 1053 | #define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT) |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1054 | #define DBE6x_BOOT_LOC_FLASH 2 |
| 1055 | #define DBE6x_BOOT_LOC_FWHUB 3 |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 1056 | |
Stefan Reinauer | b4fe664 | 2009-08-12 18:25:24 +0000 | [diff] [blame] | 1057 | msr_t msr; |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 1058 | unsigned long boot_loc; |
| 1059 | |
Stefan Reinauer | b4fe664 | 2009-08-12 18:25:24 +0000 | [diff] [blame] | 1060 | /* Geode only has a single core */ |
| 1061 | if (setup_cpu_msr(0)) |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 1062 | return -1; |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 1063 | |
Stefan Reinauer | b4fe664 | 2009-08-12 18:25:24 +0000 | [diff] [blame] | 1064 | msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS); |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 1065 | |
Stefan Reinauer | b4fe664 | 2009-08-12 18:25:24 +0000 | [diff] [blame] | 1066 | if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) == |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 1067 | (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT)) |
| 1068 | boot_loc = DBE6x_BOOT_LOC_FWHUB; |
| 1069 | else |
| 1070 | boot_loc = DBE6x_BOOT_LOC_FLASH; |
| 1071 | |
Stefan Reinauer | b4fe664 | 2009-08-12 18:25:24 +0000 | [diff] [blame] | 1072 | msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC); |
| 1073 | msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 1074 | (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT)); |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 1075 | |
Stefan Reinauer | b4fe664 | 2009-08-12 18:25:24 +0000 | [diff] [blame] | 1076 | wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr); |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 1077 | |
Stefan Reinauer | b4fe664 | 2009-08-12 18:25:24 +0000 | [diff] [blame] | 1078 | cleanup_cpu_msr(); |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 1079 | |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 1080 | return 0; |
| 1081 | } |
| 1082 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1083 | /* |
Uwe Hermann | 4e3d0b3 | 2010-03-25 23:18:41 +0000 | [diff] [blame] | 1084 | * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}. |
Luc Verhaegen | f522691 | 2009-12-14 10:41:58 +0000 | [diff] [blame] | 1085 | */ |
| 1086 | static int intel_piix4_gpo_set(unsigned int gpo, int raise) |
| 1087 | { |
Michael Karcher | 01f6d7d | 2010-02-24 00:00:21 +0000 | [diff] [blame] | 1088 | unsigned int gpo_byte, gpo_bit; |
Luc Verhaegen | f522691 | 2009-12-14 10:41:58 +0000 | [diff] [blame] | 1089 | struct pci_dev *dev; |
| 1090 | uint32_t tmp, base; |
| 1091 | |
Mattias Mattsson | d7ed7f7 | 2010-08-15 22:35:31 +0000 | [diff] [blame] | 1092 | static const uint32_t nonmuxed_gpos = 0x58000101; /* GPPO {0,8,27,28,30} are always available */ |
| 1093 | |
| 1094 | static const struct {unsigned int reg, mask, value; } piix4_gpo[] = { |
| 1095 | {0}, |
| 1096 | {0xB0, 0x0001, 0x0000}, /* GPO1... */ |
| 1097 | {0xB0, 0x0001, 0x0000}, |
| 1098 | {0xB0, 0x0001, 0x0000}, |
| 1099 | {0xB0, 0x0001, 0x0000}, |
| 1100 | {0xB0, 0x0001, 0x0000}, |
| 1101 | {0xB0, 0x0001, 0x0000}, |
| 1102 | {0xB0, 0x0001, 0x0000}, /* ...GPO7: GENCFG bit 0 */ |
| 1103 | {0}, |
| 1104 | {0xB0, 0x0100, 0x0000}, /* GPO9: GENCFG bit 8 */ |
| 1105 | {0xB0, 0x0200, 0x0000}, /* GPO10: GENCFG bit 9 */ |
| 1106 | {0xB0, 0x0400, 0x0000}, /* GPO11: GENCFG bit 10 */ |
| 1107 | {0x4E, 0x0100, 0x0000}, /* GPO12... */ |
| 1108 | {0x4E, 0x0100, 0x0000}, |
| 1109 | {0x4E, 0x0100, 0x0000}, /* ...GPO14: XBCS bit 8 */ |
| 1110 | {0xB2, 0x0002, 0x0002}, /* GPO15... */ |
| 1111 | {0xB2, 0x0002, 0x0002}, /* ...GPO16: GENCFG bit 17 */ |
| 1112 | {0xB2, 0x0004, 0x0004}, /* GPO17: GENCFG bit 18 */ |
| 1113 | {0xB2, 0x0008, 0x0008}, /* GPO18: GENCFG bit 19 */ |
| 1114 | {0xB2, 0x0010, 0x0010}, /* GPO19: GENCFG bit 20 */ |
| 1115 | {0xB2, 0x0020, 0x0020}, /* GPO20: GENCFG bit 21 */ |
| 1116 | {0xB2, 0x0040, 0x0040}, /* GPO21: GENCFG bit 22 */ |
| 1117 | {0xB2, 0x1000, 0x1000}, /* GPO22... */ |
| 1118 | {0xB2, 0x1000, 0x1000}, /* ...GPO23: GENCFG bit 28 */ |
| 1119 | {0xB2, 0x2000, 0x2000}, /* GPO24: GENCFG bit 29 */ |
| 1120 | {0xB2, 0x4000, 0x4000}, /* GPO25: GENCFG bit 30 */ |
| 1121 | {0xB2, 0x8000, 0x8000}, /* GPO26: GENCFG bit 31 */ |
| 1122 | {0}, |
| 1123 | {0}, |
| 1124 | {0x4E, 0x0100, 0x0000}, /* ...GPO29: XBCS bit 8 */ |
| 1125 | {0} |
| 1126 | }; |
| 1127 | |
| 1128 | |
Luc Verhaegen | f522691 | 2009-12-14 10:41:58 +0000 | [diff] [blame] | 1129 | dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */ |
| 1130 | if (!dev) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1131 | msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n"); |
Luc Verhaegen | f522691 | 2009-12-14 10:41:58 +0000 | [diff] [blame] | 1132 | return -1; |
| 1133 | } |
| 1134 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1135 | /* Sanity check. */ |
Luc Verhaegen | f522691 | 2009-12-14 10:41:58 +0000 | [diff] [blame] | 1136 | if (gpo > 30) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1137 | msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo); |
Luc Verhaegen | f522691 | 2009-12-14 10:41:58 +0000 | [diff] [blame] | 1138 | return -1; |
| 1139 | } |
| 1140 | |
Mattias Mattsson | d7ed7f7 | 2010-08-15 22:35:31 +0000 | [diff] [blame] | 1141 | if ( (((1 << gpo) & nonmuxed_gpos) == 0) && |
| 1142 | (pci_read_word(dev, piix4_gpo[gpo].reg) & piix4_gpo[gpo].mask) != piix4_gpo[gpo].value ) { |
Peter Huewe | 3d3fd6a | 2011-01-25 00:23:32 +0000 | [diff] [blame] | 1143 | msg_perr("\nERROR: PIIX4 GPO%d not programmed for output.\n", gpo); |
Mattias Mattsson | d7ed7f7 | 2010-08-15 22:35:31 +0000 | [diff] [blame] | 1144 | return -1; |
Luc Verhaegen | f522691 | 2009-12-14 10:41:58 +0000 | [diff] [blame] | 1145 | } |
| 1146 | |
Luc Verhaegen | f522691 | 2009-12-14 10:41:58 +0000 | [diff] [blame] | 1147 | dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */ |
| 1148 | if (!dev) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1149 | msg_perr("\nERROR: Intel PIIX4 PM not found.\n"); |
Luc Verhaegen | f522691 | 2009-12-14 10:41:58 +0000 | [diff] [blame] | 1150 | return -1; |
| 1151 | } |
| 1152 | |
| 1153 | /* PM IO base */ |
| 1154 | base = pci_read_long(dev, 0x40) & 0x0000FFC0; |
| 1155 | |
Michael Karcher | 01f6d7d | 2010-02-24 00:00:21 +0000 | [diff] [blame] | 1156 | gpo_byte = gpo >> 3; |
| 1157 | gpo_bit = gpo & 7; |
| 1158 | tmp = INB(base + 0x34 + gpo_byte); /* GPO register */ |
Luc Verhaegen | f522691 | 2009-12-14 10:41:58 +0000 | [diff] [blame] | 1159 | if (raise) |
Michael Karcher | 01f6d7d | 2010-02-24 00:00:21 +0000 | [diff] [blame] | 1160 | tmp |= 0x01 << gpo_bit; |
Luc Verhaegen | f522691 | 2009-12-14 10:41:58 +0000 | [diff] [blame] | 1161 | else |
Michael Karcher | 01f6d7d | 2010-02-24 00:00:21 +0000 | [diff] [blame] | 1162 | tmp &= ~(0x01 << gpo_bit); |
| 1163 | OUTB(tmp, base + 0x34 + gpo_byte); |
Luc Verhaegen | f522691 | 2009-12-14 10:41:58 +0000 | [diff] [blame] | 1164 | |
| 1165 | return 0; |
| 1166 | } |
| 1167 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1168 | /* |
| 1169 | * Suited for: |
Mattias Mattsson | 85016b9 | 2010-09-01 01:21:34 +0000 | [diff] [blame] | 1170 | * - ASUS P2B-N |
| 1171 | */ |
| 1172 | static int intel_piix4_gpo18_lower(void) |
| 1173 | { |
| 1174 | return intel_piix4_gpo_set(18, 0); |
| 1175 | } |
| 1176 | |
| 1177 | /* |
| 1178 | * Suited for: |
Mattias Mattsson | c8ca3de | 2010-09-13 18:22:36 +0000 | [diff] [blame] | 1179 | * - MSI MS-6163 v2 (MS-6163 Pro): Intel 440BX + PIIX4E + Winbond W83977EF |
| 1180 | */ |
| 1181 | static int intel_piix4_gpo14_raise(void) |
| 1182 | { |
| 1183 | return intel_piix4_gpo_set(14, 1); |
| 1184 | } |
| 1185 | |
| 1186 | /* |
| 1187 | * Suited for: |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1188 | * - EPoX EP-BX3 |
Luc Verhaegen | f522691 | 2009-12-14 10:41:58 +0000 | [diff] [blame] | 1189 | */ |
Mattias Mattsson | d7ed7f7 | 2010-08-15 22:35:31 +0000 | [diff] [blame] | 1190 | static int intel_piix4_gpo22_raise(void) |
Luc Verhaegen | f522691 | 2009-12-14 10:41:58 +0000 | [diff] [blame] | 1191 | { |
| 1192 | return intel_piix4_gpo_set(22, 1); |
| 1193 | } |
| 1194 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1195 | /* |
| 1196 | * Suited for: |
Tim ter Laak | 4b933f0 | 2010-09-13 23:00:57 +0000 | [diff] [blame] | 1197 | * - abit BM6 |
| 1198 | */ |
| 1199 | static int intel_piix4_gpo26_lower(void) |
| 1200 | { |
| 1201 | return intel_piix4_gpo_set(26, 0); |
| 1202 | } |
| 1203 | |
| 1204 | /* |
| 1205 | * Suited for: |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1206 | * - Intel SE440BX-2 |
Michael Karcher | 51cd0c9 | 2010-03-19 22:35:21 +0000 | [diff] [blame] | 1207 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 1208 | static int intel_piix4_gpo27_lower(void) |
Michael Karcher | 51cd0c9 | 2010-03-19 22:35:21 +0000 | [diff] [blame] | 1209 | { |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1210 | return intel_piix4_gpo_set(27, 0); |
Michael Karcher | 51cd0c9 | 2010-03-19 22:35:21 +0000 | [diff] [blame] | 1211 | } |
| 1212 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1213 | /* |
Mattias Mattsson | 2eaad63 | 2010-10-05 21:32:29 +0000 | [diff] [blame] | 1214 | * Suited for: |
| 1215 | * - Dell OptiPlex GX1 |
| 1216 | */ |
| 1217 | static int intel_piix4_gpo30_lower(void) |
| 1218 | { |
| 1219 | return intel_piix4_gpo_set(30, 0); |
| 1220 | } |
| 1221 | |
| 1222 | /* |
Uwe Hermann | 4e3d0b3 | 2010-03-25 23:18:41 +0000 | [diff] [blame] | 1223 | * Set a GPIO line on a given Intel ICH LPC controller. |
Uwe Hermann | 93f66db | 2008-05-22 21:19:38 +0000 | [diff] [blame] | 1224 | */ |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1225 | static int intel_ich_gpio_set(int gpio, int raise) |
Uwe Hermann | 93f66db | 2008-05-22 21:19:38 +0000 | [diff] [blame] | 1226 | { |
Uwe Hermann | 4e3d0b3 | 2010-03-25 23:18:41 +0000 | [diff] [blame] | 1227 | /* Table mapping the different Intel ICH LPC chipsets. */ |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1228 | static struct { |
| 1229 | uint16_t id; |
| 1230 | uint8_t base_reg; |
| 1231 | uint32_t bank0; |
| 1232 | uint32_t bank1; |
| 1233 | uint32_t bank2; |
| 1234 | } intel_ich_gpio_table[] = { |
| 1235 | {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */ |
| 1236 | {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */ |
| 1237 | {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */ |
| 1238 | {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */ |
| 1239 | {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */ |
| 1240 | {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */ |
| 1241 | {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */ |
| 1242 | {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */ |
| 1243 | {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */ |
| 1244 | {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */ |
| 1245 | {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */ |
| 1246 | {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */ |
| 1247 | {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */ |
| 1248 | {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */ |
| 1249 | {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */ |
| 1250 | {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */ |
| 1251 | {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */ |
| 1252 | {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */ |
| 1253 | {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */ |
| 1254 | {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */ |
| 1255 | {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */ |
| 1256 | {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */ |
| 1257 | {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */ |
| 1258 | {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */ |
| 1259 | {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */ |
| 1260 | {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */ |
| 1261 | {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */ |
| 1262 | {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */ |
| 1263 | {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */ |
| 1264 | {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */ |
| 1265 | {0, 0, 0, 0, 0} /* end marker */ |
| 1266 | }; |
Uwe Hermann | 93f66db | 2008-05-22 21:19:38 +0000 | [diff] [blame] | 1267 | |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1268 | struct pci_dev *dev; |
| 1269 | uint16_t base; |
| 1270 | uint32_t tmp; |
| 1271 | int i, allowed; |
| 1272 | |
| 1273 | /* First, look for a known LPC bridge */ |
Jonathan A. Kollasch | b87f23b | 2009-12-14 04:24:42 +0000 | [diff] [blame] | 1274 | for (dev = pacc->devices; dev; dev = dev->next) { |
Carl-Daniel Hailfinger | d175e06 | 2010-05-21 23:00:56 +0000 | [diff] [blame] | 1275 | uint16_t device_class; |
| 1276 | /* libpci before version 2.2.4 does not store class info. */ |
| 1277 | device_class = pci_read_word(dev, PCI_CLASS_DEVICE); |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1278 | if ((dev->vendor_id == 0x8086) && |
Carl-Daniel Hailfinger | d175e06 | 2010-05-21 23:00:56 +0000 | [diff] [blame] | 1279 | (device_class == 0x0601)) { /* ISA Bridge */ |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1280 | /* Is this device in our list? */ |
| 1281 | for (i = 0; intel_ich_gpio_table[i].id; i++) |
| 1282 | if (dev->device_id == intel_ich_gpio_table[i].id) |
| 1283 | break; |
| 1284 | |
| 1285 | if (intel_ich_gpio_table[i].id) |
| 1286 | break; |
| 1287 | } |
Jonathan A. Kollasch | b87f23b | 2009-12-14 04:24:42 +0000 | [diff] [blame] | 1288 | } |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1289 | |
Uwe Hermann | 93f66db | 2008-05-22 21:19:38 +0000 | [diff] [blame] | 1290 | if (!dev) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1291 | msg_perr("\nERROR: No Known Intel LPC Bridge found.\n"); |
Uwe Hermann | 93f66db | 2008-05-22 21:19:38 +0000 | [diff] [blame] | 1292 | return -1; |
| 1293 | } |
| 1294 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1295 | /* |
| 1296 | * According to the datasheets, all Intel ICHs have the GPIO bar 5:1 |
| 1297 | * strapped to zero. From some mobile ICH9 version on, this becomes |
| 1298 | * 6:1. The mask below catches all. |
| 1299 | */ |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1300 | base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0; |
Uwe Hermann | 93f66db | 2008-05-22 21:19:38 +0000 | [diff] [blame] | 1301 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1302 | /* Check whether the line is allowed. */ |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1303 | if (gpio < 32) |
| 1304 | allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01; |
| 1305 | else if (gpio < 64) |
| 1306 | allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01; |
| 1307 | else |
| 1308 | allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01; |
| 1309 | |
| 1310 | if (!allowed) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1311 | msg_perr("\nERROR: This Intel LPC Bridge does not allow" |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1312 | " setting GPIO%02d\n", gpio); |
| 1313 | return -1; |
| 1314 | } |
| 1315 | |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1316 | msg_pdbg("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n", |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1317 | raise ? "Rais" : "Dropp", gpio); |
| 1318 | |
| 1319 | if (gpio < 32) { |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1320 | /* Set line to GPIO. */ |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1321 | tmp = INL(base); |
| 1322 | /* ICH/ICH0 multiplexes 27/28 on the line set. */ |
| 1323 | if ((gpio == 28) && |
| 1324 | ((dev->device_id == 0x2410) || (dev->device_id == 0x2420))) |
| 1325 | tmp |= 1 << 27; |
| 1326 | else |
| 1327 | tmp |= 1 << gpio; |
| 1328 | OUTL(tmp, base); |
| 1329 | |
| 1330 | /* As soon as we are talking to ICH8 and above, this register |
| 1331 | decides whether we can set the gpio or not. */ |
| 1332 | if (dev->device_id > 0x2800) { |
| 1333 | tmp = INL(base); |
| 1334 | if (!(tmp & (1 << gpio))) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1335 | msg_perr("\nERROR: This Intel LPC Bridge" |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1336 | " does not allow setting GPIO%02d\n", |
| 1337 | gpio); |
| 1338 | return -1; |
| 1339 | } |
| 1340 | } |
| 1341 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1342 | /* Set GPIO to OUTPUT. */ |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1343 | tmp = INL(base + 0x04); |
| 1344 | tmp &= ~(1 << gpio); |
| 1345 | OUTL(tmp, base + 0x04); |
| 1346 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1347 | /* Raise GPIO line. */ |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1348 | tmp = INL(base + 0x0C); |
| 1349 | if (raise) |
| 1350 | tmp |= 1 << gpio; |
| 1351 | else |
| 1352 | tmp &= ~(1 << gpio); |
| 1353 | OUTL(tmp, base + 0x0C); |
| 1354 | } else if (gpio < 64) { |
| 1355 | gpio -= 32; |
| 1356 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1357 | /* Set line to GPIO. */ |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1358 | tmp = INL(base + 0x30); |
| 1359 | tmp |= 1 << gpio; |
| 1360 | OUTL(tmp, base + 0x30); |
| 1361 | |
| 1362 | /* As soon as we are talking to ICH8 and above, this register |
| 1363 | decides whether we can set the gpio or not. */ |
| 1364 | if (dev->device_id > 0x2800) { |
| 1365 | tmp = INL(base + 30); |
| 1366 | if (!(tmp & (1 << gpio))) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1367 | msg_perr("\nERROR: This Intel LPC Bridge" |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1368 | " does not allow setting GPIO%02d\n", |
| 1369 | gpio + 32); |
| 1370 | return -1; |
| 1371 | } |
| 1372 | } |
| 1373 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1374 | /* Set GPIO to OUTPUT. */ |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1375 | tmp = INL(base + 0x34); |
| 1376 | tmp &= ~(1 << gpio); |
| 1377 | OUTL(tmp, base + 0x34); |
| 1378 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1379 | /* Raise GPIO line. */ |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1380 | tmp = INL(base + 0x38); |
| 1381 | if (raise) |
| 1382 | tmp |= 1 << gpio; |
| 1383 | else |
| 1384 | tmp &= ~(1 << gpio); |
| 1385 | OUTL(tmp, base + 0x38); |
| 1386 | } else { |
| 1387 | gpio -= 64; |
| 1388 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1389 | /* Set line to GPIO. */ |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1390 | tmp = INL(base + 0x40); |
| 1391 | tmp |= 1 << gpio; |
| 1392 | OUTL(tmp, base + 0x40); |
| 1393 | |
| 1394 | tmp = INL(base + 40); |
| 1395 | if (!(tmp & (1 << gpio))) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1396 | msg_perr("\nERROR: This Intel LPC Bridge does " |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1397 | "not allow setting GPIO%02d\n", gpio + 64); |
| 1398 | return -1; |
| 1399 | } |
| 1400 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1401 | /* Set GPIO to OUTPUT. */ |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1402 | tmp = INL(base + 0x44); |
| 1403 | tmp &= ~(1 << gpio); |
| 1404 | OUTL(tmp, base + 0x44); |
| 1405 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1406 | /* Raise GPIO line. */ |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1407 | tmp = INL(base + 0x48); |
| 1408 | if (raise) |
| 1409 | tmp |= 1 << gpio; |
| 1410 | else |
| 1411 | tmp &= ~(1 << gpio); |
| 1412 | OUTL(tmp, base + 0x48); |
| 1413 | } |
Uwe Hermann | 93f66db | 2008-05-22 21:19:38 +0000 | [diff] [blame] | 1414 | |
| 1415 | return 0; |
| 1416 | } |
| 1417 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1418 | /* |
| 1419 | * Suited for: |
| 1420 | * - abit IP35: Intel P35 + ICH9R |
| 1421 | * - abit IP35 Pro: Intel P35 + ICH9R |
Uwe Hermann | 93f66db | 2008-05-22 21:19:38 +0000 | [diff] [blame] | 1422 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 1423 | static int intel_ich_gpio16_raise(void) |
Uwe Hermann | 93f66db | 2008-05-22 21:19:38 +0000 | [diff] [blame] | 1424 | { |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1425 | return intel_ich_gpio_set(16, 1); |
Uwe Hermann | 93f66db | 2008-05-22 21:19:38 +0000 | [diff] [blame] | 1426 | } |
| 1427 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1428 | /* |
| 1429 | * Suited for: |
| 1430 | * - HP Puffer2-UL8E (ASUS PTGD-LA OEM): LGA775 + 915 + ICH6 |
Michael Karcher | e57957c | 2010-07-24 11:14:37 +0000 | [diff] [blame] | 1431 | */ |
| 1432 | static int intel_ich_gpio18_raise(void) |
| 1433 | { |
| 1434 | return intel_ich_gpio_set(18, 1); |
| 1435 | } |
| 1436 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1437 | /* |
| 1438 | * Suited for: |
Uwe Hermann | ead705f | 2010-08-15 15:26:30 +0000 | [diff] [blame] | 1439 | * - ASUS A8Jm (laptop): Intel 945 + ICH7 |
James Lancaster | 998c9dc | 2010-03-19 22:39:24 +0000 | [diff] [blame] | 1440 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 1441 | static int intel_ich_gpio34_raise(void) |
James Lancaster | 998c9dc | 2010-03-19 22:39:24 +0000 | [diff] [blame] | 1442 | { |
| 1443 | return intel_ich_gpio_set(34, 1); |
| 1444 | } |
| 1445 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1446 | /* |
| 1447 | * Suited for: |
| 1448 | * - MSI MS-7046: LGA775 + 915P + ICH6 |
Carl-Daniel Hailfinger | 2912426 | 2009-09-23 02:05:12 +0000 | [diff] [blame] | 1449 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 1450 | static int intel_ich_gpio19_raise(void) |
Carl-Daniel Hailfinger | 2912426 | 2009-09-23 02:05:12 +0000 | [diff] [blame] | 1451 | { |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1452 | return intel_ich_gpio_set(19, 1); |
Carl-Daniel Hailfinger | 2912426 | 2009-09-23 02:05:12 +0000 | [diff] [blame] | 1453 | } |
| 1454 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1455 | /* |
Luc Verhaegen | 6c5d4cc | 2009-11-28 18:26:21 +0000 | [diff] [blame] | 1456 | * Suited for: |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1457 | * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2 |
| 1458 | * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5 |
Michael Karcher | f4b5879 | 2010-09-10 14:54:18 +0000 | [diff] [blame] | 1459 | * - ASUS P4P800: Intel socket478 + 865PE + ICH5R |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1460 | * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R |
Michael Karcher | 4a23e44 | 2010-09-10 14:46:46 +0000 | [diff] [blame] | 1461 | * - ASUS P5GD1 Pro: Intel LGA 775 + 915P + ICH6R |
Joshua Roys | b1d980f | 2010-09-13 14:02:22 +0000 | [diff] [blame] | 1462 | * - ASUS P5GDC Deluxe: Intel socket775 + 915P + ICH6R |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1463 | * - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5 |
| 1464 | * - Samsung Polaris 32: socket478 + 865P + ICH5 |
Peter Stuge | 09c1333 | 2009-02-02 22:55:26 +0000 | [diff] [blame] | 1465 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 1466 | static int intel_ich_gpio21_raise(void) |
Peter Stuge | 09c1333 | 2009-02-02 22:55:26 +0000 | [diff] [blame] | 1467 | { |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1468 | return intel_ich_gpio_set(21, 1); |
Peter Stuge | 09c1333 | 2009-02-02 22:55:26 +0000 | [diff] [blame] | 1469 | } |
| 1470 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1471 | /* |
Michael Karcher | 03b80e9 | 2010-03-07 16:32:32 +0000 | [diff] [blame] | 1472 | * Suited for: |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1473 | * - ASUS P4B266: socket478 + Intel 845D + ICH2 |
Uwe Hermann | 4e3d0b3 | 2010-03-25 23:18:41 +0000 | [diff] [blame] | 1474 | * - ASUS P4B533-E: socket478 + 845E + ICH4 |
| 1475 | * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2 |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1476 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 1477 | static int intel_ich_gpio22_raise(void) |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1478 | { |
| 1479 | return intel_ich_gpio_set(22, 1); |
| 1480 | } |
| 1481 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1482 | /* |
| 1483 | * Suited for: |
| 1484 | * - HP Vectra VL400: 815 + ICH + PC87360 |
Michael Karcher | 5fbd18d | 2010-02-27 18:35:54 +0000 | [diff] [blame] | 1485 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 1486 | static int board_hp_vl400(void) |
Michael Karcher | 5fbd18d | 2010-02-27 18:35:54 +0000 | [diff] [blame] | 1487 | { |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1488 | int ret; |
| 1489 | ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */ |
| 1490 | if (!ret) |
Michael Karcher | cba52de | 2011-03-06 12:07:19 +0000 | [diff] [blame] | 1491 | ret = pc8736x_gpio_set(PC87360_ID, 0x09, 1); /* #WP ? */ |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1492 | if (!ret) |
Michael Karcher | cba52de | 2011-03-06 12:07:19 +0000 | [diff] [blame] | 1493 | ret = pc8736x_gpio_set(PC87360_ID, 0x27, 1); /* #TBL */ |
| 1494 | return ret; |
| 1495 | } |
| 1496 | |
| 1497 | /* |
| 1498 | * Suited for: |
| 1499 | * - HP e-Vectra P2706T: 810E + ICH + PC87364 |
| 1500 | */ |
| 1501 | static int board_hp_p2706t(void) |
| 1502 | { |
| 1503 | int ret; |
| 1504 | ret = pc8736x_gpio_set(PC87364_ID, 0x25, 1); |
| 1505 | if (!ret) |
| 1506 | ret = pc8736x_gpio_set(PC87364_ID, 0x26, 1); |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1507 | return ret; |
Michael Karcher | 5fbd18d | 2010-02-27 18:35:54 +0000 | [diff] [blame] | 1508 | } |
| 1509 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1510 | /* |
Luc Verhaegen | 1265d8d | 2009-11-28 18:16:31 +0000 | [diff] [blame] | 1511 | * Suited for: |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1512 | * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R |
| 1513 | * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R |
| 1514 | * - ASRock 775i65G: Intel LGA 775 + 865G + ICH5 |
Uwe Hermann | 742999c | 2010-12-02 21:57:42 +0000 | [diff] [blame] | 1515 | * - MSI MS-6391 (845 Pro4): Intel Socket478 + 845 + ICH2 |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1516 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 1517 | static int intel_ich_gpio23_raise(void) |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1518 | { |
| 1519 | return intel_ich_gpio_set(23, 1); |
| 1520 | } |
| 1521 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1522 | /* |
| 1523 | * Suited for: |
Michael Karcher | 39dcdec | 2010-10-05 17:29:35 +0000 | [diff] [blame] | 1524 | * - GIGABYTE GA-6IEM: Intel Socket370 + i815 + ICH2 |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1525 | * - GIGABYTE GA-8IRML: Intel Socket478 + i845 + ICH2 |
Michael Karcher | c7a1ffb | 2010-07-24 22:27:29 +0000 | [diff] [blame] | 1526 | */ |
| 1527 | static int intel_ich_gpio25_raise(void) |
| 1528 | { |
| 1529 | return intel_ich_gpio_set(25, 1); |
| 1530 | } |
| 1531 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1532 | /* |
| 1533 | * Suited for: |
| 1534 | * - IBASE MB899: i945GM + ICH7 |
Luc Verhaegen | f63c436 | 2010-03-19 23:01:34 +0000 | [diff] [blame] | 1535 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 1536 | static int intel_ich_gpio26_raise(void) |
Luc Verhaegen | f63c436 | 2010-03-19 23:01:34 +0000 | [diff] [blame] | 1537 | { |
| 1538 | return intel_ich_gpio_set(26, 1); |
| 1539 | } |
| 1540 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1541 | /* |
| 1542 | * Suited for: |
| 1543 | * - P4SD-LA (HP OEM): i865 + ICH5 |
Michael Karcher | c861324 | 2010-08-13 12:49:01 +0000 | [diff] [blame] | 1544 | * - GIGABYTE GA-8PE667 Ultra 2: socket 478 + i845PE + ICH4 |
Michael Karcher | 87c9099 | 2010-07-24 11:03:48 +0000 | [diff] [blame] | 1545 | */ |
Idwer Vollering | 19dceac | 2010-07-24 18:47:45 +0000 | [diff] [blame] | 1546 | static int intel_ich_gpio32_raise(void) |
Michael Karcher | 87c9099 | 2010-07-24 11:03:48 +0000 | [diff] [blame] | 1547 | { |
| 1548 | return intel_ich_gpio_set(32, 1); |
| 1549 | } |
| 1550 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1551 | /* |
| 1552 | * Suited for: |
| 1553 | * - Acorp 6A815EPD: socket 370 + intel 815 + ICH2 |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1554 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 1555 | static int board_acorp_6a815epd(void) |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1556 | { |
| 1557 | int ret; |
| 1558 | |
| 1559 | /* Lower Blocks Lock -- pin 7 of PLCC32 */ |
| 1560 | ret = intel_ich_gpio_set(22, 1); |
| 1561 | if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */ |
| 1562 | ret = intel_ich_gpio_set(23, 1); |
| 1563 | |
| 1564 | return ret; |
| 1565 | } |
| 1566 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1567 | /* |
| 1568 | * Suited for: |
| 1569 | * - Kontron 986LCD-M: Socket478 + 915GM + ICH7R |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1570 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 1571 | static int board_kontron_986lcd_m(void) |
Stefan Reinauer | ac37897 | 2008-03-17 22:59:40 +0000 | [diff] [blame] | 1572 | { |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1573 | int ret; |
Stefan Reinauer | ac37897 | 2008-03-17 22:59:40 +0000 | [diff] [blame] | 1574 | |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1575 | ret = intel_ich_gpio_set(34, 1); /* #TBL */ |
| 1576 | if (!ret) |
| 1577 | ret = intel_ich_gpio_set(35, 1); /* #WP */ |
Stefan Reinauer | ac37897 | 2008-03-17 22:59:40 +0000 | [diff] [blame] | 1578 | |
Luc Verhaegen | 60ea7dc | 2009-11-28 18:07:51 +0000 | [diff] [blame] | 1579 | return ret; |
Stefan Reinauer | ac37897 | 2008-03-17 22:59:40 +0000 | [diff] [blame] | 1580 | } |
| 1581 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1582 | /* |
| 1583 | * Suited for: |
| 1584 | * - Soyo SY-7VCA: Pro133A + VT82C686 |
Luc Verhaegen | 3920eda | 2009-06-17 14:43:24 +0000 | [diff] [blame] | 1585 | */ |
Michael Karcher | 0647733 | 2010-03-19 22:49:09 +0000 | [diff] [blame] | 1586 | static int via_apollo_gpo_set(int gpio, int raise) |
Luc Verhaegen | 3920eda | 2009-06-17 14:43:24 +0000 | [diff] [blame] | 1587 | { |
Michael Karcher | 0647733 | 2010-03-19 22:49:09 +0000 | [diff] [blame] | 1588 | struct pci_dev *dev; |
Luc Verhaegen | 3920eda | 2009-06-17 14:43:24 +0000 | [diff] [blame] | 1589 | uint32_t base; |
Michael Karcher | 0647733 | 2010-03-19 22:49:09 +0000 | [diff] [blame] | 1590 | uint32_t tmp; |
Luc Verhaegen | 3920eda | 2009-06-17 14:43:24 +0000 | [diff] [blame] | 1591 | |
| 1592 | /* VT82C686 Power management */ |
| 1593 | dev = pci_dev_find(0x1106, 0x3057); |
| 1594 | if (!dev) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1595 | msg_perr("\nERROR: VT82C686 PM device not found.\n"); |
Luc Verhaegen | 3920eda | 2009-06-17 14:43:24 +0000 | [diff] [blame] | 1596 | return -1; |
| 1597 | } |
| 1598 | |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1599 | msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n", |
Michael Karcher | 0647733 | 2010-03-19 22:49:09 +0000 | [diff] [blame] | 1600 | raise ? "Rais" : "Dropp", gpio); |
| 1601 | |
| 1602 | /* select GPO function on multiplexed pins */ |
Luc Verhaegen | 3920eda | 2009-06-17 14:43:24 +0000 | [diff] [blame] | 1603 | tmp = pci_read_byte(dev, 0x54); |
Michael Karcher | 0647733 | 2010-03-19 22:49:09 +0000 | [diff] [blame] | 1604 | switch(gpio) |
| 1605 | { |
| 1606 | case 0: |
| 1607 | tmp &= ~0x03; |
| 1608 | break; |
| 1609 | case 1: |
| 1610 | tmp |= 0x04; |
| 1611 | break; |
| 1612 | case 2: |
| 1613 | tmp |= 0x08; |
| 1614 | break; |
| 1615 | case 3: |
| 1616 | tmp |= 0x10; |
| 1617 | break; |
| 1618 | } |
Luc Verhaegen | 3920eda | 2009-06-17 14:43:24 +0000 | [diff] [blame] | 1619 | pci_write_byte(dev, 0x54, tmp); |
| 1620 | |
| 1621 | /* PM IO base */ |
| 1622 | base = pci_read_long(dev, 0x48) & 0x0000FF00; |
| 1623 | |
| 1624 | /* Drop GPO0 */ |
Michael Karcher | 0647733 | 2010-03-19 22:49:09 +0000 | [diff] [blame] | 1625 | tmp = INL(base + 0x4C); |
| 1626 | if (raise) |
| 1627 | tmp |= 1U << gpio; |
| 1628 | else |
| 1629 | tmp &= ~(1U << gpio); |
| 1630 | OUTL(tmp, base + 0x4C); |
Luc Verhaegen | 3920eda | 2009-06-17 14:43:24 +0000 | [diff] [blame] | 1631 | |
| 1632 | return 0; |
| 1633 | } |
| 1634 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1635 | /* |
| 1636 | * Suited for: |
| 1637 | * - abit VT6X4: Pro133x + VT82C686A |
Mattias Mattsson | e3df96e | 2010-08-15 22:43:23 +0000 | [diff] [blame] | 1638 | * - abit VA6: Pro133x + VT82C686A |
Michael Karcher | 187a46a | 2010-03-19 22:30:49 +0000 | [diff] [blame] | 1639 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 1640 | static int via_apollo_gpo4_lower(void) |
Michael Karcher | 187a46a | 2010-03-19 22:30:49 +0000 | [diff] [blame] | 1641 | { |
| 1642 | return via_apollo_gpo_set(4, 0); |
| 1643 | } |
| 1644 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1645 | /* |
| 1646 | * Suited for: |
| 1647 | * - Soyo SY-7VCA: Pro133A + VT82C686 |
Michael Karcher | 0647733 | 2010-03-19 22:49:09 +0000 | [diff] [blame] | 1648 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 1649 | static int via_apollo_gpo0_lower(void) |
Michael Karcher | 0647733 | 2010-03-19 22:49:09 +0000 | [diff] [blame] | 1650 | { |
| 1651 | return via_apollo_gpo_set(0, 0); |
| 1652 | } |
| 1653 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1654 | /* |
Michael Karcher | 9f9e613 | 2010-01-09 17:36:06 +0000 | [diff] [blame] | 1655 | * Enable some GPIO pin on SiS southbridge. |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1656 | * |
| 1657 | * Suited for: |
| 1658 | * - MSI 651M-L: SiS651 / SiS962 |
Michael Karcher | 9f9e613 | 2010-01-09 17:36:06 +0000 | [diff] [blame] | 1659 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 1660 | static int board_msi_651ml(void) |
Michael Karcher | 9f9e613 | 2010-01-09 17:36:06 +0000 | [diff] [blame] | 1661 | { |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1662 | struct pci_dev *dev; |
Uwe Hermann | 4395970 | 2010-03-13 17:28:29 +0000 | [diff] [blame] | 1663 | uint16_t base, temp; |
Michael Karcher | 9f9e613 | 2010-01-09 17:36:06 +0000 | [diff] [blame] | 1664 | |
| 1665 | dev = pci_dev_find(0x1039, 0x0962); |
| 1666 | if (!dev) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1667 | msg_perr("Expected south bridge not found\n"); |
Michael Karcher | 9f9e613 | 2010-01-09 17:36:06 +0000 | [diff] [blame] | 1668 | return 1; |
| 1669 | } |
| 1670 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1671 | /* Registers 68 and 64 seem like bitmaps. */ |
Michael Karcher | 9f9e613 | 2010-01-09 17:36:06 +0000 | [diff] [blame] | 1672 | base = pci_read_word(dev, 0x74); |
| 1673 | temp = INW(base + 0x68); |
| 1674 | temp &= ~(1 << 0); /* Make pin output? */ |
Michael Karcher | 0435dfd | 2010-01-09 23:31:13 +0000 | [diff] [blame] | 1675 | OUTW(temp, base + 0x68); |
Michael Karcher | 9f9e613 | 2010-01-09 17:36:06 +0000 | [diff] [blame] | 1676 | |
| 1677 | temp = INW(base + 0x64); |
| 1678 | temp |= (1 << 0); /* Raise output? */ |
| 1679 | OUTW(temp, base + 0x64); |
| 1680 | |
| 1681 | w836xx_memw_enable(0x2E); |
| 1682 | |
| 1683 | return 0; |
| 1684 | } |
| 1685 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1686 | /* |
Michael Gold | 6d52e47 | 2009-06-19 13:00:24 +0000 | [diff] [blame] | 1687 | * Find the runtime registers of an SMSC Super I/O, after verifying its |
| 1688 | * chip ID. |
| 1689 | * |
| 1690 | * Returns the base port of the runtime register block, or 0 on error. |
| 1691 | */ |
| 1692 | static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id, |
| 1693 | uint8_t logical_device) |
| 1694 | { |
| 1695 | uint16_t rt_port = 0; |
| 1696 | |
| 1697 | /* Verify the chip ID. */ |
Uwe Hermann | 1432a60 | 2009-06-28 23:26:37 +0000 | [diff] [blame] | 1698 | OUTB(0x55, sio_port); /* Enable configuration. */ |
Michael Gold | 6d52e47 | 2009-06-19 13:00:24 +0000 | [diff] [blame] | 1699 | if (sio_read(sio_port, 0x20) != chip_id) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1700 | msg_perr("\nERROR: SMSC Super I/O not found.\n"); |
Michael Gold | 6d52e47 | 2009-06-19 13:00:24 +0000 | [diff] [blame] | 1701 | goto out; |
| 1702 | } |
| 1703 | |
| 1704 | /* If the runtime block is active, get its address. */ |
| 1705 | sio_write(sio_port, 0x07, logical_device); |
| 1706 | if (sio_read(sio_port, 0x30) & 1) { |
| 1707 | rt_port = (sio_read(sio_port, 0x60) << 8) |
| 1708 | | sio_read(sio_port, 0x61); |
| 1709 | } |
| 1710 | |
| 1711 | if (rt_port == 0) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1712 | msg_perr("\nERROR: " |
Michael Gold | 6d52e47 | 2009-06-19 13:00:24 +0000 | [diff] [blame] | 1713 | "Super I/O runtime interface not available.\n"); |
| 1714 | } |
| 1715 | out: |
Uwe Hermann | 1432a60 | 2009-06-28 23:26:37 +0000 | [diff] [blame] | 1716 | OUTB(0xaa, sio_port); /* Disable configuration. */ |
Michael Gold | 6d52e47 | 2009-06-19 13:00:24 +0000 | [diff] [blame] | 1717 | return rt_port; |
| 1718 | } |
| 1719 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1720 | /* |
| 1721 | * Disable write protection on the Mitac 6513WU. WP# on the FWH is |
Michael Gold | 6d52e47 | 2009-06-19 13:00:24 +0000 | [diff] [blame] | 1722 | * connected to GP30 on the Super I/O, and TBL# is always high. |
| 1723 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 1724 | static int board_mitac_6513wu(void) |
Michael Gold | 6d52e47 | 2009-06-19 13:00:24 +0000 | [diff] [blame] | 1725 | { |
| 1726 | struct pci_dev *dev; |
| 1727 | uint16_t rt_port; |
| 1728 | uint8_t val; |
| 1729 | |
| 1730 | dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */ |
| 1731 | if (!dev) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1732 | msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n"); |
Michael Gold | 6d52e47 | 2009-06-19 13:00:24 +0000 | [diff] [blame] | 1733 | return -1; |
| 1734 | } |
| 1735 | |
Uwe Hermann | 1432a60 | 2009-06-28 23:26:37 +0000 | [diff] [blame] | 1736 | rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa); |
Michael Gold | 6d52e47 | 2009-06-19 13:00:24 +0000 | [diff] [blame] | 1737 | if (rt_port == 0) |
| 1738 | return -1; |
| 1739 | |
| 1740 | /* Configure the GPIO pin. */ |
| 1741 | val = INB(rt_port + 0x33); /* GP30 config */ |
Uwe Hermann | 1432a60 | 2009-06-28 23:26:37 +0000 | [diff] [blame] | 1742 | val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */ |
Michael Gold | 6d52e47 | 2009-06-19 13:00:24 +0000 | [diff] [blame] | 1743 | OUTB(val, rt_port + 0x33); |
| 1744 | |
| 1745 | /* Disable write protection. */ |
| 1746 | val = INB(rt_port + 0x4d); /* GP3 values */ |
Uwe Hermann | 1432a60 | 2009-06-28 23:26:37 +0000 | [diff] [blame] | 1747 | val |= 0x01; /* Set GP30 high. */ |
Michael Gold | 6d52e47 | 2009-06-19 13:00:24 +0000 | [diff] [blame] | 1748 | OUTB(val, rt_port + 0x4d); |
| 1749 | |
| 1750 | return 0; |
| 1751 | } |
| 1752 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1753 | /* |
| 1754 | * Suited for: |
Uwe Hermann | 45bd144 | 2010-09-14 23:20:35 +0000 | [diff] [blame] | 1755 | * - ASUS A7V333: VIA KT333 + VT8233A + IT8703F |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1756 | * - ASUS A7V8X: VIA KT400 + VT8235 + IT8703F |
Luc Verhaegen | 78e4e12 | 2009-07-13 12:40:17 +0000 | [diff] [blame] | 1757 | */ |
Uwe Hermann | 45bd144 | 2010-09-14 23:20:35 +0000 | [diff] [blame] | 1758 | static int it8703f_gpio51_raise(void) |
Luc Verhaegen | 78e4e12 | 2009-07-13 12:40:17 +0000 | [diff] [blame] | 1759 | { |
| 1760 | uint16_t id, base; |
| 1761 | uint8_t tmp; |
| 1762 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1763 | /* Find the IT8703F. */ |
Luc Verhaegen | 78e4e12 | 2009-07-13 12:40:17 +0000 | [diff] [blame] | 1764 | w836xx_ext_enter(0x2E); |
| 1765 | id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21); |
| 1766 | w836xx_ext_leave(0x2E); |
| 1767 | |
| 1768 | if (id != 0x8701) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1769 | msg_perr("\nERROR: IT8703F Super I/O not found.\n"); |
Luc Verhaegen | 78e4e12 | 2009-07-13 12:40:17 +0000 | [diff] [blame] | 1770 | return -1; |
| 1771 | } |
| 1772 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1773 | /* Get the GP567 I/O base. */ |
Luc Verhaegen | 78e4e12 | 2009-07-13 12:40:17 +0000 | [diff] [blame] | 1774 | w836xx_ext_enter(0x2E); |
| 1775 | sio_write(0x2E, 0x07, 0x0C); |
| 1776 | base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61); |
| 1777 | w836xx_ext_leave(0x2E); |
| 1778 | |
| 1779 | if (!base) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1780 | msg_perr("\nERROR: Failed to read IT8703F Super I/O GPIO" |
Luc Verhaegen | 78e4e12 | 2009-07-13 12:40:17 +0000 | [diff] [blame] | 1781 | " Base.\n"); |
| 1782 | return -1; |
| 1783 | } |
| 1784 | |
| 1785 | /* Raise GP51. */ |
| 1786 | tmp = INB(base); |
| 1787 | tmp |= 0x02; |
| 1788 | OUTB(tmp, base); |
| 1789 | |
| 1790 | return 0; |
| 1791 | } |
| 1792 | |
Luc Verhaegen | 7227291 | 2009-09-01 21:22:23 +0000 | [diff] [blame] | 1793 | /* |
| 1794 | * General routine for raising/dropping GPIO lines on the ITE IT8712F. |
| 1795 | * There is only some limited checking on the port numbers. |
| 1796 | */ |
Uwe Hermann | 4395970 | 2010-03-13 17:28:29 +0000 | [diff] [blame] | 1797 | static int it8712f_gpio_set(unsigned int line, int raise) |
Luc Verhaegen | 7227291 | 2009-09-01 21:22:23 +0000 | [diff] [blame] | 1798 | { |
| 1799 | unsigned int port; |
| 1800 | uint16_t id, base; |
| 1801 | uint8_t tmp; |
| 1802 | |
| 1803 | port = line / 10; |
| 1804 | port--; |
| 1805 | line %= 10; |
| 1806 | |
| 1807 | /* Check line */ |
| 1808 | if ((port > 4) || /* also catches unsigned -1 */ |
| 1809 | ((port < 4) && (line > 7)) || ((port == 4) && (line > 5))) { |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1810 | msg_perr("\nERROR: Unsupported IT8712F GPIO line %02d.\n", line); |
Luc Verhaegen | 7227291 | 2009-09-01 21:22:23 +0000 | [diff] [blame] | 1811 | return -1; |
| 1812 | } |
| 1813 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1814 | /* Find the IT8712F. */ |
Luc Verhaegen | 7227291 | 2009-09-01 21:22:23 +0000 | [diff] [blame] | 1815 | enter_conf_mode_ite(0x2E); |
| 1816 | id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21); |
| 1817 | exit_conf_mode_ite(0x2E); |
| 1818 | |
| 1819 | if (id != 0x8712) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1820 | msg_perr("\nERROR: IT8712F Super I/O not found.\n"); |
Luc Verhaegen | 7227291 | 2009-09-01 21:22:23 +0000 | [diff] [blame] | 1821 | return -1; |
| 1822 | } |
| 1823 | |
| 1824 | /* Get the GPIO base */ |
| 1825 | enter_conf_mode_ite(0x2E); |
| 1826 | sio_write(0x2E, 0x07, 0x07); |
| 1827 | base = (sio_read(0x2E, 0x62) << 8) | sio_read(0x2E, 0x63); |
| 1828 | exit_conf_mode_ite(0x2E); |
| 1829 | |
| 1830 | if (!base) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1831 | msg_perr("\nERROR: Failed to read IT8712F Super I/O GPIO" |
Luc Verhaegen | 7227291 | 2009-09-01 21:22:23 +0000 | [diff] [blame] | 1832 | " Base.\n"); |
| 1833 | return -1; |
| 1834 | } |
| 1835 | |
| 1836 | /* set GPIO. */ |
| 1837 | tmp = INB(base + port); |
| 1838 | if (raise) |
| 1839 | tmp |= 1 << line; |
| 1840 | else |
| 1841 | tmp &= ~(1 << line); |
| 1842 | OUTB(tmp, base + port); |
| 1843 | |
| 1844 | return 0; |
| 1845 | } |
| 1846 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1847 | /* |
Russ Dill | bd622d1 | 2010-03-09 16:57:06 +0000 | [diff] [blame] | 1848 | * Suited for: |
Uwe Hermann | 4e3d0b3 | 2010-03-25 23:18:41 +0000 | [diff] [blame] | 1849 | * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F |
| 1850 | * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F |
Luc Verhaegen | 7227291 | 2009-09-01 21:22:23 +0000 | [diff] [blame] | 1851 | */ |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 1852 | static int it8712f_gpio3_1_raise(void) |
Luc Verhaegen | 7227291 | 2009-09-01 21:22:23 +0000 | [diff] [blame] | 1853 | { |
| 1854 | return it8712f_gpio_set(32, 1); |
| 1855 | } |
| 1856 | |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 1857 | #endif |
| 1858 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1859 | /* |
Uwe Hermann | d0e347d | 2009-10-06 13:00:00 +0000 | [diff] [blame] | 1860 | * Below is the list of boards which need a special "board enable" code in |
| 1861 | * flashrom before their ROM chip can be accessed/written to. |
| 1862 | * |
| 1863 | * NOTE: Please add boards that _don't_ need such enables or don't work yet |
| 1864 | * to the respective tables in print.c. Thanks! |
| 1865 | * |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 1866 | * We use 2 sets of IDs here, you're free to choose which is which. This |
| 1867 | * is to provide a very high degree of certainty when matching a board on |
| 1868 | * the basis of subsystem/card IDs. As not every vendor handles |
| 1869 | * subsystem/card IDs in a sane manner. |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1870 | * |
Luc Verhaegen | c521016 | 2009-04-20 12:38:17 +0000 | [diff] [blame] | 1871 | * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs |
Carl-Daniel Hailfinger | 7a788f5 | 2010-02-04 11:12:04 +0000 | [diff] [blame] | 1872 | * NULLed if they don't identify the board fully and if you can't use DMI. |
| 1873 | * But please take care to provide an as complete set of pci ids as possible; |
| 1874 | * autodetection is the preferred behaviour and we would like to make sure that |
| 1875 | * matches are unique. |
Mart Raudsepp | faa62fb | 2008-02-20 11:11:18 +0000 | [diff] [blame] | 1876 | * |
Michael Karcher | 6701ee8 | 2010-01-20 14:14:11 +0000 | [diff] [blame] | 1877 | * If PCI IDs are not sufficient for board matching, the match can be further |
| 1878 | * constrained by a string that has to be present in the DMI database for |
Uwe Hermann | 4e3d0b3 | 2010-03-25 23:18:41 +0000 | [diff] [blame] | 1879 | * the baseboard or the system entry. The pattern is matched by case sensitive |
Michael Karcher | 6701ee8 | 2010-01-20 14:14:11 +0000 | [diff] [blame] | 1880 | * substring match, unless it is anchored to the beginning (with a ^ in front) |
| 1881 | * or the end (with a $ at the end). Both anchors may be specified at the |
| 1882 | * same time to match the full field. |
| 1883 | * |
Carl-Daniel Hailfinger | 7a788f5 | 2010-02-04 11:12:04 +0000 | [diff] [blame] | 1884 | * When a board is matched through DMI, the first and second main PCI IDs |
| 1885 | * and the first subsystem PCI ID have to match as well. If you specify the |
| 1886 | * first subsystem ID as 0x0:0x0, the DMI matching code expects that the |
| 1887 | * subsystem ID of that device is indeed zero. |
| 1888 | * |
Luc Verhaegen | c521016 | 2009-04-20 12:38:17 +0000 | [diff] [blame] | 1889 | * The coreboot ids are used two fold. When running with a coreboot firmware, |
| 1890 | * the ids uniquely matches the coreboot board identification string. When a |
| 1891 | * legacy bios is installed and when autodetection is not possible, these ids |
| 1892 | * can be used to identify the board through the -m command line argument. |
| 1893 | * |
| 1894 | * When a board is identified through its coreboot ids (in both cases), the |
| 1895 | * main pci ids are still required to match, as a safeguard. |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1896 | */ |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1897 | |
Uwe Hermann | deeebe2 | 2009-05-08 16:23:34 +0000 | [diff] [blame] | 1898 | /* Please keep this list alphabetically ordered by vendor/board name. */ |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 1899 | const struct board_pciid_enable board_pciid_enables[] = { |
Uwe Hermann | 5ab8889 | 2009-06-21 20:50:22 +0000 | [diff] [blame] | 1900 | |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1901 | /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */ |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 1902 | #if defined(__i386__) || defined(__x86_64__) |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1903 | {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise}, |
Tim ter Laak | 4b933f0 | 2010-09-13 23:00:57 +0000 | [diff] [blame] | 1904 | {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^i440BX-W977 (BM6)$", NULL, NULL, "abit", "BM6", 0, OK, intel_piix4_gpo26_lower}, |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1905 | {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, "abit", "IC7", 0, NT, intel_ich_gpio23_raise}, |
| 1906 | {0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "abit", "IP35", 0, OK, intel_ich_gpio16_raise}, |
| 1907 | {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise}, |
| 1908 | {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, "abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower}, |
| 1909 | {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, "abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise}, |
| 1910 | {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0240, 0x10de, 0x0222, NULL, NULL, NULL, "abit", "NF-M2 nView", 0, NT, nvidia_mcp_gpio4_lower}, |
Mattias Mattsson | e3df96e | 2010-08-15 22:43:23 +0000 | [diff] [blame] | 1911 | {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, "(VA6)$", NULL, NULL, "abit", "VA6", 0, OK, via_apollo_gpo4_lower}, |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1912 | {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "abit", "VT6X4", 0, OK, via_apollo_gpo4_lower}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1913 | {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1914 | {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e}, |
Peter Lemenkov | 4073c09 | 2010-05-26 22:29:51 +0000 | [diff] [blame] | 1915 | {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1916 | {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x}, |
| 1917 | {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x}, |
Uwe Hermann | 17da61e | 2010-10-05 21:48:43 +0000 | [diff] [blame] | 1918 | {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e}, |
Peter Lemenkov | eb75ced | 2010-05-26 22:26:44 +0000 | [diff] [blame] | 1919 | {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise}, |
Joshua Roys | 7507de4 | 2010-08-08 16:05:23 +0000 | [diff] [blame] | 1920 | {0x8086, 0x2570, 0x1849, 0x2570, 0x8086, 0x24d3, 0x1849, 0x24d0, NULL, NULL, NULL, "ASRock", "775i65G", 0, OK, intel_ich_gpio23_raise}, |
Russ Dill | bd622d1 | 2010-03-09 16:57:06 +0000 | [diff] [blame] | 1921 | {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise}, |
Peter Lemenkov | eb75ced | 2010-05-26 22:26:44 +0000 | [diff] [blame] | 1922 | {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e}, |
Uwe Hermann | 45bd144 | 2010-09-14 23:20:35 +0000 | [diff] [blame] | 1923 | {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, it8703f_gpio51_raise}, |
| 1924 | {0x1106, 0x3099, 0x1043, 0x807F, 0x1106, 0x3147, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V333", 0, OK, it8703f_gpio51_raise}, |
Russ Dill | bd622d1 | 2010-03-09 16:57:06 +0000 | [diff] [blame] | 1925 | {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise}, |
Uwe Hermann | ead705f | 2010-08-15 15:26:30 +0000 | [diff] [blame] | 1926 | {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, "ASUS", "A8Jm", 0, NT, intel_ich_gpio34_raise}, |
Sean Nelson | 0a24751 | 2010-08-15 14:36:18 +0000 | [diff] [blame] | 1927 | {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L", NULL, NULL, "ASUS", "A8N-LA (Nagami-GL8E)", 0, OK, nvidia_mcp_gpio0_raise}, |
Uwe Hermann | ead705f | 2010-08-15 15:26:30 +0000 | [diff] [blame] | 1928 | {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N", 0, NT, board_shuttle_fn25}, /* TODO: This should probably be A8N-SLI Deluxe, see http://www.coreboot.org/pipermail/flashrom/2009-November/000878.html. */ |
Michael Karcher | 7af6cef | 2010-07-08 09:32:18 +0000 | [diff] [blame] | 1929 | {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, "ASUS", "A8N-VM CSM", 0, NT, w83627ehf_gpio24_raise_2e}, |
Michael Karcher | b2184c1 | 2010-03-07 16:42:55 +0000 | [diff] [blame] | 1930 | {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1931 | {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise}, |
Mattias Mattsson | 85016b9 | 2010-09-01 01:21:34 +0000 | [diff] [blame] | 1932 | {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^P2B-N$", NULL, NULL, "ASUS", "P2B-N", 0, OK, intel_piix4_gpo18_lower}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1933 | {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise}, |
Peter Lemenkov | eb75ced | 2010-05-26 22:26:44 +0000 | [diff] [blame] | 1934 | {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise}, |
Michael Karcher | 255a9e0 | 2010-03-19 22:52:00 +0000 | [diff] [blame] | 1935 | {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise}, |
Michael Karcher | 6499d5a | 2010-03-17 06:19:23 +0000 | [diff] [blame] | 1936 | {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, |
Michael Karcher | f4b5879 | 2010-09-10 14:54:18 +0000 | [diff] [blame] | 1937 | {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, "ASUS", "P4P800", 0, NT, intel_ich_gpio21_raise}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1938 | {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise}, |
Mattias Mattsson | fb60cec | 2010-09-13 19:39:25 +0000 | [diff] [blame] | 1939 | {0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, "ASUS", "P4SC-E", 0, OK, it8707f_write_enable_2e}, |
Michael Karcher | 87c9099 | 2010-07-24 11:03:48 +0000 | [diff] [blame] | 1940 | {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise}, |
David Borg | b6417a6 | 2010-08-02 08:29:34 +0000 | [diff] [blame] | 1941 | {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1942 | {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a}, |
Michael Karcher | 4a23e44 | 2010-09-10 14:46:46 +0000 | [diff] [blame] | 1943 | {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise}, |
Joshua Roys | b1d980f | 2010-09-13 14:02:22 +0000 | [diff] [blame] | 1944 | {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1945 | {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise}, |
Michael Karcher | 72eeab5 | 2010-07-24 10:41:42 +0000 | [diff] [blame] | 1946 | {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise}, |
Mattias Mattsson | 2eaad63 | 2010-10-05 21:32:29 +0000 | [diff] [blame] | 1947 | {0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1948 | {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise}, |
Mattias Mattsson | f492516 | 2010-09-16 22:09:18 +0000 | [diff] [blame] | 1949 | {0x10de, 0x03ea, 0x1019, 0x2602, 0x10de, 0x03e0, 0x1019, 0x2602, NULL, NULL, NULL, "Elitegroup", "GeForce6100SM-M", 0, OK, board_ecs_geforce6100sm_m}, |
Carl-Daniel Hailfinger | 76d4b37 | 2010-07-10 16:56:32 +0000 | [diff] [blame] | 1950 | {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, NULL}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1951 | {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e}, |
Uwe Hermann | 83d349a | 2010-10-18 22:32:03 +0000 | [diff] [blame] | 1952 | {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, NULL, NULL, NULL, "EPoX", "EP-8NPA7I", 0, OK, nvidia_mcp_gpio4_raise}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1953 | {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise}, |
Mattias Mattsson | d7ed7f7 | 2010-08-15 22:35:31 +0000 | [diff] [blame] | 1954 | {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", "EPoX", "EP-BX3", 0, NT, intel_piix4_gpo22_raise}, |
Michael Karcher | 39dcdec | 2010-10-05 17:29:35 +0000 | [diff] [blame] | 1955 | {0x8086, 0x2443, 0x8086, 0x2442, 0x8086, 0x1130, 0x8086, 0x1130, "^6IEM ", NULL, NULL, "GIGABYTE", "GA-6IEM", 0, NT, intel_ich_gpio25_raise}, |
Peter Lemenkov | eb75ced | 2010-05-26 22:26:44 +0000 | [diff] [blame] | 1956 | {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL}, |
Uwe Hermann | 51afebb | 2010-08-01 00:13:49 +0000 | [diff] [blame] | 1957 | {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise}, |
Michael Karcher | c861324 | 2010-08-13 12:49:01 +0000 | [diff] [blame] | 1958 | {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise}, |
Michael Karcher | 242efd4 | 2011-03-06 12:09:05 +0000 | [diff] [blame] | 1959 | {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise}, |
Joshua Roys | 2ee137f | 2010-09-07 17:52:09 +0000 | [diff] [blame] | 1960 | {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1961 | {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise}, |
Michael Karcher | cba52de | 2011-03-06 12:07:19 +0000 | [diff] [blame] | 1962 | {0x8086, 0x2415, 0x103c, 0x1250, 0x10b7, 0x9200, 0x103c, 0x1247, NULL, NULL, NULL, "HP", "e-Vectra P2706T", 0, OK, board_hp_p2706t}, |
Uwe Hermann | ead705f | 2010-08-15 15:26:30 +0000 | [diff] [blame] | 1963 | {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable}, |
| 1964 | {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", "HP", "ProLiant DL165 G6", 0, OK, board_hp_dl165_g6_enable}, |
Michael Karcher | e57957c | 2010-07-24 11:14:37 +0000 | [diff] [blame] | 1965 | {0x8086, 0x2580, 0x103c, 0x2a08, 0x8086, 0x2640, 0x103c, 0x2a0a, NULL, NULL, NULL, "HP", "Puffer2-UL8E", 0, OK, intel_ich_gpio18_raise}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1966 | {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400}, |
Uwe Hermann | ead705f | 2010-08-15 15:26:30 +0000 | [diff] [blame] | 1967 | {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "Vectra VL420 SFF", 0, OK, intel_ich_gpio22_raise}, |
Michael Karcher | 8262e82 | 2011-03-06 17:37:30 +0000 | [diff] [blame] | 1968 | {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, "hp", "xw9400", "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise}, |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1969 | {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", "IBASE", "MB899", 0, OK, intel_ich_gpio26_raise}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1970 | {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455}, |
| 1971 | {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi}, |
Michael Karcher | 51cd0c9 | 2010-03-19 22:35:21 +0000 | [diff] [blame] | 1972 | {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1973 | {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e}, |
James Lancaster | 998c9dc | 2010-03-19 22:39:24 +0000 | [diff] [blame] | 1974 | {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1975 | {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, "Mitac", "6513WU", 0, OK, board_mitac_6513wu}, |
Uwe Hermann | ead705f | 2010-08-15 15:26:30 +0000 | [diff] [blame] | 1976 | {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, /* TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html. */ |
Mattias Mattsson | c8ca3de | 2010-09-13 18:22:36 +0000 | [diff] [blame] | 1977 | {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^MS-6163 (i440BX)$", NULL, NULL, "MSI", "MS-6163 (MS-6163 Pro)", 0, OK, intel_piix4_gpo14_raise}, |
Mattias Mattsson | e838824 | 2010-09-11 15:25:48 +0000 | [diff] [blame] | 1978 | {0x1039, 0x0745, 0, 0, 0x1039, 0x0018, 0, 0, "^MS-6561", NULL, NULL, "MSI", "MS-6561 (745 Ultra)", 0, OK, w836xx_memw_enable_2e}, |
Uwe Hermann | ead705f | 2010-08-15 15:26:30 +0000 | [diff] [blame] | 1979 | {0x8086, 0x2560, 0x1462, 0x5770, 0x8086, 0x2562, 0x1462, 0x5778, NULL, NULL, NULL, "MSI", "MS-6577 (Xenon)", 0, OK, w83627hf_gpio25_raise_2e}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1980 | {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v}, |
Michael Karcher | bcd80cd | 2010-06-27 15:07:49 +0000 | [diff] [blame] | 1981 | {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio44_raise_2e}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1982 | {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v}, |
Uwe Hermann | a347324 | 2010-09-14 22:59:39 +0000 | [diff] [blame] | 1983 | {0x1106, 0x3148, 0 , 0 , 0x1106, 0x3177, 0 , 0 , NULL, "msi", "ms6787", "MSI", "MS-6787 (P4MAM-V/P4MAM-L)", 0, OK, w836xx_memw_enable_2e}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1984 | {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml}, |
Michael Karcher | 5f31ebe | 2010-06-12 23:07:26 +0000 | [diff] [blame] | 1985 | {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1986 | {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise}, |
Uwe Hermann | 742999c | 2010-12-02 21:57:42 +0000 | [diff] [blame] | 1987 | {0x8086, 0x244b, 0x1462, 0x3910, 0x8086, 0x2442, 0x1462, 0x3910, NULL, NULL, NULL, "MSI", "MS-6391 (845 Pro4)", 0, OK, intel_ich_gpio23_raise}, |
Mattias Mattsson | e295eee | 2010-08-15 10:21:29 +0000 | [diff] [blame] | 1988 | {0x1106, 0x3149, 0x1462, 0x7061, 0x1106, 0x3227, 0, 0, NULL, NULL, NULL, "MSI", "MS-7061 (KM4M-V/KM4AM-V)", 0, OK, w836xx_memw_enable_2e}, |
Michael Karcher | bcd80cd | 2010-06-27 15:07:49 +0000 | [diff] [blame] | 1989 | {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio44_raise_4e}, |
Uwe Hermann | ead705f | 2010-08-15 15:26:30 +0000 | [diff] [blame] | 1990 | {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8NGM2-L)", 0, NT, nvidia_mcp_gpio2_raise}, |
Michael Karcher | b3fe2fc | 2010-05-24 16:03:57 +0000 | [diff] [blame] | 1991 | {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0}, |
Michael Karcher | 3b11252 | 2010-07-24 22:36:01 +0000 | [diff] [blame] | 1992 | {0x8086, 0x24d3, 0x144d, 0xb025, 0x8086, 0x1050, 0x144d, 0xb025, NULL, NULL, NULL, "Samsung", "Polaris 32", 0, OK, intel_ich_gpio21_raise}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1993 | {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e}, |
Carl-Daniel Hailfinger | 76d4b37 | 2010-07-10 16:56:32 +0000 | [diff] [blame] | 1994 | {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, NULL}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1995 | {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25}, |
Michael Karcher | 0647733 | 2010-03-19 22:49:09 +0000 | [diff] [blame] | 1996 | {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 1997 | {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, OK, NULL}, |
Daniel Brandt | 4ad4c74 | 2010-03-21 13:36:20 +0000 | [diff] [blame] | 1998 | {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e}, |
Peter Lemenkov | eb75ced | 2010-05-26 22:26:44 +0000 | [diff] [blame] | 1999 | {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e}, |
Michael Karcher | bcd2556 | 2010-06-12 17:27:44 +0000 | [diff] [blame] | 2000 | {0x1106, 0x0259, 0x1106, 0xAA07, 0x1106, 0x3227, 0x1106, 0xAA07, NULL, NULL, NULL, "VIA", "EPIA EK", 0, NT, via_vt823x_gpio9_raise}, |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 2001 | {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise}, |
| 2002 | {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise}, |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 2003 | #endif |
Michael Karcher | 0bdc092 | 2010-02-28 01:33:48 +0000 | [diff] [blame] | 2004 | { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */ |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 2005 | }; |
| 2006 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 2007 | /* |
Stefan Reinauer | e3f3e2e | 2008-01-18 15:33:10 +0000 | [diff] [blame] | 2008 | * Match boards on coreboot table gathered vendor and part name. |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 2009 | * Require main PCI IDs to match too as extra safety. |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 2010 | */ |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 2011 | static const struct board_pciid_enable *board_match_coreboot_name(const char *vendor, |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 2012 | const char *part) |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 2013 | { |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 2014 | const struct board_pciid_enable *board = board_pciid_enables; |
| 2015 | const struct board_pciid_enable *partmatch = NULL; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 2016 | |
Uwe Hermann | a93045c | 2009-05-09 00:47:04 +0000 | [diff] [blame] | 2017 | for (; board->vendor_name; board++) { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 2018 | if (vendor && (!board->lb_vendor |
| 2019 | || strcasecmp(board->lb_vendor, vendor))) |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 2020 | continue; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 2021 | |
Peter Stuge | 0b9c5f3 | 2008-07-02 00:47:30 +0000 | [diff] [blame] | 2022 | if (!board->lb_part || strcasecmp(board->lb_part, part)) |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 2023 | continue; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 2024 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 2025 | if (!pci_dev_find(board->first_vendor, board->first_device)) |
| 2026 | continue; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 2027 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 2028 | if (board->second_vendor && |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 2029 | !pci_dev_find(board->second_vendor, board->second_device)) |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 2030 | continue; |
Peter Stuge | 6b53fed | 2008-01-27 16:21:21 +0000 | [diff] [blame] | 2031 | |
| 2032 | if (vendor) |
| 2033 | return board; |
| 2034 | |
| 2035 | if (partmatch) { |
| 2036 | /* a second entry has a matching part name */ |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 2037 | msg_pinfo("AMBIGUOUS BOARD NAME: %s\n", part); |
| 2038 | msg_pinfo("At least vendors '%s' and '%s' match.\n", |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 2039 | partmatch->lb_vendor, board->lb_vendor); |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 2040 | msg_perr("Please use the full -m vendor:part syntax.\n"); |
Peter Stuge | 6b53fed | 2008-01-27 16:21:21 +0000 | [diff] [blame] | 2041 | return NULL; |
| 2042 | } |
| 2043 | partmatch = board; |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 2044 | } |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 2045 | |
Peter Stuge | 6b53fed | 2008-01-27 16:21:21 +0000 | [diff] [blame] | 2046 | if (partmatch) |
| 2047 | return partmatch; |
| 2048 | |
Carl-Daniel Hailfinger | bc25f94 | 2009-07-30 13:30:17 +0000 | [diff] [blame] | 2049 | if (!partvendor_from_cbtable) { |
| 2050 | /* Only warn if the mainboard type was not gathered from the |
| 2051 | * coreboot table. If it was, the coreboot implementor is |
| 2052 | * expected to fix flashrom, too. |
| 2053 | */ |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 2054 | msg_perr("\nUnknown vendor:board from -m option: %s:%s\n\n", |
Carl-Daniel Hailfinger | bc25f94 | 2009-07-30 13:30:17 +0000 | [diff] [blame] | 2055 | vendor, part); |
| 2056 | } |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 2057 | return NULL; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 2058 | } |
| 2059 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 2060 | /* |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 2061 | * Match boards on PCI IDs and subsystem IDs. |
| 2062 | * Second set of IDs can be main only or missing completely. |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 2063 | */ |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 2064 | const static struct board_pciid_enable *board_match_pci_card_ids(void) |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 2065 | { |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 2066 | const struct board_pciid_enable *board = board_pciid_enables; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 2067 | |
Uwe Hermann | a93045c | 2009-05-09 00:47:04 +0000 | [diff] [blame] | 2068 | for (; board->vendor_name; board++) { |
Michael Karcher | 2eab70d | 2010-02-04 10:58:50 +0000 | [diff] [blame] | 2069 | if ((!board->first_card_vendor || !board->first_card_device) && |
| 2070 | !board->dmi_pattern) |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 2071 | continue; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 2072 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 2073 | if (!pci_card_find(board->first_vendor, board->first_device, |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 2074 | board->first_card_vendor, |
| 2075 | board->first_card_device)) |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 2076 | continue; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 2077 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 2078 | if (board->second_vendor) { |
| 2079 | if (board->second_card_vendor) { |
| 2080 | if (!pci_card_find(board->second_vendor, |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 2081 | board->second_device, |
| 2082 | board->second_card_vendor, |
| 2083 | board->second_card_device)) |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 2084 | continue; |
| 2085 | } else { |
| 2086 | if (!pci_dev_find(board->second_vendor, |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 2087 | board->second_device)) |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 2088 | continue; |
| 2089 | } |
| 2090 | } |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 2091 | |
Michael Karcher | 6701ee8 | 2010-01-20 14:14:11 +0000 | [diff] [blame] | 2092 | if (board->dmi_pattern) { |
| 2093 | if (!has_dmi_support) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 2094 | msg_perr("WARNING: Can't autodetect %s %s," |
Michael Karcher | 6701ee8 | 2010-01-20 14:14:11 +0000 | [diff] [blame] | 2095 | " DMI info unavailable.\n", |
| 2096 | board->vendor_name, board->board_name); |
| 2097 | continue; |
| 2098 | } else { |
| 2099 | if (!dmi_match(board->dmi_pattern)) |
| 2100 | continue; |
| 2101 | } |
| 2102 | } |
| 2103 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 2104 | return board; |
| 2105 | } |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 2106 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 2107 | return NULL; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 2108 | } |
| 2109 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 2110 | int board_flash_enable(const char *vendor, const char *part) |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 2111 | { |
Carl-Daniel Hailfinger | ad3cc55 | 2010-07-03 11:02:10 +0000 | [diff] [blame] | 2112 | const struct board_pciid_enable *board = NULL; |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 2113 | int ret = 0; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 2114 | |
Peter Stuge | 6b53fed | 2008-01-27 16:21:21 +0000 | [diff] [blame] | 2115 | if (part) |
Stefan Reinauer | e3f3e2e | 2008-01-18 15:33:10 +0000 | [diff] [blame] | 2116 | board = board_match_coreboot_name(vendor, part); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 2117 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 2118 | if (!board) |
| 2119 | board = board_match_pci_card_ids(); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 2120 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 2121 | if (board && board->status == NT) { |
| 2122 | if (!force_boardenable) { |
| 2123 | msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n" |
| 2124 | "code has not been tested, and thus will not not be executed by default.\n" |
| 2125 | "Depending on your hardware environment, erasing, writing or even probing\n" |
| 2126 | "can fail without running the board specific code.\n\n" |
| 2127 | "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n" |
| 2128 | "\"internal programmer\") for details.\n", |
| 2129 | board->vendor_name, board->board_name); |
| 2130 | board = NULL; |
| 2131 | } else { |
| 2132 | msg_pinfo("NOTE: Running an untested board enable procedure.\n" |
Paul Menzel | ab6328f | 2010-10-08 11:03:02 +0000 | [diff] [blame] | 2133 | "Please report success/failure to flashrom@flashrom.org\n" |
| 2134 | "with your board name and SUCCESS or FAILURE in the subject.\n"); |
Uwe Hermann | 4395970 | 2010-03-13 17:28:29 +0000 | [diff] [blame] | 2135 | } |
Michael Karcher | 7f0c3ec | 2010-03-07 22:29:28 +0000 | [diff] [blame] | 2136 | } |
| 2137 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 2138 | if (board) { |
Luc Verhaegen | 93938c3 | 2010-01-20 14:45:03 +0000 | [diff] [blame] | 2139 | if (board->max_rom_decode_parallel) |
| 2140 | max_rom_decode.parallel = |
| 2141 | board->max_rom_decode_parallel * 1024; |
| 2142 | |
Uwe Hermann | b1bd3e8 | 2010-01-28 19:02:36 +0000 | [diff] [blame] | 2143 | if (board->enable != NULL) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 2144 | msg_pinfo("Disabling flash write protection for " |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 2145 | "board \"%s %s\"... ", board->vendor_name, |
| 2146 | board->board_name); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 2147 | |
Uwe Hermann | 36dec8b | 2010-06-07 19:06:26 +0000 | [diff] [blame] | 2148 | ret = board->enable(); |
Uwe Hermann | b1bd3e8 | 2010-01-28 19:02:36 +0000 | [diff] [blame] | 2149 | if (ret) |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 2150 | msg_pinfo("FAILED!\n"); |
Uwe Hermann | b1bd3e8 | 2010-01-28 19:02:36 +0000 | [diff] [blame] | 2151 | else |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 2152 | msg_pinfo("OK.\n"); |
Uwe Hermann | b1bd3e8 | 2010-01-28 19:02:36 +0000 | [diff] [blame] | 2153 | } |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 2154 | } |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 2155 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 2156 | return ret; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 2157 | } |