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Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +00006 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
Carl-Daniel Hailfinger92242622007-09-27 14:29:57 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000021 */
22
23/*
24 * Contains the board specific flash enables.
25 */
26
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000027#include <string.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000028#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000029#include "programmer.h"
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000030
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000031#if defined(__i386__) || defined(__x86_64__)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000032/*
Uwe Hermannffec5f32007-08-23 16:08:21 +000033 * Helper functions for many Winbond Super I/Os of the W836xx range.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000034 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000035/* Enter extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000036void w836xx_ext_enter(uint16_t port)
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000037{
Andriy Gapon65c1b862008-05-22 13:22:45 +000038 OUTB(0x87, port);
39 OUTB(0x87, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000040}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000041
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000042/* Leave extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000043void w836xx_ext_leave(uint16_t port)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000044{
Andriy Gapon65c1b862008-05-22 13:22:45 +000045 OUTB(0xAA, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000046}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000047
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000048/* Generic Super I/O helper functions */
49uint8_t sio_read(uint16_t port, uint8_t reg)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000050{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000051 OUTB(reg, port);
52 return INB(port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000053}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000054
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000055void sio_write(uint16_t port, uint8_t reg, uint8_t data)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000056{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000057 OUTB(reg, port);
58 OUTB(data, port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000059}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000060
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000061void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000062{
Ronald G. Minnichfa496922007-10-12 21:22:40 +000063 uint8_t tmp;
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000064
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000065 OUTB(reg, port);
66 tmp = INB(port + 1) & ~mask;
67 OUTB(tmp | (data & mask), port + 1);
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000068}
69
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000070/* Not used yet. */
71#if 0
72static int enable_flash_decode_superio(void)
73{
74 int ret;
75 uint8_t tmp;
76
77 switch (superio.vendor) {
78 case SUPERIO_VENDOR_NONE:
79 ret = -1;
80 break;
81 case SUPERIO_VENDOR_ITE:
82 enter_conf_mode_ite(superio.port);
Uwe Hermann43959702010-03-13 17:28:29 +000083 /* Enable flash mapping. Works for most old ITE style Super I/O. */
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000084 tmp = sio_read(superio.port, 0x24);
85 tmp |= 0xfc;
86 sio_write(superio.port, 0x24, tmp);
87 exit_conf_mode_ite(superio.port);
88 ret = 0;
89 break;
90 default:
Sean Nelson316a29f2010-05-07 20:09:04 +000091 msg_pdbg("Unhandled Super I/O type!\n");
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000092 ret = -1;
93 break;
94 }
95 return ret;
96}
97#endif
98
Uwe Hermann48ec1b12010-08-08 17:01:18 +000099/*
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000100 * SMSC FDC37B787: Raise GPIO50
101 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000102static int fdc37b787_gpio50_raise(uint16_t port)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000103{
104 uint8_t id, val;
105
106 OUTB(0x55, port); /* enter conf mode */
107 id = sio_read(port, 0x20);
108 if (id != 0x44) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000109 msg_perr("\nERROR: FDC37B787: Wrong ID 0x%02X.\n", id);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000110 OUTB(0xAA, port); /* leave conf mode */
111 return -1;
112 }
113
114 sio_write(port, 0x07, 0x08); /* Select Aux I/O subdevice */
115
116 val = sio_read(port, 0xC8); /* GP50 */
117 if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */
118 {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000119 msg_perr("\nERROR: GPIO50 mode 0x%02X unexpected.\n", val);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000120 OUTB(0xAA, port);
121 return -1;
122 }
123
124 sio_mask(port, 0xF9, 0x01, 0x01);
125
126 OUTB(0xAA, port); /* Leave conf mode */
127 return 0;
128}
129
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000130/*
131 * Suited for:
132 * - Nokia IP530: Intel 440BX + PIIX4 + FDC37B787
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000133 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000134static int fdc37b787_gpio50_raise_3f0(void)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000135{
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000136 return fdc37b787_gpio50_raise(0x3f0);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000137}
138
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000139struct winbond_mux {
140 uint8_t reg; /* 0 if the corresponding pin is not muxed */
141 uint8_t data; /* reg/data/mask may be directly ... */
142 uint8_t mask; /* ... passed to sio_mask */
143};
144
145struct winbond_port {
146 const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */
147 uint8_t ldn; /* LDN this GPIO register is located in */
148 uint8_t enable_bit; /* bit in 0x30 of that LDN to enable
149 the GPIO port */
150 uint8_t base; /* base register in that LDN for the port */
151};
152
153struct winbond_chip {
154 uint8_t device_id; /* reg 0x20 of the expected w83626x */
155 uint8_t gpio_port_count;
156 const struct winbond_port *port;
157};
158
159
160#define UNIMPLEMENTED_PORT {NULL, 0, 0, 0}
161
162enum winbond_id {
163 WINBOND_W83627HF_ID = 0x52,
Michael Karcherea36c9c2010-06-27 15:07:52 +0000164 WINBOND_W83627EHF_ID = 0x88,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000165 WINBOND_W83627THF_ID = 0x82,
166};
167
168static const struct winbond_mux w83627hf_port2_mux[8] = {
169 {0x2A, 0x01, 0x01}, /* or MIDI */
170 {0x2B, 0x80, 0x80}, /* or SPI */
171 {0x2B, 0x40, 0x40}, /* or SPI */
172 {0x2B, 0x20, 0x20}, /* or power LED */
173 {0x2B, 0x10, 0x10}, /* or watchdog */
174 {0x2B, 0x08, 0x08}, /* or infra red */
175 {0x2B, 0x04, 0x04}, /* or infra red */
176 {0x2B, 0x03, 0x03} /* or IRQ1 input */
177};
178
179static const struct winbond_port w83627hf[3] = {
180 UNIMPLEMENTED_PORT,
181 {w83627hf_port2_mux, 0x08, 0, 0xF0},
182 UNIMPLEMENTED_PORT
183};
184
Michael Karcherea36c9c2010-06-27 15:07:52 +0000185static const struct winbond_mux w83627ehf_port2_mux[8] = {
186 {0x29, 0x06, 0x02}, /* or MIDI */
187 {0x29, 0x06, 0x02},
188 {0x24, 0x02, 0x00}, /* or SPI ROM interface */
189 {0x24, 0x02, 0x00},
190 {0x2A, 0x01, 0x01}, /* or keyboard/mouse interface */
191 {0x2A, 0x01, 0x01},
192 {0x2A, 0x01, 0x01},
193 {0x2A, 0x01, 0x01}
194};
195
196static const struct winbond_port w83627ehf[6] = {
197 UNIMPLEMENTED_PORT,
198 {w83627ehf_port2_mux, 0x09, 0, 0xE3},
199 UNIMPLEMENTED_PORT,
200 UNIMPLEMENTED_PORT,
201 UNIMPLEMENTED_PORT,
202 UNIMPLEMENTED_PORT
203};
204
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000205static const struct winbond_mux w83627thf_port4_mux[8] = {
206 {0x2D, 0x01, 0x01}, /* or watchdog or VID level strap */
207 {0x2D, 0x02, 0x02}, /* or resume reset */
208 {0x2D, 0x04, 0x04}, /* or S3 input */
209 {0x2D, 0x08, 0x08}, /* or PSON# */
210 {0x2D, 0x10, 0x10}, /* or PWROK */
211 {0x2D, 0x20, 0x20}, /* or suspend LED */
212 {0x2D, 0x40, 0x40}, /* or panel switch input */
213 {0x2D, 0x80, 0x80} /* or panel switch output */
214};
215
216static const struct winbond_port w83627thf[5] = {
217 UNIMPLEMENTED_PORT, /* GPIO1 */
218 UNIMPLEMENTED_PORT, /* GPIO2 */
219 UNIMPLEMENTED_PORT, /* GPIO3 */
220 {w83627thf_port4_mux, 0x09, 1, 0xF4},
221 UNIMPLEMENTED_PORT /* GPIO5 */
222};
223
224static const struct winbond_chip winbond_chips[] = {
225 {WINBOND_W83627HF_ID, ARRAY_SIZE(w83627hf), w83627hf },
Michael Karcherea36c9c2010-06-27 15:07:52 +0000226 {WINBOND_W83627EHF_ID, ARRAY_SIZE(w83627ehf), w83627ehf},
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000227 {WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf},
228};
229
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000230/*
231 * Detects which Winbond Super I/O is responding at the given base address,
232 * but takes no effort to make sure the chip is really a Winbond Super I/O.
233 */
234static const struct winbond_chip *winbond_superio_detect(uint16_t base)
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000235{
236 uint8_t chipid;
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000237 const struct winbond_chip *chip = NULL;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000238 int i;
239
240 w836xx_ext_enter(base);
241 chipid = sio_read(base, 0x20);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000242
243 for (i = 0; i < ARRAY_SIZE(winbond_chips); i++) {
244 if (winbond_chips[i].device_id == chipid) {
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000245 chip = &winbond_chips[i];
246 break;
247 }
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000248 }
249
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000250 w836xx_ext_leave(base);
251 return chip;
252}
253
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000254/*
255 * The chipid parameter goes away as soon as we have Super I/O matching in the
256 * board enable table. The call to winbond_superio_detect() goes away as
257 * soon as we have generic Super I/O detection code.
258 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000259static int winbond_gpio_set(uint16_t base, enum winbond_id chipid,
260 int pin, int raise)
261{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000262 const struct winbond_chip *chip = NULL;
263 const struct winbond_port *gpio;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000264 int port = pin / 10;
265 int bit = pin % 10;
266
267 chip = winbond_superio_detect(base);
268 if (!chip) {
269 msg_perr("\nERROR: No supported Winbond Super I/O found\n");
270 return -1;
271 }
Michael Karcher979d9252010-06-29 14:44:40 +0000272 if (chip->device_id != chipid) {
273 msg_perr("\nERROR: Found Winbond chip with ID 0x%x, "
274 "expected %x\n", chip->device_id, chipid);
275 return -1;
276 }
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000277 if (bit >= 8 || port == 0 || port > chip->gpio_port_count) {
278 msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n",
279 pin);
280 return -1;
281 }
282
283 gpio = &chip->port[port - 1];
284
285 if (gpio->ldn == 0) {
286 msg_perr("\nERROR: GPIO%d is not supported yet on this"
287 " winbond chip\n", port);
288 return -1;
289 }
290
291 w836xx_ext_enter(base);
292
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000293 /* Select logical device. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000294 sio_write(base, 0x07, gpio->ldn);
295
296 /* Activate logical device. */
297 sio_mask(base, 0x30, 1 << gpio->enable_bit, 1 << gpio->enable_bit);
298
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000299 /* Select GPIO function of that pin. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000300 if (gpio->mux && gpio->mux[bit].reg)
301 sio_mask(base, gpio->mux[bit].reg,
302 gpio->mux[bit].data, gpio->mux[bit].mask);
303
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000304 sio_mask(base, gpio->base + 0, 0, 1 << bit); /* Make pin output */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000305 sio_mask(base, gpio->base + 2, 0, 1 << bit); /* Clear inversion */
306 sio_mask(base, gpio->base + 1, raise << bit, 1 << bit);
307
308 w836xx_ext_leave(base);
309
310 return 0;
311}
312
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000313/*
Uwe Hermannffec5f32007-08-23 16:08:21 +0000314 * Winbond W83627HF: Raise GPIO24.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000315 *
316 * Suited for:
Uwe Hermannffec5f32007-08-23 16:08:21 +0000317 * - Agami Aruma
318 * - IWILL DK8-HTX
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000319 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000320static int w83627hf_gpio24_raise_2e(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000321{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000322 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000323}
324
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000325/*
Joshua Roysf280a382010-08-07 21:49:11 +0000326 * Winbond W83627HF: Raise GPIO25.
327 *
328 * Suited for:
329 * - MSI MS-6577
330 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000331static int w83627hf_gpio25_raise_2e(void)
Joshua Roysf280a382010-08-07 21:49:11 +0000332{
333 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 25, 1);
334}
335
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000336/*
Michael Karcherea36c9c2010-06-27 15:07:52 +0000337 * Winbond W83627EHF: Raise GPIO24.
338 *
339 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000340 * - ASUS A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51
Michael Karcherea36c9c2010-06-27 15:07:52 +0000341 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000342static int w83627ehf_gpio24_raise_2e(void)
Michael Karcherea36c9c2010-06-27 15:07:52 +0000343{
344 return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 24, 1);
345}
346
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000347/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000348 * Winbond W83627THF: Raise GPIO 44.
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000349 *
350 * Suited for:
Peter Stugecce26822008-07-21 17:48:40 +0000351 * - MSI K8T Neo2-F
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000352 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000353static int w83627thf_gpio44_raise_2e(void)
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000354{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000355 return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000356}
357
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000358/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000359 * Winbond W83627THF: Raise GPIO 44.
360 *
361 * Suited for:
362 * - MSI K8N Neo3
363 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000364static int w83627thf_gpio44_raise_4e(void)
Peter Stugecce26822008-07-21 17:48:40 +0000365{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000366 return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000367}
Uwe Hermann372eeb52007-12-04 21:49:06 +0000368
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000369/*
David Borgb6417a62010-08-02 08:29:34 +0000370 * Enable MEMW# and set ROM size to max.
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000371 * Supported chips: W83L517D, W83697HF/F/HG, W83697SF/UF/UG
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000372 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000373static void w836xx_memw_enable(uint16_t port)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000374{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000375 w836xx_ext_enter(port);
376 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000377 /* Enable MEMW# and set ROM size select to max. (4M). */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000378 sio_mask(port, 0x24, 0x28, 0x28);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000379 }
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000380 w836xx_ext_leave(port);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000381}
382
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000383/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000384 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000385 * - EPoX EP-8K5A2: VIA KT333 + VT8235
386 * - Albatron PM266A Pro: VIA P4M266A + VT8235
387 * - Shuttle AK31 (all versions): VIA KT266 + VT8233
388 * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
389 * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237
Mattias Mattssone295eee2010-08-15 10:21:29 +0000390 * - MSI KM4M-V and KM4AM-V: VIA KM400/KM400A + VT8237
Mattias Mattssone8388242010-09-11 15:25:48 +0000391 * - MSI MS-6561 (745 Ultra): SiS 745 + W83697HF
Sergey A Lichackf3a4bff2010-09-07 18:14:53 +0000392 * - MSI MS-6787 (P4MAM-V/P4MAM-L): VIA P4M266 + VT8235
Uwe Hermann17da61e2010-10-05 21:48:43 +0000393 * - ASRock K7S41: SiS 741 + SiS 963 + W83697HF
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000394 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000395static int w836xx_memw_enable_2e(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000396{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000397 w836xx_memw_enable(0x2E);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000398
Luc Verhaegen73d21192009-12-23 00:54:26 +0000399 return 0;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000400}
401
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000402/*
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000403 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000404 * - Termtek TK-3370 (rev. 2.5b)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000405 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000406static int w836xx_memw_enable_4e(void)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000407{
408 w836xx_memw_enable(0x4E);
409
410 return 0;
411}
412
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000413/*
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000414 * Suited for all boards with ITE IT8705F.
415 * The SIS950 Super I/O probably requires a similar flash write enable.
Luc Verhaegen21f54962010-01-20 14:45:07 +0000416 */
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000417int it8705f_write_enable(uint8_t port)
Luc Verhaegen21f54962010-01-20 14:45:07 +0000418{
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000419 uint8_t tmp;
420 int ret = 0;
421
Luc Verhaegen21f54962010-01-20 14:45:07 +0000422 enter_conf_mode_ite(port);
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000423 tmp = sio_read(port, 0x24);
424 /* Check if at least one flash segment is enabled. */
425 if (tmp & 0xf0) {
426 /* The IT8705F will respond to LPC cycles and translate them. */
427 buses_supported = CHIP_BUSTYPE_PARALLEL;
428 /* Flash ROM I/F Writes Enable */
429 tmp |= 0x04;
430 msg_pdbg("Enabling IT8705F flash ROM interface write.\n");
431 if (tmp & 0x02) {
432 /* The data sheet contradicts itself about max size. */
433 max_rom_decode.parallel = 1024 * 1024;
434 msg_pinfo("IT8705F with very unusual settings. Please "
435 "send the output of \"flashrom -V\" to \n"
Paul Menzelab6328f2010-10-08 11:03:02 +0000436 "flashrom@flashrom.org with "
437 "IT8705: your board name: flashrom -V\n"
438 "as the subject to help us finish "
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000439 "support for your Super I/O. Thanks.\n");
440 ret = 1;
441 } else if (tmp & 0x08) {
442 max_rom_decode.parallel = 512 * 1024;
443 } else {
444 max_rom_decode.parallel = 256 * 1024;
445 }
446 /* Safety checks. The data sheet is unclear here: Segments 1+3
447 * overlap, no segment seems to cover top - 1MB to top - 512kB.
448 * We assume that certain combinations make no sense.
449 */
450 if (((tmp & 0x02) && !(tmp & 0x08)) || /* 1 MB en, 512 kB dis */
451 (!(tmp & 0x10)) || /* 128 kB dis */
452 (!(tmp & 0x40))) { /* 256/512 kB dis */
453 msg_perr("Inconsistent IT8705F decode size!\n");
454 ret = 1;
455 }
456 if (sio_read(port, 0x25) != 0) {
457 msg_perr("IT8705F flash data pins disabled!\n");
458 ret = 1;
459 }
460 if (sio_read(port, 0x26) != 0) {
461 msg_perr("IT8705F flash address pins 0-7 disabled!\n");
462 ret = 1;
463 }
464 if (sio_read(port, 0x27) != 0) {
465 msg_perr("IT8705F flash address pins 8-15 disabled!\n");
466 ret = 1;
467 }
468 if ((sio_read(port, 0x29) & 0x10) != 0) {
469 msg_perr("IT8705F flash write enable pin disabled!\n");
470 ret = 1;
471 }
472 if ((sio_read(port, 0x29) & 0x08) != 0) {
473 msg_perr("IT8705F flash chip select pin disabled!\n");
474 ret = 1;
475 }
476 if ((sio_read(port, 0x29) & 0x04) != 0) {
477 msg_perr("IT8705F flash read strobe pin disabled!\n");
478 ret = 1;
479 }
480 if ((sio_read(port, 0x29) & 0x03) != 0) {
481 msg_perr("IT8705F flash address pins 16-17 disabled!\n");
482 /* Not really an error if you use flash chips smaller
483 * than 256 kByte, but such a configuration is unlikely.
484 */
485 ret = 1;
486 }
487 msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n",
488 max_rom_decode.parallel);
489 if (ret) {
490 msg_pinfo("Not enabling IT8705F flash write.\n");
491 } else {
492 sio_write(port, 0x24, tmp);
493 }
494 } else {
495 msg_pdbg("No IT8705F flash segment enabled.\n");
496 /* Not sure if this is an error or not. */
497 ret = 0;
498 }
Luc Verhaegen21f54962010-01-20 14:45:07 +0000499 exit_conf_mode_ite(port);
500
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000501 return ret;
Luc Verhaegen21f54962010-01-20 14:45:07 +0000502}
Luc Verhaegen73d21192009-12-23 00:54:26 +0000503
Mattias Mattssonfb60cec2010-09-13 19:39:25 +0000504/*
505 * The ITE IT8707F is a custom chip made by ITE exclusively for ASUS.
506 * It uses the Winbond command sequence to enter extended configuration
507 * mode and the ITE sequence to exit.
508 *
509 * Registers seems similar to the ones on ITE IT8710F.
510 */
511static int it8707f_write_enable(uint8_t port)
512{
513 uint8_t tmp;
514
515 w836xx_ext_enter(port);
516
517 /* Set bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A rw */
518 tmp = sio_read(port, 0x23);
519 tmp |= (1 << 3);
520 sio_write(port, 0x23, tmp);
521
522 /* Set bit 2 (FLASH_WE) and bit 3 (FLASH_IF_EN) of reg 0x24 */
523 tmp = sio_read(port, 0x24);
524 tmp |= (1 << 2) | (1 << 3);
525 sio_write(port, 0x24, tmp);
526
527 /* Clear bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A ro */
528 tmp = sio_read(port, 0x23);
529 tmp &= ~(1 << 3);
530 sio_write(port, 0x23, tmp);
531
532 exit_conf_mode_ite(port);
533
534 return 0;
535}
536
537/*
538 * Suited for:
539 * - ASUS P4SC-E: SiS 651 + 962 + ITE IT8707F
540 */
541static int it8707f_write_enable_2e(void)
542{
543 return it8707f_write_enable(0x2e);
544}
545
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000546static int pc87360_gpio_set(uint8_t gpio, int raise)
547{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000548 static const int bankbase[] = {0, 4, 8, 10, 12};
549 int gpio_bank = gpio / 8;
550 int gpio_pin = gpio % 8;
551 uint16_t baseport;
552 uint8_t id, val;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000553
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000554 if (gpio_bank > 4) {
555 msg_perr("PC87360: Invalid GPIO %d\n", gpio);
556 return -1;
557 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000558
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000559 id = sio_read(0x2E, 0x20);
560 if (id != 0xE1) {
561 msg_perr("PC87360: unexpected ID %02x\n", id);
562 return -1;
563 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000564
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000565 sio_write(0x2E, 0x07, 0x07); /* Select GPIO device. */
566 baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
567 if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) {
568 msg_perr("PC87360: invalid GPIO base address %04x\n",
569 baseport);
570 return -1;
571 }
572 sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device. */
573 sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin);
574 sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output. */
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000575
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000576 val = INB(baseport + bankbase[gpio_bank]);
577 if (raise)
578 val |= 1 << gpio_pin;
579 else
580 val &= ~(1 << gpio_pin);
581 OUTB(val, baseport + bankbase[gpio_bank]);
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000582
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000583 return 0;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000584}
585
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000586/*
587 * VIA VT823x: Set one of the GPIO pins.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000588 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000589static int via_vt823x_gpio_set(uint8_t gpio, int raise)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000590{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000591 struct pci_dev *dev;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000592 uint16_t base;
David Bartleyf58d3642009-12-09 07:53:01 +0000593 uint8_t val, bit, offset;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000594
Luc Verhaegen73d21192009-12-23 00:54:26 +0000595 dev = pci_dev_find_vendorclass(0x1106, 0x0601);
596 switch (dev->device_id) {
597 case 0x3177: /* VT8235 */
598 case 0x3227: /* VT8237R */
599 case 0x3337: /* VT8237A */
600 break;
601 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000602 msg_perr("\nERROR: VT823x ISA bridge not found.\n");
Luc Verhaegen73d21192009-12-23 00:54:26 +0000603 return -1;
604 }
605
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000606 if ((gpio >= 12) && (gpio <= 15)) {
607 /* GPIO12-15 -> output */
608 val = pci_read_byte(dev, 0xE4);
609 val |= 0x10;
610 pci_write_byte(dev, 0xE4, val);
611 } else if (gpio == 9) {
612 /* GPIO9 -> Output */
613 val = pci_read_byte(dev, 0xE4);
614 val |= 0x20;
615 pci_write_byte(dev, 0xE4, val);
David Bartleyf58d3642009-12-09 07:53:01 +0000616 } else if (gpio == 5) {
617 val = pci_read_byte(dev, 0xE4);
618 val |= 0x01;
619 pci_write_byte(dev, 0xE4, val);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000620 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000621 msg_perr("\nERROR: "
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000622 "VT823x GPIO%02d is not implemented.\n", gpio);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000623 return -1;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000624 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000625
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000626 /* We need the I/O Base Address for this board's flash enable. */
627 base = pci_read_word(dev, 0x88) & 0xff80;
628
David Bartleyf58d3642009-12-09 07:53:01 +0000629 offset = 0x4C + gpio / 8;
630 bit = 0x01 << (gpio % 8);
631
632 val = INB(base + offset);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000633 if (raise)
634 val |= bit;
635 else
636 val &= ~bit;
David Bartleyf58d3642009-12-09 07:53:01 +0000637 OUTB(val, base + offset);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000638
Uwe Hermanna7e05482007-05-09 10:17:44 +0000639 return 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000640}
641
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000642/*
643 * Suited for:
644 * - ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000645 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000646static int via_vt823x_gpio5_raise(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000647{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000648 /* On M2V-MX: GPO5 is connected to WP# and TBL#. */
649 return via_vt823x_gpio_set(5, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000650}
651
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000652/*
653 * Suited for:
654 * - VIA EPIA EK & N & NL
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000655 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000656static int via_vt823x_gpio9_raise(void)
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000657{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000658 return via_vt823x_gpio_set(9, 1);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000659}
660
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000661/*
662 * Suited for:
663 * - VIA EPIA M and MII (and maybe other CLE266 based EPIAs)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000664 *
665 * We don't need to do this for EPIA M when using coreboot, GPIO15 is never
666 * lowered there.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000667 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000668static int via_vt823x_gpio15_raise(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000669{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000670 return via_vt823x_gpio_set(15, 1);
671}
672
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000673/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000674 * Winbond W83697HF Super I/O + VIA VT8235 southbridge
675 *
676 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000677 * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
678 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
Luc Verhaegen73d21192009-12-23 00:54:26 +0000679 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000680static int board_msi_kt4v(void)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000681{
682 int ret;
683
684 ret = via_vt823x_gpio_set(12, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000685 w836xx_memw_enable(0x2E);
Luc Verhaegen97866082008-02-09 02:03:06 +0000686
Luc Verhaegen73d21192009-12-23 00:54:26 +0000687 return ret;
Luc Verhaegen97866082008-02-09 02:03:06 +0000688}
689
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000690/*
691 * Suited for:
692 * - ASUS P5A
Luc Verhaegen6b141752007-05-20 16:16:13 +0000693 *
694 * This is rather nasty code, but there's no way to do this cleanly.
695 * We're basically talking to some unknown device on SMBus, my guess
696 * is that it is the Winbond W83781D that lives near the DIP BIOS.
697 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000698static int board_asus_p5a(void)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000699{
700 uint8_t tmp;
701 int i;
702
703#define ASUSP5A_LOOP 5000
704
Andriy Gapon65c1b862008-05-22 13:22:45 +0000705 OUTB(0x00, 0xE807);
706 OUTB(0xEF, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000707
Andriy Gapon65c1b862008-05-22 13:22:45 +0000708 OUTB(0xFF, 0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000709
710 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000711 OUTB(0xE1, 0xFF);
712 if (INB(0xE800) & 0x04)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000713 break;
714 }
715
716 if (i == ASUSP5A_LOOP) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000717 msg_perr("Unable to contact device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000718 return -1;
719 }
720
Andriy Gapon65c1b862008-05-22 13:22:45 +0000721 OUTB(0x20, 0xE801);
722 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000723
Andriy Gapon65c1b862008-05-22 13:22:45 +0000724 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000725
726 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000727 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000728 if (tmp & 0x70)
729 break;
730 }
731
732 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000733 msg_perr("Failed to read device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000734 return -1;
735 }
736
Andriy Gapon65c1b862008-05-22 13:22:45 +0000737 tmp = INB(0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000738 tmp &= ~0x02;
739
Andriy Gapon65c1b862008-05-22 13:22:45 +0000740 OUTB(0x00, 0xE807);
741 OUTB(0xEE, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000742
Andriy Gapon65c1b862008-05-22 13:22:45 +0000743 OUTB(tmp, 0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000744
Andriy Gapon65c1b862008-05-22 13:22:45 +0000745 OUTB(0xFF, 0xE800);
746 OUTB(0xE1, 0xFF);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000747
Andriy Gapon65c1b862008-05-22 13:22:45 +0000748 OUTB(0x20, 0xE801);
749 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000750
Andriy Gapon65c1b862008-05-22 13:22:45 +0000751 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000752
753 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000754 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000755 if (tmp & 0x70)
756 break;
757 }
758
759 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000760 msg_perr("Failed to write to device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000761 return -1;
762 }
763
764 return 0;
765}
766
Luc Verhaegena7e30502009-12-09 11:39:02 +0000767/*
768 * Set GPIO lines in the Broadcom HT-1000 southbridge.
769 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000770 * It's not a Super I/O but it uses the same index/data port method.
Luc Verhaegena7e30502009-12-09 11:39:02 +0000771 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000772static int board_hp_dl145_g3_enable(void)
Luc Verhaegena7e30502009-12-09 11:39:02 +0000773{
774 /* GPIO 0 reg from PM regs */
775 /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
776 sio_mask(0xcd6, 0x44, 0x24, 0x24);
777
778 return 0;
779}
780
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +0000781/*
782 * Set GPIO lines in the Broadcom HT-1000 southbridge.
783 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000784 * It's not a Super I/O but it uses the same index/data port method.
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +0000785 */
786static int board_hp_dl165_g6_enable(void)
787{
788 /* Variant of DL145, with slightly different pin placement. */
789 sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */
790 sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */
791
792 return 0;
793}
794
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000795static int board_ibm_x3455(void)
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000796{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000797 /* Raise GPIO13. */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +0000798 sio_mask(0xcd6, 0x45, 0x20, 0x20);
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000799
800 return 0;
801}
802
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000803/*
804 * Suited for:
805 * - Shuttle FN25 (SN25P): AMD S939 + NVIDIA CK804 (nForce4)
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000806 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000807static int board_shuttle_fn25(void)
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000808{
809 struct pci_dev *dev;
810
811 dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA Bridge. */
812 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000813 msg_perr("\nERROR: NVIDIA nForce4 ISA bridge not found.\n");
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000814 return -1;
815 }
816
817 /* one of those bits seems to be connected to TBL#, but -ENOINFO. */
818 pci_write_byte(dev, 0x92, 0);
819
820 return 0;
821}
822
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000823/*
Mattias Mattssonf4925162010-09-16 22:09:18 +0000824 * Suited for:
825 * - Elitegroup GeForce6100SM-M: NVIDIA MCP61 + ITE IT8726F
826 */
Mattias Mattssonf4925162010-09-16 22:09:18 +0000827static int board_ecs_geforce6100sm_m(void)
828{
829 struct pci_dev *dev;
830 uint32_t tmp;
831
832 dev = pci_dev_find(0x10DE, 0x03EB); /* NVIDIA MCP61 SMBus. */
833 if (!dev) {
834 msg_perr("\nERROR: NVIDIA MCP61 SMBus not found.\n");
835 return -1;
836 }
837
838 tmp = pci_read_byte(dev, 0xE0);
839 tmp &= ~(1 << 3);
840 pci_write_byte(dev, 0xE0, tmp);
841
842 return 0;
843}
844
845/*
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000846 * Very similar to AMD 8111 IO Hub.
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000847 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000848static int nvidia_mcp_gpio_set(int gpio, int raise)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000849{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000850 struct pci_dev *dev;
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000851 uint16_t base;
Michael Karcher2ead2e22010-06-01 16:09:06 +0000852 uint16_t devclass;
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000853 uint8_t tmp;
854
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000855 if ((gpio < 0) || (gpio >= 0x40)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000856 msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000857 return -1;
858 }
859
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000860 /* First, check the ISA Bridge */
861 dev = pci_dev_find_vendorclass(0x10DE, 0x0601);
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000862 switch (dev->device_id) {
863 case 0x0030: /* CK804 */
864 case 0x0050: /* MCP04 */
865 case 0x0060: /* MCP2 */
Michael Karcher5f31ebe2010-06-12 23:07:26 +0000866 case 0x00E0: /* CK8 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000867 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +0000868 case 0x0260: /* MCP51 */
869 case 0x0364: /* MCP55 */
870 /* find SMBus controller on *this* southbridge */
871 /* The infamous Tyan S2915-E has two south bridges; they are
872 easily told apart from each other by the class of the
873 LPC bridge, but have the same SMBus bridge IDs */
874 if (dev->func != 0) {
875 msg_perr("MCP LPC bridge at unexpected function"
876 " number %d\n", dev->func);
877 return -1;
878 }
879
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +0000880#if PCI_LIB_VERSION >= 0x020200
Michael Karcher2ead2e22010-06-01 16:09:06 +0000881 dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1);
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +0000882#else
883 /* pciutils/libpci before version 2.2 is too old to support
884 * PCI domains. Such old machines usually don't have domains
885 * besides domain 0, so this is not a problem.
886 */
887 dev = pci_get_dev(pacc, dev->bus, dev->dev, 1);
888#endif
Michael Karcher2ead2e22010-06-01 16:09:06 +0000889 if (!dev) {
890 msg_perr("MCP SMBus controller could not be found\n");
891 return -1;
892 }
893 devclass = pci_read_word(dev, PCI_CLASS_DEVICE);
894 if (devclass != 0x0C05) {
895 msg_perr("Unexpected device class %04x for SMBus"
896 " controller\n", devclass);
897 return -1;
898 }
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000899 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +0000900 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000901 msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n");
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000902 return -1;
903 }
904
905 base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
906 base += 0xC0;
907
908 tmp = INB(base + gpio);
909 tmp &= ~0x0F; /* null lower nibble */
910 tmp |= 0x04; /* gpio -> output. */
911 if (raise)
912 tmp |= 0x01;
913 OUTB(tmp, base + gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000914
915 return 0;
916}
917
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000918/*
919 * Suited for:
Sean Nelson0a247512010-08-15 14:36:18 +0000920 * - ASUS A8N-LA (HP OEM "Nagami-GL8E"): NVIDIA MCP51
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000921 * - ASUS M2NBP-VM CSM: NVIDIA MCP51
Michael Karcherb2184c12010-03-07 16:42:55 +0000922 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000923static int nvidia_mcp_gpio0_raise(void)
Michael Karcherb2184c12010-03-07 16:42:55 +0000924{
925 return nvidia_mcp_gpio_set(0x00, 1);
926}
927
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000928/*
929 * Suited for:
930 * - abit KN8 Ultra: NVIDIA CK804
Sean Nelson92bc6bd2010-03-19 22:37:29 +0000931 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000932static int nvidia_mcp_gpio2_lower(void)
Sean Nelson92bc6bd2010-03-19 22:37:29 +0000933{
934 return nvidia_mcp_gpio_set(0x02, 0);
935}
936
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000937/*
938 * Suited for:
Uwe Hermannead705f2010-08-15 15:26:30 +0000939 * - MSI K8N Neo4: NVIDIA CK804. TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html.
940 * - MSI K8NGM2-L: NVIDIA MCP51
Luc Verhaegen6c5f7332009-12-23 03:01:36 +0000941 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000942static int nvidia_mcp_gpio2_raise(void)
Luc Verhaegen6c5f7332009-12-23 03:01:36 +0000943{
944 return nvidia_mcp_gpio_set(0x02, 1);
945}
946
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000947/*
948 * Suited for:
Uwe Hermann83d349a2010-10-18 22:32:03 +0000949 * - EPoX EP-8NPA7I: Socket 754 + NVIDIA nForce4 4X
Jonathan Kollaschf8db9592010-10-15 23:02:15 +0000950 */
951static int nvidia_mcp_gpio4_raise(void)
952{
953 return nvidia_mcp_gpio_set(0x04, 1);
954}
955
956/*
957 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000958 * - HP xw9400 (Tyan S2915-E OEM): Dual(!) NVIDIA MCP55
959 *
960 * Notes: a) There are two MCP55 chips, so also two SMBus bridges on that
961 * board. We can't tell the SMBus logical devices apart, but we
962 * can tell the LPC bridge functions apart.
963 * We need to choose the SMBus bridge next to the LPC bridge with
964 * ID 0x364 and the "LPC bridge" class.
965 * b) #TBL is hardwired on that board to a pull-down. It can be
966 * overridden by connecting the two solder points next to F2.
Michael Karcher2ead2e22010-06-01 16:09:06 +0000967 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000968static int nvidia_mcp_gpio5_raise(void)
Michael Karcher2ead2e22010-06-01 16:09:06 +0000969{
970 return nvidia_mcp_gpio_set(0x05, 1);
971}
972
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000973/*
974 * Suited for:
975 * - abit NF7-S: NVIDIA CK804
Michael Karcher8f10d242010-04-11 21:01:06 +0000976 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000977static int nvidia_mcp_gpio8_raise(void)
Michael Karcher8f10d242010-04-11 21:01:06 +0000978{
979 return nvidia_mcp_gpio_set(0x08, 1);
980}
981
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000982/*
983 * Suited for:
984 * - MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + CK8
Michael Karcher5f31ebe2010-06-12 23:07:26 +0000985 */
Michael Karcher51825082010-06-12 23:14:03 +0000986static int nvidia_mcp_gpio0c_raise(void)
Michael Karcher5f31ebe2010-06-12 23:07:26 +0000987{
988 return nvidia_mcp_gpio_set(0x0c, 1);
989}
990
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000991/*
992 * Suited for:
993 * - abit NF-M2 nView: Socket AM2 + NVIDIA MCP51
Michael Karcherefd8af32010-07-24 22:50:54 +0000994 */
995static int nvidia_mcp_gpio4_lower(void)
996{
997 return nvidia_mcp_gpio_set(0x04, 0);
998}
999
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001000/*
1001 * Suited for:
1002 * - ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001003 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001004static int nvidia_mcp_gpio10_raise(void)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001005{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001006 return nvidia_mcp_gpio_set(0x10, 1);
1007}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001008
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001009/*
1010 * Suited for:
1011 * - GIGABYTE GA-K8N-SLI: AMD socket 939 + NVIDIA CK804 + ITE IT8712F
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001012 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001013static int nvidia_mcp_gpio21_raise(void)
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001014{
1015 return nvidia_mcp_gpio_set(0x21, 0x01);
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001016}
1017
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001018/*
1019 * Suited for:
1020 * - EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001021 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001022static int nvidia_mcp_gpio31_raise(void)
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001023{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001024 return nvidia_mcp_gpio_set(0x31, 0x01);
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001025}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001026
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001027/*
1028 * Suited for:
Joshua Roys2ee137f2010-09-07 17:52:09 +00001029 * - GIGABYTE GA-K8N51GMF-9
1030 */
1031static int nvidia_mcp_gpio3b_raise(void)
1032{
1033 return nvidia_mcp_gpio_set(0x3b, 1);
1034}
1035
1036/*
1037 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001038 * - Artec Group DBE61 and DBE62
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001039 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001040static int board_artecgroup_dbe6x(void)
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001041{
1042#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001043#define DBE6x_PRI_BOOT_LOC_SHIFT 2
1044#define DBE6x_BOOT_OP_LATCHED_SHIFT 8
1045#define DBE6x_SEC_BOOT_LOC_SHIFT 10
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001046#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
1047#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
1048#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001049#define DBE6x_BOOT_LOC_FLASH 2
1050#define DBE6x_BOOT_LOC_FWHUB 3
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001051
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001052 msr_t msr;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001053 unsigned long boot_loc;
1054
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001055 /* Geode only has a single core */
1056 if (setup_cpu_msr(0))
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001057 return -1;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001058
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001059 msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001060
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001061 if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) ==
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001062 (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
1063 boot_loc = DBE6x_BOOT_LOC_FWHUB;
1064 else
1065 boot_loc = DBE6x_BOOT_LOC_FLASH;
1066
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001067 msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
1068 msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
Uwe Hermann394131e2008-10-18 21:14:13 +00001069 (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001070
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001071 wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001072
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001073 cleanup_cpu_msr();
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001074
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001075 return 0;
1076}
1077
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001078/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001079 * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}.
Luc Verhaegenf5226912009-12-14 10:41:58 +00001080 */
1081static int intel_piix4_gpo_set(unsigned int gpo, int raise)
1082{
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001083 unsigned int gpo_byte, gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001084 struct pci_dev *dev;
1085 uint32_t tmp, base;
1086
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001087 static const uint32_t nonmuxed_gpos = 0x58000101; /* GPPO {0,8,27,28,30} are always available */
1088
1089 static const struct {unsigned int reg, mask, value; } piix4_gpo[] = {
1090 {0},
1091 {0xB0, 0x0001, 0x0000}, /* GPO1... */
1092 {0xB0, 0x0001, 0x0000},
1093 {0xB0, 0x0001, 0x0000},
1094 {0xB0, 0x0001, 0x0000},
1095 {0xB0, 0x0001, 0x0000},
1096 {0xB0, 0x0001, 0x0000},
1097 {0xB0, 0x0001, 0x0000}, /* ...GPO7: GENCFG bit 0 */
1098 {0},
1099 {0xB0, 0x0100, 0x0000}, /* GPO9: GENCFG bit 8 */
1100 {0xB0, 0x0200, 0x0000}, /* GPO10: GENCFG bit 9 */
1101 {0xB0, 0x0400, 0x0000}, /* GPO11: GENCFG bit 10 */
1102 {0x4E, 0x0100, 0x0000}, /* GPO12... */
1103 {0x4E, 0x0100, 0x0000},
1104 {0x4E, 0x0100, 0x0000}, /* ...GPO14: XBCS bit 8 */
1105 {0xB2, 0x0002, 0x0002}, /* GPO15... */
1106 {0xB2, 0x0002, 0x0002}, /* ...GPO16: GENCFG bit 17 */
1107 {0xB2, 0x0004, 0x0004}, /* GPO17: GENCFG bit 18 */
1108 {0xB2, 0x0008, 0x0008}, /* GPO18: GENCFG bit 19 */
1109 {0xB2, 0x0010, 0x0010}, /* GPO19: GENCFG bit 20 */
1110 {0xB2, 0x0020, 0x0020}, /* GPO20: GENCFG bit 21 */
1111 {0xB2, 0x0040, 0x0040}, /* GPO21: GENCFG bit 22 */
1112 {0xB2, 0x1000, 0x1000}, /* GPO22... */
1113 {0xB2, 0x1000, 0x1000}, /* ...GPO23: GENCFG bit 28 */
1114 {0xB2, 0x2000, 0x2000}, /* GPO24: GENCFG bit 29 */
1115 {0xB2, 0x4000, 0x4000}, /* GPO25: GENCFG bit 30 */
1116 {0xB2, 0x8000, 0x8000}, /* GPO26: GENCFG bit 31 */
1117 {0},
1118 {0},
1119 {0x4E, 0x0100, 0x0000}, /* ...GPO29: XBCS bit 8 */
1120 {0}
1121 };
1122
1123
Luc Verhaegenf5226912009-12-14 10:41:58 +00001124 dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */
1125 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001126 msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001127 return -1;
1128 }
1129
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001130 /* Sanity check. */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001131 if (gpo > 30) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001132 msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001133 return -1;
1134 }
1135
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001136 if ( (((1 << gpo) & nonmuxed_gpos) == 0) &&
1137 (pci_read_word(dev, piix4_gpo[gpo].reg) & piix4_gpo[gpo].mask) != piix4_gpo[gpo].value ) {
Peter Huewe3d3fd6a2011-01-25 00:23:32 +00001138 msg_perr("\nERROR: PIIX4 GPO%d not programmed for output.\n", gpo);
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001139 return -1;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001140 }
1141
Luc Verhaegenf5226912009-12-14 10:41:58 +00001142 dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */
1143 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001144 msg_perr("\nERROR: Intel PIIX4 PM not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001145 return -1;
1146 }
1147
1148 /* PM IO base */
1149 base = pci_read_long(dev, 0x40) & 0x0000FFC0;
1150
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001151 gpo_byte = gpo >> 3;
1152 gpo_bit = gpo & 7;
1153 tmp = INB(base + 0x34 + gpo_byte); /* GPO register */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001154 if (raise)
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001155 tmp |= 0x01 << gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001156 else
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001157 tmp &= ~(0x01 << gpo_bit);
1158 OUTB(tmp, base + 0x34 + gpo_byte);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001159
1160 return 0;
1161}
1162
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001163/*
1164 * Suited for:
Mattias Mattsson85016b92010-09-01 01:21:34 +00001165 * - ASUS P2B-N
1166 */
1167static int intel_piix4_gpo18_lower(void)
1168{
1169 return intel_piix4_gpo_set(18, 0);
1170}
1171
1172/*
1173 * Suited for:
Mattias Mattssonc8ca3de2010-09-13 18:22:36 +00001174 * - MSI MS-6163 v2 (MS-6163 Pro): Intel 440BX + PIIX4E + Winbond W83977EF
1175 */
1176static int intel_piix4_gpo14_raise(void)
1177{
1178 return intel_piix4_gpo_set(14, 1);
1179}
1180
1181/*
1182 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001183 * - EPoX EP-BX3
Luc Verhaegenf5226912009-12-14 10:41:58 +00001184 */
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001185static int intel_piix4_gpo22_raise(void)
Luc Verhaegenf5226912009-12-14 10:41:58 +00001186{
1187 return intel_piix4_gpo_set(22, 1);
1188}
1189
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001190/*
1191 * Suited for:
Tim ter Laak4b933f02010-09-13 23:00:57 +00001192 * - abit BM6
1193 */
1194static int intel_piix4_gpo26_lower(void)
1195{
1196 return intel_piix4_gpo_set(26, 0);
1197}
1198
1199/*
1200 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001201 * - Intel SE440BX-2
Michael Karcher51cd0c92010-03-19 22:35:21 +00001202 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001203static int intel_piix4_gpo27_lower(void)
Michael Karcher51cd0c92010-03-19 22:35:21 +00001204{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001205 return intel_piix4_gpo_set(27, 0);
Michael Karcher51cd0c92010-03-19 22:35:21 +00001206}
1207
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001208/*
Mattias Mattsson2eaad632010-10-05 21:32:29 +00001209 * Suited for:
1210 * - Dell OptiPlex GX1
1211 */
1212static int intel_piix4_gpo30_lower(void)
1213{
1214 return intel_piix4_gpo_set(30, 0);
1215}
1216
1217/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001218 * Set a GPIO line on a given Intel ICH LPC controller.
Uwe Hermann93f66db2008-05-22 21:19:38 +00001219 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001220static int intel_ich_gpio_set(int gpio, int raise)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001221{
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001222 /* Table mapping the different Intel ICH LPC chipsets. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001223 static struct {
1224 uint16_t id;
1225 uint8_t base_reg;
1226 uint32_t bank0;
1227 uint32_t bank1;
1228 uint32_t bank2;
1229 } intel_ich_gpio_table[] = {
1230 {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */
1231 {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */
1232 {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */
1233 {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */
1234 {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */
1235 {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */
1236 {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */
1237 {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */
1238 {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */
1239 {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */
1240 {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */
1241 {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */
1242 {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */
1243 {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */
1244 {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */
1245 {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */
1246 {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */
1247 {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */
1248 {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */
1249 {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */
1250 {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */
1251 {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */
1252 {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */
1253 {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */
1254 {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */
1255 {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */
1256 {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */
1257 {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */
1258 {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */
1259 {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */
1260 {0, 0, 0, 0, 0} /* end marker */
1261 };
Uwe Hermann93f66db2008-05-22 21:19:38 +00001262
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001263 struct pci_dev *dev;
1264 uint16_t base;
1265 uint32_t tmp;
1266 int i, allowed;
1267
1268 /* First, look for a known LPC bridge */
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001269 for (dev = pacc->devices; dev; dev = dev->next) {
Carl-Daniel Hailfingerd175e062010-05-21 23:00:56 +00001270 uint16_t device_class;
1271 /* libpci before version 2.2.4 does not store class info. */
1272 device_class = pci_read_word(dev, PCI_CLASS_DEVICE);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001273 if ((dev->vendor_id == 0x8086) &&
Carl-Daniel Hailfingerd175e062010-05-21 23:00:56 +00001274 (device_class == 0x0601)) { /* ISA Bridge */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001275 /* Is this device in our list? */
1276 for (i = 0; intel_ich_gpio_table[i].id; i++)
1277 if (dev->device_id == intel_ich_gpio_table[i].id)
1278 break;
1279
1280 if (intel_ich_gpio_table[i].id)
1281 break;
1282 }
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001283 }
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001284
Uwe Hermann93f66db2008-05-22 21:19:38 +00001285 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001286 msg_perr("\nERROR: No Known Intel LPC Bridge found.\n");
Uwe Hermann93f66db2008-05-22 21:19:38 +00001287 return -1;
1288 }
1289
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001290 /*
1291 * According to the datasheets, all Intel ICHs have the GPIO bar 5:1
1292 * strapped to zero. From some mobile ICH9 version on, this becomes
1293 * 6:1. The mask below catches all.
1294 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001295 base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
Uwe Hermann93f66db2008-05-22 21:19:38 +00001296
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001297 /* Check whether the line is allowed. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001298 if (gpio < 32)
1299 allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01;
1300 else if (gpio < 64)
1301 allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01;
1302 else
1303 allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;
1304
1305 if (!allowed) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001306 msg_perr("\nERROR: This Intel LPC Bridge does not allow"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001307 " setting GPIO%02d\n", gpio);
1308 return -1;
1309 }
1310
Sean Nelson316a29f2010-05-07 20:09:04 +00001311 msg_pdbg("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n",
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001312 raise ? "Rais" : "Dropp", gpio);
1313
1314 if (gpio < 32) {
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001315 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001316 tmp = INL(base);
1317 /* ICH/ICH0 multiplexes 27/28 on the line set. */
1318 if ((gpio == 28) &&
1319 ((dev->device_id == 0x2410) || (dev->device_id == 0x2420)))
1320 tmp |= 1 << 27;
1321 else
1322 tmp |= 1 << gpio;
1323 OUTL(tmp, base);
1324
1325 /* As soon as we are talking to ICH8 and above, this register
1326 decides whether we can set the gpio or not. */
1327 if (dev->device_id > 0x2800) {
1328 tmp = INL(base);
1329 if (!(tmp & (1 << gpio))) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001330 msg_perr("\nERROR: This Intel LPC Bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001331 " does not allow setting GPIO%02d\n",
1332 gpio);
1333 return -1;
1334 }
1335 }
1336
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001337 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001338 tmp = INL(base + 0x04);
1339 tmp &= ~(1 << gpio);
1340 OUTL(tmp, base + 0x04);
1341
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001342 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001343 tmp = INL(base + 0x0C);
1344 if (raise)
1345 tmp |= 1 << gpio;
1346 else
1347 tmp &= ~(1 << gpio);
1348 OUTL(tmp, base + 0x0C);
1349 } else if (gpio < 64) {
1350 gpio -= 32;
1351
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001352 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001353 tmp = INL(base + 0x30);
1354 tmp |= 1 << gpio;
1355 OUTL(tmp, base + 0x30);
1356
1357 /* As soon as we are talking to ICH8 and above, this register
1358 decides whether we can set the gpio or not. */
1359 if (dev->device_id > 0x2800) {
1360 tmp = INL(base + 30);
1361 if (!(tmp & (1 << gpio))) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001362 msg_perr("\nERROR: This Intel LPC Bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001363 " does not allow setting GPIO%02d\n",
1364 gpio + 32);
1365 return -1;
1366 }
1367 }
1368
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001369 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001370 tmp = INL(base + 0x34);
1371 tmp &= ~(1 << gpio);
1372 OUTL(tmp, base + 0x34);
1373
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001374 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001375 tmp = INL(base + 0x38);
1376 if (raise)
1377 tmp |= 1 << gpio;
1378 else
1379 tmp &= ~(1 << gpio);
1380 OUTL(tmp, base + 0x38);
1381 } else {
1382 gpio -= 64;
1383
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001384 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001385 tmp = INL(base + 0x40);
1386 tmp |= 1 << gpio;
1387 OUTL(tmp, base + 0x40);
1388
1389 tmp = INL(base + 40);
1390 if (!(tmp & (1 << gpio))) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001391 msg_perr("\nERROR: This Intel LPC Bridge does "
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001392 "not allow setting GPIO%02d\n", gpio + 64);
1393 return -1;
1394 }
1395
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001396 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001397 tmp = INL(base + 0x44);
1398 tmp &= ~(1 << gpio);
1399 OUTL(tmp, base + 0x44);
1400
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001401 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001402 tmp = INL(base + 0x48);
1403 if (raise)
1404 tmp |= 1 << gpio;
1405 else
1406 tmp &= ~(1 << gpio);
1407 OUTL(tmp, base + 0x48);
1408 }
Uwe Hermann93f66db2008-05-22 21:19:38 +00001409
1410 return 0;
1411}
1412
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001413/*
1414 * Suited for:
1415 * - abit IP35: Intel P35 + ICH9R
1416 * - abit IP35 Pro: Intel P35 + ICH9R
Uwe Hermann93f66db2008-05-22 21:19:38 +00001417 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001418static int intel_ich_gpio16_raise(void)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001419{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001420 return intel_ich_gpio_set(16, 1);
Uwe Hermann93f66db2008-05-22 21:19:38 +00001421}
1422
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001423/*
1424 * Suited for:
1425 * - HP Puffer2-UL8E (ASUS PTGD-LA OEM): LGA775 + 915 + ICH6
Michael Karchere57957c2010-07-24 11:14:37 +00001426 */
1427static int intel_ich_gpio18_raise(void)
1428{
1429 return intel_ich_gpio_set(18, 1);
1430}
1431
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001432/*
1433 * Suited for:
Uwe Hermannead705f2010-08-15 15:26:30 +00001434 * - ASUS A8Jm (laptop): Intel 945 + ICH7
James Lancaster998c9dc2010-03-19 22:39:24 +00001435 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001436static int intel_ich_gpio34_raise(void)
James Lancaster998c9dc2010-03-19 22:39:24 +00001437{
1438 return intel_ich_gpio_set(34, 1);
1439}
1440
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001441/*
1442 * Suited for:
1443 * - MSI MS-7046: LGA775 + 915P + ICH6
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001444 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001445static int intel_ich_gpio19_raise(void)
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001446{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001447 return intel_ich_gpio_set(19, 1);
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001448}
1449
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001450/*
Luc Verhaegen6c5d4cc2009-11-28 18:26:21 +00001451 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001452 * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2
1453 * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5
Michael Karcherf4b58792010-09-10 14:54:18 +00001454 * - ASUS P4P800: Intel socket478 + 865PE + ICH5R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001455 * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R
Michael Karcher4a23e442010-09-10 14:46:46 +00001456 * - ASUS P5GD1 Pro: Intel LGA 775 + 915P + ICH6R
Joshua Roysb1d980f2010-09-13 14:02:22 +00001457 * - ASUS P5GDC Deluxe: Intel socket775 + 915P + ICH6R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001458 * - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5
1459 * - Samsung Polaris 32: socket478 + 865P + ICH5
Peter Stuge09c13332009-02-02 22:55:26 +00001460 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001461static int intel_ich_gpio21_raise(void)
Peter Stuge09c13332009-02-02 22:55:26 +00001462{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001463 return intel_ich_gpio_set(21, 1);
Peter Stuge09c13332009-02-02 22:55:26 +00001464}
1465
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001466/*
Michael Karcher03b80e92010-03-07 16:32:32 +00001467 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001468 * - ASUS P4B266: socket478 + Intel 845D + ICH2
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001469 * - ASUS P4B533-E: socket478 + 845E + ICH4
1470 * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001471 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001472static int intel_ich_gpio22_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001473{
1474 return intel_ich_gpio_set(22, 1);
1475}
1476
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001477/*
1478 * Suited for:
1479 * - HP Vectra VL400: 815 + ICH + PC87360
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001480 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001481static int board_hp_vl400(void)
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001482{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001483 int ret;
1484 ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */
1485 if (!ret)
1486 ret = pc87360_gpio_set(0x09, 1); /* #WP ? */
1487 if (!ret)
1488 ret = pc87360_gpio_set(0x27, 1); /* #TBL */
1489 return ret;
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001490}
1491
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001492/*
Luc Verhaegen1265d8d2009-11-28 18:16:31 +00001493 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001494 * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R
1495 * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R
1496 * - ASRock 775i65G: Intel LGA 775 + 865G + ICH5
Uwe Hermann742999c2010-12-02 21:57:42 +00001497 * - MSI MS-6391 (845 Pro4): Intel Socket478 + 845 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001498 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001499static int intel_ich_gpio23_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001500{
1501 return intel_ich_gpio_set(23, 1);
1502}
1503
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001504/*
1505 * Suited for:
Michael Karcher39dcdec2010-10-05 17:29:35 +00001506 * - GIGABYTE GA-6IEM: Intel Socket370 + i815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001507 * - GIGABYTE GA-8IRML: Intel Socket478 + i845 + ICH2
Michael Karcherc7a1ffb2010-07-24 22:27:29 +00001508 */
1509static int intel_ich_gpio25_raise(void)
1510{
1511 return intel_ich_gpio_set(25, 1);
1512}
1513
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001514/*
1515 * Suited for:
1516 * - IBASE MB899: i945GM + ICH7
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001517 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001518static int intel_ich_gpio26_raise(void)
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001519{
1520 return intel_ich_gpio_set(26, 1);
1521}
1522
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001523/*
1524 * Suited for:
1525 * - P4SD-LA (HP OEM): i865 + ICH5
Michael Karcherc8613242010-08-13 12:49:01 +00001526 * - GIGABYTE GA-8PE667 Ultra 2: socket 478 + i845PE + ICH4
Michael Karcher87c90992010-07-24 11:03:48 +00001527 */
Idwer Vollering19dceac2010-07-24 18:47:45 +00001528static int intel_ich_gpio32_raise(void)
Michael Karcher87c90992010-07-24 11:03:48 +00001529{
1530 return intel_ich_gpio_set(32, 1);
1531}
1532
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001533/*
1534 * Suited for:
1535 * - Acorp 6A815EPD: socket 370 + intel 815 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001536 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001537static int board_acorp_6a815epd(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001538{
1539 int ret;
1540
1541 /* Lower Blocks Lock -- pin 7 of PLCC32 */
1542 ret = intel_ich_gpio_set(22, 1);
1543 if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */
1544 ret = intel_ich_gpio_set(23, 1);
1545
1546 return ret;
1547}
1548
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001549/*
1550 * Suited for:
1551 * - Kontron 986LCD-M: Socket478 + 915GM + ICH7R
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001552 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001553static int board_kontron_986lcd_m(void)
Stefan Reinauerac378972008-03-17 22:59:40 +00001554{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001555 int ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001556
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001557 ret = intel_ich_gpio_set(34, 1); /* #TBL */
1558 if (!ret)
1559 ret = intel_ich_gpio_set(35, 1); /* #WP */
Stefan Reinauerac378972008-03-17 22:59:40 +00001560
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001561 return ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001562}
1563
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001564/*
1565 * Suited for:
1566 * - Soyo SY-7VCA: Pro133A + VT82C686
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001567 */
Michael Karcher06477332010-03-19 22:49:09 +00001568static int via_apollo_gpo_set(int gpio, int raise)
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001569{
Michael Karcher06477332010-03-19 22:49:09 +00001570 struct pci_dev *dev;
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001571 uint32_t base;
Michael Karcher06477332010-03-19 22:49:09 +00001572 uint32_t tmp;
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001573
1574 /* VT82C686 Power management */
1575 dev = pci_dev_find(0x1106, 0x3057);
1576 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001577 msg_perr("\nERROR: VT82C686 PM device not found.\n");
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001578 return -1;
1579 }
1580
Sean Nelson316a29f2010-05-07 20:09:04 +00001581 msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n",
Michael Karcher06477332010-03-19 22:49:09 +00001582 raise ? "Rais" : "Dropp", gpio);
1583
1584 /* select GPO function on multiplexed pins */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001585 tmp = pci_read_byte(dev, 0x54);
Michael Karcher06477332010-03-19 22:49:09 +00001586 switch(gpio)
1587 {
1588 case 0:
1589 tmp &= ~0x03;
1590 break;
1591 case 1:
1592 tmp |= 0x04;
1593 break;
1594 case 2:
1595 tmp |= 0x08;
1596 break;
1597 case 3:
1598 tmp |= 0x10;
1599 break;
1600 }
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001601 pci_write_byte(dev, 0x54, tmp);
1602
1603 /* PM IO base */
1604 base = pci_read_long(dev, 0x48) & 0x0000FF00;
1605
1606 /* Drop GPO0 */
Michael Karcher06477332010-03-19 22:49:09 +00001607 tmp = INL(base + 0x4C);
1608 if (raise)
1609 tmp |= 1U << gpio;
1610 else
1611 tmp &= ~(1U << gpio);
1612 OUTL(tmp, base + 0x4C);
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001613
1614 return 0;
1615}
1616
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001617/*
1618 * Suited for:
1619 * - abit VT6X4: Pro133x + VT82C686A
Mattias Mattssone3df96e2010-08-15 22:43:23 +00001620 * - abit VA6: Pro133x + VT82C686A
Michael Karcher187a46a2010-03-19 22:30:49 +00001621 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001622static int via_apollo_gpo4_lower(void)
Michael Karcher187a46a2010-03-19 22:30:49 +00001623{
1624 return via_apollo_gpo_set(4, 0);
1625}
1626
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001627/*
1628 * Suited for:
1629 * - Soyo SY-7VCA: Pro133A + VT82C686
Michael Karcher06477332010-03-19 22:49:09 +00001630 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001631static int via_apollo_gpo0_lower(void)
Michael Karcher06477332010-03-19 22:49:09 +00001632{
1633 return via_apollo_gpo_set(0, 0);
1634}
1635
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001636/*
Michael Karcher9f9e6132010-01-09 17:36:06 +00001637 * Enable some GPIO pin on SiS southbridge.
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001638 *
1639 * Suited for:
1640 * - MSI 651M-L: SiS651 / SiS962
Michael Karcher9f9e6132010-01-09 17:36:06 +00001641 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001642static int board_msi_651ml(void)
Michael Karcher9f9e6132010-01-09 17:36:06 +00001643{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001644 struct pci_dev *dev;
Uwe Hermann43959702010-03-13 17:28:29 +00001645 uint16_t base, temp;
Michael Karcher9f9e6132010-01-09 17:36:06 +00001646
1647 dev = pci_dev_find(0x1039, 0x0962);
1648 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001649 msg_perr("Expected south bridge not found\n");
Michael Karcher9f9e6132010-01-09 17:36:06 +00001650 return 1;
1651 }
1652
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001653 /* Registers 68 and 64 seem like bitmaps. */
Michael Karcher9f9e6132010-01-09 17:36:06 +00001654 base = pci_read_word(dev, 0x74);
1655 temp = INW(base + 0x68);
1656 temp &= ~(1 << 0); /* Make pin output? */
Michael Karcher0435dfd2010-01-09 23:31:13 +00001657 OUTW(temp, base + 0x68);
Michael Karcher9f9e6132010-01-09 17:36:06 +00001658
1659 temp = INW(base + 0x64);
1660 temp |= (1 << 0); /* Raise output? */
1661 OUTW(temp, base + 0x64);
1662
1663 w836xx_memw_enable(0x2E);
1664
1665 return 0;
1666}
1667
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001668/*
Michael Gold6d52e472009-06-19 13:00:24 +00001669 * Find the runtime registers of an SMSC Super I/O, after verifying its
1670 * chip ID.
1671 *
1672 * Returns the base port of the runtime register block, or 0 on error.
1673 */
1674static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
1675 uint8_t logical_device)
1676{
1677 uint16_t rt_port = 0;
1678
1679 /* Verify the chip ID. */
Uwe Hermann1432a602009-06-28 23:26:37 +00001680 OUTB(0x55, sio_port); /* Enable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00001681 if (sio_read(sio_port, 0x20) != chip_id) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001682 msg_perr("\nERROR: SMSC Super I/O not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00001683 goto out;
1684 }
1685
1686 /* If the runtime block is active, get its address. */
1687 sio_write(sio_port, 0x07, logical_device);
1688 if (sio_read(sio_port, 0x30) & 1) {
1689 rt_port = (sio_read(sio_port, 0x60) << 8)
1690 | sio_read(sio_port, 0x61);
1691 }
1692
1693 if (rt_port == 0) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001694 msg_perr("\nERROR: "
Michael Gold6d52e472009-06-19 13:00:24 +00001695 "Super I/O runtime interface not available.\n");
1696 }
1697out:
Uwe Hermann1432a602009-06-28 23:26:37 +00001698 OUTB(0xaa, sio_port); /* Disable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00001699 return rt_port;
1700}
1701
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001702/*
1703 * Disable write protection on the Mitac 6513WU. WP# on the FWH is
Michael Gold6d52e472009-06-19 13:00:24 +00001704 * connected to GP30 on the Super I/O, and TBL# is always high.
1705 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001706static int board_mitac_6513wu(void)
Michael Gold6d52e472009-06-19 13:00:24 +00001707{
1708 struct pci_dev *dev;
1709 uint16_t rt_port;
1710 uint8_t val;
1711
1712 dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */
1713 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001714 msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00001715 return -1;
1716 }
1717
Uwe Hermann1432a602009-06-28 23:26:37 +00001718 rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa);
Michael Gold6d52e472009-06-19 13:00:24 +00001719 if (rt_port == 0)
1720 return -1;
1721
1722 /* Configure the GPIO pin. */
1723 val = INB(rt_port + 0x33); /* GP30 config */
Uwe Hermann1432a602009-06-28 23:26:37 +00001724 val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */
Michael Gold6d52e472009-06-19 13:00:24 +00001725 OUTB(val, rt_port + 0x33);
1726
1727 /* Disable write protection. */
1728 val = INB(rt_port + 0x4d); /* GP3 values */
Uwe Hermann1432a602009-06-28 23:26:37 +00001729 val |= 0x01; /* Set GP30 high. */
Michael Gold6d52e472009-06-19 13:00:24 +00001730 OUTB(val, rt_port + 0x4d);
1731
1732 return 0;
1733}
1734
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001735/*
1736 * Suited for:
Uwe Hermann45bd1442010-09-14 23:20:35 +00001737 * - ASUS A7V333: VIA KT333 + VT8233A + IT8703F
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001738 * - ASUS A7V8X: VIA KT400 + VT8235 + IT8703F
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001739 */
Uwe Hermann45bd1442010-09-14 23:20:35 +00001740static int it8703f_gpio51_raise(void)
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001741{
1742 uint16_t id, base;
1743 uint8_t tmp;
1744
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001745 /* Find the IT8703F. */
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001746 w836xx_ext_enter(0x2E);
1747 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
1748 w836xx_ext_leave(0x2E);
1749
1750 if (id != 0x8701) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001751 msg_perr("\nERROR: IT8703F Super I/O not found.\n");
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001752 return -1;
1753 }
1754
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001755 /* Get the GP567 I/O base. */
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001756 w836xx_ext_enter(0x2E);
1757 sio_write(0x2E, 0x07, 0x0C);
1758 base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
1759 w836xx_ext_leave(0x2E);
1760
1761 if (!base) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001762 msg_perr("\nERROR: Failed to read IT8703F Super I/O GPIO"
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001763 " Base.\n");
1764 return -1;
1765 }
1766
1767 /* Raise GP51. */
1768 tmp = INB(base);
1769 tmp |= 0x02;
1770 OUTB(tmp, base);
1771
1772 return 0;
1773}
1774
Luc Verhaegen72272912009-09-01 21:22:23 +00001775/*
1776 * General routine for raising/dropping GPIO lines on the ITE IT8712F.
1777 * There is only some limited checking on the port numbers.
1778 */
Uwe Hermann43959702010-03-13 17:28:29 +00001779static int it8712f_gpio_set(unsigned int line, int raise)
Luc Verhaegen72272912009-09-01 21:22:23 +00001780{
1781 unsigned int port;
1782 uint16_t id, base;
1783 uint8_t tmp;
1784
1785 port = line / 10;
1786 port--;
1787 line %= 10;
1788
1789 /* Check line */
1790 if ((port > 4) || /* also catches unsigned -1 */
1791 ((port < 4) && (line > 7)) || ((port == 4) && (line > 5))) {
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001792 msg_perr("\nERROR: Unsupported IT8712F GPIO line %02d.\n", line);
Luc Verhaegen72272912009-09-01 21:22:23 +00001793 return -1;
1794 }
1795
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001796 /* Find the IT8712F. */
Luc Verhaegen72272912009-09-01 21:22:23 +00001797 enter_conf_mode_ite(0x2E);
1798 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
1799 exit_conf_mode_ite(0x2E);
1800
1801 if (id != 0x8712) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001802 msg_perr("\nERROR: IT8712F Super I/O not found.\n");
Luc Verhaegen72272912009-09-01 21:22:23 +00001803 return -1;
1804 }
1805
1806 /* Get the GPIO base */
1807 enter_conf_mode_ite(0x2E);
1808 sio_write(0x2E, 0x07, 0x07);
1809 base = (sio_read(0x2E, 0x62) << 8) | sio_read(0x2E, 0x63);
1810 exit_conf_mode_ite(0x2E);
1811
1812 if (!base) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001813 msg_perr("\nERROR: Failed to read IT8712F Super I/O GPIO"
Luc Verhaegen72272912009-09-01 21:22:23 +00001814 " Base.\n");
1815 return -1;
1816 }
1817
1818 /* set GPIO. */
1819 tmp = INB(base + port);
1820 if (raise)
1821 tmp |= 1 << line;
1822 else
1823 tmp &= ~(1 << line);
1824 OUTB(tmp, base + port);
1825
1826 return 0;
1827}
1828
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001829/*
Russ Dillbd622d12010-03-09 16:57:06 +00001830 * Suited for:
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001831 * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F
1832 * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F
Luc Verhaegen72272912009-09-01 21:22:23 +00001833 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001834static int it8712f_gpio3_1_raise(void)
Luc Verhaegen72272912009-09-01 21:22:23 +00001835{
1836 return it8712f_gpio_set(32, 1);
1837}
1838
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001839#endif
1840
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001841/*
Uwe Hermannd0e347d2009-10-06 13:00:00 +00001842 * Below is the list of boards which need a special "board enable" code in
1843 * flashrom before their ROM chip can be accessed/written to.
1844 *
1845 * NOTE: Please add boards that _don't_ need such enables or don't work yet
1846 * to the respective tables in print.c. Thanks!
1847 *
Uwe Hermannffec5f32007-08-23 16:08:21 +00001848 * We use 2 sets of IDs here, you're free to choose which is which. This
1849 * is to provide a very high degree of certainty when matching a board on
1850 * the basis of subsystem/card IDs. As not every vendor handles
1851 * subsystem/card IDs in a sane manner.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001852 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00001853 * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00001854 * NULLed if they don't identify the board fully and if you can't use DMI.
1855 * But please take care to provide an as complete set of pci ids as possible;
1856 * autodetection is the preferred behaviour and we would like to make sure that
1857 * matches are unique.
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001858 *
Michael Karcher6701ee82010-01-20 14:14:11 +00001859 * If PCI IDs are not sufficient for board matching, the match can be further
1860 * constrained by a string that has to be present in the DMI database for
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001861 * the baseboard or the system entry. The pattern is matched by case sensitive
Michael Karcher6701ee82010-01-20 14:14:11 +00001862 * substring match, unless it is anchored to the beginning (with a ^ in front)
1863 * or the end (with a $ at the end). Both anchors may be specified at the
1864 * same time to match the full field.
1865 *
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00001866 * When a board is matched through DMI, the first and second main PCI IDs
1867 * and the first subsystem PCI ID have to match as well. If you specify the
1868 * first subsystem ID as 0x0:0x0, the DMI matching code expects that the
1869 * subsystem ID of that device is indeed zero.
1870 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00001871 * The coreboot ids are used two fold. When running with a coreboot firmware,
1872 * the ids uniquely matches the coreboot board identification string. When a
1873 * legacy bios is installed and when autodetection is not possible, these ids
1874 * can be used to identify the board through the -m command line argument.
1875 *
1876 * When a board is identified through its coreboot ids (in both cases), the
1877 * main pci ids are still required to match, as a safeguard.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001878 */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001879
Uwe Hermanndeeebe22009-05-08 16:23:34 +00001880/* Please keep this list alphabetically ordered by vendor/board name. */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00001881const struct board_pciid_enable board_pciid_enables[] = {
Uwe Hermann5ab88892009-06-21 20:50:22 +00001882
Michael Karcher0bdc0922010-02-28 01:33:48 +00001883 /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001884#if defined(__i386__) || defined(__x86_64__)
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001885 {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise},
Tim ter Laak4b933f02010-09-13 23:00:57 +00001886 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^i440BX-W977 (BM6)$", NULL, NULL, "abit", "BM6", 0, OK, intel_piix4_gpo26_lower},
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001887 {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, "abit", "IC7", 0, NT, intel_ich_gpio23_raise},
1888 {0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "abit", "IP35", 0, OK, intel_ich_gpio16_raise},
1889 {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise},
1890 {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, "abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower},
1891 {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, "abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise},
1892 {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0240, 0x10de, 0x0222, NULL, NULL, NULL, "abit", "NF-M2 nView", 0, NT, nvidia_mcp_gpio4_lower},
Mattias Mattssone3df96e2010-08-15 22:43:23 +00001893 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, "(VA6)$", NULL, NULL, "abit", "VA6", 0, OK, via_apollo_gpo4_lower},
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001894 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "abit", "VT6X4", 0, OK, via_apollo_gpo4_lower},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001895 {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001896 {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e},
Peter Lemenkov4073c092010-05-26 22:29:51 +00001897 {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001898 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x},
1899 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x},
Uwe Hermann17da61e2010-10-05 21:48:43 +00001900 {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e},
Peter Lemenkoveb75ced2010-05-26 22:26:44 +00001901 {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise},
Joshua Roys7507de42010-08-08 16:05:23 +00001902 {0x8086, 0x2570, 0x1849, 0x2570, 0x8086, 0x24d3, 0x1849, 0x24d0, NULL, NULL, NULL, "ASRock", "775i65G", 0, OK, intel_ich_gpio23_raise},
Russ Dillbd622d12010-03-09 16:57:06 +00001903 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise},
Peter Lemenkoveb75ced2010-05-26 22:26:44 +00001904 {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e},
Uwe Hermann45bd1442010-09-14 23:20:35 +00001905 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, it8703f_gpio51_raise},
1906 {0x1106, 0x3099, 0x1043, 0x807F, 0x1106, 0x3147, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V333", 0, OK, it8703f_gpio51_raise},
Russ Dillbd622d12010-03-09 16:57:06 +00001907 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise},
Uwe Hermannead705f2010-08-15 15:26:30 +00001908 {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, "ASUS", "A8Jm", 0, NT, intel_ich_gpio34_raise},
Sean Nelson0a247512010-08-15 14:36:18 +00001909 {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L", NULL, NULL, "ASUS", "A8N-LA (Nagami-GL8E)", 0, OK, nvidia_mcp_gpio0_raise},
Uwe Hermannead705f2010-08-15 15:26:30 +00001910 {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N", 0, NT, board_shuttle_fn25}, /* TODO: This should probably be A8N-SLI Deluxe, see http://www.coreboot.org/pipermail/flashrom/2009-November/000878.html. */
Michael Karcher7af6cef2010-07-08 09:32:18 +00001911 {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, "ASUS", "A8N-VM CSM", 0, NT, w83627ehf_gpio24_raise_2e},
Michael Karcherb2184c12010-03-07 16:42:55 +00001912 {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001913 {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise},
Mattias Mattsson85016b92010-09-01 01:21:34 +00001914 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^P2B-N$", NULL, NULL, "ASUS", "P2B-N", 0, OK, intel_piix4_gpo18_lower},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001915 {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise},
Peter Lemenkoveb75ced2010-05-26 22:26:44 +00001916 {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise},
Michael Karcher255a9e02010-03-19 22:52:00 +00001917 {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise},
Michael Karcher6499d5a2010-03-17 06:19:23 +00001918 {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
Michael Karcherf4b58792010-09-10 14:54:18 +00001919 {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, "ASUS", "P4P800", 0, NT, intel_ich_gpio21_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001920 {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
Mattias Mattssonfb60cec2010-09-13 19:39:25 +00001921 {0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, "ASUS", "P4SC-E", 0, OK, it8707f_write_enable_2e},
Michael Karcher87c90992010-07-24 11:03:48 +00001922 {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise},
David Borgb6417a62010-08-02 08:29:34 +00001923 {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001924 {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a},
Michael Karcher4a23e442010-09-10 14:46:46 +00001925 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise},
Joshua Roysb1d980f2010-09-13 14:02:22 +00001926 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001927 {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise},
Michael Karcher72eeab52010-07-24 10:41:42 +00001928 {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise},
Mattias Mattsson2eaad632010-10-05 21:32:29 +00001929 {0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001930 {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise},
Mattias Mattssonf4925162010-09-16 22:09:18 +00001931 {0x10de, 0x03ea, 0x1019, 0x2602, 0x10de, 0x03e0, 0x1019, 0x2602, NULL, NULL, NULL, "Elitegroup", "GeForce6100SM-M", 0, OK, board_ecs_geforce6100sm_m},
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +00001932 {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, NULL},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001933 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e},
Uwe Hermann83d349a2010-10-18 22:32:03 +00001934 {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, NULL, NULL, NULL, "EPoX", "EP-8NPA7I", 0, OK, nvidia_mcp_gpio4_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001935 {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise},
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001936 {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", "EPoX", "EP-BX3", 0, NT, intel_piix4_gpo22_raise},
Michael Karcher39dcdec2010-10-05 17:29:35 +00001937 {0x8086, 0x2443, 0x8086, 0x2442, 0x8086, 0x1130, 0x8086, 0x1130, "^6IEM ", NULL, NULL, "GIGABYTE", "GA-6IEM", 0, NT, intel_ich_gpio25_raise},
Peter Lemenkoveb75ced2010-05-26 22:26:44 +00001938 {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL},
Uwe Hermann51afebb2010-08-01 00:13:49 +00001939 {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise},
Michael Karcherc8613242010-08-13 12:49:01 +00001940 {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise},
Joshua Roys2ee137f2010-09-07 17:52:09 +00001941 {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001942 {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise},
Uwe Hermannead705f2010-08-15 15:26:30 +00001943 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable},
1944 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", "HP", "ProLiant DL165 G6", 0, OK, board_hp_dl165_g6_enable},
Michael Karchere57957c2010-07-24 11:14:37 +00001945 {0x8086, 0x2580, 0x103c, 0x2a08, 0x8086, 0x2640, 0x103c, 0x2a0a, NULL, NULL, NULL, "HP", "Puffer2-UL8E", 0, OK, intel_ich_gpio18_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001946 {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400},
Uwe Hermannead705f2010-08-15 15:26:30 +00001947 {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "Vectra VL420 SFF", 0, OK, intel_ich_gpio22_raise},
Michael Karcher2ead2e22010-06-01 16:09:06 +00001948 {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, NULL, NULL, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise},
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001949 {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", "IBASE", "MB899", 0, OK, intel_ich_gpio26_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001950 {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455},
1951 {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi},
Michael Karcher51cd0c92010-03-19 22:35:21 +00001952 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001953 {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e},
James Lancaster998c9dc2010-03-19 22:39:24 +00001954 {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001955 {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, "Mitac", "6513WU", 0, OK, board_mitac_6513wu},
Uwe Hermannead705f2010-08-15 15:26:30 +00001956 {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, /* TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html. */
Mattias Mattssonc8ca3de2010-09-13 18:22:36 +00001957 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^MS-6163 (i440BX)$", NULL, NULL, "MSI", "MS-6163 (MS-6163 Pro)", 0, OK, intel_piix4_gpo14_raise},
Mattias Mattssone8388242010-09-11 15:25:48 +00001958 {0x1039, 0x0745, 0, 0, 0x1039, 0x0018, 0, 0, "^MS-6561", NULL, NULL, "MSI", "MS-6561 (745 Ultra)", 0, OK, w836xx_memw_enable_2e},
Uwe Hermannead705f2010-08-15 15:26:30 +00001959 {0x8086, 0x2560, 0x1462, 0x5770, 0x8086, 0x2562, 0x1462, 0x5778, NULL, NULL, NULL, "MSI", "MS-6577 (Xenon)", 0, OK, w83627hf_gpio25_raise_2e},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001960 {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v},
Michael Karcherbcd80cd2010-06-27 15:07:49 +00001961 {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio44_raise_2e},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001962 {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v},
Uwe Hermanna3473242010-09-14 22:59:39 +00001963 {0x1106, 0x3148, 0 , 0 , 0x1106, 0x3177, 0 , 0 , NULL, "msi", "ms6787", "MSI", "MS-6787 (P4MAM-V/P4MAM-L)", 0, OK, w836xx_memw_enable_2e},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001964 {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml},
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001965 {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001966 {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise},
Uwe Hermann742999c2010-12-02 21:57:42 +00001967 {0x8086, 0x244b, 0x1462, 0x3910, 0x8086, 0x2442, 0x1462, 0x3910, NULL, NULL, NULL, "MSI", "MS-6391 (845 Pro4)", 0, OK, intel_ich_gpio23_raise},
Mattias Mattssone295eee2010-08-15 10:21:29 +00001968 {0x1106, 0x3149, 0x1462, 0x7061, 0x1106, 0x3227, 0, 0, NULL, NULL, NULL, "MSI", "MS-7061 (KM4M-V/KM4AM-V)", 0, OK, w836xx_memw_enable_2e},
Michael Karcherbcd80cd2010-06-27 15:07:49 +00001969 {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio44_raise_4e},
Uwe Hermannead705f2010-08-15 15:26:30 +00001970 {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8NGM2-L)", 0, NT, nvidia_mcp_gpio2_raise},
Michael Karcherb3fe2fc2010-05-24 16:03:57 +00001971 {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0},
Michael Karcher3b112522010-07-24 22:36:01 +00001972 {0x8086, 0x24d3, 0x144d, 0xb025, 0x8086, 0x1050, 0x144d, 0xb025, NULL, NULL, NULL, "Samsung", "Polaris 32", 0, OK, intel_ich_gpio21_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001973 {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e},
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +00001974 {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, NULL},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001975 {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25},
Michael Karcher06477332010-03-19 22:49:09 +00001976 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001977 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, OK, NULL},
Daniel Brandt4ad4c742010-03-21 13:36:20 +00001978 {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e},
Peter Lemenkoveb75ced2010-05-26 22:26:44 +00001979 {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e},
Michael Karcherbcd25562010-06-12 17:27:44 +00001980 {0x1106, 0x0259, 0x1106, 0xAA07, 0x1106, 0x3227, 0x1106, 0xAA07, NULL, NULL, NULL, "VIA", "EPIA EK", 0, NT, via_vt823x_gpio9_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001981 {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise},
1982 {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise},
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001983#endif
Michael Karcher0bdc0922010-02-28 01:33:48 +00001984 { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001985};
1986
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001987/*
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00001988 * Match boards on coreboot table gathered vendor and part name.
Uwe Hermannffec5f32007-08-23 16:08:21 +00001989 * Require main PCI IDs to match too as extra safety.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001990 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00001991static const struct board_pciid_enable *board_match_coreboot_name(const char *vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00001992 const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001993{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00001994 const struct board_pciid_enable *board = board_pciid_enables;
1995 const struct board_pciid_enable *partmatch = NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001996
Uwe Hermanna93045c2009-05-09 00:47:04 +00001997 for (; board->vendor_name; board++) {
Uwe Hermann394131e2008-10-18 21:14:13 +00001998 if (vendor && (!board->lb_vendor
1999 || strcasecmp(board->lb_vendor, vendor)))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002000 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002001
Peter Stuge0b9c5f32008-07-02 00:47:30 +00002002 if (!board->lb_part || strcasecmp(board->lb_part, part))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002003 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002004
Uwe Hermanna7e05482007-05-09 10:17:44 +00002005 if (!pci_dev_find(board->first_vendor, board->first_device))
2006 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002007
Uwe Hermanna7e05482007-05-09 10:17:44 +00002008 if (board->second_vendor &&
Uwe Hermann394131e2008-10-18 21:14:13 +00002009 !pci_dev_find(board->second_vendor, board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002010 continue;
Peter Stuge6b53fed2008-01-27 16:21:21 +00002011
2012 if (vendor)
2013 return board;
2014
2015 if (partmatch) {
2016 /* a second entry has a matching part name */
Sean Nelson316a29f2010-05-07 20:09:04 +00002017 msg_pinfo("AMBIGUOUS BOARD NAME: %s\n", part);
2018 msg_pinfo("At least vendors '%s' and '%s' match.\n",
Uwe Hermann394131e2008-10-18 21:14:13 +00002019 partmatch->lb_vendor, board->lb_vendor);
Sean Nelson316a29f2010-05-07 20:09:04 +00002020 msg_perr("Please use the full -m vendor:part syntax.\n");
Peter Stuge6b53fed2008-01-27 16:21:21 +00002021 return NULL;
2022 }
2023 partmatch = board;
Uwe Hermanna7e05482007-05-09 10:17:44 +00002024 }
Uwe Hermann372eeb52007-12-04 21:49:06 +00002025
Peter Stuge6b53fed2008-01-27 16:21:21 +00002026 if (partmatch)
2027 return partmatch;
2028
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00002029 if (!partvendor_from_cbtable) {
2030 /* Only warn if the mainboard type was not gathered from the
2031 * coreboot table. If it was, the coreboot implementor is
2032 * expected to fix flashrom, too.
2033 */
Sean Nelson316a29f2010-05-07 20:09:04 +00002034 msg_perr("\nUnknown vendor:board from -m option: %s:%s\n\n",
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00002035 vendor, part);
2036 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00002037 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002038}
2039
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002040/*
Uwe Hermannffec5f32007-08-23 16:08:21 +00002041 * Match boards on PCI IDs and subsystem IDs.
2042 * Second set of IDs can be main only or missing completely.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002043 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00002044const static struct board_pciid_enable *board_match_pci_card_ids(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002045{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00002046 const struct board_pciid_enable *board = board_pciid_enables;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002047
Uwe Hermanna93045c2009-05-09 00:47:04 +00002048 for (; board->vendor_name; board++) {
Michael Karcher2eab70d2010-02-04 10:58:50 +00002049 if ((!board->first_card_vendor || !board->first_card_device) &&
2050 !board->dmi_pattern)
Uwe Hermanna7e05482007-05-09 10:17:44 +00002051 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002052
Uwe Hermanna7e05482007-05-09 10:17:44 +00002053 if (!pci_card_find(board->first_vendor, board->first_device,
Uwe Hermann394131e2008-10-18 21:14:13 +00002054 board->first_card_vendor,
2055 board->first_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002056 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002057
Uwe Hermanna7e05482007-05-09 10:17:44 +00002058 if (board->second_vendor) {
2059 if (board->second_card_vendor) {
2060 if (!pci_card_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00002061 board->second_device,
2062 board->second_card_vendor,
2063 board->second_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002064 continue;
2065 } else {
2066 if (!pci_dev_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00002067 board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002068 continue;
2069 }
2070 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002071
Michael Karcher6701ee82010-01-20 14:14:11 +00002072 if (board->dmi_pattern) {
2073 if (!has_dmi_support) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002074 msg_perr("WARNING: Can't autodetect %s %s,"
Michael Karcher6701ee82010-01-20 14:14:11 +00002075 " DMI info unavailable.\n",
2076 board->vendor_name, board->board_name);
2077 continue;
2078 } else {
2079 if (!dmi_match(board->dmi_pattern))
2080 continue;
2081 }
2082 }
2083
Uwe Hermanna7e05482007-05-09 10:17:44 +00002084 return board;
2085 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002086
Uwe Hermanna7e05482007-05-09 10:17:44 +00002087 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002088}
2089
Uwe Hermann372eeb52007-12-04 21:49:06 +00002090int board_flash_enable(const char *vendor, const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002091{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00002092 const struct board_pciid_enable *board = NULL;
Uwe Hermanna7e05482007-05-09 10:17:44 +00002093 int ret = 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002094
Peter Stuge6b53fed2008-01-27 16:21:21 +00002095 if (part)
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00002096 board = board_match_coreboot_name(vendor, part);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002097
Uwe Hermanna7e05482007-05-09 10:17:44 +00002098 if (!board)
2099 board = board_match_pci_card_ids();
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002100
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002101 if (board && board->status == NT) {
2102 if (!force_boardenable) {
2103 msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n"
2104 "code has not been tested, and thus will not not be executed by default.\n"
2105 "Depending on your hardware environment, erasing, writing or even probing\n"
2106 "can fail without running the board specific code.\n\n"
2107 "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n"
2108 "\"internal programmer\") for details.\n",
2109 board->vendor_name, board->board_name);
2110 board = NULL;
2111 } else {
2112 msg_pinfo("NOTE: Running an untested board enable procedure.\n"
Paul Menzelab6328f2010-10-08 11:03:02 +00002113 "Please report success/failure to flashrom@flashrom.org\n"
2114 "with your board name and SUCCESS or FAILURE in the subject.\n");
Uwe Hermann43959702010-03-13 17:28:29 +00002115 }
Michael Karcher7f0c3ec2010-03-07 22:29:28 +00002116 }
2117
Uwe Hermanna7e05482007-05-09 10:17:44 +00002118 if (board) {
Luc Verhaegen93938c32010-01-20 14:45:03 +00002119 if (board->max_rom_decode_parallel)
2120 max_rom_decode.parallel =
2121 board->max_rom_decode_parallel * 1024;
2122
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00002123 if (board->enable != NULL) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002124 msg_pinfo("Disabling flash write protection for "
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002125 "board \"%s %s\"... ", board->vendor_name,
2126 board->board_name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002127
Uwe Hermann36dec8b2010-06-07 19:06:26 +00002128 ret = board->enable();
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00002129 if (ret)
Sean Nelson316a29f2010-05-07 20:09:04 +00002130 msg_pinfo("FAILED!\n");
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00002131 else
Sean Nelson316a29f2010-05-07 20:09:04 +00002132 msg_pinfo("OK.\n");
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00002133 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00002134 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002135
Uwe Hermanna7e05482007-05-09 10:17:44 +00002136 return ret;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002137}