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review.sourcearcade.org / libgfxinit / dde0630af418e6a3c2cd391579df5cea7350095a / . / common / hw-gfx-gma-registers.ads
blob: 68e566486c4395ec332ed31c1f6e62f317287dbf [file] [log] [blame]
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1--
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]2-- Copyright (C) 2015-2017 secunet Security Networks AG
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +0200[diff] [blame]6-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]8--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
15with System;
16with HW.GFX.GMA;
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]17with HW.GFX.GMA.Config;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]18
19private package HW.GFX.GMA.Registers
20with
21 Abstract_State =>
22 ((Address_State with Part_Of => GMA.State),
23 (Register_State with External, Part_Of => GMA.Device_State),
24 (GTT_State with External, Part_Of => GMA.Device_State)),
25 Initializes => Address_State
26is
Nico Huber0b2329a2018-06-09 21:14:27 +0200[diff] [blame]27
28 MMIO_GTT_32_Size : constant := 16#20_0000#;
29 MMIO_GTT_32_Offset : constant := 16#20_0000#;
30
31 -- Limit Broadwell+ to 4MiB to have a stable
32 -- interface (i.e. same number of entries):
33 MMIO_GTT_64_Size : constant := 16#40_0000#;
34 MMIO_GTT_64_Offset : constant := 16#80_0000#;
35
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]36 type Registers_Invalid_Index is
37 (Invalid_Register, -- Allow a placeholder when access is not acceptable
38
39 RCS_RING_BUFFER_TAIL,
40 RCS_RING_BUFFER_HEAD,
41 RCS_RING_BUFFER_STRT,
42 RCS_RING_BUFFER_CTL,
43 QUIRK_02084,
44 QUIRK_02090,
45 HWSTAM,
46 MI_MODE,
47 INSTPM,
48 GT_MODE,
49 CACHE_MODE_0,
50 CTX_SIZE,
51 PP_DCLV_HIGH,
52 PP_DCLV_LOW,
53 GFX_MODE,
54 ARB_MODE,
55 HWS_PGA,
56 GAM_ECOCHK,
Arthur Heymans229ed1c2018-03-28 16:45:43 +0200[diff] [blame]57 GMCH_GMBUS0,
58 GMCH_GMBUS1,
59 GMCH_GMBUS2,
60 GMCH_GMBUS3,
61 GMCH_GMBUS4,
62 GMCH_GMBUS5,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]63 GMCH_DPLL_A,
64 GMCH_DPLL_B,
65 GMCH_FPA0,
66 GMCH_FPA1,
67 GMCH_FPB0,
68 GMCH_FPB1,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]69 MBCTL,
70 UCGCTL1,
71 UCGCTL2,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]72 GMCH_CLKCFG,
Nico Huberb47a5c42019-09-29 00:07:21 +0200[diff] [blame]73 GMCH_HPLLVCO_MOBILE,
74 GMCH_HPLLVCO,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]75 VCS_RING_BUFFER_TAIL,
76 VCS_RING_BUFFER_HEAD,
77 VCS_RING_BUFFER_STRT,
78 VCS_RING_BUFFER_CTL,
79 SLEEP_PSMI_CONTROL,
80 VCS_HWSTAM,
81 VCS_PP_DCLV_HIGH,
82 VCS_PP_DCLV_LOW,
83 GAC_ECO_BITS,
84 BCS_RING_BUFFER_TAIL,
85 BCS_RING_BUFFER_HEAD,
86 BCS_RING_BUFFER_STRT,
87 BCS_RING_BUFFER_CTL,
88 BCS_HWSTAM,
89 BCS_PP_DCLV_HIGH,
90 BCS_PP_DCLV_LOW,
91 GAB_CTL_REG,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]92 CPU_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]93 FUSE_STATUS,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]94 ILK_DISPLAY_CHICKEN2,
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]95 FUSE_STRAP,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]96 DSPCLK_GATE_D,
97 FBA_CFB_BASE,
98 FBC_CTL,
99 IPS_CTL,
100 DEISR,
101 DEIMR,
102 DEIIR,
103 DEIER,
104 GTISR,
105 GTIMR,
106 GTIIR,
107 GTIER,
108 IIR,
109 HOTPLUG_CTL,
110 ARB_CTL,
111 DBUF_CTL,
112 WM_PIPE_A,
113 WM_PIPE_B,
114 WM1_LP_ILK,
115 WM2_LP_ILK,
116 WM3_LP_ILK,
117 WM_PIPE_C,
118 WM_LINETIME_A,
119 WM_LINETIME_B,
120 WM_LINETIME_C,
121 PWR_WELL_CTL_BIOS,
122 PWR_WELL_CTL_DRIVER,
123 PWR_WELL_CTL_KVMR,
124 PWR_WELL_CTL_DEBUG,
125 PWR_WELL_CTL5,
126 PWR_WELL_CTL6,
127 CDCLK_CTL,
128 LCPLL1_CTL,
129 LCPLL2_CTL,
130 SPLL_CTL,
131 WRPLL_CTL_1,
132 WRPLL_CTL_2,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]133 BXT_DE_PLL_ENABLE,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]134 BXT_PORT_PLL_ENABLE_A,
135 BXT_PORT_PLL_ENABLE_B,
136 BXT_PORT_PLL_ENABLE_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]137 PORT_CLK_SEL_DDIA,
138 PORT_CLK_SEL_DDIB,
139 PORT_CLK_SEL_DDIC,
140 PORT_CLK_SEL_DDID,
141 PORT_CLK_SEL_DDIE,
142 TRANSA_CLK_SEL,
143 TRANSB_CLK_SEL,
144 TRANSC_CLK_SEL,
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]145 CDCLK_FREQ,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]146 NDE_RSTWRN_OPT,
147 BLC_PWM_CPU_CTL2,
148 BLC_PWM_CPU_CTL,
Nico Huber6b4678d2019-09-22 21:31:52 +0200[diff] [blame]149 DFSM,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]150 HTOTAL_A,
151 HBLANK_A,
152 HSYNC_A,
153 VTOTAL_A,
154 VBLANK_A,
155 VSYNC_A,
156 PIPEASRC,
157 PIPE_VSYNCSHIFT_A,
158 PIPEA_DATA_M1,
159 PIPEA_DATA_N1,
160 PIPEA_LINK_M1,
161 PIPEA_LINK_N1,
162 FDI_TX_CTL_A,
163 PIPEA_DDI_FUNC_CTL,
164 PIPEA_MSA_MISC,
165 SRD_CTL_A,
166 SRD_STATUS_A,
167 HTOTAL_B,
168 HBLANK_B,
169 HSYNC_B,
170 VTOTAL_B,
171 VBLANK_B,
172 VSYNC_B,
173 PIPEBSRC,
174 PIPE_VSYNCSHIFT_B,
175 PIPEB_DATA_M1,
176 PIPEB_DATA_N1,
177 PIPEB_LINK_M1,
178 PIPEB_LINK_N1,
179 FDI_TX_CTL_B,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]180 PORT_HOTPLUG_EN,
181 PORT_HOTPLUG_STAT,
182 GMCH_SDVOB,
183 GMCH_SDVOC,
184 GMCH_LVDS,
Arthur Heymanse87d0d12018-03-28 17:02:49 +0200[diff] [blame]185 GMCH_PP_STATUS,
186 GMCH_PP_CONTROL,
187 GMCH_PP_ON_DELAYS,
188 GMCH_PP_OFF_DELAYS,
189 GMCH_PP_DIVISOR,
Arthur Heymansd5198442018-03-28 17:05:12 +0200[diff] [blame]190 GMCH_PFIT_CONTROL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]191 PIPEB_DDI_FUNC_CTL,
192 PIPEB_MSA_MISC,
193 SRD_CTL_B,
194 SRD_STATUS_B,
195 HTOTAL_C,
196 HBLANK_C,
197 HSYNC_C,
198 VTOTAL_C,
199 VBLANK_C,
200 VSYNC_C,
201 PIPECSRC,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]202 G4X_AUD_VID_DID,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]203 PIPE_VSYNCSHIFT_C,
204 PIPEC_DATA_M1,
205 PIPEC_DATA_N1,
206 PIPEC_LINK_M1,
207 PIPEC_LINK_N1,
208 FDI_TX_CTL_C,
209 PIPEC_DDI_FUNC_CTL,
210 PIPEC_MSA_MISC,
211 SRD_CTL_C,
212 SRD_STATUS_C,
213 DDI_BUF_CTL_A,
214 DDI_AUX_CTL_A,
215 DDI_AUX_DATA_A_1,
216 DDI_AUX_DATA_A_2,
217 DDI_AUX_DATA_A_3,
218 DDI_AUX_DATA_A_4,
219 DDI_AUX_DATA_A_5,
220 DDI_AUX_MUTEX_A,
221 DP_TP_CTL_A,
222 DDI_BUF_CTL_B,
223 DDI_AUX_CTL_B,
224 DDI_AUX_DATA_B_1,
225 DDI_AUX_DATA_B_2,
226 DDI_AUX_DATA_B_3,
227 DDI_AUX_DATA_B_4,
228 DDI_AUX_DATA_B_5,
229 DDI_AUX_MUTEX_B,
230 DP_TP_CTL_B,
231 DP_TP_STATUS_B,
232 DDI_BUF_CTL_C,
233 DDI_AUX_CTL_C,
234 DDI_AUX_DATA_C_1,
235 DDI_AUX_DATA_C_2,
236 DDI_AUX_DATA_C_3,
237 DDI_AUX_DATA_C_4,
238 DDI_AUX_DATA_C_5,
239 DDI_AUX_MUTEX_C,
240 DP_TP_CTL_C,
241 DP_TP_STATUS_C,
242 DDI_BUF_CTL_D,
243 DDI_AUX_CTL_D,
244 DDI_AUX_DATA_D_1,
245 DDI_AUX_DATA_D_2,
246 DDI_AUX_DATA_D_3,
247 DDI_AUX_DATA_D_4,
248 DDI_AUX_DATA_D_5,
249 DDI_AUX_MUTEX_D,
250 DP_TP_CTL_D,
251 DP_TP_STATUS_D,
252 DDI_BUF_CTL_E,
253 DP_TP_CTL_E,
254 DP_TP_STATUS_E,
255 SRD_CTL,
256 SRD_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]257 BXT_PHY_CTL_A,
258 BXT_PHY_CTL_B,
259 BXT_PHY_CTL_C,
260 BXT_PHY_CTL_FAM_EDP,
261 BXT_PHY_CTL_FAM_DDI,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]262 DDI_BUF_TRANS_A_S0T1,
263 DDI_BUF_TRANS_A_S0T2,
264 DDI_BUF_TRANS_A_S1T1,
265 DDI_BUF_TRANS_A_S1T2,
266 DDI_BUF_TRANS_A_S2T1,
267 DDI_BUF_TRANS_A_S2T2,
268 DDI_BUF_TRANS_A_S3T1,
269 DDI_BUF_TRANS_A_S3T2,
270 DDI_BUF_TRANS_A_S4T1,
271 DDI_BUF_TRANS_A_S4T2,
272 DDI_BUF_TRANS_A_S5T1,
273 DDI_BUF_TRANS_A_S5T2,
274 DDI_BUF_TRANS_A_S6T1,
275 DDI_BUF_TRANS_A_S6T2,
276 DDI_BUF_TRANS_A_S7T1,
277 DDI_BUF_TRANS_A_S7T2,
278 DDI_BUF_TRANS_A_S8T1,
279 DDI_BUF_TRANS_A_S8T2,
280 DDI_BUF_TRANS_A_S9T1,
281 DDI_BUF_TRANS_A_S9T2,
282 DDI_BUF_TRANS_B_S0T1,
283 DDI_BUF_TRANS_B_S0T2,
284 DDI_BUF_TRANS_B_S1T1,
285 DDI_BUF_TRANS_B_S1T2,
286 DDI_BUF_TRANS_B_S2T1,
287 DDI_BUF_TRANS_B_S2T2,
288 DDI_BUF_TRANS_B_S3T1,
289 DDI_BUF_TRANS_B_S3T2,
290 DDI_BUF_TRANS_B_S4T1,
291 DDI_BUF_TRANS_B_S4T2,
292 DDI_BUF_TRANS_B_S5T1,
293 DDI_BUF_TRANS_B_S5T2,
294 DDI_BUF_TRANS_B_S6T1,
295 DDI_BUF_TRANS_B_S6T2,
296 DDI_BUF_TRANS_B_S7T1,
297 DDI_BUF_TRANS_B_S7T2,
298 DDI_BUF_TRANS_B_S8T1,
299 DDI_BUF_TRANS_B_S8T2,
300 DDI_BUF_TRANS_B_S9T1,
301 DDI_BUF_TRANS_B_S9T2,
302 DDI_BUF_TRANS_C_S0T1,
303 DDI_BUF_TRANS_C_S0T2,
304 DDI_BUF_TRANS_C_S1T1,
305 DDI_BUF_TRANS_C_S1T2,
306 DDI_BUF_TRANS_C_S2T1,
307 DDI_BUF_TRANS_C_S2T2,
308 DDI_BUF_TRANS_C_S3T1,
309 DDI_BUF_TRANS_C_S3T2,
310 DDI_BUF_TRANS_C_S4T1,
311 DDI_BUF_TRANS_C_S4T2,
312 DDI_BUF_TRANS_C_S5T1,
313 DDI_BUF_TRANS_C_S5T2,
314 DDI_BUF_TRANS_C_S6T1,
315 DDI_BUF_TRANS_C_S6T2,
316 DDI_BUF_TRANS_C_S7T1,
317 DDI_BUF_TRANS_C_S7T2,
318 DDI_BUF_TRANS_C_S8T1,
319 DDI_BUF_TRANS_C_S8T2,
320 DDI_BUF_TRANS_C_S9T1,
321 DDI_BUF_TRANS_C_S9T2,
322 DDI_BUF_TRANS_D_S0T1,
323 DDI_BUF_TRANS_D_S0T2,
324 DDI_BUF_TRANS_D_S1T1,
325 DDI_BUF_TRANS_D_S1T2,
326 DDI_BUF_TRANS_D_S2T1,
327 DDI_BUF_TRANS_D_S2T2,
328 DDI_BUF_TRANS_D_S3T1,
329 DDI_BUF_TRANS_D_S3T2,
330 DDI_BUF_TRANS_D_S4T1,
331 DDI_BUF_TRANS_D_S4T2,
332 DDI_BUF_TRANS_D_S5T1,
333 DDI_BUF_TRANS_D_S5T2,
334 DDI_BUF_TRANS_D_S6T1,
335 DDI_BUF_TRANS_D_S6T2,
336 DDI_BUF_TRANS_D_S7T1,
337 DDI_BUF_TRANS_D_S7T2,
338 DDI_BUF_TRANS_D_S8T1,
339 DDI_BUF_TRANS_D_S8T2,
340 DDI_BUF_TRANS_D_S9T1,
341 DDI_BUF_TRANS_D_S9T2,
342 DDI_BUF_TRANS_E_S0T1,
343 DDI_BUF_TRANS_E_S0T2,
344 DDI_BUF_TRANS_E_S1T1,
345 DDI_BUF_TRANS_E_S1T2,
346 DDI_BUF_TRANS_E_S2T1,
347 DDI_BUF_TRANS_E_S2T2,
348 DDI_BUF_TRANS_E_S3T1,
349 DDI_BUF_TRANS_E_S3T2,
350 DDI_BUF_TRANS_E_S4T1,
351 DDI_BUF_TRANS_E_S4T2,
352 DDI_BUF_TRANS_E_S5T1,
353 DDI_BUF_TRANS_E_S5T2,
354 DDI_BUF_TRANS_E_S6T1,
355 DDI_BUF_TRANS_E_S6T2,
356 DDI_BUF_TRANS_E_S7T1,
357 DDI_BUF_TRANS_E_S7T2,
358 DDI_BUF_TRANS_E_S8T1,
359 DDI_BUF_TRANS_E_S8T2,
360 DDI_BUF_TRANS_E_S9T1,
361 DDI_BUF_TRANS_E_S9T2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]362 AUD_VID_DID,
363 PFA_WIN_POS,
364 PFA_WIN_SZ,
365 PFA_CTL_1,
366 PS_WIN_POS_1_A,
367 PS_WIN_SZ_1_A,
368 PS_CTRL_1_A,
369 PS_WIN_POS_2_A,
370 PS_WIN_SZ_2_A,
371 PS_CTRL_2_A,
372 PFB_WIN_POS,
373 PFB_WIN_SZ,
374 PFB_CTL_1,
375 PS_WIN_POS_1_B,
376 PS_WIN_SZ_1_B,
377 PS_CTRL_1_B,
378 PS_WIN_POS_2_B,
379 PS_WIN_SZ_2_B,
380 PS_CTRL_2_B,
381 PFC_WIN_POS,
382 PFC_WIN_SZ,
383 PFC_CTL_1,
384 PS_WIN_POS_1_C,
385 PS_WIN_SZ_1_C,
386 PS_CTRL_1_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]387 BXT_PORT_CL1CM_DW0_BC,
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]388 DISPIO_CR_TX_BMU_CR0,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]389 BXT_PORT_CL1CM_DW9_BC,
390 BXT_PORT_CL1CM_DW10_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]391 BXT_PORT_PLL_EBB_0_B,
392 BXT_PORT_PLL_EBB_4_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]393 DPLL1_CFGR1,
394 DPLL1_CFGR2,
395 DPLL2_CFGR1,
396 DPLL2_CFGR2,
397 DPLL3_CFGR1,
398 DPLL3_CFGR2,
399 DPLL_CTRL1,
400 DPLL_CTRL2,
401 DPLL_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]402 BXT_PORT_CL1CM_DW28_BC,
403 BXT_PORT_CL1CM_DW30_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]404 BXT_PORT_PLL_0_B,
405 BXT_PORT_PLL_1_B,
406 BXT_PORT_PLL_2_B,
407 BXT_PORT_PLL_3_B,
408 BXT_PORT_PLL_6_B,
409 BXT_PORT_PLL_8_B,
410 BXT_PORT_PLL_9_B,
411 BXT_PORT_PLL_10_B,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]412 BXT_PORT_REF_DW3_BC,
413 BXT_PORT_REF_DW6_BC,
414 BXT_PORT_REF_DW8_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]415 BXT_PORT_PLL_EBB_0_C,
416 BXT_PORT_PLL_EBB_4_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]417 BXT_PORT_CL2CM_DW6_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]418 BXT_PORT_PLL_0_C,
419 BXT_PORT_PLL_1_C,
420 BXT_PORT_PLL_2_C,
421 BXT_PORT_PLL_3_C,
422 BXT_PORT_PLL_6_C,
423 BXT_PORT_PLL_8_C,
424 BXT_PORT_PLL_9_C,
425 BXT_PORT_PLL_10_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]426 BXT_PORT_PCS_DW10_01_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]427 BXT_PORT_PCS_DW12_01_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]428 BXT_PORT_TX_DW2_LN0_B,
429 BXT_PORT_TX_DW3_LN0_B,
430 BXT_PORT_TX_DW4_LN0_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]431 BXT_PORT_TX_DW14_LN0_B,
432 BXT_PORT_TX_DW14_LN1_B,
433 BXT_PORT_TX_DW14_LN2_B,
434 BXT_PORT_TX_DW14_LN3_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]435 BXT_PORT_PCS_DW10_01_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]436 BXT_PORT_PCS_DW12_01_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]437 BXT_PORT_TX_DW2_LN0_C,
438 BXT_PORT_TX_DW3_LN0_C,
439 BXT_PORT_TX_DW4_LN0_C,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]440 BXT_PORT_TX_DW14_LN0_C,
441 BXT_PORT_TX_DW14_LN1_C,
442 BXT_PORT_TX_DW14_LN2_C,
443 BXT_PORT_TX_DW14_LN3_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]444 BXT_PORT_PCS_DW10_GRP_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]445 BXT_PORT_PCS_DW12_GRP_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]446 BXT_PORT_TX_DW2_GRP_B,
447 BXT_PORT_TX_DW3_GRP_B,
448 BXT_PORT_TX_DW4_GRP_B,
449 BXT_PORT_PCS_DW10_GRP_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]450 BXT_PORT_PCS_DW12_GRP_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]451 BXT_PORT_TX_DW2_GRP_C,
452 BXT_PORT_TX_DW3_GRP_C,
453 BXT_PORT_TX_DW4_GRP_C,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]454 BXT_DE_PLL_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]455 HTOTAL_EDP,
456 HBLANK_EDP,
457 HSYNC_EDP,
458 VTOTAL_EDP,
459 VBLANK_EDP,
460 VSYNC_EDP,
461 PIPE_EDP_DATA_M1,
462 PIPE_EDP_DATA_N1,
463 PIPE_EDP_LINK_M1,
464 PIPE_EDP_LINK_N1,
465 PIPE_EDP_DDI_FUNC_CTL,
466 PIPE_EDP_MSA_MISC,
467 SRD_CTL_EDP,
468 SRD_STATUS_EDP,
469 PIPE_SCANLINE_A,
470 PIPEACONF,
471 PIPEAMISC,
472 PIPE_FRMCNT_A,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]473 PIPEA_GMCH_DATA_M,
474 PIPEA_GMCH_DATA_N,
475 PIPEA_GMCH_LINK_M,
476 PIPEA_GMCH_LINK_N,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]477 CUR_CTL_A,
478 CUR_BASE_A,
479 CUR_POS_A,
480 CUR_FBC_CTL_A,
Nico Huber75a707f2018-06-18 16:28:33 +0200[diff] [blame]481 CURBCNTR,
482 CURBBASE,
483 CURBPOS,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]484 CUR_WM_A_0,
485 CUR_WM_A_1,
486 CUR_WM_A_2,
487 CUR_WM_A_3,
488 CUR_WM_A_4,
489 CUR_WM_A_5,
490 CUR_WM_A_6,
491 CUR_WM_A_7,
492 CUR_BUF_CFG_A,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]493 DSPACNTR,
494 DSPALINOFF,
495 DSPASTRIDE,
496 PLANE_POS_1_A,
497 PLANE_SIZE_1_A,
498 DSPASURF,
499 DSPATILEOFF,
500 PLANE_WM_1_A_0,
501 PLANE_WM_1_A_1,
502 PLANE_WM_1_A_2,
503 PLANE_WM_1_A_3,
504 PLANE_WM_1_A_4,
505 PLANE_WM_1_A_5,
506 PLANE_WM_1_A_6,
507 PLANE_WM_1_A_7,
508 PLANE_BUF_CFG_1_A,
509 SPACNTR,
510 PIPE_SCANLINE_B,
511 PIPEBCONF,
512 PIPEBMISC,
513 PIPE_FRMCNT_B,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]514 PIPEB_GMCH_DATA_M,
515 PIPEB_GMCH_DATA_N,
516 PIPEB_GMCH_LINK_M,
517 PIPEB_GMCH_LINK_N,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]518 CUR_CTL_B,
519 CUR_BASE_B,
520 CUR_POS_B,
521 CUR_FBC_CTL_B,
522 CUR_WM_B_0,
523 CUR_WM_B_1,
524 CUR_WM_B_2,
525 CUR_WM_B_3,
526 CUR_WM_B_4,
527 CUR_WM_B_5,
528 CUR_WM_B_6,
529 CUR_WM_B_7,
530 CUR_BUF_CFG_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]531 DSPBCNTR,
532 DSPBLINOFF,
533 DSPBSTRIDE,
534 PLANE_POS_1_B,
535 PLANE_SIZE_1_B,
536 DSPBSURF,
537 DSPBTILEOFF,
538 PLANE_WM_1_B_0,
539 PLANE_WM_1_B_1,
540 PLANE_WM_1_B_2,
541 PLANE_WM_1_B_3,
542 PLANE_WM_1_B_4,
543 PLANE_WM_1_B_5,
544 PLANE_WM_1_B_6,
545 PLANE_WM_1_B_7,
546 PLANE_BUF_CFG_1_B,
547 SPBCNTR,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]548 GMCH_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]549 PIPE_SCANLINE_C,
550 PIPECCONF,
551 PIPECMISC,
552 PIPE_FRMCNT_C,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]553 CUR_CTL_C,
554 CUR_BASE_C,
555 CUR_POS_C,
556 CUR_FBC_CTL_C,
557 CUR_WM_C_0,
558 CUR_WM_C_1,
559 CUR_WM_C_2,
560 CUR_WM_C_3,
561 CUR_WM_C_4,
562 CUR_WM_C_5,
563 CUR_WM_C_6,
564 CUR_WM_C_7,
565 CUR_BUF_CFG_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]566 DSPCCNTR,
567 DSPCLINOFF,
568 DSPCSTRIDE,
569 PLANE_POS_1_C,
570 PLANE_SIZE_1_C,
571 DSPCSURF,
572 DSPCTILEOFF,
573 PLANE_WM_1_C_0,
574 PLANE_WM_1_C_1,
575 PLANE_WM_1_C_2,
576 PLANE_WM_1_C_3,
577 PLANE_WM_1_C_4,
578 PLANE_WM_1_C_5,
579 PLANE_WM_1_C_6,
580 PLANE_WM_1_C_7,
581 PLANE_BUF_CFG_1_C,
582 SPCCNTR,
583 PIPE_EDP_CONF,
584 PCH_FDI_CHICKEN_B_C,
585 QUIRK_C2004,
586 SFUSE_STRAP,
587 PCH_DSPCLK_GATE_D,
588 SDEISR,
589 SDEIMR,
590 SDEIIR,
591 SDEIER,
592 SHOTPLUG_CTL,
593 PCH_GMBUS0,
594 PCH_GMBUS1,
595 PCH_GMBUS2,
596 PCH_GMBUS3,
597 PCH_GMBUS4,
598 PCH_GMBUS5,
599 SBI_ADDR,
600 SBI_DATA,
601 SBI_CTL_STAT,
602 PCH_DPLL_A,
603 PCH_DPLL_B,
604 PCH_PIXCLK_GATE,
605 PCH_FPA0,
606 PCH_FPA1,
607 PCH_FPB0,
608 PCH_FPB1,
609 PCH_DREF_CONTROL,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]610 PCH_RAWCLK_FREQ,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]611 PCH_DPLL_SEL,
612 PCH_PP_STATUS,
613 PCH_PP_CONTROL,
614 PCH_PP_ON_DELAYS,
615 PCH_PP_OFF_DELAYS,
616 PCH_PP_DIVISOR,
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]617 BXT_PP_STATUS_2,
618 BXT_PP_CONTROL_2,
619 BXT_PP_ON_DELAYS_2,
620 BXT_PP_OFF_DELAYS_2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]621 BLC_PWM_PCH_CTL1,
622 BLC_PWM_PCH_CTL2,
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]623 BXT_BLC_PWM_DUTY_1,
624 BXT_BLC_PWM_CTL_2,
625 BXT_BLC_PWM_FREQ_2,
626 BXT_BLC_PWM_DUTY_2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]627 TRANS_HTOTAL_A,
628 TRANS_HBLANK_A,
629 TRANS_HSYNC_A,
630 TRANS_VTOTAL_A,
631 TRANS_VBLANK_A,
632 TRANS_VSYNC_A,
633 TRANS_VSYNCSHIFT_A,
634 TRANSA_DATA_M1,
635 TRANSA_DATA_N1,
636 TRANSA_DP_LINK_M1,
637 TRANSA_DP_LINK_N1,
638 TRANS_DP_CTL_A,
639 TRANS_HTOTAL_B,
640 TRANS_HBLANK_B,
641 TRANS_HSYNC_B,
642 TRANS_VTOTAL_B,
643 TRANS_VBLANK_B,
644 TRANS_VSYNC_B,
645 TRANS_VSYNCSHIFT_B,
646 TRANSB_DATA_M1,
647 TRANSB_DATA_N1,
648 TRANSB_DP_LINK_M1,
649 TRANSB_DP_LINK_N1,
650 PCH_ADPA,
651 PCH_HDMIB,
652 PCH_HDMIC,
653 PCH_HDMID,
654 PCH_LVDS,
655 TRANS_DP_CTL_B,
656 TRANS_HTOTAL_C,
657 TRANS_HBLANK_C,
658 TRANS_HSYNC_C,
659 TRANS_VTOTAL_C,
660 TRANS_VBLANK_C,
661 TRANS_VSYNC_C,
662 TRANS_VSYNCSHIFT_C,
663 TRANSC_DATA_M1,
664 TRANSC_DATA_N1,
665 TRANSC_DP_LINK_M1,
666 TRANSC_DP_LINK_N1,
667 TRANS_DP_CTL_C,
668 PCH_DP_B,
669 PCH_DP_AUX_CTL_B,
670 PCH_DP_AUX_DATA_B_1,
671 PCH_DP_AUX_DATA_B_2,
672 PCH_DP_AUX_DATA_B_3,
673 PCH_DP_AUX_DATA_B_4,
674 PCH_DP_AUX_DATA_B_5,
675 PCH_DP_C,
676 PCH_DP_AUX_CTL_C,
677 PCH_DP_AUX_DATA_C_1,
678 PCH_DP_AUX_DATA_C_2,
679 PCH_DP_AUX_DATA_C_3,
680 PCH_DP_AUX_DATA_C_4,
681 PCH_DP_AUX_DATA_C_5,
682 PCH_DP_D,
683 PCH_DP_AUX_CTL_D,
684 PCH_DP_AUX_DATA_D_1,
685 PCH_DP_AUX_DATA_D_2,
686 PCH_DP_AUX_DATA_D_3,
687 PCH_DP_AUX_DATA_D_4,
688 PCH_DP_AUX_DATA_D_5,
689 AUD_CONFIG_A,
690 PCH_AUD_VID_DID,
691 AUD_HDMIW_HDMIEDID_A,
692 AUD_CNTL_ST_A,
693 AUD_CNTRL_ST2,
694 AUD_CONFIG_B,
695 AUD_HDMIW_HDMIEDID_B,
696 AUD_CNTL_ST_B,
697 AUD_CONFIG_C,
698 AUD_HDMIW_HDMIEDID_C,
699 AUD_CNTL_ST_C,
700 TRANSACONF,
701 FDI_RXA_CTL,
702 FDI_RX_MISC_A,
703 FDI_RXA_IIR,
704 FDI_RXA_IMR,
705 FDI_RXA_TUSIZE1,
706 QUIRK_F0060,
707 TRANSA_CHICKEN2,
708 TRANSBCONF,
709 FDI_RXB_CTL,
710 FDI_RX_MISC_B,
711 FDI_RXB_IIR,
712 FDI_RXB_IMR,
713 FDI_RXB_TUSIZE1,
714 QUIRK_F1060,
715 TRANSB_CHICKEN2,
716 TRANSCCONF,
717 FDI_RXC_CTL,
718 FDI_RX_MISC_C,
719 FDI_RXC_IIR,
720 FDI_RXC_IMR,
721 FDI_RXC_TUSIZE1,
722 QUIRK_F2060,
723 TRANSC_CHICKEN2,
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]724 LCPLL_CTL,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]725 BXT_P_CR_GT_DISP_PWRON,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]726 GT_MAILBOX,
727 GT_MAILBOX_DATA,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]728 GT_MAILBOX_DATA_1,
729 BXT_PORT_CL1CM_DW0_A,
730 BXT_PORT_CL1CM_DW9_A,
731 BXT_PORT_CL1CM_DW10_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]732 BXT_PORT_PLL_EBB_0_A,
733 BXT_PORT_PLL_EBB_4_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]734 BXT_PORT_CL1CM_DW28_A,
735 BXT_PORT_CL1CM_DW30_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]736 BXT_PORT_PLL_0_A,
737 BXT_PORT_PLL_1_A,
738 BXT_PORT_PLL_2_A,
739 BXT_PORT_PLL_3_A,
740 BXT_PORT_PLL_6_A,
741 BXT_PORT_PLL_8_A,
742 BXT_PORT_PLL_9_A,
743 BXT_PORT_PLL_10_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]744 BXT_PORT_REF_DW3_A,
745 BXT_PORT_REF_DW6_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]746 BXT_PORT_REF_DW8_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]747 BXT_PORT_PCS_DW10_01_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]748 BXT_PORT_PCS_DW12_01_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]749 BXT_PORT_TX_DW2_LN0_A,
750 BXT_PORT_TX_DW3_LN0_A,
751 BXT_PORT_TX_DW4_LN0_A,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]752 BXT_PORT_TX_DW14_LN0_A,
753 BXT_PORT_TX_DW14_LN1_A,
754 BXT_PORT_TX_DW14_LN2_A,
755 BXT_PORT_TX_DW14_LN3_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]756 BXT_PORT_PCS_DW10_GRP_A,
757 BXT_PORT_PCS_DW12_GRP_A,
758 BXT_PORT_TX_DW2_GRP_A,
759 BXT_PORT_TX_DW3_GRP_A,
760 BXT_PORT_TX_DW4_GRP_A);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]761
762 pragma Warnings
763 (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)",
764 Reason => "TODO: Should it matter?");
765 pragma Keep_Names (Registers_Invalid_Index);
766 pragma Warnings
767 (GNATprove, On, "pragma ""KEEP_NAMES"" ignored *(not yet supported)");
768
769 Register_Width : constant := 4;
770
771 for Registers_Invalid_Index use
772 (Invalid_Register => 0,
773
774 ---------------------------------------------------------------------------
775 -- Pipe A registers
776 ---------------------------------------------------------------------------
777
778 -- pipe timing registers
779
780 HTOTAL_A => 16#06_0000# / Register_Width,
781 HBLANK_A => 16#06_0004# / Register_Width,
782 HSYNC_A => 16#06_0008# / Register_Width,
783 VTOTAL_A => 16#06_000c# / Register_Width,
784 VBLANK_A => 16#06_0010# / Register_Width,
785 VSYNC_A => 16#06_0014# / Register_Width,
786 PIPEASRC => 16#06_001c# / Register_Width,
787 PIPEACONF => 16#07_0008# / Register_Width,
788 PIPEAMISC => 16#07_0030# / Register_Width,
789 TRANS_HTOTAL_A => 16#0e_0000# / Register_Width,
790 TRANS_HBLANK_A => 16#0e_0004# / Register_Width,
791 TRANS_HSYNC_A => 16#0e_0008# / Register_Width,
792 TRANS_VTOTAL_A => 16#0e_000c# / Register_Width,
793 TRANS_VBLANK_A => 16#0e_0010# / Register_Width,
794 TRANS_VSYNC_A => 16#0e_0014# / Register_Width,
795 TRANSA_DATA_M1 => 16#0e_0030# / Register_Width,
796 TRANSA_DATA_N1 => 16#0e_0034# / Register_Width,
797 TRANSA_DP_LINK_M1 => 16#0e_0040# / Register_Width,
798 TRANSA_DP_LINK_N1 => 16#0e_0044# / Register_Width,
799 PIPEA_DATA_M1 => 16#06_0030# / Register_Width,
800 PIPEA_DATA_N1 => 16#06_0034# / Register_Width,
801 PIPEA_LINK_M1 => 16#06_0040# / Register_Width,
802 PIPEA_LINK_N1 => 16#06_0044# / Register_Width,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]803 PIPEA_GMCH_DATA_M => 16#07_0050# / Register_Width,
804 PIPEA_GMCH_DATA_N => 16#07_0054# / Register_Width,
805 PIPEA_GMCH_LINK_M => 16#07_0060# / Register_Width,
806 PIPEA_GMCH_LINK_N => 16#07_0064# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]807 PIPEA_DDI_FUNC_CTL => 16#06_0400# / Register_Width,
808 PIPEA_MSA_MISC => 16#06_0410# / Register_Width,
809
810 -- PCH sideband interface registers
811 SBI_ADDR => 16#0c_6000# / Register_Width,
812 SBI_DATA => 16#0c_6004# / Register_Width,
813 SBI_CTL_STAT => 16#0c_6008# / Register_Width,
814
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]815 -- GMCH clock registers
816 GMCH_DPLL_A => 16#00_6014# / Register_Width,
817 GMCH_FPA0 => 16#00_6040# / Register_Width,
818 GMCH_FPA1 => 16#00_6044# / Register_Width,
819
820 -- PCH clock registers
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]821 PCH_DPLL_A => 16#0c_6014# / Register_Width,
822 PCH_PIXCLK_GATE => 16#0c_6020# / Register_Width,
823 PCH_FPA0 => 16#0c_6040# / Register_Width,
824 PCH_FPA1 => 16#0c_6044# / Register_Width,
825
826 -- panel fitter
827 PFA_CTL_1 => 16#06_8080# / Register_Width,
828 PFA_WIN_POS => 16#06_8070# / Register_Width,
829 PFA_WIN_SZ => 16#06_8074# / Register_Width,
830 PS_WIN_POS_1_A => 16#06_8170# / Register_Width,
831 PS_WIN_SZ_1_A => 16#06_8174# / Register_Width,
832 PS_CTRL_1_A => 16#06_8180# / Register_Width,
833 PS_WIN_POS_2_A => 16#06_8270# / Register_Width,
834 PS_WIN_SZ_2_A => 16#06_8274# / Register_Width,
835 PS_CTRL_2_A => 16#06_8280# / Register_Width,
836
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]837 -- cursor control
838 CUR_CTL_A => 16#07_0080# / Register_Width,
839 CUR_BASE_A => 16#07_0084# / Register_Width,
840 CUR_POS_A => 16#07_0088# / Register_Width,
841 CUR_FBC_CTL_A => 16#07_00a0# / Register_Width,
842
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]843 -- display control
844 DSPACNTR => 16#07_0180# / Register_Width,
845 DSPALINOFF => 16#07_0184# / Register_Width,
846 DSPASTRIDE => 16#07_0188# / Register_Width,
847 PLANE_POS_1_A => 16#07_018c# / Register_Width,
848 PLANE_SIZE_1_A => 16#07_0190# / Register_Width,
849 DSPASURF => 16#07_019c# / Register_Width,
850 DSPATILEOFF => 16#07_01a4# / Register_Width,
851
852 -- sprite control
853 SPACNTR => 16#07_0280# / Register_Width,
854
855 -- FDI and PCH transcoder control
856 FDI_TX_CTL_A => 16#06_0100# / Register_Width,
857 FDI_RXA_CTL => 16#0f_000c# / Register_Width,
858 FDI_RX_MISC_A => 16#0f_0010# / Register_Width,
859 FDI_RXA_IIR => 16#0f_0014# / Register_Width,
860 FDI_RXA_IMR => 16#0f_0018# / Register_Width,
861 FDI_RXA_TUSIZE1 => 16#0f_0030# / Register_Width,
862 TRANSACONF => 16#0f_0008# / Register_Width,
863 TRANSA_CHICKEN2 => 16#0f_0064# / Register_Width,
864
865 -- watermark registers
866 WM_LINETIME_A => 16#04_5270# / Register_Width,
867 PLANE_WM_1_A_0 => 16#07_0240# / Register_Width,
868 PLANE_WM_1_A_1 => 16#07_0244# / Register_Width,
869 PLANE_WM_1_A_2 => 16#07_0248# / Register_Width,
870 PLANE_WM_1_A_3 => 16#07_024c# / Register_Width,
871 PLANE_WM_1_A_4 => 16#07_0250# / Register_Width,
872 PLANE_WM_1_A_5 => 16#07_0254# / Register_Width,
873 PLANE_WM_1_A_6 => 16#07_0258# / Register_Width,
874 PLANE_WM_1_A_7 => 16#07_025c# / Register_Width,
875 PLANE_BUF_CFG_1_A => 16#07_027c# / Register_Width,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]876 CUR_WM_A_0 => 16#07_0140# / Register_Width,
877 CUR_WM_A_1 => 16#07_0144# / Register_Width,
878 CUR_WM_A_2 => 16#07_0148# / Register_Width,
879 CUR_WM_A_3 => 16#07_014c# / Register_Width,
880 CUR_WM_A_4 => 16#07_0150# / Register_Width,
881 CUR_WM_A_5 => 16#07_0154# / Register_Width,
882 CUR_WM_A_6 => 16#07_0158# / Register_Width,
883 CUR_WM_A_7 => 16#07_015c# / Register_Width,
884 CUR_BUF_CFG_A => 16#07_017c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]885
886 -- CPU transcoder clock select
887 TRANSA_CLK_SEL => 16#04_6140# / Register_Width,
888
889 ---------------------------------------------------------------------------
890 -- Pipe B registers
891 ---------------------------------------------------------------------------
892
893 -- pipe timing registers
894
895 HTOTAL_B => 16#06_1000# / Register_Width,
896 HBLANK_B => 16#06_1004# / Register_Width,
897 HSYNC_B => 16#06_1008# / Register_Width,
898 VTOTAL_B => 16#06_100c# / Register_Width,
899 VBLANK_B => 16#06_1010# / Register_Width,
900 VSYNC_B => 16#06_1014# / Register_Width,
901 PIPEBSRC => 16#06_101c# / Register_Width,
902 PIPEBCONF => 16#07_1008# / Register_Width,
903 PIPEBMISC => 16#07_1030# / Register_Width,
904 TRANS_HTOTAL_B => 16#0e_1000# / Register_Width,
905 TRANS_HBLANK_B => 16#0e_1004# / Register_Width,
906 TRANS_HSYNC_B => 16#0e_1008# / Register_Width,
907 TRANS_VTOTAL_B => 16#0e_100c# / Register_Width,
908 TRANS_VBLANK_B => 16#0e_1010# / Register_Width,
909 TRANS_VSYNC_B => 16#0e_1014# / Register_Width,
910 TRANSB_DATA_M1 => 16#0e_1030# / Register_Width,
911 TRANSB_DATA_N1 => 16#0e_1034# / Register_Width,
912 TRANSB_DP_LINK_M1 => 16#0e_1040# / Register_Width,
913 TRANSB_DP_LINK_N1 => 16#0e_1044# / Register_Width,
914 PIPEB_DATA_M1 => 16#06_1030# / Register_Width,
915 PIPEB_DATA_N1 => 16#06_1034# / Register_Width,
916 PIPEB_LINK_M1 => 16#06_1040# / Register_Width,
917 PIPEB_LINK_N1 => 16#06_1044# / Register_Width,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]918 PIPEB_GMCH_DATA_M => 16#07_1050# / Register_Width,
919 PIPEB_GMCH_DATA_N => 16#07_1054# / Register_Width,
920 PIPEB_GMCH_LINK_M => 16#07_1060# / Register_Width,
921 PIPEB_GMCH_LINK_N => 16#07_1064# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]922 PIPEB_DDI_FUNC_CTL => 16#06_1400# / Register_Width,
923 PIPEB_MSA_MISC => 16#06_1410# / Register_Width,
924
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]925 -- GMCH clock registers
926 GMCH_DPLL_B => 16#00_6018# / Register_Width,
927 GMCH_FPB0 => 16#00_6048# / Register_Width,
928 GMCH_FPB1 => 16#00_604c# / Register_Width,
929
930 -- PCH clock registers
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]931 PCH_DPLL_B => 16#0c_6018# / Register_Width,
932 PCH_FPB0 => 16#0c_6048# / Register_Width,
933 PCH_FPB1 => 16#0c_604c# / Register_Width,
934
935 -- panel fitter
936 PFB_CTL_1 => 16#06_8880# / Register_Width,
937 PFB_WIN_POS => 16#06_8870# / Register_Width,
938 PFB_WIN_SZ => 16#06_8874# / Register_Width,
939 PS_WIN_POS_1_B => 16#06_8970# / Register_Width,
940 PS_WIN_SZ_1_B => 16#06_8974# / Register_Width,
941 PS_CTRL_1_B => 16#06_8980# / Register_Width,
942 PS_WIN_POS_2_B => 16#06_8a70# / Register_Width,
943 PS_WIN_SZ_2_B => 16#06_8a74# / Register_Width,
944 PS_CTRL_2_B => 16#06_8a80# / Register_Width,
945
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]946 -- cursor control
Nico Huber75a707f2018-06-18 16:28:33 +0200[diff] [blame]947 CURBCNTR => 16#07_00c0# / Register_Width, -- <= SNB
948 CURBBASE => 16#07_00c4# / Register_Width, -- <= SNB
949 CURBPOS => 16#07_00c8# / Register_Width, -- <= SNB
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]950 CUR_CTL_B => 16#07_1080# / Register_Width,
951 CUR_BASE_B => 16#07_1084# / Register_Width,
952 CUR_POS_B => 16#07_1088# / Register_Width,
953 CUR_FBC_CTL_B => 16#07_10a0# / Register_Width,
954
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]955 -- display control
956 DSPBCNTR => 16#07_1180# / Register_Width,
957 DSPBLINOFF => 16#07_1184# / Register_Width,
958 DSPBSTRIDE => 16#07_1188# / Register_Width,
959 PLANE_POS_1_B => 16#07_118c# / Register_Width,
960 PLANE_SIZE_1_B => 16#07_1190# / Register_Width,
961 DSPBSURF => 16#07_119c# / Register_Width,
962 DSPBTILEOFF => 16#07_11a4# / Register_Width,
963
964 -- sprite control
965 SPBCNTR => 16#07_1280# / Register_Width,
966
967 -- FDI and PCH transcoder control
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]968 FDI_TX_CTL_B => 16#06_1100# / Register_Width, -- aliased by GMCH_ADPA
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]969 FDI_RXB_CTL => 16#0f_100c# / Register_Width,
970 FDI_RX_MISC_B => 16#0f_1010# / Register_Width,
971 FDI_RXB_IIR => 16#0f_1014# / Register_Width,
972 FDI_RXB_IMR => 16#0f_1018# / Register_Width,
973 FDI_RXB_TUSIZE1 => 16#0f_1030# / Register_Width,
974 TRANSBCONF => 16#0f_1008# / Register_Width,
975 TRANSB_CHICKEN2 => 16#0f_1064# / Register_Width,
976
977 -- watermark registers
978 WM_LINETIME_B => 16#04_5274# / Register_Width,
979 PLANE_WM_1_B_0 => 16#07_1240# / Register_Width,
980 PLANE_WM_1_B_1 => 16#07_1244# / Register_Width,
981 PLANE_WM_1_B_2 => 16#07_1248# / Register_Width,
982 PLANE_WM_1_B_3 => 16#07_124c# / Register_Width,
983 PLANE_WM_1_B_4 => 16#07_1250# / Register_Width,
984 PLANE_WM_1_B_5 => 16#07_1254# / Register_Width,
985 PLANE_WM_1_B_6 => 16#07_1258# / Register_Width,
986 PLANE_WM_1_B_7 => 16#07_125c# / Register_Width,
987 PLANE_BUF_CFG_1_B => 16#07_127c# / Register_Width,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]988 CUR_WM_B_0 => 16#07_1140# / Register_Width,
989 CUR_WM_B_1 => 16#07_1144# / Register_Width,
990 CUR_WM_B_2 => 16#07_1148# / Register_Width,
991 CUR_WM_B_3 => 16#07_114c# / Register_Width,
992 CUR_WM_B_4 => 16#07_1150# / Register_Width,
993 CUR_WM_B_5 => 16#07_1154# / Register_Width,
994 CUR_WM_B_6 => 16#07_1158# / Register_Width,
995 CUR_WM_B_7 => 16#07_115c# / Register_Width,
996 CUR_BUF_CFG_B => 16#07_117c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]997
998 -- CPU transcoder clock select
999 TRANSB_CLK_SEL => 16#04_6144# / Register_Width,
1000
1001 ---------------------------------------------------------------------------
1002 -- Pipe C registers
1003 ---------------------------------------------------------------------------
1004
1005 -- pipe timing registers
1006
1007 HTOTAL_C => 16#06_2000# / Register_Width,
1008 HBLANK_C => 16#06_2004# / Register_Width,
1009 HSYNC_C => 16#06_2008# / Register_Width,
1010 VTOTAL_C => 16#06_200c# / Register_Width,
1011 VBLANK_C => 16#06_2010# / Register_Width,
1012 VSYNC_C => 16#06_2014# / Register_Width,
1013 PIPECSRC => 16#06_201c# / Register_Width,
1014 PIPECCONF => 16#07_2008# / Register_Width,
1015 PIPECMISC => 16#07_2030# / Register_Width,
1016 TRANS_HTOTAL_C => 16#0e_2000# / Register_Width,
1017 TRANS_HBLANK_C => 16#0e_2004# / Register_Width,
1018 TRANS_HSYNC_C => 16#0e_2008# / Register_Width,
1019 TRANS_VTOTAL_C => 16#0e_200c# / Register_Width,
1020 TRANS_VBLANK_C => 16#0e_2010# / Register_Width,
1021 TRANS_VSYNC_C => 16#0e_2014# / Register_Width,
1022 TRANSC_DATA_M1 => 16#0e_2030# / Register_Width,
1023 TRANSC_DATA_N1 => 16#0e_2034# / Register_Width,
1024 TRANSC_DP_LINK_M1 => 16#0e_2040# / Register_Width,
1025 TRANSC_DP_LINK_N1 => 16#0e_2044# / Register_Width,
1026 PIPEC_DATA_M1 => 16#06_2030# / Register_Width,
1027 PIPEC_DATA_N1 => 16#06_2034# / Register_Width,
1028 PIPEC_LINK_M1 => 16#06_2040# / Register_Width,
1029 PIPEC_LINK_N1 => 16#06_2044# / Register_Width,
1030 PIPEC_DDI_FUNC_CTL => 16#06_2400# / Register_Width,
1031 PIPEC_MSA_MISC => 16#06_2410# / Register_Width,
1032
1033 -- panel fitter
1034 PFC_CTL_1 => 16#06_9080# / Register_Width,
1035 PFC_WIN_POS => 16#06_9070# / Register_Width,
1036 PFC_WIN_SZ => 16#06_9074# / Register_Width,
1037 PS_WIN_POS_1_C => 16#06_9170# / Register_Width,
1038 PS_WIN_SZ_1_C => 16#06_9174# / Register_Width,
1039 PS_CTRL_1_C => 16#06_9180# / Register_Width,
1040
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1041 -- cursor control
1042 CUR_CTL_C => 16#07_2080# / Register_Width,
1043 CUR_BASE_C => 16#07_2084# / Register_Width,
1044 CUR_POS_C => 16#07_2088# / Register_Width,
1045 CUR_FBC_CTL_C => 16#07_20a0# / Register_Width,
1046
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1047 -- display control
1048 DSPCCNTR => 16#07_2180# / Register_Width,
1049 DSPCLINOFF => 16#07_2184# / Register_Width,
1050 DSPCSTRIDE => 16#07_2188# / Register_Width,
1051 PLANE_POS_1_C => 16#07_218c# / Register_Width,
1052 PLANE_SIZE_1_C => 16#07_2190# / Register_Width,
1053 DSPCSURF => 16#07_219c# / Register_Width,
1054 DSPCTILEOFF => 16#07_21a4# / Register_Width,
1055
1056 -- sprite control
1057 SPCCNTR => 16#07_2280# / Register_Width,
1058
1059 -- PCH transcoder control
1060 FDI_TX_CTL_C => 16#06_2100# / Register_Width,
1061 FDI_RXC_CTL => 16#0f_200c# / Register_Width,
1062 FDI_RX_MISC_C => 16#0f_2010# / Register_Width,
1063 FDI_RXC_IIR => 16#0f_2014# / Register_Width,
1064 FDI_RXC_IMR => 16#0f_2018# / Register_Width,
1065 FDI_RXC_TUSIZE1 => 16#0f_2030# / Register_Width,
1066 TRANSCCONF => 16#0f_2008# / Register_Width,
1067 TRANSC_CHICKEN2 => 16#0f_2064# / Register_Width,
1068
1069 -- watermark registers
1070 WM_LINETIME_C => 16#04_5278# / Register_Width,
1071 PLANE_WM_1_C_0 => 16#07_2240# / Register_Width,
1072 PLANE_WM_1_C_1 => 16#07_2244# / Register_Width,
1073 PLANE_WM_1_C_2 => 16#07_2248# / Register_Width,
1074 PLANE_WM_1_C_3 => 16#07_224c# / Register_Width,
1075 PLANE_WM_1_C_4 => 16#07_2250# / Register_Width,
1076 PLANE_WM_1_C_5 => 16#07_2254# / Register_Width,
1077 PLANE_WM_1_C_6 => 16#07_2258# / Register_Width,
1078 PLANE_WM_1_C_7 => 16#07_225c# / Register_Width,
1079 PLANE_BUF_CFG_1_C => 16#07_227c# / Register_Width,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1080 CUR_WM_C_0 => 16#07_2140# / Register_Width,
1081 CUR_WM_C_1 => 16#07_2144# / Register_Width,
1082 CUR_WM_C_2 => 16#07_2148# / Register_Width,
1083 CUR_WM_C_3 => 16#07_214c# / Register_Width,
1084 CUR_WM_C_4 => 16#07_2150# / Register_Width,
1085 CUR_WM_C_5 => 16#07_2154# / Register_Width,
1086 CUR_WM_C_6 => 16#07_2158# / Register_Width,
1087 CUR_WM_C_7 => 16#07_215c# / Register_Width,
1088 CUR_BUF_CFG_C => 16#07_217c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1089
1090 -- CPU transcoder clock select
1091 TRANSC_CLK_SEL => 16#04_6148# / Register_Width,
1092
1093 ---------------------------------------------------------------------------
1094 -- Pipe EDP registers
1095 ---------------------------------------------------------------------------
1096
1097 -- pipe timing registers
1098
1099 HTOTAL_EDP => 16#06_f000# / Register_Width,
1100 HBLANK_EDP => 16#06_f004# / Register_Width,
1101 HSYNC_EDP => 16#06_f008# / Register_Width,
1102 VTOTAL_EDP => 16#06_f00c# / Register_Width,
1103 VBLANK_EDP => 16#06_f010# / Register_Width,
1104 VSYNC_EDP => 16#06_f014# / Register_Width,
1105 PIPE_EDP_CONF => 16#07_f008# / Register_Width,
1106 PIPE_EDP_DATA_M1 => 16#06_f030# / Register_Width,
1107 PIPE_EDP_DATA_N1 => 16#06_f034# / Register_Width,
1108 PIPE_EDP_LINK_M1 => 16#06_f040# / Register_Width,
1109 PIPE_EDP_LINK_N1 => 16#06_f044# / Register_Width,
1110 PIPE_EDP_DDI_FUNC_CTL => 16#06_f400# / Register_Width,
1111 PIPE_EDP_MSA_MISC => 16#06_f410# / Register_Width,
1112
1113 -- PSR registers
1114 SRD_CTL => 16#06_4800# / Register_Width,
1115 SRD_CTL_A => 16#06_0800# / Register_Width,
1116 SRD_CTL_B => 16#06_1800# / Register_Width,
1117 SRD_CTL_C => 16#06_2800# / Register_Width,
1118 SRD_CTL_EDP => 16#06_f800# / Register_Width,
1119 SRD_STATUS => 16#06_4840# / Register_Width,
1120 SRD_STATUS_A => 16#06_0840# / Register_Width,
1121 SRD_STATUS_B => 16#06_1840# / Register_Width,
1122 SRD_STATUS_C => 16#06_2840# / Register_Width,
1123 SRD_STATUS_EDP => 16#06_f840# / Register_Width,
1124
1125 -- DDI registers
1126 DDI_BUF_CTL_A => 16#06_4000# / Register_Width, -- aliased by DP_CTL_A
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1127 DDI_BUF_TRANS_A_S0T1 => 16#06_4e00# / Register_Width,
1128 DDI_BUF_TRANS_A_S0T2 => 16#06_4e04# / Register_Width,
1129 DDI_BUF_TRANS_A_S1T1 => 16#06_4e08# / Register_Width,
1130 DDI_BUF_TRANS_A_S1T2 => 16#06_4e0c# / Register_Width,
1131 DDI_BUF_TRANS_A_S2T1 => 16#06_4e10# / Register_Width,
1132 DDI_BUF_TRANS_A_S2T2 => 16#06_4e14# / Register_Width,
1133 DDI_BUF_TRANS_A_S3T1 => 16#06_4e18# / Register_Width,
1134 DDI_BUF_TRANS_A_S3T2 => 16#06_4e1c# / Register_Width,
1135 DDI_BUF_TRANS_A_S4T1 => 16#06_4e20# / Register_Width,
1136 DDI_BUF_TRANS_A_S4T2 => 16#06_4e24# / Register_Width,
1137 DDI_BUF_TRANS_A_S5T1 => 16#06_4e28# / Register_Width,
1138 DDI_BUF_TRANS_A_S5T2 => 16#06_4e2c# / Register_Width,
1139 DDI_BUF_TRANS_A_S6T1 => 16#06_4e30# / Register_Width,
1140 DDI_BUF_TRANS_A_S6T2 => 16#06_4e34# / Register_Width,
1141 DDI_BUF_TRANS_A_S7T1 => 16#06_4e38# / Register_Width,
1142 DDI_BUF_TRANS_A_S7T2 => 16#06_4e3c# / Register_Width,
1143 DDI_BUF_TRANS_A_S8T1 => 16#06_4e40# / Register_Width,
1144 DDI_BUF_TRANS_A_S8T2 => 16#06_4e44# / Register_Width,
1145 DDI_BUF_TRANS_A_S9T1 => 16#06_4e48# / Register_Width,
1146 DDI_BUF_TRANS_A_S9T2 => 16#06_4e4c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1147 DDI_AUX_CTL_A => 16#06_4010# / Register_Width, -- aliased by DP_AUX_CTL_A
1148 DDI_AUX_DATA_A_1 => 16#06_4014# / Register_Width, -- aliased by DP_AUX_DATA_A_1
1149 DDI_AUX_DATA_A_2 => 16#06_4018# / Register_Width, -- aliased by DP_AUX_DATA_A_2
1150 DDI_AUX_DATA_A_3 => 16#06_401c# / Register_Width, -- aliased by DP_AUX_DATA_A_3
1151 DDI_AUX_DATA_A_4 => 16#06_4020# / Register_Width, -- aliased by DP_AUX_DATA_A_4
1152 DDI_AUX_DATA_A_5 => 16#06_4024# / Register_Width, -- aliased by DP_AUX_DATA_A_5
1153 DDI_AUX_MUTEX_A => 16#06_402c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1154
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1155 DDI_BUF_CTL_B => 16#06_4100# / Register_Width, -- aliased by GMCH_DP_B
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1156 DDI_BUF_TRANS_B_S0T1 => 16#06_4e60# / Register_Width,
1157 DDI_BUF_TRANS_B_S0T2 => 16#06_4e64# / Register_Width,
1158 DDI_BUF_TRANS_B_S1T1 => 16#06_4e68# / Register_Width,
1159 DDI_BUF_TRANS_B_S1T2 => 16#06_4e6c# / Register_Width,
1160 DDI_BUF_TRANS_B_S2T1 => 16#06_4e70# / Register_Width,
1161 DDI_BUF_TRANS_B_S2T2 => 16#06_4e74# / Register_Width,
1162 DDI_BUF_TRANS_B_S3T1 => 16#06_4e78# / Register_Width,
1163 DDI_BUF_TRANS_B_S3T2 => 16#06_4e7c# / Register_Width,
1164 DDI_BUF_TRANS_B_S4T1 => 16#06_4e80# / Register_Width,
1165 DDI_BUF_TRANS_B_S4T2 => 16#06_4e84# / Register_Width,
1166 DDI_BUF_TRANS_B_S5T1 => 16#06_4e88# / Register_Width,
1167 DDI_BUF_TRANS_B_S5T2 => 16#06_4e8c# / Register_Width,
1168 DDI_BUF_TRANS_B_S6T1 => 16#06_4e90# / Register_Width,
1169 DDI_BUF_TRANS_B_S6T2 => 16#06_4e94# / Register_Width,
1170 DDI_BUF_TRANS_B_S7T1 => 16#06_4e98# / Register_Width,
1171 DDI_BUF_TRANS_B_S7T2 => 16#06_4e9c# / Register_Width,
1172 DDI_BUF_TRANS_B_S8T1 => 16#06_4ea0# / Register_Width,
1173 DDI_BUF_TRANS_B_S8T2 => 16#06_4ea4# / Register_Width,
1174 DDI_BUF_TRANS_B_S9T1 => 16#06_4ea8# / Register_Width,
1175 DDI_BUF_TRANS_B_S9T2 => 16#06_4eac# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1176 DDI_AUX_CTL_B => 16#06_4110# / Register_Width,
1177 DDI_AUX_DATA_B_1 => 16#06_4114# / Register_Width,
1178 DDI_AUX_DATA_B_2 => 16#06_4118# / Register_Width,
1179 DDI_AUX_DATA_B_3 => 16#06_411c# / Register_Width,
1180 DDI_AUX_DATA_B_4 => 16#06_4120# / Register_Width,
1181 DDI_AUX_DATA_B_5 => 16#06_4124# / Register_Width,
1182 DDI_AUX_MUTEX_B => 16#06_412c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1183
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1184 DDI_BUF_CTL_C => 16#06_4200# / Register_Width, -- aliased by GMCH_DP_C
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1185 DDI_BUF_TRANS_C_S0T1 => 16#06_4ec0# / Register_Width,
1186 DDI_BUF_TRANS_C_S0T2 => 16#06_4ec4# / Register_Width,
1187 DDI_BUF_TRANS_C_S1T1 => 16#06_4ec8# / Register_Width,
1188 DDI_BUF_TRANS_C_S1T2 => 16#06_4ecc# / Register_Width,
1189 DDI_BUF_TRANS_C_S2T1 => 16#06_4ed0# / Register_Width,
1190 DDI_BUF_TRANS_C_S2T2 => 16#06_4ed4# / Register_Width,
1191 DDI_BUF_TRANS_C_S3T1 => 16#06_4ed8# / Register_Width,
1192 DDI_BUF_TRANS_C_S3T2 => 16#06_4edc# / Register_Width,
1193 DDI_BUF_TRANS_C_S4T1 => 16#06_4ee0# / Register_Width,
1194 DDI_BUF_TRANS_C_S4T2 => 16#06_4ee4# / Register_Width,
1195 DDI_BUF_TRANS_C_S5T1 => 16#06_4ee8# / Register_Width,
1196 DDI_BUF_TRANS_C_S5T2 => 16#06_4eec# / Register_Width,
1197 DDI_BUF_TRANS_C_S6T1 => 16#06_4ef0# / Register_Width,
1198 DDI_BUF_TRANS_C_S6T2 => 16#06_4ef4# / Register_Width,
1199 DDI_BUF_TRANS_C_S7T1 => 16#06_4ef8# / Register_Width,
1200 DDI_BUF_TRANS_C_S7T2 => 16#06_4efc# / Register_Width,
1201 DDI_BUF_TRANS_C_S8T1 => 16#06_4f00# / Register_Width,
1202 DDI_BUF_TRANS_C_S8T2 => 16#06_4f04# / Register_Width,
1203 DDI_BUF_TRANS_C_S9T1 => 16#06_4f08# / Register_Width,
1204 DDI_BUF_TRANS_C_S9T2 => 16#06_4f0c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1205 DDI_AUX_CTL_C => 16#06_4210# / Register_Width,
1206 DDI_AUX_DATA_C_1 => 16#06_4214# / Register_Width,
1207 DDI_AUX_DATA_C_2 => 16#06_4218# / Register_Width,
1208 DDI_AUX_DATA_C_3 => 16#06_421c# / Register_Width,
1209 DDI_AUX_DATA_C_4 => 16#06_4220# / Register_Width,
1210 DDI_AUX_DATA_C_5 => 16#06_4224# / Register_Width,
1211 DDI_AUX_MUTEX_C => 16#06_422c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1212
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1213 DDI_BUF_CTL_D => 16#06_4300# / Register_Width, -- aliased by GMCH_DP_D
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1214 DDI_BUF_TRANS_D_S0T1 => 16#06_4f20# / Register_Width,
1215 DDI_BUF_TRANS_D_S0T2 => 16#06_4f24# / Register_Width,
1216 DDI_BUF_TRANS_D_S1T1 => 16#06_4f28# / Register_Width,
1217 DDI_BUF_TRANS_D_S1T2 => 16#06_4f2c# / Register_Width,
1218 DDI_BUF_TRANS_D_S2T1 => 16#06_4f30# / Register_Width,
1219 DDI_BUF_TRANS_D_S2T2 => 16#06_4f34# / Register_Width,
1220 DDI_BUF_TRANS_D_S3T1 => 16#06_4f38# / Register_Width,
1221 DDI_BUF_TRANS_D_S3T2 => 16#06_4f3c# / Register_Width,
1222 DDI_BUF_TRANS_D_S4T1 => 16#06_4f40# / Register_Width,
1223 DDI_BUF_TRANS_D_S4T2 => 16#06_4f44# / Register_Width,
1224 DDI_BUF_TRANS_D_S5T1 => 16#06_4f48# / Register_Width,
1225 DDI_BUF_TRANS_D_S5T2 => 16#06_4f4c# / Register_Width,
1226 DDI_BUF_TRANS_D_S6T1 => 16#06_4f50# / Register_Width,
1227 DDI_BUF_TRANS_D_S6T2 => 16#06_4f54# / Register_Width,
1228 DDI_BUF_TRANS_D_S7T1 => 16#06_4f58# / Register_Width,
1229 DDI_BUF_TRANS_D_S7T2 => 16#06_4f5c# / Register_Width,
1230 DDI_BUF_TRANS_D_S8T1 => 16#06_4f60# / Register_Width,
1231 DDI_BUF_TRANS_D_S8T2 => 16#06_4f64# / Register_Width,
1232 DDI_BUF_TRANS_D_S9T1 => 16#06_4f68# / Register_Width,
1233 DDI_BUF_TRANS_D_S9T2 => 16#06_4f6c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1234 DDI_AUX_CTL_D => 16#06_4310# / Register_Width,
1235 DDI_AUX_DATA_D_1 => 16#06_4314# / Register_Width,
1236 DDI_AUX_DATA_D_2 => 16#06_4318# / Register_Width,
1237 DDI_AUX_DATA_D_3 => 16#06_431c# / Register_Width,
1238 DDI_AUX_DATA_D_4 => 16#06_4320# / Register_Width,
1239 DDI_AUX_DATA_D_5 => 16#06_4324# / Register_Width,
1240 DDI_AUX_MUTEX_D => 16#06_432c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1241
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1242 DDI_BUF_CTL_E => 16#06_4400# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1243 DDI_BUF_TRANS_E_S0T1 => 16#06_4f80# / Register_Width,
1244 DDI_BUF_TRANS_E_S0T2 => 16#06_4f84# / Register_Width,
1245 DDI_BUF_TRANS_E_S1T1 => 16#06_4f88# / Register_Width,
1246 DDI_BUF_TRANS_E_S1T2 => 16#06_4f8c# / Register_Width,
1247 DDI_BUF_TRANS_E_S2T1 => 16#06_4f90# / Register_Width,
1248 DDI_BUF_TRANS_E_S2T2 => 16#06_4f94# / Register_Width,
1249 DDI_BUF_TRANS_E_S3T1 => 16#06_4f98# / Register_Width,
1250 DDI_BUF_TRANS_E_S3T2 => 16#06_4f9c# / Register_Width,
1251 DDI_BUF_TRANS_E_S4T1 => 16#06_4fa0# / Register_Width,
1252 DDI_BUF_TRANS_E_S4T2 => 16#06_4fa4# / Register_Width,
1253 DDI_BUF_TRANS_E_S5T1 => 16#06_4fa8# / Register_Width,
1254 DDI_BUF_TRANS_E_S5T2 => 16#06_4fac# / Register_Width,
1255 DDI_BUF_TRANS_E_S6T1 => 16#06_4fb0# / Register_Width,
1256 DDI_BUF_TRANS_E_S6T2 => 16#06_4fb4# / Register_Width,
1257 DDI_BUF_TRANS_E_S7T1 => 16#06_4fb8# / Register_Width,
1258 DDI_BUF_TRANS_E_S7T2 => 16#06_4fbc# / Register_Width,
1259 DDI_BUF_TRANS_E_S8T1 => 16#06_4fc0# / Register_Width,
1260 DDI_BUF_TRANS_E_S8T2 => 16#06_4fc4# / Register_Width,
1261 DDI_BUF_TRANS_E_S9T1 => 16#06_4fc8# / Register_Width,
1262 DDI_BUF_TRANS_E_S9T2 => 16#06_4fcc# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1263 DP_TP_CTL_A => 16#06_4040# / Register_Width,
1264 DP_TP_CTL_B => 16#06_4140# / Register_Width,
1265 DP_TP_CTL_C => 16#06_4240# / Register_Width,
1266 DP_TP_CTL_D => 16#06_4340# / Register_Width,
1267 DP_TP_CTL_E => 16#06_4440# / Register_Width,
1268 DP_TP_STATUS_B => 16#06_4144# / Register_Width,
1269 DP_TP_STATUS_C => 16#06_4244# / Register_Width,
1270 DP_TP_STATUS_D => 16#06_4344# / Register_Width,
1271 DP_TP_STATUS_E => 16#06_4444# / Register_Width,
1272 PORT_CLK_SEL_DDIA => 16#04_6100# / Register_Width,
1273 PORT_CLK_SEL_DDIB => 16#04_6104# / Register_Width,
1274 PORT_CLK_SEL_DDIC => 16#04_6108# / Register_Width,
1275 PORT_CLK_SEL_DDID => 16#04_610c# / Register_Width,
1276 PORT_CLK_SEL_DDIE => 16#04_6110# / Register_Width,
1277
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]1278 -- Haswell LCPLL registers
1279 LCPLL_CTL => 16#13_0040# / Register_Width,
1280
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]1281 -- Skylake I_boost configuration
1282 DISPIO_CR_TX_BMU_CR0 => 16#06_c00c# / Register_Width,
1283
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1284 -- Skylake DPLL registers
1285 DPLL1_CFGR1 => 16#06_c040# / Register_Width,
1286 DPLL1_CFGR2 => 16#06_c044# / Register_Width,
1287 DPLL2_CFGR1 => 16#06_c048# / Register_Width,
1288 DPLL2_CFGR2 => 16#06_c04c# / Register_Width,
1289 DPLL3_CFGR1 => 16#06_c050# / Register_Width,
1290 DPLL3_CFGR2 => 16#06_c054# / Register_Width,
1291 DPLL_CTRL1 => 16#06_c058# / Register_Width,
1292 DPLL_CTRL2 => 16#06_c05c# / Register_Width,
1293 DPLL_STATUS => 16#06_c060# / Register_Width,
1294
1295 -- CD CLK register
1296 CDCLK_CTL => 16#04_6000# / Register_Width,
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]1297 CDCLK_FREQ => 16#04_6200# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1298
1299 -- Skylake LCPLL registers
1300 LCPLL1_CTL => 16#04_6010# / Register_Width,
1301 LCPLL2_CTL => 16#04_6014# / Register_Width,
1302
1303 -- SPLL register
1304 SPLL_CTL => 16#04_6020# / Register_Width,
1305
1306 -- WRPLL registers
1307 WRPLL_CTL_1 => 16#04_6040# / Register_Width,
1308 WRPLL_CTL_2 => 16#04_6060# / Register_Width,
1309
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]1310 -- Broxton Display Engine PLL registers
1311 BXT_DE_PLL_CTL => 16#06_d000# / Register_Width,
1312 BXT_DE_PLL_ENABLE => 16#04_6070# / Register_Width,
1313
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1314 -- Broxton DDI PHY PLL registers
1315 BXT_PORT_PLL_ENABLE_A => 16#04_6074# / Register_Width,
1316 BXT_PORT_PLL_ENABLE_B => 16#04_6078# / Register_Width,
1317 BXT_PORT_PLL_ENABLE_C => 16#04_607c# / Register_Width,
1318 BXT_PORT_PLL_EBB_0_A => 16#16_2034# / Register_Width,
1319 BXT_PORT_PLL_EBB_4_A => 16#16_2038# / Register_Width,
1320 BXT_PORT_PLL_0_A => 16#16_2100# / Register_Width,
1321 BXT_PORT_PLL_1_A => 16#16_2104# / Register_Width,
1322 BXT_PORT_PLL_2_A => 16#16_2108# / Register_Width,
1323 BXT_PORT_PLL_3_A => 16#16_210c# / Register_Width,
1324 BXT_PORT_PLL_6_A => 16#16_2118# / Register_Width,
1325 BXT_PORT_PLL_8_A => 16#16_2120# / Register_Width,
1326 BXT_PORT_PLL_9_A => 16#16_2124# / Register_Width,
1327 BXT_PORT_PLL_10_A => 16#16_2128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1328 BXT_PORT_PLL_EBB_0_B => 16#06_c034# / Register_Width,
1329 BXT_PORT_PLL_EBB_4_B => 16#06_c038# / Register_Width,
1330 BXT_PORT_PLL_0_B => 16#06_c100# / Register_Width,
1331 BXT_PORT_PLL_1_B => 16#06_c104# / Register_Width,
1332 BXT_PORT_PLL_2_B => 16#06_c108# / Register_Width,
1333 BXT_PORT_PLL_3_B => 16#06_c10c# / Register_Width,
1334 BXT_PORT_PLL_6_B => 16#06_c118# / Register_Width,
1335 BXT_PORT_PLL_8_B => 16#06_c120# / Register_Width,
1336 BXT_PORT_PLL_9_B => 16#06_c124# / Register_Width,
1337 BXT_PORT_PLL_10_B => 16#06_c128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1338 BXT_PORT_PLL_EBB_0_C => 16#06_c340# / Register_Width,
1339 BXT_PORT_PLL_EBB_4_C => 16#06_c344# / Register_Width,
1340 BXT_PORT_PLL_0_C => 16#06_c380# / Register_Width,
1341 BXT_PORT_PLL_1_C => 16#06_c384# / Register_Width,
1342 BXT_PORT_PLL_2_C => 16#06_c388# / Register_Width,
1343 BXT_PORT_PLL_3_C => 16#06_c38c# / Register_Width,
1344 BXT_PORT_PLL_6_C => 16#06_c398# / Register_Width,
1345 BXT_PORT_PLL_8_C => 16#06_c3a0# / Register_Width,
1346 BXT_PORT_PLL_9_C => 16#06_c3a4# / Register_Width,
1347 BXT_PORT_PLL_10_C => 16#06_c3a8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1348
1349 -- Broxton DDI PHY PCS? registers
1350 BXT_PORT_PCS_DW10_01_A => 16#16_2428# / Register_Width,
1351 BXT_PORT_PCS_DW12_01_A => 16#16_2430# / Register_Width,
1352 BXT_PORT_PCS_DW10_GRP_A => 16#16_2c28# / Register_Width,
1353 BXT_PORT_PCS_DW12_GRP_A => 16#16_2c30# / Register_Width,
1354 BXT_PORT_PCS_DW10_01_B => 16#06_c428# / Register_Width,
1355 BXT_PORT_PCS_DW12_01_B => 16#06_c430# / Register_Width,
1356 BXT_PORT_PCS_DW10_01_C => 16#06_c828# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1357 BXT_PORT_PCS_DW12_01_C => 16#06_c830# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1358 BXT_PORT_PCS_DW10_GRP_B => 16#06_cc28# / Register_Width,
1359 BXT_PORT_PCS_DW12_GRP_B => 16#06_cc30# / Register_Width,
1360 BXT_PORT_PCS_DW10_GRP_C => 16#06_ce28# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1361 BXT_PORT_PCS_DW12_GRP_C => 16#06_ce30# / Register_Width,
1362
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1363 -- Broxton DDI PHY registers
1364 BXT_P_CR_GT_DISP_PWRON => 16#13_8090# / Register_Width,
1365 BXT_PHY_CTL_A => 16#06_4c00# / Register_Width,
1366 BXT_PHY_CTL_B => 16#06_4c10# / Register_Width,
1367 BXT_PHY_CTL_C => 16#06_4c20# / Register_Width,
1368 BXT_PHY_CTL_FAM_EDP => 16#06_4c80# / Register_Width,
1369 BXT_PHY_CTL_FAM_DDI => 16#06_4c90# / Register_Width,
1370
1371 -- Broxton DDI PHY common lane registers
1372 BXT_PORT_CL1CM_DW0_A => 16#16_2000# / Register_Width,
1373 BXT_PORT_CL1CM_DW0_BC => 16#06_c000# / Register_Width,
1374 BXT_PORT_CL1CM_DW9_A => 16#16_2024# / Register_Width,
1375 BXT_PORT_CL1CM_DW9_BC => 16#06_c024# / Register_Width,
1376 BXT_PORT_CL1CM_DW10_A => 16#16_2028# / Register_Width,
1377 BXT_PORT_CL1CM_DW10_BC => 16#06_c028# / Register_Width,
1378 BXT_PORT_CL1CM_DW28_A => 16#16_2070# / Register_Width,
1379 BXT_PORT_CL1CM_DW28_BC => 16#06_c070# / Register_Width,
1380 BXT_PORT_CL1CM_DW30_A => 16#16_2078# / Register_Width,
1381 BXT_PORT_CL1CM_DW30_BC => 16#06_c078# / Register_Width,
1382 BXT_PORT_CL2CM_DW6_BC => 16#06_c358# / Register_Width,
1383
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1384 -- Broxton DDI PHY TX lane registers
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1385 BXT_PORT_TX_DW2_LN0_A => 16#16_2508# / Register_Width,
1386 BXT_PORT_TX_DW3_LN0_A => 16#16_250c# / Register_Width,
1387 BXT_PORT_TX_DW4_LN0_A => 16#16_2510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1388 BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width,
1389 BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width,
1390 BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width,
1391 BXT_PORT_TX_DW14_LN3_A => 16#16_27b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1392 BXT_PORT_TX_DW2_GRP_A => 16#16_2d08# / Register_Width,
1393 BXT_PORT_TX_DW3_GRP_A => 16#16_2d0c# / Register_Width,
1394 BXT_PORT_TX_DW4_GRP_A => 16#16_2d10# / Register_Width,
1395 BXT_PORT_TX_DW2_LN0_B => 16#06_c508# / Register_Width,
1396 BXT_PORT_TX_DW3_LN0_B => 16#06_c50c# / Register_Width,
1397 BXT_PORT_TX_DW4_LN0_B => 16#06_c510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1398 BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width,
1399 BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width,
1400 BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width,
1401 BXT_PORT_TX_DW14_LN3_B => 16#06_c7b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1402 BXT_PORT_TX_DW2_GRP_B => 16#06_cd08# / Register_Width,
1403 BXT_PORT_TX_DW3_GRP_B => 16#06_cd0c# / Register_Width,
1404 BXT_PORT_TX_DW4_GRP_B => 16#06_cd10# / Register_Width,
1405 BXT_PORT_TX_DW2_LN0_C => 16#06_c908# / Register_Width,
1406 BXT_PORT_TX_DW3_LN0_C => 16#06_c90c# / Register_Width,
1407 BXT_PORT_TX_DW4_LN0_C => 16#06_c910# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1408 BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width,
1409 BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width,
1410 BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width,
1411 BXT_PORT_TX_DW14_LN3_C => 16#06_cbb8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1412 BXT_PORT_TX_DW2_GRP_C => 16#06_cf08# / Register_Width,
1413 BXT_PORT_TX_DW3_GRP_C => 16#06_cf0c# / Register_Width,
1414 BXT_PORT_TX_DW4_GRP_C => 16#06_cf10# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1415
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1416 -- Broxton DDI PHY ref registers
1417 BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width,
1418 BXT_PORT_REF_DW3_BC => 16#06_c18c# / Register_Width,
1419 BXT_PORT_REF_DW6_A => 16#16_2198# / Register_Width,
1420 BXT_PORT_REF_DW6_BC => 16#06_c198# / Register_Width,
1421 BXT_PORT_REF_DW8_A => 16#16_21a0# / Register_Width,
1422 BXT_PORT_REF_DW8_BC => 16#06_c1a0# / Register_Width,
1423
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1424 -- Power Down Well registers
1425 PWR_WELL_CTL_BIOS => 16#04_5400# / Register_Width,
1426 PWR_WELL_CTL_DRIVER => 16#04_5404# / Register_Width,
1427 PWR_WELL_CTL_KVMR => 16#04_5408# / Register_Width,
1428 PWR_WELL_CTL_DEBUG => 16#04_540c# / Register_Width,
1429 PWR_WELL_CTL5 => 16#04_5410# / Register_Width,
1430 PWR_WELL_CTL6 => 16#04_5414# / Register_Width,
1431
1432 -- class Panel registers
Arthur Heymanse87d0d12018-03-28 17:02:49 +0200[diff] [blame]1433 GMCH_PP_STATUS => 16#06_1200# / Register_Width,
1434 GMCH_PP_CONTROL => 16#06_1204# / Register_Width,
1435 GMCH_PP_ON_DELAYS => 16#06_1208# / Register_Width,
1436 GMCH_PP_OFF_DELAYS => 16#06_120c# / Register_Width,
1437 GMCH_PP_DIVISOR => 16#06_1210# / Register_Width,
Arthur Heymansd5198442018-03-28 17:05:12 +0200[diff] [blame]1438 GMCH_PFIT_CONTROL => 16#06_1230# / Register_Width,
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]1439 PCH_PP_STATUS => 16#0c_7200# / Register_Width, -- aliased with BXT_PP_STATUS_1
1440 PCH_PP_CONTROL => 16#0c_7204# / Register_Width, -- aliased with BXT_PP_CONTROL_1
1441 PCH_PP_ON_DELAYS => 16#0c_7208# / Register_Width, -- aliased with BXT_PP_ON_DELAYS_1
1442 PCH_PP_OFF_DELAYS => 16#0c_720c# / Register_Width, -- aliased with BXT_PP_OFF_DELAYS_1
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1443 PCH_PP_DIVISOR => 16#0c_7210# / Register_Width,
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]1444 BXT_PP_STATUS_2 => 16#0c_7300# / Register_Width,
1445 BXT_PP_CONTROL_2 => 16#0c_7304# / Register_Width,
1446 BXT_PP_ON_DELAYS_2 => 16#0c_7308# / Register_Width,
1447 BXT_PP_OFF_DELAYS_2 => 16#0c_730c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1448 BLC_PWM_CPU_CTL => 16#04_8254# / Register_Width,
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]1449 BLC_PWM_CPU_CTL2 => 16#04_8250# / Register_Width,
1450 BLC_PWM_PCH_CTL1 => 16#0c_8250# / Register_Width, -- aliased with BXT_BLC_PWM_CTL_1
1451 BLC_PWM_PCH_CTL2 => 16#0c_8254# / Register_Width, -- aliased with BXT_BLC_PWM_FREQ_1
1452 BXT_BLC_PWM_DUTY_1 => 16#0c_8258# / Register_Width,
1453 BXT_BLC_PWM_CTL_2 => 16#0c_8350# / Register_Width,
1454 BXT_BLC_PWM_FREQ_2 => 16#0c_8354# / Register_Width,
1455 BXT_BLC_PWM_DUTY_2 => 16#0c_8358# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1456
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1457 -- GMCH LVDS Connector Registers
1458 GMCH_LVDS => 16#06_1180# / Register_Width,
1459
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1460 -- PCH LVDS Connector Registers
1461 PCH_LVDS => 16#0e_1180# / Register_Width,
1462
1463 -- PCH ADPA Connector Registers
1464 PCH_ADPA => 16#0e_1100# / Register_Width,
1465
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1466 -- GMCH DVOB Connector Registers
1467 GMCH_SDVOB => 16#06_1140# / Register_Width,
1468
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1469 -- PCH HDMIB Connector Registers
1470 PCH_HDMIB => 16#0e_1140# / Register_Width,
1471
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1472 -- GMCH DVOC Connector Registers
1473 GMCH_SDVOC => 16#06_1160# / Register_Width,
1474
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1475 -- PCH HDMIC Connector Registers
1476 PCH_HDMIC => 16#0e_1150# / Register_Width,
1477
1478 -- PCH HDMID Connector Registers
1479 PCH_HDMID => 16#0e_1160# / Register_Width,
1480
1481 -- Intel Registers
Nico Huber6b4678d2019-09-22 21:31:52 +0200[diff] [blame]1482 DFSM => 16#05_1000# / Register_Width,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]1483 CPU_VGACNTRL => 16#04_1000# / Register_Width,
1484 GMCH_VGACNTRL => 16#07_1400# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1485 FUSE_STATUS => 16#04_2000# / Register_Width,
Nico Huberd0f84b92019-09-22 21:31:52 +0200[diff] [blame]1486 FUSE_STRAP => 16#04_2014# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1487 FBA_CFB_BASE => 16#04_3200# / Register_Width,
1488 IPS_CTL => 16#04_3408# / Register_Width,
1489 ARB_CTL => 16#04_5000# / Register_Width,
1490 DBUF_CTL => 16#04_5008# / Register_Width,
1491 NDE_RSTWRN_OPT => 16#04_6408# / Register_Width,
1492 PCH_DREF_CONTROL => 16#0c_6200# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1493 PCH_DPLL_SEL => 16#0c_7000# / Register_Width,
1494 GT_MAILBOX => 16#13_8124# / Register_Width,
1495 GT_MAILBOX_DATA => 16#13_8128# / Register_Width,
1496 GT_MAILBOX_DATA_1 => 16#13_812c# / Register_Width,
1497
1498 PCH_DP_B => 16#0e_4100# / Register_Width,
1499 PCH_DP_AUX_CTL_B => 16#0e_4110# / Register_Width,
1500 PCH_DP_AUX_DATA_B_1 => 16#0e_4114# / Register_Width,
1501 PCH_DP_AUX_DATA_B_2 => 16#0e_4118# / Register_Width,
1502 PCH_DP_AUX_DATA_B_3 => 16#0e_411c# / Register_Width,
1503 PCH_DP_AUX_DATA_B_4 => 16#0e_4120# / Register_Width,
1504 PCH_DP_AUX_DATA_B_5 => 16#0e_4124# / Register_Width,
1505 PCH_DP_C => 16#0e_4200# / Register_Width,
1506 PCH_DP_AUX_CTL_C => 16#0e_4210# / Register_Width,
1507 PCH_DP_AUX_DATA_C_1 => 16#0e_4214# / Register_Width,
1508 PCH_DP_AUX_DATA_C_2 => 16#0e_4218# / Register_Width,
1509 PCH_DP_AUX_DATA_C_3 => 16#0e_421c# / Register_Width,
1510 PCH_DP_AUX_DATA_C_4 => 16#0e_4220# / Register_Width,
1511 PCH_DP_AUX_DATA_C_5 => 16#0e_4224# / Register_Width,
1512 PCH_DP_D => 16#0e_4300# / Register_Width,
1513 PCH_DP_AUX_CTL_D => 16#0e_4310# / Register_Width,
1514 PCH_DP_AUX_DATA_D_1 => 16#0e_4314# / Register_Width,
1515 PCH_DP_AUX_DATA_D_2 => 16#0e_4318# / Register_Width,
1516 PCH_DP_AUX_DATA_D_3 => 16#0e_431c# / Register_Width,
1517 PCH_DP_AUX_DATA_D_4 => 16#0e_4320# / Register_Width,
1518 PCH_DP_AUX_DATA_D_5 => 16#0e_4324# / Register_Width,
1519
1520 -- watermark registers
1521 WM1_LP_ILK => 16#04_5108# / Register_Width,
1522 WM2_LP_ILK => 16#04_510c# / Register_Width,
1523 WM3_LP_ILK => 16#04_5110# / Register_Width,
1524
1525 -- audio VID/DID
1526 AUD_VID_DID => 16#06_5020# / Register_Width,
1527 PCH_AUD_VID_DID => 16#0e_5020# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1528 G4X_AUD_VID_DID => 16#06_2020# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1529
1530 -- interrupt registers
1531 DEISR => 16#04_4000# / Register_Width,
1532 DEIMR => 16#04_4004# / Register_Width,
1533 DEIIR => 16#04_4008# / Register_Width,
1534 DEIER => 16#04_400c# / Register_Width,
1535 GTISR => 16#04_4010# / Register_Width,
1536 GTIMR => 16#04_4014# / Register_Width,
1537 GTIIR => 16#04_4018# / Register_Width,
1538 GTIER => 16#04_401c# / Register_Width,
1539 SDEISR => 16#0c_4000# / Register_Width,
1540 SDEIMR => 16#0c_4004# / Register_Width,
1541 SDEIIR => 16#0c_4008# / Register_Width,
1542 SDEIER => 16#0c_400c# / Register_Width,
1543
1544 -- I2C stuff
Arthur Heymans229ed1c2018-03-28 16:45:43 +0200[diff] [blame]1545 GMCH_GMBUS0 => 16#00_5100# / Register_Width,
1546 GMCH_GMBUS1 => 16#00_5104# / Register_Width,
1547 GMCH_GMBUS2 => 16#00_5108# / Register_Width,
1548 GMCH_GMBUS3 => 16#00_510c# / Register_Width,
1549 GMCH_GMBUS4 => 16#00_5110# / Register_Width,
1550 GMCH_GMBUS5 => 16#00_5120# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1551 PCH_GMBUS0 => 16#0c_5100# / Register_Width,
1552 PCH_GMBUS1 => 16#0c_5104# / Register_Width,
1553 PCH_GMBUS2 => 16#0c_5108# / Register_Width,
1554 PCH_GMBUS3 => 16#0c_510c# / Register_Width,
1555 PCH_GMBUS4 => 16#0c_5110# / Register_Width,
1556 PCH_GMBUS5 => 16#0c_5120# / Register_Width,
1557
1558 -- clock gating -- maybe have to touch this
1559 DSPCLK_GATE_D => 16#04_2020# / Register_Width,
1560 PCH_FDI_CHICKEN_B_C => 16#0c_2000# / Register_Width,
1561 PCH_DSPCLK_GATE_D => 16#0c_2020# / Register_Width,
1562
1563 -- hotplug and initial detection
1564 HOTPLUG_CTL => 16#04_4030# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1565 PORT_HOTPLUG_EN => 16#06_1110# / Register_Width,
1566 PORT_HOTPLUG_STAT => 16#06_1114# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1567 SHOTPLUG_CTL => 16#0c_4030# / Register_Width,
1568 SFUSE_STRAP => 16#0c_2014# / Register_Width,
1569
1570 -- Render Engine Command Streamer
1571 ARB_MODE => 16#00_4030# / Register_Width,
1572 HWS_PGA => 16#00_4080# / Register_Width,
1573 RCS_RING_BUFFER_TAIL => 16#00_2030# / Register_Width,
1574 VCS_RING_BUFFER_TAIL => 16#01_2030# / Register_Width,
1575 BCS_RING_BUFFER_TAIL => 16#02_2030# / Register_Width,
1576 RCS_RING_BUFFER_HEAD => 16#00_2034# / Register_Width,
1577 VCS_RING_BUFFER_HEAD => 16#01_2034# / Register_Width,
1578 BCS_RING_BUFFER_HEAD => 16#02_2034# / Register_Width,
1579 RCS_RING_BUFFER_STRT => 16#00_2038# / Register_Width,
1580 VCS_RING_BUFFER_STRT => 16#01_2038# / Register_Width,
1581 BCS_RING_BUFFER_STRT => 16#02_2038# / Register_Width,
1582 RCS_RING_BUFFER_CTL => 16#00_203c# / Register_Width,
1583 VCS_RING_BUFFER_CTL => 16#01_203c# / Register_Width,
1584 BCS_RING_BUFFER_CTL => 16#02_203c# / Register_Width,
1585 MI_MODE => 16#00_209c# / Register_Width,
1586 INSTPM => 16#00_20c0# / Register_Width,
1587 GAB_CTL_REG => 16#02_4000# / Register_Width,
1588 PP_DCLV_HIGH => 16#00_2220# / Register_Width,
1589 PP_DCLV_LOW => 16#00_2228# / Register_Width,
1590 VCS_PP_DCLV_HIGH => 16#01_2220# / Register_Width,
1591 VCS_PP_DCLV_LOW => 16#01_2228# / Register_Width,
1592 BCS_PP_DCLV_HIGH => 16#02_2220# / Register_Width,
1593 BCS_PP_DCLV_LOW => 16#02_2228# / Register_Width,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1594 ILK_DISPLAY_CHICKEN2 => 16#04_2004# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1595 UCGCTL1 => 16#00_9400# / Register_Width,
1596 UCGCTL2 => 16#00_9404# / Register_Width,
1597 MBCTL => 16#00_907c# / Register_Width,
1598 HWSTAM => 16#00_2098# / Register_Width,
1599 VCS_HWSTAM => 16#01_2098# / Register_Width,
1600 BCS_HWSTAM => 16#02_2098# / Register_Width,
1601 IIR => 16#04_4028# / Register_Width,
1602 PIPE_FRMCNT_A => 16#07_0040# / Register_Width,
1603 PIPE_FRMCNT_B => 16#07_1040# / Register_Width,
1604 PIPE_FRMCNT_C => 16#07_2040# / Register_Width,
1605 FBC_CTL => 16#04_3208# / Register_Width,
1606 PIPE_VSYNCSHIFT_A => 16#06_0028# / Register_Width,
1607 PIPE_VSYNCSHIFT_B => 16#06_1028# / Register_Width,
1608 PIPE_VSYNCSHIFT_C => 16#06_2028# / Register_Width,
1609 WM_PIPE_A => 16#04_5100# / Register_Width,
1610 WM_PIPE_B => 16#04_5104# / Register_Width,
1611 WM_PIPE_C => 16#04_5200# / Register_Width,
1612 PIPE_SCANLINE_A => 16#07_0000# / Register_Width,
1613 PIPE_SCANLINE_B => 16#07_1000# / Register_Width,
1614 PIPE_SCANLINE_C => 16#07_2000# / Register_Width,
1615 GFX_MODE => 16#00_2520# / Register_Width,
1616 CACHE_MODE_0 => 16#00_2120# / Register_Width,
1617 SLEEP_PSMI_CONTROL => 16#01_2050# / Register_Width,
1618 CTX_SIZE => 16#00_21a0# / Register_Width,
1619 GAC_ECO_BITS => 16#01_4090# / Register_Width,
1620 GAM_ECOCHK => 16#00_4090# / Register_Width,
1621 QUIRK_02084 => 16#00_2084# / Register_Width,
1622 QUIRK_02090 => 16#00_2090# / Register_Width,
1623 GT_MODE => 16#00_20d0# / Register_Width,
1624 QUIRK_F0060 => 16#0f_0060# / Register_Width,
1625 QUIRK_F1060 => 16#0f_1060# / Register_Width,
1626 QUIRK_F2060 => 16#0f_2060# / Register_Width,
1627 AUD_CNTRL_ST2 => 16#0e_50c0# / Register_Width,
1628 AUD_CNTL_ST_A => 16#0e_50b4# / Register_Width,
1629 AUD_CNTL_ST_B => 16#0e_51b4# / Register_Width,
1630 AUD_CNTL_ST_C => 16#0e_52b4# / Register_Width,
1631 AUD_HDMIW_HDMIEDID_A => 16#0e_5050# / Register_Width,
1632 AUD_HDMIW_HDMIEDID_B => 16#0e_5150# / Register_Width,
1633 AUD_HDMIW_HDMIEDID_C => 16#0e_5250# / Register_Width,
1634 AUD_CONFIG_A => 16#0e_5000# / Register_Width,
1635 AUD_CONFIG_B => 16#0e_5100# / Register_Width,
1636 AUD_CONFIG_C => 16#0e_5200# / Register_Width,
1637 TRANS_DP_CTL_A => 16#0e_0300# / Register_Width,
1638 TRANS_DP_CTL_B => 16#0e_1300# / Register_Width,
1639 TRANS_DP_CTL_C => 16#0e_2300# / Register_Width,
1640 TRANS_VSYNCSHIFT_A => 16#0e_0028# / Register_Width,
1641 TRANS_VSYNCSHIFT_B => 16#0e_1028# / Register_Width,
1642 TRANS_VSYNCSHIFT_C => 16#0e_2028# / Register_Width,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]1643 PCH_RAWCLK_FREQ => 16#0c_6204# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1644 QUIRK_C2004 => 16#0c_2004# / Register_Width,
1645
1646 -- MCHBAR Mirror
1647
Nico Huberb47a5c42019-09-29 00:07:21 +0200[diff] [blame]1648 GMCH_CLKCFG => 16#01_0c00# / Register_Width,
1649 GMCH_HPLLVCO_MOBILE => 16#01_0c0f# / Register_Width,
1650 GMCH_HPLLVCO => 16#01_0c38# / Register_Width);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1651
1652 subtype Registers_Index is Registers_Invalid_Index range
1653 Registers_Invalid_Index'Succ (Invalid_Register) ..
1654 Registers_Invalid_Index'Last;
1655
1656 -- aliased registers
1657 DP_CTL_A : constant Registers_Index := DDI_BUF_CTL_A;
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1658 GMCH_DP_B : constant Registers_Index := DDI_BUF_CTL_B;
1659 GMCH_DP_C : constant Registers_Index := DDI_BUF_CTL_C;
1660 GMCH_DP_D : constant Registers_Index := DDI_BUF_CTL_D;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1661 DP_AUX_CTL_A : constant Registers_Index := DDI_AUX_CTL_A;
1662 DP_AUX_DATA_A_1 : constant Registers_Index := DDI_AUX_DATA_A_1;
1663 DP_AUX_DATA_A_2 : constant Registers_Index := DDI_AUX_DATA_A_2;
1664 DP_AUX_DATA_A_3 : constant Registers_Index := DDI_AUX_DATA_A_3;
1665 DP_AUX_DATA_A_4 : constant Registers_Index := DDI_AUX_DATA_A_4;
1666 DP_AUX_DATA_A_5 : constant Registers_Index := DDI_AUX_DATA_A_5;
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1667 ILK_DISPLAY_CHICKEN1 : constant Registers_Index := FUSE_STATUS;
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1668 GMCH_ADPA : constant Registers_Index := FDI_TX_CTL_B;
1669 GMCH_HDMIB : constant Registers_Index := GMCH_SDVOB;
1670 GMCH_HDMIC : constant Registers_Index := GMCH_SDVOC;
Nico Huber75a707f2018-06-18 16:28:33 +0200[diff] [blame]1671 CURACNTR : constant Registers_Index := CUR_CTL_A;
1672 CURABASE : constant Registers_Index := CUR_BASE_A;
1673 CURAPOS : constant Registers_Index := CUR_POS_A;
Nico Huber7050d2d2020-01-08 13:25:41 +0100[diff] [blame]1674 BXT_BLC_PWM_CTL_1 : constant Registers_Index := BLC_PWM_PCH_CTL1;
1675 BXT_BLC_PWM_FREQ_1 : constant Registers_Index := BLC_PWM_PCH_CTL2;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1676
1677 ---------------------------------------------------------------------------
1678
1679 Default_Timeout_MS : constant := 10;
1680
1681 ---------------------------------------------------------------------------
1682
1683 procedure Posting_Read
1684 (Register : in Registers_Index)
1685 with
1686 Global => (In_Out => Register_State),
1687 Depends => (Register_State =>+ (Register)),
1688 Pre => True,
1689 Post => True;
1690
1691 pragma Warnings (GNATprove, Off, "unused variable ""Verbose""",
1692 Reason => "Only used on debugging path");
1693 procedure Read
1694 (Register : in Registers_Index;
1695 Value : out Word32;
1696 Verbose : in Boolean := True)
1697 with
1698 Global => (In_Out => Register_State),
1699 Depends => ((Value, Register_State) => (Register, Register_State),
1700 null => Verbose),
1701 Pre => True,
1702 Post => True;
1703 pragma Warnings (GNATprove, On, "unused variable ""Verbose""");
1704
1705 procedure Write
1706 (Register : Registers_Index;
1707 Value : Word32)
1708 with
1709 Global => (In_Out => Register_State),
1710 Depends => (Register_State => (Register, Register_State, Value)),
1711 Pre => True,
1712 Post => True;
1713
1714 procedure Is_Set_Mask
1715 (Register : in Registers_Index;
1716 Mask : in Word32;
1717 Result : out Boolean);
1718
1719 pragma Warnings (GNATprove, Off, "unused initial value of ""Verbose""",
1720 Reason => "Only used on debugging path");
Nico Huberbcb2c472017-02-02 16:39:26 +0100[diff] [blame]1721 procedure Wait
Nico Huber82ca09f2019-09-28 02:37:50 +0200[diff] [blame]1722 (Register : in Registers_Index;
1723 Mask : in Word32;
1724 Value : in Word32;
1725 TOut_MS : in Natural := Default_Timeout_MS;
1726 Verbose : in Boolean := False;
1727 Success : out Boolean);
1728 procedure Wait
Nico Huberbcb2c472017-02-02 16:39:26 +0100[diff] [blame]1729 (Register : Registers_Index;
1730 Mask : Word32;
1731 Value : Word32;
1732 TOut_MS : Natural := Default_Timeout_MS;
1733 Verbose : Boolean := False);
1734
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1735 procedure Wait_Set_Mask
Nico Huber82ca09f2019-09-28 02:37:50 +0200[diff] [blame]1736 (Register : in Registers_Index;
1737 Mask : in Word32;
1738 TOut_MS : in Natural := Default_Timeout_MS;
1739 Verbose : in Boolean := False;
1740 Success : out Boolean);
1741 procedure Wait_Set_Mask
1742 (Register : Registers_Index;
1743 Mask : Word32;
1744 TOut_MS : Natural := Default_Timeout_MS;
1745 Verbose : Boolean := False);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1746
1747 procedure Wait_Unset_Mask
Nico Huber82ca09f2019-09-28 02:37:50 +0200[diff] [blame]1748 (Register : in Registers_Index;
1749 Mask : in Word32;
1750 TOut_MS : in Natural := Default_Timeout_MS;
1751 Verbose : in Boolean := False;
1752 Success : out Boolean);
1753 procedure Wait_Unset_Mask
1754 (Register : Registers_Index;
1755 Mask : Word32;
1756 TOut_MS : Natural := Default_Timeout_MS;
1757 Verbose : Boolean := False);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1758 pragma Warnings (GNATprove, On, "unused initial value of ""Verbose""");
1759
1760 procedure Set_Mask
1761 (Register : Registers_Index;
1762 Mask : Word32);
1763
1764 procedure Unset_Mask
1765 (Register : Registers_Index;
1766 Mask : Word32);
1767
1768 procedure Unset_And_Set_Mask
1769 (Register : Registers_Index;
1770 Mask_Unset : Word32;
1771 Mask_Set : Word32);
1772
Nico Huber17d64b62017-07-15 20:51:25 +0200[diff] [blame]1773 procedure Clear_Fences;
1774
Nico Huberb03c8f12017-08-25 13:29:08 +0200[diff] [blame]1775 procedure Add_Fence
1776 (First_Page : in GTT_Range;
1777 Last_Page : in GTT_Range;
1778 Tiling : in XY_Tiling;
1779 Pitch : in Natural;
1780 Success : out Boolean);
1781
1782 procedure Remove_Fence (First_Page, Last_Page : GTT_Range);
1783
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]1784 pragma Warnings (GNATprove, Off, "no check message justified by this",
1785 Reason => "see Annotate aspects.");
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1786 procedure Write_GTT
1787 (GTT_Page : GTT_Range;
1788 Device_Address : GTT_Address_Type;
1789 Valid : Boolean)
1790 with
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]1791 Global =>
1792 (Input => Config.Variable,
1793 In_Out => GTT_State),
1794 Depends =>
1795 (GTT_State =>+ (Config.Variable, GTT_Page, Device_Address, Valid)),
1796 Annotate =>
1797 (GNATprove, Intentional,
Nico Hubere317e9c2019-09-29 03:03:18 +0200[diff] [blame]1798 """GMA.State"" of ""Write_GTT"" not read",
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]1799 "Reading of Config_State depends on the platform configuration.");
Nico Huberceda17d2018-06-09 22:00:29 +0200[diff] [blame]1800
1801 procedure Read_GTT
1802 (Device_Address : out GTT_Address_Type;
1803 Valid : out Boolean;
1804 GTT_Page : in GTT_Range)
1805 with
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]1806 Global =>
1807 (Input => Config.Variable,
1808 In_Out => GTT_State),
1809 Depends =>
1810 ((Device_Address, Valid, GTT_State) =>
1811 (Config.Variable, GTT_State, GTT_Page)),
1812 Annotate =>
1813 (GNATprove, Intentional,
Nico Hubere317e9c2019-09-29 03:03:18 +0200[diff] [blame]1814 """GMA.State"" of ""Read_GTT"" not read",
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]1815 "Reading of Config_State depends on the platform configuration.");
1816 pragma Warnings (GNATprove, On, "no check message justified by this");
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1817
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]1818 procedure Set_Register_Base (Base : Word64; GTT_Base : Word64 := 0)
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1819 with
1820 Global => (Output => Address_State),
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]1821 Depends => (Address_State => (Base, GTT_Base)),
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1822 Pre => True,
1823 Post => True;
1824
1825end HW.GFX.GMA.Registers;