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Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +00006 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
Carl-Daniel Hailfinger92242622007-09-27 14:29:57 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000021 */
22
23/*
24 * Contains the board specific flash enables.
25 */
26
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000027#include <string.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000028#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000029#include "programmer.h"
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000030
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000031#if defined(__i386__) || defined(__x86_64__)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000032/*
Uwe Hermannffec5f32007-08-23 16:08:21 +000033 * Helper functions for many Winbond Super I/Os of the W836xx range.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000034 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000035/* Enter extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000036void w836xx_ext_enter(uint16_t port)
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000037{
Andriy Gapon65c1b862008-05-22 13:22:45 +000038 OUTB(0x87, port);
39 OUTB(0x87, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000040}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000041
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000042/* Leave extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000043void w836xx_ext_leave(uint16_t port)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000044{
Andriy Gapon65c1b862008-05-22 13:22:45 +000045 OUTB(0xAA, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000046}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000047
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000048/* Generic Super I/O helper functions */
49uint8_t sio_read(uint16_t port, uint8_t reg)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000050{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000051 OUTB(reg, port);
52 return INB(port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000053}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000054
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000055void sio_write(uint16_t port, uint8_t reg, uint8_t data)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000056{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000057 OUTB(reg, port);
58 OUTB(data, port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000059}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000060
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000061void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000062{
Ronald G. Minnichfa496922007-10-12 21:22:40 +000063 uint8_t tmp;
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000064
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000065 OUTB(reg, port);
66 tmp = INB(port + 1) & ~mask;
67 OUTB(tmp | (data & mask), port + 1);
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000068}
69
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000070/* Not used yet. */
71#if 0
72static int enable_flash_decode_superio(void)
73{
74 int ret;
75 uint8_t tmp;
76
77 switch (superio.vendor) {
78 case SUPERIO_VENDOR_NONE:
79 ret = -1;
80 break;
81 case SUPERIO_VENDOR_ITE:
82 enter_conf_mode_ite(superio.port);
Uwe Hermann43959702010-03-13 17:28:29 +000083 /* Enable flash mapping. Works for most old ITE style Super I/O. */
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000084 tmp = sio_read(superio.port, 0x24);
85 tmp |= 0xfc;
86 sio_write(superio.port, 0x24, tmp);
87 exit_conf_mode_ite(superio.port);
88 ret = 0;
89 break;
90 default:
Sean Nelson316a29f2010-05-07 20:09:04 +000091 msg_pdbg("Unhandled Super I/O type!\n");
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000092 ret = -1;
93 break;
94 }
95 return ret;
96}
97#endif
98
Uwe Hermann48ec1b12010-08-08 17:01:18 +000099/*
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000100 * SMSC FDC37B787: Raise GPIO50
101 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000102static int fdc37b787_gpio50_raise(uint16_t port)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000103{
104 uint8_t id, val;
105
106 OUTB(0x55, port); /* enter conf mode */
107 id = sio_read(port, 0x20);
108 if (id != 0x44) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000109 msg_perr("\nERROR: FDC37B787: Wrong ID 0x%02X.\n", id);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000110 OUTB(0xAA, port); /* leave conf mode */
111 return -1;
112 }
113
114 sio_write(port, 0x07, 0x08); /* Select Aux I/O subdevice */
115
116 val = sio_read(port, 0xC8); /* GP50 */
117 if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */
118 {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000119 msg_perr("\nERROR: GPIO50 mode 0x%02X unexpected.\n", val);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000120 OUTB(0xAA, port);
121 return -1;
122 }
123
124 sio_mask(port, 0xF9, 0x01, 0x01);
125
126 OUTB(0xAA, port); /* Leave conf mode */
127 return 0;
128}
129
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000130/*
131 * Suited for:
132 * - Nokia IP530: Intel 440BX + PIIX4 + FDC37B787
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000133 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000134static int fdc37b787_gpio50_raise_3f0(void)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000135{
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000136 return fdc37b787_gpio50_raise(0x3f0);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000137}
138
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000139struct winbond_mux {
140 uint8_t reg; /* 0 if the corresponding pin is not muxed */
141 uint8_t data; /* reg/data/mask may be directly ... */
142 uint8_t mask; /* ... passed to sio_mask */
143};
144
145struct winbond_port {
146 const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */
147 uint8_t ldn; /* LDN this GPIO register is located in */
148 uint8_t enable_bit; /* bit in 0x30 of that LDN to enable
149 the GPIO port */
150 uint8_t base; /* base register in that LDN for the port */
151};
152
153struct winbond_chip {
154 uint8_t device_id; /* reg 0x20 of the expected w83626x */
155 uint8_t gpio_port_count;
156 const struct winbond_port *port;
157};
158
159
160#define UNIMPLEMENTED_PORT {NULL, 0, 0, 0}
161
162enum winbond_id {
163 WINBOND_W83627HF_ID = 0x52,
Michael Karcherea36c9c2010-06-27 15:07:52 +0000164 WINBOND_W83627EHF_ID = 0x88,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000165 WINBOND_W83627THF_ID = 0x82,
166};
167
168static const struct winbond_mux w83627hf_port2_mux[8] = {
169 {0x2A, 0x01, 0x01}, /* or MIDI */
170 {0x2B, 0x80, 0x80}, /* or SPI */
171 {0x2B, 0x40, 0x40}, /* or SPI */
172 {0x2B, 0x20, 0x20}, /* or power LED */
173 {0x2B, 0x10, 0x10}, /* or watchdog */
174 {0x2B, 0x08, 0x08}, /* or infra red */
175 {0x2B, 0x04, 0x04}, /* or infra red */
176 {0x2B, 0x03, 0x03} /* or IRQ1 input */
177};
178
179static const struct winbond_port w83627hf[3] = {
180 UNIMPLEMENTED_PORT,
181 {w83627hf_port2_mux, 0x08, 0, 0xF0},
182 UNIMPLEMENTED_PORT
183};
184
Michael Karcherea36c9c2010-06-27 15:07:52 +0000185static const struct winbond_mux w83627ehf_port2_mux[8] = {
186 {0x29, 0x06, 0x02}, /* or MIDI */
187 {0x29, 0x06, 0x02},
188 {0x24, 0x02, 0x00}, /* or SPI ROM interface */
189 {0x24, 0x02, 0x00},
190 {0x2A, 0x01, 0x01}, /* or keyboard/mouse interface */
191 {0x2A, 0x01, 0x01},
192 {0x2A, 0x01, 0x01},
193 {0x2A, 0x01, 0x01}
194};
195
196static const struct winbond_port w83627ehf[6] = {
197 UNIMPLEMENTED_PORT,
198 {w83627ehf_port2_mux, 0x09, 0, 0xE3},
199 UNIMPLEMENTED_PORT,
200 UNIMPLEMENTED_PORT,
201 UNIMPLEMENTED_PORT,
202 UNIMPLEMENTED_PORT
203};
204
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000205static const struct winbond_mux w83627thf_port4_mux[8] = {
206 {0x2D, 0x01, 0x01}, /* or watchdog or VID level strap */
207 {0x2D, 0x02, 0x02}, /* or resume reset */
208 {0x2D, 0x04, 0x04}, /* or S3 input */
209 {0x2D, 0x08, 0x08}, /* or PSON# */
210 {0x2D, 0x10, 0x10}, /* or PWROK */
211 {0x2D, 0x20, 0x20}, /* or suspend LED */
212 {0x2D, 0x40, 0x40}, /* or panel switch input */
213 {0x2D, 0x80, 0x80} /* or panel switch output */
214};
215
216static const struct winbond_port w83627thf[5] = {
217 UNIMPLEMENTED_PORT, /* GPIO1 */
218 UNIMPLEMENTED_PORT, /* GPIO2 */
219 UNIMPLEMENTED_PORT, /* GPIO3 */
220 {w83627thf_port4_mux, 0x09, 1, 0xF4},
221 UNIMPLEMENTED_PORT /* GPIO5 */
222};
223
224static const struct winbond_chip winbond_chips[] = {
225 {WINBOND_W83627HF_ID, ARRAY_SIZE(w83627hf), w83627hf },
Michael Karcherea36c9c2010-06-27 15:07:52 +0000226 {WINBOND_W83627EHF_ID, ARRAY_SIZE(w83627ehf), w83627ehf},
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000227 {WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf},
228};
229
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000230/*
231 * Detects which Winbond Super I/O is responding at the given base address,
232 * but takes no effort to make sure the chip is really a Winbond Super I/O.
233 */
234static const struct winbond_chip *winbond_superio_detect(uint16_t base)
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000235{
236 uint8_t chipid;
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000237 const struct winbond_chip *chip = NULL;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000238 int i;
239
240 w836xx_ext_enter(base);
241 chipid = sio_read(base, 0x20);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000242
243 for (i = 0; i < ARRAY_SIZE(winbond_chips); i++) {
244 if (winbond_chips[i].device_id == chipid) {
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000245 chip = &winbond_chips[i];
246 break;
247 }
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000248 }
249
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000250 w836xx_ext_leave(base);
251 return chip;
252}
253
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000254/*
255 * The chipid parameter goes away as soon as we have Super I/O matching in the
256 * board enable table. The call to winbond_superio_detect() goes away as
257 * soon as we have generic Super I/O detection code.
258 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000259static int winbond_gpio_set(uint16_t base, enum winbond_id chipid,
260 int pin, int raise)
261{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000262 const struct winbond_chip *chip = NULL;
263 const struct winbond_port *gpio;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000264 int port = pin / 10;
265 int bit = pin % 10;
266
267 chip = winbond_superio_detect(base);
268 if (!chip) {
269 msg_perr("\nERROR: No supported Winbond Super I/O found\n");
270 return -1;
271 }
Michael Karcher979d9252010-06-29 14:44:40 +0000272 if (chip->device_id != chipid) {
273 msg_perr("\nERROR: Found Winbond chip with ID 0x%x, "
274 "expected %x\n", chip->device_id, chipid);
275 return -1;
276 }
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000277 if (bit >= 8 || port == 0 || port > chip->gpio_port_count) {
278 msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n",
279 pin);
280 return -1;
281 }
282
283 gpio = &chip->port[port - 1];
284
285 if (gpio->ldn == 0) {
286 msg_perr("\nERROR: GPIO%d is not supported yet on this"
287 " winbond chip\n", port);
288 return -1;
289 }
290
291 w836xx_ext_enter(base);
292
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000293 /* Select logical device. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000294 sio_write(base, 0x07, gpio->ldn);
295
296 /* Activate logical device. */
297 sio_mask(base, 0x30, 1 << gpio->enable_bit, 1 << gpio->enable_bit);
298
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000299 /* Select GPIO function of that pin. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000300 if (gpio->mux && gpio->mux[bit].reg)
301 sio_mask(base, gpio->mux[bit].reg,
302 gpio->mux[bit].data, gpio->mux[bit].mask);
303
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000304 sio_mask(base, gpio->base + 0, 0, 1 << bit); /* Make pin output */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000305 sio_mask(base, gpio->base + 2, 0, 1 << bit); /* Clear inversion */
306 sio_mask(base, gpio->base + 1, raise << bit, 1 << bit);
307
308 w836xx_ext_leave(base);
309
310 return 0;
311}
312
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000313/*
Uwe Hermannffec5f32007-08-23 16:08:21 +0000314 * Winbond W83627HF: Raise GPIO24.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000315 *
316 * Suited for:
Uwe Hermannffec5f32007-08-23 16:08:21 +0000317 * - Agami Aruma
318 * - IWILL DK8-HTX
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000319 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000320static int w83627hf_gpio24_raise_2e(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000321{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000322 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000323}
324
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000325/*
Joshua Roysf280a382010-08-07 21:49:11 +0000326 * Winbond W83627HF: Raise GPIO25.
327 *
328 * Suited for:
329 * - MSI MS-6577
330 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000331static int w83627hf_gpio25_raise_2e(void)
Joshua Roysf280a382010-08-07 21:49:11 +0000332{
333 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 25, 1);
334}
335
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000336/*
Michael Karcherea36c9c2010-06-27 15:07:52 +0000337 * Winbond W83627EHF: Raise GPIO24.
338 *
339 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000340 * - ASUS A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51
Michael Karcherea36c9c2010-06-27 15:07:52 +0000341 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000342static int w83627ehf_gpio24_raise_2e(void)
Michael Karcherea36c9c2010-06-27 15:07:52 +0000343{
344 return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 24, 1);
345}
346
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000347/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000348 * Winbond W83627THF: Raise GPIO 44.
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000349 *
350 * Suited for:
Peter Stugecce26822008-07-21 17:48:40 +0000351 * - MSI K8T Neo2-F
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000352 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000353static int w83627thf_gpio44_raise_2e(void)
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000354{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000355 return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000356}
357
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000358/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000359 * Winbond W83627THF: Raise GPIO 44.
360 *
361 * Suited for:
362 * - MSI K8N Neo3
363 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000364static int w83627thf_gpio44_raise_4e(void)
Peter Stugecce26822008-07-21 17:48:40 +0000365{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000366 return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000367}
Uwe Hermann372eeb52007-12-04 21:49:06 +0000368
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000369/*
David Borgb6417a62010-08-02 08:29:34 +0000370 * Enable MEMW# and set ROM size to max.
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000371 * Supported chips: W83L517D, W83697HF/F/HG, W83697SF/UF/UG
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000372 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000373static void w836xx_memw_enable(uint16_t port)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000374{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000375 w836xx_ext_enter(port);
376 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000377 /* Enable MEMW# and set ROM size select to max. (4M). */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000378 sio_mask(port, 0x24, 0x28, 0x28);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000379 }
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000380 w836xx_ext_leave(port);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000381}
382
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000383/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000384 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000385 * - EPoX EP-8K5A2: VIA KT333 + VT8235
386 * - Albatron PM266A Pro: VIA P4M266A + VT8235
387 * - Shuttle AK31 (all versions): VIA KT266 + VT8233
388 * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
389 * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237
Mattias Mattssone295eee2010-08-15 10:21:29 +0000390 * - MSI KM4M-V and KM4AM-V: VIA KM400/KM400A + VT8237
Mattias Mattssone8388242010-09-11 15:25:48 +0000391 * - MSI MS-6561 (745 Ultra): SiS 745 + W83697HF
Sergey A Lichackf3a4bff2010-09-07 18:14:53 +0000392 * - MSI MS-6787 (P4MAM-V/P4MAM-L): VIA P4M266 + VT8235
Uwe Hermann17da61e2010-10-05 21:48:43 +0000393 * - ASRock K7S41: SiS 741 + SiS 963 + W83697HF
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000394 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000395static int w836xx_memw_enable_2e(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000396{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000397 w836xx_memw_enable(0x2E);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000398
Luc Verhaegen73d21192009-12-23 00:54:26 +0000399 return 0;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000400}
401
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000402/*
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000403 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000404 * - Termtek TK-3370 (rev. 2.5b)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000405 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000406static int w836xx_memw_enable_4e(void)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000407{
408 w836xx_memw_enable(0x4E);
409
410 return 0;
411}
412
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000413/*
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000414 * Suited for all boards with ITE IT8705F.
415 * The SIS950 Super I/O probably requires a similar flash write enable.
Luc Verhaegen21f54962010-01-20 14:45:07 +0000416 */
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000417int it8705f_write_enable(uint8_t port)
Luc Verhaegen21f54962010-01-20 14:45:07 +0000418{
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000419 uint8_t tmp;
420 int ret = 0;
421
Luc Verhaegen21f54962010-01-20 14:45:07 +0000422 enter_conf_mode_ite(port);
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000423 tmp = sio_read(port, 0x24);
424 /* Check if at least one flash segment is enabled. */
425 if (tmp & 0xf0) {
426 /* The IT8705F will respond to LPC cycles and translate them. */
427 buses_supported = CHIP_BUSTYPE_PARALLEL;
428 /* Flash ROM I/F Writes Enable */
429 tmp |= 0x04;
430 msg_pdbg("Enabling IT8705F flash ROM interface write.\n");
431 if (tmp & 0x02) {
432 /* The data sheet contradicts itself about max size. */
433 max_rom_decode.parallel = 1024 * 1024;
434 msg_pinfo("IT8705F with very unusual settings. Please "
435 "send the output of \"flashrom -V\" to \n"
Paul Menzelab6328f2010-10-08 11:03:02 +0000436 "flashrom@flashrom.org with "
437 "IT8705: your board name: flashrom -V\n"
438 "as the subject to help us finish "
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000439 "support for your Super I/O. Thanks.\n");
440 ret = 1;
441 } else if (tmp & 0x08) {
442 max_rom_decode.parallel = 512 * 1024;
443 } else {
444 max_rom_decode.parallel = 256 * 1024;
445 }
446 /* Safety checks. The data sheet is unclear here: Segments 1+3
447 * overlap, no segment seems to cover top - 1MB to top - 512kB.
448 * We assume that certain combinations make no sense.
449 */
450 if (((tmp & 0x02) && !(tmp & 0x08)) || /* 1 MB en, 512 kB dis */
451 (!(tmp & 0x10)) || /* 128 kB dis */
452 (!(tmp & 0x40))) { /* 256/512 kB dis */
453 msg_perr("Inconsistent IT8705F decode size!\n");
454 ret = 1;
455 }
456 if (sio_read(port, 0x25) != 0) {
457 msg_perr("IT8705F flash data pins disabled!\n");
458 ret = 1;
459 }
460 if (sio_read(port, 0x26) != 0) {
461 msg_perr("IT8705F flash address pins 0-7 disabled!\n");
462 ret = 1;
463 }
464 if (sio_read(port, 0x27) != 0) {
465 msg_perr("IT8705F flash address pins 8-15 disabled!\n");
466 ret = 1;
467 }
468 if ((sio_read(port, 0x29) & 0x10) != 0) {
469 msg_perr("IT8705F flash write enable pin disabled!\n");
470 ret = 1;
471 }
472 if ((sio_read(port, 0x29) & 0x08) != 0) {
473 msg_perr("IT8705F flash chip select pin disabled!\n");
474 ret = 1;
475 }
476 if ((sio_read(port, 0x29) & 0x04) != 0) {
477 msg_perr("IT8705F flash read strobe pin disabled!\n");
478 ret = 1;
479 }
480 if ((sio_read(port, 0x29) & 0x03) != 0) {
481 msg_perr("IT8705F flash address pins 16-17 disabled!\n");
482 /* Not really an error if you use flash chips smaller
483 * than 256 kByte, but such a configuration is unlikely.
484 */
485 ret = 1;
486 }
487 msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n",
488 max_rom_decode.parallel);
489 if (ret) {
490 msg_pinfo("Not enabling IT8705F flash write.\n");
491 } else {
492 sio_write(port, 0x24, tmp);
493 }
494 } else {
495 msg_pdbg("No IT8705F flash segment enabled.\n");
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000496 ret = 0;
497 }
Luc Verhaegen21f54962010-01-20 14:45:07 +0000498 exit_conf_mode_ite(port);
499
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000500 return ret;
Luc Verhaegen21f54962010-01-20 14:45:07 +0000501}
Luc Verhaegen73d21192009-12-23 00:54:26 +0000502
Mattias Mattssonfb60cec2010-09-13 19:39:25 +0000503/*
504 * The ITE IT8707F is a custom chip made by ITE exclusively for ASUS.
505 * It uses the Winbond command sequence to enter extended configuration
506 * mode and the ITE sequence to exit.
507 *
508 * Registers seems similar to the ones on ITE IT8710F.
509 */
510static int it8707f_write_enable(uint8_t port)
511{
512 uint8_t tmp;
513
514 w836xx_ext_enter(port);
515
516 /* Set bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A rw */
517 tmp = sio_read(port, 0x23);
518 tmp |= (1 << 3);
519 sio_write(port, 0x23, tmp);
520
521 /* Set bit 2 (FLASH_WE) and bit 3 (FLASH_IF_EN) of reg 0x24 */
522 tmp = sio_read(port, 0x24);
523 tmp |= (1 << 2) | (1 << 3);
524 sio_write(port, 0x24, tmp);
525
526 /* Clear bit 3 (GLB_REG_WE) of reg 0x23: Makes reg 0x24-0x2A ro */
527 tmp = sio_read(port, 0x23);
528 tmp &= ~(1 << 3);
529 sio_write(port, 0x23, tmp);
530
531 exit_conf_mode_ite(port);
532
533 return 0;
534}
535
536/*
537 * Suited for:
538 * - ASUS P4SC-E: SiS 651 + 962 + ITE IT8707F
539 */
540static int it8707f_write_enable_2e(void)
541{
542 return it8707f_write_enable(0x2e);
543}
544
Michael Karchercba52de2011-03-06 12:07:19 +0000545#define PC87360_ID 0xE1
546#define PC87364_ID 0xE4
547
548static int pc8736x_gpio_set(uint8_t chipid, uint8_t gpio, int raise)
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000549{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000550 static const int bankbase[] = {0, 4, 8, 10, 12};
551 int gpio_bank = gpio / 8;
552 int gpio_pin = gpio % 8;
553 uint16_t baseport;
554 uint8_t id, val;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000555
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000556 if (gpio_bank > 4) {
Michael Karchercba52de2011-03-06 12:07:19 +0000557 msg_perr("PC8736x: Invalid GPIO %d\n", gpio);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000558 return -1;
559 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000560
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000561 id = sio_read(0x2E, 0x20);
Michael Karchercba52de2011-03-06 12:07:19 +0000562 if (id != chipid) {
563 msg_perr("PC8736x: unexpected ID %02x (expected %02x)\n", id, chipid);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000564 return -1;
565 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000566
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000567 sio_write(0x2E, 0x07, 0x07); /* Select GPIO device. */
568 baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
569 if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) {
570 msg_perr("PC87360: invalid GPIO base address %04x\n",
571 baseport);
572 return -1;
573 }
574 sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device. */
575 sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin);
576 sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output. */
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000577
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000578 val = INB(baseport + bankbase[gpio_bank]);
579 if (raise)
580 val |= 1 << gpio_pin;
581 else
582 val &= ~(1 << gpio_pin);
583 OUTB(val, baseport + bankbase[gpio_bank]);
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000584
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000585 return 0;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000586}
587
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000588/*
589 * VIA VT823x: Set one of the GPIO pins.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000590 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000591static int via_vt823x_gpio_set(uint8_t gpio, int raise)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000592{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000593 struct pci_dev *dev;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000594 uint16_t base;
David Bartleyf58d3642009-12-09 07:53:01 +0000595 uint8_t val, bit, offset;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000596
Luc Verhaegen73d21192009-12-23 00:54:26 +0000597 dev = pci_dev_find_vendorclass(0x1106, 0x0601);
598 switch (dev->device_id) {
599 case 0x3177: /* VT8235 */
600 case 0x3227: /* VT8237R */
601 case 0x3337: /* VT8237A */
602 break;
603 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000604 msg_perr("\nERROR: VT823x ISA bridge not found.\n");
Luc Verhaegen73d21192009-12-23 00:54:26 +0000605 return -1;
606 }
607
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000608 if ((gpio >= 12) && (gpio <= 15)) {
609 /* GPIO12-15 -> output */
610 val = pci_read_byte(dev, 0xE4);
611 val |= 0x10;
612 pci_write_byte(dev, 0xE4, val);
613 } else if (gpio == 9) {
614 /* GPIO9 -> Output */
615 val = pci_read_byte(dev, 0xE4);
616 val |= 0x20;
617 pci_write_byte(dev, 0xE4, val);
David Bartleyf58d3642009-12-09 07:53:01 +0000618 } else if (gpio == 5) {
619 val = pci_read_byte(dev, 0xE4);
620 val |= 0x01;
621 pci_write_byte(dev, 0xE4, val);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000622 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000623 msg_perr("\nERROR: "
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000624 "VT823x GPIO%02d is not implemented.\n", gpio);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000625 return -1;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000626 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000627
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000628 /* We need the I/O Base Address for this board's flash enable. */
629 base = pci_read_word(dev, 0x88) & 0xff80;
630
David Bartleyf58d3642009-12-09 07:53:01 +0000631 offset = 0x4C + gpio / 8;
632 bit = 0x01 << (gpio % 8);
633
634 val = INB(base + offset);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000635 if (raise)
636 val |= bit;
637 else
638 val &= ~bit;
David Bartleyf58d3642009-12-09 07:53:01 +0000639 OUTB(val, base + offset);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000640
Uwe Hermanna7e05482007-05-09 10:17:44 +0000641 return 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000642}
643
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000644/*
645 * Suited for:
646 * - ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000647 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000648static int via_vt823x_gpio5_raise(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000649{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000650 /* On M2V-MX: GPO5 is connected to WP# and TBL#. */
651 return via_vt823x_gpio_set(5, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000652}
653
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000654/*
655 * Suited for:
656 * - VIA EPIA EK & N & NL
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000657 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000658static int via_vt823x_gpio9_raise(void)
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000659{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000660 return via_vt823x_gpio_set(9, 1);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000661}
662
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000663/*
664 * Suited for:
665 * - VIA EPIA M and MII (and maybe other CLE266 based EPIAs)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000666 *
667 * We don't need to do this for EPIA M when using coreboot, GPIO15 is never
668 * lowered there.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000669 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000670static int via_vt823x_gpio15_raise(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000671{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000672 return via_vt823x_gpio_set(15, 1);
673}
674
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000675/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000676 * Winbond W83697HF Super I/O + VIA VT8235 southbridge
677 *
678 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000679 * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
680 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
Luc Verhaegen73d21192009-12-23 00:54:26 +0000681 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000682static int board_msi_kt4v(void)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000683{
684 int ret;
685
686 ret = via_vt823x_gpio_set(12, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000687 w836xx_memw_enable(0x2E);
Luc Verhaegen97866082008-02-09 02:03:06 +0000688
Luc Verhaegen73d21192009-12-23 00:54:26 +0000689 return ret;
Luc Verhaegen97866082008-02-09 02:03:06 +0000690}
691
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000692/*
693 * Suited for:
694 * - ASUS P5A
Luc Verhaegen6b141752007-05-20 16:16:13 +0000695 *
696 * This is rather nasty code, but there's no way to do this cleanly.
697 * We're basically talking to some unknown device on SMBus, my guess
698 * is that it is the Winbond W83781D that lives near the DIP BIOS.
699 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000700static int board_asus_p5a(void)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000701{
702 uint8_t tmp;
703 int i;
704
705#define ASUSP5A_LOOP 5000
706
Andriy Gapon65c1b862008-05-22 13:22:45 +0000707 OUTB(0x00, 0xE807);
708 OUTB(0xEF, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000709
Andriy Gapon65c1b862008-05-22 13:22:45 +0000710 OUTB(0xFF, 0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000711
712 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000713 OUTB(0xE1, 0xFF);
714 if (INB(0xE800) & 0x04)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000715 break;
716 }
717
718 if (i == ASUSP5A_LOOP) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000719 msg_perr("Unable to contact device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000720 return -1;
721 }
722
Andriy Gapon65c1b862008-05-22 13:22:45 +0000723 OUTB(0x20, 0xE801);
724 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000725
Andriy Gapon65c1b862008-05-22 13:22:45 +0000726 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000727
728 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000729 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000730 if (tmp & 0x70)
731 break;
732 }
733
734 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000735 msg_perr("Failed to read device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000736 return -1;
737 }
738
Andriy Gapon65c1b862008-05-22 13:22:45 +0000739 tmp = INB(0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000740 tmp &= ~0x02;
741
Andriy Gapon65c1b862008-05-22 13:22:45 +0000742 OUTB(0x00, 0xE807);
743 OUTB(0xEE, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000744
Andriy Gapon65c1b862008-05-22 13:22:45 +0000745 OUTB(tmp, 0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000746
Andriy Gapon65c1b862008-05-22 13:22:45 +0000747 OUTB(0xFF, 0xE800);
748 OUTB(0xE1, 0xFF);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000749
Andriy Gapon65c1b862008-05-22 13:22:45 +0000750 OUTB(0x20, 0xE801);
751 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000752
Andriy Gapon65c1b862008-05-22 13:22:45 +0000753 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000754
755 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000756 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000757 if (tmp & 0x70)
758 break;
759 }
760
761 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000762 msg_perr("Failed to write to device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000763 return -1;
764 }
765
766 return 0;
767}
768
Luc Verhaegena7e30502009-12-09 11:39:02 +0000769/*
770 * Set GPIO lines in the Broadcom HT-1000 southbridge.
771 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000772 * It's not a Super I/O but it uses the same index/data port method.
Luc Verhaegena7e30502009-12-09 11:39:02 +0000773 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000774static int board_hp_dl145_g3_enable(void)
Luc Verhaegena7e30502009-12-09 11:39:02 +0000775{
776 /* GPIO 0 reg from PM regs */
777 /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
778 sio_mask(0xcd6, 0x44, 0x24, 0x24);
779
780 return 0;
781}
782
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +0000783/*
784 * Set GPIO lines in the Broadcom HT-1000 southbridge.
785 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000786 * It's not a Super I/O but it uses the same index/data port method.
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +0000787 */
788static int board_hp_dl165_g6_enable(void)
789{
790 /* Variant of DL145, with slightly different pin placement. */
791 sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */
792 sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */
793
794 return 0;
795}
796
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000797static int board_ibm_x3455(void)
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000798{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000799 /* Raise GPIO13. */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +0000800 sio_mask(0xcd6, 0x45, 0x20, 0x20);
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000801
802 return 0;
803}
804
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000805/*
806 * Suited for:
807 * - Shuttle FN25 (SN25P): AMD S939 + NVIDIA CK804 (nForce4)
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000808 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000809static int board_shuttle_fn25(void)
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000810{
811 struct pci_dev *dev;
812
813 dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA Bridge. */
814 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000815 msg_perr("\nERROR: NVIDIA nForce4 ISA bridge not found.\n");
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000816 return -1;
817 }
818
819 /* one of those bits seems to be connected to TBL#, but -ENOINFO. */
820 pci_write_byte(dev, 0x92, 0);
821
822 return 0;
823}
824
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000825/*
Mattias Mattssonf4925162010-09-16 22:09:18 +0000826 * Suited for:
827 * - Elitegroup GeForce6100SM-M: NVIDIA MCP61 + ITE IT8726F
828 */
Mattias Mattssonf4925162010-09-16 22:09:18 +0000829static int board_ecs_geforce6100sm_m(void)
830{
831 struct pci_dev *dev;
832 uint32_t tmp;
833
834 dev = pci_dev_find(0x10DE, 0x03EB); /* NVIDIA MCP61 SMBus. */
835 if (!dev) {
836 msg_perr("\nERROR: NVIDIA MCP61 SMBus not found.\n");
837 return -1;
838 }
839
840 tmp = pci_read_byte(dev, 0xE0);
841 tmp &= ~(1 << 3);
842 pci_write_byte(dev, 0xE0, tmp);
843
844 return 0;
845}
846
847/*
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000848 * Very similar to AMD 8111 IO Hub.
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000849 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000850static int nvidia_mcp_gpio_set(int gpio, int raise)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000851{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000852 struct pci_dev *dev;
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000853 uint16_t base;
Michael Karcher2ead2e22010-06-01 16:09:06 +0000854 uint16_t devclass;
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000855 uint8_t tmp;
856
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000857 if ((gpio < 0) || (gpio >= 0x40)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000858 msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000859 return -1;
860 }
861
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000862 /* First, check the ISA Bridge */
863 dev = pci_dev_find_vendorclass(0x10DE, 0x0601);
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000864 switch (dev->device_id) {
865 case 0x0030: /* CK804 */
866 case 0x0050: /* MCP04 */
867 case 0x0060: /* MCP2 */
Michael Karcher5f31ebe2010-06-12 23:07:26 +0000868 case 0x00E0: /* CK8 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000869 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +0000870 case 0x0260: /* MCP51 */
Michael Karcher242efd42011-03-06 12:09:05 +0000871 case 0x0261: /* MCP51 */
Michael Karcher2ead2e22010-06-01 16:09:06 +0000872 case 0x0364: /* MCP55 */
873 /* find SMBus controller on *this* southbridge */
874 /* The infamous Tyan S2915-E has two south bridges; they are
875 easily told apart from each other by the class of the
876 LPC bridge, but have the same SMBus bridge IDs */
877 if (dev->func != 0) {
878 msg_perr("MCP LPC bridge at unexpected function"
879 " number %d\n", dev->func);
880 return -1;
881 }
882
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +0000883#if PCI_LIB_VERSION >= 0x020200
Michael Karcher2ead2e22010-06-01 16:09:06 +0000884 dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1);
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +0000885#else
886 /* pciutils/libpci before version 2.2 is too old to support
887 * PCI domains. Such old machines usually don't have domains
888 * besides domain 0, so this is not a problem.
889 */
890 dev = pci_get_dev(pacc, dev->bus, dev->dev, 1);
891#endif
Michael Karcher2ead2e22010-06-01 16:09:06 +0000892 if (!dev) {
893 msg_perr("MCP SMBus controller could not be found\n");
894 return -1;
895 }
896 devclass = pci_read_word(dev, PCI_CLASS_DEVICE);
897 if (devclass != 0x0C05) {
898 msg_perr("Unexpected device class %04x for SMBus"
899 " controller\n", devclass);
900 return -1;
901 }
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000902 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +0000903 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000904 msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n");
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000905 return -1;
906 }
907
908 base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
909 base += 0xC0;
910
911 tmp = INB(base + gpio);
912 tmp &= ~0x0F; /* null lower nibble */
913 tmp |= 0x04; /* gpio -> output. */
914 if (raise)
915 tmp |= 0x01;
916 OUTB(tmp, base + gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000917
918 return 0;
919}
920
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000921/*
922 * Suited for:
Sean Nelson0a247512010-08-15 14:36:18 +0000923 * - ASUS A8N-LA (HP OEM "Nagami-GL8E"): NVIDIA MCP51
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000924 * - ASUS M2NBP-VM CSM: NVIDIA MCP51
Michael Karcherb2184c12010-03-07 16:42:55 +0000925 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000926static int nvidia_mcp_gpio0_raise(void)
Michael Karcherb2184c12010-03-07 16:42:55 +0000927{
928 return nvidia_mcp_gpio_set(0x00, 1);
929}
930
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000931/*
932 * Suited for:
933 * - abit KN8 Ultra: NVIDIA CK804
Sean Nelson92bc6bd2010-03-19 22:37:29 +0000934 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000935static int nvidia_mcp_gpio2_lower(void)
Sean Nelson92bc6bd2010-03-19 22:37:29 +0000936{
937 return nvidia_mcp_gpio_set(0x02, 0);
938}
939
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000940/*
941 * Suited for:
Michael Karcher2842db32011-04-14 23:14:27 +0000942 * - Foxconn 6150K8MD-8EKRSH: Socket 939 + NVIDIA MCP51
Uwe Hermannead705f2010-08-15 15:26:30 +0000943 * - MSI K8N Neo4: NVIDIA CK804. TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html.
944 * - MSI K8NGM2-L: NVIDIA MCP51
Luc Verhaegen6c5f7332009-12-23 03:01:36 +0000945 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000946static int nvidia_mcp_gpio2_raise(void)
Luc Verhaegen6c5f7332009-12-23 03:01:36 +0000947{
948 return nvidia_mcp_gpio_set(0x02, 1);
949}
950
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000951/*
952 * Suited for:
Uwe Hermann83d349a2010-10-18 22:32:03 +0000953 * - EPoX EP-8NPA7I: Socket 754 + NVIDIA nForce4 4X
Jonathan Kollaschf8db9592010-10-15 23:02:15 +0000954 */
955static int nvidia_mcp_gpio4_raise(void)
956{
957 return nvidia_mcp_gpio_set(0x04, 1);
958}
959
960/*
961 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000962 * - HP xw9400 (Tyan S2915-E OEM): Dual(!) NVIDIA MCP55
963 *
964 * Notes: a) There are two MCP55 chips, so also two SMBus bridges on that
965 * board. We can't tell the SMBus logical devices apart, but we
966 * can tell the LPC bridge functions apart.
967 * We need to choose the SMBus bridge next to the LPC bridge with
968 * ID 0x364 and the "LPC bridge" class.
969 * b) #TBL is hardwired on that board to a pull-down. It can be
970 * overridden by connecting the two solder points next to F2.
Michael Karcher2ead2e22010-06-01 16:09:06 +0000971 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000972static int nvidia_mcp_gpio5_raise(void)
Michael Karcher2ead2e22010-06-01 16:09:06 +0000973{
974 return nvidia_mcp_gpio_set(0x05, 1);
975}
976
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000977/*
978 * Suited for:
979 * - abit NF7-S: NVIDIA CK804
Michael Karcher8f10d242010-04-11 21:01:06 +0000980 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000981static int nvidia_mcp_gpio8_raise(void)
Michael Karcher8f10d242010-04-11 21:01:06 +0000982{
983 return nvidia_mcp_gpio_set(0x08, 1);
984}
985
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000986/*
987 * Suited for:
Idwer Volleringd8a00a02011-06-13 16:58:54 +0000988 * - Gigabyte GA-K8NS Pro-939: Socket 939 + NVIDIA nForce3 + CK8
989 */
990static int nvidia_mcp_gpio0a_raise(void)
991{
992 return nvidia_mcp_gpio_set(0x0a, 1);
993}
994
995/*
996 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000997 * - MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + CK8
Michael Karcher5f31ebe2010-06-12 23:07:26 +0000998 */
Michael Karcher51825082010-06-12 23:14:03 +0000999static int nvidia_mcp_gpio0c_raise(void)
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001000{
1001 return nvidia_mcp_gpio_set(0x0c, 1);
1002}
1003
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001004/*
1005 * Suited for:
1006 * - abit NF-M2 nView: Socket AM2 + NVIDIA MCP51
Michael Karcherefd8af32010-07-24 22:50:54 +00001007 */
1008static int nvidia_mcp_gpio4_lower(void)
1009{
1010 return nvidia_mcp_gpio_set(0x04, 0);
1011}
1012
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001013/*
1014 * Suited for:
1015 * - ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001016 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001017static int nvidia_mcp_gpio10_raise(void)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001018{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001019 return nvidia_mcp_gpio_set(0x10, 1);
1020}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001021
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001022/*
1023 * Suited for:
1024 * - GIGABYTE GA-K8N-SLI: AMD socket 939 + NVIDIA CK804 + ITE IT8712F
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001025 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001026static int nvidia_mcp_gpio21_raise(void)
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001027{
1028 return nvidia_mcp_gpio_set(0x21, 0x01);
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001029}
1030
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001031/*
1032 * Suited for:
1033 * - EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001034 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001035static int nvidia_mcp_gpio31_raise(void)
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001036{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +00001037 return nvidia_mcp_gpio_set(0x31, 0x01);
Luc Verhaegen2c04fab2009-10-05 18:46:35 +00001038}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +00001039
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001040/*
1041 * Suited for:
Michael Karcher242efd42011-03-06 12:09:05 +00001042 * - GIGABYTE GA-K8N51GMF: Socket 754 + Geforce 6100 + MCP51
1043 * - GIGABYTE GA-K8N51GMF-9: Socket 939 + Geforce 6100 + MCP51
Joshua Roys2ee137f2010-09-07 17:52:09 +00001044 */
1045static int nvidia_mcp_gpio3b_raise(void)
1046{
1047 return nvidia_mcp_gpio_set(0x3b, 1);
1048}
1049
1050/*
1051 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001052 * - Artec Group DBE61 and DBE62
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001053 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001054static int board_artecgroup_dbe6x(void)
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001055{
1056#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001057#define DBE6x_PRI_BOOT_LOC_SHIFT 2
1058#define DBE6x_BOOT_OP_LATCHED_SHIFT 8
1059#define DBE6x_SEC_BOOT_LOC_SHIFT 10
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001060#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
1061#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
1062#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001063#define DBE6x_BOOT_LOC_FLASH 2
1064#define DBE6x_BOOT_LOC_FWHUB 3
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001065
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001066 msr_t msr;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001067 unsigned long boot_loc;
1068
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001069 /* Geode only has a single core */
1070 if (setup_cpu_msr(0))
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001071 return -1;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001072
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001073 msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001074
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001075 if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) ==
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001076 (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
1077 boot_loc = DBE6x_BOOT_LOC_FWHUB;
1078 else
1079 boot_loc = DBE6x_BOOT_LOC_FLASH;
1080
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001081 msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
1082 msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
Uwe Hermann394131e2008-10-18 21:14:13 +00001083 (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001084
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001085 wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001086
Stefan Reinauerb4fe6642009-08-12 18:25:24 +00001087 cleanup_cpu_msr();
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001088
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001089 return 0;
1090}
1091
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001092/*
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001093 * Suited for:
1094 * - Asus A8AE-LE (Codename AmberineM; used in Compaq Presario 061)
1095 * Datasheet(s) used:
1096 * - AMD document 43009 "AMD SB700/710/750 Register Reference Guide" rev. 1.00
1097 */
1098static int amd_sbxxx_gpio9_raise(void)
1099{
1100 struct pci_dev *dev;
1101 uint32_t reg;
1102
1103 dev = pci_dev_find(0x1002, 0x4372); /* AMD SMBus Controller */
1104 if (!dev) {
1105 msg_perr("\nERROR: AMD SMBus Controller (0x4372) not found.\n");
1106 return -1;
1107 }
1108
1109 reg = pci_read_long(dev, 0xA8); /* GPIO_12_to_4_Cntrl CI_Reg: A8h-ABh */
1110 /* enable output (0: enable, 1: tristate):
1111 GPIO9 output enable is at bit 5 in 0xA9 */
1112 reg &= ~((uint32_t)1<<(8+5));
1113 /* raise:
1114 GPIO9 output register is at bit 5 in 0xA8 */
1115 reg |= (1<<5);
1116 pci_write_long(dev, 0xA8, reg);
1117
1118 return 0;
1119}
1120
1121/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001122 * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}.
Luc Verhaegenf5226912009-12-14 10:41:58 +00001123 */
1124static int intel_piix4_gpo_set(unsigned int gpo, int raise)
1125{
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001126 unsigned int gpo_byte, gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001127 struct pci_dev *dev;
1128 uint32_t tmp, base;
1129
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001130 static const uint32_t nonmuxed_gpos = 0x58000101; /* GPPO {0,8,27,28,30} are always available */
1131
1132 static const struct {unsigned int reg, mask, value; } piix4_gpo[] = {
1133 {0},
1134 {0xB0, 0x0001, 0x0000}, /* GPO1... */
1135 {0xB0, 0x0001, 0x0000},
1136 {0xB0, 0x0001, 0x0000},
1137 {0xB0, 0x0001, 0x0000},
1138 {0xB0, 0x0001, 0x0000},
1139 {0xB0, 0x0001, 0x0000},
1140 {0xB0, 0x0001, 0x0000}, /* ...GPO7: GENCFG bit 0 */
1141 {0},
1142 {0xB0, 0x0100, 0x0000}, /* GPO9: GENCFG bit 8 */
1143 {0xB0, 0x0200, 0x0000}, /* GPO10: GENCFG bit 9 */
1144 {0xB0, 0x0400, 0x0000}, /* GPO11: GENCFG bit 10 */
1145 {0x4E, 0x0100, 0x0000}, /* GPO12... */
1146 {0x4E, 0x0100, 0x0000},
1147 {0x4E, 0x0100, 0x0000}, /* ...GPO14: XBCS bit 8 */
1148 {0xB2, 0x0002, 0x0002}, /* GPO15... */
1149 {0xB2, 0x0002, 0x0002}, /* ...GPO16: GENCFG bit 17 */
1150 {0xB2, 0x0004, 0x0004}, /* GPO17: GENCFG bit 18 */
1151 {0xB2, 0x0008, 0x0008}, /* GPO18: GENCFG bit 19 */
1152 {0xB2, 0x0010, 0x0010}, /* GPO19: GENCFG bit 20 */
1153 {0xB2, 0x0020, 0x0020}, /* GPO20: GENCFG bit 21 */
1154 {0xB2, 0x0040, 0x0040}, /* GPO21: GENCFG bit 22 */
1155 {0xB2, 0x1000, 0x1000}, /* GPO22... */
1156 {0xB2, 0x1000, 0x1000}, /* ...GPO23: GENCFG bit 28 */
1157 {0xB2, 0x2000, 0x2000}, /* GPO24: GENCFG bit 29 */
1158 {0xB2, 0x4000, 0x4000}, /* GPO25: GENCFG bit 30 */
1159 {0xB2, 0x8000, 0x8000}, /* GPO26: GENCFG bit 31 */
1160 {0},
1161 {0},
1162 {0x4E, 0x0100, 0x0000}, /* ...GPO29: XBCS bit 8 */
1163 {0}
1164 };
1165
1166
Luc Verhaegenf5226912009-12-14 10:41:58 +00001167 dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */
1168 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001169 msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001170 return -1;
1171 }
1172
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001173 /* Sanity check. */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001174 if (gpo > 30) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001175 msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001176 return -1;
1177 }
1178
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001179 if ( (((1 << gpo) & nonmuxed_gpos) == 0) &&
1180 (pci_read_word(dev, piix4_gpo[gpo].reg) & piix4_gpo[gpo].mask) != piix4_gpo[gpo].value ) {
Peter Huewe3d3fd6a2011-01-25 00:23:32 +00001181 msg_perr("\nERROR: PIIX4 GPO%d not programmed for output.\n", gpo);
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001182 return -1;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001183 }
1184
Luc Verhaegenf5226912009-12-14 10:41:58 +00001185 dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */
1186 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001187 msg_perr("\nERROR: Intel PIIX4 PM not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001188 return -1;
1189 }
1190
1191 /* PM IO base */
1192 base = pci_read_long(dev, 0x40) & 0x0000FFC0;
1193
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001194 gpo_byte = gpo >> 3;
1195 gpo_bit = gpo & 7;
1196 tmp = INB(base + 0x34 + gpo_byte); /* GPO register */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001197 if (raise)
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001198 tmp |= 0x01 << gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001199 else
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001200 tmp &= ~(0x01 << gpo_bit);
1201 OUTB(tmp, base + 0x34 + gpo_byte);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001202
1203 return 0;
1204}
1205
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001206/*
1207 * Suited for:
Mattias Mattsson85016b92010-09-01 01:21:34 +00001208 * - ASUS P2B-N
1209 */
1210static int intel_piix4_gpo18_lower(void)
1211{
1212 return intel_piix4_gpo_set(18, 0);
1213}
1214
1215/*
1216 * Suited for:
Mattias Mattssonc8ca3de2010-09-13 18:22:36 +00001217 * - MSI MS-6163 v2 (MS-6163 Pro): Intel 440BX + PIIX4E + Winbond W83977EF
1218 */
1219static int intel_piix4_gpo14_raise(void)
1220{
1221 return intel_piix4_gpo_set(14, 1);
1222}
1223
1224/*
1225 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001226 * - EPoX EP-BX3
Luc Verhaegenf5226912009-12-14 10:41:58 +00001227 */
Mattias Mattssond7ed7f72010-08-15 22:35:31 +00001228static int intel_piix4_gpo22_raise(void)
Luc Verhaegenf5226912009-12-14 10:41:58 +00001229{
1230 return intel_piix4_gpo_set(22, 1);
1231}
1232
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001233/*
1234 * Suited for:
Tim ter Laak4b933f02010-09-13 23:00:57 +00001235 * - abit BM6
1236 */
1237static int intel_piix4_gpo26_lower(void)
1238{
1239 return intel_piix4_gpo_set(26, 0);
1240}
1241
1242/*
1243 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001244 * - Intel SE440BX-2
Michael Karcher51cd0c92010-03-19 22:35:21 +00001245 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001246static int intel_piix4_gpo27_lower(void)
Michael Karcher51cd0c92010-03-19 22:35:21 +00001247{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001248 return intel_piix4_gpo_set(27, 0);
Michael Karcher51cd0c92010-03-19 22:35:21 +00001249}
1250
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001251/*
Mattias Mattsson2eaad632010-10-05 21:32:29 +00001252 * Suited for:
1253 * - Dell OptiPlex GX1
1254 */
1255static int intel_piix4_gpo30_lower(void)
1256{
1257 return intel_piix4_gpo_set(30, 0);
1258}
1259
1260/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001261 * Set a GPIO line on a given Intel ICH LPC controller.
Uwe Hermann93f66db2008-05-22 21:19:38 +00001262 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001263static int intel_ich_gpio_set(int gpio, int raise)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001264{
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001265 /* Table mapping the different Intel ICH LPC chipsets. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001266 static struct {
1267 uint16_t id;
1268 uint8_t base_reg;
1269 uint32_t bank0;
1270 uint32_t bank1;
1271 uint32_t bank2;
1272 } intel_ich_gpio_table[] = {
1273 {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */
1274 {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */
1275 {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */
1276 {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */
1277 {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */
1278 {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */
1279 {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */
1280 {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */
1281 {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */
1282 {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */
1283 {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */
1284 {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */
1285 {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */
1286 {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */
1287 {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */
1288 {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */
1289 {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */
1290 {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */
1291 {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */
1292 {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */
1293 {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */
1294 {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */
1295 {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */
1296 {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */
1297 {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */
1298 {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */
1299 {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */
1300 {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */
1301 {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */
1302 {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */
1303 {0, 0, 0, 0, 0} /* end marker */
1304 };
Uwe Hermann93f66db2008-05-22 21:19:38 +00001305
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001306 struct pci_dev *dev;
1307 uint16_t base;
1308 uint32_t tmp;
1309 int i, allowed;
1310
1311 /* First, look for a known LPC bridge */
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001312 for (dev = pacc->devices; dev; dev = dev->next) {
Carl-Daniel Hailfingerd175e062010-05-21 23:00:56 +00001313 uint16_t device_class;
1314 /* libpci before version 2.2.4 does not store class info. */
1315 device_class = pci_read_word(dev, PCI_CLASS_DEVICE);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001316 if ((dev->vendor_id == 0x8086) &&
Carl-Daniel Hailfingerd175e062010-05-21 23:00:56 +00001317 (device_class == 0x0601)) { /* ISA Bridge */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001318 /* Is this device in our list? */
1319 for (i = 0; intel_ich_gpio_table[i].id; i++)
1320 if (dev->device_id == intel_ich_gpio_table[i].id)
1321 break;
1322
1323 if (intel_ich_gpio_table[i].id)
1324 break;
1325 }
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001326 }
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001327
Uwe Hermann93f66db2008-05-22 21:19:38 +00001328 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001329 msg_perr("\nERROR: No Known Intel LPC Bridge found.\n");
Uwe Hermann93f66db2008-05-22 21:19:38 +00001330 return -1;
1331 }
1332
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001333 /*
1334 * According to the datasheets, all Intel ICHs have the GPIO bar 5:1
1335 * strapped to zero. From some mobile ICH9 version on, this becomes
1336 * 6:1. The mask below catches all.
1337 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001338 base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
Uwe Hermann93f66db2008-05-22 21:19:38 +00001339
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001340 /* Check whether the line is allowed. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001341 if (gpio < 32)
1342 allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01;
1343 else if (gpio < 64)
1344 allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01;
1345 else
1346 allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;
1347
1348 if (!allowed) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001349 msg_perr("\nERROR: This Intel LPC Bridge does not allow"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001350 " setting GPIO%02d\n", gpio);
1351 return -1;
1352 }
1353
Sean Nelson316a29f2010-05-07 20:09:04 +00001354 msg_pdbg("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n",
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001355 raise ? "Rais" : "Dropp", gpio);
1356
1357 if (gpio < 32) {
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001358 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001359 tmp = INL(base);
1360 /* ICH/ICH0 multiplexes 27/28 on the line set. */
1361 if ((gpio == 28) &&
1362 ((dev->device_id == 0x2410) || (dev->device_id == 0x2420)))
1363 tmp |= 1 << 27;
1364 else
1365 tmp |= 1 << gpio;
1366 OUTL(tmp, base);
1367
1368 /* As soon as we are talking to ICH8 and above, this register
1369 decides whether we can set the gpio or not. */
1370 if (dev->device_id > 0x2800) {
1371 tmp = INL(base);
1372 if (!(tmp & (1 << gpio))) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001373 msg_perr("\nERROR: This Intel LPC Bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001374 " does not allow setting GPIO%02d\n",
1375 gpio);
1376 return -1;
1377 }
1378 }
1379
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001380 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001381 tmp = INL(base + 0x04);
1382 tmp &= ~(1 << gpio);
1383 OUTL(tmp, base + 0x04);
1384
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001385 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001386 tmp = INL(base + 0x0C);
1387 if (raise)
1388 tmp |= 1 << gpio;
1389 else
1390 tmp &= ~(1 << gpio);
1391 OUTL(tmp, base + 0x0C);
1392 } else if (gpio < 64) {
1393 gpio -= 32;
1394
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001395 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001396 tmp = INL(base + 0x30);
1397 tmp |= 1 << gpio;
1398 OUTL(tmp, base + 0x30);
1399
1400 /* As soon as we are talking to ICH8 and above, this register
1401 decides whether we can set the gpio or not. */
1402 if (dev->device_id > 0x2800) {
1403 tmp = INL(base + 30);
1404 if (!(tmp & (1 << gpio))) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001405 msg_perr("\nERROR: This Intel LPC Bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001406 " does not allow setting GPIO%02d\n",
1407 gpio + 32);
1408 return -1;
1409 }
1410 }
1411
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001412 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001413 tmp = INL(base + 0x34);
1414 tmp &= ~(1 << gpio);
1415 OUTL(tmp, base + 0x34);
1416
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001417 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001418 tmp = INL(base + 0x38);
1419 if (raise)
1420 tmp |= 1 << gpio;
1421 else
1422 tmp &= ~(1 << gpio);
1423 OUTL(tmp, base + 0x38);
1424 } else {
1425 gpio -= 64;
1426
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001427 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001428 tmp = INL(base + 0x40);
1429 tmp |= 1 << gpio;
1430 OUTL(tmp, base + 0x40);
1431
1432 tmp = INL(base + 40);
1433 if (!(tmp & (1 << gpio))) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001434 msg_perr("\nERROR: This Intel LPC Bridge does "
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001435 "not allow setting GPIO%02d\n", gpio + 64);
1436 return -1;
1437 }
1438
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001439 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001440 tmp = INL(base + 0x44);
1441 tmp &= ~(1 << gpio);
1442 OUTL(tmp, base + 0x44);
1443
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001444 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001445 tmp = INL(base + 0x48);
1446 if (raise)
1447 tmp |= 1 << gpio;
1448 else
1449 tmp &= ~(1 << gpio);
1450 OUTL(tmp, base + 0x48);
1451 }
Uwe Hermann93f66db2008-05-22 21:19:38 +00001452
1453 return 0;
1454}
1455
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001456/*
1457 * Suited for:
1458 * - abit IP35: Intel P35 + ICH9R
1459 * - abit IP35 Pro: Intel P35 + ICH9R
Uwe Hermann93f66db2008-05-22 21:19:38 +00001460 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001461static int intel_ich_gpio16_raise(void)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001462{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001463 return intel_ich_gpio_set(16, 1);
Uwe Hermann93f66db2008-05-22 21:19:38 +00001464}
1465
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001466/*
1467 * Suited for:
1468 * - HP Puffer2-UL8E (ASUS PTGD-LA OEM): LGA775 + 915 + ICH6
Michael Karchere57957c2010-07-24 11:14:37 +00001469 */
1470static int intel_ich_gpio18_raise(void)
1471{
1472 return intel_ich_gpio_set(18, 1);
1473}
1474
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001475/*
1476 * Suited for:
Uwe Hermannead705f2010-08-15 15:26:30 +00001477 * - ASUS A8Jm (laptop): Intel 945 + ICH7
James Lancaster998c9dc2010-03-19 22:39:24 +00001478 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001479static int intel_ich_gpio34_raise(void)
James Lancaster998c9dc2010-03-19 22:39:24 +00001480{
1481 return intel_ich_gpio_set(34, 1);
1482}
1483
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001484/*
1485 * Suited for:
1486 * - MSI MS-7046: LGA775 + 915P + ICH6
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001487 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001488static int intel_ich_gpio19_raise(void)
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001489{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001490 return intel_ich_gpio_set(19, 1);
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001491}
1492
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001493/*
Luc Verhaegen6c5d4cc2009-11-28 18:26:21 +00001494 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001495 * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2
1496 * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5
Michael Karcherf4b58792010-09-10 14:54:18 +00001497 * - ASUS P4P800: Intel socket478 + 865PE + ICH5R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001498 * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R
Diego Elio Pettenòc6f71462011-03-06 22:52:55 +00001499 * - ASUS P4P800-VM: Intel socket478 + 865PE + ICH5R
Michael Karcher4a23e442010-09-10 14:46:46 +00001500 * - ASUS P5GD1 Pro: Intel LGA 775 + 915P + ICH6R
Joshua Roysb1d980f2010-09-13 14:02:22 +00001501 * - ASUS P5GDC Deluxe: Intel socket775 + 915P + ICH6R
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001502 * - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5
1503 * - Samsung Polaris 32: socket478 + 865P + ICH5
Peter Stuge09c13332009-02-02 22:55:26 +00001504 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001505static int intel_ich_gpio21_raise(void)
Peter Stuge09c13332009-02-02 22:55:26 +00001506{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001507 return intel_ich_gpio_set(21, 1);
Peter Stuge09c13332009-02-02 22:55:26 +00001508}
1509
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001510/*
Michael Karcher03b80e92010-03-07 16:32:32 +00001511 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001512 * - ASUS P4B266: socket478 + Intel 845D + ICH2
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001513 * - ASUS P4B533-E: socket478 + 845E + ICH4
1514 * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001515 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001516static int intel_ich_gpio22_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001517{
1518 return intel_ich_gpio_set(22, 1);
1519}
1520
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001521/*
1522 * Suited for:
1523 * - HP Vectra VL400: 815 + ICH + PC87360
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001524 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001525static int board_hp_vl400(void)
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001526{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001527 int ret;
1528 ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */
1529 if (!ret)
Michael Karchercba52de2011-03-06 12:07:19 +00001530 ret = pc8736x_gpio_set(PC87360_ID, 0x09, 1); /* #WP ? */
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001531 if (!ret)
Michael Karchercba52de2011-03-06 12:07:19 +00001532 ret = pc8736x_gpio_set(PC87360_ID, 0x27, 1); /* #TBL */
1533 return ret;
1534}
1535
1536/*
1537 * Suited for:
1538 * - HP e-Vectra P2706T: 810E + ICH + PC87364
1539 */
1540static int board_hp_p2706t(void)
1541{
1542 int ret;
1543 ret = pc8736x_gpio_set(PC87364_ID, 0x25, 1);
1544 if (!ret)
1545 ret = pc8736x_gpio_set(PC87364_ID, 0x26, 1);
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001546 return ret;
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001547}
1548
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001549/*
Luc Verhaegen1265d8d2009-11-28 18:16:31 +00001550 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001551 * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R
1552 * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R
1553 * - ASRock 775i65G: Intel LGA 775 + 865G + ICH5
Uwe Hermann742999c2010-12-02 21:57:42 +00001554 * - MSI MS-6391 (845 Pro4): Intel Socket478 + 845 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001555 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001556static int intel_ich_gpio23_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001557{
1558 return intel_ich_gpio_set(23, 1);
1559}
1560
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001561/*
1562 * Suited for:
Michael Karcher39dcdec2010-10-05 17:29:35 +00001563 * - GIGABYTE GA-6IEM: Intel Socket370 + i815 + ICH2
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001564 * - GIGABYTE GA-8IRML: Intel Socket478 + i845 + ICH2
Michael Karcherc7a1ffb2010-07-24 22:27:29 +00001565 */
1566static int intel_ich_gpio25_raise(void)
1567{
1568 return intel_ich_gpio_set(25, 1);
1569}
1570
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001571/*
1572 * Suited for:
1573 * - IBASE MB899: i945GM + ICH7
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001574 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001575static int intel_ich_gpio26_raise(void)
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001576{
1577 return intel_ich_gpio_set(26, 1);
1578}
1579
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001580/*
1581 * Suited for:
1582 * - P4SD-LA (HP OEM): i865 + ICH5
Michael Karcherc8613242010-08-13 12:49:01 +00001583 * - GIGABYTE GA-8PE667 Ultra 2: socket 478 + i845PE + ICH4
Maciej Pijanka6add0942011-06-09 20:59:30 +00001584 * - MSI MS-6788-40 (aka 848P Neo-V)
Michael Karcher87c90992010-07-24 11:03:48 +00001585 */
Idwer Vollering19dceac2010-07-24 18:47:45 +00001586static int intel_ich_gpio32_raise(void)
Michael Karcher87c90992010-07-24 11:03:48 +00001587{
1588 return intel_ich_gpio_set(32, 1);
1589}
1590
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001591/*
1592 * Suited for:
Joshua Roys7225ccd2011-05-18 01:32:16 +00001593 * - AOpen i975Xa-YDG: i975X + ICH7 + W83627EHF
1594 */
1595static int board_aopen_i975xa_ydg(void)
1596{
1597 int ret;
1598
1599 /* vendor BIOS ends up in LDN6... maybe the board enable is wrong,
1600 * or perhaps it's not needed at all?
1601 * the regs it tries to touch are 0xF0, 0xF1, 0xF2 which means if it
1602 * were in the right LDN, it would have to be GPIO1 or GPIO3
1603 */
1604/*
1605 ret = winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, x, 0)
1606 if (!ret)
1607*/
1608 ret = intel_ich_gpio_set(33, 1);
1609
1610 return ret;
1611}
1612
1613/*
1614 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001615 * - Acorp 6A815EPD: socket 370 + intel 815 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001616 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001617static int board_acorp_6a815epd(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001618{
1619 int ret;
1620
1621 /* Lower Blocks Lock -- pin 7 of PLCC32 */
1622 ret = intel_ich_gpio_set(22, 1);
1623 if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */
1624 ret = intel_ich_gpio_set(23, 1);
1625
1626 return ret;
1627}
1628
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001629/*
1630 * Suited for:
1631 * - Kontron 986LCD-M: Socket478 + 915GM + ICH7R
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001632 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001633static int board_kontron_986lcd_m(void)
Stefan Reinauerac378972008-03-17 22:59:40 +00001634{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001635 int ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001636
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001637 ret = intel_ich_gpio_set(34, 1); /* #TBL */
1638 if (!ret)
1639 ret = intel_ich_gpio_set(35, 1); /* #WP */
Stefan Reinauerac378972008-03-17 22:59:40 +00001640
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001641 return ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001642}
1643
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001644/*
1645 * Suited for:
1646 * - Soyo SY-7VCA: Pro133A + VT82C686
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001647 */
Michael Karcher06477332010-03-19 22:49:09 +00001648static int via_apollo_gpo_set(int gpio, int raise)
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001649{
Michael Karcher06477332010-03-19 22:49:09 +00001650 struct pci_dev *dev;
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001651 uint32_t base;
Michael Karcher06477332010-03-19 22:49:09 +00001652 uint32_t tmp;
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001653
1654 /* VT82C686 Power management */
1655 dev = pci_dev_find(0x1106, 0x3057);
1656 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001657 msg_perr("\nERROR: VT82C686 PM device not found.\n");
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001658 return -1;
1659 }
1660
Sean Nelson316a29f2010-05-07 20:09:04 +00001661 msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n",
Michael Karcher06477332010-03-19 22:49:09 +00001662 raise ? "Rais" : "Dropp", gpio);
1663
1664 /* select GPO function on multiplexed pins */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001665 tmp = pci_read_byte(dev, 0x54);
Michael Karcher06477332010-03-19 22:49:09 +00001666 switch(gpio)
1667 {
1668 case 0:
1669 tmp &= ~0x03;
1670 break;
1671 case 1:
1672 tmp |= 0x04;
1673 break;
1674 case 2:
1675 tmp |= 0x08;
1676 break;
1677 case 3:
1678 tmp |= 0x10;
1679 break;
1680 }
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001681 pci_write_byte(dev, 0x54, tmp);
1682
1683 /* PM IO base */
1684 base = pci_read_long(dev, 0x48) & 0x0000FF00;
1685
1686 /* Drop GPO0 */
Michael Karcher06477332010-03-19 22:49:09 +00001687 tmp = INL(base + 0x4C);
1688 if (raise)
1689 tmp |= 1U << gpio;
1690 else
1691 tmp &= ~(1U << gpio);
1692 OUTL(tmp, base + 0x4C);
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001693
1694 return 0;
1695}
1696
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001697/*
1698 * Suited for:
1699 * - abit VT6X4: Pro133x + VT82C686A
Mattias Mattssone3df96e2010-08-15 22:43:23 +00001700 * - abit VA6: Pro133x + VT82C686A
Michael Karcher187a46a2010-03-19 22:30:49 +00001701 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001702static int via_apollo_gpo4_lower(void)
Michael Karcher187a46a2010-03-19 22:30:49 +00001703{
1704 return via_apollo_gpo_set(4, 0);
1705}
1706
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001707/*
1708 * Suited for:
1709 * - Soyo SY-7VCA: Pro133A + VT82C686
Michael Karcher06477332010-03-19 22:49:09 +00001710 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001711static int via_apollo_gpo0_lower(void)
Michael Karcher06477332010-03-19 22:49:09 +00001712{
1713 return via_apollo_gpo_set(0, 0);
1714}
1715
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001716/*
Michael Karcher9f9e6132010-01-09 17:36:06 +00001717 * Enable some GPIO pin on SiS southbridge.
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001718 *
1719 * Suited for:
1720 * - MSI 651M-L: SiS651 / SiS962
Michael Karcher9f9e6132010-01-09 17:36:06 +00001721 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001722static int board_msi_651ml(void)
Michael Karcher9f9e6132010-01-09 17:36:06 +00001723{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001724 struct pci_dev *dev;
Uwe Hermann43959702010-03-13 17:28:29 +00001725 uint16_t base, temp;
Michael Karcher9f9e6132010-01-09 17:36:06 +00001726
1727 dev = pci_dev_find(0x1039, 0x0962);
1728 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001729 msg_perr("Expected south bridge not found\n");
Michael Karcher9f9e6132010-01-09 17:36:06 +00001730 return 1;
1731 }
1732
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001733 /* Registers 68 and 64 seem like bitmaps. */
Michael Karcher9f9e6132010-01-09 17:36:06 +00001734 base = pci_read_word(dev, 0x74);
1735 temp = INW(base + 0x68);
1736 temp &= ~(1 << 0); /* Make pin output? */
Michael Karcher0435dfd2010-01-09 23:31:13 +00001737 OUTW(temp, base + 0x68);
Michael Karcher9f9e6132010-01-09 17:36:06 +00001738
1739 temp = INW(base + 0x64);
1740 temp |= (1 << 0); /* Raise output? */
1741 OUTW(temp, base + 0x64);
1742
1743 w836xx_memw_enable(0x2E);
1744
1745 return 0;
1746}
1747
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001748/*
Michael Gold6d52e472009-06-19 13:00:24 +00001749 * Find the runtime registers of an SMSC Super I/O, after verifying its
1750 * chip ID.
1751 *
1752 * Returns the base port of the runtime register block, or 0 on error.
1753 */
1754static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
1755 uint8_t logical_device)
1756{
1757 uint16_t rt_port = 0;
1758
1759 /* Verify the chip ID. */
Uwe Hermann1432a602009-06-28 23:26:37 +00001760 OUTB(0x55, sio_port); /* Enable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00001761 if (sio_read(sio_port, 0x20) != chip_id) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001762 msg_perr("\nERROR: SMSC Super I/O not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00001763 goto out;
1764 }
1765
1766 /* If the runtime block is active, get its address. */
1767 sio_write(sio_port, 0x07, logical_device);
1768 if (sio_read(sio_port, 0x30) & 1) {
1769 rt_port = (sio_read(sio_port, 0x60) << 8)
1770 | sio_read(sio_port, 0x61);
1771 }
1772
1773 if (rt_port == 0) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001774 msg_perr("\nERROR: "
Michael Gold6d52e472009-06-19 13:00:24 +00001775 "Super I/O runtime interface not available.\n");
1776 }
1777out:
Uwe Hermann1432a602009-06-28 23:26:37 +00001778 OUTB(0xaa, sio_port); /* Disable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00001779 return rt_port;
1780}
1781
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001782/*
1783 * Disable write protection on the Mitac 6513WU. WP# on the FWH is
Michael Gold6d52e472009-06-19 13:00:24 +00001784 * connected to GP30 on the Super I/O, and TBL# is always high.
1785 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001786static int board_mitac_6513wu(void)
Michael Gold6d52e472009-06-19 13:00:24 +00001787{
1788 struct pci_dev *dev;
1789 uint16_t rt_port;
1790 uint8_t val;
1791
1792 dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */
1793 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001794 msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00001795 return -1;
1796 }
1797
Uwe Hermann1432a602009-06-28 23:26:37 +00001798 rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa);
Michael Gold6d52e472009-06-19 13:00:24 +00001799 if (rt_port == 0)
1800 return -1;
1801
1802 /* Configure the GPIO pin. */
1803 val = INB(rt_port + 0x33); /* GP30 config */
Uwe Hermann1432a602009-06-28 23:26:37 +00001804 val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */
Michael Gold6d52e472009-06-19 13:00:24 +00001805 OUTB(val, rt_port + 0x33);
1806
1807 /* Disable write protection. */
1808 val = INB(rt_port + 0x4d); /* GP3 values */
Uwe Hermann1432a602009-06-28 23:26:37 +00001809 val |= 0x01; /* Set GP30 high. */
Michael Gold6d52e472009-06-19 13:00:24 +00001810 OUTB(val, rt_port + 0x4d);
1811
1812 return 0;
1813}
1814
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001815/*
1816 * Suited for:
Uwe Hermann45bd1442010-09-14 23:20:35 +00001817 * - ASUS A7V333: VIA KT333 + VT8233A + IT8703F
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001818 * - ASUS A7V8X: VIA KT400 + VT8235 + IT8703F
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001819 */
Uwe Hermann45bd1442010-09-14 23:20:35 +00001820static int it8703f_gpio51_raise(void)
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001821{
1822 uint16_t id, base;
1823 uint8_t tmp;
1824
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001825 /* Find the IT8703F. */
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001826 w836xx_ext_enter(0x2E);
1827 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
1828 w836xx_ext_leave(0x2E);
1829
1830 if (id != 0x8701) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001831 msg_perr("\nERROR: IT8703F Super I/O not found.\n");
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001832 return -1;
1833 }
1834
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001835 /* Get the GP567 I/O base. */
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001836 w836xx_ext_enter(0x2E);
1837 sio_write(0x2E, 0x07, 0x0C);
1838 base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
1839 w836xx_ext_leave(0x2E);
1840
1841 if (!base) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001842 msg_perr("\nERROR: Failed to read IT8703F Super I/O GPIO"
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001843 " Base.\n");
1844 return -1;
1845 }
1846
1847 /* Raise GP51. */
1848 tmp = INB(base);
1849 tmp |= 0x02;
1850 OUTB(tmp, base);
1851
1852 return 0;
1853}
1854
Luc Verhaegen72272912009-09-01 21:22:23 +00001855/*
1856 * General routine for raising/dropping GPIO lines on the ITE IT8712F.
1857 * There is only some limited checking on the port numbers.
1858 */
Uwe Hermann43959702010-03-13 17:28:29 +00001859static int it8712f_gpio_set(unsigned int line, int raise)
Luc Verhaegen72272912009-09-01 21:22:23 +00001860{
1861 unsigned int port;
1862 uint16_t id, base;
1863 uint8_t tmp;
1864
1865 port = line / 10;
1866 port--;
1867 line %= 10;
1868
1869 /* Check line */
1870 if ((port > 4) || /* also catches unsigned -1 */
1871 ((port < 4) && (line > 7)) || ((port == 4) && (line > 5))) {
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001872 msg_perr("\nERROR: Unsupported IT8712F GPIO line %02d.\n", line);
Luc Verhaegen72272912009-09-01 21:22:23 +00001873 return -1;
1874 }
1875
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001876 /* Find the IT8712F. */
Luc Verhaegen72272912009-09-01 21:22:23 +00001877 enter_conf_mode_ite(0x2E);
1878 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
1879 exit_conf_mode_ite(0x2E);
1880
1881 if (id != 0x8712) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001882 msg_perr("\nERROR: IT8712F Super I/O not found.\n");
Luc Verhaegen72272912009-09-01 21:22:23 +00001883 return -1;
1884 }
1885
1886 /* Get the GPIO base */
1887 enter_conf_mode_ite(0x2E);
1888 sio_write(0x2E, 0x07, 0x07);
1889 base = (sio_read(0x2E, 0x62) << 8) | sio_read(0x2E, 0x63);
1890 exit_conf_mode_ite(0x2E);
1891
1892 if (!base) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001893 msg_perr("\nERROR: Failed to read IT8712F Super I/O GPIO"
Luc Verhaegen72272912009-09-01 21:22:23 +00001894 " Base.\n");
1895 return -1;
1896 }
1897
1898 /* set GPIO. */
1899 tmp = INB(base + port);
1900 if (raise)
1901 tmp |= 1 << line;
1902 else
1903 tmp &= ~(1 << line);
1904 OUTB(tmp, base + port);
1905
1906 return 0;
1907}
1908
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001909/*
Russ Dillbd622d12010-03-09 16:57:06 +00001910 * Suited for:
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001911 * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F
1912 * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F
Luc Verhaegen72272912009-09-01 21:22:23 +00001913 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001914static int it8712f_gpio3_1_raise(void)
Luc Verhaegen72272912009-09-01 21:22:23 +00001915{
1916 return it8712f_gpio_set(32, 1);
1917}
1918
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001919#endif
1920
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001921/*
Uwe Hermannd0e347d2009-10-06 13:00:00 +00001922 * Below is the list of boards which need a special "board enable" code in
1923 * flashrom before their ROM chip can be accessed/written to.
1924 *
1925 * NOTE: Please add boards that _don't_ need such enables or don't work yet
1926 * to the respective tables in print.c. Thanks!
1927 *
Uwe Hermannffec5f32007-08-23 16:08:21 +00001928 * We use 2 sets of IDs here, you're free to choose which is which. This
1929 * is to provide a very high degree of certainty when matching a board on
1930 * the basis of subsystem/card IDs. As not every vendor handles
1931 * subsystem/card IDs in a sane manner.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001932 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00001933 * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00001934 * NULLed if they don't identify the board fully and if you can't use DMI.
1935 * But please take care to provide an as complete set of pci ids as possible;
1936 * autodetection is the preferred behaviour and we would like to make sure that
1937 * matches are unique.
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001938 *
Michael Karcher6701ee82010-01-20 14:14:11 +00001939 * If PCI IDs are not sufficient for board matching, the match can be further
1940 * constrained by a string that has to be present in the DMI database for
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001941 * the baseboard or the system entry. The pattern is matched by case sensitive
Michael Karcher6701ee82010-01-20 14:14:11 +00001942 * substring match, unless it is anchored to the beginning (with a ^ in front)
1943 * or the end (with a $ at the end). Both anchors may be specified at the
1944 * same time to match the full field.
1945 *
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00001946 * When a board is matched through DMI, the first and second main PCI IDs
1947 * and the first subsystem PCI ID have to match as well. If you specify the
1948 * first subsystem ID as 0x0:0x0, the DMI matching code expects that the
1949 * subsystem ID of that device is indeed zero.
1950 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00001951 * The coreboot ids are used two fold. When running with a coreboot firmware,
1952 * the ids uniquely matches the coreboot board identification string. When a
1953 * legacy bios is installed and when autodetection is not possible, these ids
1954 * can be used to identify the board through the -m command line argument.
1955 *
1956 * When a board is identified through its coreboot ids (in both cases), the
1957 * main pci ids are still required to match, as a safeguard.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001958 */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001959
Uwe Hermanndeeebe22009-05-08 16:23:34 +00001960/* Please keep this list alphabetically ordered by vendor/board name. */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00001961const struct board_pciid_enable board_pciid_enables[] = {
Uwe Hermann5ab88892009-06-21 20:50:22 +00001962
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00001963 /* first pci-id set [4], second pci-id set [4], dmi identifier, coreboot id [2], phase, vendor name, board name max_rom_... OK? flash enable */
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001964#if defined(__i386__) || defined(__x86_64__)
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00001965 {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, P3, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise},
1966 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^i440BX-W977 (BM6)$", NULL, NULL, P3, "abit", "BM6", 0, OK, intel_piix4_gpo26_lower},
1967 {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, P3, "abit", "IC7", 0, NT, intel_ich_gpio23_raise},
1968 {0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, P3, "abit", "IP35", 0, OK, intel_ich_gpio16_raise},
1969 {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, P3, "abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise},
1970 {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, P3, "abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower},
1971 {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, P3, "abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise},
Antony Rheneus0fbba982011-05-26 14:28:51 +00001972 {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0240, 0x10de, 0x0222, NULL, NULL, NULL, P3, "abit", "NF-M2 nView", 0, OK, nvidia_mcp_gpio4_lower},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00001973 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, "(VA6)$", NULL, NULL, P3, "abit", "VA6", 0, OK, via_apollo_gpo4_lower},
1974 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", P3, "abit", "VT6X4", 0, OK, via_apollo_gpo4_lower},
1975 {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, P3, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd},
1976 {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", P3, "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e},
1977 {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, P3, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e},
1978 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", P3, "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x},
1979 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", P3, "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x},
Joshua Roys7225ccd2011-05-18 01:32:16 +00001980 {0x8086, 0x277c, 0xa0a0, 0x060b, 0x8086, 0x27da, 0xa0a0, 0x060b, NULL, NULL, NULL, P3, "AOpen", "i975Xa-YDG", 0, OK, board_aopen_i975xa_ydg},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00001981 {0x1039, 0x0741, 0x1849, 0x0741, 0x1039, 0x5513, 0x1849, 0x5513, "^K7S41 $", NULL, NULL, P3, "ASRock", "K7S41", 0, OK, w836xx_memw_enable_2e},
1982 {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, P3, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise},
1983 {0x8086, 0x2570, 0x1849, 0x2570, 0x8086, 0x24d3, 0x1849, 0x24d0, NULL, NULL, NULL, P3, "ASRock", "775i65G", 0, OK, intel_ich_gpio23_raise},
1984 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, P3, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise},
1985 {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, P3, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e},
1986 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V8X", 0, OK, it8703f_gpio51_raise},
1987 {0x1106, 0x3099, 0x1043, 0x807F, 0x1106, 0x3147, 0x1043, 0x808C, NULL, NULL, NULL, P3, "ASUS", "A7V333", 0, OK, it8703f_gpio51_raise},
1988 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, P3, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise},
Stefan Taunerf0bcfa52011-05-17 13:31:55 +00001989 {0x1002, 0x4372, 0x103c, 0x2a26, 0x1002, 0x4377, 0x103c, 0x2a26, NULL, NULL, NULL, P3, "ASUS", "A8AE-LE", 0, OK, amd_sbxxx_gpio9_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00001990 {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, P3, "ASUS", "A8Jm", 0, NT, intel_ich_gpio34_raise},
1991 {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L", NULL, NULL, P3, "ASUS", "A8N-LA (Nagami-GL8E)", 0, OK, nvidia_mcp_gpio0_raise},
Stefan Taunerd06d9412011-06-12 19:47:55 +00001992 {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, "^A8N-SLI", NULL, NULL, P3, "ASUS", "A8N-SLI Deluxe", 0, NT, board_shuttle_fn25},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00001993 {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, P3, "ASUS", "A8N-VM CSM", 0, NT, w83627ehf_gpio24_raise_2e},
1994 {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, P3, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise},
1995 {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, P3, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise},
1996 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^P2B-N$", NULL, NULL, P3, "ASUS", "P2B-N", 0, OK, intel_piix4_gpo18_lower},
1997 {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, P3, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise},
1998 {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, P3, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise},
1999 {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, P3, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise},
2000 {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, P3, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
2001 {0x8086, 0x2570, 0x1043, 0x80F2, 0x8086, 0x24D5, 0x1043, 0x80F3, NULL, NULL, NULL, P3, "ASUS", "P4P800", 0, NT, intel_ich_gpio21_raise},
2002 {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, P3, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
2003 {0x8086, 0x2570, 0x1043, 0x80A5, 0x8086, 0x24d0, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4P800-VM", 0, OK, intel_ich_gpio21_raise},
2004 {0x1039, 0x0651, 0x1043, 0x8081, 0x1039, 0x0962, 0, 0, NULL, NULL, NULL, P3, "ASUS", "P4SC-E", 0, OK, it8707f_write_enable_2e},
2005 {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, P3, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise},
2006 {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, P3, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e},
2007 {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", P3, "ASUS", "P5A", 0, OK, board_asus_p5a},
2008 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x814e, NULL, NULL, NULL, P3, "ASUS", "P5GD1 Pro", 0, OK, intel_ich_gpio21_raise},
2009 {0x8086, 0x266a, 0x1043, 0x80a6, 0x8086, 0x2668, 0x1043, 0x813d, NULL, NULL, NULL, P3, "ASUS", "P5GDC Deluxe", 0, OK, intel_ich_gpio21_raise},
2010 {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, P3, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise},
2011 {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, P3, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise},
2012 {0x10b7, 0x9055, 0x1028, 0x0082, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Dell", "OptiPlex GX1", 0, OK, intel_piix4_gpo30_lower},
2013 {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, P3, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise},
2014 {0x10de, 0x03ea, 0x1019, 0x2602, 0x10de, 0x03e0, 0x1019, 0x2602, NULL, NULL, NULL, P3, "Elitegroup", "GeForce6100SM-M", 0, OK, board_ecs_geforce6100sm_m},
2015 {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, P3, "Elitegroup", "K7VTA3", 256, OK, NULL},
2016 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, P3, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e},
2017 {0x10DE, 0x005E, 0x1695, 0x1010, 0x10DE, 0x0050, 0x1695, 0x1010, NULL, NULL, NULL, P3, "EPoX", "EP-8NPA7I", 0, OK, nvidia_mcp_gpio4_raise},
2018 {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, P3, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise},
2019 {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", P3, "EPoX", "EP-BX3", 0, NT, intel_piix4_gpo22_raise},
2020 {0x10de, 0x02f0, 0x105b, 0x0d01, 0x10de, 0x0264, 0x105b, 0x0d01, NULL, NULL, NULL, P3, "Foxconn", "6150K8MD-8EKRSH", 0, NT, nvidia_mcp_gpio2_raise},
2021 {0x8086, 0x2443, 0x8086, 0x2442, 0x8086, 0x1130, 0x8086, 0x1130, "^6IEM ", NULL, NULL, P3, "GIGABYTE", "GA-6IEM", 0, NT, intel_ich_gpio25_raise},
2022 {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-7ZM", 512, OK, NULL},
2023 {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise},
2024 {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, P3, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise},
2025 {0x10DE, 0x02F1, 0x1458, 0x5000, 0x10DE, 0x0261, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF", 0, OK, nvidia_mcp_gpio3b_raise},
2026 {0x10DE, 0x026C, 0x1458, 0xA102, 0x10DE, 0x0260, 0x1458, 0x5001, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N51GMF-9", 0, OK, nvidia_mcp_gpio3b_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002027 {0x10de, 0x00e4, 0x1458, 0x0c11, 0x10de, 0x00e0, 0x1458, 0x0c11, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8NS Pro-939", 0, NT, nvidia_mcp_gpio0a_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002028 {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, P3, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002029 {0x8086, 0x2415, 0x103c, 0x1250, 0x10b7, 0x9200, 0x103c, 0x1247, NULL, NULL, NULL, P3, "HP", "e-Vectra P2706T", 0, OK, board_hp_p2706t},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002030 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", P3, "HP", "ProLiant DL145 G3", 0, OK, board_hp_dl145_g3_enable},
2031 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", P3, "HP", "ProLiant DL165 G6", 0, OK, board_hp_dl165_g6_enable},
2032 {0x8086, 0x2580, 0x103c, 0x2a08, 0x8086, 0x2640, 0x103c, 0x2a0a, NULL, NULL, NULL, P3, "HP", "Puffer2-UL8E", 0, OK, intel_ich_gpio18_raise},
Idwer Volleringd8a00a02011-06-13 16:58:54 +00002033 {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, P3, "HP", "Vectra VL400", 0, OK, board_hp_vl400},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002034 {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, P3, "HP", "Vectra VL420 SFF", 0, OK, intel_ich_gpio22_raise},
2035 {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, "hp", "xw9400", P3, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise},
2036 {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", P3, "IBASE", "MB899", 0, OK, intel_ich_gpio26_raise},
2037 {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, P3, "IBM", "x3455", 0, OK, board_ibm_x3455},
2038 {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, P3, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi},
2039 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, P3, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower},
2040 {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", P3, "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e},
2041 {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", P3, "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m},
2042 {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, P3, "Mitac", "6513WU", 0, OK, board_mitac_6513wu},
2043 {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, P3, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise}, /* TODO: Should probably be K8N Neo4 Platinum, see http://www.coreboot.org/pipermail/flashrom/2010-August/004362.html. */
2044 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^MS-6163 (i440BX)$", NULL, NULL, P3, "MSI", "MS-6163 (MS-6163 Pro)", 0, OK, intel_piix4_gpo14_raise},
2045 {0x1039, 0x0745, 0, 0, 0x1039, 0x0018, 0, 0, "^MS-6561", NULL, NULL, P3, "MSI", "MS-6561 (745 Ultra)", 0, OK, w836xx_memw_enable_2e},
2046 {0x8086, 0x2560, 0x1462, 0x5770, 0x8086, 0x2562, 0x1462, 0x5778, NULL, NULL, NULL, P3, "MSI", "MS-6577 (Xenon)", 0, OK, w83627hf_gpio25_raise_2e},
2047 {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, P3, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v},
2048 {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, P3, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio44_raise_2e},
2049 {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, P3, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v},
2050 {0x1106, 0x3148, 0 , 0 , 0x1106, 0x3177, 0 , 0 , NULL, "msi", "ms6787", P3, "MSI", "MS-6787 (P4MAM-V/P4MAM-L)", 0, OK, w836xx_memw_enable_2e},
Maciej Pijanka6add0942011-06-09 20:59:30 +00002051 {0x8086, 0x24d3, 0x1462, 0x7880, 0x8086, 0x2570, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-6788-040 (848P NeoV)", 0, OK, intel_ich_gpio32_raise},
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002052 {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, P3, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml},
2053 {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, P3, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise},
2054 {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, P3, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise},
2055 {0x8086, 0x244b, 0x1462, 0x3910, 0x8086, 0x2442, 0x1462, 0x3910, NULL, NULL, NULL, P3, "MSI", "MS-6391 (845 Pro4)", 0, OK, intel_ich_gpio23_raise},
2056 {0x1106, 0x3149, 0x1462, 0x7061, 0x1106, 0x3227, 0, 0, NULL, NULL, NULL, P3, "MSI", "MS-7061 (KM4M-V/KM4AM-V)", 0, OK, w836xx_memw_enable_2e},
2057 {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", P3, "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio44_raise_4e},
2058 {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, P3, "MSI", "MS-7207 (K8NGM2-L)", 0, NT, nvidia_mcp_gpio2_raise},
2059 {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, P3, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0},
2060 {0x8086, 0x24d3, 0x144d, 0xb025, 0x8086, 0x1050, 0x144d, 0xb025, NULL, NULL, NULL, P3, "Samsung", "Polaris 32", 0, OK, intel_ich_gpio21_raise},
2061 {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", P3, "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e},
2062 {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, P3, "Shuttle", "AK38N", 256, OK, NULL},
2063 {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, P3, "Shuttle", "FN25", 0, OK, board_shuttle_fn25},
2064 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, P3, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower},
2065 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, P3, "Tekram", "P6Pro-A5", 256, OK, NULL},
2066 {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, P3, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e},
2067 {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, P3, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e},
2068 {0x1106, 0x0259, 0x1106, 0xAA07, 0x1106, 0x3227, 0x1106, 0xAA07, NULL, NULL, NULL, P3, "VIA", "EPIA EK", 0, NT, via_vt823x_gpio9_raise},
2069 {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, P3, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise},
2070 {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, P3, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise},
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00002071#endif
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002072 { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, P3, NULL, NULL, 0, NT, NULL}, /* end marker */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002073};
2074
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002075/*
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00002076 * Match boards on coreboot table gathered vendor and part name.
Uwe Hermannffec5f32007-08-23 16:08:21 +00002077 * Require main PCI IDs to match too as extra safety.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002078 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00002079static const struct board_pciid_enable *board_match_coreboot_name(const char *vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00002080 const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002081{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00002082 const struct board_pciid_enable *board = board_pciid_enables;
2083 const struct board_pciid_enable *partmatch = NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002084
Uwe Hermanna93045c2009-05-09 00:47:04 +00002085 for (; board->vendor_name; board++) {
Uwe Hermann394131e2008-10-18 21:14:13 +00002086 if (vendor && (!board->lb_vendor
2087 || strcasecmp(board->lb_vendor, vendor)))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002088 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002089
Peter Stuge0b9c5f32008-07-02 00:47:30 +00002090 if (!board->lb_part || strcasecmp(board->lb_part, part))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002091 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002092
Uwe Hermanna7e05482007-05-09 10:17:44 +00002093 if (!pci_dev_find(board->first_vendor, board->first_device))
2094 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002095
Uwe Hermanna7e05482007-05-09 10:17:44 +00002096 if (board->second_vendor &&
Uwe Hermann394131e2008-10-18 21:14:13 +00002097 !pci_dev_find(board->second_vendor, board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002098 continue;
Peter Stuge6b53fed2008-01-27 16:21:21 +00002099
2100 if (vendor)
2101 return board;
2102
2103 if (partmatch) {
2104 /* a second entry has a matching part name */
Sean Nelson316a29f2010-05-07 20:09:04 +00002105 msg_pinfo("AMBIGUOUS BOARD NAME: %s\n", part);
2106 msg_pinfo("At least vendors '%s' and '%s' match.\n",
Uwe Hermann394131e2008-10-18 21:14:13 +00002107 partmatch->lb_vendor, board->lb_vendor);
Sean Nelson316a29f2010-05-07 20:09:04 +00002108 msg_perr("Please use the full -m vendor:part syntax.\n");
Peter Stuge6b53fed2008-01-27 16:21:21 +00002109 return NULL;
2110 }
2111 partmatch = board;
Uwe Hermanna7e05482007-05-09 10:17:44 +00002112 }
Uwe Hermann372eeb52007-12-04 21:49:06 +00002113
Peter Stuge6b53fed2008-01-27 16:21:21 +00002114 if (partmatch)
2115 return partmatch;
2116
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00002117 if (!partvendor_from_cbtable) {
2118 /* Only warn if the mainboard type was not gathered from the
2119 * coreboot table. If it was, the coreboot implementor is
2120 * expected to fix flashrom, too.
2121 */
Sean Nelson316a29f2010-05-07 20:09:04 +00002122 msg_perr("\nUnknown vendor:board from -m option: %s:%s\n\n",
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00002123 vendor, part);
2124 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00002125 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002126}
2127
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002128/*
Uwe Hermannffec5f32007-08-23 16:08:21 +00002129 * Match boards on PCI IDs and subsystem IDs.
2130 * Second set of IDs can be main only or missing completely.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002131 */
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002132const static struct board_pciid_enable *board_match_pci_card_ids(enum board_match_phase phase)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002133{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00002134 const struct board_pciid_enable *board = board_pciid_enables;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002135
Uwe Hermanna93045c2009-05-09 00:47:04 +00002136 for (; board->vendor_name; board++) {
Michael Karcher2eab70d2010-02-04 10:58:50 +00002137 if ((!board->first_card_vendor || !board->first_card_device) &&
2138 !board->dmi_pattern)
Uwe Hermanna7e05482007-05-09 10:17:44 +00002139 continue;
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002140 if (board->phase != phase)
2141 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002142
Uwe Hermanna7e05482007-05-09 10:17:44 +00002143 if (!pci_card_find(board->first_vendor, board->first_device,
Uwe Hermann394131e2008-10-18 21:14:13 +00002144 board->first_card_vendor,
2145 board->first_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002146 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002147
Uwe Hermanna7e05482007-05-09 10:17:44 +00002148 if (board->second_vendor) {
2149 if (board->second_card_vendor) {
2150 if (!pci_card_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00002151 board->second_device,
2152 board->second_card_vendor,
2153 board->second_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002154 continue;
2155 } else {
2156 if (!pci_dev_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00002157 board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00002158 continue;
2159 }
2160 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002161
Michael Karcher6701ee82010-01-20 14:14:11 +00002162 if (board->dmi_pattern) {
2163 if (!has_dmi_support) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002164 msg_perr("WARNING: Can't autodetect %s %s,"
Michael Karcher6701ee82010-01-20 14:14:11 +00002165 " DMI info unavailable.\n",
2166 board->vendor_name, board->board_name);
2167 continue;
2168 } else {
2169 if (!dmi_match(board->dmi_pattern))
2170 continue;
2171 }
2172 }
2173
Uwe Hermanna7e05482007-05-09 10:17:44 +00002174 return board;
2175 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002176
Uwe Hermanna7e05482007-05-09 10:17:44 +00002177 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002178}
2179
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002180static int unsafe_board_handler(const struct board_pciid_enable *board)
2181{
2182 if (!board)
2183 return 1;
2184
2185 if (board->status == OK)
2186 return 0;
2187
2188 if (!force_boardenable) {
2189 msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n"
Stefan Tauner9df880f2011-05-17 23:30:13 +00002190 "code has not been tested, and thus will not be executed by default.\n"
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002191 "Depending on your hardware environment, erasing, writing or even probing\n"
2192 "can fail without running the board specific code.\n\n"
2193 "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n"
2194 "\"internal programmer\") for details.\n",
2195 board->vendor_name, board->board_name);
2196 return 1;
2197 }
2198 msg_pinfo("NOTE: Running an untested board enable procedure.\n"
2199 "Please report success/failure to flashrom@flashrom.org\n"
2200 "with your board name and SUCCESS or FAILURE in the subject.\n");
2201 return 0;
2202}
2203
2204/* FIXME: Should this be identical to board_flash_enable? */
2205static int board_handle_phase(enum board_match_phase phase)
2206{
2207 const struct board_pciid_enable *board = NULL;
2208
2209 board = board_match_pci_card_ids(phase);
2210
2211 if (unsafe_board_handler(board))
2212 board = NULL;
2213
2214 if (!board)
2215 return 0;
2216
2217 if (!board->enable) {
2218 /* Not sure if there is a valid case for this. */
2219 msg_perr("Board match found, but nothing to do?\n");
2220 return 0;
2221 }
2222
2223 return board->enable();
2224}
2225
2226void board_handle_before_superio(void)
2227{
2228 board_handle_phase(P1);
2229}
2230
2231void board_handle_before_laptop(void)
2232{
2233 board_handle_phase(P2);
2234}
2235
Uwe Hermann372eeb52007-12-04 21:49:06 +00002236int board_flash_enable(const char *vendor, const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002237{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00002238 const struct board_pciid_enable *board = NULL;
Uwe Hermanna7e05482007-05-09 10:17:44 +00002239 int ret = 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002240
Peter Stuge6b53fed2008-01-27 16:21:21 +00002241 if (part)
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00002242 board = board_match_coreboot_name(vendor, part);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002243
Uwe Hermanna7e05482007-05-09 10:17:44 +00002244 if (!board)
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002245 board = board_match_pci_card_ids(P3);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002246
Carl-Daniel Hailfinger580d29a2011-05-05 07:12:40 +00002247 if (unsafe_board_handler(board))
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002248 board = NULL;
Michael Karcher7f0c3ec2010-03-07 22:29:28 +00002249
Uwe Hermanna7e05482007-05-09 10:17:44 +00002250 if (board) {
Luc Verhaegen93938c32010-01-20 14:45:03 +00002251 if (board->max_rom_decode_parallel)
2252 max_rom_decode.parallel =
2253 board->max_rom_decode_parallel * 1024;
2254
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00002255 if (board->enable != NULL) {
Sean Nelson316a29f2010-05-07 20:09:04 +00002256 msg_pinfo("Disabling flash write protection for "
Uwe Hermann48ec1b12010-08-08 17:01:18 +00002257 "board \"%s %s\"... ", board->vendor_name,
2258 board->board_name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002259
Uwe Hermann36dec8b2010-06-07 19:06:26 +00002260 ret = board->enable();
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00002261 if (ret)
Sean Nelson316a29f2010-05-07 20:09:04 +00002262 msg_pinfo("FAILED!\n");
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00002263 else
Sean Nelson316a29f2010-05-07 20:09:04 +00002264 msg_pinfo("OK.\n");
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00002265 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00002266 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002267
Uwe Hermanna7e05482007-05-09 10:17:44 +00002268 return ret;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00002269}