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Ollie Lho184a4042005-11-26 21:55:36 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ollie Lho184a4042005-11-26 21:55:36 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Stefan Reinauer8fa64812009-08-12 09:27:45 +00005 * Copyright (C) 2005-2009 coresystems GmbH
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00007 * Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger
Adam Jurkowskie4984102009-12-21 15:30:46 +00008 * Copyright (C) 2009 Kontron Modular Computers GmbH
Helge Wagnerdd73d832012-08-24 23:03:46 +00009 * Copyright (C) 2011, 2012 Stefan Tauner
Nico Huber93c30692017-03-20 14:25:09 +010010 * Copyright (C) 2017 secunet Security Networks AG
11 * (Written by Nico Huber <nico.huber@secunet.com> for secunet)
Ollie Lho184a4042005-11-26 21:55:36 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
Ollie Lho184a4042005-11-26 21:55:36 +000016 *
Uwe Hermannd1107642007-08-29 17:52:32 +000017 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
Uwe Hermannd1107642007-08-29 17:52:32 +000021 */
22
23/*
24 * Contains the chipset specific flash enables.
Ollie Lho184a4042005-11-26 21:55:36 +000025 */
26
Lane Brooksd54958a2007-11-13 16:45:22 +000027#define _LARGEFILE64_SOURCE
28
Ollie Lhocbbf1252004-03-17 22:22:08 +000029#include <stdlib.h>
Uwe Hermanne8ba5382009-05-22 11:37:27 +000030#include <string.h>
Carl-Daniel Hailfingerdcef67e2010-06-21 23:20:15 +000031#include <unistd.h>
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +000032#include <inttypes.h>
33#include <errno.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000034#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000035#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000036#include "hwaccess.h"
Stefan Reinauer86de2832006-03-31 11:26:55 +000037
Michael Karcher89bed6d2010-06-13 10:16:12 +000038#define NOT_DONE_YET 1
39
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +000040#if defined(__i386__) || defined(__x86_64__)
41
Uwe Hermann372eeb52007-12-04 21:49:06 +000042static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
Luc Verhaegen6b141752007-05-20 16:16:13 +000043{
44 uint8_t tmp;
45
Uwe Hermann372eeb52007-12-04 21:49:06 +000046 /*
47 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
48 * 0xFFFE0000-0xFFFFFFFF ROM select enable.
49 */
Luc Verhaegen6b141752007-05-20 16:16:13 +000050 tmp = pci_read_byte(dev, 0x47);
51 tmp |= 0x46;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000052 rpci_write_byte(dev, 0x47, tmp);
Luc Verhaegen6b141752007-05-20 16:16:13 +000053
54 return 0;
55}
56
Rudolf Marek23907d82012-02-07 21:29:48 +000057static int enable_flash_rdc_r8610(struct pci_dev *dev, const char *name)
58{
59 uint8_t tmp;
60
61 /* enable ROMCS for writes */
62 tmp = pci_read_byte(dev, 0x43);
63 tmp |= 0x80;
64 pci_write_byte(dev, 0x43, tmp);
65
66 /* read the bootstrapping register */
67 tmp = pci_read_byte(dev, 0x40) & 0x3;
68 switch (tmp) {
69 case 3:
70 internal_buses_supported = BUS_FWH;
71 break;
72 case 2:
73 internal_buses_supported = BUS_LPC;
74 break;
75 default:
76 internal_buses_supported = BUS_PARALLEL;
77 break;
78 }
79
80 return 0;
81}
82
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000083static int enable_flash_sis85c496(struct pci_dev *dev, const char *name)
84{
85 uint8_t tmp;
86
87 tmp = pci_read_byte(dev, 0xd0);
88 tmp |= 0xf8;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000089 rpci_write_byte(dev, 0xd0, tmp);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000090
91 return 0;
92}
93
94static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name)
95{
Stefan Taunere34e3e82013-01-01 00:06:51 +000096 #define SIS_MAPREG 0x40
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000097 uint8_t new, newer;
98
99 /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
100 /* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
Stefan Taunere34e3e82013-01-01 00:06:51 +0000101 new = pci_read_byte(dev, SIS_MAPREG);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000102 new &= (~0x04); /* No idea why we clear bit 2. */
103 new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */
Stefan Taunere34e3e82013-01-01 00:06:51 +0000104 rpci_write_byte(dev, SIS_MAPREG, new);
105 newer = pci_read_byte(dev, SIS_MAPREG);
106 if (newer != new) { /* FIXME: share this with other code? */
107 msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
108 SIS_MAPREG, new, name);
109 msg_pinfo("Stuck at 0x%02x.\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000110 return -1;
111 }
112 return 0;
113}
114
115static struct pci_dev *find_southbridge(uint16_t vendor, const char *name)
116{
117 struct pci_dev *sbdev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000118
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000119 sbdev = pci_dev_find_vendorclass(vendor, 0x0601);
120 if (!sbdev)
121 sbdev = pci_dev_find_vendorclass(vendor, 0x0680);
122 if (!sbdev)
123 sbdev = pci_dev_find_vendorclass(vendor, 0x0000);
124 if (!sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +0000125 msg_perr("No southbridge found for %s!\n", name);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000126 if (sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +0000127 msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000128 sbdev->vendor_id, sbdev->device_id,
129 sbdev->bus, sbdev->dev, sbdev->func);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000130 return sbdev;
131}
132
133static int enable_flash_sis501(struct pci_dev *dev, const char *name)
134{
135 uint8_t tmp;
136 int ret = 0;
137 struct pci_dev *sbdev;
138
139 sbdev = find_southbridge(dev->vendor_id, name);
140 if (!sbdev)
141 return -1;
142
143 ret = enable_flash_sis_mapping(sbdev, name);
144
145 tmp = sio_read(0x22, 0x80);
146 tmp &= (~0x20);
147 tmp |= 0x4;
148 sio_write(0x22, 0x80, tmp);
149
150 tmp = sio_read(0x22, 0x70);
151 tmp &= (~0x20);
152 tmp |= 0x4;
153 sio_write(0x22, 0x70, tmp);
154
155 return ret;
156}
157
158static int enable_flash_sis5511(struct pci_dev *dev, const char *name)
159{
160 uint8_t tmp;
161 int ret = 0;
162 struct pci_dev *sbdev;
163
164 sbdev = find_southbridge(dev->vendor_id, name);
165 if (!sbdev)
166 return -1;
167
168 ret = enable_flash_sis_mapping(sbdev, name);
169
170 tmp = sio_read(0x22, 0x50);
171 tmp &= (~0x20);
172 tmp |= 0x4;
173 sio_write(0x22, 0x50, tmp);
174
175 return ret;
176}
177
Stefan Taunere34e3e82013-01-01 00:06:51 +0000178static int enable_flash_sis5x0(struct pci_dev *dev, const char *name, uint8_t dis_mask, uint8_t en_mask)
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000179{
Stefan Taunere34e3e82013-01-01 00:06:51 +0000180 #define SIS_REG 0x45
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000181 uint8_t new, newer;
182 int ret = 0;
183 struct pci_dev *sbdev;
184
185 sbdev = find_southbridge(dev->vendor_id, name);
186 if (!sbdev)
187 return -1;
188
189 ret = enable_flash_sis_mapping(sbdev, name);
190
Stefan Taunere34e3e82013-01-01 00:06:51 +0000191 new = pci_read_byte(sbdev, SIS_REG);
192 new &= (~dis_mask);
193 new |= en_mask;
194 rpci_write_byte(sbdev, SIS_REG, new);
195 newer = pci_read_byte(sbdev, SIS_REG);
196 if (newer != new) { /* FIXME: share this with other code? */
197 msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", SIS_REG, new, name);
198 msg_pinfo("Stuck at 0x%02x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000199 ret = -1;
200 }
201
202 return ret;
203}
204
Stefan Taunere34e3e82013-01-01 00:06:51 +0000205static int enable_flash_sis530(struct pci_dev *dev, const char *name)
206{
207 return enable_flash_sis5x0(dev, name, 0x20, 0x04);
208}
209
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000210static int enable_flash_sis540(struct pci_dev *dev, const char *name)
211{
Stefan Taunere34e3e82013-01-01 00:06:51 +0000212 return enable_flash_sis5x0(dev, name, 0x80, 0x40);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000213}
214
Uwe Hermann987942d2006-11-07 11:16:21 +0000215/* Datasheet:
216 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
217 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
218 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
219 * - Order Number: 290562-001
220 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000221static int enable_flash_piix4(struct pci_dev *dev, const char *name)
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000222{
223 uint16_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000224 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000225
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000226 internal_buses_supported = BUS_PARALLEL;
Maciej Pijankaa661e152009-12-08 17:26:24 +0000227
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000228 old = pci_read_word(dev, xbcs);
229
230 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
Uwe Hermanna7e05482007-05-09 10:17:44 +0000231 * FFF00000-FFF7FFFF are forwarded to ISA).
Uwe Hermannc556d322008-10-28 11:50:05 +0000232 * Note: This bit is reserved on PIIX/PIIX3/MPIIX.
Uwe Hermanna7e05482007-05-09 10:17:44 +0000233 * Set bit 7: Extended BIOS Enable (PCI master accesses to
234 * FFF80000-FFFDFFFF are forwarded to ISA).
235 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
236 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
237 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
238 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
239 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
240 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
241 */
Uwe Hermannc556d322008-10-28 11:50:05 +0000242 if (dev->device_id == 0x122e || dev->device_id == 0x7000
243 || dev->device_id == 0x1234)
244 new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
Uwe Hermann87203452008-10-26 18:40:42 +0000245 else
246 new = old | 0x02c4;
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000247
248 if (new == old)
249 return 0;
250
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000251 rpci_write_word(dev, xbcs, new);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000252
Stefan Taunere34e3e82013-01-01 00:06:51 +0000253 if (pci_read_word(dev, xbcs) != new) { /* FIXME: share this with other code? */
254 msg_pinfo("Setting register 0x%04x to 0x%04x on %s failed (WARNING ONLY).\n", xbcs, new, name);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000255 return -1;
256 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000257
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000258 return 0;
259}
260
Duncan Laurie4095ed72014-08-20 15:39:32 +0000261/* Handle BIOS_CNTL (aka. BCR). Disable locks and enable writes. The register can either be in PCI config space
262 * at the offset given by 'bios_cntl' or at the memory-mapped address 'addr'.
263 *
264 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, in Poulsbo, Tunnel Creek and other Atom
Stefan Tauner92d6a862013-10-25 00:33:37 +0000265 * chipsets/SoCs it is even 32b, but just treating it as 8 bit wide seems to work fine in practice. */
Duncan Laurie4095ed72014-08-20 15:39:32 +0000266static int enable_flash_ich_bios_cntl_common(enum ich_chipset ich_generation, void *addr,
267 struct pci_dev *dev, uint8_t bios_cntl)
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000268{
Stefan Taunerd5c4ab42011-09-09 12:46:32 +0000269 uint8_t old, new, wanted;
Stefan Reinauereb366472006-09-06 15:48:48 +0000270
Stefan Tauner92d6a862013-10-25 00:33:37 +0000271 switch (ich_generation) {
272 case CHIPSET_ICH_UNKNOWN:
273 return ERROR_FATAL;
274 /* Non-SPI-capable */
275 case CHIPSET_ICH:
276 case CHIPSET_ICH2345:
277 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000278 /* Some Atom chipsets are special: The second byte of BIOS_CNTL (D9h) contains a prefetch bit similar to
279 * what other SPI-capable chipsets have at DCh. Others like Bay Trail use a memmapped register.
Stefan Tauner92d6a862013-10-25 00:33:37 +0000280 * The Tunnel Creek datasheet contains a lot of details about the SPI controller, among other things it
281 * mentions that the prefetching and caching does only happen for direct memory reads.
282 * Therefore - at least for Tunnel Creek - it should not matter to flashrom because we use the
283 * programmed access only and not memory mapping. */
284 case CHIPSET_TUNNEL_CREEK:
285 case CHIPSET_POULSBO:
286 case CHIPSET_CENTERTON:
287 old = pci_read_byte(dev, bios_cntl + 1);
288 msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis");
289 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000290 case CHIPSET_BAYTRAIL:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000291 case CHIPSET_ICH7:
292 default: /* Future version might behave the same */
Duncan Laurie4095ed72014-08-20 15:39:32 +0000293 if (ich_generation == CHIPSET_BAYTRAIL)
294 old = (mmio_readl(addr) >> 2) & 0x3;
295 else
296 old = (pci_read_byte(dev, bios_cntl) >> 2) & 0x3;
Stefan Tauner92d6a862013-10-25 00:33:37 +0000297 msg_pdbg("SPI Read Configuration: ");
298 if (old == 3)
299 msg_pdbg("invalid prefetching/caching settings, ");
300 else
301 msg_pdbg("prefetching %sabled, caching %sabled, ",
302 (old & 0x2) ? "en" : "dis",
303 (old & 0x1) ? "dis" : "en");
304 }
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000305
Duncan Laurie4095ed72014-08-20 15:39:32 +0000306 if (ich_generation == CHIPSET_BAYTRAIL)
307 wanted = old = mmio_readl(addr);
308 else
309 wanted = old = pci_read_byte(dev, bios_cntl);
310
Stefan Taunerf9a8da52011-06-11 18:16:50 +0000311 /*
312 * Quote from the 6 Series datasheet (Document Number: 324645-004):
313 * "Bit 5: SMM BIOS Write Protect Disable (SMM_BWP)
314 * 1 = BIOS region SMM protection is enabled.
315 * The BIOS Region is not writable unless all processors are in SMM."
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000316 * In earlier chipsets this bit is reserved.
Stefan Reinauer62218c32012-08-26 02:35:13 +0000317 *
318 * Try to unset it in any case.
319 * It won't hurt and makes sense in some cases according to Stefan Reinauer.
Stefan Tauner92d6a862013-10-25 00:33:37 +0000320 *
321 * At least in Centerton aforementioned bit is located at bit 7. It is unspecified in all other Atom
322 * and Desktop chipsets before Ibex Peak/5 Series, but we reset bit 5 anyway.
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000323 */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000324 int smm_bwp_bit;
325 if (ich_generation == CHIPSET_CENTERTON)
326 smm_bwp_bit = 7;
327 else
328 smm_bwp_bit = 5;
329 wanted &= ~(1 << smm_bwp_bit);
Stefan Reinauer62218c32012-08-26 02:35:13 +0000330
Stefan Tauner92d6a862013-10-25 00:33:37 +0000331 /* Tunnel Creek has a cache disable at bit 2 of the lowest BIOS_CNTL byte. */
332 if (ich_generation == CHIPSET_TUNNEL_CREEK)
333 wanted |= (1 << 2);
334
335 wanted |= (1 << 0); /* Set BIOS Write Enable */
336 wanted &= ~(1 << 1); /* Disable lock (futile) */
Stefan Reinauer62218c32012-08-26 02:35:13 +0000337
338 /* Only write the register if it's necessary */
339 if (wanted != old) {
Duncan Laurie4095ed72014-08-20 15:39:32 +0000340 if (ich_generation == CHIPSET_BAYTRAIL) {
341 rmmio_writel(wanted, addr);
342 new = mmio_readl(addr);
343 } else {
344 rpci_write_byte(dev, bios_cntl, wanted);
345 new = pci_read_byte(dev, bios_cntl);
346 }
Stefan Reinauer62218c32012-08-26 02:35:13 +0000347 } else
348 new = old;
349
350 msg_pdbg("\nBIOS_CNTL = 0x%02x: ", new);
351 msg_pdbg("BIOS Lock Enable: %sabled, ", (new & (1 << 1)) ? "en" : "dis");
352 msg_pdbg("BIOS Write Enable: %sabled\n", (new & (1 << 0)) ? "en" : "dis");
Stefan Tauner92d6a862013-10-25 00:33:37 +0000353 if (new & (1 << smm_bwp_bit))
Stefan Taunerc6fa32d2013-01-04 22:54:07 +0000354 msg_pwarn("Warning: BIOS region SMM protection is enabled!\n");
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000355
Stefan Reinauer62218c32012-08-26 02:35:13 +0000356 if (new != wanted)
Stefan Tauner92d6a862013-10-25 00:33:37 +0000357 msg_pwarn("Warning: Setting Bios Control at 0x%x from 0x%02x to 0x%02x failed.\n"
358 "New value is 0x%02x.\n", bios_cntl, old, wanted, new);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000359
Stefan Tauner92d6a862013-10-25 00:33:37 +0000360 /* Return an error if we could not set the write enable only. */
Stefan Reinauer62218c32012-08-26 02:35:13 +0000361 if (!(new & (1 << 0)))
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000362 return -1;
Uwe Hermannffec5f32007-08-23 16:08:21 +0000363
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000364 return 0;
365}
366
Duncan Laurie4095ed72014-08-20 15:39:32 +0000367static int enable_flash_ich_bios_cntl_config_space(struct pci_dev *dev, enum ich_chipset ich_generation,
368 uint8_t bios_cntl)
369{
370 return enable_flash_ich_bios_cntl_common(ich_generation, NULL, dev, bios_cntl);
371}
372
373static int enable_flash_ich_bios_cntl_memmapped(enum ich_chipset ich_generation, void *addr)
374{
375 return enable_flash_ich_bios_cntl_common(ich_generation, addr, NULL, 0);
376}
377
Stefan Tauner92d6a862013-10-25 00:33:37 +0000378static int enable_flash_ich_fwh_decode(struct pci_dev *dev, enum ich_chipset ich_generation)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000379{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000380 uint8_t fwh_sel1 = 0, fwh_sel2 = 0, fwh_dec_en_lo = 0, fwh_dec_en_hi = 0; /* silence compilers */
381 bool implemented = 0;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000382 void *ilb = NULL; /* Only for Baytrail */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000383 switch (ich_generation) {
384 case CHIPSET_ICH:
385 /* FIXME: Unlike later chipsets, ICH and ICH-0 do only support mapping of the top-most 4MB
386 * and therefore do only feature FWH_DEC_EN (E3h, different default too) and FWH_SEL (E8h). */
387 break;
388 case CHIPSET_ICH2345:
Kyösti Mälkki88ee0402013-09-14 23:37:01 +0000389 fwh_sel1 = 0xe8;
390 fwh_sel2 = 0xee;
391 fwh_dec_en_lo = 0xf0;
392 fwh_dec_en_hi = 0xe3;
Stefan Tauner92d6a862013-10-25 00:33:37 +0000393 implemented = 1;
394 break;
395 case CHIPSET_POULSBO:
396 case CHIPSET_TUNNEL_CREEK:
397 /* FIXME: Similar to ICH and ICH-0, Tunnel Creek and Poulsbo do only feature one register each,
398 * FWH_DEC_EN (D7h) and FWH_SEL (D0h). */
399 break;
400 case CHIPSET_CENTERTON:
401 /* FIXME: Similar to above FWH_DEC_EN (D4h) and FWH_SEL (D0h). */
402 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000403 case CHIPSET_BAYTRAIL: {
404 uint32_t ilb_base = pci_read_long(dev, 0x50) & 0xfffffe00; /* bits 31:9 */
405 if (ilb_base == 0) {
406 msg_perr("Error: Invalid ILB_BASE_ADDRESS\n");
407 return ERROR_FATAL;
408 }
409 ilb = rphysmap("BYT IBASE", ilb_base, 512);
410 fwh_sel1 = 0x18;
411 fwh_dec_en_lo = 0xd8;
412 fwh_dec_en_hi = 0xd9;
413 implemented = 1;
414 break;
415 }
Stefan Tauner92d6a862013-10-25 00:33:37 +0000416 case CHIPSET_ICH6:
417 case CHIPSET_ICH7:
418 default: /* Future version might behave the same */
419 fwh_sel1 = 0xd0;
420 fwh_sel2 = 0xd4;
421 fwh_dec_en_lo = 0xd8;
422 fwh_dec_en_hi = 0xd9;
423 implemented = 1;
424 break;
Kyösti Mälkki88ee0402013-09-14 23:37:01 +0000425 }
Kyösti Mälkki743babc2013-09-14 23:36:53 +0000426
Stefan Tauner92d6a862013-10-25 00:33:37 +0000427 char *idsel = extract_programmer_param("fwh_idsel");
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000428 if (idsel && strlen(idsel)) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000429 if (!implemented) {
430 msg_perr("Error: fwh_idsel= specified, but (yet) unsupported on this chipset.\n");
431 goto idsel_garbage_out;
432 }
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000433 errno = 0;
434 /* Base 16, nothing else makes sense. */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000435 uint64_t fwh_idsel = (uint64_t)strtoull(idsel, NULL, 16);
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000436 if (errno) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000437 msg_perr("Error: fwh_idsel= specified, but value could not be converted.\n");
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000438 goto idsel_garbage_out;
439 }
Duncan Laurie4095ed72014-08-20 15:39:32 +0000440 uint64_t fwh_mask = 0xffffffff;
441 if (fwh_sel2 > 0)
442 fwh_mask |= (0xffffULL << 32);
443 if (fwh_idsel & ~fwh_mask) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000444 msg_perr("Error: fwh_idsel= specified, but value had unused bits set.\n");
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000445 goto idsel_garbage_out;
446 }
Duncan Laurie4095ed72014-08-20 15:39:32 +0000447 uint64_t fwh_idsel_old;
448 if (ich_generation == CHIPSET_BAYTRAIL) {
449 fwh_idsel_old = mmio_readl(ilb + fwh_sel1);
450 rmmio_writel(fwh_idsel, ilb + fwh_sel1);
451 } else {
Stefan Tauner5c316f92015-02-08 21:57:52 +0000452 fwh_idsel_old = (uint64_t)pci_read_long(dev, fwh_sel1) << 16;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000453 rpci_write_long(dev, fwh_sel1, (fwh_idsel >> 16) & 0xffffffff);
454 if (fwh_sel2 > 0) {
455 fwh_idsel_old |= pci_read_word(dev, fwh_sel2);
456 rpci_write_word(dev, fwh_sel2, fwh_idsel & 0xffff);
457 }
458 }
Stefan Taunereff156e2014-07-13 17:06:11 +0000459 msg_pdbg("Setting IDSEL from 0x%012" PRIx64 " to 0x%012" PRIx64 " for top 16 MB.\n",
Stefan Tauner92d6a862013-10-25 00:33:37 +0000460 fwh_idsel_old, fwh_idsel);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000461 /* FIXME: Decode settings are not changed. */
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000462 } else if (idsel) {
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000463 msg_perr("Error: fwh_idsel= specified, but no value given.\n");
Sylvain "ythier" Hitier3093f8f2011-09-03 11:22:27 +0000464idsel_garbage_out:
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000465 free(idsel);
Tadas Slotkus0e3f1cf2011-09-06 18:49:31 +0000466 return ERROR_FATAL;
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000467 }
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000468 free(idsel);
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000469
Stefan Tauner92d6a862013-10-25 00:33:37 +0000470 if (!implemented) {
Stefan Taunereff156e2014-07-13 17:06:11 +0000471 msg_pdbg2("FWH IDSEL handling is not implemented on this chipset.\n");
Stefan Tauner92d6a862013-10-25 00:33:37 +0000472 return 0;
473 }
474
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000475 /* Ignore all legacy ranges below 1 MB.
476 * We currently only support flashing the chip which responds to
477 * IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations
478 * have to be adjusted.
479 */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000480 int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0;
481 bool contiguous = 1;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000482 uint32_t fwh_conf;
483 if (ich_generation == CHIPSET_BAYTRAIL)
484 fwh_conf = mmio_readl(ilb + fwh_sel1);
485 else
486 fwh_conf = pci_read_long(dev, fwh_sel1);
487
Stefan Tauner92d6a862013-10-25 00:33:37 +0000488 int i;
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000489 /* FWH_SEL1 */
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000490 for (i = 7; i >= 0; i--) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000491 int tmp = (fwh_conf >> (i * 4)) & 0xf;
Stefan Taunereff156e2014-07-13 17:06:11 +0000492 msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000493 (0x1ff8 + i) * 0x80000,
494 (0x1ff0 + i) * 0x80000,
495 tmp);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000496 if ((tmp == 0) && contiguous) {
497 max_decode_fwh_idsel = (8 - i) * 0x80000;
498 } else {
499 contiguous = 0;
500 }
501 }
Duncan Laurie4095ed72014-08-20 15:39:32 +0000502 if (fwh_sel2 > 0) {
503 /* FWH_SEL2 */
504 fwh_conf = pci_read_word(dev, fwh_sel2);
505 for (i = 3; i >= 0; i--) {
506 int tmp = (fwh_conf >> (i * 4)) & 0xf;
507 msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n",
508 (0xff4 + i) * 0x100000,
509 (0xff0 + i) * 0x100000,
510 tmp);
511 if ((tmp == 0) && contiguous) {
512 max_decode_fwh_idsel = (8 - i) * 0x100000;
513 } else {
514 contiguous = 0;
515 }
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000516 }
517 }
518 contiguous = 1;
519 /* FWH_DEC_EN1 */
Kyösti Mälkki743babc2013-09-14 23:36:53 +0000520 fwh_conf = pci_read_byte(dev, fwh_dec_en_hi);
521 fwh_conf <<= 8;
522 fwh_conf |= pci_read_byte(dev, fwh_dec_en_lo);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000523 for (i = 7; i >= 0; i--) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000524 int tmp = (fwh_conf >> (i + 0x8)) & 0x1;
Stefan Taunereff156e2014-07-13 17:06:11 +0000525 msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000526 (0x1ff8 + i) * 0x80000,
527 (0x1ff0 + i) * 0x80000,
528 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000529 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000530 max_decode_fwh_decode = (8 - i) * 0x80000;
531 } else {
532 contiguous = 0;
533 }
534 }
535 for (i = 3; i >= 0; i--) {
Stefan Tauner92d6a862013-10-25 00:33:37 +0000536 int tmp = (fwh_conf >> i) & 0x1;
Stefan Taunereff156e2014-07-13 17:06:11 +0000537 msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000538 (0xff4 + i) * 0x100000,
539 (0xff0 + i) * 0x100000,
540 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000541 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000542 max_decode_fwh_decode = (8 - i) * 0x100000;
543 } else {
544 contiguous = 0;
545 }
546 }
547 max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode);
Stefan Taunereff156e2014-07-13 17:06:11 +0000548 msg_pdbg("Maximum FWH chip size: 0x%x bytes\n", max_rom_decode.fwh);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000549
Kyösti Mälkki743babc2013-09-14 23:36:53 +0000550 return 0;
551}
552
Stefan Tauner92d6a862013-10-25 00:33:37 +0000553static int enable_flash_ich_fwh(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl)
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000554{
Kyösti Mälkki88ee0402013-09-14 23:37:01 +0000555 int err;
556
557 /* Configure FWH IDSEL decoder maps. */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000558 if ((err = enable_flash_ich_fwh_decode(dev, ich_generation)) != 0)
Kyösti Mälkki88ee0402013-09-14 23:37:01 +0000559 return err;
560
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000561 internal_buses_supported = BUS_FWH;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000562 return enable_flash_ich_bios_cntl_config_space(dev, ich_generation, bios_cntl);
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000563}
564
Stefan Tauner92d6a862013-10-25 00:33:37 +0000565static int enable_flash_ich0(struct pci_dev *dev, const char *name)
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000566{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000567 return enable_flash_ich_fwh(dev, CHIPSET_ICH, 0x4e);
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000568}
569
Stefan Tauner92d6a862013-10-25 00:33:37 +0000570static int enable_flash_ich2345(struct pci_dev *dev, const char *name)
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000571{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000572 return enable_flash_ich_fwh(dev, CHIPSET_ICH2345, 0x4e);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000573}
574
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000575static int enable_flash_ich6(struct pci_dev *dev, const char *name)
576{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000577 return enable_flash_ich_fwh(dev, CHIPSET_ICH6, 0xdc);
Kyösti Mälkki78cd0872013-09-14 23:36:57 +0000578}
579
Adam Jurkowskie4984102009-12-21 15:30:46 +0000580static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
581{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000582 return enable_flash_ich_fwh(dev, CHIPSET_POULSBO, 0xd8);
Adam Jurkowskie4984102009-12-21 15:30:46 +0000583}
584
Nico Huber0ea99f52017-03-17 17:22:53 +0100585static void enable_flash_ich_report_gcs(struct pci_dev *const dev, const enum ich_chipset ich_generation,
586 const uint8_t *const rcrb)
Ingo Feldschmiddadc0a62011-09-07 19:18:25 +0000587{
Nico Huber0ea99f52017-03-17 17:22:53 +0100588 uint32_t gcs;
Nico Huber93c30692017-03-20 14:25:09 +0100589 const char *reg_name;
590 bool bild, top_swap;
Nico Huber0ea99f52017-03-17 17:22:53 +0100591
592 switch (ich_generation) {
593 case CHIPSET_BAYTRAIL:
Nico Huber93c30692017-03-20 14:25:09 +0100594 reg_name = "GCS";
Nico Huber0ea99f52017-03-17 17:22:53 +0100595 gcs = mmio_readl(rcrb + 0);
Nico Huber93c30692017-03-20 14:25:09 +0100596 bild = gcs & 1;
Nico Huber0ea99f52017-03-17 17:22:53 +0100597 top_swap = (gcs & 2) >> 1;
598 break;
Nico Huber93c30692017-03-20 14:25:09 +0100599 case CHIPSET_100_SERIES_SUNRISE_POINT:
David Hendricksa5216362017-08-08 20:02:22 -0700600 case CHIPSET_C620_SERIES_LEWISBURG:
Nico Huber93c30692017-03-20 14:25:09 +0100601 reg_name = "BIOS_SPI_BC";
602 gcs = pci_read_long(dev, 0xdc);
603 bild = (gcs >> 7) & 1;
604 top_swap = (gcs >> 4) & 1;
605 break;
Nico Huber0ea99f52017-03-17 17:22:53 +0100606 default:
Nico Huber93c30692017-03-20 14:25:09 +0100607 reg_name = "GCS";
Nico Huber0ea99f52017-03-17 17:22:53 +0100608 gcs = mmio_readl(rcrb + 0x3410);
Nico Huber93c30692017-03-20 14:25:09 +0100609 bild = gcs & 1;
Nico Huber0ea99f52017-03-17 17:22:53 +0100610 top_swap = mmio_readb(rcrb + 0x3414) & 1;
611 break;
612 }
613
Nico Huber93c30692017-03-20 14:25:09 +0100614 msg_pdbg("%s = 0x%x: ", reg_name, gcs);
615 msg_pdbg("BIOS Interface Lock-Down: %sabled, ", bild ? "en" : "dis");
Duncan Laurie4095ed72014-08-20 15:39:32 +0000616
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000617 static const char *const straps_names_EP80579[] = { "SPI", "reserved", "reserved", "LPC" };
618 static const char *const straps_names_ich7_nm10[] = { "reserved", "SPI", "PCI", "LPC" };
Stefan Tauner92d6a862013-10-25 00:33:37 +0000619 static const char *const straps_names_tunnel_creek[] = { "SPI", "LPC" };
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000620 static const char *const straps_names_ich8910[] = { "SPI", "SPI", "PCI", "LPC" };
Helge Wagnera0fce5f2012-07-24 16:33:55 +0000621 static const char *const straps_names_pch567[] = { "LPC", "reserved", "PCI", "SPI" };
Duncan Laurie823096e2014-08-20 15:39:38 +0000622 static const char *const straps_names_pch89_baytrail[] = { "LPC", "reserved", "reserved", "SPI" };
Stefan Tauner92d6a862013-10-25 00:33:37 +0000623 static const char *const straps_names_pch8_lp[] = { "SPI", "LPC" };
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000624 static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" };
625
Stefan Tauner92d6a862013-10-25 00:33:37 +0000626 const char *const *straps_names;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000627 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +0000628 case CHIPSET_ICH7:
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000629 /* EP80579 may need further changes, but this is the least
630 * intrusive way to get correct BOOT Strap printing without
631 * changing the rest of its code path). */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000632 if (dev->device_id == 0x5031)
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000633 straps_names = straps_names_EP80579;
634 else
635 straps_names = straps_names_ich7_nm10;
636 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000637 case CHIPSET_ICH8:
638 case CHIPSET_ICH9:
639 case CHIPSET_ICH10:
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000640 straps_names = straps_names_ich8910;
641 break;
Stefan Tauner92d6a862013-10-25 00:33:37 +0000642 case CHIPSET_TUNNEL_CREEK:
643 straps_names = straps_names_tunnel_creek;
644 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000645 case CHIPSET_5_SERIES_IBEX_PEAK:
646 case CHIPSET_6_SERIES_COUGAR_POINT:
Helge Wagnera0fce5f2012-07-24 16:33:55 +0000647 case CHIPSET_7_SERIES_PANTHER_POINT:
648 straps_names = straps_names_pch567;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000649 break;
Duncan Laurie90eb2262013-03-15 03:12:29 +0000650 case CHIPSET_8_SERIES_LYNX_POINT:
Duncan Laurie823096e2014-08-20 15:39:38 +0000651 case CHIPSET_9_SERIES_WILDCAT_POINT:
Duncan Laurie4095ed72014-08-20 15:39:32 +0000652 case CHIPSET_BAYTRAIL:
Duncan Laurie823096e2014-08-20 15:39:38 +0000653 straps_names = straps_names_pch89_baytrail;
Duncan Laurie90eb2262013-03-15 03:12:29 +0000654 break;
655 case CHIPSET_8_SERIES_LYNX_POINT_LP:
Nico Huber51205912017-03-17 17:59:54 +0100656 case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
Nico Huber93c30692017-03-20 14:25:09 +0100657 case CHIPSET_100_SERIES_SUNRISE_POINT:
David Hendricksa5216362017-08-08 20:02:22 -0700658 case CHIPSET_C620_SERIES_LEWISBURG:
Duncan Laurie90eb2262013-03-15 03:12:29 +0000659 straps_names = straps_names_pch8_lp;
660 break;
661 case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
Stefan Tauner92d6a862013-10-25 00:33:37 +0000662 case CHIPSET_CENTERTON: // FIXME: Datasheet does not mention GCS at all
Duncan Laurie90eb2262013-03-15 03:12:29 +0000663 straps_names = straps_names_unknown;
664 break;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000665 default:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000666 msg_gerr("%s: unknown ICH generation. Please report!\n", __func__);
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000667 straps_names = straps_names_unknown;
668 break;
669 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000670
Duncan Laurie4095ed72014-08-20 15:39:32 +0000671 uint8_t bbs;
672 switch (ich_generation) {
673 case CHIPSET_TUNNEL_CREEK:
674 bbs = (gcs >> 1) & 0x1;
675 break;
676 case CHIPSET_8_SERIES_LYNX_POINT_LP:
Nico Huber51205912017-03-17 17:59:54 +0100677 case CHIPSET_9_SERIES_WILDCAT_POINT_LP:
678 /* LP PCHs use a single bit for BBS */
Duncan Laurie4095ed72014-08-20 15:39:32 +0000679 bbs = (gcs >> 10) & 0x1;
680 break;
Nico Huber93c30692017-03-20 14:25:09 +0100681 case CHIPSET_100_SERIES_SUNRISE_POINT:
David Hendricksa5216362017-08-08 20:02:22 -0700682 case CHIPSET_C620_SERIES_LEWISBURG:
Nico Huber93c30692017-03-20 14:25:09 +0100683 bbs = (gcs >> 6) & 0x1;
684 break;
Duncan Laurie4095ed72014-08-20 15:39:32 +0000685 default:
686 /* Other chipsets use two bits for BBS */
687 bbs = (gcs >> 10) & 0x3;
688 break;
689 }
690 msg_pdbg("Boot BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
691
692 /* Centerton has its TS bit in [GPE0BLK] + 0x30 while the exact location for Tunnel Creek is unknown. */
693 if (ich_generation != CHIPSET_TUNNEL_CREEK && ich_generation != CHIPSET_CENTERTON)
694 msg_pdbg("Top Swap: %s\n", (top_swap) ? "enabled (A16(+) inverted)" : "not enabled");
695}
696
697static int enable_flash_ich_spi(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl)
698{
699
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000700 /* Get physical address of Root Complex Register Block */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000701 uint32_t rcra = pci_read_long(dev, 0xf0) & 0xffffc000;
702 msg_pdbg("Root Complex Register Block address = 0x%x\n", rcra);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000703
704 /* Map RCBA to virtual memory */
Stefan Tauner92d6a862013-10-25 00:33:37 +0000705 void *rcrb = rphysmap("ICH RCRB", rcra, 0x4000);
Stefan Tauner7fb5aa02013-08-14 15:48:44 +0000706 if (rcrb == ERROR_PTR)
Niklas Söderlund5d307202013-09-14 09:02:27 +0000707 return ERROR_FATAL;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000708
Nico Huber0ea99f52017-03-17 17:22:53 +0100709 enable_flash_ich_report_gcs(dev, ich_generation, rcrb);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000710
Stefan Tauner92d6a862013-10-25 00:33:37 +0000711 /* Handle FWH-related parameters and initialization */
712 int ret_fwh = enable_flash_ich_fwh(dev, ich_generation, bios_cntl);
713 if (ret_fwh == ERROR_FATAL)
714 return ret_fwh;
715
716 /* SPIBAR is at RCRB+0x3020 for ICH[78], Tunnel Creek and Centerton, and RCRB+0x3800 for ICH9. */
717 uint16_t spibar_offset;
718 switch (ich_generation) {
Duncan Laurie4095ed72014-08-20 15:39:32 +0000719 case CHIPSET_BAYTRAIL:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000720 case CHIPSET_ICH_UNKNOWN:
721 return ERROR_FATAL;
722 case CHIPSET_ICH7:
723 case CHIPSET_ICH8:
724 case CHIPSET_TUNNEL_CREEK:
725 case CHIPSET_CENTERTON:
726 spibar_offset = 0x3020;
727 break;
728 case CHIPSET_ICH9:
729 default: /* Future version might behave the same */
730 spibar_offset = 0x3800;
731 break;
732 }
733 msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " + 0x%04x\n", PRIxPTR_WIDTH, (uintptr_t)rcrb, spibar_offset);
734 void *spibar = rcrb + spibar_offset;
735
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000736 /* This adds BUS_SPI */
Nico Huber560111e2017-04-26 12:27:17 +0200737 int ret_spi = ich_init_spi(spibar, ich_generation);
Stefan Tauner50e7c602011-11-08 10:55:54 +0000738 if (ret_spi == ERROR_FATAL)
739 return ret_spi;
740
Stefan Tauner92d6a862013-10-25 00:33:37 +0000741 if (ret_fwh || ret_spi)
742 return ERROR_NONFATAL;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000743
Stefan Tauner92d6a862013-10-25 00:33:37 +0000744 return 0;
745}
746
747static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name)
748{
749 return enable_flash_ich_spi(dev, CHIPSET_TUNNEL_CREEK, 0xd8);
750}
751
752static int enable_flash_s12x0(struct pci_dev *dev, const char *name)
753{
754 return enable_flash_ich_spi(dev, CHIPSET_CENTERTON, 0xd8);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000755}
Stefan Reinauera9424d52008-06-27 16:28:34 +0000756
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000757static int enable_flash_ich7(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000758{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000759 return enable_flash_ich_spi(dev, CHIPSET_ICH7, 0xdc);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000760}
761
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000762static int enable_flash_ich8(struct pci_dev *dev, const char *name)
763{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000764 return enable_flash_ich_spi(dev, CHIPSET_ICH8, 0xdc);
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000765}
766
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000767static int enable_flash_ich9(struct pci_dev *dev, const char *name)
768{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000769 return enable_flash_ich_spi(dev, CHIPSET_ICH9, 0xdc);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000770}
771
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000772static int enable_flash_ich10(struct pci_dev *dev, const char *name)
773{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000774 return enable_flash_ich_spi(dev, CHIPSET_ICH10, 0xdc);
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000775}
776
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000777/* Ibex Peak aka. 5 series & 3400 series */
778static int enable_flash_pch5(struct pci_dev *dev, const char *name)
779{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000780 return enable_flash_ich_spi(dev, CHIPSET_5_SERIES_IBEX_PEAK, 0xdc);
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000781}
782
783/* Cougar Point aka. 6 series & c200 series */
784static int enable_flash_pch6(struct pci_dev *dev, const char *name)
785{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000786 return enable_flash_ich_spi(dev, CHIPSET_6_SERIES_COUGAR_POINT, 0xdc);
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000787}
788
Stefan Tauner2abab942012-04-27 20:41:23 +0000789/* Panther Point aka. 7 series */
790static int enable_flash_pch7(struct pci_dev *dev, const char *name)
791{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000792 return enable_flash_ich_spi(dev, CHIPSET_7_SERIES_PANTHER_POINT, 0xdc);
Stefan Tauner2abab942012-04-27 20:41:23 +0000793}
794
795/* Lynx Point aka. 8 series */
796static int enable_flash_pch8(struct pci_dev *dev, const char *name)
797{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000798 return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT, 0xdc);
Stefan Tauner2abab942012-04-27 20:41:23 +0000799}
800
Stefan Tauner92d6a862013-10-25 00:33:37 +0000801/* Lynx Point LP aka. 8 series low-power */
Duncan Laurie90eb2262013-03-15 03:12:29 +0000802static int enable_flash_pch8_lp(struct pci_dev *dev, const char *name)
803{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000804 return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT_LP, 0xdc);
Duncan Laurie90eb2262013-03-15 03:12:29 +0000805}
806
807/* Wellsburg (for Haswell-EP Xeons) */
808static int enable_flash_pch8_wb(struct pci_dev *dev, const char *name)
809{
Stefan Tauner92d6a862013-10-25 00:33:37 +0000810 return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_WELLSBURG, 0xdc);
Duncan Laurie90eb2262013-03-15 03:12:29 +0000811}
812
Duncan Laurie823096e2014-08-20 15:39:38 +0000813/* Wildcat Point */
814static int enable_flash_pch9(struct pci_dev *dev, const char *name)
815{
816 return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc);
817}
818
Nico Huber51205912017-03-17 17:59:54 +0100819/* Wildcat Point LP */
820static int enable_flash_pch9_lp(struct pci_dev *dev, const char *name)
821{
822 return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT_LP, 0xdc);
823}
824
Nico Huber93c30692017-03-20 14:25:09 +0100825/* Sunrise Point */
826static int enable_flash_pch100_shutdown(void *const pci_acc)
827{
828 pci_cleanup(pci_acc);
829 return 0;
830}
831
David Hendricksa5216362017-08-08 20:02:22 -0700832static int enable_flash_pch100_or_c620(struct pci_dev *const dev, const char *const name, const enum ich_chipset pch_generation)
Nico Huber93c30692017-03-20 14:25:09 +0100833{
Nico Huber93c30692017-03-20 14:25:09 +0100834 int ret = ERROR_FATAL;
835
836 /*
837 * The SPI PCI device is usually hidden (by hiding PCI vendor
838 * and device IDs). So we need a PCI access method that works
839 * even when the OS doesn't know the PCI device. We can't use
840 * this method globally since it would bring along other con-
841 * straints (e.g. on PCI domains, extended PCIe config space).
842 */
843 struct pci_access *const pci_acc = pci_alloc();
Youness Alaouia54ceb12017-07-26 18:03:36 -0400844 struct pci_access *const saved_pacc = pacc;
Nico Huber93c30692017-03-20 14:25:09 +0100845 if (!pci_acc) {
846 msg_perr("Can't allocate PCI accessor.\n");
847 return ret;
848 }
849 pci_acc->method = PCI_ACCESS_I386_TYPE1;
850 pci_init(pci_acc);
851 register_shutdown(enable_flash_pch100_shutdown, pci_acc);
852
853 struct pci_dev *const spi_dev = pci_get_dev(pci_acc, dev->domain, dev->bus, 0x1f, 5);
854 if (!spi_dev) {
855 msg_perr("Can't allocate PCI device.\n");
856 return ret;
857 }
858
Youness Alaouia54ceb12017-07-26 18:03:36 -0400859 /* Modify pacc so the rpci_write can register the undo callback with a
860 * device using the correct pci_access */
861 pacc = pci_acc;
Nico Huber93c30692017-03-20 14:25:09 +0100862 enable_flash_ich_report_gcs(spi_dev, pch_generation, NULL);
863
864 const int ret_bc = enable_flash_ich_bios_cntl_config_space(spi_dev, pch_generation, 0xdc);
865 if (ret_bc == ERROR_FATAL)
866 goto _freepci_ret;
867
868 const uint32_t phys_spibar = pci_read_long(spi_dev, PCI_BASE_ADDRESS_0) & 0xfffff000;
869 void *const spibar = rphysmap("SPIBAR", phys_spibar, 0x1000);
870 if (spibar == ERROR_PTR)
871 goto _freepci_ret;
872 msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " (phys = 0x%08x)\n", PRIxPTR_WIDTH, (uintptr_t)spibar, phys_spibar);
873
874 /* This adds BUS_SPI */
875 const int ret_spi = ich_init_spi(spibar, pch_generation);
876 if (ret_spi != ERROR_FATAL) {
877 if (ret_bc || ret_spi)
878 ret = ERROR_NONFATAL;
879 else
880 ret = 0;
881 }
882
883_freepci_ret:
884 pci_free_dev(spi_dev);
Youness Alaouia54ceb12017-07-26 18:03:36 -0400885 pacc = saved_pacc;
Nico Huber93c30692017-03-20 14:25:09 +0100886 return ret;
887}
888
David Hendricksa5216362017-08-08 20:02:22 -0700889static int enable_flash_pch100(struct pci_dev *const dev, const char *const name)
890{
891 return enable_flash_pch100_or_c620(dev, name, CHIPSET_100_SERIES_SUNRISE_POINT);
892}
893
894static int enable_flash_c620(struct pci_dev *const dev, const char *const name)
895{
896 return enable_flash_pch100_or_c620(dev, name, CHIPSET_C620_SERIES_LEWISBURG);
897}
898
Duncan Laurie4095ed72014-08-20 15:39:32 +0000899/* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley.
900 * These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately.
901 *
902 * Differences include:
903 * - RCBA at LPC config 0xF0 too but mapped range is only 4 B long instead of 16 kB.
904 * - GCS at [RCRB] + 0 (instead of [RCRB] + 0x3410).
905 * - TS (Top Swap) in GCS (instead of [RCRB] + 0x3414).
906 * - SPIBAR (coined SBASE) at LPC config 0x54 (instead of [RCRB] + 0x3800).
907 * - BIOS_CNTL (coined BCR) at [SPIBAR] + 0xFC (instead of LPC config 0xDC).
908 */
909static int enable_flash_silvermont(struct pci_dev *dev, const char *name)
910{
911 enum ich_chipset ich_generation = CHIPSET_BAYTRAIL;
912
913 /* Get physical address of Root Complex Register Block */
914 uint32_t rcba = pci_read_long(dev, 0xf0) & 0xfffffc00;
915 msg_pdbg("Root Complex Register Block address = 0x%x\n", rcba);
916
917 /* Handle GCS (in RCRB) */
918 void *rcrb = physmap("BYT RCRB", rcba, 4);
Nico Huber0ea99f52017-03-17 17:22:53 +0100919 enable_flash_ich_report_gcs(dev, ich_generation, rcrb);
Duncan Laurie4095ed72014-08-20 15:39:32 +0000920 physunmap(rcrb, 4);
921
922 /* Handle fwh_idsel parameter */
923 int ret_fwh = enable_flash_ich_fwh_decode(dev, ich_generation);
924 if (ret_fwh == ERROR_FATAL)
925 return ret_fwh;
926
927 internal_buses_supported = BUS_FWH;
928
929 /* Get physical address of SPI Base Address and map it */
930 uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00;
931 msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase);
932 void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */
933
934 /* Enable Flash Writes.
935 * Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C).
936 */
937 enable_flash_ich_bios_cntl_memmapped(ich_generation, spibar + 0xFC);
938
Nico Huber560111e2017-04-26 12:27:17 +0200939 int ret_spi = ich_init_spi(spibar, ich_generation);
Duncan Laurie4095ed72014-08-20 15:39:32 +0000940 if (ret_spi == ERROR_FATAL)
941 return ret_spi;
942
943 if (ret_fwh || ret_spi)
944 return ERROR_NONFATAL;
945
946 return 0;
947}
948
Michael Karcher89bed6d2010-06-13 10:16:12 +0000949static int via_no_byte_merge(struct pci_dev *dev, const char *name)
950{
951 uint8_t val;
952
953 val = pci_read_byte(dev, 0x71);
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000954 if (val & 0x40) {
Michael Karcher89bed6d2010-06-13 10:16:12 +0000955 msg_pdbg("Disabling byte merging\n");
956 val &= ~0x40;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000957 rpci_write_byte(dev, 0x71, val);
Michael Karcher89bed6d2010-06-13 10:16:12 +0000958 }
959 return NOT_DONE_YET; /* need to find south bridge, too */
960}
961
Uwe Hermann372eeb52007-12-04 21:49:06 +0000962static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000963{
Ollie Lho184a4042005-11-26 21:55:36 +0000964 uint8_t val;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000965
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000966 /* Enable ROM decode range (1MB) FFC00000 - FFFFFFFF. */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000967 rpci_write_byte(dev, 0x41, 0x7f);
Bari Ari9477c4e2008-04-29 13:46:38 +0000968
Uwe Hermannffec5f32007-08-23 16:08:21 +0000969 /* ROM write enable */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000970 val = pci_read_byte(dev, 0x40);
971 val |= 0x10;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000972 rpci_write_byte(dev, 0x40, val);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000973
974 if (pci_read_byte(dev, 0x40) != val) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +0000975 msg_pwarn("\nWarning: Failed to enable flash write on \"%s\"\n", name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000976 return -1;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000977 }
Luc Verhaegen6382b442007-03-02 22:16:38 +0000978
Helge Wagnerdd73d832012-08-24 23:03:46 +0000979 if (dev->device_id == 0x3227) { /* VT8237/VT8237R */
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000980 /* All memory cycles, not just ROM ones, go to LPC. */
981 val = pci_read_byte(dev, 0x59);
982 val &= ~0x80;
983 rpci_write_byte(dev, 0x59, val);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000984 }
985
Uwe Hermanna7e05482007-05-09 10:17:44 +0000986 return 0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000987}
988
Helge Wagnerdd73d832012-08-24 23:03:46 +0000989static int enable_flash_vt_vx(struct pci_dev *dev, const char *name)
990{
991 struct pci_dev *south_north = pci_dev_find(0x1106, 0xa353);
992 if (south_north == NULL) {
993 msg_perr("Could not find South-North Module Interface Control device!\n");
994 return ERROR_FATAL;
995 }
996
997 msg_pdbg("Strapped to ");
998 if ((pci_read_byte(south_north, 0x56) & 0x01) == 0) {
999 msg_pdbg("LPC.\n");
1000 return enable_flash_vt823x(dev, name);
1001 }
1002 msg_pdbg("SPI.\n");
1003
1004 uint32_t mmio_base;
1005 void *mmio_base_physmapped;
1006 uint32_t spi_cntl;
1007 #define SPI_CNTL_LEN 0x08
1008 uint32_t spi0_mm_base = 0;
1009 switch(dev->device_id) {
1010 case 0x8353: /* VX800/VX820 */
1011 spi0_mm_base = pci_read_long(dev, 0xbc) << 8;
Lubomir Rinteld0803c82017-10-30 07:57:53 +01001012 if (spi0_mm_base == 0x0) {
1013 msg_pdbg ("MMIO not enabled!\n");
1014 return ERROR_FATAL;
1015 }
Helge Wagnerdd73d832012-08-24 23:03:46 +00001016 break;
1017 case 0x8409: /* VX855/VX875 */
1018 case 0x8410: /* VX900 */
1019 mmio_base = pci_read_long(dev, 0xbc) << 8;
Lubomir Rinteld0803c82017-10-30 07:57:53 +01001020 if (mmio_base == 0x0) {
1021 msg_pdbg ("MMIO not enabled!\n");
1022 return ERROR_FATAL;
1023 }
Helge Wagnerdd73d832012-08-24 23:03:46 +00001024 mmio_base_physmapped = physmap("VIA VX MMIO register", mmio_base, SPI_CNTL_LEN);
Stefan Tauner7fb5aa02013-08-14 15:48:44 +00001025 if (mmio_base_physmapped == ERROR_PTR)
Helge Wagnerdd73d832012-08-24 23:03:46 +00001026 return ERROR_FATAL;
Helge Wagnerdd73d832012-08-24 23:03:46 +00001027
1028 /* Offset 0 - Bit 0 holds SPI Bus0 Enable Bit. */
1029 spi_cntl = mmio_readl(mmio_base_physmapped) + 0x00;
1030 if ((spi_cntl & 0x01) == 0) {
1031 msg_pdbg ("SPI Bus0 disabled!\n");
1032 physunmap(mmio_base_physmapped, SPI_CNTL_LEN);
1033 return ERROR_FATAL;
1034 }
1035 /* Offset 1-3 has SPI Bus Memory Map Base Address: */
1036 spi0_mm_base = spi_cntl & 0xFFFFFF00;
1037
1038 /* Offset 4 - Bit 0 holds SPI Bus1 Enable Bit. */
1039 spi_cntl = mmio_readl(mmio_base_physmapped) + 0x04;
1040 if ((spi_cntl & 0x01) == 1)
1041 msg_pdbg2("SPI Bus1 is enabled too.\n");
1042
1043 physunmap(mmio_base_physmapped, SPI_CNTL_LEN);
1044 break;
1045 default:
1046 msg_perr("%s: Unsupported chipset %x:%x!\n", __func__, dev->vendor_id, dev->device_id);
1047 return ERROR_FATAL;
1048 }
1049
Nico Huber560111e2017-04-26 12:27:17 +02001050 return via_init_spi(spi0_mm_base);
Helge Wagnerdd73d832012-08-24 23:03:46 +00001051}
1052
1053static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
1054{
Nico Huber560111e2017-04-26 12:27:17 +02001055 return via_init_spi(pci_read_long(dev, 0xbc) << 8);
Helge Wagnerdd73d832012-08-24 23:03:46 +00001056}
1057
Uwe Hermann372eeb52007-12-04 21:49:06 +00001058static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001059{
Uwe Hermannf4a673b2007-06-06 21:35:45 +00001060 uint8_t reg8;
Ollie Lho761bf1b2004-03-20 16:46:10 +00001061
Uwe Hermann394131e2008-10-18 21:14:13 +00001062#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
1063#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00001064#define CS5530_RESET_CONTROL_REG 0x44 /* F0 index 0x44 */
1065#define CS5530_USB_SHADOW_REG 0x43 /* F0 index 0x43 */
Ollie Lhocbbf1252004-03-17 22:22:08 +00001066
Uwe Hermann394131e2008-10-18 21:14:13 +00001067#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
1068#define ROM_WRITE_ENABLE (1 << 1)
1069#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
1070#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00001071#define CS5530_ISA_MASTER (1 << 7)
1072#define CS5530_ENABLE_SA2320 (1 << 2)
1073#define CS5530_ENABLE_SA20 (1 << 6)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001074
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001075 internal_buses_supported = BUS_PARALLEL;
Stefan Taunerc0aaf952011-05-19 02:58:17 +00001076 /* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and
1077 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB.
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00001078 * FIXME: Should we really touch the low mapping below 1 MB? Flashrom
1079 * ignores that region completely.
Uwe Hermannf4a673b2007-06-06 21:35:45 +00001080 * Make the configured ROM areas writable.
1081 */
1082 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
1083 reg8 |= LOWER_ROM_ADDRESS_RANGE;
1084 reg8 |= UPPER_ROM_ADDRESS_RANGE;
1085 reg8 |= ROM_WRITE_ENABLE;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001086 rpci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001087
Uwe Hermannf4a673b2007-06-06 21:35:45 +00001088 /* Set positive decode on ROM. */
1089 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
1090 reg8 |= BIOS_ROM_POSITIVE_DECODE;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001091 rpci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001092
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00001093 reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG);
1094 if (reg8 & CS5530_ISA_MASTER) {
1095 /* We have A0-A23 available. */
1096 max_rom_decode.parallel = 16 * 1024 * 1024;
1097 } else {
1098 reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG);
1099 if (reg8 & CS5530_ENABLE_SA2320) {
1100 /* We have A0-19, A20-A23 available. */
1101 max_rom_decode.parallel = 16 * 1024 * 1024;
1102 } else if (reg8 & CS5530_ENABLE_SA20) {
1103 /* We have A0-19, A20 available. */
1104 max_rom_decode.parallel = 2 * 1024 * 1024;
1105 } else {
1106 /* A20 and above are not active. */
1107 max_rom_decode.parallel = 1024 * 1024;
1108 }
1109 }
1110
Ollie Lhocbbf1252004-03-17 22:22:08 +00001111 return 0;
1112}
1113
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001114/*
Mart Raudseppe1344da2008-02-08 10:10:57 +00001115 * Geode systems write protect the BIOS via RCONFs (cache settings similar
Elyes HAOUAS124ef382018-03-27 12:15:09 +02001116 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
Mart Raudseppe1344da2008-02-08 10:10:57 +00001117 *
1118 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
1119 * To enable write to NOR Boot flash for the benefit of systems that have such
1120 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
Mart Raudseppe1344da2008-02-08 10:10:57 +00001121 */
Uwe Hermann372eeb52007-12-04 21:49:06 +00001122static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
Lane Brooksd54958a2007-11-13 16:45:22 +00001123{
Uwe Hermann394131e2008-10-18 21:14:13 +00001124#define MSR_RCONF_DEFAULT 0x1808
1125#define MSR_NORF_CTL 0x51400018
Mart Raudsepp0514a5f2008-02-08 09:59:58 +00001126
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001127 msr_t msr;
Lane Brooksd54958a2007-11-13 16:45:22 +00001128
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001129 /* Geode only has a single core */
1130 if (setup_cpu_msr(0))
Lane Brooksd54958a2007-11-13 16:45:22 +00001131 return -1;
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001132
1133 msr = rdmsr(MSR_RCONF_DEFAULT);
1134 if ((msr.hi >> 24) != 0x22) {
1135 msr.hi &= 0xfbffffff;
1136 wrmsr(MSR_RCONF_DEFAULT, msr);
Lane Brooksd54958a2007-11-13 16:45:22 +00001137 }
Mart Raudseppe1344da2008-02-08 10:10:57 +00001138
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001139 msr = rdmsr(MSR_NORF_CTL);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +00001140 /* Raise WE_CS3 bit. */
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001141 msr.lo |= 0x08;
1142 wrmsr(MSR_NORF_CTL, msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +00001143
Stefan Reinauer8fa64812009-08-12 09:27:45 +00001144 cleanup_cpu_msr();
Mart Raudsepp0514a5f2008-02-08 09:59:58 +00001145
Uwe Hermann394131e2008-10-18 21:14:13 +00001146#undef MSR_RCONF_DEFAULT
1147#undef MSR_NORF_CTL
Lane Brooksd54958a2007-11-13 16:45:22 +00001148 return 0;
1149}
1150
Uwe Hermann372eeb52007-12-04 21:49:06 +00001151static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001152{
Stefan Taunere34e3e82013-01-01 00:06:51 +00001153 #define SC_REG 0x52
Ollie Lho184a4042005-11-26 21:55:36 +00001154 uint8_t new;
Ollie Lho761bf1b2004-03-20 16:46:10 +00001155
Stefan Taunere34e3e82013-01-01 00:06:51 +00001156 rpci_write_byte(dev, SC_REG, 0xee);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001157
Stefan Taunere34e3e82013-01-01 00:06:51 +00001158 new = pci_read_byte(dev, SC_REG);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001159
Stefan Taunere34e3e82013-01-01 00:06:51 +00001160 if (new != 0xee) { /* FIXME: share this with other code? */
1161 msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", SC_REG, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001162 return -1;
1163 }
Uwe Hermannffec5f32007-08-23 16:08:21 +00001164
Ollie Lhocbbf1252004-03-17 22:22:08 +00001165 return 0;
1166}
1167
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001168/* Works for AMD-768, AMD-8111, VIA VT82C586A/B, VIA VT82C596, VIA VT82C686A/B.
1169 *
1170 * ROM decode control register matrix
Elyes HAOUASac01baa2018-05-28 16:52:21 +02001171 * AMD-768 AMD-8111 VT82C586A/B VT82C596 VT82C686A/B
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001172 * 7 FFC0_0000h–FFFF_FFFFh <- FFFE0000h-FFFEFFFFh <- <-
1173 * 6 FFB0_0000h–FFBF_FFFFh <- FFF80000h-FFFDFFFFh <- <-
1174 * 5 00E8... <- <- FFF00000h-FFF7FFFFh <-
1175 */
1176static int enable_flash_amd_via(struct pci_dev *dev, const char *name, uint8_t decode_val)
Ollie Lho761bf1b2004-03-20 16:46:10 +00001177{
Stefan Taunere34e3e82013-01-01 00:06:51 +00001178 #define AMD_MAPREG 0x43
1179 #define AMD_ENREG 0x40
Ollie Lho184a4042005-11-26 21:55:36 +00001180 uint8_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001181
Stefan Taunere34e3e82013-01-01 00:06:51 +00001182 old = pci_read_byte(dev, AMD_MAPREG);
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001183 new = old | decode_val;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001184 if (new != old) {
Stefan Taunere34e3e82013-01-01 00:06:51 +00001185 rpci_write_byte(dev, AMD_MAPREG, new);
1186 if (pci_read_byte(dev, AMD_MAPREG) != new) {
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001187 msg_pwarn("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
Stefan Taunere34e3e82013-01-01 00:06:51 +00001188 AMD_MAPREG, new, name);
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001189 } else
1190 msg_pdbg("Changed ROM decode range to 0x%02x successfully.\n", new);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001191 }
1192
Uwe Hermann190f8492008-10-25 18:03:50 +00001193 /* Enable 'ROM write' bit. */
Stefan Taunere34e3e82013-01-01 00:06:51 +00001194 old = pci_read_byte(dev, AMD_ENREG);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001195 new = old | 0x01;
1196 if (new == old)
1197 return 0;
Stefan Taunere34e3e82013-01-01 00:06:51 +00001198 rpci_write_byte(dev, AMD_ENREG, new);
Ollie Lhocbbf1252004-03-17 22:22:08 +00001199
Stefan Taunere34e3e82013-01-01 00:06:51 +00001200 if (pci_read_byte(dev, AMD_ENREG) != new) {
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001201 msg_pwarn("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n",
Stefan Taunere34e3e82013-01-01 00:06:51 +00001202 AMD_ENREG, new, name);
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001203 return ERROR_NONFATAL;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001204 }
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001205 msg_pdbg2("Set ROM enable bit successfully.\n");
Uwe Hermannffec5f32007-08-23 16:08:21 +00001206
Ollie Lhocbbf1252004-03-17 22:22:08 +00001207 return 0;
1208}
1209
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001210static int enable_flash_amd_768_8111(struct pci_dev *dev, const char *name)
1211{
1212 /* Enable decoding of 0xFFB00000 to 0xFFFFFFFF (5 MB). */
1213 max_rom_decode.lpc = 5 * 1024 * 1024;
1214 return enable_flash_amd_via(dev, name, 0xC0);
1215}
1216
1217static int enable_flash_vt82c586(struct pci_dev *dev, const char *name)
1218{
1219 /* Enable decoding of 0xFFF80000 to 0xFFFFFFFF. (512 kB) */
1220 max_rom_decode.parallel = 512 * 1024;
1221 return enable_flash_amd_via(dev, name, 0xC0);
1222}
1223
1224/* Works for VT82C686A/B too. */
1225static int enable_flash_vt82c596(struct pci_dev *dev, const char *name)
1226{
Stefan Taunerc2eec2c2014-05-03 21:33:01 +00001227 /* Enable decoding of 0xFFF00000 to 0xFFFFFFFF. (1 MB) */
Stefan Tauner6c67f1c2013-09-12 08:38:23 +00001228 max_rom_decode.parallel = 1024 * 1024;
1229 return enable_flash_amd_via(dev, name, 0xE0);
1230}
1231
Marc Jones3af487d2008-10-15 17:50:29 +00001232static int enable_flash_sb600(struct pci_dev *dev, const char *name)
1233{
Michael Karcherb05b9e12010-07-22 18:04:19 +00001234 uint32_t prot;
Marc Jones3af487d2008-10-15 17:50:29 +00001235 uint8_t reg;
Michael Karcherb05b9e12010-07-22 18:04:19 +00001236 int ret;
Marc Jones3af487d2008-10-15 17:50:29 +00001237
Jason Wanga3f04be2008-11-28 21:36:51 +00001238 /* Clear ROM protect 0-3. */
1239 for (reg = 0x50; reg < 0x60; reg += 4) {
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001240 prot = pci_read_long(dev, reg);
1241 /* No protection flags for this region?*/
1242 if ((prot & 0x3) == 0)
1243 continue;
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001244 msg_pdbg("Chipset %s%sprotected flash from 0x%08x to 0x%08x, unlocking...",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001245 (prot & 0x2) ? "read " : "",
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001246 (prot & 0x1) ? "write " : "",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001247 (prot & 0xfffff800),
1248 (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001249 prot &= 0xfffffffc;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001250 rpci_write_byte(dev, reg, prot);
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001251 prot = pci_read_long(dev, reg);
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001252 if ((prot & 0x3) != 0) {
1253 msg_perr("Disabling %s%sprotection of flash addresses from 0x%08x to 0x%08x failed.\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001254 (prot & 0x2) ? "read " : "",
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001255 (prot & 0x1) ? "write " : "",
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001256 (prot & 0xfffff800),
1257 (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
Stefan Tauner0e0a0dc2014-07-15 13:50:17 +00001258 continue;
1259 }
1260 msg_pdbg("done.\n");
Jason Wanga3f04be2008-11-28 21:36:51 +00001261 }
1262
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001263 internal_buses_supported = BUS_LPC | BUS_FWH;
Michael Karcherb05b9e12010-07-22 18:04:19 +00001264
1265 ret = sb600_probe_spi(dev);
Jason Wanga3f04be2008-11-28 21:36:51 +00001266
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001267 /* Read ROM strap override register. */
1268 OUTB(0x8f, 0xcd6);
1269 reg = INB(0xcd7);
1270 reg &= 0x0e;
Sean Nelson316a29f2010-05-07 20:09:04 +00001271 msg_pdbg("ROM strap override is %sactive", (reg & 0x02) ? "" : "not ");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001272 if (reg & 0x02) {
1273 switch ((reg & 0x0c) >> 2) {
1274 case 0x00:
Sean Nelson316a29f2010-05-07 20:09:04 +00001275 msg_pdbg(": LPC");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001276 break;
1277 case 0x01:
Sean Nelson316a29f2010-05-07 20:09:04 +00001278 msg_pdbg(": PCI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001279 break;
1280 case 0x02:
Sean Nelson316a29f2010-05-07 20:09:04 +00001281 msg_pdbg(": FWH");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001282 break;
1283 case 0x03:
Sean Nelson316a29f2010-05-07 20:09:04 +00001284 msg_pdbg(": SPI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001285 break;
1286 }
1287 }
Sean Nelson316a29f2010-05-07 20:09:04 +00001288 msg_pdbg("\n");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +00001289
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001290 /* Force enable SPI ROM in SB600 PM register.
1291 * If we enable SPI ROM here, we have to disable it after we leave.
Zheng Bao284a6002009-05-04 22:33:50 +00001292 * But how can we know which ROM we are going to handle? So we have
1293 * to trade off. We only access LPC ROM if we boot via LPC ROM. And
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +00001294 * only SPI ROM if we boot via SPI ROM. If you want to access SPI on
1295 * boards with LPC straps, you have to use the code below.
Zheng Bao284a6002009-05-04 22:33:50 +00001296 */
1297 /*
Jason Wanga3f04be2008-11-28 21:36:51 +00001298 OUTB(0x8f, 0xcd6);
1299 OUTB(0x0e, 0xcd7);
Zheng Bao284a6002009-05-04 22:33:50 +00001300 */
Marc Jones3af487d2008-10-15 17:50:29 +00001301
Michael Karcherb05b9e12010-07-22 18:04:19 +00001302 return ret;
Marc Jones3af487d2008-10-15 17:50:29 +00001303}
1304
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001305/* sets bit 0 in 0x6d */
1306static int enable_flash_nvidia_common(struct pci_dev *dev, const char *name)
1307{
1308 uint8_t old, new;
1309
1310 old = pci_read_byte(dev, 0x6d);
1311 new = old | 0x01;
1312 if (new == old)
1313 return 0;
1314
1315 rpci_write_byte(dev, 0x6d, new);
1316 if (pci_read_byte(dev, 0x6d) != new) {
1317 msg_pinfo("Setting register 0x6d to 0x%02x on %s failed.\n", new, name);
1318 return 1;
1319 }
1320 return 0;
1321}
1322
Luc Verhaegen90e8e612009-05-26 09:48:28 +00001323static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name)
1324{
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001325 rpci_write_byte(dev, 0x92, 0);
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001326 if (enable_flash_nvidia_common(dev, name))
1327 return ERROR_NONFATAL;
1328 else
1329 return 0;
Luc Verhaegen90e8e612009-05-26 09:48:28 +00001330}
1331
Uwe Hermann372eeb52007-12-04 21:49:06 +00001332static int enable_flash_ck804(struct pci_dev *dev, const char *name)
Yinghai Lu952dfce2005-07-06 17:13:46 +00001333{
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001334 uint32_t segctrl;
1335 uint8_t reg, old, new;
1336 unsigned int err = 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +00001337
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001338 /* 0x8A is special: it is a single byte and only one nibble is touched. */
1339 reg = 0x8A;
1340 segctrl = pci_read_byte(dev, reg);
1341 if ((segctrl & 0x3) != 0x0) {
1342 if ((segctrl & 0xC) != 0x0) {
1343 msg_pinfo("Can not unlock existing protection in register 0x%02x.\n", reg);
1344 err++;
1345 } else {
1346 msg_pdbg("Unlocking protection in register 0x%02x... ", reg);
1347 rpci_write_byte(dev, reg, segctrl & 0xF0);
1348
1349 segctrl = pci_read_byte(dev, reg);
1350 if ((segctrl & 0x3) != 0x0) {
1351 msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%x).\n",
1352 reg, segctrl);
1353 err++;
1354 } else
1355 msg_pdbg("OK\n");
1356 }
Jonathan Kollasch9ce498e2011-08-06 12:45:21 +00001357 }
1358
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001359 for (reg = 0x8C; reg <= 0x94; reg += 4) {
1360 segctrl = pci_read_long(dev, reg);
1361 if ((segctrl & 0x33333333) == 0x00000000) {
1362 /* reads and writes are unlocked */
1363 continue;
1364 }
1365 if ((segctrl & 0xCCCCCCCC) != 0x00000000) {
1366 msg_pinfo("Can not unlock existing protection in register 0x%02x.\n", reg);
1367 err++;
1368 continue;
1369 }
1370 msg_pdbg("Unlocking protection in register 0x%02x... ", reg);
1371 rpci_write_long(dev, reg, 0x00000000);
1372
1373 segctrl = pci_read_long(dev, reg);
1374 if ((segctrl & 0x33333333) != 0x00000000) {
1375 msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%08x).\n",
1376 reg, segctrl);
1377 err++;
1378 } else
1379 msg_pdbg("OK\n");
1380 }
1381
1382 if (err > 0) {
1383 msg_pinfo("%d locks could not be disabled, disabling writes (reads may also fail).\n", err);
1384 programmer_may_write = 0;
1385 }
1386
1387 reg = 0x88;
1388 old = pci_read_byte(dev, reg);
1389 new = old | 0xC0;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001390 if (new != old) {
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001391 rpci_write_byte(dev, reg, new);
Stefan Taunere34e3e82013-01-01 00:06:51 +00001392 if (pci_read_byte(dev, reg) != new) { /* FIXME: share this with other code? */
1393 msg_pinfo("Setting register 0x%02x to 0x%02x on %s failed.\n", reg, new, name);
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001394 err++;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001395 }
1396 }
Yinghai Lu952dfce2005-07-06 17:13:46 +00001397
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001398 if (enable_flash_nvidia_common(dev, name))
Jonathan Kollaschc8190002012-09-04 03:55:04 +00001399 err++;
1400
1401 if (err > 0)
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001402 return ERROR_NONFATAL;
1403 else
Uwe Hermanna7e05482007-05-09 10:17:44 +00001404 return 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +00001405}
1406
Joshua Roys85835d82010-09-15 14:47:56 +00001407static int enable_flash_osb4(struct pci_dev *dev, const char *name)
1408{
1409 uint8_t tmp;
1410
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001411 internal_buses_supported = BUS_PARALLEL;
Joshua Roys85835d82010-09-15 14:47:56 +00001412
1413 tmp = INB(0xc06);
1414 tmp |= 0x1;
1415 OUTB(tmp, 0xc06);
1416
1417 tmp = INB(0xc6f);
1418 tmp |= 0x40;
1419 OUTB(tmp, 0xc6f);
1420
1421 return 0;
1422}
1423
Uwe Hermann372eeb52007-12-04 21:49:06 +00001424/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
1425static int enable_flash_sb400(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +00001426{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001427 uint8_t tmp;
Stefan Reinauer86de2832006-03-31 11:26:55 +00001428 struct pci_dev *smbusdev;
1429
Uwe Hermann372eeb52007-12-04 21:49:06 +00001430 /* Look for the SMBus device. */
Carl-Daniel Hailfingerf6e3efb2009-05-06 00:35:31 +00001431 smbusdev = pci_dev_find(0x1002, 0x4372);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001432
Uwe Hermanna7e05482007-05-09 10:17:44 +00001433 if (!smbusdev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001434 msg_perr("ERROR: SMBus device not found. Aborting.\n");
Tadas Slotkus0e3f1cf2011-09-06 18:49:31 +00001435 return ERROR_FATAL;
Stefan Reinauer86de2832006-03-31 11:26:55 +00001436 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001437
Uwe Hermann372eeb52007-12-04 21:49:06 +00001438 /* Enable some SMBus stuff. */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001439 tmp = pci_read_byte(smbusdev, 0x79);
1440 tmp |= 0x01;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001441 rpci_write_byte(smbusdev, 0x79, tmp);
Stefan Reinauer86de2832006-03-31 11:26:55 +00001442
Uwe Hermann372eeb52007-12-04 21:49:06 +00001443 /* Change southbridge. */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001444 tmp = pci_read_byte(dev, 0x48);
1445 tmp |= 0x21;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001446 rpci_write_byte(dev, 0x48, tmp);
Stefan Reinauer86de2832006-03-31 11:26:55 +00001447
Uwe Hermann372eeb52007-12-04 21:49:06 +00001448 /* Now become a bit silly. */
Andriy Gapon65c1b862008-05-22 13:22:45 +00001449 tmp = INB(0xc6f);
1450 OUTB(tmp, 0xeb);
1451 OUTB(tmp, 0xeb);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001452 tmp |= 0x40;
Andriy Gapon65c1b862008-05-22 13:22:45 +00001453 OUTB(tmp, 0xc6f);
1454 OUTB(tmp, 0xeb);
1455 OUTB(tmp, 0xeb);
Stefan Reinauer86de2832006-03-31 11:26:55 +00001456
1457 return 0;
1458}
1459
Uwe Hermann372eeb52007-12-04 21:49:06 +00001460static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
Yinghai Luca782972007-01-22 20:21:17 +00001461{
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001462 uint8_t val;
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001463 uint16_t wordval;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001464
Uwe Hermann372eeb52007-12-04 21:49:06 +00001465 /* Set the 0-16 MB enable bits. */
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001466 val = pci_read_byte(dev, 0x88);
1467 val |= 0xff; /* 256K */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001468 rpci_write_byte(dev, 0x88, val);
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001469 val = pci_read_byte(dev, 0x8c);
1470 val |= 0xff; /* 1M */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001471 rpci_write_byte(dev, 0x8c, val);
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001472 wordval = pci_read_word(dev, 0x90);
1473 wordval |= 0x7fff; /* 16M */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001474 rpci_write_word(dev, 0x90, wordval);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001475
Stefan Taunerb66ba1e2012-09-04 01:49:49 +00001476 if (enable_flash_nvidia_common(dev, name))
1477 return ERROR_NONFATAL;
1478 else
Uwe Hermanna7e05482007-05-09 10:17:44 +00001479 return 0;
Yinghai Luca782972007-01-22 20:21:17 +00001480}
1481
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001482/*
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001483 * The MCP6x/MCP7x code is based on cleanroom reverse engineering.
1484 * It is assumed that LPC chips need the MCP55 code and SPI chips need the
1485 * code provided in enable_flash_mcp6x_7x_common.
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001486 */
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001487static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001488{
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001489 int ret = 0, want_spi = 0;
Michael Karchercfa674f2010-02-25 11:38:23 +00001490 uint8_t val;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001491
1492 /* dev is the ISA bridge. No idea what the stuff below does. */
Michael Karchercfa674f2010-02-25 11:38:23 +00001493 val = pci_read_byte(dev, 0x8a);
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001494 msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 "
Michael Karchercfa674f2010-02-25 11:38:23 +00001495 "is %i\n", val, (val >> 6) & 0x1, (val >> 5) & 0x1);
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001496
Michael Karchercfa674f2010-02-25 11:38:23 +00001497 switch ((val >> 5) & 0x3) {
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001498 case 0x0:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001499 ret = enable_flash_mcp55(dev, name);
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001500 internal_buses_supported = BUS_LPC;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001501 msg_pdbg("Flash bus type is LPC\n");
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001502 break;
1503 case 0x2:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001504 want_spi = 1;
1505 /* SPI is added in mcp6x_spi_init if it works.
1506 * Do we really want to disable LPC in this case?
1507 */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001508 internal_buses_supported = BUS_NONE;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001509 msg_pdbg("Flash bus type is SPI\n");
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001510 break;
1511 default:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001512 /* Should not happen. */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001513 internal_buses_supported = BUS_NONE;
Stefan Tauner7ba3d6c2014-06-12 21:07:03 +00001514 msg_pwarn("Flash bus type is unknown (none)\n");
Elyes HAOUASac01baa2018-05-28 16:52:21 +02001515 msg_pinfo("Please send the log files created by \"flashrom -p internal -o logfile\" to\n"
Stefan Tauner7ba3d6c2014-06-12 21:07:03 +00001516 "flashrom@flashrom.org with \"your board name: flashrom -V\" as the subject to\n"
1517 "help us finish support for your chipset. Thanks.\n");
1518 return ERROR_NONFATAL;
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001519 }
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001520
1521 /* Force enable SPI and disable LPC? Not a good idea. */
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001522#if 0
Michael Karchercfa674f2010-02-25 11:38:23 +00001523 val |= (1 << 6);
1524 val &= ~(1 << 5);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001525 rpci_write_byte(dev, 0x8a, val);
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001526#endif
1527
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001528 if (mcp6x_spi_init(want_spi))
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001529 ret = 1;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001530
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001531 return ret;
1532}
1533
Uwe Hermann372eeb52007-12-04 21:49:06 +00001534static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001535{
Michael Karchercfa674f2010-02-25 11:38:23 +00001536 uint8_t val;
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001537
Uwe Hermanne823ee02007-06-05 15:02:18 +00001538 /* Set the 4MB enable bit. */
Michael Karchercfa674f2010-02-25 11:38:23 +00001539 val = pci_read_byte(dev, 0x41);
1540 val |= 0x0e;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001541 rpci_write_byte(dev, 0x41, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001542
Michael Karchercfa674f2010-02-25 11:38:23 +00001543 val = pci_read_byte(dev, 0x43);
1544 val |= (1 << 4);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001545 rpci_write_byte(dev, 0x43, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001546
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001547 return 0;
1548}
1549
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001550/*
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001551 * Usually on the x86 architectures (and on other PC-like platforms like some
1552 * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
1553 * Elan SC520 only a small piece of the system flash is mapped there, but the
1554 * complete flash is mapped somewhere below 1G. The position can be determined
1555 * by the BOOTCS PAR register.
1556 */
1557static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
1558{
1559 int i, bootcs_found = 0;
1560 uint32_t parx = 0;
1561 void *mmcr;
1562
1563 /* 1. Map MMCR */
Stefan Reinauer0593f212009-01-26 01:10:48 +00001564 mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize());
Niklas Söderlund5d307202013-09-14 09:02:27 +00001565 if (mmcr == ERROR_PTR)
1566 return ERROR_FATAL;
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001567
1568 /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for
1569 * BOOTCS region (PARx[31:29] = 100b)e
1570 */
1571 for (i = 0x88; i <= 0xc4; i += 4) {
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +00001572 parx = mmio_readl(mmcr + i);
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001573 if ((parx >> 29) == 4) {
1574 bootcs_found = 1;
1575 break; /* BOOTCS found */
1576 }
1577 }
1578
1579 /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0]
1580 * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0]
1581 */
1582 if (bootcs_found) {
1583 if (parx & (1 << 25)) {
1584 parx &= (1 << 14) - 1; /* Mask [13:0] */
1585 flashbase = parx << 16;
1586 } else {
1587 parx &= (1 << 18) - 1; /* Mask [17:0] */
1588 flashbase = parx << 12;
1589 }
1590 } else {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001591 msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. "
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001592 "Assuming flash at 4G.\n");
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001593 }
1594
1595 /* 4. Clean up */
Carl-Daniel Hailfingerbe726812009-08-09 12:44:08 +00001596 physunmap(mmcr, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001597 return 0;
1598}
1599
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001600#endif
1601
Idwer Vollering326a0602011-06-18 18:45:41 +00001602/* Please keep this list numerically sorted by vendor/device ID. */
Uwe Hermann05fab752009-05-16 23:42:17 +00001603const struct penable chipset_enables[] = {
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001604#if defined(__i386__) || defined(__x86_64__)
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001605 {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400},
1606 {0x1002, 0x438d, OK, "AMD", "SB600", enable_flash_sb600},
1607 {0x1002, 0x439d, OK, "AMD", "SB7x0/SB8x0/SB9x0", enable_flash_sb600},
1608 {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100},
1609 {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536},
1610 {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536},
1611 {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520},
1612 {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd_768_8111},
1613 {0x1022, 0x7468, OK, "AMD", "AMD-8111", enable_flash_amd_768_8111},
1614 {0x1022, 0x780e, OK, "AMD", "FCH", enable_flash_sb600},
Ricardo Ribalda Delgado7b629bc2017-03-22 14:08:31 +01001615 {0x1022, 0x790e, OK, "AMD", "FP4", enable_flash_sb600},
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001616 {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501},
1617 {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496},
1618 {0x1039, 0x0530, OK, "SiS", "530", enable_flash_sis530},
1619 {0x1039, 0x0540, NT, "SiS", "540", enable_flash_sis540},
1620 {0x1039, 0x0620, NT, "SiS", "620", enable_flash_sis530},
Nico Huberbbf0dbd2017-11-19 16:29:45 +01001621 {0x1039, 0x0630, OK, "SiS", "630", enable_flash_sis540},
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001622 {0x1039, 0x0635, NT, "SiS", "635", enable_flash_sis540},
1623 {0x1039, 0x0640, NT, "SiS", "640", enable_flash_sis540},
1624 {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis540},
1625 {0x1039, 0x0646, OK, "SiS", "645DX", enable_flash_sis540},
1626 {0x1039, 0x0648, OK, "SiS", "648", enable_flash_sis540},
1627 {0x1039, 0x0650, OK, "SiS", "650", enable_flash_sis540},
1628 {0x1039, 0x0651, OK, "SiS", "651", enable_flash_sis540},
1629 {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis540},
1630 {0x1039, 0x0661, OK, "SiS", "661", enable_flash_sis540},
1631 {0x1039, 0x0730, OK, "SiS", "730", enable_flash_sis540},
1632 {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis540},
1633 {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis540},
1634 {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis540},
1635 {0x1039, 0x0741, OK, "SiS", "741", enable_flash_sis540},
1636 {0x1039, 0x0745, OK, "SiS", "745", enable_flash_sis540},
1637 {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540},
1638 {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540},
1639 {0x1039, 0x0755, OK, "SiS", "755", enable_flash_sis540},
1640 {0x1039, 0x5511, NT, "SiS", "5511", enable_flash_sis5511},
1641 {0x1039, 0x5571, NT, "SiS", "5571", enable_flash_sis530},
1642 {0x1039, 0x5591, NT, "SiS", "5591/5592", enable_flash_sis530},
1643 {0x1039, 0x5596, NT, "SiS", "5596", enable_flash_sis5511},
1644 {0x1039, 0x5597, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530},
1645 {0x1039, 0x5600, NT, "SiS", "600", enable_flash_sis530},
1646 {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530},
1647 {0x10b9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533},
1648 {0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2},
1649 {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */
1650 {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */
1651 {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2},
1652 {0x10de, 0x00e0, OK, "NVIDIA", "NForce3", enable_flash_nvidia_nforce2},
Uwe Hermanneac10162008-03-13 18:52:51 +00001653 /* Slave, should not be here, to fix known bug for A01. */
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001654 {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804},
1655 {0x10de, 0x0260, OK, "NVIDIA", "MCP51", enable_flash_ck804},
1656 {0x10de, 0x0261, OK, "NVIDIA", "MCP51", enable_flash_ck804},
1657 {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1658 {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1659 {0x10de, 0x0360, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/
Carl-Daniel Hailfinger33d7b6a2010-05-22 07:27:16 +00001660 /* 10de:0361 is present in Tyan S2915 OEM systems, but not connected to
1661 * the flash chip. Instead, 10de:0364 is connected to the flash chip.
1662 * Until we have PCI device class matching or some fallback mechanism,
1663 * this is needed to get flashrom working on Tyan S2915 and maybe other
1664 * dual-MCP55 boards.
1665 */
1666#if 0
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001667 {0x10de, 0x0361, NT, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
Carl-Daniel Hailfinger33d7b6a2010-05-22 07:27:16 +00001668#endif
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001669 {0x10de, 0x0362, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1670 {0x10de, 0x0363, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1671 {0x10de, 0x0364, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1672 {0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1673 {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1674 {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */
1675 {0x10de, 0x03e0, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1676 {0x10de, 0x03e1, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1677 {0x10de, 0x03e3, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1678 {0x10de, 0x0440, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1679 {0x10de, 0x0441, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1680 {0x10de, 0x0442, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1681 {0x10de, 0x0443, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1682 {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp6x_7x},
1683 {0x10de, 0x075c, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x},
1684 {0x10de, 0x075d, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x},
1685 {0x10de, 0x07d7, OK, "NVIDIA", "MCP73", enable_flash_mcp6x_7x},
1686 {0x10de, 0x0aac, OK, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1687 {0x10de, 0x0aad, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1688 {0x10de, 0x0aae, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1689 {0x10de, 0x0aaf, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1690 {0x10de, 0x0d80, NT, "NVIDIA", "MCP89", enable_flash_mcp6x_7x},
Michael Karcher89bed6d2010-06-13 10:16:12 +00001691 /* VIA northbridges */
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001692 {0x1106, 0x0585, NT, "VIA", "VT82C585VPX", via_no_byte_merge},
1693 {0x1106, 0x0595, NT, "VIA", "VT82C595", via_no_byte_merge},
1694 {0x1106, 0x0597, NT, "VIA", "VT82C597", via_no_byte_merge},
1695 {0x1106, 0x0601, NT, "VIA", "VT8601/VT8601A", via_no_byte_merge},
1696 {0x1106, 0x0691, OK, "VIA", "VT82C69x", via_no_byte_merge},
1697 {0x1106, 0x8601, NT, "VIA", "VT8601T", via_no_byte_merge},
Michael Karcher89bed6d2010-06-13 10:16:12 +00001698 /* VIA southbridges */
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001699 {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_vt82c586},
1700 {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_vt82c596},
1701 {0x1106, 0x0686, OK, "VIA", "VT82C686A/B", enable_flash_vt82c596},
1702 {0x1106, 0x3074, OK, "VIA", "VT8233", enable_flash_vt823x},
1703 {0x1106, 0x3147, OK, "VIA", "VT8233A", enable_flash_vt823x},
1704 {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x},
1705 {0x1106, 0x3227, OK, "VIA", "VT8237(R)", enable_flash_vt823x},
Stefan Tauner94d86652015-11-21 23:35:47 +00001706 {0x1106, 0x3287, OK, "VIA", "VT8251", enable_flash_vt823x},
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001707 {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x},
1708 {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi},
1709 {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x},
1710 {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x},
1711 {0x1106, 0x8353, NT, "VIA", "VX800/VX820", enable_flash_vt_vx},
Lubomir Rintel305a2b32018-01-08 05:31:55 +01001712 {0x1106, 0x8409, OK, "VIA", "VX855/VX875", enable_flash_vt_vx},
Lubomir Rintel73c88202017-12-28 20:19:21 +01001713 {0x1106, 0x8410, OK, "VIA", "VX900", enable_flash_vt_vx},
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001714 {0x1166, 0x0200, OK, "Broadcom", "OSB4", enable_flash_osb4},
1715 {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000},
1716 {0x17f3, 0x6030, OK, "RDC", "R8610/R3210", enable_flash_rdc_r8610},
1717 {0x8086, 0x0c60, NT, "Intel", "S12x0", enable_flash_s12x0},
Stefan Tauner5c316f92015-02-08 21:57:52 +00001718 {0x8086, 0x0f1c, OK, "Intel", "Bay Trail", enable_flash_silvermont},
Duncan Laurie4095ed72014-08-20 15:39:32 +00001719 {0x8086, 0x0f1d, NT, "Intel", "Bay Trail", enable_flash_silvermont},
1720 {0x8086, 0x0f1e, NT, "Intel", "Bay Trail", enable_flash_silvermont},
1721 {0x8086, 0x0f1f, NT, "Intel", "Bay Trail", enable_flash_silvermont},
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001722 {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4},
1723 {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4},
1724 {0x8086, 0x1c44, DEP, "Intel", "Z68", enable_flash_pch6},
1725 {0x8086, 0x1c46, DEP, "Intel", "P67", enable_flash_pch6},
1726 {0x8086, 0x1c47, NT, "Intel", "UM67", enable_flash_pch6},
1727 {0x8086, 0x1c49, NT, "Intel", "HM65", enable_flash_pch6},
1728 {0x8086, 0x1c4a, DEP, "Intel", "H67", enable_flash_pch6},
1729 {0x8086, 0x1c4b, NT, "Intel", "HM67", enable_flash_pch6},
1730 {0x8086, 0x1c4c, NT, "Intel", "Q65", enable_flash_pch6},
1731 {0x8086, 0x1c4d, NT, "Intel", "QS67", enable_flash_pch6},
1732 {0x8086, 0x1c4e, NT, "Intel", "Q67", enable_flash_pch6},
1733 {0x8086, 0x1c4f, DEP, "Intel", "QM67", enable_flash_pch6},
1734 {0x8086, 0x1c50, NT, "Intel", "B65", enable_flash_pch6},
1735 {0x8086, 0x1c52, NT, "Intel", "C202", enable_flash_pch6},
1736 {0x8086, 0x1c54, DEP, "Intel", "C204", enable_flash_pch6},
1737 {0x8086, 0x1c56, NT, "Intel", "C206", enable_flash_pch6},
1738 {0x8086, 0x1c5c, DEP, "Intel", "H61", enable_flash_pch6},
1739 {0x8086, 0x1d40, DEP, "Intel", "C60x/X79", enable_flash_pch6},
1740 {0x8086, 0x1d41, DEP, "Intel", "C60x/X79", enable_flash_pch6},
1741 {0x8086, 0x1e44, DEP, "Intel", "Z77", enable_flash_pch7},
1742 {0x8086, 0x1e46, NT, "Intel", "Z75", enable_flash_pch7},
1743 {0x8086, 0x1e47, NT, "Intel", "Q77", enable_flash_pch7},
1744 {0x8086, 0x1e48, NT, "Intel", "Q75", enable_flash_pch7},
1745 {0x8086, 0x1e49, DEP, "Intel", "B75", enable_flash_pch7},
1746 {0x8086, 0x1e4a, DEP, "Intel", "H77", enable_flash_pch7},
1747 {0x8086, 0x1e53, NT, "Intel", "C216", enable_flash_pch7},
1748 {0x8086, 0x1e55, DEP, "Intel", "QM77", enable_flash_pch7},
1749 {0x8086, 0x1e56, NT, "Intel", "QS77", enable_flash_pch7},
1750 {0x8086, 0x1e57, DEP, "Intel", "HM77", enable_flash_pch7},
1751 {0x8086, 0x1e58, NT, "Intel", "UM77", enable_flash_pch7},
1752 {0x8086, 0x1e59, NT, "Intel", "HM76", enable_flash_pch7},
1753 {0x8086, 0x1e5d, NT, "Intel", "HM75", enable_flash_pch7},
1754 {0x8086, 0x1e5e, NT, "Intel", "HM70", enable_flash_pch7},
1755 {0x8086, 0x1e5f, DEP, "Intel", "NM70", enable_flash_pch7},
Stefan Tauner23e10b82016-01-23 16:16:49 +00001756 {0x8086, 0x1f38, DEP, "Intel", "Avoton/Rangeley", enable_flash_silvermont},
Duncan Laurie4095ed72014-08-20 15:39:32 +00001757 {0x8086, 0x1f39, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont},
1758 {0x8086, 0x1f3a, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont},
1759 {0x8086, 0x1f3b, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont},
David Hendricksa1bccd82017-08-08 23:28:54 -07001760 {0x8086, 0x229c, OK, "Intel", "Braswell", enable_flash_silvermont},
Duncan Laurie4095ed72014-08-20 15:39:32 +00001761 {0x8086, 0x2310, NT, "Intel", "DH89xxCC (Cave Creek)", enable_flash_pch7},
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001762 {0x8086, 0x2390, NT, "Intel", "Coleto Creek", enable_flash_pch7},
1763 {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich0},
1764 {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich0},
1765 {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich2345},
1766 {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich2345},
1767 {0x8086, 0x2450, NT, "Intel", "C-ICH", enable_flash_ich2345},
1768 {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich2345},
1769 {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich2345},
1770 {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich2345},
1771 {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich2345},
1772 {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich2345},
1773 {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich2345},
1774 {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich6},
1775 {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich6},
1776 {0x8086, 0x2642, NT, "Intel", "ICH6W/ICH6RW", enable_flash_ich6},
1777 {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich6},
1778 {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7},
1779 {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7},
1780 {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7},
1781 {0x8086, 0x27bc, OK, "Intel", "NM10", enable_flash_ich7},
1782 {0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7},
1783 {0x8086, 0x2810, DEP, "Intel", "ICH8/ICH8R", enable_flash_ich8},
1784 {0x8086, 0x2811, DEP, "Intel", "ICH8M-E", enable_flash_ich8},
1785 {0x8086, 0x2812, DEP, "Intel", "ICH8DH", enable_flash_ich8},
1786 {0x8086, 0x2814, DEP, "Intel", "ICH8DO", enable_flash_ich8},
1787 {0x8086, 0x2815, DEP, "Intel", "ICH8M", enable_flash_ich8},
1788 {0x8086, 0x2910, DEP, "Intel", "ICH9 Eng. Sample", enable_flash_ich9},
1789 {0x8086, 0x2912, DEP, "Intel", "ICH9DH", enable_flash_ich9},
1790 {0x8086, 0x2914, DEP, "Intel", "ICH9DO", enable_flash_ich9},
1791 {0x8086, 0x2916, DEP, "Intel", "ICH9R", enable_flash_ich9},
1792 {0x8086, 0x2917, DEP, "Intel", "ICH9M-E", enable_flash_ich9},
1793 {0x8086, 0x2918, DEP, "Intel", "ICH9", enable_flash_ich9},
1794 {0x8086, 0x2919, DEP, "Intel", "ICH9M", enable_flash_ich9},
1795 {0x8086, 0x3a10, NT, "Intel", "ICH10R Eng. Sample", enable_flash_ich10},
1796 {0x8086, 0x3a14, DEP, "Intel", "ICH10DO", enable_flash_ich10},
1797 {0x8086, 0x3a16, DEP, "Intel", "ICH10R", enable_flash_ich10},
1798 {0x8086, 0x3a18, DEP, "Intel", "ICH10", enable_flash_ich10},
1799 {0x8086, 0x3a1a, DEP, "Intel", "ICH10D", enable_flash_ich10},
1800 {0x8086, 0x3a1e, NT, "Intel", "ICH10 Eng. Sample", enable_flash_ich10},
1801 {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_pch5},
1802 {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_pch5},
1803 {0x8086, 0x3b02, NT, "Intel", "P55", enable_flash_pch5},
1804 {0x8086, 0x3b03, NT, "Intel", "PM55", enable_flash_pch5},
1805 {0x8086, 0x3b06, DEP, "Intel", "H55", enable_flash_pch5},
1806 {0x8086, 0x3b07, DEP, "Intel", "QM57", enable_flash_pch5},
1807 {0x8086, 0x3b08, NT, "Intel", "H57", enable_flash_pch5},
Angel Ponsccfa8f92018-08-21 03:30:58 +02001808 {0x8086, 0x3b09, DEP, "Intel", "HM55", enable_flash_pch5},
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001809 {0x8086, 0x3b0a, NT, "Intel", "Q57", enable_flash_pch5},
1810 {0x8086, 0x3b0b, NT, "Intel", "HM57", enable_flash_pch5},
1811 {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_pch5},
1812 {0x8086, 0x3b0e, NT, "Intel", "B55", enable_flash_pch5},
1813 {0x8086, 0x3b0f, DEP, "Intel", "QS57", enable_flash_pch5},
1814 {0x8086, 0x3b12, NT, "Intel", "3400", enable_flash_pch5},
1815 {0x8086, 0x3b14, DEP, "Intel", "3420", enable_flash_pch5},
1816 {0x8086, 0x3b16, NT, "Intel", "3450", enable_flash_pch5},
1817 {0x8086, 0x3b1e, NT, "Intel", "B55", enable_flash_pch5},
1818 {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7},
1819 {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4},
1820 {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4},
1821 {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4},
1822 {0x8086, 0x8119, OK, "Intel", "SCH Poulsbo", enable_flash_poulsbo},
Duncan Laurie4095ed72014-08-20 15:39:32 +00001823 {0x8086, 0x8186, OK, "Intel", "Atom E6xx(T) (Tunnel Creek)", enable_flash_tunnelcreek},
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001824 {0x8086, 0x8c40, NT, "Intel", "Lynx Point", enable_flash_pch8},
1825 {0x8086, 0x8c41, NT, "Intel", "Lynx Point Mobile Eng. Sample", enable_flash_pch8},
1826 {0x8086, 0x8c42, NT, "Intel", "Lynx Point Desktop Eng. Sample",enable_flash_pch8},
1827 {0x8086, 0x8c43, NT, "Intel", "Lynx Point", enable_flash_pch8},
1828 {0x8086, 0x8c44, DEP, "Intel", "Z87", enable_flash_pch8},
1829 {0x8086, 0x8c45, NT, "Intel", "Lynx Point", enable_flash_pch8},
1830 {0x8086, 0x8c46, NT, "Intel", "Z85", enable_flash_pch8},
1831 {0x8086, 0x8c47, NT, "Intel", "Lynx Point", enable_flash_pch8},
1832 {0x8086, 0x8c48, NT, "Intel", "Lynx Point", enable_flash_pch8},
1833 {0x8086, 0x8c49, NT, "Intel", "HM86", enable_flash_pch8},
1834 {0x8086, 0x8c4a, DEP, "Intel", "H87", enable_flash_pch8},
1835 {0x8086, 0x8c4b, DEP, "Intel", "HM87", enable_flash_pch8},
1836 {0x8086, 0x8c4c, NT, "Intel", "Q85", enable_flash_pch8},
1837 {0x8086, 0x8c4d, NT, "Intel", "Lynx Point", enable_flash_pch8},
1838 {0x8086, 0x8c4e, NT, "Intel", "Q87", enable_flash_pch8},
1839 {0x8086, 0x8c4f, NT, "Intel", "QM87", enable_flash_pch8},
1840 {0x8086, 0x8c50, DEP, "Intel", "B85", enable_flash_pch8},
1841 {0x8086, 0x8c51, NT, "Intel", "Lynx Point", enable_flash_pch8},
1842 {0x8086, 0x8c52, NT, "Intel", "C222", enable_flash_pch8},
1843 {0x8086, 0x8c53, NT, "Intel", "Lynx Point", enable_flash_pch8},
1844 {0x8086, 0x8c54, NT, "Intel", "C224", enable_flash_pch8},
1845 {0x8086, 0x8c55, NT, "Intel", "Lynx Point", enable_flash_pch8},
1846 {0x8086, 0x8c56, NT, "Intel", "C226", enable_flash_pch8},
1847 {0x8086, 0x8c57, NT, "Intel", "Lynx Point", enable_flash_pch8},
1848 {0x8086, 0x8c58, NT, "Intel", "Lynx Point", enable_flash_pch8},
1849 {0x8086, 0x8c59, NT, "Intel", "Lynx Point", enable_flash_pch8},
1850 {0x8086, 0x8c5a, NT, "Intel", "Lynx Point", enable_flash_pch8},
1851 {0x8086, 0x8c5b, NT, "Intel", "Lynx Point", enable_flash_pch8},
1852 {0x8086, 0x8c5c, NT, "Intel", "H81", enable_flash_pch8},
1853 {0x8086, 0x8c5d, NT, "Intel", "Lynx Point", enable_flash_pch8},
1854 {0x8086, 0x8c5e, NT, "Intel", "Lynx Point", enable_flash_pch8},
1855 {0x8086, 0x8c5f, NT, "Intel", "Lynx Point", enable_flash_pch8},
Stefan Tauner5c316f92015-02-08 21:57:52 +00001856 {0x8086, 0x8cc1, NT, "Intel", "9 Series", enable_flash_pch9},
1857 {0x8086, 0x8cc2, NT, "Intel", "9 Series Engineering Sample", enable_flash_pch9},
1858 {0x8086, 0x8cc3, NT, "Intel", "9 Series", enable_flash_pch9},
1859 {0x8086, 0x8cc4, NT, "Intel", "Z97", enable_flash_pch9},
1860 {0x8086, 0x8cc6, NT, "Intel", "H97", enable_flash_pch9},
1861 {0x8086, 0x8d40, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1862 {0x8086, 0x8d41, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1863 {0x8086, 0x8d42, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1864 {0x8086, 0x8d43, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1865 {0x8086, 0x8d44, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1866 {0x8086, 0x8d45, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1867 {0x8086, 0x8d46, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1868 {0x8086, 0x8d47, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1869 {0x8086, 0x8d48, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1870 {0x8086, 0x8d49, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1871 {0x8086, 0x8d4a, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1872 {0x8086, 0x8d4b, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1873 {0x8086, 0x8d4c, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1874 {0x8086, 0x8d4d, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1875 {0x8086, 0x8d4e, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1876 {0x8086, 0x8d4f, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1877 {0x8086, 0x8d50, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1878 {0x8086, 0x8d51, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1879 {0x8086, 0x8d52, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1880 {0x8086, 0x8d53, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1881 {0x8086, 0x8d54, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1882 {0x8086, 0x8d55, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1883 {0x8086, 0x8d56, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1884 {0x8086, 0x8d57, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1885 {0x8086, 0x8d58, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1886 {0x8086, 0x8d59, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1887 {0x8086, 0x8d5a, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1888 {0x8086, 0x8d5b, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1889 {0x8086, 0x8d5c, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1890 {0x8086, 0x8d5d, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1891 {0x8086, 0x8d5e, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
1892 {0x8086, 0x8d5f, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb},
Stefan Tauner428ba2b2014-06-02 00:34:58 +00001893 {0x8086, 0x9c41, NT, "Intel", "Lynx Point LP Eng. Sample", enable_flash_pch8_lp},
1894 {0x8086, 0x9c43, NT, "Intel", "Lynx Point LP Premium", enable_flash_pch8_lp},
1895 {0x8086, 0x9c45, NT, "Intel", "Lynx Point LP Mainstream", enable_flash_pch8_lp},
1896 {0x8086, 0x9c47, NT, "Intel", "Lynx Point LP Value", enable_flash_pch8_lp},
Nico Huber51205912017-03-17 17:59:54 +01001897 {0x8086, 0x9cc1, NT, "Intel", "Haswell U Sample", enable_flash_pch9_lp},
1898 {0x8086, 0x9cc2, NT, "Intel", "Broadwell U Sample", enable_flash_pch9_lp},
Angel Ponsc4d3efb2018-09-30 19:39:41 +02001899 {0x8086, 0x9cc3, DEP, "Intel", "Broadwell U Premium", enable_flash_pch9_lp},
Nico Huber51205912017-03-17 17:59:54 +01001900 {0x8086, 0x9cc5, NT, "Intel", "Broadwell U Base", enable_flash_pch9_lp},
1901 {0x8086, 0x9cc6, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9_lp},
1902 {0x8086, 0x9cc7, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9_lp},
1903 {0x8086, 0x9cc9, NT, "Intel", "Broadwell Y Base", enable_flash_pch9_lp},
Duncan Laurie823096e2014-08-20 15:39:38 +00001904 {0x8086, 0x9ccb, NT, "Intel", "Broadwell H", enable_flash_pch9},
Nico Huber50026342017-03-29 18:24:32 +02001905 {0x8086, 0x9d41, NT, "Intel", "Skylake / Kaby Lake Sample", enable_flash_pch100},
1906 {0x8086, 0x9d43, NT, "Intel", "Skylake U Base", enable_flash_pch100},
1907 {0x8086, 0x9d46, NT, "Intel", "Skylake Y Premium", enable_flash_pch100},
1908 {0x8086, 0x9d48, NT, "Intel", "Skylake U Premium", enable_flash_pch100},
1909 {0x8086, 0x9d4b, NT, "Intel", "Kaby Lake Y w/ iHDCP2.2 Prem.", enable_flash_pch100},
1910 {0x8086, 0x9d4e, NT, "Intel", "Kaby Lake U w/ iHDCP2.2 Prem.", enable_flash_pch100},
1911 {0x8086, 0x9d50, NT, "Intel", "Kaby Lake U w/ iHDCP2.2 Base", enable_flash_pch100},
1912 {0x8086, 0x9d51, NT, "Intel", "Kabe Lake w/ iHDCP2.2 Sample", enable_flash_pch100},
1913 {0x8086, 0x9d53, NT, "Intel", "Kaby Lake U Base", enable_flash_pch100},
1914 {0x8086, 0x9d56, NT, "Intel", "Kaby Lake Y Premium", enable_flash_pch100},
1915 {0x8086, 0x9d58, NT, "Intel", "Kaby Lake U Premium", enable_flash_pch100},
1916 {0x8086, 0xa141, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100},
1917 {0x8086, 0xa142, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100},
1918 {0x8086, 0xa143, NT, "Intel", "H110", enable_flash_pch100},
1919 {0x8086, 0xa144, NT, "Intel", "H170", enable_flash_pch100},
1920 {0x8086, 0xa145, NT, "Intel", "Z170", enable_flash_pch100},
1921 {0x8086, 0xa146, NT, "Intel", "Q170", enable_flash_pch100},
1922 {0x8086, 0xa147, NT, "Intel", "Q150", enable_flash_pch100},
1923 {0x8086, 0xa148, NT, "Intel", "B150", enable_flash_pch100},
1924 {0x8086, 0xa149, NT, "Intel", "C236", enable_flash_pch100},
1925 {0x8086, 0xa14a, NT, "Intel", "C232", enable_flash_pch100},
1926 {0x8086, 0xa14b, NT, "Intel", "Sunrise Point Server Sample", enable_flash_pch100},
1927 {0x8086, 0xa14d, NT, "Intel", "QM170", enable_flash_pch100},
1928 {0x8086, 0xa14e, NT, "Intel", "HM170", enable_flash_pch100},
1929 {0x8086, 0xa150, NT, "Intel", "CM236", enable_flash_pch100},
1930 {0x8086, 0xa151, NT, "Intel", "QMS180", enable_flash_pch100},
1931 {0x8086, 0xa152, NT, "Intel", "HM175", enable_flash_pch100},
1932 {0x8086, 0xa153, NT, "Intel", "QM175", enable_flash_pch100},
1933 {0x8086, 0xa154, NT, "Intel", "CM238", enable_flash_pch100},
1934 {0x8086, 0xa155, NT, "Intel", "QMU185", enable_flash_pch100},
David Hendricksa5216362017-08-08 20:02:22 -07001935 {0x8086, 0xa1c1, NT, "Intel", "C621 Series Chipset (QS/PRQ)", enable_flash_c620},
1936 {0x8086, 0xa1c2, NT, "Intel", "C622 Series Chipset (QS/PRQ)", enable_flash_c620},
1937 {0x8086, 0xa1c3, NT, "Intel", "C624 Series Chipset (QS/PRQ)", enable_flash_c620},
1938 {0x8086, 0xa1c4, NT, "Intel", "C625 Series Chipset (QS/PRQ)", enable_flash_c620},
1939 {0x8086, 0xa1c5, NT, "Intel", "C626 Series Chipset (QS/PRQ)", enable_flash_c620},
1940 {0x8086, 0xa1c6, NT, "Intel", "C627 Series Chipset (QS/PRQ)", enable_flash_c620},
1941 {0x8086, 0xa1c7, NT, "Intel", "C628 Series Chipset (QS/PRQ)", enable_flash_c620},
1942 {0x8086, 0xa242, NT, "Intel", "C624 Series Chipset Supersku", enable_flash_c620},
1943 {0x8086, 0xa243, NT, "Intel", "C627 Series Chipset Supersku", enable_flash_c620},
1944 {0x8086, 0xa244, NT, "Intel", "C621 Series Chipset Supersku", enable_flash_c620},
1945 {0x8086, 0xa245, NT, "Intel", "C627 Series Chipset Supersku", enable_flash_c620},
1946 {0x8086, 0xa246, NT, "Intel", "C628 Series Chipset Supersku", enable_flash_c620},
1947 {0x8086, 0xa247, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620},
Nico Hubera50b8fd2017-03-20 14:25:09 +01001948 {0x8086, 0xa2c4, NT, "Intel", "H270", enable_flash_pch100},
1949 {0x8086, 0xa2c5, NT, "Intel", "Z270", enable_flash_pch100},
1950 {0x8086, 0xa2c6, NT, "Intel", "Q270", enable_flash_pch100},
1951 {0x8086, 0xa2c7, NT, "Intel", "Q250", enable_flash_pch100},
1952 {0x8086, 0xa2c8, NT, "Intel", "B250", enable_flash_pch100},
1953 {0x8086, 0xa2c9, NT, "Intel", "Z370", enable_flash_pch100},
1954 {0x8086, 0xa2d2, NT, "Intel", "X299", enable_flash_pch100},
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001955#endif
Carl-Daniel Hailfinger1c6d2ff2012-08-27 00:44:42 +00001956 {0},
Ollie Lhocbbf1252004-03-17 22:22:08 +00001957};
Ollie Lho761bf1b2004-03-20 16:46:10 +00001958
Uwe Hermanna7e05482007-05-09 10:17:44 +00001959int chipset_flash_enable(void)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001960{
Peter Huewe73f8ec82011-01-24 19:15:51 +00001961 struct pci_dev *dev = NULL;
Uwe Hermann372eeb52007-12-04 21:49:06 +00001962 int ret = -2; /* Nothing! */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001963 int i;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001964
Uwe Hermann372eeb52007-12-04 21:49:06 +00001965 /* Now let's try to find the chipset we have... */
Uwe Hermann05fab752009-05-16 23:42:17 +00001966 for (i = 0; chipset_enables[i].vendor_name != NULL; i++) {
1967 dev = pci_dev_find(chipset_enables[i].vendor_id,
1968 chipset_enables[i].device_id);
Michael Karcher89bed6d2010-06-13 10:16:12 +00001969 if (!dev)
1970 continue;
1971 if (ret != -2) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00001972 msg_pwarn("Warning: unexpected second chipset match: "
Paul Menzelab6328f2010-10-08 11:03:02 +00001973 "\"%s %s\"\n"
1974 "ignoring, please report lspci and board URL "
1975 "to flashrom@flashrom.org\n"
Stefan Reinauerbf282b12011-03-29 21:41:41 +00001976 "with \'CHIPSET: your board name\' in the "
Paul Menzelab6328f2010-10-08 11:03:02 +00001977 "subject line.\n",
Michael Karcher89bed6d2010-06-13 10:16:12 +00001978 chipset_enables[i].vendor_name,
1979 chipset_enables[i].device_name);
1980 continue;
1981 }
Stefan Taunerec8c2482011-07-21 19:59:34 +00001982 msg_pinfo("Found chipset \"%s %s\"",
1983 chipset_enables[i].vendor_name,
1984 chipset_enables[i].device_name);
Stefan Tauner716e0982011-07-25 20:38:52 +00001985 msg_pdbg(" with PCI ID %04x:%04x",
Carl-Daniel Hailfingerf469c272010-05-22 07:31:50 +00001986 chipset_enables[i].vendor_id,
1987 chipset_enables[i].device_id);
Stefan Tauner5c316f92015-02-08 21:57:52 +00001988 msg_pinfo(".\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00001989
Stefan Tauner23e10b82016-01-23 16:16:49 +00001990 if (chipset_enables[i].status == BAD) {
1991 msg_perr("ERROR: This chipset is not supported yet.\n");
1992 return ERROR_FATAL;
1993 }
Stefan Taunerec8c2482011-07-21 19:59:34 +00001994 if (chipset_enables[i].status == NT) {
Stefan Tauner5c316f92015-02-08 21:57:52 +00001995 msg_pinfo("This chipset is marked as untested. If "
Stefan Taunerec8c2482011-07-21 19:59:34 +00001996 "you are using an up-to-date version\nof "
Stefan Tauner2abab942012-04-27 20:41:23 +00001997 "flashrom *and* were (not) able to "
1998 "successfully update your firmware with it,\n"
1999 "then please email a report to "
2000 "flashrom@flashrom.org including a verbose "
2001 "(-V) log.\nThank you!\n");
Stefan Taunerec8c2482011-07-21 19:59:34 +00002002 }
2003 msg_pinfo("Enabling flash write... ");
Stefan Tauner23e10b82016-01-23 16:16:49 +00002004 ret = chipset_enables[i].doit(dev, chipset_enables[i].device_name);
Michael Karcher89bed6d2010-06-13 10:16:12 +00002005 if (ret == NOT_DONE_YET) {
2006 ret = -2;
2007 msg_pinfo("OK - searching further chips.\n");
2008 } else if (ret < 0)
Sean Nelson316a29f2010-05-07 20:09:04 +00002009 msg_pinfo("FAILED!\n");
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002010 else if (ret == 0)
Sean Nelson316a29f2010-05-07 20:09:04 +00002011 msg_pinfo("OK.\n");
Uwe Hermann91f4afa2011-07-28 08:13:25 +00002012 else if (ret == ERROR_NONFATAL)
Michael Karchera4448d92010-07-22 18:04:15 +00002013 msg_pinfo("PROBLEMS, continuing anyway\n");
Tadas Slotkusad470342011-09-03 17:15:00 +00002014 if (ret == ERROR_FATAL) {
2015 msg_perr("FATAL ERROR!\n");
2016 return ret;
2017 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00002018 }
Michael Karcher89bed6d2010-06-13 10:16:12 +00002019
Uwe Hermanna7e05482007-05-09 10:17:44 +00002020 return ret;
Ollie Lhocbbf1252004-03-17 22:22:08 +00002021}