chipset_enable: Add PCI IDs for discrete Kaby Lake PCHs
The Kaby Lake "200 Series" PCHs [1,2] share the register layout of their
Skylake "100 Series" siblings.
[1] Intel® 200 Series (including X299) and Intel® Z370 Series
Chipset Families Platform Controller Hub (PCH)
Datasheet - Volume 1 of 2
Revision 003
Document Number 335192
[2] Intel® 200 Series (including X299) Chipset Family Platform
Controller Hub (PCH)
Datasheet - Volume 2 of 2
Revision 003
Document Number 335193
Change-Id: Ida545d69ec998a5d3ae4dc88e76adbb13952bceb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
diff --git a/chipset_enable.c b/chipset_enable.c
index 15b760b..5c874f5 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -1945,6 +1945,13 @@
{0x8086, 0xa245, NT, "Intel", "C627 Series Chipset Supersku", enable_flash_c620},
{0x8086, 0xa246, NT, "Intel", "C628 Series Chipset Supersku", enable_flash_c620},
{0x8086, 0xa247, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620},
+ {0x8086, 0xa2c4, NT, "Intel", "H270", enable_flash_pch100},
+ {0x8086, 0xa2c5, NT, "Intel", "Z270", enable_flash_pch100},
+ {0x8086, 0xa2c6, NT, "Intel", "Q270", enable_flash_pch100},
+ {0x8086, 0xa2c7, NT, "Intel", "Q250", enable_flash_pch100},
+ {0x8086, 0xa2c8, NT, "Intel", "B250", enable_flash_pch100},
+ {0x8086, 0xa2c9, NT, "Intel", "Z370", enable_flash_pch100},
+ {0x8086, 0xa2d2, NT, "Intel", "X299", enable_flash_pch100},
#endif
{0},
};