Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 1 | /* |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 2 | * This file is part of the flashrom project. |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 3 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 4 | * Copyright (C) 2000 Silicon Integrated System Corporation |
Stefan Reinauer | 8fa6481 | 2009-08-12 09:27:45 +0000 | [diff] [blame] | 5 | * Copyright (C) 2005-2009 coresystems GmbH |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 6 | * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de> |
Carl-Daniel Hailfinger | 2a9e245 | 2009-12-17 15:20:01 +0000 | [diff] [blame] | 7 | * Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger |
Adam Jurkowski | e498410 | 2009-12-21 15:30:46 +0000 | [diff] [blame] | 8 | * Copyright (C) 2009 Kontron Modular Computers GmbH |
Helge Wagner | dd73d83 | 2012-08-24 23:03:46 +0000 | [diff] [blame] | 9 | * Copyright (C) 2011, 2012 Stefan Tauner |
Nico Huber | 93c3069 | 2017-03-20 14:25:09 +0100 | [diff] [blame] | 10 | * Copyright (C) 2017 secunet Security Networks AG |
| 11 | * (Written by Nico Huber <nico.huber@secunet.com> for secunet) |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 12 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 13 | * This program is free software; you can redistribute it and/or modify |
| 14 | * it under the terms of the GNU General Public License as published by |
| 15 | * the Free Software Foundation; version 2 of the License. |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 16 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 25 | */ |
| 26 | |
| 27 | /* |
| 28 | * Contains the chipset specific flash enables. |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 29 | */ |
| 30 | |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 31 | #define _LARGEFILE64_SOURCE |
| 32 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 33 | #include <stdlib.h> |
Uwe Hermann | e8ba538 | 2009-05-22 11:37:27 +0000 | [diff] [blame] | 34 | #include <string.h> |
Carl-Daniel Hailfinger | dcef67e | 2010-06-21 23:20:15 +0000 | [diff] [blame] | 35 | #include <unistd.h> |
Carl-Daniel Hailfinger | 46fa068 | 2011-07-25 22:44:09 +0000 | [diff] [blame] | 36 | #include <inttypes.h> |
| 37 | #include <errno.h> |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 38 | #include "flash.h" |
Carl-Daniel Hailfinger | 5b997c3 | 2010-07-27 22:41:39 +0000 | [diff] [blame] | 39 | #include "programmer.h" |
Patrick Georgi | 32508eb | 2012-07-20 20:35:14 +0000 | [diff] [blame] | 40 | #include "hwaccess.h" |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 41 | |
Michael Karcher | 89bed6d | 2010-06-13 10:16:12 +0000 | [diff] [blame] | 42 | #define NOT_DONE_YET 1 |
| 43 | |
Carl-Daniel Hailfinger | 1d3a2fe | 2010-07-27 22:03:46 +0000 | [diff] [blame] | 44 | #if defined(__i386__) || defined(__x86_64__) |
| 45 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 46 | static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 47 | { |
| 48 | uint8_t tmp; |
| 49 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 50 | /* |
| 51 | * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and |
| 52 | * 0xFFFE0000-0xFFFFFFFF ROM select enable. |
| 53 | */ |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 54 | tmp = pci_read_byte(dev, 0x47); |
| 55 | tmp |= 0x46; |
Carl-Daniel Hailfinger | 2bee8cf | 2010-11-10 15:25:18 +0000 | [diff] [blame] | 56 | rpci_write_byte(dev, 0x47, tmp); |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 57 | |
| 58 | return 0; |
| 59 | } |
| 60 | |
Rudolf Marek | 23907d8 | 2012-02-07 21:29:48 +0000 | [diff] [blame] | 61 | static int enable_flash_rdc_r8610(struct pci_dev *dev, const char *name) |
| 62 | { |
| 63 | uint8_t tmp; |
| 64 | |
| 65 | /* enable ROMCS for writes */ |
| 66 | tmp = pci_read_byte(dev, 0x43); |
| 67 | tmp |= 0x80; |
| 68 | pci_write_byte(dev, 0x43, tmp); |
| 69 | |
| 70 | /* read the bootstrapping register */ |
| 71 | tmp = pci_read_byte(dev, 0x40) & 0x3; |
| 72 | switch (tmp) { |
| 73 | case 3: |
| 74 | internal_buses_supported = BUS_FWH; |
| 75 | break; |
| 76 | case 2: |
| 77 | internal_buses_supported = BUS_LPC; |
| 78 | break; |
| 79 | default: |
| 80 | internal_buses_supported = BUS_PARALLEL; |
| 81 | break; |
| 82 | } |
| 83 | |
| 84 | return 0; |
| 85 | } |
| 86 | |
Carl-Daniel Hailfinger | 9f46cfc | 2009-11-15 17:13:29 +0000 | [diff] [blame] | 87 | static int enable_flash_sis85c496(struct pci_dev *dev, const char *name) |
| 88 | { |
| 89 | uint8_t tmp; |
| 90 | |
| 91 | tmp = pci_read_byte(dev, 0xd0); |
| 92 | tmp |= 0xf8; |
Carl-Daniel Hailfinger | 2bee8cf | 2010-11-10 15:25:18 +0000 | [diff] [blame] | 93 | rpci_write_byte(dev, 0xd0, tmp); |
Carl-Daniel Hailfinger | 9f46cfc | 2009-11-15 17:13:29 +0000 | [diff] [blame] | 94 | |
| 95 | return 0; |
| 96 | } |
| 97 | |
| 98 | static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name) |
| 99 | { |
Stefan Tauner | e34e3e8 | 2013-01-01 00:06:51 +0000 | [diff] [blame] | 100 | #define SIS_MAPREG 0x40 |
Carl-Daniel Hailfinger | 9f46cfc | 2009-11-15 17:13:29 +0000 | [diff] [blame] | 101 | uint8_t new, newer; |
| 102 | |
| 103 | /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */ |
| 104 | /* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */ |
Stefan Tauner | e34e3e8 | 2013-01-01 00:06:51 +0000 | [diff] [blame] | 105 | new = pci_read_byte(dev, SIS_MAPREG); |
Carl-Daniel Hailfinger | 9f46cfc | 2009-11-15 17:13:29 +0000 | [diff] [blame] | 106 | new &= (~0x04); /* No idea why we clear bit 2. */ |
| 107 | new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */ |
Stefan Tauner | e34e3e8 | 2013-01-01 00:06:51 +0000 | [diff] [blame] | 108 | rpci_write_byte(dev, SIS_MAPREG, new); |
| 109 | newer = pci_read_byte(dev, SIS_MAPREG); |
| 110 | if (newer != new) { /* FIXME: share this with other code? */ |
| 111 | msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", |
| 112 | SIS_MAPREG, new, name); |
| 113 | msg_pinfo("Stuck at 0x%02x.\n", newer); |
Carl-Daniel Hailfinger | 9f46cfc | 2009-11-15 17:13:29 +0000 | [diff] [blame] | 114 | return -1; |
| 115 | } |
| 116 | return 0; |
| 117 | } |
| 118 | |
| 119 | static struct pci_dev *find_southbridge(uint16_t vendor, const char *name) |
| 120 | { |
| 121 | struct pci_dev *sbdev; |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 122 | |
Carl-Daniel Hailfinger | 9f46cfc | 2009-11-15 17:13:29 +0000 | [diff] [blame] | 123 | sbdev = pci_dev_find_vendorclass(vendor, 0x0601); |
| 124 | if (!sbdev) |
| 125 | sbdev = pci_dev_find_vendorclass(vendor, 0x0680); |
| 126 | if (!sbdev) |
| 127 | sbdev = pci_dev_find_vendorclass(vendor, 0x0000); |
| 128 | if (!sbdev) |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 129 | msg_perr("No southbridge found for %s!\n", name); |
Carl-Daniel Hailfinger | 9f46cfc | 2009-11-15 17:13:29 +0000 | [diff] [blame] | 130 | if (sbdev) |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 131 | msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n", |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 132 | sbdev->vendor_id, sbdev->device_id, |
| 133 | sbdev->bus, sbdev->dev, sbdev->func); |
Carl-Daniel Hailfinger | 9f46cfc | 2009-11-15 17:13:29 +0000 | [diff] [blame] | 134 | return sbdev; |
| 135 | } |
| 136 | |
| 137 | static int enable_flash_sis501(struct pci_dev *dev, const char *name) |
| 138 | { |
| 139 | uint8_t tmp; |
| 140 | int ret = 0; |
| 141 | struct pci_dev *sbdev; |
| 142 | |
| 143 | sbdev = find_southbridge(dev->vendor_id, name); |
| 144 | if (!sbdev) |
| 145 | return -1; |
| 146 | |
| 147 | ret = enable_flash_sis_mapping(sbdev, name); |
| 148 | |
| 149 | tmp = sio_read(0x22, 0x80); |
| 150 | tmp &= (~0x20); |
| 151 | tmp |= 0x4; |
| 152 | sio_write(0x22, 0x80, tmp); |
| 153 | |
| 154 | tmp = sio_read(0x22, 0x70); |
| 155 | tmp &= (~0x20); |
| 156 | tmp |= 0x4; |
| 157 | sio_write(0x22, 0x70, tmp); |
| 158 | |
| 159 | return ret; |
| 160 | } |
| 161 | |
| 162 | static int enable_flash_sis5511(struct pci_dev *dev, const char *name) |
| 163 | { |
| 164 | uint8_t tmp; |
| 165 | int ret = 0; |
| 166 | struct pci_dev *sbdev; |
| 167 | |
| 168 | sbdev = find_southbridge(dev->vendor_id, name); |
| 169 | if (!sbdev) |
| 170 | return -1; |
| 171 | |
| 172 | ret = enable_flash_sis_mapping(sbdev, name); |
| 173 | |
| 174 | tmp = sio_read(0x22, 0x50); |
| 175 | tmp &= (~0x20); |
| 176 | tmp |= 0x4; |
| 177 | sio_write(0x22, 0x50, tmp); |
| 178 | |
| 179 | return ret; |
| 180 | } |
| 181 | |
Stefan Tauner | e34e3e8 | 2013-01-01 00:06:51 +0000 | [diff] [blame] | 182 | static int enable_flash_sis5x0(struct pci_dev *dev, const char *name, uint8_t dis_mask, uint8_t en_mask) |
Carl-Daniel Hailfinger | 9f46cfc | 2009-11-15 17:13:29 +0000 | [diff] [blame] | 183 | { |
Stefan Tauner | e34e3e8 | 2013-01-01 00:06:51 +0000 | [diff] [blame] | 184 | #define SIS_REG 0x45 |
Carl-Daniel Hailfinger | 9f46cfc | 2009-11-15 17:13:29 +0000 | [diff] [blame] | 185 | uint8_t new, newer; |
| 186 | int ret = 0; |
| 187 | struct pci_dev *sbdev; |
| 188 | |
| 189 | sbdev = find_southbridge(dev->vendor_id, name); |
| 190 | if (!sbdev) |
| 191 | return -1; |
| 192 | |
| 193 | ret = enable_flash_sis_mapping(sbdev, name); |
| 194 | |
Stefan Tauner | e34e3e8 | 2013-01-01 00:06:51 +0000 | [diff] [blame] | 195 | new = pci_read_byte(sbdev, SIS_REG); |
| 196 | new &= (~dis_mask); |
| 197 | new |= en_mask; |
| 198 | rpci_write_byte(sbdev, SIS_REG, new); |
| 199 | newer = pci_read_byte(sbdev, SIS_REG); |
| 200 | if (newer != new) { /* FIXME: share this with other code? */ |
| 201 | msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", SIS_REG, new, name); |
| 202 | msg_pinfo("Stuck at 0x%02x\n", newer); |
Carl-Daniel Hailfinger | 9f46cfc | 2009-11-15 17:13:29 +0000 | [diff] [blame] | 203 | ret = -1; |
| 204 | } |
| 205 | |
| 206 | return ret; |
| 207 | } |
| 208 | |
Stefan Tauner | e34e3e8 | 2013-01-01 00:06:51 +0000 | [diff] [blame] | 209 | static int enable_flash_sis530(struct pci_dev *dev, const char *name) |
| 210 | { |
| 211 | return enable_flash_sis5x0(dev, name, 0x20, 0x04); |
| 212 | } |
| 213 | |
Carl-Daniel Hailfinger | 9f46cfc | 2009-11-15 17:13:29 +0000 | [diff] [blame] | 214 | static int enable_flash_sis540(struct pci_dev *dev, const char *name) |
| 215 | { |
Stefan Tauner | e34e3e8 | 2013-01-01 00:06:51 +0000 | [diff] [blame] | 216 | return enable_flash_sis5x0(dev, name, 0x80, 0x40); |
Carl-Daniel Hailfinger | 9f46cfc | 2009-11-15 17:13:29 +0000 | [diff] [blame] | 217 | } |
| 218 | |
Uwe Hermann | 987942d | 2006-11-07 11:16:21 +0000 | [diff] [blame] | 219 | /* Datasheet: |
| 220 | * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4) |
| 221 | * - URL: http://www.intel.com/design/intarch/datashts/290562.htm |
| 222 | * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf |
| 223 | * - Order Number: 290562-001 |
| 224 | */ |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 225 | static int enable_flash_piix4(struct pci_dev *dev, const char *name) |
Uwe Hermann | ea2c66d | 2006-11-05 18:26:08 +0000 | [diff] [blame] | 226 | { |
| 227 | uint16_t old, new; |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 228 | uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */ |
Uwe Hermann | ea2c66d | 2006-11-05 18:26:08 +0000 | [diff] [blame] | 229 | |
Carl-Daniel Hailfinger | eaacd2d | 2011-11-09 23:40:00 +0000 | [diff] [blame] | 230 | internal_buses_supported = BUS_PARALLEL; |
Maciej Pijanka | a661e15 | 2009-12-08 17:26:24 +0000 | [diff] [blame] | 231 | |
Uwe Hermann | ea2c66d | 2006-11-05 18:26:08 +0000 | [diff] [blame] | 232 | old = pci_read_word(dev, xbcs); |
| 233 | |
| 234 | /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 235 | * FFF00000-FFF7FFFF are forwarded to ISA). |
Uwe Hermann | c556d32 | 2008-10-28 11:50:05 +0000 | [diff] [blame] | 236 | * Note: This bit is reserved on PIIX/PIIX3/MPIIX. |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 237 | * Set bit 7: Extended BIOS Enable (PCI master accesses to |
| 238 | * FFF80000-FFFDFFFF are forwarded to ISA). |
| 239 | * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to |
| 240 | * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top |
| 241 | * of 1 Mbyte, or the aliases at the top of 4 Gbyte |
| 242 | * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#. |
| 243 | * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA. |
| 244 | * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable). |
| 245 | */ |
Uwe Hermann | c556d32 | 2008-10-28 11:50:05 +0000 | [diff] [blame] | 246 | if (dev->device_id == 0x122e || dev->device_id == 0x7000 |
| 247 | || dev->device_id == 0x1234) |
| 248 | new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */ |
Uwe Hermann | 8720345 | 2008-10-26 18:40:42 +0000 | [diff] [blame] | 249 | else |
| 250 | new = old | 0x02c4; |
Uwe Hermann | ea2c66d | 2006-11-05 18:26:08 +0000 | [diff] [blame] | 251 | |
| 252 | if (new == old) |
| 253 | return 0; |
| 254 | |
Carl-Daniel Hailfinger | 2bee8cf | 2010-11-10 15:25:18 +0000 | [diff] [blame] | 255 | rpci_write_word(dev, xbcs, new); |
Uwe Hermann | ea2c66d | 2006-11-05 18:26:08 +0000 | [diff] [blame] | 256 | |
Stefan Tauner | e34e3e8 | 2013-01-01 00:06:51 +0000 | [diff] [blame] | 257 | if (pci_read_word(dev, xbcs) != new) { /* FIXME: share this with other code? */ |
| 258 | msg_pinfo("Setting register 0x%04x to 0x%04x on %s failed (WARNING ONLY).\n", xbcs, new, name); |
Uwe Hermann | ea2c66d | 2006-11-05 18:26:08 +0000 | [diff] [blame] | 259 | return -1; |
| 260 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 261 | |
Uwe Hermann | ea2c66d | 2006-11-05 18:26:08 +0000 | [diff] [blame] | 262 | return 0; |
| 263 | } |
| 264 | |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 265 | /* Handle BIOS_CNTL (aka. BCR). Disable locks and enable writes. The register can either be in PCI config space |
| 266 | * at the offset given by 'bios_cntl' or at the memory-mapped address 'addr'. |
| 267 | * |
| 268 | * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, in Poulsbo, Tunnel Creek and other Atom |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 269 | * chipsets/SoCs it is even 32b, but just treating it as 8 bit wide seems to work fine in practice. */ |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 270 | static int enable_flash_ich_bios_cntl_common(enum ich_chipset ich_generation, void *addr, |
| 271 | struct pci_dev *dev, uint8_t bios_cntl) |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 272 | { |
Stefan Tauner | d5c4ab4 | 2011-09-09 12:46:32 +0000 | [diff] [blame] | 273 | uint8_t old, new, wanted; |
Stefan Reinauer | eb36647 | 2006-09-06 15:48:48 +0000 | [diff] [blame] | 274 | |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 275 | switch (ich_generation) { |
| 276 | case CHIPSET_ICH_UNKNOWN: |
| 277 | return ERROR_FATAL; |
| 278 | /* Non-SPI-capable */ |
| 279 | case CHIPSET_ICH: |
| 280 | case CHIPSET_ICH2345: |
| 281 | break; |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 282 | /* Some Atom chipsets are special: The second byte of BIOS_CNTL (D9h) contains a prefetch bit similar to |
| 283 | * what other SPI-capable chipsets have at DCh. Others like Bay Trail use a memmapped register. |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 284 | * The Tunnel Creek datasheet contains a lot of details about the SPI controller, among other things it |
| 285 | * mentions that the prefetching and caching does only happen for direct memory reads. |
| 286 | * Therefore - at least for Tunnel Creek - it should not matter to flashrom because we use the |
| 287 | * programmed access only and not memory mapping. */ |
| 288 | case CHIPSET_TUNNEL_CREEK: |
| 289 | case CHIPSET_POULSBO: |
| 290 | case CHIPSET_CENTERTON: |
| 291 | old = pci_read_byte(dev, bios_cntl + 1); |
| 292 | msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis"); |
| 293 | break; |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 294 | case CHIPSET_BAYTRAIL: |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 295 | case CHIPSET_ICH7: |
| 296 | default: /* Future version might behave the same */ |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 297 | if (ich_generation == CHIPSET_BAYTRAIL) |
| 298 | old = (mmio_readl(addr) >> 2) & 0x3; |
| 299 | else |
| 300 | old = (pci_read_byte(dev, bios_cntl) >> 2) & 0x3; |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 301 | msg_pdbg("SPI Read Configuration: "); |
| 302 | if (old == 3) |
| 303 | msg_pdbg("invalid prefetching/caching settings, "); |
| 304 | else |
| 305 | msg_pdbg("prefetching %sabled, caching %sabled, ", |
| 306 | (old & 0x2) ? "en" : "dis", |
| 307 | (old & 0x1) ? "dis" : "en"); |
| 308 | } |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 309 | |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 310 | if (ich_generation == CHIPSET_BAYTRAIL) |
| 311 | wanted = old = mmio_readl(addr); |
| 312 | else |
| 313 | wanted = old = pci_read_byte(dev, bios_cntl); |
| 314 | |
Stefan Tauner | f9a8da5 | 2011-06-11 18:16:50 +0000 | [diff] [blame] | 315 | /* |
| 316 | * Quote from the 6 Series datasheet (Document Number: 324645-004): |
| 317 | * "Bit 5: SMM BIOS Write Protect Disable (SMM_BWP) |
| 318 | * 1 = BIOS region SMM protection is enabled. |
| 319 | * The BIOS Region is not writable unless all processors are in SMM." |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 320 | * In earlier chipsets this bit is reserved. |
Stefan Reinauer | 62218c3 | 2012-08-26 02:35:13 +0000 | [diff] [blame] | 321 | * |
| 322 | * Try to unset it in any case. |
| 323 | * It won't hurt and makes sense in some cases according to Stefan Reinauer. |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 324 | * |
| 325 | * At least in Centerton aforementioned bit is located at bit 7. It is unspecified in all other Atom |
| 326 | * and Desktop chipsets before Ibex Peak/5 Series, but we reset bit 5 anyway. |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 327 | */ |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 328 | int smm_bwp_bit; |
| 329 | if (ich_generation == CHIPSET_CENTERTON) |
| 330 | smm_bwp_bit = 7; |
| 331 | else |
| 332 | smm_bwp_bit = 5; |
| 333 | wanted &= ~(1 << smm_bwp_bit); |
Stefan Reinauer | 62218c3 | 2012-08-26 02:35:13 +0000 | [diff] [blame] | 334 | |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 335 | /* Tunnel Creek has a cache disable at bit 2 of the lowest BIOS_CNTL byte. */ |
| 336 | if (ich_generation == CHIPSET_TUNNEL_CREEK) |
| 337 | wanted |= (1 << 2); |
| 338 | |
| 339 | wanted |= (1 << 0); /* Set BIOS Write Enable */ |
| 340 | wanted &= ~(1 << 1); /* Disable lock (futile) */ |
Stefan Reinauer | 62218c3 | 2012-08-26 02:35:13 +0000 | [diff] [blame] | 341 | |
| 342 | /* Only write the register if it's necessary */ |
| 343 | if (wanted != old) { |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 344 | if (ich_generation == CHIPSET_BAYTRAIL) { |
| 345 | rmmio_writel(wanted, addr); |
| 346 | new = mmio_readl(addr); |
| 347 | } else { |
| 348 | rpci_write_byte(dev, bios_cntl, wanted); |
| 349 | new = pci_read_byte(dev, bios_cntl); |
| 350 | } |
Stefan Reinauer | 62218c3 | 2012-08-26 02:35:13 +0000 | [diff] [blame] | 351 | } else |
| 352 | new = old; |
| 353 | |
| 354 | msg_pdbg("\nBIOS_CNTL = 0x%02x: ", new); |
| 355 | msg_pdbg("BIOS Lock Enable: %sabled, ", (new & (1 << 1)) ? "en" : "dis"); |
| 356 | msg_pdbg("BIOS Write Enable: %sabled\n", (new & (1 << 0)) ? "en" : "dis"); |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 357 | if (new & (1 << smm_bwp_bit)) |
Stefan Tauner | c6fa32d | 2013-01-04 22:54:07 +0000 | [diff] [blame] | 358 | msg_pwarn("Warning: BIOS region SMM protection is enabled!\n"); |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 359 | |
Stefan Reinauer | 62218c3 | 2012-08-26 02:35:13 +0000 | [diff] [blame] | 360 | if (new != wanted) |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 361 | msg_pwarn("Warning: Setting Bios Control at 0x%x from 0x%02x to 0x%02x failed.\n" |
| 362 | "New value is 0x%02x.\n", bios_cntl, old, wanted, new); |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 363 | |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 364 | /* Return an error if we could not set the write enable only. */ |
Stefan Reinauer | 62218c3 | 2012-08-26 02:35:13 +0000 | [diff] [blame] | 365 | if (!(new & (1 << 0))) |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 366 | return -1; |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 367 | |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 368 | return 0; |
| 369 | } |
| 370 | |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 371 | static int enable_flash_ich_bios_cntl_config_space(struct pci_dev *dev, enum ich_chipset ich_generation, |
| 372 | uint8_t bios_cntl) |
| 373 | { |
| 374 | return enable_flash_ich_bios_cntl_common(ich_generation, NULL, dev, bios_cntl); |
| 375 | } |
| 376 | |
| 377 | static int enable_flash_ich_bios_cntl_memmapped(enum ich_chipset ich_generation, void *addr) |
| 378 | { |
| 379 | return enable_flash_ich_bios_cntl_common(ich_generation, addr, NULL, 0); |
| 380 | } |
| 381 | |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 382 | static int enable_flash_ich_fwh_decode(struct pci_dev *dev, enum ich_chipset ich_generation) |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 383 | { |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 384 | uint8_t fwh_sel1 = 0, fwh_sel2 = 0, fwh_dec_en_lo = 0, fwh_dec_en_hi = 0; /* silence compilers */ |
| 385 | bool implemented = 0; |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 386 | void *ilb = NULL; /* Only for Baytrail */ |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 387 | switch (ich_generation) { |
| 388 | case CHIPSET_ICH: |
| 389 | /* FIXME: Unlike later chipsets, ICH and ICH-0 do only support mapping of the top-most 4MB |
| 390 | * and therefore do only feature FWH_DEC_EN (E3h, different default too) and FWH_SEL (E8h). */ |
| 391 | break; |
| 392 | case CHIPSET_ICH2345: |
Kyösti Mälkki | 88ee040 | 2013-09-14 23:37:01 +0000 | [diff] [blame] | 393 | fwh_sel1 = 0xe8; |
| 394 | fwh_sel2 = 0xee; |
| 395 | fwh_dec_en_lo = 0xf0; |
| 396 | fwh_dec_en_hi = 0xe3; |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 397 | implemented = 1; |
| 398 | break; |
| 399 | case CHIPSET_POULSBO: |
| 400 | case CHIPSET_TUNNEL_CREEK: |
| 401 | /* FIXME: Similar to ICH and ICH-0, Tunnel Creek and Poulsbo do only feature one register each, |
| 402 | * FWH_DEC_EN (D7h) and FWH_SEL (D0h). */ |
| 403 | break; |
| 404 | case CHIPSET_CENTERTON: |
| 405 | /* FIXME: Similar to above FWH_DEC_EN (D4h) and FWH_SEL (D0h). */ |
| 406 | break; |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 407 | case CHIPSET_BAYTRAIL: { |
| 408 | uint32_t ilb_base = pci_read_long(dev, 0x50) & 0xfffffe00; /* bits 31:9 */ |
| 409 | if (ilb_base == 0) { |
| 410 | msg_perr("Error: Invalid ILB_BASE_ADDRESS\n"); |
| 411 | return ERROR_FATAL; |
| 412 | } |
| 413 | ilb = rphysmap("BYT IBASE", ilb_base, 512); |
| 414 | fwh_sel1 = 0x18; |
| 415 | fwh_dec_en_lo = 0xd8; |
| 416 | fwh_dec_en_hi = 0xd9; |
| 417 | implemented = 1; |
| 418 | break; |
| 419 | } |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 420 | case CHIPSET_ICH6: |
| 421 | case CHIPSET_ICH7: |
| 422 | default: /* Future version might behave the same */ |
| 423 | fwh_sel1 = 0xd0; |
| 424 | fwh_sel2 = 0xd4; |
| 425 | fwh_dec_en_lo = 0xd8; |
| 426 | fwh_dec_en_hi = 0xd9; |
| 427 | implemented = 1; |
| 428 | break; |
Kyösti Mälkki | 88ee040 | 2013-09-14 23:37:01 +0000 | [diff] [blame] | 429 | } |
Kyösti Mälkki | 743babc | 2013-09-14 23:36:53 +0000 | [diff] [blame] | 430 | |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 431 | char *idsel = extract_programmer_param("fwh_idsel"); |
Carl-Daniel Hailfinger | 744132a | 2010-07-06 09:55:48 +0000 | [diff] [blame] | 432 | if (idsel && strlen(idsel)) { |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 433 | if (!implemented) { |
| 434 | msg_perr("Error: fwh_idsel= specified, but (yet) unsupported on this chipset.\n"); |
| 435 | goto idsel_garbage_out; |
| 436 | } |
Carl-Daniel Hailfinger | 46fa068 | 2011-07-25 22:44:09 +0000 | [diff] [blame] | 437 | errno = 0; |
| 438 | /* Base 16, nothing else makes sense. */ |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 439 | uint64_t fwh_idsel = (uint64_t)strtoull(idsel, NULL, 16); |
Carl-Daniel Hailfinger | 46fa068 | 2011-07-25 22:44:09 +0000 | [diff] [blame] | 440 | if (errno) { |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 441 | msg_perr("Error: fwh_idsel= specified, but value could not be converted.\n"); |
Carl-Daniel Hailfinger | 46fa068 | 2011-07-25 22:44:09 +0000 | [diff] [blame] | 442 | goto idsel_garbage_out; |
| 443 | } |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 444 | uint64_t fwh_mask = 0xffffffff; |
| 445 | if (fwh_sel2 > 0) |
| 446 | fwh_mask |= (0xffffULL << 32); |
| 447 | if (fwh_idsel & ~fwh_mask) { |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 448 | msg_perr("Error: fwh_idsel= specified, but value had unused bits set.\n"); |
Carl-Daniel Hailfinger | 46fa068 | 2011-07-25 22:44:09 +0000 | [diff] [blame] | 449 | goto idsel_garbage_out; |
| 450 | } |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 451 | uint64_t fwh_idsel_old; |
| 452 | if (ich_generation == CHIPSET_BAYTRAIL) { |
| 453 | fwh_idsel_old = mmio_readl(ilb + fwh_sel1); |
| 454 | rmmio_writel(fwh_idsel, ilb + fwh_sel1); |
| 455 | } else { |
Stefan Tauner | 5c316f9 | 2015-02-08 21:57:52 +0000 | [diff] [blame] | 456 | fwh_idsel_old = (uint64_t)pci_read_long(dev, fwh_sel1) << 16; |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 457 | rpci_write_long(dev, fwh_sel1, (fwh_idsel >> 16) & 0xffffffff); |
| 458 | if (fwh_sel2 > 0) { |
| 459 | fwh_idsel_old |= pci_read_word(dev, fwh_sel2); |
| 460 | rpci_write_word(dev, fwh_sel2, fwh_idsel & 0xffff); |
| 461 | } |
| 462 | } |
Stefan Tauner | eff156e | 2014-07-13 17:06:11 +0000 | [diff] [blame] | 463 | msg_pdbg("Setting IDSEL from 0x%012" PRIx64 " to 0x%012" PRIx64 " for top 16 MB.\n", |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 464 | fwh_idsel_old, fwh_idsel); |
Carl-Daniel Hailfinger | 2a9e245 | 2009-12-17 15:20:01 +0000 | [diff] [blame] | 465 | /* FIXME: Decode settings are not changed. */ |
Carl-Daniel Hailfinger | 744132a | 2010-07-06 09:55:48 +0000 | [diff] [blame] | 466 | } else if (idsel) { |
Carl-Daniel Hailfinger | 46fa068 | 2011-07-25 22:44:09 +0000 | [diff] [blame] | 467 | msg_perr("Error: fwh_idsel= specified, but no value given.\n"); |
Sylvain "ythier" Hitier | 3093f8f | 2011-09-03 11:22:27 +0000 | [diff] [blame] | 468 | idsel_garbage_out: |
Carl-Daniel Hailfinger | 744132a | 2010-07-06 09:55:48 +0000 | [diff] [blame] | 469 | free(idsel); |
Tadas Slotkus | 0e3f1cf | 2011-09-06 18:49:31 +0000 | [diff] [blame] | 470 | return ERROR_FATAL; |
Carl-Daniel Hailfinger | 4449868 | 2009-08-13 23:23:37 +0000 | [diff] [blame] | 471 | } |
Carl-Daniel Hailfinger | 744132a | 2010-07-06 09:55:48 +0000 | [diff] [blame] | 472 | free(idsel); |
Carl-Daniel Hailfinger | 4449868 | 2009-08-13 23:23:37 +0000 | [diff] [blame] | 473 | |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 474 | if (!implemented) { |
Stefan Tauner | eff156e | 2014-07-13 17:06:11 +0000 | [diff] [blame] | 475 | msg_pdbg2("FWH IDSEL handling is not implemented on this chipset.\n"); |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 476 | return 0; |
| 477 | } |
| 478 | |
Carl-Daniel Hailfinger | 2a9e245 | 2009-12-17 15:20:01 +0000 | [diff] [blame] | 479 | /* Ignore all legacy ranges below 1 MB. |
| 480 | * We currently only support flashing the chip which responds to |
| 481 | * IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations |
| 482 | * have to be adjusted. |
| 483 | */ |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 484 | int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0; |
| 485 | bool contiguous = 1; |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 486 | uint32_t fwh_conf; |
| 487 | if (ich_generation == CHIPSET_BAYTRAIL) |
| 488 | fwh_conf = mmio_readl(ilb + fwh_sel1); |
| 489 | else |
| 490 | fwh_conf = pci_read_long(dev, fwh_sel1); |
| 491 | |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 492 | int i; |
Carl-Daniel Hailfinger | 2a9e245 | 2009-12-17 15:20:01 +0000 | [diff] [blame] | 493 | /* FWH_SEL1 */ |
Carl-Daniel Hailfinger | 2a9e245 | 2009-12-17 15:20:01 +0000 | [diff] [blame] | 494 | for (i = 7; i >= 0; i--) { |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 495 | int tmp = (fwh_conf >> (i * 4)) & 0xf; |
Stefan Tauner | eff156e | 2014-07-13 17:06:11 +0000 | [diff] [blame] | 496 | msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n", |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 497 | (0x1ff8 + i) * 0x80000, |
| 498 | (0x1ff0 + i) * 0x80000, |
| 499 | tmp); |
Carl-Daniel Hailfinger | 2a9e245 | 2009-12-17 15:20:01 +0000 | [diff] [blame] | 500 | if ((tmp == 0) && contiguous) { |
| 501 | max_decode_fwh_idsel = (8 - i) * 0x80000; |
| 502 | } else { |
| 503 | contiguous = 0; |
| 504 | } |
| 505 | } |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 506 | if (fwh_sel2 > 0) { |
| 507 | /* FWH_SEL2 */ |
| 508 | fwh_conf = pci_read_word(dev, fwh_sel2); |
| 509 | for (i = 3; i >= 0; i--) { |
| 510 | int tmp = (fwh_conf >> (i * 4)) & 0xf; |
| 511 | msg_pdbg("0x%08x/0x%08x FWH IDSEL: 0x%x\n", |
| 512 | (0xff4 + i) * 0x100000, |
| 513 | (0xff0 + i) * 0x100000, |
| 514 | tmp); |
| 515 | if ((tmp == 0) && contiguous) { |
| 516 | max_decode_fwh_idsel = (8 - i) * 0x100000; |
| 517 | } else { |
| 518 | contiguous = 0; |
| 519 | } |
Carl-Daniel Hailfinger | 2a9e245 | 2009-12-17 15:20:01 +0000 | [diff] [blame] | 520 | } |
| 521 | } |
| 522 | contiguous = 1; |
| 523 | /* FWH_DEC_EN1 */ |
Kyösti Mälkki | 743babc | 2013-09-14 23:36:53 +0000 | [diff] [blame] | 524 | fwh_conf = pci_read_byte(dev, fwh_dec_en_hi); |
| 525 | fwh_conf <<= 8; |
| 526 | fwh_conf |= pci_read_byte(dev, fwh_dec_en_lo); |
Carl-Daniel Hailfinger | 2a9e245 | 2009-12-17 15:20:01 +0000 | [diff] [blame] | 527 | for (i = 7; i >= 0; i--) { |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 528 | int tmp = (fwh_conf >> (i + 0x8)) & 0x1; |
Stefan Tauner | eff156e | 2014-07-13 17:06:11 +0000 | [diff] [blame] | 529 | msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n", |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 530 | (0x1ff8 + i) * 0x80000, |
| 531 | (0x1ff0 + i) * 0x80000, |
| 532 | tmp ? "en" : "dis"); |
Michael Karcher | 9678539 | 2010-01-03 15:09:17 +0000 | [diff] [blame] | 533 | if ((tmp == 1) && contiguous) { |
Carl-Daniel Hailfinger | 2a9e245 | 2009-12-17 15:20:01 +0000 | [diff] [blame] | 534 | max_decode_fwh_decode = (8 - i) * 0x80000; |
| 535 | } else { |
| 536 | contiguous = 0; |
| 537 | } |
| 538 | } |
| 539 | for (i = 3; i >= 0; i--) { |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 540 | int tmp = (fwh_conf >> i) & 0x1; |
Stefan Tauner | eff156e | 2014-07-13 17:06:11 +0000 | [diff] [blame] | 541 | msg_pdbg("0x%08x/0x%08x FWH decode %sabled\n", |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 542 | (0xff4 + i) * 0x100000, |
| 543 | (0xff0 + i) * 0x100000, |
| 544 | tmp ? "en" : "dis"); |
Michael Karcher | 9678539 | 2010-01-03 15:09:17 +0000 | [diff] [blame] | 545 | if ((tmp == 1) && contiguous) { |
Carl-Daniel Hailfinger | 2a9e245 | 2009-12-17 15:20:01 +0000 | [diff] [blame] | 546 | max_decode_fwh_decode = (8 - i) * 0x100000; |
| 547 | } else { |
| 548 | contiguous = 0; |
| 549 | } |
| 550 | } |
| 551 | max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode); |
Stefan Tauner | eff156e | 2014-07-13 17:06:11 +0000 | [diff] [blame] | 552 | msg_pdbg("Maximum FWH chip size: 0x%x bytes\n", max_rom_decode.fwh); |
Carl-Daniel Hailfinger | 2a9e245 | 2009-12-17 15:20:01 +0000 | [diff] [blame] | 553 | |
Kyösti Mälkki | 743babc | 2013-09-14 23:36:53 +0000 | [diff] [blame] | 554 | return 0; |
| 555 | } |
| 556 | |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 557 | static int enable_flash_ich_fwh(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl) |
Kyösti Mälkki | 78cd087 | 2013-09-14 23:36:57 +0000 | [diff] [blame] | 558 | { |
Kyösti Mälkki | 88ee040 | 2013-09-14 23:37:01 +0000 | [diff] [blame] | 559 | int err; |
| 560 | |
| 561 | /* Configure FWH IDSEL decoder maps. */ |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 562 | if ((err = enable_flash_ich_fwh_decode(dev, ich_generation)) != 0) |
Kyösti Mälkki | 88ee040 | 2013-09-14 23:37:01 +0000 | [diff] [blame] | 563 | return err; |
| 564 | |
Kyösti Mälkki | 78cd087 | 2013-09-14 23:36:57 +0000 | [diff] [blame] | 565 | internal_buses_supported = BUS_FWH; |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 566 | return enable_flash_ich_bios_cntl_config_space(dev, ich_generation, bios_cntl); |
Kyösti Mälkki | 78cd087 | 2013-09-14 23:36:57 +0000 | [diff] [blame] | 567 | } |
| 568 | |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 569 | static int enable_flash_ich0(struct pci_dev *dev, const char *name) |
Kyösti Mälkki | 78cd087 | 2013-09-14 23:36:57 +0000 | [diff] [blame] | 570 | { |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 571 | return enable_flash_ich_fwh(dev, CHIPSET_ICH, 0x4e); |
Kyösti Mälkki | 78cd087 | 2013-09-14 23:36:57 +0000 | [diff] [blame] | 572 | } |
| 573 | |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 574 | static int enable_flash_ich2345(struct pci_dev *dev, const char *name) |
Kyösti Mälkki | 78cd087 | 2013-09-14 23:36:57 +0000 | [diff] [blame] | 575 | { |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 576 | return enable_flash_ich_fwh(dev, CHIPSET_ICH2345, 0x4e); |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 577 | } |
| 578 | |
Kyösti Mälkki | 78cd087 | 2013-09-14 23:36:57 +0000 | [diff] [blame] | 579 | static int enable_flash_ich6(struct pci_dev *dev, const char *name) |
| 580 | { |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 581 | return enable_flash_ich_fwh(dev, CHIPSET_ICH6, 0xdc); |
Kyösti Mälkki | 78cd087 | 2013-09-14 23:36:57 +0000 | [diff] [blame] | 582 | } |
| 583 | |
Adam Jurkowski | e498410 | 2009-12-21 15:30:46 +0000 | [diff] [blame] | 584 | static int enable_flash_poulsbo(struct pci_dev *dev, const char *name) |
| 585 | { |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 586 | return enable_flash_ich_fwh(dev, CHIPSET_POULSBO, 0xd8); |
Adam Jurkowski | e498410 | 2009-12-21 15:30:46 +0000 | [diff] [blame] | 587 | } |
| 588 | |
Nico Huber | 0ea99f5 | 2017-03-17 17:22:53 +0100 | [diff] [blame] | 589 | static void enable_flash_ich_report_gcs(struct pci_dev *const dev, const enum ich_chipset ich_generation, |
| 590 | const uint8_t *const rcrb) |
Ingo Feldschmid | dadc0a6 | 2011-09-07 19:18:25 +0000 | [diff] [blame] | 591 | { |
Nico Huber | 0ea99f5 | 2017-03-17 17:22:53 +0100 | [diff] [blame] | 592 | uint32_t gcs; |
Nico Huber | 93c3069 | 2017-03-20 14:25:09 +0100 | [diff] [blame] | 593 | const char *reg_name; |
| 594 | bool bild, top_swap; |
Nico Huber | 0ea99f5 | 2017-03-17 17:22:53 +0100 | [diff] [blame] | 595 | |
| 596 | switch (ich_generation) { |
| 597 | case CHIPSET_BAYTRAIL: |
Nico Huber | 93c3069 | 2017-03-20 14:25:09 +0100 | [diff] [blame] | 598 | reg_name = "GCS"; |
Nico Huber | 0ea99f5 | 2017-03-17 17:22:53 +0100 | [diff] [blame] | 599 | gcs = mmio_readl(rcrb + 0); |
Nico Huber | 93c3069 | 2017-03-20 14:25:09 +0100 | [diff] [blame] | 600 | bild = gcs & 1; |
Nico Huber | 0ea99f5 | 2017-03-17 17:22:53 +0100 | [diff] [blame] | 601 | top_swap = (gcs & 2) >> 1; |
| 602 | break; |
Nico Huber | 93c3069 | 2017-03-20 14:25:09 +0100 | [diff] [blame] | 603 | case CHIPSET_100_SERIES_SUNRISE_POINT: |
David Hendricks | a521636 | 2017-08-08 20:02:22 -0700 | [diff] [blame] | 604 | case CHIPSET_C620_SERIES_LEWISBURG: |
Nico Huber | 93c3069 | 2017-03-20 14:25:09 +0100 | [diff] [blame] | 605 | reg_name = "BIOS_SPI_BC"; |
| 606 | gcs = pci_read_long(dev, 0xdc); |
| 607 | bild = (gcs >> 7) & 1; |
| 608 | top_swap = (gcs >> 4) & 1; |
| 609 | break; |
Nico Huber | 0ea99f5 | 2017-03-17 17:22:53 +0100 | [diff] [blame] | 610 | default: |
Nico Huber | 93c3069 | 2017-03-20 14:25:09 +0100 | [diff] [blame] | 611 | reg_name = "GCS"; |
Nico Huber | 0ea99f5 | 2017-03-17 17:22:53 +0100 | [diff] [blame] | 612 | gcs = mmio_readl(rcrb + 0x3410); |
Nico Huber | 93c3069 | 2017-03-20 14:25:09 +0100 | [diff] [blame] | 613 | bild = gcs & 1; |
Nico Huber | 0ea99f5 | 2017-03-17 17:22:53 +0100 | [diff] [blame] | 614 | top_swap = mmio_readb(rcrb + 0x3414) & 1; |
| 615 | break; |
| 616 | } |
| 617 | |
Nico Huber | 93c3069 | 2017-03-20 14:25:09 +0100 | [diff] [blame] | 618 | msg_pdbg("%s = 0x%x: ", reg_name, gcs); |
| 619 | msg_pdbg("BIOS Interface Lock-Down: %sabled, ", bild ? "en" : "dis"); |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 620 | |
Stefan Tauner | bd0c70a | 2011-08-27 21:19:56 +0000 | [diff] [blame] | 621 | static const char *const straps_names_EP80579[] = { "SPI", "reserved", "reserved", "LPC" }; |
| 622 | static const char *const straps_names_ich7_nm10[] = { "reserved", "SPI", "PCI", "LPC" }; |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 623 | static const char *const straps_names_tunnel_creek[] = { "SPI", "LPC" }; |
Stefan Tauner | bd0c70a | 2011-08-27 21:19:56 +0000 | [diff] [blame] | 624 | static const char *const straps_names_ich8910[] = { "SPI", "SPI", "PCI", "LPC" }; |
Helge Wagner | a0fce5f | 2012-07-24 16:33:55 +0000 | [diff] [blame] | 625 | static const char *const straps_names_pch567[] = { "LPC", "reserved", "PCI", "SPI" }; |
Duncan Laurie | 823096e | 2014-08-20 15:39:38 +0000 | [diff] [blame] | 626 | static const char *const straps_names_pch89_baytrail[] = { "LPC", "reserved", "reserved", "SPI" }; |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 627 | static const char *const straps_names_pch8_lp[] = { "SPI", "LPC" }; |
Stefan Tauner | bd0c70a | 2011-08-27 21:19:56 +0000 | [diff] [blame] | 628 | static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" }; |
| 629 | |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 630 | const char *const *straps_names; |
Stefan Tauner | bd0c70a | 2011-08-27 21:19:56 +0000 | [diff] [blame] | 631 | switch (ich_generation) { |
Stefan Tauner | a8d838d | 2011-11-06 23:51:09 +0000 | [diff] [blame] | 632 | case CHIPSET_ICH7: |
Stefan Tauner | bd0c70a | 2011-08-27 21:19:56 +0000 | [diff] [blame] | 633 | /* EP80579 may need further changes, but this is the least |
| 634 | * intrusive way to get correct BOOT Strap printing without |
| 635 | * changing the rest of its code path). */ |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 636 | if (dev->device_id == 0x5031) |
Stefan Tauner | bd0c70a | 2011-08-27 21:19:56 +0000 | [diff] [blame] | 637 | straps_names = straps_names_EP80579; |
| 638 | else |
| 639 | straps_names = straps_names_ich7_nm10; |
| 640 | break; |
Stefan Tauner | a8d838d | 2011-11-06 23:51:09 +0000 | [diff] [blame] | 641 | case CHIPSET_ICH8: |
| 642 | case CHIPSET_ICH9: |
| 643 | case CHIPSET_ICH10: |
Stefan Tauner | bd0c70a | 2011-08-27 21:19:56 +0000 | [diff] [blame] | 644 | straps_names = straps_names_ich8910; |
| 645 | break; |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 646 | case CHIPSET_TUNNEL_CREEK: |
| 647 | straps_names = straps_names_tunnel_creek; |
| 648 | break; |
Stefan Tauner | a8d838d | 2011-11-06 23:51:09 +0000 | [diff] [blame] | 649 | case CHIPSET_5_SERIES_IBEX_PEAK: |
| 650 | case CHIPSET_6_SERIES_COUGAR_POINT: |
Helge Wagner | a0fce5f | 2012-07-24 16:33:55 +0000 | [diff] [blame] | 651 | case CHIPSET_7_SERIES_PANTHER_POINT: |
| 652 | straps_names = straps_names_pch567; |
Stefan Tauner | bd0c70a | 2011-08-27 21:19:56 +0000 | [diff] [blame] | 653 | break; |
Duncan Laurie | 90eb226 | 2013-03-15 03:12:29 +0000 | [diff] [blame] | 654 | case CHIPSET_8_SERIES_LYNX_POINT: |
Duncan Laurie | 823096e | 2014-08-20 15:39:38 +0000 | [diff] [blame] | 655 | case CHIPSET_9_SERIES_WILDCAT_POINT: |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 656 | case CHIPSET_BAYTRAIL: |
Duncan Laurie | 823096e | 2014-08-20 15:39:38 +0000 | [diff] [blame] | 657 | straps_names = straps_names_pch89_baytrail; |
Duncan Laurie | 90eb226 | 2013-03-15 03:12:29 +0000 | [diff] [blame] | 658 | break; |
| 659 | case CHIPSET_8_SERIES_LYNX_POINT_LP: |
Nico Huber | 5120591 | 2017-03-17 17:59:54 +0100 | [diff] [blame] | 660 | case CHIPSET_9_SERIES_WILDCAT_POINT_LP: |
Nico Huber | 93c3069 | 2017-03-20 14:25:09 +0100 | [diff] [blame] | 661 | case CHIPSET_100_SERIES_SUNRISE_POINT: |
David Hendricks | a521636 | 2017-08-08 20:02:22 -0700 | [diff] [blame] | 662 | case CHIPSET_C620_SERIES_LEWISBURG: |
Duncan Laurie | 90eb226 | 2013-03-15 03:12:29 +0000 | [diff] [blame] | 663 | straps_names = straps_names_pch8_lp; |
| 664 | break; |
| 665 | case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 666 | case CHIPSET_CENTERTON: // FIXME: Datasheet does not mention GCS at all |
Duncan Laurie | 90eb226 | 2013-03-15 03:12:29 +0000 | [diff] [blame] | 667 | straps_names = straps_names_unknown; |
| 668 | break; |
Stefan Tauner | bd0c70a | 2011-08-27 21:19:56 +0000 | [diff] [blame] | 669 | default: |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 670 | msg_gerr("%s: unknown ICH generation. Please report!\n", __func__); |
Stefan Tauner | bd0c70a | 2011-08-27 21:19:56 +0000 | [diff] [blame] | 671 | straps_names = straps_names_unknown; |
| 672 | break; |
| 673 | } |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 674 | |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 675 | uint8_t bbs; |
| 676 | switch (ich_generation) { |
| 677 | case CHIPSET_TUNNEL_CREEK: |
| 678 | bbs = (gcs >> 1) & 0x1; |
| 679 | break; |
| 680 | case CHIPSET_8_SERIES_LYNX_POINT_LP: |
Nico Huber | 5120591 | 2017-03-17 17:59:54 +0100 | [diff] [blame] | 681 | case CHIPSET_9_SERIES_WILDCAT_POINT_LP: |
| 682 | /* LP PCHs use a single bit for BBS */ |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 683 | bbs = (gcs >> 10) & 0x1; |
| 684 | break; |
Nico Huber | 93c3069 | 2017-03-20 14:25:09 +0100 | [diff] [blame] | 685 | case CHIPSET_100_SERIES_SUNRISE_POINT: |
David Hendricks | a521636 | 2017-08-08 20:02:22 -0700 | [diff] [blame] | 686 | case CHIPSET_C620_SERIES_LEWISBURG: |
Nico Huber | 93c3069 | 2017-03-20 14:25:09 +0100 | [diff] [blame] | 687 | bbs = (gcs >> 6) & 0x1; |
| 688 | break; |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 689 | default: |
| 690 | /* Other chipsets use two bits for BBS */ |
| 691 | bbs = (gcs >> 10) & 0x3; |
| 692 | break; |
| 693 | } |
| 694 | msg_pdbg("Boot BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]); |
| 695 | |
| 696 | /* Centerton has its TS bit in [GPE0BLK] + 0x30 while the exact location for Tunnel Creek is unknown. */ |
| 697 | if (ich_generation != CHIPSET_TUNNEL_CREEK && ich_generation != CHIPSET_CENTERTON) |
| 698 | msg_pdbg("Top Swap: %s\n", (top_swap) ? "enabled (A16(+) inverted)" : "not enabled"); |
| 699 | } |
| 700 | |
| 701 | static int enable_flash_ich_spi(struct pci_dev *dev, enum ich_chipset ich_generation, uint8_t bios_cntl) |
| 702 | { |
| 703 | |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 704 | /* Get physical address of Root Complex Register Block */ |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 705 | uint32_t rcra = pci_read_long(dev, 0xf0) & 0xffffc000; |
| 706 | msg_pdbg("Root Complex Register Block address = 0x%x\n", rcra); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 707 | |
| 708 | /* Map RCBA to virtual memory */ |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 709 | void *rcrb = rphysmap("ICH RCRB", rcra, 0x4000); |
Stefan Tauner | 7fb5aa0 | 2013-08-14 15:48:44 +0000 | [diff] [blame] | 710 | if (rcrb == ERROR_PTR) |
Niklas Söderlund | 5d30720 | 2013-09-14 09:02:27 +0000 | [diff] [blame] | 711 | return ERROR_FATAL; |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 712 | |
Nico Huber | 0ea99f5 | 2017-03-17 17:22:53 +0100 | [diff] [blame] | 713 | enable_flash_ich_report_gcs(dev, ich_generation, rcrb); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 714 | |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 715 | /* Handle FWH-related parameters and initialization */ |
| 716 | int ret_fwh = enable_flash_ich_fwh(dev, ich_generation, bios_cntl); |
| 717 | if (ret_fwh == ERROR_FATAL) |
| 718 | return ret_fwh; |
| 719 | |
| 720 | /* SPIBAR is at RCRB+0x3020 for ICH[78], Tunnel Creek and Centerton, and RCRB+0x3800 for ICH9. */ |
| 721 | uint16_t spibar_offset; |
| 722 | switch (ich_generation) { |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 723 | case CHIPSET_BAYTRAIL: |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 724 | case CHIPSET_ICH_UNKNOWN: |
| 725 | return ERROR_FATAL; |
| 726 | case CHIPSET_ICH7: |
| 727 | case CHIPSET_ICH8: |
| 728 | case CHIPSET_TUNNEL_CREEK: |
| 729 | case CHIPSET_CENTERTON: |
| 730 | spibar_offset = 0x3020; |
| 731 | break; |
| 732 | case CHIPSET_ICH9: |
| 733 | default: /* Future version might behave the same */ |
| 734 | spibar_offset = 0x3800; |
| 735 | break; |
| 736 | } |
| 737 | msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " + 0x%04x\n", PRIxPTR_WIDTH, (uintptr_t)rcrb, spibar_offset); |
| 738 | void *spibar = rcrb + spibar_offset; |
| 739 | |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 740 | /* This adds BUS_SPI */ |
Nico Huber | 560111e | 2017-04-26 12:27:17 +0200 | [diff] [blame] | 741 | int ret_spi = ich_init_spi(spibar, ich_generation); |
Stefan Tauner | 50e7c60 | 2011-11-08 10:55:54 +0000 | [diff] [blame] | 742 | if (ret_spi == ERROR_FATAL) |
| 743 | return ret_spi; |
| 744 | |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 745 | if (ret_fwh || ret_spi) |
| 746 | return ERROR_NONFATAL; |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 747 | |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 748 | return 0; |
| 749 | } |
| 750 | |
| 751 | static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name) |
| 752 | { |
| 753 | return enable_flash_ich_spi(dev, CHIPSET_TUNNEL_CREEK, 0xd8); |
| 754 | } |
| 755 | |
| 756 | static int enable_flash_s12x0(struct pci_dev *dev, const char *name) |
| 757 | { |
| 758 | return enable_flash_ich_spi(dev, CHIPSET_CENTERTON, 0xd8); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 759 | } |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 760 | |
Carl-Daniel Hailfinger | 1b18b3c | 2008-05-16 14:39:39 +0000 | [diff] [blame] | 761 | static int enable_flash_ich7(struct pci_dev *dev, const char *name) |
Carl-Daniel Hailfinger | 6dc1d3b | 2008-05-14 14:51:22 +0000 | [diff] [blame] | 762 | { |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 763 | return enable_flash_ich_spi(dev, CHIPSET_ICH7, 0xdc); |
Carl-Daniel Hailfinger | 6dc1d3b | 2008-05-14 14:51:22 +0000 | [diff] [blame] | 764 | } |
| 765 | |
Carl-Daniel Hailfinger | 1b18b3c | 2008-05-16 14:39:39 +0000 | [diff] [blame] | 766 | static int enable_flash_ich8(struct pci_dev *dev, const char *name) |
| 767 | { |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 768 | return enable_flash_ich_spi(dev, CHIPSET_ICH8, 0xdc); |
Carl-Daniel Hailfinger | 1b18b3c | 2008-05-16 14:39:39 +0000 | [diff] [blame] | 769 | } |
| 770 | |
Carl-Daniel Hailfinger | 6dc1d3b | 2008-05-14 14:51:22 +0000 | [diff] [blame] | 771 | static int enable_flash_ich9(struct pci_dev *dev, const char *name) |
| 772 | { |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 773 | return enable_flash_ich_spi(dev, CHIPSET_ICH9, 0xdc); |
Carl-Daniel Hailfinger | 6dc1d3b | 2008-05-14 14:51:22 +0000 | [diff] [blame] | 774 | } |
| 775 | |
Carl-Daniel Hailfinger | 28ec74b | 2008-10-10 20:54:41 +0000 | [diff] [blame] | 776 | static int enable_flash_ich10(struct pci_dev *dev, const char *name) |
| 777 | { |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 778 | return enable_flash_ich_spi(dev, CHIPSET_ICH10, 0xdc); |
Carl-Daniel Hailfinger | 28ec74b | 2008-10-10 20:54:41 +0000 | [diff] [blame] | 779 | } |
| 780 | |
Stefan Tauner | bd0c70a | 2011-08-27 21:19:56 +0000 | [diff] [blame] | 781 | /* Ibex Peak aka. 5 series & 3400 series */ |
| 782 | static int enable_flash_pch5(struct pci_dev *dev, const char *name) |
| 783 | { |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 784 | return enable_flash_ich_spi(dev, CHIPSET_5_SERIES_IBEX_PEAK, 0xdc); |
Stefan Tauner | bd0c70a | 2011-08-27 21:19:56 +0000 | [diff] [blame] | 785 | } |
| 786 | |
| 787 | /* Cougar Point aka. 6 series & c200 series */ |
| 788 | static int enable_flash_pch6(struct pci_dev *dev, const char *name) |
| 789 | { |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 790 | return enable_flash_ich_spi(dev, CHIPSET_6_SERIES_COUGAR_POINT, 0xdc); |
Stefan Tauner | bd0c70a | 2011-08-27 21:19:56 +0000 | [diff] [blame] | 791 | } |
| 792 | |
Stefan Tauner | 2abab94 | 2012-04-27 20:41:23 +0000 | [diff] [blame] | 793 | /* Panther Point aka. 7 series */ |
| 794 | static int enable_flash_pch7(struct pci_dev *dev, const char *name) |
| 795 | { |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 796 | return enable_flash_ich_spi(dev, CHIPSET_7_SERIES_PANTHER_POINT, 0xdc); |
Stefan Tauner | 2abab94 | 2012-04-27 20:41:23 +0000 | [diff] [blame] | 797 | } |
| 798 | |
| 799 | /* Lynx Point aka. 8 series */ |
| 800 | static int enable_flash_pch8(struct pci_dev *dev, const char *name) |
| 801 | { |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 802 | return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT, 0xdc); |
Stefan Tauner | 2abab94 | 2012-04-27 20:41:23 +0000 | [diff] [blame] | 803 | } |
| 804 | |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 805 | /* Lynx Point LP aka. 8 series low-power */ |
Duncan Laurie | 90eb226 | 2013-03-15 03:12:29 +0000 | [diff] [blame] | 806 | static int enable_flash_pch8_lp(struct pci_dev *dev, const char *name) |
| 807 | { |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 808 | return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_LYNX_POINT_LP, 0xdc); |
Duncan Laurie | 90eb226 | 2013-03-15 03:12:29 +0000 | [diff] [blame] | 809 | } |
| 810 | |
| 811 | /* Wellsburg (for Haswell-EP Xeons) */ |
| 812 | static int enable_flash_pch8_wb(struct pci_dev *dev, const char *name) |
| 813 | { |
Stefan Tauner | 92d6a86 | 2013-10-25 00:33:37 +0000 | [diff] [blame] | 814 | return enable_flash_ich_spi(dev, CHIPSET_8_SERIES_WELLSBURG, 0xdc); |
Duncan Laurie | 90eb226 | 2013-03-15 03:12:29 +0000 | [diff] [blame] | 815 | } |
| 816 | |
Duncan Laurie | 823096e | 2014-08-20 15:39:38 +0000 | [diff] [blame] | 817 | /* Wildcat Point */ |
| 818 | static int enable_flash_pch9(struct pci_dev *dev, const char *name) |
| 819 | { |
| 820 | return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT, 0xdc); |
| 821 | } |
| 822 | |
Nico Huber | 5120591 | 2017-03-17 17:59:54 +0100 | [diff] [blame] | 823 | /* Wildcat Point LP */ |
| 824 | static int enable_flash_pch9_lp(struct pci_dev *dev, const char *name) |
| 825 | { |
| 826 | return enable_flash_ich_spi(dev, CHIPSET_9_SERIES_WILDCAT_POINT_LP, 0xdc); |
| 827 | } |
| 828 | |
Nico Huber | 93c3069 | 2017-03-20 14:25:09 +0100 | [diff] [blame] | 829 | /* Sunrise Point */ |
| 830 | static int enable_flash_pch100_shutdown(void *const pci_acc) |
| 831 | { |
| 832 | pci_cleanup(pci_acc); |
| 833 | return 0; |
| 834 | } |
| 835 | |
David Hendricks | a521636 | 2017-08-08 20:02:22 -0700 | [diff] [blame] | 836 | static int enable_flash_pch100_or_c620(struct pci_dev *const dev, const char *const name, const enum ich_chipset pch_generation) |
Nico Huber | 93c3069 | 2017-03-20 14:25:09 +0100 | [diff] [blame] | 837 | { |
Nico Huber | 93c3069 | 2017-03-20 14:25:09 +0100 | [diff] [blame] | 838 | int ret = ERROR_FATAL; |
| 839 | |
| 840 | /* |
| 841 | * The SPI PCI device is usually hidden (by hiding PCI vendor |
| 842 | * and device IDs). So we need a PCI access method that works |
| 843 | * even when the OS doesn't know the PCI device. We can't use |
| 844 | * this method globally since it would bring along other con- |
| 845 | * straints (e.g. on PCI domains, extended PCIe config space). |
| 846 | */ |
| 847 | struct pci_access *const pci_acc = pci_alloc(); |
Youness Alaoui | a54ceb1 | 2017-07-26 18:03:36 -0400 | [diff] [blame] | 848 | struct pci_access *const saved_pacc = pacc; |
Nico Huber | 93c3069 | 2017-03-20 14:25:09 +0100 | [diff] [blame] | 849 | if (!pci_acc) { |
| 850 | msg_perr("Can't allocate PCI accessor.\n"); |
| 851 | return ret; |
| 852 | } |
| 853 | pci_acc->method = PCI_ACCESS_I386_TYPE1; |
| 854 | pci_init(pci_acc); |
| 855 | register_shutdown(enable_flash_pch100_shutdown, pci_acc); |
| 856 | |
| 857 | struct pci_dev *const spi_dev = pci_get_dev(pci_acc, dev->domain, dev->bus, 0x1f, 5); |
| 858 | if (!spi_dev) { |
| 859 | msg_perr("Can't allocate PCI device.\n"); |
| 860 | return ret; |
| 861 | } |
| 862 | |
Youness Alaoui | a54ceb1 | 2017-07-26 18:03:36 -0400 | [diff] [blame] | 863 | /* Modify pacc so the rpci_write can register the undo callback with a |
| 864 | * device using the correct pci_access */ |
| 865 | pacc = pci_acc; |
Nico Huber | 93c3069 | 2017-03-20 14:25:09 +0100 | [diff] [blame] | 866 | enable_flash_ich_report_gcs(spi_dev, pch_generation, NULL); |
| 867 | |
| 868 | const int ret_bc = enable_flash_ich_bios_cntl_config_space(spi_dev, pch_generation, 0xdc); |
| 869 | if (ret_bc == ERROR_FATAL) |
| 870 | goto _freepci_ret; |
| 871 | |
| 872 | const uint32_t phys_spibar = pci_read_long(spi_dev, PCI_BASE_ADDRESS_0) & 0xfffff000; |
| 873 | void *const spibar = rphysmap("SPIBAR", phys_spibar, 0x1000); |
| 874 | if (spibar == ERROR_PTR) |
| 875 | goto _freepci_ret; |
| 876 | msg_pdbg("SPIBAR = 0x%0*" PRIxPTR " (phys = 0x%08x)\n", PRIxPTR_WIDTH, (uintptr_t)spibar, phys_spibar); |
| 877 | |
| 878 | /* This adds BUS_SPI */ |
| 879 | const int ret_spi = ich_init_spi(spibar, pch_generation); |
| 880 | if (ret_spi != ERROR_FATAL) { |
| 881 | if (ret_bc || ret_spi) |
| 882 | ret = ERROR_NONFATAL; |
| 883 | else |
| 884 | ret = 0; |
| 885 | } |
| 886 | |
| 887 | _freepci_ret: |
| 888 | pci_free_dev(spi_dev); |
Youness Alaoui | a54ceb1 | 2017-07-26 18:03:36 -0400 | [diff] [blame] | 889 | pacc = saved_pacc; |
Nico Huber | 93c3069 | 2017-03-20 14:25:09 +0100 | [diff] [blame] | 890 | return ret; |
| 891 | } |
| 892 | |
David Hendricks | a521636 | 2017-08-08 20:02:22 -0700 | [diff] [blame] | 893 | static int enable_flash_pch100(struct pci_dev *const dev, const char *const name) |
| 894 | { |
| 895 | return enable_flash_pch100_or_c620(dev, name, CHIPSET_100_SERIES_SUNRISE_POINT); |
| 896 | } |
| 897 | |
| 898 | static int enable_flash_c620(struct pci_dev *const dev, const char *const name) |
| 899 | { |
| 900 | return enable_flash_pch100_or_c620(dev, name, CHIPSET_C620_SERIES_LEWISBURG); |
| 901 | } |
| 902 | |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 903 | /* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley. |
| 904 | * These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately. |
| 905 | * |
| 906 | * Differences include: |
| 907 | * - RCBA at LPC config 0xF0 too but mapped range is only 4 B long instead of 16 kB. |
| 908 | * - GCS at [RCRB] + 0 (instead of [RCRB] + 0x3410). |
| 909 | * - TS (Top Swap) in GCS (instead of [RCRB] + 0x3414). |
| 910 | * - SPIBAR (coined SBASE) at LPC config 0x54 (instead of [RCRB] + 0x3800). |
| 911 | * - BIOS_CNTL (coined BCR) at [SPIBAR] + 0xFC (instead of LPC config 0xDC). |
| 912 | */ |
| 913 | static int enable_flash_silvermont(struct pci_dev *dev, const char *name) |
| 914 | { |
| 915 | enum ich_chipset ich_generation = CHIPSET_BAYTRAIL; |
| 916 | |
| 917 | /* Get physical address of Root Complex Register Block */ |
| 918 | uint32_t rcba = pci_read_long(dev, 0xf0) & 0xfffffc00; |
| 919 | msg_pdbg("Root Complex Register Block address = 0x%x\n", rcba); |
| 920 | |
| 921 | /* Handle GCS (in RCRB) */ |
| 922 | void *rcrb = physmap("BYT RCRB", rcba, 4); |
Nico Huber | 0ea99f5 | 2017-03-17 17:22:53 +0100 | [diff] [blame] | 923 | enable_flash_ich_report_gcs(dev, ich_generation, rcrb); |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 924 | physunmap(rcrb, 4); |
| 925 | |
| 926 | /* Handle fwh_idsel parameter */ |
| 927 | int ret_fwh = enable_flash_ich_fwh_decode(dev, ich_generation); |
| 928 | if (ret_fwh == ERROR_FATAL) |
| 929 | return ret_fwh; |
| 930 | |
| 931 | internal_buses_supported = BUS_FWH; |
| 932 | |
| 933 | /* Get physical address of SPI Base Address and map it */ |
| 934 | uint32_t sbase = pci_read_long(dev, 0x54) & 0xfffffe00; |
| 935 | msg_pdbg("SPI_BASE_ADDRESS = 0x%x\n", sbase); |
| 936 | void *spibar = rphysmap("BYT SBASE", sbase, 512); /* Last defined address on Bay Trail is 0x100 */ |
| 937 | |
| 938 | /* Enable Flash Writes. |
| 939 | * Silvermont-based: BCR at SBASE + 0xFC (some bits of BCR are also accessible via BC at IBASE + 0x1C). |
| 940 | */ |
| 941 | enable_flash_ich_bios_cntl_memmapped(ich_generation, spibar + 0xFC); |
| 942 | |
Nico Huber | 560111e | 2017-04-26 12:27:17 +0200 | [diff] [blame] | 943 | int ret_spi = ich_init_spi(spibar, ich_generation); |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 944 | if (ret_spi == ERROR_FATAL) |
| 945 | return ret_spi; |
| 946 | |
| 947 | if (ret_fwh || ret_spi) |
| 948 | return ERROR_NONFATAL; |
| 949 | |
| 950 | return 0; |
| 951 | } |
| 952 | |
Michael Karcher | 89bed6d | 2010-06-13 10:16:12 +0000 | [diff] [blame] | 953 | static int via_no_byte_merge(struct pci_dev *dev, const char *name) |
| 954 | { |
| 955 | uint8_t val; |
| 956 | |
| 957 | val = pci_read_byte(dev, 0x71); |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 958 | if (val & 0x40) { |
Michael Karcher | 89bed6d | 2010-06-13 10:16:12 +0000 | [diff] [blame] | 959 | msg_pdbg("Disabling byte merging\n"); |
| 960 | val &= ~0x40; |
Carl-Daniel Hailfinger | 2bee8cf | 2010-11-10 15:25:18 +0000 | [diff] [blame] | 961 | rpci_write_byte(dev, 0x71, val); |
Michael Karcher | 89bed6d | 2010-06-13 10:16:12 +0000 | [diff] [blame] | 962 | } |
| 963 | return NOT_DONE_YET; /* need to find south bridge, too */ |
| 964 | } |
| 965 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 966 | static int enable_flash_vt823x(struct pci_dev *dev, const char *name) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 967 | { |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 968 | uint8_t val; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 969 | |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 970 | /* Enable ROM decode range (1MB) FFC00000 - FFFFFFFF. */ |
Carl-Daniel Hailfinger | 2bee8cf | 2010-11-10 15:25:18 +0000 | [diff] [blame] | 971 | rpci_write_byte(dev, 0x41, 0x7f); |
Bari Ari | 9477c4e | 2008-04-29 13:46:38 +0000 | [diff] [blame] | 972 | |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 973 | /* ROM write enable */ |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 974 | val = pci_read_byte(dev, 0x40); |
| 975 | val |= 0x10; |
Carl-Daniel Hailfinger | 2bee8cf | 2010-11-10 15:25:18 +0000 | [diff] [blame] | 976 | rpci_write_byte(dev, 0x40, val); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 977 | |
| 978 | if (pci_read_byte(dev, 0x40) != val) { |
Stefan Tauner | c6fa32d | 2013-01-04 22:54:07 +0000 | [diff] [blame] | 979 | msg_pwarn("\nWarning: Failed to enable flash write on \"%s\"\n", name); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 980 | return -1; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 981 | } |
Luc Verhaegen | 6382b44 | 2007-03-02 22:16:38 +0000 | [diff] [blame] | 982 | |
Helge Wagner | dd73d83 | 2012-08-24 23:03:46 +0000 | [diff] [blame] | 983 | if (dev->device_id == 0x3227) { /* VT8237/VT8237R */ |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 984 | /* All memory cycles, not just ROM ones, go to LPC. */ |
| 985 | val = pci_read_byte(dev, 0x59); |
| 986 | val &= ~0x80; |
| 987 | rpci_write_byte(dev, 0x59, val); |
Luc Verhaegen | 73d2119 | 2009-12-23 00:54:26 +0000 | [diff] [blame] | 988 | } |
| 989 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 990 | return 0; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 991 | } |
| 992 | |
Helge Wagner | dd73d83 | 2012-08-24 23:03:46 +0000 | [diff] [blame] | 993 | static int enable_flash_vt_vx(struct pci_dev *dev, const char *name) |
| 994 | { |
| 995 | struct pci_dev *south_north = pci_dev_find(0x1106, 0xa353); |
| 996 | if (south_north == NULL) { |
| 997 | msg_perr("Could not find South-North Module Interface Control device!\n"); |
| 998 | return ERROR_FATAL; |
| 999 | } |
| 1000 | |
| 1001 | msg_pdbg("Strapped to "); |
| 1002 | if ((pci_read_byte(south_north, 0x56) & 0x01) == 0) { |
| 1003 | msg_pdbg("LPC.\n"); |
| 1004 | return enable_flash_vt823x(dev, name); |
| 1005 | } |
| 1006 | msg_pdbg("SPI.\n"); |
| 1007 | |
| 1008 | uint32_t mmio_base; |
| 1009 | void *mmio_base_physmapped; |
| 1010 | uint32_t spi_cntl; |
| 1011 | #define SPI_CNTL_LEN 0x08 |
| 1012 | uint32_t spi0_mm_base = 0; |
| 1013 | switch(dev->device_id) { |
| 1014 | case 0x8353: /* VX800/VX820 */ |
| 1015 | spi0_mm_base = pci_read_long(dev, 0xbc) << 8; |
| 1016 | break; |
| 1017 | case 0x8409: /* VX855/VX875 */ |
| 1018 | case 0x8410: /* VX900 */ |
| 1019 | mmio_base = pci_read_long(dev, 0xbc) << 8; |
| 1020 | mmio_base_physmapped = physmap("VIA VX MMIO register", mmio_base, SPI_CNTL_LEN); |
Stefan Tauner | 7fb5aa0 | 2013-08-14 15:48:44 +0000 | [diff] [blame] | 1021 | if (mmio_base_physmapped == ERROR_PTR) |
Helge Wagner | dd73d83 | 2012-08-24 23:03:46 +0000 | [diff] [blame] | 1022 | return ERROR_FATAL; |
Helge Wagner | dd73d83 | 2012-08-24 23:03:46 +0000 | [diff] [blame] | 1023 | |
| 1024 | /* Offset 0 - Bit 0 holds SPI Bus0 Enable Bit. */ |
| 1025 | spi_cntl = mmio_readl(mmio_base_physmapped) + 0x00; |
| 1026 | if ((spi_cntl & 0x01) == 0) { |
| 1027 | msg_pdbg ("SPI Bus0 disabled!\n"); |
| 1028 | physunmap(mmio_base_physmapped, SPI_CNTL_LEN); |
| 1029 | return ERROR_FATAL; |
| 1030 | } |
| 1031 | /* Offset 1-3 has SPI Bus Memory Map Base Address: */ |
| 1032 | spi0_mm_base = spi_cntl & 0xFFFFFF00; |
| 1033 | |
| 1034 | /* Offset 4 - Bit 0 holds SPI Bus1 Enable Bit. */ |
| 1035 | spi_cntl = mmio_readl(mmio_base_physmapped) + 0x04; |
| 1036 | if ((spi_cntl & 0x01) == 1) |
| 1037 | msg_pdbg2("SPI Bus1 is enabled too.\n"); |
| 1038 | |
| 1039 | physunmap(mmio_base_physmapped, SPI_CNTL_LEN); |
| 1040 | break; |
| 1041 | default: |
| 1042 | msg_perr("%s: Unsupported chipset %x:%x!\n", __func__, dev->vendor_id, dev->device_id); |
| 1043 | return ERROR_FATAL; |
| 1044 | } |
| 1045 | |
Nico Huber | 560111e | 2017-04-26 12:27:17 +0200 | [diff] [blame] | 1046 | return via_init_spi(spi0_mm_base); |
Helge Wagner | dd73d83 | 2012-08-24 23:03:46 +0000 | [diff] [blame] | 1047 | } |
| 1048 | |
| 1049 | static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) |
| 1050 | { |
Nico Huber | 560111e | 2017-04-26 12:27:17 +0200 | [diff] [blame] | 1051 | return via_init_spi(pci_read_long(dev, 0xbc) << 8); |
Helge Wagner | dd73d83 | 2012-08-24 23:03:46 +0000 | [diff] [blame] | 1052 | } |
| 1053 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 1054 | static int enable_flash_cs5530(struct pci_dev *dev, const char *name) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 1055 | { |
Uwe Hermann | f4a673b | 2007-06-06 21:35:45 +0000 | [diff] [blame] | 1056 | uint8_t reg8; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 1057 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 1058 | #define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */ |
| 1059 | #define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */ |
Carl-Daniel Hailfinger | 2a9e245 | 2009-12-17 15:20:01 +0000 | [diff] [blame] | 1060 | #define CS5530_RESET_CONTROL_REG 0x44 /* F0 index 0x44 */ |
| 1061 | #define CS5530_USB_SHADOW_REG 0x43 /* F0 index 0x43 */ |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 1062 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 1063 | #define LOWER_ROM_ADDRESS_RANGE (1 << 0) |
| 1064 | #define ROM_WRITE_ENABLE (1 << 1) |
| 1065 | #define UPPER_ROM_ADDRESS_RANGE (1 << 2) |
| 1066 | #define BIOS_ROM_POSITIVE_DECODE (1 << 5) |
Carl-Daniel Hailfinger | 2a9e245 | 2009-12-17 15:20:01 +0000 | [diff] [blame] | 1067 | #define CS5530_ISA_MASTER (1 << 7) |
| 1068 | #define CS5530_ENABLE_SA2320 (1 << 2) |
| 1069 | #define CS5530_ENABLE_SA20 (1 << 6) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 1070 | |
Carl-Daniel Hailfinger | eaacd2d | 2011-11-09 23:40:00 +0000 | [diff] [blame] | 1071 | internal_buses_supported = BUS_PARALLEL; |
Stefan Tauner | c0aaf95 | 2011-05-19 02:58:17 +0000 | [diff] [blame] | 1072 | /* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and |
| 1073 | * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB. |
Carl-Daniel Hailfinger | 2a9e245 | 2009-12-17 15:20:01 +0000 | [diff] [blame] | 1074 | * FIXME: Should we really touch the low mapping below 1 MB? Flashrom |
| 1075 | * ignores that region completely. |
Uwe Hermann | f4a673b | 2007-06-06 21:35:45 +0000 | [diff] [blame] | 1076 | * Make the configured ROM areas writable. |
| 1077 | */ |
| 1078 | reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG); |
| 1079 | reg8 |= LOWER_ROM_ADDRESS_RANGE; |
| 1080 | reg8 |= UPPER_ROM_ADDRESS_RANGE; |
| 1081 | reg8 |= ROM_WRITE_ENABLE; |
Carl-Daniel Hailfinger | 2bee8cf | 2010-11-10 15:25:18 +0000 | [diff] [blame] | 1082 | rpci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1083 | |
Uwe Hermann | f4a673b | 2007-06-06 21:35:45 +0000 | [diff] [blame] | 1084 | /* Set positive decode on ROM. */ |
| 1085 | reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2); |
| 1086 | reg8 |= BIOS_ROM_POSITIVE_DECODE; |
Carl-Daniel Hailfinger | 2bee8cf | 2010-11-10 15:25:18 +0000 | [diff] [blame] | 1087 | rpci_write_byte(dev, DECODE_CONTROL_REG2, reg8); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1088 | |
Carl-Daniel Hailfinger | 2a9e245 | 2009-12-17 15:20:01 +0000 | [diff] [blame] | 1089 | reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG); |
| 1090 | if (reg8 & CS5530_ISA_MASTER) { |
| 1091 | /* We have A0-A23 available. */ |
| 1092 | max_rom_decode.parallel = 16 * 1024 * 1024; |
| 1093 | } else { |
| 1094 | reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG); |
| 1095 | if (reg8 & CS5530_ENABLE_SA2320) { |
| 1096 | /* We have A0-19, A20-A23 available. */ |
| 1097 | max_rom_decode.parallel = 16 * 1024 * 1024; |
| 1098 | } else if (reg8 & CS5530_ENABLE_SA20) { |
| 1099 | /* We have A0-19, A20 available. */ |
| 1100 | max_rom_decode.parallel = 2 * 1024 * 1024; |
| 1101 | } else { |
| 1102 | /* A20 and above are not active. */ |
| 1103 | max_rom_decode.parallel = 1024 * 1024; |
| 1104 | } |
| 1105 | } |
| 1106 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 1107 | return 0; |
| 1108 | } |
| 1109 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1110 | /* |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 1111 | * Geode systems write protect the BIOS via RCONFs (cache settings similar |
Stefan Reinauer | 8fa6481 | 2009-08-12 09:27:45 +0000 | [diff] [blame] | 1112 | * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22. |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 1113 | * |
| 1114 | * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL. |
| 1115 | * To enable write to NOR Boot flash for the benefit of systems that have such |
| 1116 | * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select). |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 1117 | */ |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 1118 | static int enable_flash_cs5536(struct pci_dev *dev, const char *name) |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 1119 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 1120 | #define MSR_RCONF_DEFAULT 0x1808 |
| 1121 | #define MSR_NORF_CTL 0x51400018 |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 1122 | |
Stefan Reinauer | 8fa6481 | 2009-08-12 09:27:45 +0000 | [diff] [blame] | 1123 | msr_t msr; |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 1124 | |
Stefan Reinauer | 8fa6481 | 2009-08-12 09:27:45 +0000 | [diff] [blame] | 1125 | /* Geode only has a single core */ |
| 1126 | if (setup_cpu_msr(0)) |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 1127 | return -1; |
Stefan Reinauer | 8fa6481 | 2009-08-12 09:27:45 +0000 | [diff] [blame] | 1128 | |
| 1129 | msr = rdmsr(MSR_RCONF_DEFAULT); |
| 1130 | if ((msr.hi >> 24) != 0x22) { |
| 1131 | msr.hi &= 0xfbffffff; |
| 1132 | wrmsr(MSR_RCONF_DEFAULT, msr); |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 1133 | } |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 1134 | |
Stefan Reinauer | 8fa6481 | 2009-08-12 09:27:45 +0000 | [diff] [blame] | 1135 | msr = rdmsr(MSR_NORF_CTL); |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 1136 | /* Raise WE_CS3 bit. */ |
Stefan Reinauer | 8fa6481 | 2009-08-12 09:27:45 +0000 | [diff] [blame] | 1137 | msr.lo |= 0x08; |
| 1138 | wrmsr(MSR_NORF_CTL, msr); |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 1139 | |
Stefan Reinauer | 8fa6481 | 2009-08-12 09:27:45 +0000 | [diff] [blame] | 1140 | cleanup_cpu_msr(); |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 1141 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 1142 | #undef MSR_RCONF_DEFAULT |
| 1143 | #undef MSR_NORF_CTL |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 1144 | return 0; |
| 1145 | } |
| 1146 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 1147 | static int enable_flash_sc1100(struct pci_dev *dev, const char *name) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 1148 | { |
Stefan Tauner | e34e3e8 | 2013-01-01 00:06:51 +0000 | [diff] [blame] | 1149 | #define SC_REG 0x52 |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 1150 | uint8_t new; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 1151 | |
Stefan Tauner | e34e3e8 | 2013-01-01 00:06:51 +0000 | [diff] [blame] | 1152 | rpci_write_byte(dev, SC_REG, 0xee); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 1153 | |
Stefan Tauner | e34e3e8 | 2013-01-01 00:06:51 +0000 | [diff] [blame] | 1154 | new = pci_read_byte(dev, SC_REG); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 1155 | |
Stefan Tauner | e34e3e8 | 2013-01-01 00:06:51 +0000 | [diff] [blame] | 1156 | if (new != 0xee) { /* FIXME: share this with other code? */ |
| 1157 | msg_pinfo("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", SC_REG, new, name); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 1158 | return -1; |
| 1159 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 1160 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 1161 | return 0; |
| 1162 | } |
| 1163 | |
Stefan Tauner | 6c67f1c | 2013-09-12 08:38:23 +0000 | [diff] [blame] | 1164 | /* Works for AMD-768, AMD-8111, VIA VT82C586A/B, VIA VT82C596, VIA VT82C686A/B. |
| 1165 | * |
| 1166 | * ROM decode control register matrix |
| 1167 | * AMD-768 AMD-8111 VT82C586A/B VT82C596 VT82C686A/B |
| 1168 | * 7 FFC0_0000h–FFFF_FFFFh <- FFFE0000h-FFFEFFFFh <- <- |
| 1169 | * 6 FFB0_0000h–FFBF_FFFFh <- FFF80000h-FFFDFFFFh <- <- |
| 1170 | * 5 00E8... <- <- FFF00000h-FFF7FFFFh <- |
| 1171 | */ |
| 1172 | static int enable_flash_amd_via(struct pci_dev *dev, const char *name, uint8_t decode_val) |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 1173 | { |
Stefan Tauner | e34e3e8 | 2013-01-01 00:06:51 +0000 | [diff] [blame] | 1174 | #define AMD_MAPREG 0x43 |
| 1175 | #define AMD_ENREG 0x40 |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 1176 | uint8_t old, new; |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1177 | |
Stefan Tauner | e34e3e8 | 2013-01-01 00:06:51 +0000 | [diff] [blame] | 1178 | old = pci_read_byte(dev, AMD_MAPREG); |
Stefan Tauner | 6c67f1c | 2013-09-12 08:38:23 +0000 | [diff] [blame] | 1179 | new = old | decode_val; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 1180 | if (new != old) { |
Stefan Tauner | e34e3e8 | 2013-01-01 00:06:51 +0000 | [diff] [blame] | 1181 | rpci_write_byte(dev, AMD_MAPREG, new); |
| 1182 | if (pci_read_byte(dev, AMD_MAPREG) != new) { |
Stefan Tauner | 6c67f1c | 2013-09-12 08:38:23 +0000 | [diff] [blame] | 1183 | msg_pwarn("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", |
Stefan Tauner | e34e3e8 | 2013-01-01 00:06:51 +0000 | [diff] [blame] | 1184 | AMD_MAPREG, new, name); |
Stefan Tauner | 6c67f1c | 2013-09-12 08:38:23 +0000 | [diff] [blame] | 1185 | } else |
| 1186 | msg_pdbg("Changed ROM decode range to 0x%02x successfully.\n", new); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 1187 | } |
| 1188 | |
Uwe Hermann | 190f849 | 2008-10-25 18:03:50 +0000 | [diff] [blame] | 1189 | /* Enable 'ROM write' bit. */ |
Stefan Tauner | e34e3e8 | 2013-01-01 00:06:51 +0000 | [diff] [blame] | 1190 | old = pci_read_byte(dev, AMD_ENREG); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 1191 | new = old | 0x01; |
| 1192 | if (new == old) |
| 1193 | return 0; |
Stefan Tauner | e34e3e8 | 2013-01-01 00:06:51 +0000 | [diff] [blame] | 1194 | rpci_write_byte(dev, AMD_ENREG, new); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 1195 | |
Stefan Tauner | e34e3e8 | 2013-01-01 00:06:51 +0000 | [diff] [blame] | 1196 | if (pci_read_byte(dev, AMD_ENREG) != new) { |
Stefan Tauner | 6c67f1c | 2013-09-12 08:38:23 +0000 | [diff] [blame] | 1197 | msg_pwarn("Setting register 0x%x to 0x%02x on %s failed (WARNING ONLY).\n", |
Stefan Tauner | e34e3e8 | 2013-01-01 00:06:51 +0000 | [diff] [blame] | 1198 | AMD_ENREG, new, name); |
Stefan Tauner | 6c67f1c | 2013-09-12 08:38:23 +0000 | [diff] [blame] | 1199 | return ERROR_NONFATAL; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 1200 | } |
Stefan Tauner | 6c67f1c | 2013-09-12 08:38:23 +0000 | [diff] [blame] | 1201 | msg_pdbg2("Set ROM enable bit successfully.\n"); |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 1202 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 1203 | return 0; |
| 1204 | } |
| 1205 | |
Stefan Tauner | 6c67f1c | 2013-09-12 08:38:23 +0000 | [diff] [blame] | 1206 | static int enable_flash_amd_768_8111(struct pci_dev *dev, const char *name) |
| 1207 | { |
| 1208 | /* Enable decoding of 0xFFB00000 to 0xFFFFFFFF (5 MB). */ |
| 1209 | max_rom_decode.lpc = 5 * 1024 * 1024; |
| 1210 | return enable_flash_amd_via(dev, name, 0xC0); |
| 1211 | } |
| 1212 | |
| 1213 | static int enable_flash_vt82c586(struct pci_dev *dev, const char *name) |
| 1214 | { |
| 1215 | /* Enable decoding of 0xFFF80000 to 0xFFFFFFFF. (512 kB) */ |
| 1216 | max_rom_decode.parallel = 512 * 1024; |
| 1217 | return enable_flash_amd_via(dev, name, 0xC0); |
| 1218 | } |
| 1219 | |
| 1220 | /* Works for VT82C686A/B too. */ |
| 1221 | static int enable_flash_vt82c596(struct pci_dev *dev, const char *name) |
| 1222 | { |
Stefan Tauner | c2eec2c | 2014-05-03 21:33:01 +0000 | [diff] [blame] | 1223 | /* Enable decoding of 0xFFF00000 to 0xFFFFFFFF. (1 MB) */ |
Stefan Tauner | 6c67f1c | 2013-09-12 08:38:23 +0000 | [diff] [blame] | 1224 | max_rom_decode.parallel = 1024 * 1024; |
| 1225 | return enable_flash_amd_via(dev, name, 0xE0); |
| 1226 | } |
| 1227 | |
Marc Jones | 3af487d | 2008-10-15 17:50:29 +0000 | [diff] [blame] | 1228 | static int enable_flash_sb600(struct pci_dev *dev, const char *name) |
| 1229 | { |
Michael Karcher | b05b9e1 | 2010-07-22 18:04:19 +0000 | [diff] [blame] | 1230 | uint32_t prot; |
Marc Jones | 3af487d | 2008-10-15 17:50:29 +0000 | [diff] [blame] | 1231 | uint8_t reg; |
Michael Karcher | b05b9e1 | 2010-07-22 18:04:19 +0000 | [diff] [blame] | 1232 | int ret; |
Marc Jones | 3af487d | 2008-10-15 17:50:29 +0000 | [diff] [blame] | 1233 | |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 1234 | /* Clear ROM protect 0-3. */ |
| 1235 | for (reg = 0x50; reg < 0x60; reg += 4) { |
Carl-Daniel Hailfinger | 41d6bd9 | 2009-05-05 22:50:07 +0000 | [diff] [blame] | 1236 | prot = pci_read_long(dev, reg); |
| 1237 | /* No protection flags for this region?*/ |
| 1238 | if ((prot & 0x3) == 0) |
| 1239 | continue; |
Stefan Tauner | 0e0a0dc | 2014-07-15 13:50:17 +0000 | [diff] [blame] | 1240 | msg_pdbg("Chipset %s%sprotected flash from 0x%08x to 0x%08x, unlocking...", |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 1241 | (prot & 0x2) ? "read " : "", |
Stefan Tauner | 0e0a0dc | 2014-07-15 13:50:17 +0000 | [diff] [blame] | 1242 | (prot & 0x1) ? "write " : "", |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 1243 | (prot & 0xfffff800), |
| 1244 | (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff)); |
Carl-Daniel Hailfinger | 41d6bd9 | 2009-05-05 22:50:07 +0000 | [diff] [blame] | 1245 | prot &= 0xfffffffc; |
Carl-Daniel Hailfinger | 2bee8cf | 2010-11-10 15:25:18 +0000 | [diff] [blame] | 1246 | rpci_write_byte(dev, reg, prot); |
Carl-Daniel Hailfinger | 41d6bd9 | 2009-05-05 22:50:07 +0000 | [diff] [blame] | 1247 | prot = pci_read_long(dev, reg); |
Stefan Tauner | 0e0a0dc | 2014-07-15 13:50:17 +0000 | [diff] [blame] | 1248 | if ((prot & 0x3) != 0) { |
| 1249 | msg_perr("Disabling %s%sprotection of flash addresses from 0x%08x to 0x%08x failed.\n", |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 1250 | (prot & 0x2) ? "read " : "", |
Stefan Tauner | 0e0a0dc | 2014-07-15 13:50:17 +0000 | [diff] [blame] | 1251 | (prot & 0x1) ? "write " : "", |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 1252 | (prot & 0xfffff800), |
| 1253 | (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff)); |
Stefan Tauner | 0e0a0dc | 2014-07-15 13:50:17 +0000 | [diff] [blame] | 1254 | continue; |
| 1255 | } |
| 1256 | msg_pdbg("done.\n"); |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 1257 | } |
| 1258 | |
Carl-Daniel Hailfinger | eaacd2d | 2011-11-09 23:40:00 +0000 | [diff] [blame] | 1259 | internal_buses_supported = BUS_LPC | BUS_FWH; |
Michael Karcher | b05b9e1 | 2010-07-22 18:04:19 +0000 | [diff] [blame] | 1260 | |
| 1261 | ret = sb600_probe_spi(dev); |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 1262 | |
Carl-Daniel Hailfinger | 9862251 | 2009-05-15 23:36:23 +0000 | [diff] [blame] | 1263 | /* Read ROM strap override register. */ |
| 1264 | OUTB(0x8f, 0xcd6); |
| 1265 | reg = INB(0xcd7); |
| 1266 | reg &= 0x0e; |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1267 | msg_pdbg("ROM strap override is %sactive", (reg & 0x02) ? "" : "not "); |
Carl-Daniel Hailfinger | 9862251 | 2009-05-15 23:36:23 +0000 | [diff] [blame] | 1268 | if (reg & 0x02) { |
| 1269 | switch ((reg & 0x0c) >> 2) { |
| 1270 | case 0x00: |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1271 | msg_pdbg(": LPC"); |
Carl-Daniel Hailfinger | 9862251 | 2009-05-15 23:36:23 +0000 | [diff] [blame] | 1272 | break; |
| 1273 | case 0x01: |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1274 | msg_pdbg(": PCI"); |
Carl-Daniel Hailfinger | 9862251 | 2009-05-15 23:36:23 +0000 | [diff] [blame] | 1275 | break; |
| 1276 | case 0x02: |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1277 | msg_pdbg(": FWH"); |
Carl-Daniel Hailfinger | 9862251 | 2009-05-15 23:36:23 +0000 | [diff] [blame] | 1278 | break; |
| 1279 | case 0x03: |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1280 | msg_pdbg(": SPI"); |
Carl-Daniel Hailfinger | 9862251 | 2009-05-15 23:36:23 +0000 | [diff] [blame] | 1281 | break; |
| 1282 | } |
| 1283 | } |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1284 | msg_pdbg("\n"); |
Carl-Daniel Hailfinger | 9862251 | 2009-05-15 23:36:23 +0000 | [diff] [blame] | 1285 | |
Carl-Daniel Hailfinger | 41d6bd9 | 2009-05-05 22:50:07 +0000 | [diff] [blame] | 1286 | /* Force enable SPI ROM in SB600 PM register. |
| 1287 | * If we enable SPI ROM here, we have to disable it after we leave. |
Zheng Bao | 284a600 | 2009-05-04 22:33:50 +0000 | [diff] [blame] | 1288 | * But how can we know which ROM we are going to handle? So we have |
| 1289 | * to trade off. We only access LPC ROM if we boot via LPC ROM. And |
Carl-Daniel Hailfinger | 41d6bd9 | 2009-05-05 22:50:07 +0000 | [diff] [blame] | 1290 | * only SPI ROM if we boot via SPI ROM. If you want to access SPI on |
| 1291 | * boards with LPC straps, you have to use the code below. |
Zheng Bao | 284a600 | 2009-05-04 22:33:50 +0000 | [diff] [blame] | 1292 | */ |
| 1293 | /* |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 1294 | OUTB(0x8f, 0xcd6); |
| 1295 | OUTB(0x0e, 0xcd7); |
Zheng Bao | 284a600 | 2009-05-04 22:33:50 +0000 | [diff] [blame] | 1296 | */ |
Marc Jones | 3af487d | 2008-10-15 17:50:29 +0000 | [diff] [blame] | 1297 | |
Michael Karcher | b05b9e1 | 2010-07-22 18:04:19 +0000 | [diff] [blame] | 1298 | return ret; |
Marc Jones | 3af487d | 2008-10-15 17:50:29 +0000 | [diff] [blame] | 1299 | } |
| 1300 | |
Stefan Tauner | b66ba1e | 2012-09-04 01:49:49 +0000 | [diff] [blame] | 1301 | /* sets bit 0 in 0x6d */ |
| 1302 | static int enable_flash_nvidia_common(struct pci_dev *dev, const char *name) |
| 1303 | { |
| 1304 | uint8_t old, new; |
| 1305 | |
| 1306 | old = pci_read_byte(dev, 0x6d); |
| 1307 | new = old | 0x01; |
| 1308 | if (new == old) |
| 1309 | return 0; |
| 1310 | |
| 1311 | rpci_write_byte(dev, 0x6d, new); |
| 1312 | if (pci_read_byte(dev, 0x6d) != new) { |
| 1313 | msg_pinfo("Setting register 0x6d to 0x%02x on %s failed.\n", new, name); |
| 1314 | return 1; |
| 1315 | } |
| 1316 | return 0; |
| 1317 | } |
| 1318 | |
Luc Verhaegen | 90e8e61 | 2009-05-26 09:48:28 +0000 | [diff] [blame] | 1319 | static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name) |
| 1320 | { |
Carl-Daniel Hailfinger | 2bee8cf | 2010-11-10 15:25:18 +0000 | [diff] [blame] | 1321 | rpci_write_byte(dev, 0x92, 0); |
Stefan Tauner | b66ba1e | 2012-09-04 01:49:49 +0000 | [diff] [blame] | 1322 | if (enable_flash_nvidia_common(dev, name)) |
| 1323 | return ERROR_NONFATAL; |
| 1324 | else |
| 1325 | return 0; |
Luc Verhaegen | 90e8e61 | 2009-05-26 09:48:28 +0000 | [diff] [blame] | 1326 | } |
| 1327 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 1328 | static int enable_flash_ck804(struct pci_dev *dev, const char *name) |
Yinghai Lu | 952dfce | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 1329 | { |
Jonathan Kollasch | c819000 | 2012-09-04 03:55:04 +0000 | [diff] [blame] | 1330 | uint32_t segctrl; |
| 1331 | uint8_t reg, old, new; |
| 1332 | unsigned int err = 0; |
Yinghai Lu | 952dfce | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 1333 | |
Jonathan Kollasch | c819000 | 2012-09-04 03:55:04 +0000 | [diff] [blame] | 1334 | /* 0x8A is special: it is a single byte and only one nibble is touched. */ |
| 1335 | reg = 0x8A; |
| 1336 | segctrl = pci_read_byte(dev, reg); |
| 1337 | if ((segctrl & 0x3) != 0x0) { |
| 1338 | if ((segctrl & 0xC) != 0x0) { |
| 1339 | msg_pinfo("Can not unlock existing protection in register 0x%02x.\n", reg); |
| 1340 | err++; |
| 1341 | } else { |
| 1342 | msg_pdbg("Unlocking protection in register 0x%02x... ", reg); |
| 1343 | rpci_write_byte(dev, reg, segctrl & 0xF0); |
| 1344 | |
| 1345 | segctrl = pci_read_byte(dev, reg); |
| 1346 | if ((segctrl & 0x3) != 0x0) { |
| 1347 | msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%x).\n", |
| 1348 | reg, segctrl); |
| 1349 | err++; |
| 1350 | } else |
| 1351 | msg_pdbg("OK\n"); |
| 1352 | } |
Jonathan Kollasch | 9ce498e | 2011-08-06 12:45:21 +0000 | [diff] [blame] | 1353 | } |
| 1354 | |
Jonathan Kollasch | c819000 | 2012-09-04 03:55:04 +0000 | [diff] [blame] | 1355 | for (reg = 0x8C; reg <= 0x94; reg += 4) { |
| 1356 | segctrl = pci_read_long(dev, reg); |
| 1357 | if ((segctrl & 0x33333333) == 0x00000000) { |
| 1358 | /* reads and writes are unlocked */ |
| 1359 | continue; |
| 1360 | } |
| 1361 | if ((segctrl & 0xCCCCCCCC) != 0x00000000) { |
| 1362 | msg_pinfo("Can not unlock existing protection in register 0x%02x.\n", reg); |
| 1363 | err++; |
| 1364 | continue; |
| 1365 | } |
| 1366 | msg_pdbg("Unlocking protection in register 0x%02x... ", reg); |
| 1367 | rpci_write_long(dev, reg, 0x00000000); |
| 1368 | |
| 1369 | segctrl = pci_read_long(dev, reg); |
| 1370 | if ((segctrl & 0x33333333) != 0x00000000) { |
| 1371 | msg_pinfo("Could not unlock protection in register 0x%02x (new value: 0x%08x).\n", |
| 1372 | reg, segctrl); |
| 1373 | err++; |
| 1374 | } else |
| 1375 | msg_pdbg("OK\n"); |
| 1376 | } |
| 1377 | |
| 1378 | if (err > 0) { |
| 1379 | msg_pinfo("%d locks could not be disabled, disabling writes (reads may also fail).\n", err); |
| 1380 | programmer_may_write = 0; |
| 1381 | } |
| 1382 | |
| 1383 | reg = 0x88; |
| 1384 | old = pci_read_byte(dev, reg); |
| 1385 | new = old | 0xC0; |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1386 | if (new != old) { |
Jonathan Kollasch | c819000 | 2012-09-04 03:55:04 +0000 | [diff] [blame] | 1387 | rpci_write_byte(dev, reg, new); |
Stefan Tauner | e34e3e8 | 2013-01-01 00:06:51 +0000 | [diff] [blame] | 1388 | if (pci_read_byte(dev, reg) != new) { /* FIXME: share this with other code? */ |
| 1389 | msg_pinfo("Setting register 0x%02x to 0x%02x on %s failed.\n", reg, new, name); |
Jonathan Kollasch | c819000 | 2012-09-04 03:55:04 +0000 | [diff] [blame] | 1390 | err++; |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1391 | } |
| 1392 | } |
Yinghai Lu | 952dfce | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 1393 | |
Stefan Tauner | b66ba1e | 2012-09-04 01:49:49 +0000 | [diff] [blame] | 1394 | if (enable_flash_nvidia_common(dev, name)) |
Jonathan Kollasch | c819000 | 2012-09-04 03:55:04 +0000 | [diff] [blame] | 1395 | err++; |
| 1396 | |
| 1397 | if (err > 0) |
Stefan Tauner | b66ba1e | 2012-09-04 01:49:49 +0000 | [diff] [blame] | 1398 | return ERROR_NONFATAL; |
| 1399 | else |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1400 | return 0; |
Yinghai Lu | 952dfce | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 1401 | } |
| 1402 | |
Joshua Roys | 85835d8 | 2010-09-15 14:47:56 +0000 | [diff] [blame] | 1403 | static int enable_flash_osb4(struct pci_dev *dev, const char *name) |
| 1404 | { |
| 1405 | uint8_t tmp; |
| 1406 | |
Carl-Daniel Hailfinger | eaacd2d | 2011-11-09 23:40:00 +0000 | [diff] [blame] | 1407 | internal_buses_supported = BUS_PARALLEL; |
Joshua Roys | 85835d8 | 2010-09-15 14:47:56 +0000 | [diff] [blame] | 1408 | |
| 1409 | tmp = INB(0xc06); |
| 1410 | tmp |= 0x1; |
| 1411 | OUTB(tmp, 0xc06); |
| 1412 | |
| 1413 | tmp = INB(0xc6f); |
| 1414 | tmp |= 0x40; |
| 1415 | OUTB(tmp, 0xc6f); |
| 1416 | |
| 1417 | return 0; |
| 1418 | } |
| 1419 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 1420 | /* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */ |
| 1421 | static int enable_flash_sb400(struct pci_dev *dev, const char *name) |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 1422 | { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1423 | uint8_t tmp; |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 1424 | struct pci_dev *smbusdev; |
| 1425 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 1426 | /* Look for the SMBus device. */ |
Carl-Daniel Hailfinger | f6e3efb | 2009-05-06 00:35:31 +0000 | [diff] [blame] | 1427 | smbusdev = pci_dev_find(0x1002, 0x4372); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1428 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1429 | if (!smbusdev) { |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1430 | msg_perr("ERROR: SMBus device not found. Aborting.\n"); |
Tadas Slotkus | 0e3f1cf | 2011-09-06 18:49:31 +0000 | [diff] [blame] | 1431 | return ERROR_FATAL; |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 1432 | } |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1433 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 1434 | /* Enable some SMBus stuff. */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1435 | tmp = pci_read_byte(smbusdev, 0x79); |
| 1436 | tmp |= 0x01; |
Carl-Daniel Hailfinger | 2bee8cf | 2010-11-10 15:25:18 +0000 | [diff] [blame] | 1437 | rpci_write_byte(smbusdev, 0x79, tmp); |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 1438 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 1439 | /* Change southbridge. */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1440 | tmp = pci_read_byte(dev, 0x48); |
| 1441 | tmp |= 0x21; |
Carl-Daniel Hailfinger | 2bee8cf | 2010-11-10 15:25:18 +0000 | [diff] [blame] | 1442 | rpci_write_byte(dev, 0x48, tmp); |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 1443 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 1444 | /* Now become a bit silly. */ |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 1445 | tmp = INB(0xc6f); |
| 1446 | OUTB(tmp, 0xeb); |
| 1447 | OUTB(tmp, 0xeb); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1448 | tmp |= 0x40; |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 1449 | OUTB(tmp, 0xc6f); |
| 1450 | OUTB(tmp, 0xeb); |
| 1451 | OUTB(tmp, 0xeb); |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 1452 | |
| 1453 | return 0; |
| 1454 | } |
| 1455 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 1456 | static int enable_flash_mcp55(struct pci_dev *dev, const char *name) |
Yinghai Lu | ca78297 | 2007-01-22 20:21:17 +0000 | [diff] [blame] | 1457 | { |
Stefan Tauner | b66ba1e | 2012-09-04 01:49:49 +0000 | [diff] [blame] | 1458 | uint8_t val; |
Michael Karcher | 4e2fb0e | 2010-01-12 23:29:26 +0000 | [diff] [blame] | 1459 | uint16_t wordval; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1460 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 1461 | /* Set the 0-16 MB enable bits. */ |
Michael Karcher | 4e2fb0e | 2010-01-12 23:29:26 +0000 | [diff] [blame] | 1462 | val = pci_read_byte(dev, 0x88); |
| 1463 | val |= 0xff; /* 256K */ |
Carl-Daniel Hailfinger | 2bee8cf | 2010-11-10 15:25:18 +0000 | [diff] [blame] | 1464 | rpci_write_byte(dev, 0x88, val); |
Michael Karcher | 4e2fb0e | 2010-01-12 23:29:26 +0000 | [diff] [blame] | 1465 | val = pci_read_byte(dev, 0x8c); |
| 1466 | val |= 0xff; /* 1M */ |
Carl-Daniel Hailfinger | 2bee8cf | 2010-11-10 15:25:18 +0000 | [diff] [blame] | 1467 | rpci_write_byte(dev, 0x8c, val); |
Michael Karcher | 4e2fb0e | 2010-01-12 23:29:26 +0000 | [diff] [blame] | 1468 | wordval = pci_read_word(dev, 0x90); |
| 1469 | wordval |= 0x7fff; /* 16M */ |
Carl-Daniel Hailfinger | 2bee8cf | 2010-11-10 15:25:18 +0000 | [diff] [blame] | 1470 | rpci_write_word(dev, 0x90, wordval); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 1471 | |
Stefan Tauner | b66ba1e | 2012-09-04 01:49:49 +0000 | [diff] [blame] | 1472 | if (enable_flash_nvidia_common(dev, name)) |
| 1473 | return ERROR_NONFATAL; |
| 1474 | else |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1475 | return 0; |
Yinghai Lu | ca78297 | 2007-01-22 20:21:17 +0000 | [diff] [blame] | 1476 | } |
| 1477 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1478 | /* |
Carl-Daniel Hailfinger | 2f43616 | 2010-07-28 15:08:35 +0000 | [diff] [blame] | 1479 | * The MCP6x/MCP7x code is based on cleanroom reverse engineering. |
| 1480 | * It is assumed that LPC chips need the MCP55 code and SPI chips need the |
| 1481 | * code provided in enable_flash_mcp6x_7x_common. |
Carl-Daniel Hailfinger | ea3b1b4 | 2010-02-13 23:41:01 +0000 | [diff] [blame] | 1482 | */ |
Carl-Daniel Hailfinger | 2f43616 | 2010-07-28 15:08:35 +0000 | [diff] [blame] | 1483 | static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name) |
Carl-Daniel Hailfinger | ea3b1b4 | 2010-02-13 23:41:01 +0000 | [diff] [blame] | 1484 | { |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 1485 | int ret = 0, want_spi = 0; |
Michael Karcher | cfa674f | 2010-02-25 11:38:23 +0000 | [diff] [blame] | 1486 | uint8_t val; |
Carl-Daniel Hailfinger | ea3b1b4 | 2010-02-13 23:41:01 +0000 | [diff] [blame] | 1487 | |
| 1488 | /* dev is the ISA bridge. No idea what the stuff below does. */ |
Michael Karcher | cfa674f | 2010-02-25 11:38:23 +0000 | [diff] [blame] | 1489 | val = pci_read_byte(dev, 0x8a); |
Carl-Daniel Hailfinger | ce5fad0 | 2010-02-18 12:24:38 +0000 | [diff] [blame] | 1490 | msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 " |
Michael Karcher | cfa674f | 2010-02-25 11:38:23 +0000 | [diff] [blame] | 1491 | "is %i\n", val, (val >> 6) & 0x1, (val >> 5) & 0x1); |
Carl-Daniel Hailfinger | 2f43616 | 2010-07-28 15:08:35 +0000 | [diff] [blame] | 1492 | |
Michael Karcher | cfa674f | 2010-02-25 11:38:23 +0000 | [diff] [blame] | 1493 | switch ((val >> 5) & 0x3) { |
Carl-Daniel Hailfinger | ce5fad0 | 2010-02-18 12:24:38 +0000 | [diff] [blame] | 1494 | case 0x0: |
Carl-Daniel Hailfinger | 2f43616 | 2010-07-28 15:08:35 +0000 | [diff] [blame] | 1495 | ret = enable_flash_mcp55(dev, name); |
Carl-Daniel Hailfinger | eaacd2d | 2011-11-09 23:40:00 +0000 | [diff] [blame] | 1496 | internal_buses_supported = BUS_LPC; |
Carl-Daniel Hailfinger | 2f43616 | 2010-07-28 15:08:35 +0000 | [diff] [blame] | 1497 | msg_pdbg("Flash bus type is LPC\n"); |
Carl-Daniel Hailfinger | ce5fad0 | 2010-02-18 12:24:38 +0000 | [diff] [blame] | 1498 | break; |
| 1499 | case 0x2: |
Carl-Daniel Hailfinger | 2f43616 | 2010-07-28 15:08:35 +0000 | [diff] [blame] | 1500 | want_spi = 1; |
| 1501 | /* SPI is added in mcp6x_spi_init if it works. |
| 1502 | * Do we really want to disable LPC in this case? |
| 1503 | */ |
Carl-Daniel Hailfinger | eaacd2d | 2011-11-09 23:40:00 +0000 | [diff] [blame] | 1504 | internal_buses_supported = BUS_NONE; |
Carl-Daniel Hailfinger | 2f43616 | 2010-07-28 15:08:35 +0000 | [diff] [blame] | 1505 | msg_pdbg("Flash bus type is SPI\n"); |
Carl-Daniel Hailfinger | ce5fad0 | 2010-02-18 12:24:38 +0000 | [diff] [blame] | 1506 | break; |
| 1507 | default: |
Carl-Daniel Hailfinger | 2f43616 | 2010-07-28 15:08:35 +0000 | [diff] [blame] | 1508 | /* Should not happen. */ |
Carl-Daniel Hailfinger | eaacd2d | 2011-11-09 23:40:00 +0000 | [diff] [blame] | 1509 | internal_buses_supported = BUS_NONE; |
Stefan Tauner | 7ba3d6c | 2014-06-12 21:07:03 +0000 | [diff] [blame] | 1510 | msg_pwarn("Flash bus type is unknown (none)\n"); |
| 1511 | msg_pinfo("Please send the log files created by \"flashrom -p internal -o logfile\" to \n" |
| 1512 | "flashrom@flashrom.org with \"your board name: flashrom -V\" as the subject to\n" |
| 1513 | "help us finish support for your chipset. Thanks.\n"); |
| 1514 | return ERROR_NONFATAL; |
Carl-Daniel Hailfinger | ce5fad0 | 2010-02-18 12:24:38 +0000 | [diff] [blame] | 1515 | } |
Carl-Daniel Hailfinger | ce5fad0 | 2010-02-18 12:24:38 +0000 | [diff] [blame] | 1516 | |
| 1517 | /* Force enable SPI and disable LPC? Not a good idea. */ |
Carl-Daniel Hailfinger | ea3b1b4 | 2010-02-13 23:41:01 +0000 | [diff] [blame] | 1518 | #if 0 |
Michael Karcher | cfa674f | 2010-02-25 11:38:23 +0000 | [diff] [blame] | 1519 | val |= (1 << 6); |
| 1520 | val &= ~(1 << 5); |
Carl-Daniel Hailfinger | 2bee8cf | 2010-11-10 15:25:18 +0000 | [diff] [blame] | 1521 | rpci_write_byte(dev, 0x8a, val); |
Carl-Daniel Hailfinger | ea3b1b4 | 2010-02-13 23:41:01 +0000 | [diff] [blame] | 1522 | #endif |
| 1523 | |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 1524 | if (mcp6x_spi_init(want_spi)) |
Carl-Daniel Hailfinger | ce5fad0 | 2010-02-18 12:24:38 +0000 | [diff] [blame] | 1525 | ret = 1; |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 1526 | |
Carl-Daniel Hailfinger | ce5fad0 | 2010-02-18 12:24:38 +0000 | [diff] [blame] | 1527 | return ret; |
| 1528 | } |
| 1529 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 1530 | static int enable_flash_ht1000(struct pci_dev *dev, const char *name) |
Stefan Reinauer | c868b9e | 2007-06-05 10:28:39 +0000 | [diff] [blame] | 1531 | { |
Michael Karcher | cfa674f | 2010-02-25 11:38:23 +0000 | [diff] [blame] | 1532 | uint8_t val; |
Stefan Reinauer | c868b9e | 2007-06-05 10:28:39 +0000 | [diff] [blame] | 1533 | |
Uwe Hermann | e823ee0 | 2007-06-05 15:02:18 +0000 | [diff] [blame] | 1534 | /* Set the 4MB enable bit. */ |
Michael Karcher | cfa674f | 2010-02-25 11:38:23 +0000 | [diff] [blame] | 1535 | val = pci_read_byte(dev, 0x41); |
| 1536 | val |= 0x0e; |
Carl-Daniel Hailfinger | 2bee8cf | 2010-11-10 15:25:18 +0000 | [diff] [blame] | 1537 | rpci_write_byte(dev, 0x41, val); |
Stefan Reinauer | c868b9e | 2007-06-05 10:28:39 +0000 | [diff] [blame] | 1538 | |
Michael Karcher | cfa674f | 2010-02-25 11:38:23 +0000 | [diff] [blame] | 1539 | val = pci_read_byte(dev, 0x43); |
| 1540 | val |= (1 << 4); |
Carl-Daniel Hailfinger | 2bee8cf | 2010-11-10 15:25:18 +0000 | [diff] [blame] | 1541 | rpci_write_byte(dev, 0x43, val); |
Stefan Reinauer | c868b9e | 2007-06-05 10:28:39 +0000 | [diff] [blame] | 1542 | |
Stefan Reinauer | c868b9e | 2007-06-05 10:28:39 +0000 | [diff] [blame] | 1543 | return 0; |
| 1544 | } |
| 1545 | |
Uwe Hermann | 48ec1b1 | 2010-08-08 17:01:18 +0000 | [diff] [blame] | 1546 | /* |
Stefan Reinauer | 9a6d176 | 2008-12-03 21:24:40 +0000 | [diff] [blame] | 1547 | * Usually on the x86 architectures (and on other PC-like platforms like some |
| 1548 | * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD |
| 1549 | * Elan SC520 only a small piece of the system flash is mapped there, but the |
| 1550 | * complete flash is mapped somewhere below 1G. The position can be determined |
| 1551 | * by the BOOTCS PAR register. |
| 1552 | */ |
| 1553 | static int get_flashbase_sc520(struct pci_dev *dev, const char *name) |
| 1554 | { |
| 1555 | int i, bootcs_found = 0; |
| 1556 | uint32_t parx = 0; |
| 1557 | void *mmcr; |
| 1558 | |
| 1559 | /* 1. Map MMCR */ |
Stefan Reinauer | 0593f21 | 2009-01-26 01:10:48 +0000 | [diff] [blame] | 1560 | mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize()); |
Niklas Söderlund | 5d30720 | 2013-09-14 09:02:27 +0000 | [diff] [blame] | 1561 | if (mmcr == ERROR_PTR) |
| 1562 | return ERROR_FATAL; |
Stefan Reinauer | 9a6d176 | 2008-12-03 21:24:40 +0000 | [diff] [blame] | 1563 | |
| 1564 | /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for |
| 1565 | * BOOTCS region (PARx[31:29] = 100b)e |
| 1566 | */ |
| 1567 | for (i = 0x88; i <= 0xc4; i += 4) { |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 1568 | parx = mmio_readl(mmcr + i); |
Stefan Reinauer | 9a6d176 | 2008-12-03 21:24:40 +0000 | [diff] [blame] | 1569 | if ((parx >> 29) == 4) { |
| 1570 | bootcs_found = 1; |
| 1571 | break; /* BOOTCS found */ |
| 1572 | } |
| 1573 | } |
| 1574 | |
| 1575 | /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0] |
| 1576 | * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0] |
| 1577 | */ |
| 1578 | if (bootcs_found) { |
| 1579 | if (parx & (1 << 25)) { |
| 1580 | parx &= (1 << 14) - 1; /* Mask [13:0] */ |
| 1581 | flashbase = parx << 16; |
| 1582 | } else { |
| 1583 | parx &= (1 << 18) - 1; /* Mask [17:0] */ |
| 1584 | flashbase = parx << 12; |
| 1585 | } |
| 1586 | } else { |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 1587 | msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. " |
Carl-Daniel Hailfinger | 082c8b5 | 2011-08-15 19:54:20 +0000 | [diff] [blame] | 1588 | "Assuming flash at 4G.\n"); |
Stefan Reinauer | 9a6d176 | 2008-12-03 21:24:40 +0000 | [diff] [blame] | 1589 | } |
| 1590 | |
| 1591 | /* 4. Clean up */ |
Carl-Daniel Hailfinger | be72681 | 2009-08-09 12:44:08 +0000 | [diff] [blame] | 1592 | physunmap(mmcr, getpagesize()); |
Stefan Reinauer | 9a6d176 | 2008-12-03 21:24:40 +0000 | [diff] [blame] | 1593 | return 0; |
| 1594 | } |
| 1595 | |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 1596 | #endif |
| 1597 | |
Idwer Vollering | 326a060 | 2011-06-18 18:45:41 +0000 | [diff] [blame] | 1598 | /* Please keep this list numerically sorted by vendor/device ID. */ |
Uwe Hermann | 05fab75 | 2009-05-16 23:42:17 +0000 | [diff] [blame] | 1599 | const struct penable chipset_enables[] = { |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 1600 | #if defined(__i386__) || defined(__x86_64__) |
Stefan Tauner | 428ba2b | 2014-06-02 00:34:58 +0000 | [diff] [blame] | 1601 | {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400}, |
| 1602 | {0x1002, 0x438d, OK, "AMD", "SB600", enable_flash_sb600}, |
| 1603 | {0x1002, 0x439d, OK, "AMD", "SB7x0/SB8x0/SB9x0", enable_flash_sb600}, |
| 1604 | {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100}, |
| 1605 | {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536}, |
| 1606 | {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536}, |
| 1607 | {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520}, |
| 1608 | {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd_768_8111}, |
| 1609 | {0x1022, 0x7468, OK, "AMD", "AMD-8111", enable_flash_amd_768_8111}, |
| 1610 | {0x1022, 0x780e, OK, "AMD", "FCH", enable_flash_sb600}, |
Ricardo Ribalda Delgado | 7b629bc | 2017-03-22 14:08:31 +0100 | [diff] [blame] | 1611 | {0x1022, 0x790e, OK, "AMD", "FP4", enable_flash_sb600}, |
Stefan Tauner | 428ba2b | 2014-06-02 00:34:58 +0000 | [diff] [blame] | 1612 | {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501}, |
| 1613 | {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496}, |
| 1614 | {0x1039, 0x0530, OK, "SiS", "530", enable_flash_sis530}, |
| 1615 | {0x1039, 0x0540, NT, "SiS", "540", enable_flash_sis540}, |
| 1616 | {0x1039, 0x0620, NT, "SiS", "620", enable_flash_sis530}, |
Nico Huber | bbf0dbd | 2017-11-19 16:29:45 +0100 | [diff] [blame] | 1617 | {0x1039, 0x0630, OK, "SiS", "630", enable_flash_sis540}, |
Stefan Tauner | 428ba2b | 2014-06-02 00:34:58 +0000 | [diff] [blame] | 1618 | {0x1039, 0x0635, NT, "SiS", "635", enable_flash_sis540}, |
| 1619 | {0x1039, 0x0640, NT, "SiS", "640", enable_flash_sis540}, |
| 1620 | {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis540}, |
| 1621 | {0x1039, 0x0646, OK, "SiS", "645DX", enable_flash_sis540}, |
| 1622 | {0x1039, 0x0648, OK, "SiS", "648", enable_flash_sis540}, |
| 1623 | {0x1039, 0x0650, OK, "SiS", "650", enable_flash_sis540}, |
| 1624 | {0x1039, 0x0651, OK, "SiS", "651", enable_flash_sis540}, |
| 1625 | {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis540}, |
| 1626 | {0x1039, 0x0661, OK, "SiS", "661", enable_flash_sis540}, |
| 1627 | {0x1039, 0x0730, OK, "SiS", "730", enable_flash_sis540}, |
| 1628 | {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis540}, |
| 1629 | {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis540}, |
| 1630 | {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis540}, |
| 1631 | {0x1039, 0x0741, OK, "SiS", "741", enable_flash_sis540}, |
| 1632 | {0x1039, 0x0745, OK, "SiS", "745", enable_flash_sis540}, |
| 1633 | {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540}, |
| 1634 | {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540}, |
| 1635 | {0x1039, 0x0755, OK, "SiS", "755", enable_flash_sis540}, |
| 1636 | {0x1039, 0x5511, NT, "SiS", "5511", enable_flash_sis5511}, |
| 1637 | {0x1039, 0x5571, NT, "SiS", "5571", enable_flash_sis530}, |
| 1638 | {0x1039, 0x5591, NT, "SiS", "5591/5592", enable_flash_sis530}, |
| 1639 | {0x1039, 0x5596, NT, "SiS", "5596", enable_flash_sis5511}, |
| 1640 | {0x1039, 0x5597, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530}, |
| 1641 | {0x1039, 0x5600, NT, "SiS", "600", enable_flash_sis530}, |
| 1642 | {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530}, |
| 1643 | {0x10b9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, |
| 1644 | {0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2}, |
| 1645 | {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */ |
| 1646 | {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */ |
| 1647 | {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2}, |
| 1648 | {0x10de, 0x00e0, OK, "NVIDIA", "NForce3", enable_flash_nvidia_nforce2}, |
Uwe Hermann | eac1016 | 2008-03-13 18:52:51 +0000 | [diff] [blame] | 1649 | /* Slave, should not be here, to fix known bug for A01. */ |
Stefan Tauner | 428ba2b | 2014-06-02 00:34:58 +0000 | [diff] [blame] | 1650 | {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804}, |
| 1651 | {0x10de, 0x0260, OK, "NVIDIA", "MCP51", enable_flash_ck804}, |
| 1652 | {0x10de, 0x0261, OK, "NVIDIA", "MCP51", enable_flash_ck804}, |
| 1653 | {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804}, |
| 1654 | {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804}, |
| 1655 | {0x10de, 0x0360, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/ |
Carl-Daniel Hailfinger | 33d7b6a | 2010-05-22 07:27:16 +0000 | [diff] [blame] | 1656 | /* 10de:0361 is present in Tyan S2915 OEM systems, but not connected to |
| 1657 | * the flash chip. Instead, 10de:0364 is connected to the flash chip. |
| 1658 | * Until we have PCI device class matching or some fallback mechanism, |
| 1659 | * this is needed to get flashrom working on Tyan S2915 and maybe other |
| 1660 | * dual-MCP55 boards. |
| 1661 | */ |
| 1662 | #if 0 |
Stefan Tauner | 428ba2b | 2014-06-02 00:34:58 +0000 | [diff] [blame] | 1663 | {0x10de, 0x0361, NT, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ |
Carl-Daniel Hailfinger | 33d7b6a | 2010-05-22 07:27:16 +0000 | [diff] [blame] | 1664 | #endif |
Stefan Tauner | 428ba2b | 2014-06-02 00:34:58 +0000 | [diff] [blame] | 1665 | {0x10de, 0x0362, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ |
| 1666 | {0x10de, 0x0363, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ |
| 1667 | {0x10de, 0x0364, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ |
| 1668 | {0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ |
| 1669 | {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ |
| 1670 | {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */ |
| 1671 | {0x10de, 0x03e0, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, |
| 1672 | {0x10de, 0x03e1, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, |
| 1673 | {0x10de, 0x03e3, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x}, |
| 1674 | {0x10de, 0x0440, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, |
| 1675 | {0x10de, 0x0441, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, |
| 1676 | {0x10de, 0x0442, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, |
| 1677 | {0x10de, 0x0443, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x}, |
| 1678 | {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp6x_7x}, |
| 1679 | {0x10de, 0x075c, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x}, |
| 1680 | {0x10de, 0x075d, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x}, |
| 1681 | {0x10de, 0x07d7, OK, "NVIDIA", "MCP73", enable_flash_mcp6x_7x}, |
| 1682 | {0x10de, 0x0aac, OK, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, |
| 1683 | {0x10de, 0x0aad, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, |
| 1684 | {0x10de, 0x0aae, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, |
| 1685 | {0x10de, 0x0aaf, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x}, |
| 1686 | {0x10de, 0x0d80, NT, "NVIDIA", "MCP89", enable_flash_mcp6x_7x}, |
Michael Karcher | 89bed6d | 2010-06-13 10:16:12 +0000 | [diff] [blame] | 1687 | /* VIA northbridges */ |
Stefan Tauner | 428ba2b | 2014-06-02 00:34:58 +0000 | [diff] [blame] | 1688 | {0x1106, 0x0585, NT, "VIA", "VT82C585VPX", via_no_byte_merge}, |
| 1689 | {0x1106, 0x0595, NT, "VIA", "VT82C595", via_no_byte_merge}, |
| 1690 | {0x1106, 0x0597, NT, "VIA", "VT82C597", via_no_byte_merge}, |
| 1691 | {0x1106, 0x0601, NT, "VIA", "VT8601/VT8601A", via_no_byte_merge}, |
| 1692 | {0x1106, 0x0691, OK, "VIA", "VT82C69x", via_no_byte_merge}, |
| 1693 | {0x1106, 0x8601, NT, "VIA", "VT8601T", via_no_byte_merge}, |
Michael Karcher | 89bed6d | 2010-06-13 10:16:12 +0000 | [diff] [blame] | 1694 | /* VIA southbridges */ |
Stefan Tauner | 428ba2b | 2014-06-02 00:34:58 +0000 | [diff] [blame] | 1695 | {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_vt82c586}, |
| 1696 | {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_vt82c596}, |
| 1697 | {0x1106, 0x0686, OK, "VIA", "VT82C686A/B", enable_flash_vt82c596}, |
| 1698 | {0x1106, 0x3074, OK, "VIA", "VT8233", enable_flash_vt823x}, |
| 1699 | {0x1106, 0x3147, OK, "VIA", "VT8233A", enable_flash_vt823x}, |
| 1700 | {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x}, |
| 1701 | {0x1106, 0x3227, OK, "VIA", "VT8237(R)", enable_flash_vt823x}, |
Stefan Tauner | 94d8665 | 2015-11-21 23:35:47 +0000 | [diff] [blame] | 1702 | {0x1106, 0x3287, OK, "VIA", "VT8251", enable_flash_vt823x}, |
Stefan Tauner | 428ba2b | 2014-06-02 00:34:58 +0000 | [diff] [blame] | 1703 | {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x}, |
| 1704 | {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi}, |
| 1705 | {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x}, |
| 1706 | {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x}, |
| 1707 | {0x1106, 0x8353, NT, "VIA", "VX800/VX820", enable_flash_vt_vx}, |
| 1708 | {0x1106, 0x8409, NT, "VIA", "VX855/VX875", enable_flash_vt_vx}, |
| 1709 | {0x1106, 0x8410, NT, "VIA", "VX900", enable_flash_vt_vx}, |
| 1710 | {0x1166, 0x0200, OK, "Broadcom", "OSB4", enable_flash_osb4}, |
| 1711 | {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, |
| 1712 | {0x17f3, 0x6030, OK, "RDC", "R8610/R3210", enable_flash_rdc_r8610}, |
| 1713 | {0x8086, 0x0c60, NT, "Intel", "S12x0", enable_flash_s12x0}, |
Stefan Tauner | 5c316f9 | 2015-02-08 21:57:52 +0000 | [diff] [blame] | 1714 | {0x8086, 0x0f1c, OK, "Intel", "Bay Trail", enable_flash_silvermont}, |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 1715 | {0x8086, 0x0f1d, NT, "Intel", "Bay Trail", enable_flash_silvermont}, |
| 1716 | {0x8086, 0x0f1e, NT, "Intel", "Bay Trail", enable_flash_silvermont}, |
| 1717 | {0x8086, 0x0f1f, NT, "Intel", "Bay Trail", enable_flash_silvermont}, |
Stefan Tauner | 428ba2b | 2014-06-02 00:34:58 +0000 | [diff] [blame] | 1718 | {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4}, |
| 1719 | {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4}, |
| 1720 | {0x8086, 0x1c44, DEP, "Intel", "Z68", enable_flash_pch6}, |
| 1721 | {0x8086, 0x1c46, DEP, "Intel", "P67", enable_flash_pch6}, |
| 1722 | {0x8086, 0x1c47, NT, "Intel", "UM67", enable_flash_pch6}, |
| 1723 | {0x8086, 0x1c49, NT, "Intel", "HM65", enable_flash_pch6}, |
| 1724 | {0x8086, 0x1c4a, DEP, "Intel", "H67", enable_flash_pch6}, |
| 1725 | {0x8086, 0x1c4b, NT, "Intel", "HM67", enable_flash_pch6}, |
| 1726 | {0x8086, 0x1c4c, NT, "Intel", "Q65", enable_flash_pch6}, |
| 1727 | {0x8086, 0x1c4d, NT, "Intel", "QS67", enable_flash_pch6}, |
| 1728 | {0x8086, 0x1c4e, NT, "Intel", "Q67", enable_flash_pch6}, |
| 1729 | {0x8086, 0x1c4f, DEP, "Intel", "QM67", enable_flash_pch6}, |
| 1730 | {0x8086, 0x1c50, NT, "Intel", "B65", enable_flash_pch6}, |
| 1731 | {0x8086, 0x1c52, NT, "Intel", "C202", enable_flash_pch6}, |
| 1732 | {0x8086, 0x1c54, DEP, "Intel", "C204", enable_flash_pch6}, |
| 1733 | {0x8086, 0x1c56, NT, "Intel", "C206", enable_flash_pch6}, |
| 1734 | {0x8086, 0x1c5c, DEP, "Intel", "H61", enable_flash_pch6}, |
| 1735 | {0x8086, 0x1d40, DEP, "Intel", "C60x/X79", enable_flash_pch6}, |
| 1736 | {0x8086, 0x1d41, DEP, "Intel", "C60x/X79", enable_flash_pch6}, |
| 1737 | {0x8086, 0x1e44, DEP, "Intel", "Z77", enable_flash_pch7}, |
| 1738 | {0x8086, 0x1e46, NT, "Intel", "Z75", enable_flash_pch7}, |
| 1739 | {0x8086, 0x1e47, NT, "Intel", "Q77", enable_flash_pch7}, |
| 1740 | {0x8086, 0x1e48, NT, "Intel", "Q75", enable_flash_pch7}, |
| 1741 | {0x8086, 0x1e49, DEP, "Intel", "B75", enable_flash_pch7}, |
| 1742 | {0x8086, 0x1e4a, DEP, "Intel", "H77", enable_flash_pch7}, |
| 1743 | {0x8086, 0x1e53, NT, "Intel", "C216", enable_flash_pch7}, |
| 1744 | {0x8086, 0x1e55, DEP, "Intel", "QM77", enable_flash_pch7}, |
| 1745 | {0x8086, 0x1e56, NT, "Intel", "QS77", enable_flash_pch7}, |
| 1746 | {0x8086, 0x1e57, DEP, "Intel", "HM77", enable_flash_pch7}, |
| 1747 | {0x8086, 0x1e58, NT, "Intel", "UM77", enable_flash_pch7}, |
| 1748 | {0x8086, 0x1e59, NT, "Intel", "HM76", enable_flash_pch7}, |
| 1749 | {0x8086, 0x1e5d, NT, "Intel", "HM75", enable_flash_pch7}, |
| 1750 | {0x8086, 0x1e5e, NT, "Intel", "HM70", enable_flash_pch7}, |
| 1751 | {0x8086, 0x1e5f, DEP, "Intel", "NM70", enable_flash_pch7}, |
Stefan Tauner | 23e10b8 | 2016-01-23 16:16:49 +0000 | [diff] [blame] | 1752 | {0x8086, 0x1f38, DEP, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 1753 | {0x8086, 0x1f39, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, |
| 1754 | {0x8086, 0x1f3a, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, |
| 1755 | {0x8086, 0x1f3b, NT, "Intel", "Avoton/Rangeley", enable_flash_silvermont}, |
David Hendricks | a1bccd8 | 2017-08-08 23:28:54 -0700 | [diff] [blame] | 1756 | {0x8086, 0x229c, OK, "Intel", "Braswell", enable_flash_silvermont}, |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 1757 | {0x8086, 0x2310, NT, "Intel", "DH89xxCC (Cave Creek)", enable_flash_pch7}, |
Stefan Tauner | 428ba2b | 2014-06-02 00:34:58 +0000 | [diff] [blame] | 1758 | {0x8086, 0x2390, NT, "Intel", "Coleto Creek", enable_flash_pch7}, |
| 1759 | {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich0}, |
| 1760 | {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich0}, |
| 1761 | {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich2345}, |
| 1762 | {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich2345}, |
| 1763 | {0x8086, 0x2450, NT, "Intel", "C-ICH", enable_flash_ich2345}, |
| 1764 | {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich2345}, |
| 1765 | {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich2345}, |
| 1766 | {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich2345}, |
| 1767 | {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich2345}, |
| 1768 | {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich2345}, |
| 1769 | {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich2345}, |
| 1770 | {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich6}, |
| 1771 | {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich6}, |
| 1772 | {0x8086, 0x2642, NT, "Intel", "ICH6W/ICH6RW", enable_flash_ich6}, |
| 1773 | {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich6}, |
| 1774 | {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7}, |
| 1775 | {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7}, |
| 1776 | {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7}, |
| 1777 | {0x8086, 0x27bc, OK, "Intel", "NM10", enable_flash_ich7}, |
| 1778 | {0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7}, |
| 1779 | {0x8086, 0x2810, DEP, "Intel", "ICH8/ICH8R", enable_flash_ich8}, |
| 1780 | {0x8086, 0x2811, DEP, "Intel", "ICH8M-E", enable_flash_ich8}, |
| 1781 | {0x8086, 0x2812, DEP, "Intel", "ICH8DH", enable_flash_ich8}, |
| 1782 | {0x8086, 0x2814, DEP, "Intel", "ICH8DO", enable_flash_ich8}, |
| 1783 | {0x8086, 0x2815, DEP, "Intel", "ICH8M", enable_flash_ich8}, |
| 1784 | {0x8086, 0x2910, DEP, "Intel", "ICH9 Eng. Sample", enable_flash_ich9}, |
| 1785 | {0x8086, 0x2912, DEP, "Intel", "ICH9DH", enable_flash_ich9}, |
| 1786 | {0x8086, 0x2914, DEP, "Intel", "ICH9DO", enable_flash_ich9}, |
| 1787 | {0x8086, 0x2916, DEP, "Intel", "ICH9R", enable_flash_ich9}, |
| 1788 | {0x8086, 0x2917, DEP, "Intel", "ICH9M-E", enable_flash_ich9}, |
| 1789 | {0x8086, 0x2918, DEP, "Intel", "ICH9", enable_flash_ich9}, |
| 1790 | {0x8086, 0x2919, DEP, "Intel", "ICH9M", enable_flash_ich9}, |
| 1791 | {0x8086, 0x3a10, NT, "Intel", "ICH10R Eng. Sample", enable_flash_ich10}, |
| 1792 | {0x8086, 0x3a14, DEP, "Intel", "ICH10DO", enable_flash_ich10}, |
| 1793 | {0x8086, 0x3a16, DEP, "Intel", "ICH10R", enable_flash_ich10}, |
| 1794 | {0x8086, 0x3a18, DEP, "Intel", "ICH10", enable_flash_ich10}, |
| 1795 | {0x8086, 0x3a1a, DEP, "Intel", "ICH10D", enable_flash_ich10}, |
| 1796 | {0x8086, 0x3a1e, NT, "Intel", "ICH10 Eng. Sample", enable_flash_ich10}, |
| 1797 | {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_pch5}, |
| 1798 | {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_pch5}, |
| 1799 | {0x8086, 0x3b02, NT, "Intel", "P55", enable_flash_pch5}, |
| 1800 | {0x8086, 0x3b03, NT, "Intel", "PM55", enable_flash_pch5}, |
| 1801 | {0x8086, 0x3b06, DEP, "Intel", "H55", enable_flash_pch5}, |
| 1802 | {0x8086, 0x3b07, DEP, "Intel", "QM57", enable_flash_pch5}, |
| 1803 | {0x8086, 0x3b08, NT, "Intel", "H57", enable_flash_pch5}, |
| 1804 | {0x8086, 0x3b09, NT, "Intel", "HM55", enable_flash_pch5}, |
| 1805 | {0x8086, 0x3b0a, NT, "Intel", "Q57", enable_flash_pch5}, |
| 1806 | {0x8086, 0x3b0b, NT, "Intel", "HM57", enable_flash_pch5}, |
| 1807 | {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_pch5}, |
| 1808 | {0x8086, 0x3b0e, NT, "Intel", "B55", enable_flash_pch5}, |
| 1809 | {0x8086, 0x3b0f, DEP, "Intel", "QS57", enable_flash_pch5}, |
| 1810 | {0x8086, 0x3b12, NT, "Intel", "3400", enable_flash_pch5}, |
| 1811 | {0x8086, 0x3b14, DEP, "Intel", "3420", enable_flash_pch5}, |
| 1812 | {0x8086, 0x3b16, NT, "Intel", "3450", enable_flash_pch5}, |
| 1813 | {0x8086, 0x3b1e, NT, "Intel", "B55", enable_flash_pch5}, |
| 1814 | {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7}, |
| 1815 | {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4}, |
| 1816 | {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, |
| 1817 | {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4}, |
| 1818 | {0x8086, 0x8119, OK, "Intel", "SCH Poulsbo", enable_flash_poulsbo}, |
Duncan Laurie | 4095ed7 | 2014-08-20 15:39:32 +0000 | [diff] [blame] | 1819 | {0x8086, 0x8186, OK, "Intel", "Atom E6xx(T) (Tunnel Creek)", enable_flash_tunnelcreek}, |
Stefan Tauner | 428ba2b | 2014-06-02 00:34:58 +0000 | [diff] [blame] | 1820 | {0x8086, 0x8c40, NT, "Intel", "Lynx Point", enable_flash_pch8}, |
| 1821 | {0x8086, 0x8c41, NT, "Intel", "Lynx Point Mobile Eng. Sample", enable_flash_pch8}, |
| 1822 | {0x8086, 0x8c42, NT, "Intel", "Lynx Point Desktop Eng. Sample",enable_flash_pch8}, |
| 1823 | {0x8086, 0x8c43, NT, "Intel", "Lynx Point", enable_flash_pch8}, |
| 1824 | {0x8086, 0x8c44, DEP, "Intel", "Z87", enable_flash_pch8}, |
| 1825 | {0x8086, 0x8c45, NT, "Intel", "Lynx Point", enable_flash_pch8}, |
| 1826 | {0x8086, 0x8c46, NT, "Intel", "Z85", enable_flash_pch8}, |
| 1827 | {0x8086, 0x8c47, NT, "Intel", "Lynx Point", enable_flash_pch8}, |
| 1828 | {0x8086, 0x8c48, NT, "Intel", "Lynx Point", enable_flash_pch8}, |
| 1829 | {0x8086, 0x8c49, NT, "Intel", "HM86", enable_flash_pch8}, |
| 1830 | {0x8086, 0x8c4a, DEP, "Intel", "H87", enable_flash_pch8}, |
| 1831 | {0x8086, 0x8c4b, DEP, "Intel", "HM87", enable_flash_pch8}, |
| 1832 | {0x8086, 0x8c4c, NT, "Intel", "Q85", enable_flash_pch8}, |
| 1833 | {0x8086, 0x8c4d, NT, "Intel", "Lynx Point", enable_flash_pch8}, |
| 1834 | {0x8086, 0x8c4e, NT, "Intel", "Q87", enable_flash_pch8}, |
| 1835 | {0x8086, 0x8c4f, NT, "Intel", "QM87", enable_flash_pch8}, |
| 1836 | {0x8086, 0x8c50, DEP, "Intel", "B85", enable_flash_pch8}, |
| 1837 | {0x8086, 0x8c51, NT, "Intel", "Lynx Point", enable_flash_pch8}, |
| 1838 | {0x8086, 0x8c52, NT, "Intel", "C222", enable_flash_pch8}, |
| 1839 | {0x8086, 0x8c53, NT, "Intel", "Lynx Point", enable_flash_pch8}, |
| 1840 | {0x8086, 0x8c54, NT, "Intel", "C224", enable_flash_pch8}, |
| 1841 | {0x8086, 0x8c55, NT, "Intel", "Lynx Point", enable_flash_pch8}, |
| 1842 | {0x8086, 0x8c56, NT, "Intel", "C226", enable_flash_pch8}, |
| 1843 | {0x8086, 0x8c57, NT, "Intel", "Lynx Point", enable_flash_pch8}, |
| 1844 | {0x8086, 0x8c58, NT, "Intel", "Lynx Point", enable_flash_pch8}, |
| 1845 | {0x8086, 0x8c59, NT, "Intel", "Lynx Point", enable_flash_pch8}, |
| 1846 | {0x8086, 0x8c5a, NT, "Intel", "Lynx Point", enable_flash_pch8}, |
| 1847 | {0x8086, 0x8c5b, NT, "Intel", "Lynx Point", enable_flash_pch8}, |
| 1848 | {0x8086, 0x8c5c, NT, "Intel", "H81", enable_flash_pch8}, |
| 1849 | {0x8086, 0x8c5d, NT, "Intel", "Lynx Point", enable_flash_pch8}, |
| 1850 | {0x8086, 0x8c5e, NT, "Intel", "Lynx Point", enable_flash_pch8}, |
| 1851 | {0x8086, 0x8c5f, NT, "Intel", "Lynx Point", enable_flash_pch8}, |
Stefan Tauner | 5c316f9 | 2015-02-08 21:57:52 +0000 | [diff] [blame] | 1852 | {0x8086, 0x8cc1, NT, "Intel", "9 Series", enable_flash_pch9}, |
| 1853 | {0x8086, 0x8cc2, NT, "Intel", "9 Series Engineering Sample", enable_flash_pch9}, |
| 1854 | {0x8086, 0x8cc3, NT, "Intel", "9 Series", enable_flash_pch9}, |
| 1855 | {0x8086, 0x8cc4, NT, "Intel", "Z97", enable_flash_pch9}, |
| 1856 | {0x8086, 0x8cc6, NT, "Intel", "H97", enable_flash_pch9}, |
| 1857 | {0x8086, 0x8d40, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1858 | {0x8086, 0x8d41, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1859 | {0x8086, 0x8d42, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1860 | {0x8086, 0x8d43, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1861 | {0x8086, 0x8d44, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1862 | {0x8086, 0x8d45, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1863 | {0x8086, 0x8d46, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1864 | {0x8086, 0x8d47, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1865 | {0x8086, 0x8d48, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1866 | {0x8086, 0x8d49, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1867 | {0x8086, 0x8d4a, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1868 | {0x8086, 0x8d4b, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1869 | {0x8086, 0x8d4c, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1870 | {0x8086, 0x8d4d, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1871 | {0x8086, 0x8d4e, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1872 | {0x8086, 0x8d4f, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1873 | {0x8086, 0x8d50, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1874 | {0x8086, 0x8d51, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1875 | {0x8086, 0x8d52, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1876 | {0x8086, 0x8d53, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1877 | {0x8086, 0x8d54, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1878 | {0x8086, 0x8d55, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1879 | {0x8086, 0x8d56, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1880 | {0x8086, 0x8d57, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1881 | {0x8086, 0x8d58, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1882 | {0x8086, 0x8d59, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1883 | {0x8086, 0x8d5a, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1884 | {0x8086, 0x8d5b, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1885 | {0x8086, 0x8d5c, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1886 | {0x8086, 0x8d5d, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1887 | {0x8086, 0x8d5e, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
| 1888 | {0x8086, 0x8d5f, NT, "Intel", "C610/X99 (Wellsburg)", enable_flash_pch8_wb}, |
Stefan Tauner | 428ba2b | 2014-06-02 00:34:58 +0000 | [diff] [blame] | 1889 | {0x8086, 0x9c41, NT, "Intel", "Lynx Point LP Eng. Sample", enable_flash_pch8_lp}, |
| 1890 | {0x8086, 0x9c43, NT, "Intel", "Lynx Point LP Premium", enable_flash_pch8_lp}, |
| 1891 | {0x8086, 0x9c45, NT, "Intel", "Lynx Point LP Mainstream", enable_flash_pch8_lp}, |
| 1892 | {0x8086, 0x9c47, NT, "Intel", "Lynx Point LP Value", enable_flash_pch8_lp}, |
Nico Huber | 5120591 | 2017-03-17 17:59:54 +0100 | [diff] [blame] | 1893 | {0x8086, 0x9cc1, NT, "Intel", "Haswell U Sample", enable_flash_pch9_lp}, |
| 1894 | {0x8086, 0x9cc2, NT, "Intel", "Broadwell U Sample", enable_flash_pch9_lp}, |
| 1895 | {0x8086, 0x9cc3, NT, "Intel", "Broadwell U Premium", enable_flash_pch9_lp}, |
| 1896 | {0x8086, 0x9cc5, NT, "Intel", "Broadwell U Base", enable_flash_pch9_lp}, |
| 1897 | {0x8086, 0x9cc6, NT, "Intel", "Broadwell Y Sample", enable_flash_pch9_lp}, |
| 1898 | {0x8086, 0x9cc7, NT, "Intel", "Broadwell Y Premium", enable_flash_pch9_lp}, |
| 1899 | {0x8086, 0x9cc9, NT, "Intel", "Broadwell Y Base", enable_flash_pch9_lp}, |
Duncan Laurie | 823096e | 2014-08-20 15:39:38 +0000 | [diff] [blame] | 1900 | {0x8086, 0x9ccb, NT, "Intel", "Broadwell H", enable_flash_pch9}, |
Nico Huber | 5002634 | 2017-03-29 18:24:32 +0200 | [diff] [blame] | 1901 | {0x8086, 0x9d41, NT, "Intel", "Skylake / Kaby Lake Sample", enable_flash_pch100}, |
| 1902 | {0x8086, 0x9d43, NT, "Intel", "Skylake U Base", enable_flash_pch100}, |
| 1903 | {0x8086, 0x9d46, NT, "Intel", "Skylake Y Premium", enable_flash_pch100}, |
| 1904 | {0x8086, 0x9d48, NT, "Intel", "Skylake U Premium", enable_flash_pch100}, |
| 1905 | {0x8086, 0x9d4b, NT, "Intel", "Kaby Lake Y w/ iHDCP2.2 Prem.", enable_flash_pch100}, |
| 1906 | {0x8086, 0x9d4e, NT, "Intel", "Kaby Lake U w/ iHDCP2.2 Prem.", enable_flash_pch100}, |
| 1907 | {0x8086, 0x9d50, NT, "Intel", "Kaby Lake U w/ iHDCP2.2 Base", enable_flash_pch100}, |
| 1908 | {0x8086, 0x9d51, NT, "Intel", "Kabe Lake w/ iHDCP2.2 Sample", enable_flash_pch100}, |
| 1909 | {0x8086, 0x9d53, NT, "Intel", "Kaby Lake U Base", enable_flash_pch100}, |
| 1910 | {0x8086, 0x9d56, NT, "Intel", "Kaby Lake Y Premium", enable_flash_pch100}, |
| 1911 | {0x8086, 0x9d58, NT, "Intel", "Kaby Lake U Premium", enable_flash_pch100}, |
| 1912 | {0x8086, 0xa141, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100}, |
| 1913 | {0x8086, 0xa142, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100}, |
| 1914 | {0x8086, 0xa143, NT, "Intel", "H110", enable_flash_pch100}, |
| 1915 | {0x8086, 0xa144, NT, "Intel", "H170", enable_flash_pch100}, |
| 1916 | {0x8086, 0xa145, NT, "Intel", "Z170", enable_flash_pch100}, |
| 1917 | {0x8086, 0xa146, NT, "Intel", "Q170", enable_flash_pch100}, |
| 1918 | {0x8086, 0xa147, NT, "Intel", "Q150", enable_flash_pch100}, |
| 1919 | {0x8086, 0xa148, NT, "Intel", "B150", enable_flash_pch100}, |
| 1920 | {0x8086, 0xa149, NT, "Intel", "C236", enable_flash_pch100}, |
| 1921 | {0x8086, 0xa14a, NT, "Intel", "C232", enable_flash_pch100}, |
| 1922 | {0x8086, 0xa14b, NT, "Intel", "Sunrise Point Server Sample", enable_flash_pch100}, |
| 1923 | {0x8086, 0xa14d, NT, "Intel", "QM170", enable_flash_pch100}, |
| 1924 | {0x8086, 0xa14e, NT, "Intel", "HM170", enable_flash_pch100}, |
| 1925 | {0x8086, 0xa150, NT, "Intel", "CM236", enable_flash_pch100}, |
| 1926 | {0x8086, 0xa151, NT, "Intel", "QMS180", enable_flash_pch100}, |
| 1927 | {0x8086, 0xa152, NT, "Intel", "HM175", enable_flash_pch100}, |
| 1928 | {0x8086, 0xa153, NT, "Intel", "QM175", enable_flash_pch100}, |
| 1929 | {0x8086, 0xa154, NT, "Intel", "CM238", enable_flash_pch100}, |
| 1930 | {0x8086, 0xa155, NT, "Intel", "QMU185", enable_flash_pch100}, |
David Hendricks | a521636 | 2017-08-08 20:02:22 -0700 | [diff] [blame] | 1931 | {0x8086, 0xa1c1, NT, "Intel", "C621 Series Chipset (QS/PRQ)", enable_flash_c620}, |
| 1932 | {0x8086, 0xa1c2, NT, "Intel", "C622 Series Chipset (QS/PRQ)", enable_flash_c620}, |
| 1933 | {0x8086, 0xa1c3, NT, "Intel", "C624 Series Chipset (QS/PRQ)", enable_flash_c620}, |
| 1934 | {0x8086, 0xa1c4, NT, "Intel", "C625 Series Chipset (QS/PRQ)", enable_flash_c620}, |
| 1935 | {0x8086, 0xa1c5, NT, "Intel", "C626 Series Chipset (QS/PRQ)", enable_flash_c620}, |
| 1936 | {0x8086, 0xa1c6, NT, "Intel", "C627 Series Chipset (QS/PRQ)", enable_flash_c620}, |
| 1937 | {0x8086, 0xa1c7, NT, "Intel", "C628 Series Chipset (QS/PRQ)", enable_flash_c620}, |
| 1938 | {0x8086, 0xa242, NT, "Intel", "C624 Series Chipset Supersku", enable_flash_c620}, |
| 1939 | {0x8086, 0xa243, NT, "Intel", "C627 Series Chipset Supersku", enable_flash_c620}, |
| 1940 | {0x8086, 0xa244, NT, "Intel", "C621 Series Chipset Supersku", enable_flash_c620}, |
| 1941 | {0x8086, 0xa245, NT, "Intel", "C627 Series Chipset Supersku", enable_flash_c620}, |
| 1942 | {0x8086, 0xa246, NT, "Intel", "C628 Series Chipset Supersku", enable_flash_c620}, |
| 1943 | {0x8086, 0xa247, NT, "Intel", "C620 Series Chipset Supersku", enable_flash_c620}, |
Carl-Daniel Hailfinger | cceafa2 | 2010-05-26 01:45:41 +0000 | [diff] [blame] | 1944 | #endif |
Carl-Daniel Hailfinger | 1c6d2ff | 2012-08-27 00:44:42 +0000 | [diff] [blame] | 1945 | {0}, |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 1946 | }; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 1947 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1948 | int chipset_flash_enable(void) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 1949 | { |
Peter Huewe | 73f8ec8 | 2011-01-24 19:15:51 +0000 | [diff] [blame] | 1950 | struct pci_dev *dev = NULL; |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 1951 | int ret = -2; /* Nothing! */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1952 | int i; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 1953 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 1954 | /* Now let's try to find the chipset we have... */ |
Uwe Hermann | 05fab75 | 2009-05-16 23:42:17 +0000 | [diff] [blame] | 1955 | for (i = 0; chipset_enables[i].vendor_name != NULL; i++) { |
| 1956 | dev = pci_dev_find(chipset_enables[i].vendor_id, |
| 1957 | chipset_enables[i].device_id); |
Michael Karcher | 89bed6d | 2010-06-13 10:16:12 +0000 | [diff] [blame] | 1958 | if (!dev) |
| 1959 | continue; |
| 1960 | if (ret != -2) { |
Stefan Tauner | c6fa32d | 2013-01-04 22:54:07 +0000 | [diff] [blame] | 1961 | msg_pwarn("Warning: unexpected second chipset match: " |
Paul Menzel | ab6328f | 2010-10-08 11:03:02 +0000 | [diff] [blame] | 1962 | "\"%s %s\"\n" |
| 1963 | "ignoring, please report lspci and board URL " |
| 1964 | "to flashrom@flashrom.org\n" |
Stefan Reinauer | bf282b1 | 2011-03-29 21:41:41 +0000 | [diff] [blame] | 1965 | "with \'CHIPSET: your board name\' in the " |
Paul Menzel | ab6328f | 2010-10-08 11:03:02 +0000 | [diff] [blame] | 1966 | "subject line.\n", |
Michael Karcher | 89bed6d | 2010-06-13 10:16:12 +0000 | [diff] [blame] | 1967 | chipset_enables[i].vendor_name, |
| 1968 | chipset_enables[i].device_name); |
| 1969 | continue; |
| 1970 | } |
Stefan Tauner | ec8c248 | 2011-07-21 19:59:34 +0000 | [diff] [blame] | 1971 | msg_pinfo("Found chipset \"%s %s\"", |
| 1972 | chipset_enables[i].vendor_name, |
| 1973 | chipset_enables[i].device_name); |
Stefan Tauner | 716e098 | 2011-07-25 20:38:52 +0000 | [diff] [blame] | 1974 | msg_pdbg(" with PCI ID %04x:%04x", |
Carl-Daniel Hailfinger | f469c27 | 2010-05-22 07:31:50 +0000 | [diff] [blame] | 1975 | chipset_enables[i].vendor_id, |
| 1976 | chipset_enables[i].device_id); |
Stefan Tauner | 5c316f9 | 2015-02-08 21:57:52 +0000 | [diff] [blame] | 1977 | msg_pinfo(".\n"); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1978 | |
Stefan Tauner | 23e10b8 | 2016-01-23 16:16:49 +0000 | [diff] [blame] | 1979 | if (chipset_enables[i].status == BAD) { |
| 1980 | msg_perr("ERROR: This chipset is not supported yet.\n"); |
| 1981 | return ERROR_FATAL; |
| 1982 | } |
Stefan Tauner | ec8c248 | 2011-07-21 19:59:34 +0000 | [diff] [blame] | 1983 | if (chipset_enables[i].status == NT) { |
Stefan Tauner | 5c316f9 | 2015-02-08 21:57:52 +0000 | [diff] [blame] | 1984 | msg_pinfo("This chipset is marked as untested. If " |
Stefan Tauner | ec8c248 | 2011-07-21 19:59:34 +0000 | [diff] [blame] | 1985 | "you are using an up-to-date version\nof " |
Stefan Tauner | 2abab94 | 2012-04-27 20:41:23 +0000 | [diff] [blame] | 1986 | "flashrom *and* were (not) able to " |
| 1987 | "successfully update your firmware with it,\n" |
| 1988 | "then please email a report to " |
| 1989 | "flashrom@flashrom.org including a verbose " |
| 1990 | "(-V) log.\nThank you!\n"); |
Stefan Tauner | ec8c248 | 2011-07-21 19:59:34 +0000 | [diff] [blame] | 1991 | } |
| 1992 | msg_pinfo("Enabling flash write... "); |
Stefan Tauner | 23e10b8 | 2016-01-23 16:16:49 +0000 | [diff] [blame] | 1993 | ret = chipset_enables[i].doit(dev, chipset_enables[i].device_name); |
Michael Karcher | 89bed6d | 2010-06-13 10:16:12 +0000 | [diff] [blame] | 1994 | if (ret == NOT_DONE_YET) { |
| 1995 | ret = -2; |
| 1996 | msg_pinfo("OK - searching further chips.\n"); |
| 1997 | } else if (ret < 0) |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 1998 | msg_pinfo("FAILED!\n"); |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 1999 | else if (ret == 0) |
Sean Nelson | 316a29f | 2010-05-07 20:09:04 +0000 | [diff] [blame] | 2000 | msg_pinfo("OK.\n"); |
Uwe Hermann | 91f4afa | 2011-07-28 08:13:25 +0000 | [diff] [blame] | 2001 | else if (ret == ERROR_NONFATAL) |
Michael Karcher | a4448d9 | 2010-07-22 18:04:15 +0000 | [diff] [blame] | 2002 | msg_pinfo("PROBLEMS, continuing anyway\n"); |
Tadas Slotkus | ad47034 | 2011-09-03 17:15:00 +0000 | [diff] [blame] | 2003 | if (ret == ERROR_FATAL) { |
| 2004 | msg_perr("FATAL ERROR!\n"); |
| 2005 | return ret; |
| 2006 | } |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 2007 | } |
Michael Karcher | 89bed6d | 2010-06-13 10:16:12 +0000 | [diff] [blame] | 2008 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 2009 | return ret; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 2010 | } |