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Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +00006 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
Carl-Daniel Hailfinger92242622007-09-27 14:29:57 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000021 */
22
23/*
24 * Contains the board specific flash enables.
25 */
26
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000027#include <string.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000028#include "flash.h"
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000029
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000030#if defined(__i386__) || defined(__x86_64__)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000031/*
Uwe Hermannffec5f32007-08-23 16:08:21 +000032 * Helper functions for many Winbond Super I/Os of the W836xx range.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000033 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000034/* Enter extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000035void w836xx_ext_enter(uint16_t port)
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000036{
Andriy Gapon65c1b862008-05-22 13:22:45 +000037 OUTB(0x87, port);
38 OUTB(0x87, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000039}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000040
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000041/* Leave extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000042void w836xx_ext_leave(uint16_t port)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000043{
Andriy Gapon65c1b862008-05-22 13:22:45 +000044 OUTB(0xAA, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000045}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000046
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000047/* Generic Super I/O helper functions */
48uint8_t sio_read(uint16_t port, uint8_t reg)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000049{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000050 OUTB(reg, port);
51 return INB(port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000052}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000053
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000054void sio_write(uint16_t port, uint8_t reg, uint8_t data)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000055{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000056 OUTB(reg, port);
57 OUTB(data, port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000058}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000059
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000060void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000061{
Ronald G. Minnichfa496922007-10-12 21:22:40 +000062 uint8_t tmp;
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000063
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000064 OUTB(reg, port);
65 tmp = INB(port + 1) & ~mask;
66 OUTB(tmp | (data & mask), port + 1);
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000067}
68
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000069/* Not used yet. */
70#if 0
71static int enable_flash_decode_superio(void)
72{
73 int ret;
74 uint8_t tmp;
75
76 switch (superio.vendor) {
77 case SUPERIO_VENDOR_NONE:
78 ret = -1;
79 break;
80 case SUPERIO_VENDOR_ITE:
81 enter_conf_mode_ite(superio.port);
Uwe Hermann43959702010-03-13 17:28:29 +000082 /* Enable flash mapping. Works for most old ITE style Super I/O. */
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000083 tmp = sio_read(superio.port, 0x24);
84 tmp |= 0xfc;
85 sio_write(superio.port, 0x24, tmp);
86 exit_conf_mode_ite(superio.port);
87 ret = 0;
88 break;
89 default:
Sean Nelson316a29f2010-05-07 20:09:04 +000090 msg_pdbg("Unhandled Super I/O type!\n");
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000091 ret = -1;
92 break;
93 }
94 return ret;
95}
96#endif
97
Uwe Hermannffec5f32007-08-23 16:08:21 +000098/**
Michael Karcherb3fe2fc2010-05-24 16:03:57 +000099 * SMSC FDC37B787: Raise GPIO50
100 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000101static int fdc37b787_gpio50_raise(uint16_t port)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000102{
103 uint8_t id, val;
104
105 OUTB(0x55, port); /* enter conf mode */
106 id = sio_read(port, 0x20);
107 if (id != 0x44) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000108 msg_perr("\nERROR: FDC37B787: Wrong ID 0x%02X.\n", id);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000109 OUTB(0xAA, port); /* leave conf mode */
110 return -1;
111 }
112
113 sio_write(port, 0x07, 0x08); /* Select Aux I/O subdevice */
114
115 val = sio_read(port, 0xC8); /* GP50 */
116 if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */
117 {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000118 msg_perr("\nERROR: GPIO50 mode 0x%02X unexpected.\n", val);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000119 OUTB(0xAA, port);
120 return -1;
121 }
122
123 sio_mask(port, 0xF9, 0x01, 0x01);
124
125 OUTB(0xAA, port); /* Leave conf mode */
126 return 0;
127}
128
129/**
130 * Suited for Nokia IP530: Intel 440BX + PIIX4 + FDC37B787
131 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000132static int fdc37b787_gpio50_raise_3f0(void)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000133{
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000134 return fdc37b787_gpio50_raise(0x3f0);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000135}
136
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000137struct winbond_mux {
138 uint8_t reg; /* 0 if the corresponding pin is not muxed */
139 uint8_t data; /* reg/data/mask may be directly ... */
140 uint8_t mask; /* ... passed to sio_mask */
141};
142
143struct winbond_port {
144 const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */
145 uint8_t ldn; /* LDN this GPIO register is located in */
146 uint8_t enable_bit; /* bit in 0x30 of that LDN to enable
147 the GPIO port */
148 uint8_t base; /* base register in that LDN for the port */
149};
150
151struct winbond_chip {
152 uint8_t device_id; /* reg 0x20 of the expected w83626x */
153 uint8_t gpio_port_count;
154 const struct winbond_port *port;
155};
156
157
158#define UNIMPLEMENTED_PORT {NULL, 0, 0, 0}
159
160enum winbond_id {
161 WINBOND_W83627HF_ID = 0x52,
Michael Karcherea36c9c2010-06-27 15:07:52 +0000162 WINBOND_W83627EHF_ID = 0x88,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000163 WINBOND_W83627THF_ID = 0x82,
164};
165
166static const struct winbond_mux w83627hf_port2_mux[8] = {
167 {0x2A, 0x01, 0x01}, /* or MIDI */
168 {0x2B, 0x80, 0x80}, /* or SPI */
169 {0x2B, 0x40, 0x40}, /* or SPI */
170 {0x2B, 0x20, 0x20}, /* or power LED */
171 {0x2B, 0x10, 0x10}, /* or watchdog */
172 {0x2B, 0x08, 0x08}, /* or infra red */
173 {0x2B, 0x04, 0x04}, /* or infra red */
174 {0x2B, 0x03, 0x03} /* or IRQ1 input */
175};
176
177static const struct winbond_port w83627hf[3] = {
178 UNIMPLEMENTED_PORT,
179 {w83627hf_port2_mux, 0x08, 0, 0xF0},
180 UNIMPLEMENTED_PORT
181};
182
Michael Karcherea36c9c2010-06-27 15:07:52 +0000183static const struct winbond_mux w83627ehf_port2_mux[8] = {
184 {0x29, 0x06, 0x02}, /* or MIDI */
185 {0x29, 0x06, 0x02},
186 {0x24, 0x02, 0x00}, /* or SPI ROM interface */
187 {0x24, 0x02, 0x00},
188 {0x2A, 0x01, 0x01}, /* or keyboard/mouse interface */
189 {0x2A, 0x01, 0x01},
190 {0x2A, 0x01, 0x01},
191 {0x2A, 0x01, 0x01}
192};
193
194static const struct winbond_port w83627ehf[6] = {
195 UNIMPLEMENTED_PORT,
196 {w83627ehf_port2_mux, 0x09, 0, 0xE3},
197 UNIMPLEMENTED_PORT,
198 UNIMPLEMENTED_PORT,
199 UNIMPLEMENTED_PORT,
200 UNIMPLEMENTED_PORT
201};
202
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000203static const struct winbond_mux w83627thf_port4_mux[8] = {
204 {0x2D, 0x01, 0x01}, /* or watchdog or VID level strap */
205 {0x2D, 0x02, 0x02}, /* or resume reset */
206 {0x2D, 0x04, 0x04}, /* or S3 input */
207 {0x2D, 0x08, 0x08}, /* or PSON# */
208 {0x2D, 0x10, 0x10}, /* or PWROK */
209 {0x2D, 0x20, 0x20}, /* or suspend LED */
210 {0x2D, 0x40, 0x40}, /* or panel switch input */
211 {0x2D, 0x80, 0x80} /* or panel switch output */
212};
213
214static const struct winbond_port w83627thf[5] = {
215 UNIMPLEMENTED_PORT, /* GPIO1 */
216 UNIMPLEMENTED_PORT, /* GPIO2 */
217 UNIMPLEMENTED_PORT, /* GPIO3 */
218 {w83627thf_port4_mux, 0x09, 1, 0xF4},
219 UNIMPLEMENTED_PORT /* GPIO5 */
220};
221
222static const struct winbond_chip winbond_chips[] = {
223 {WINBOND_W83627HF_ID, ARRAY_SIZE(w83627hf), w83627hf },
Michael Karcherea36c9c2010-06-27 15:07:52 +0000224 {WINBOND_W83627EHF_ID, ARRAY_SIZE(w83627ehf), w83627ehf},
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000225 {WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf},
226};
227
228/* Detects which Winbond Super I/O is responding at the given base
229 address, but takes no effort to make sure the chip is really a
230 Winbond Super I/O */
231
232static const struct winbond_chip * winbond_superio_detect(uint16_t base)
233{
234 uint8_t chipid;
235 const struct winbond_chip * chip = NULL;
236 int i;
237
238 w836xx_ext_enter(base);
239 chipid = sio_read(base, 0x20);
240 for (i = 0; i < ARRAY_SIZE(winbond_chips); i++)
241 if (winbond_chips[i].device_id == chipid)
242 {
243 chip = &winbond_chips[i];
244 break;
245 }
246
247 w836xx_ext_leave(base);
248 return chip;
249}
250
251/* The chipid parameter goes away as soon as we have Super I/O matching in the
252 board enable table. The call to winbond_superio_detect goes away as
253 soon as we have generic Super I/O detection code. */
254static int winbond_gpio_set(uint16_t base, enum winbond_id chipid,
255 int pin, int raise)
256{
257 const struct winbond_chip * chip = NULL;
258 const struct winbond_port * gpio;
259 int port = pin / 10;
260 int bit = pin % 10;
261
262 chip = winbond_superio_detect(base);
263 if (!chip) {
264 msg_perr("\nERROR: No supported Winbond Super I/O found\n");
265 return -1;
266 }
Michael Karcher979d9252010-06-29 14:44:40 +0000267 if (chip->device_id != chipid) {
268 msg_perr("\nERROR: Found Winbond chip with ID 0x%x, "
269 "expected %x\n", chip->device_id, chipid);
270 return -1;
271 }
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000272 if (bit >= 8 || port == 0 || port > chip->gpio_port_count) {
273 msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n",
274 pin);
275 return -1;
276 }
277
278 gpio = &chip->port[port - 1];
279
280 if (gpio->ldn == 0) {
281 msg_perr("\nERROR: GPIO%d is not supported yet on this"
282 " winbond chip\n", port);
283 return -1;
284 }
285
286 w836xx_ext_enter(base);
287
288 /* Select logical device */
289 sio_write(base, 0x07, gpio->ldn);
290
291 /* Activate logical device. */
292 sio_mask(base, 0x30, 1 << gpio->enable_bit, 1 << gpio->enable_bit);
293
294 /* Select GPIO function of that pin */
295 if (gpio->mux && gpio->mux[bit].reg)
296 sio_mask(base, gpio->mux[bit].reg,
297 gpio->mux[bit].data, gpio->mux[bit].mask);
298
299 sio_mask(base, gpio->base + 0, 0, 1 << bit); /* make pin output */
300 sio_mask(base, gpio->base + 2, 0, 1 << bit); /* Clear inversion */
301 sio_mask(base, gpio->base + 1, raise << bit, 1 << bit);
302
303 w836xx_ext_leave(base);
304
305 return 0;
306}
307
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000308/**
Uwe Hermannffec5f32007-08-23 16:08:21 +0000309 * Winbond W83627HF: Raise GPIO24.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000310 *
311 * Suited for:
Uwe Hermannffec5f32007-08-23 16:08:21 +0000312 * - Agami Aruma
313 * - IWILL DK8-HTX
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000314 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000315static int w83627hf_gpio24_raise_2e()
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000316{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000317 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000318}
319
320/**
Michael Karcherea36c9c2010-06-27 15:07:52 +0000321 * Winbond W83627EHF: Raise GPIO24.
322 *
323 * Suited for:
Michael Karcher7af6cef2010-07-08 09:32:18 +0000324 * - Asus A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51.
Michael Karcherea36c9c2010-06-27 15:07:52 +0000325 */
326static int w83627ehf_gpio24_raise_2e()
327{
328 return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 24, 1);
329}
330
331/**
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000332 * Winbond W83627THF: Raise GPIO 44.
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000333 *
334 * Suited for:
Peter Stugecce26822008-07-21 17:48:40 +0000335 * - MSI K8T Neo2-F
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000336 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000337static int w83627thf_gpio44_raise_2e()
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000338{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000339 return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000340}
341
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000342/**
343 * Winbond W83627THF: Raise GPIO 44.
344 *
345 * Suited for:
346 * - MSI K8N Neo3
347 */
348static int w83627thf_gpio44_raise_4e()
Peter Stugecce26822008-07-21 17:48:40 +0000349{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000350 return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000351}
Uwe Hermann372eeb52007-12-04 21:49:06 +0000352
Uwe Hermannffec5f32007-08-23 16:08:21 +0000353/**
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000354 * w83627: Enable MEMW# and set ROM size to max.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000355 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000356static void w836xx_memw_enable(uint16_t port)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000357{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000358 w836xx_ext_enter(port);
359 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000360 /* Enable MEMW# and set ROM size select to max. (4M). */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000361 sio_mask(port, 0x24, 0x28, 0x28);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000362 }
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000363 w836xx_ext_leave(port);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000364}
365
366/**
Luc Verhaegen73d21192009-12-23 00:54:26 +0000367 * Suited for:
368 * - EPoX EP-8K5A2: VIA KT333 + VT8235.
369 * - Albatron PM266A Pro: VIA P4M266A + VT8235.
370 * - Shuttle AK31 (all versions): VIA KT266 + VT8233.
371 * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
372 * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000373 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000374static int w836xx_memw_enable_2e(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000375{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000376 w836xx_memw_enable(0x2E);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000377
Luc Verhaegen73d21192009-12-23 00:54:26 +0000378 return 0;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000379}
380
Luc Verhaegen21f54962010-01-20 14:45:07 +0000381/**
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000382 * Suited for:
383 * - Termtek TK-3370 (rev. 2.5b)
384 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000385static int w836xx_memw_enable_4e(void)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000386{
387 w836xx_memw_enable(0x4E);
388
389 return 0;
390}
391
392/**
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000393 * Suited for all boards with ITE IT8705F.
394 * The SIS950 Super I/O probably requires a similar flash write enable.
Luc Verhaegen21f54962010-01-20 14:45:07 +0000395 */
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000396int it8705f_write_enable(uint8_t port)
Luc Verhaegen21f54962010-01-20 14:45:07 +0000397{
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000398 uint8_t tmp;
399 int ret = 0;
400
Luc Verhaegen21f54962010-01-20 14:45:07 +0000401 enter_conf_mode_ite(port);
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000402 tmp = sio_read(port, 0x24);
403 /* Check if at least one flash segment is enabled. */
404 if (tmp & 0xf0) {
405 /* The IT8705F will respond to LPC cycles and translate them. */
406 buses_supported = CHIP_BUSTYPE_PARALLEL;
407 /* Flash ROM I/F Writes Enable */
408 tmp |= 0x04;
409 msg_pdbg("Enabling IT8705F flash ROM interface write.\n");
410 if (tmp & 0x02) {
411 /* The data sheet contradicts itself about max size. */
412 max_rom_decode.parallel = 1024 * 1024;
413 msg_pinfo("IT8705F with very unusual settings. Please "
414 "send the output of \"flashrom -V\" to \n"
415 "flashrom@flashrom.org to help us finish "
416 "support for your Super I/O. Thanks.\n");
417 ret = 1;
418 } else if (tmp & 0x08) {
419 max_rom_decode.parallel = 512 * 1024;
420 } else {
421 max_rom_decode.parallel = 256 * 1024;
422 }
423 /* Safety checks. The data sheet is unclear here: Segments 1+3
424 * overlap, no segment seems to cover top - 1MB to top - 512kB.
425 * We assume that certain combinations make no sense.
426 */
427 if (((tmp & 0x02) && !(tmp & 0x08)) || /* 1 MB en, 512 kB dis */
428 (!(tmp & 0x10)) || /* 128 kB dis */
429 (!(tmp & 0x40))) { /* 256/512 kB dis */
430 msg_perr("Inconsistent IT8705F decode size!\n");
431 ret = 1;
432 }
433 if (sio_read(port, 0x25) != 0) {
434 msg_perr("IT8705F flash data pins disabled!\n");
435 ret = 1;
436 }
437 if (sio_read(port, 0x26) != 0) {
438 msg_perr("IT8705F flash address pins 0-7 disabled!\n");
439 ret = 1;
440 }
441 if (sio_read(port, 0x27) != 0) {
442 msg_perr("IT8705F flash address pins 8-15 disabled!\n");
443 ret = 1;
444 }
445 if ((sio_read(port, 0x29) & 0x10) != 0) {
446 msg_perr("IT8705F flash write enable pin disabled!\n");
447 ret = 1;
448 }
449 if ((sio_read(port, 0x29) & 0x08) != 0) {
450 msg_perr("IT8705F flash chip select pin disabled!\n");
451 ret = 1;
452 }
453 if ((sio_read(port, 0x29) & 0x04) != 0) {
454 msg_perr("IT8705F flash read strobe pin disabled!\n");
455 ret = 1;
456 }
457 if ((sio_read(port, 0x29) & 0x03) != 0) {
458 msg_perr("IT8705F flash address pins 16-17 disabled!\n");
459 /* Not really an error if you use flash chips smaller
460 * than 256 kByte, but such a configuration is unlikely.
461 */
462 ret = 1;
463 }
464 msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n",
465 max_rom_decode.parallel);
466 if (ret) {
467 msg_pinfo("Not enabling IT8705F flash write.\n");
468 } else {
469 sio_write(port, 0x24, tmp);
470 }
471 } else {
472 msg_pdbg("No IT8705F flash segment enabled.\n");
473 /* Not sure if this is an error or not. */
474 ret = 0;
475 }
Luc Verhaegen21f54962010-01-20 14:45:07 +0000476 exit_conf_mode_ite(port);
477
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000478 return ret;
Luc Verhaegen21f54962010-01-20 14:45:07 +0000479}
Luc Verhaegen73d21192009-12-23 00:54:26 +0000480
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000481static int pc87360_gpio_set(uint8_t gpio, int raise)
482{
483 static const int bankbase[] = {0, 4, 8, 10, 12};
484 int gpio_bank = gpio / 8;
485 int gpio_pin = gpio % 8;
486 uint16_t baseport;
Uwe Hermann43959702010-03-13 17:28:29 +0000487 uint8_t id, val;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000488
Uwe Hermann43959702010-03-13 17:28:29 +0000489 if (gpio_bank > 4) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000490 msg_perr("PC87360: Invalid GPIO %d\n", gpio);
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000491 return -1;
492 }
493
494 id = sio_read(0x2E, 0x20);
Uwe Hermann43959702010-03-13 17:28:29 +0000495 if (id != 0xE1) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000496 msg_perr("PC87360: unexpected ID %02x\n", id);
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000497 return -1;
498 }
499
Uwe Hermann43959702010-03-13 17:28:29 +0000500 sio_write(0x2E, 0x07, 0x07); /* Select GPIO device */
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000501 baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
Uwe Hermann43959702010-03-13 17:28:29 +0000502 if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000503 msg_perr("PC87360: invalid GPIO base address %04x\n",
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000504 baseport);
505 return -1;
506 }
507 sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device */
Uwe Hermann43959702010-03-13 17:28:29 +0000508 sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin);
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000509 sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output */
510
511 val = INB(baseport + bankbase[gpio_bank]);
Uwe Hermann43959702010-03-13 17:28:29 +0000512 if (raise)
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000513 val |= 1 << gpio_pin;
514 else
515 val &= ~(1 << gpio_pin);
516 OUTB(val, baseport + bankbase[gpio_bank]);
517
518 return 0;
519}
520
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000521/**
522 * VT823x: Set one of the GPIO pins.
523 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000524static int via_vt823x_gpio_set(uint8_t gpio, int raise)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000525{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000526 struct pci_dev *dev;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000527 uint16_t base;
David Bartleyf58d3642009-12-09 07:53:01 +0000528 uint8_t val, bit, offset;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000529
Luc Verhaegen73d21192009-12-23 00:54:26 +0000530 dev = pci_dev_find_vendorclass(0x1106, 0x0601);
531 switch (dev->device_id) {
532 case 0x3177: /* VT8235 */
533 case 0x3227: /* VT8237R */
534 case 0x3337: /* VT8237A */
535 break;
536 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000537 msg_perr("\nERROR: VT823x ISA bridge not found.\n");
Luc Verhaegen73d21192009-12-23 00:54:26 +0000538 return -1;
539 }
540
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000541 if ((gpio >= 12) && (gpio <= 15)) {
542 /* GPIO12-15 -> output */
543 val = pci_read_byte(dev, 0xE4);
544 val |= 0x10;
545 pci_write_byte(dev, 0xE4, val);
546 } else if (gpio == 9) {
547 /* GPIO9 -> Output */
548 val = pci_read_byte(dev, 0xE4);
549 val |= 0x20;
550 pci_write_byte(dev, 0xE4, val);
David Bartleyf58d3642009-12-09 07:53:01 +0000551 } else if (gpio == 5) {
552 val = pci_read_byte(dev, 0xE4);
553 val |= 0x01;
554 pci_write_byte(dev, 0xE4, val);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000555 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000556 msg_perr("\nERROR: "
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000557 "VT823x GPIO%02d is not implemented.\n", gpio);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000558 return -1;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000559 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000560
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000561 /* We need the I/O Base Address for this board's flash enable. */
562 base = pci_read_word(dev, 0x88) & 0xff80;
563
David Bartleyf58d3642009-12-09 07:53:01 +0000564 offset = 0x4C + gpio / 8;
565 bit = 0x01 << (gpio % 8);
566
567 val = INB(base + offset);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000568 if (raise)
569 val |= bit;
570 else
571 val &= ~bit;
David Bartleyf58d3642009-12-09 07:53:01 +0000572 OUTB(val, base + offset);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000573
Uwe Hermanna7e05482007-05-09 10:17:44 +0000574 return 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000575}
576
Uwe Hermannffec5f32007-08-23 16:08:21 +0000577/**
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000578 * Suited for ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000579 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000580static int via_vt823x_gpio5_raise(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000581{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000582 /* On M2V-MX: GPO5 is connected to WP# and TBL#. */
583 return via_vt823x_gpio_set(5, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000584}
585
586/**
Michael Karcherbcd25562010-06-12 17:27:44 +0000587 * Suited for VIA EPIA EK & N & NL.
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000588 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000589static int via_vt823x_gpio9_raise(void)
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000590{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000591 return via_vt823x_gpio_set(9, 1);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000592}
593
594/**
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000595 * Suited for VIA EPIA M and MII, and maybe other CLE266 based EPIAs.
Luc Verhaegen73d21192009-12-23 00:54:26 +0000596 *
597 * We don't need to do this for EPIA M when using coreboot, GPIO15 is never
598 * lowered there.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000599 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000600static int via_vt823x_gpio15_raise(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000601{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000602 return via_vt823x_gpio_set(15, 1);
603}
604
605/**
606 * Winbond W83697HF Super I/O + VIA VT8235 southbridge
607 *
608 * Suited for:
609 * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
610 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
611 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000612static int board_msi_kt4v(void)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000613{
614 int ret;
615
616 ret = via_vt823x_gpio_set(12, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000617 w836xx_memw_enable(0x2E);
Luc Verhaegen97866082008-02-09 02:03:06 +0000618
Luc Verhaegen73d21192009-12-23 00:54:26 +0000619 return ret;
Luc Verhaegen97866082008-02-09 02:03:06 +0000620}
621
622/**
Luc Verhaegen6b141752007-05-20 16:16:13 +0000623 * Suited for ASUS P5A.
624 *
625 * This is rather nasty code, but there's no way to do this cleanly.
626 * We're basically talking to some unknown device on SMBus, my guess
627 * is that it is the Winbond W83781D that lives near the DIP BIOS.
628 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000629static int board_asus_p5a(void)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000630{
631 uint8_t tmp;
632 int i;
633
634#define ASUSP5A_LOOP 5000
635
Andriy Gapon65c1b862008-05-22 13:22:45 +0000636 OUTB(0x00, 0xE807);
637 OUTB(0xEF, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000638
Andriy Gapon65c1b862008-05-22 13:22:45 +0000639 OUTB(0xFF, 0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000640
641 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000642 OUTB(0xE1, 0xFF);
643 if (INB(0xE800) & 0x04)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000644 break;
645 }
646
647 if (i == ASUSP5A_LOOP) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000648 msg_perr("Unable to contact device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000649 return -1;
650 }
651
Andriy Gapon65c1b862008-05-22 13:22:45 +0000652 OUTB(0x20, 0xE801);
653 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000654
Andriy Gapon65c1b862008-05-22 13:22:45 +0000655 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000656
657 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000658 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000659 if (tmp & 0x70)
660 break;
661 }
662
663 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000664 msg_perr("Failed to read device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000665 return -1;
666 }
667
Andriy Gapon65c1b862008-05-22 13:22:45 +0000668 tmp = INB(0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000669 tmp &= ~0x02;
670
Andriy Gapon65c1b862008-05-22 13:22:45 +0000671 OUTB(0x00, 0xE807);
672 OUTB(0xEE, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000673
Andriy Gapon65c1b862008-05-22 13:22:45 +0000674 OUTB(tmp, 0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000675
Andriy Gapon65c1b862008-05-22 13:22:45 +0000676 OUTB(0xFF, 0xE800);
677 OUTB(0xE1, 0xFF);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000678
Andriy Gapon65c1b862008-05-22 13:22:45 +0000679 OUTB(0x20, 0xE801);
680 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000681
Andriy Gapon65c1b862008-05-22 13:22:45 +0000682 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000683
684 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000685 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000686 if (tmp & 0x70)
687 break;
688 }
689
690 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000691 msg_perr("Failed to write to device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000692 return -1;
693 }
694
695 return 0;
696}
697
Luc Verhaegena7e30502009-12-09 11:39:02 +0000698/*
699 * Set GPIO lines in the Broadcom HT-1000 southbridge.
700 *
701 * It's not a Super I/O but it uses the same index/data port method.
702 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000703static int board_hp_dl145_g3_enable(void)
Luc Verhaegena7e30502009-12-09 11:39:02 +0000704{
705 /* GPIO 0 reg from PM regs */
706 /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
707 sio_mask(0xcd6, 0x44, 0x24, 0x24);
708
709 return 0;
710}
711
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +0000712/*
713 * Set GPIO lines in the Broadcom HT-1000 southbridge.
714 *
715 * It's not a Super I/O but it uses the same index/data port method.
716 */
717static int board_hp_dl165_g6_enable(void)
718{
719 /* Variant of DL145, with slightly different pin placement. */
720 sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */
721 sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */
722
723 return 0;
724}
725
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000726static int board_ibm_x3455(void)
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000727{
Luc Verhaegena7e30502009-12-09 11:39:02 +0000728 /* raise gpio13 */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +0000729 sio_mask(0xcd6, 0x45, 0x20, 0x20);
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000730
731 return 0;
732}
733
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000734/**
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000735 * Suited for Shuttle FN25 (SN25P): AMD S939 + NVIDIA CK804 (nForce4).
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000736 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000737static int board_shuttle_fn25(void)
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000738{
739 struct pci_dev *dev;
740
741 dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA Bridge. */
742 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000743 msg_perr("\nERROR: NVIDIA nForce4 ISA bridge not found.\n");
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000744 return -1;
745 }
746
747 /* one of those bits seems to be connected to TBL#, but -ENOINFO. */
748 pci_write_byte(dev, 0x92, 0);
749
750 return 0;
751}
752
753/**
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000754 * Very similar to AMD 8111 IO Hub.
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000755 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000756static int nvidia_mcp_gpio_set(int gpio, int raise)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000757{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000758 struct pci_dev *dev;
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000759 uint16_t base;
Michael Karcher2ead2e22010-06-01 16:09:06 +0000760 uint16_t devclass;
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000761 uint8_t tmp;
762
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000763 if ((gpio < 0) || (gpio >= 0x40)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000764 msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000765 return -1;
766 }
767
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000768 /* First, check the ISA Bridge */
769 dev = pci_dev_find_vendorclass(0x10DE, 0x0601);
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000770 switch (dev->device_id) {
771 case 0x0030: /* CK804 */
772 case 0x0050: /* MCP04 */
773 case 0x0060: /* MCP2 */
Michael Karcher5f31ebe2010-06-12 23:07:26 +0000774 case 0x00E0: /* CK8 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000775 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +0000776 case 0x0260: /* MCP51 */
777 case 0x0364: /* MCP55 */
778 /* find SMBus controller on *this* southbridge */
779 /* The infamous Tyan S2915-E has two south bridges; they are
780 easily told apart from each other by the class of the
781 LPC bridge, but have the same SMBus bridge IDs */
782 if (dev->func != 0) {
783 msg_perr("MCP LPC bridge at unexpected function"
784 " number %d\n", dev->func);
785 return -1;
786 }
787
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +0000788#if PCI_LIB_VERSION >= 0x020200
Michael Karcher2ead2e22010-06-01 16:09:06 +0000789 dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1);
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +0000790#else
791 /* pciutils/libpci before version 2.2 is too old to support
792 * PCI domains. Such old machines usually don't have domains
793 * besides domain 0, so this is not a problem.
794 */
795 dev = pci_get_dev(pacc, dev->bus, dev->dev, 1);
796#endif
Michael Karcher2ead2e22010-06-01 16:09:06 +0000797 if (!dev) {
798 msg_perr("MCP SMBus controller could not be found\n");
799 return -1;
800 }
801 devclass = pci_read_word(dev, PCI_CLASS_DEVICE);
802 if (devclass != 0x0C05) {
803 msg_perr("Unexpected device class %04x for SMBus"
804 " controller\n", devclass);
805 return -1;
806 }
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000807 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +0000808 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000809 msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n");
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000810 return -1;
811 }
812
813 base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
814 base += 0xC0;
815
816 tmp = INB(base + gpio);
817 tmp &= ~0x0F; /* null lower nibble */
818 tmp |= 0x04; /* gpio -> output. */
819 if (raise)
820 tmp |= 0x01;
821 OUTB(tmp, base + gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000822
823 return 0;
824}
825
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000826/**
Sean Nelson392e05a2010-03-19 22:58:15 +0000827 * Suited for ASUS A8N-LA: nVidia MCP51.
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000828 * Suited for ASUS M2NBP-VM CSM: NVIDIA MCP51.
Michael Karcherb2184c12010-03-07 16:42:55 +0000829 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000830static int nvidia_mcp_gpio0_raise(void)
Michael Karcherb2184c12010-03-07 16:42:55 +0000831{
832 return nvidia_mcp_gpio_set(0x00, 1);
833}
834
835/**
Sean Nelson92bc6bd2010-03-19 22:37:29 +0000836 * Suited for Abit KN8 Ultra: nVidia CK804.
837 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000838static int nvidia_mcp_gpio2_lower(void)
Sean Nelson92bc6bd2010-03-19 22:37:29 +0000839{
840 return nvidia_mcp_gpio_set(0x02, 0);
841}
842
843/**
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000844 * Suited for MSI K8N Neo4: NVIDIA CK804.
845 * Suited for MSI K8N GM2-L: NVIDIA MCP51.
Luc Verhaegen6c5f7332009-12-23 03:01:36 +0000846 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000847static int nvidia_mcp_gpio2_raise(void)
Luc Verhaegen6c5f7332009-12-23 03:01:36 +0000848{
849 return nvidia_mcp_gpio_set(0x02, 1);
850}
851
Michael Karcher2ead2e22010-06-01 16:09:06 +0000852
853/**
854 * Suited for HP xw9400 (Tyan S2915-E OEM): Dual(!) nVidia MCP55.
855 * Notes: a) There are two MCP55 chips, so also two SMBus bridges on that
856 * board. We can't tell the SMBus logical devices apart, but we
857 * can tell the LPC bridge functions apart.
858 * We need to choose the SMBus bridge next to the LPC bridge with
859 * ID 0x364 and the "LPC bridge" class.
860 * b) #TBL is hardwired on that board to a pull-down. It can be
861 * overridden by connecting the two solder points next to F2.
862 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000863static int nvidia_mcp_gpio5_raise(void)
Michael Karcher2ead2e22010-06-01 16:09:06 +0000864{
865 return nvidia_mcp_gpio_set(0x05, 1);
866}
867
Luc Verhaegen6c5f7332009-12-23 03:01:36 +0000868/**
Michael Karcher8f10d242010-04-11 21:01:06 +0000869 * Suited for Abit NF7-S: NVIDIA CK804.
870 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000871static int nvidia_mcp_gpio8_raise(void)
Michael Karcher8f10d242010-04-11 21:01:06 +0000872{
873 return nvidia_mcp_gpio_set(0x08, 1);
874}
875
876/**
Michael Karcher5f31ebe2010-06-12 23:07:26 +0000877 * Suited for MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + CK8.
878 */
Michael Karcher51825082010-06-12 23:14:03 +0000879static int nvidia_mcp_gpio0c_raise(void)
Michael Karcher5f31ebe2010-06-12 23:07:26 +0000880{
881 return nvidia_mcp_gpio_set(0x0c, 1);
882}
883
884/**
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000885 * Suited for ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04.
886 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000887static int nvidia_mcp_gpio10_raise(void)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000888{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000889 return nvidia_mcp_gpio_set(0x10, 1);
890}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000891
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000892/**
893 * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge.
894 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000895static int nvidia_mcp_gpio21_raise(void)
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000896{
897 return nvidia_mcp_gpio_set(0x21, 0x01);
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000898}
899
Luc Verhaegen2c04fab2009-10-05 18:46:35 +0000900/**
901 * Suited for EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2.
902 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000903static int nvidia_mcp_gpio31_raise(void)
Luc Verhaegen2c04fab2009-10-05 18:46:35 +0000904{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000905 return nvidia_mcp_gpio_set(0x31, 0x01);
Luc Verhaegen2c04fab2009-10-05 18:46:35 +0000906}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000907
Luc Verhaegenfdd0c582007-08-11 16:59:11 +0000908/**
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000909 * Suited for Artec Group DBE61 and DBE62.
910 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000911static int board_artecgroup_dbe6x(void)
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000912{
913#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
914#define DBE6x_PRI_BOOT_LOC_SHIFT (2)
915#define DBE6x_BOOT_OP_LATCHED_SHIFT (8)
916#define DBE6x_SEC_BOOT_LOC_SHIFT (10)
917#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
918#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
919#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
920#define DBE6x_BOOT_LOC_FLASH (2)
921#define DBE6x_BOOT_LOC_FWHUB (3)
922
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000923 msr_t msr;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000924 unsigned long boot_loc;
925
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000926 /* Geode only has a single core */
927 if (setup_cpu_msr(0))
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000928 return -1;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000929
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000930 msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000931
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000932 if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) ==
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000933 (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
934 boot_loc = DBE6x_BOOT_LOC_FWHUB;
935 else
936 boot_loc = DBE6x_BOOT_LOC_FLASH;
937
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000938 msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
939 msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
Uwe Hermann394131e2008-10-18 21:14:13 +0000940 (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000941
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000942 wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000943
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000944 cleanup_cpu_msr();
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000945
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000946 return 0;
947}
948
Uwe Hermann93f66db2008-05-22 21:19:38 +0000949/**
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000950 * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}.
Luc Verhaegenf5226912009-12-14 10:41:58 +0000951 */
952static int intel_piix4_gpo_set(unsigned int gpo, int raise)
953{
Michael Karcher01f6d7d2010-02-24 00:00:21 +0000954 unsigned int gpo_byte, gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +0000955 struct pci_dev *dev;
956 uint32_t tmp, base;
957
958 dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */
959 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000960 msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +0000961 return -1;
962 }
963
964 /* sanity check */
965 if (gpo > 30) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000966 msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);
Luc Verhaegenf5226912009-12-14 10:41:58 +0000967 return -1;
968 }
969
970 /* these are dual function pins which are most likely in use already */
971 if (((gpo >= 1) && (gpo <= 7)) ||
972 ((gpo >= 9) && (gpo <= 21)) || (gpo == 29)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000973 msg_perr("\nERROR: Unsupported PIIX4 GPO%d.\n", gpo);
Luc Verhaegenf5226912009-12-14 10:41:58 +0000974 return -1;
975 }
976
977 /* dual function that need special enable. */
978 if ((gpo >= 22) && (gpo <= 26)) {
979 tmp = pci_read_long(dev, 0xB0); /* GENCFG */
980 switch (gpo) {
981 case 22: /* XBUS: XDIR#/GPO22 */
982 case 23: /* XBUS: XOE#/GPO23 */
983 tmp |= 1 << 28;
984 break;
985 case 24: /* RTCSS#/GPO24 */
986 tmp |= 1 << 29;
987 break;
988 case 25: /* RTCALE/GPO25 */
989 tmp |= 1 << 30;
990 break;
991 case 26: /* KBCSS#/GPO26 */
992 tmp |= 1 << 31;
993 break;
994 }
995 pci_write_long(dev, 0xB0, tmp);
996 }
997
998 /* GPO {0,8,27,28,30} are always available. */
999
1000 dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */
1001 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001002 msg_perr("\nERROR: Intel PIIX4 PM not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001003 return -1;
1004 }
1005
1006 /* PM IO base */
1007 base = pci_read_long(dev, 0x40) & 0x0000FFC0;
1008
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001009 gpo_byte = gpo >> 3;
1010 gpo_bit = gpo & 7;
1011 tmp = INB(base + 0x34 + gpo_byte); /* GPO register */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001012 if (raise)
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001013 tmp |= 0x01 << gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001014 else
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001015 tmp &= ~(0x01 << gpo_bit);
1016 OUTB(tmp, base + 0x34 + gpo_byte);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001017
1018 return 0;
1019}
1020
1021/**
1022 * Suited for EPoX EP-BX3, and maybe some other Intel 440BX based boards.
1023 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001024static int board_epox_ep_bx3(void)
Luc Verhaegenf5226912009-12-14 10:41:58 +00001025{
1026 return intel_piix4_gpo_set(22, 1);
1027}
1028
1029/**
Michael Karcher51cd0c92010-03-19 22:35:21 +00001030 * Suited for Intel SE440BX-2
1031 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001032static int intel_piix4_gpo27_lower(void)
Michael Karcher51cd0c92010-03-19 22:35:21 +00001033{
1034 return intel_piix4_gpo_set(27, 0);
1035}
1036
1037/**
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001038 * Set a GPIO line on a given Intel ICH LPC controller.
Uwe Hermann93f66db2008-05-22 21:19:38 +00001039 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001040static int intel_ich_gpio_set(int gpio, int raise)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001041{
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001042 /* Table mapping the different Intel ICH LPC chipsets. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001043 static struct {
1044 uint16_t id;
1045 uint8_t base_reg;
1046 uint32_t bank0;
1047 uint32_t bank1;
1048 uint32_t bank2;
1049 } intel_ich_gpio_table[] = {
1050 {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */
1051 {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */
1052 {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */
1053 {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */
1054 {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */
1055 {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */
1056 {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */
1057 {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */
1058 {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */
1059 {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */
1060 {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */
1061 {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */
1062 {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */
1063 {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */
1064 {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */
1065 {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */
1066 {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */
1067 {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */
1068 {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */
1069 {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */
1070 {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */
1071 {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */
1072 {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */
1073 {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */
1074 {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */
1075 {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */
1076 {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */
1077 {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */
1078 {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */
1079 {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */
1080 {0, 0, 0, 0, 0} /* end marker */
1081 };
Uwe Hermann93f66db2008-05-22 21:19:38 +00001082
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001083 struct pci_dev *dev;
1084 uint16_t base;
1085 uint32_t tmp;
1086 int i, allowed;
1087
1088 /* First, look for a known LPC bridge */
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001089 for (dev = pacc->devices; dev; dev = dev->next) {
Carl-Daniel Hailfingerd175e062010-05-21 23:00:56 +00001090 uint16_t device_class;
1091 /* libpci before version 2.2.4 does not store class info. */
1092 device_class = pci_read_word(dev, PCI_CLASS_DEVICE);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001093 if ((dev->vendor_id == 0x8086) &&
Carl-Daniel Hailfingerd175e062010-05-21 23:00:56 +00001094 (device_class == 0x0601)) { /* ISA Bridge */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001095 /* Is this device in our list? */
1096 for (i = 0; intel_ich_gpio_table[i].id; i++)
1097 if (dev->device_id == intel_ich_gpio_table[i].id)
1098 break;
1099
1100 if (intel_ich_gpio_table[i].id)
1101 break;
1102 }
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001103 }
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001104
Uwe Hermann93f66db2008-05-22 21:19:38 +00001105 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001106 msg_perr("\nERROR: No Known Intel LPC Bridge found.\n");
Uwe Hermann93f66db2008-05-22 21:19:38 +00001107 return -1;
1108 }
1109
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001110 /* According to the datasheets, all Intel ICHs have the GPIO bar 5:1
1111 strapped to zero. From some mobile ICH9 version on, this becomes
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001112 6:1. The mask below catches all. */
1113 base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
Uwe Hermann93f66db2008-05-22 21:19:38 +00001114
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001115 /* check whether the line is allowed */
1116 if (gpio < 32)
1117 allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01;
1118 else if (gpio < 64)
1119 allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01;
1120 else
1121 allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;
1122
1123 if (!allowed) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001124 msg_perr("\nERROR: This Intel LPC Bridge does not allow"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001125 " setting GPIO%02d\n", gpio);
1126 return -1;
1127 }
1128
Sean Nelson316a29f2010-05-07 20:09:04 +00001129 msg_pdbg("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n",
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001130 raise ? "Rais" : "Dropp", gpio);
1131
1132 if (gpio < 32) {
1133 /* Set line to GPIO */
1134 tmp = INL(base);
1135 /* ICH/ICH0 multiplexes 27/28 on the line set. */
1136 if ((gpio == 28) &&
1137 ((dev->device_id == 0x2410) || (dev->device_id == 0x2420)))
1138 tmp |= 1 << 27;
1139 else
1140 tmp |= 1 << gpio;
1141 OUTL(tmp, base);
1142
1143 /* As soon as we are talking to ICH8 and above, this register
1144 decides whether we can set the gpio or not. */
1145 if (dev->device_id > 0x2800) {
1146 tmp = INL(base);
1147 if (!(tmp & (1 << gpio))) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001148 msg_perr("\nERROR: This Intel LPC Bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001149 " does not allow setting GPIO%02d\n",
1150 gpio);
1151 return -1;
1152 }
1153 }
1154
1155 /* Set GPIO to OUTPUT */
1156 tmp = INL(base + 0x04);
1157 tmp &= ~(1 << gpio);
1158 OUTL(tmp, base + 0x04);
1159
1160 /* Raise GPIO line */
1161 tmp = INL(base + 0x0C);
1162 if (raise)
1163 tmp |= 1 << gpio;
1164 else
1165 tmp &= ~(1 << gpio);
1166 OUTL(tmp, base + 0x0C);
1167 } else if (gpio < 64) {
1168 gpio -= 32;
1169
1170 /* Set line to GPIO */
1171 tmp = INL(base + 0x30);
1172 tmp |= 1 << gpio;
1173 OUTL(tmp, base + 0x30);
1174
1175 /* As soon as we are talking to ICH8 and above, this register
1176 decides whether we can set the gpio or not. */
1177 if (dev->device_id > 0x2800) {
1178 tmp = INL(base + 30);
1179 if (!(tmp & (1 << gpio))) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001180 msg_perr("\nERROR: This Intel LPC Bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001181 " does not allow setting GPIO%02d\n",
1182 gpio + 32);
1183 return -1;
1184 }
1185 }
1186
1187 /* Set GPIO to OUTPUT */
1188 tmp = INL(base + 0x34);
1189 tmp &= ~(1 << gpio);
1190 OUTL(tmp, base + 0x34);
1191
1192 /* Raise GPIO line */
1193 tmp = INL(base + 0x38);
1194 if (raise)
1195 tmp |= 1 << gpio;
1196 else
1197 tmp &= ~(1 << gpio);
1198 OUTL(tmp, base + 0x38);
1199 } else {
1200 gpio -= 64;
1201
1202 /* Set line to GPIO */
1203 tmp = INL(base + 0x40);
1204 tmp |= 1 << gpio;
1205 OUTL(tmp, base + 0x40);
1206
1207 tmp = INL(base + 40);
1208 if (!(tmp & (1 << gpio))) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001209 msg_perr("\nERROR: This Intel LPC Bridge does "
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001210 "not allow setting GPIO%02d\n", gpio + 64);
1211 return -1;
1212 }
1213
1214 /* Set GPIO to OUTPUT */
1215 tmp = INL(base + 0x44);
1216 tmp &= ~(1 << gpio);
1217 OUTL(tmp, base + 0x44);
1218
1219 /* Raise GPIO line */
1220 tmp = INL(base + 0x48);
1221 if (raise)
1222 tmp |= 1 << gpio;
1223 else
1224 tmp &= ~(1 << gpio);
1225 OUTL(tmp, base + 0x48);
1226 }
Uwe Hermann93f66db2008-05-22 21:19:38 +00001227
1228 return 0;
1229}
1230
1231/**
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001232 * Suited for Abit IP35: Intel P35 + ICH9R.
Michael Karcherb4a3d1c2010-03-03 16:15:12 +00001233 * Suited for Abit IP35 Pro: Intel P35 + ICH9R.
Uwe Hermann93f66db2008-05-22 21:19:38 +00001234 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001235static int intel_ich_gpio16_raise(void)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001236{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001237 return intel_ich_gpio_set(16, 1);
Uwe Hermann93f66db2008-05-22 21:19:38 +00001238}
1239
Peter Stuge09c13332009-02-02 22:55:26 +00001240/**
James Lancaster998c9dc2010-03-19 22:39:24 +00001241 * Suited for ASUS A8JM: Intel 945 + ICH7
1242 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001243static int intel_ich_gpio34_raise(void)
James Lancaster998c9dc2010-03-19 22:39:24 +00001244{
1245 return intel_ich_gpio_set(34, 1);
1246}
1247
1248/**
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001249 * Suited for MSI MS-7046: LGA775 + 915P + ICH6.
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001250 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001251static int intel_ich_gpio19_raise(void)
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001252{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001253 return intel_ich_gpio_set(19, 1);
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001254}
1255
1256/**
Luc Verhaegen6c5d4cc2009-11-28 18:26:21 +00001257 * Suited for:
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001258 * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2.
1259 * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5.
1260 * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R.
Peter Stuge09c13332009-02-02 22:55:26 +00001261 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001262static int intel_ich_gpio21_raise(void)
Peter Stuge09c13332009-02-02 22:55:26 +00001263{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001264 return intel_ich_gpio_set(21, 1);
Peter Stuge09c13332009-02-02 22:55:26 +00001265}
1266
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001267/**
Michael Karcher03b80e92010-03-07 16:32:32 +00001268 * Suited for:
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001269 * - ASUS P4B266: socket478 + Intel 845D + ICH2.
1270 * - ASUS P4B533-E: socket478 + 845E + ICH4
1271 * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001272 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001273static int intel_ich_gpio22_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001274{
1275 return intel_ich_gpio_set(22, 1);
1276}
1277
1278/**
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001279 * Suited for HP Vectra VL400: 815 + ICH + PC87360.
1280 */
1281
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001282static int board_hp_vl400(void)
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001283{
1284 int ret;
1285 ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */
1286 if (!ret)
1287 ret = pc87360_gpio_set(0x09, 1); /* #WP ? */
1288 if (!ret)
1289 ret = pc87360_gpio_set(0x27, 1); /* #TBL */
1290 return ret;
1291}
1292
1293/**
Luc Verhaegen1265d8d2009-11-28 18:16:31 +00001294 * Suited for:
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001295 * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R.
Luc Verhaegen1265d8d2009-11-28 18:16:31 +00001296 * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R.
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001297 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001298static int intel_ich_gpio23_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001299{
1300 return intel_ich_gpio_set(23, 1);
1301}
1302
1303/**
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001304 * Suited for IBase MB899: i945GM + ICH7.
1305 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001306static int intel_ich_gpio26_raise(void)
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001307{
1308 return intel_ich_gpio_set(26, 1);
1309}
1310
1311/**
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001312 * Suited for Acorp 6A815EPD: socket 370 + intel 815 + ICH2.
1313 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001314static int board_acorp_6a815epd(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001315{
1316 int ret;
1317
1318 /* Lower Blocks Lock -- pin 7 of PLCC32 */
1319 ret = intel_ich_gpio_set(22, 1);
1320 if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */
1321 ret = intel_ich_gpio_set(23, 1);
1322
1323 return ret;
1324}
1325
1326/**
1327 * Suited for Kontron 986LCD-M: socket478 + 915GM + ICH7R.
1328 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001329static int board_kontron_986lcd_m(void)
Stefan Reinauerac378972008-03-17 22:59:40 +00001330{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001331 int ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001332
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001333 ret = intel_ich_gpio_set(34, 1); /* #TBL */
1334 if (!ret)
1335 ret = intel_ich_gpio_set(35, 1); /* #WP */
Stefan Reinauerac378972008-03-17 22:59:40 +00001336
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001337 return ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001338}
1339
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001340/**
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001341 * Suited for Soyo SY-7VCA: Pro133A + VT82C686.
1342 */
Michael Karcher06477332010-03-19 22:49:09 +00001343static int via_apollo_gpo_set(int gpio, int raise)
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001344{
Michael Karcher06477332010-03-19 22:49:09 +00001345 struct pci_dev *dev;
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001346 uint32_t base;
Michael Karcher06477332010-03-19 22:49:09 +00001347 uint32_t tmp;
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001348
1349 /* VT82C686 Power management */
1350 dev = pci_dev_find(0x1106, 0x3057);
1351 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001352 msg_perr("\nERROR: VT82C686 PM device not found.\n");
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001353 return -1;
1354 }
1355
Sean Nelson316a29f2010-05-07 20:09:04 +00001356 msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n",
Michael Karcher06477332010-03-19 22:49:09 +00001357 raise ? "Rais" : "Dropp", gpio);
1358
1359 /* select GPO function on multiplexed pins */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001360 tmp = pci_read_byte(dev, 0x54);
Michael Karcher06477332010-03-19 22:49:09 +00001361 switch(gpio)
1362 {
1363 case 0:
1364 tmp &= ~0x03;
1365 break;
1366 case 1:
1367 tmp |= 0x04;
1368 break;
1369 case 2:
1370 tmp |= 0x08;
1371 break;
1372 case 3:
1373 tmp |= 0x10;
1374 break;
1375 }
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001376 pci_write_byte(dev, 0x54, tmp);
1377
1378 /* PM IO base */
1379 base = pci_read_long(dev, 0x48) & 0x0000FF00;
1380
1381 /* Drop GPO0 */
Michael Karcher06477332010-03-19 22:49:09 +00001382 tmp = INL(base + 0x4C);
1383 if (raise)
1384 tmp |= 1U << gpio;
1385 else
1386 tmp &= ~(1U << gpio);
1387 OUTL(tmp, base + 0x4C);
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001388
1389 return 0;
1390}
1391
Michael Karcher9f9e6132010-01-09 17:36:06 +00001392/**
Michael Karcher98eff462010-03-24 22:55:56 +00001393 * Suited for Abit VT6X4: Pro133x + VT82C686A
Michael Karcher187a46a2010-03-19 22:30:49 +00001394 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001395static int via_apollo_gpo4_lower(void)
Michael Karcher187a46a2010-03-19 22:30:49 +00001396{
1397 return via_apollo_gpo_set(4, 0);
1398}
1399
1400/**
Michael Karcher06477332010-03-19 22:49:09 +00001401 * Suited for Soyo SY-7VCA: Pro133A + VT82C686.
1402 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001403static int via_apollo_gpo0_lower(void)
Michael Karcher06477332010-03-19 22:49:09 +00001404{
1405 return via_apollo_gpo_set(0, 0);
1406}
1407
1408/**
Michael Karcher9f9e6132010-01-09 17:36:06 +00001409 * Enable some GPIO pin on SiS southbridge.
1410 * Suited for MSI 651M-L: SiS651 / SiS962
1411 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001412static int board_msi_651ml(void)
Michael Karcher9f9e6132010-01-09 17:36:06 +00001413{
1414 struct pci_dev *dev;
Uwe Hermann43959702010-03-13 17:28:29 +00001415 uint16_t base, temp;
Michael Karcher9f9e6132010-01-09 17:36:06 +00001416
1417 dev = pci_dev_find(0x1039, 0x0962);
1418 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001419 msg_perr("Expected south bridge not found\n");
Michael Karcher9f9e6132010-01-09 17:36:06 +00001420 return 1;
1421 }
1422
1423 /* Registers 68 and 64 seem like bitmaps */
1424 base = pci_read_word(dev, 0x74);
1425 temp = INW(base + 0x68);
1426 temp &= ~(1 << 0); /* Make pin output? */
Michael Karcher0435dfd2010-01-09 23:31:13 +00001427 OUTW(temp, base + 0x68);
Michael Karcher9f9e6132010-01-09 17:36:06 +00001428
1429 temp = INW(base + 0x64);
1430 temp |= (1 << 0); /* Raise output? */
1431 OUTW(temp, base + 0x64);
1432
1433 w836xx_memw_enable(0x2E);
1434
1435 return 0;
1436}
1437
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001438/**
Michael Gold6d52e472009-06-19 13:00:24 +00001439 * Find the runtime registers of an SMSC Super I/O, after verifying its
1440 * chip ID.
1441 *
1442 * Returns the base port of the runtime register block, or 0 on error.
1443 */
1444static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
1445 uint8_t logical_device)
1446{
1447 uint16_t rt_port = 0;
1448
1449 /* Verify the chip ID. */
Uwe Hermann1432a602009-06-28 23:26:37 +00001450 OUTB(0x55, sio_port); /* Enable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00001451 if (sio_read(sio_port, 0x20) != chip_id) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001452 msg_perr("\nERROR: SMSC Super I/O not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00001453 goto out;
1454 }
1455
1456 /* If the runtime block is active, get its address. */
1457 sio_write(sio_port, 0x07, logical_device);
1458 if (sio_read(sio_port, 0x30) & 1) {
1459 rt_port = (sio_read(sio_port, 0x60) << 8)
1460 | sio_read(sio_port, 0x61);
1461 }
1462
1463 if (rt_port == 0) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001464 msg_perr("\nERROR: "
Michael Gold6d52e472009-06-19 13:00:24 +00001465 "Super I/O runtime interface not available.\n");
1466 }
1467out:
Uwe Hermann1432a602009-06-28 23:26:37 +00001468 OUTB(0xaa, sio_port); /* Disable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00001469 return rt_port;
1470}
1471
1472/**
1473 * Disable write protection on the Mitac 6513WU. WP# on the FWH is
1474 * connected to GP30 on the Super I/O, and TBL# is always high.
1475 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001476static int board_mitac_6513wu(void)
Michael Gold6d52e472009-06-19 13:00:24 +00001477{
1478 struct pci_dev *dev;
1479 uint16_t rt_port;
1480 uint8_t val;
1481
1482 dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */
1483 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001484 msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00001485 return -1;
1486 }
1487
Uwe Hermann1432a602009-06-28 23:26:37 +00001488 rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa);
Michael Gold6d52e472009-06-19 13:00:24 +00001489 if (rt_port == 0)
1490 return -1;
1491
1492 /* Configure the GPIO pin. */
1493 val = INB(rt_port + 0x33); /* GP30 config */
Uwe Hermann1432a602009-06-28 23:26:37 +00001494 val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */
Michael Gold6d52e472009-06-19 13:00:24 +00001495 OUTB(val, rt_port + 0x33);
1496
1497 /* Disable write protection. */
1498 val = INB(rt_port + 0x4d); /* GP3 values */
Uwe Hermann1432a602009-06-28 23:26:37 +00001499 val |= 0x01; /* Set GP30 high. */
Michael Gold6d52e472009-06-19 13:00:24 +00001500 OUTB(val, rt_port + 0x4d);
1501
1502 return 0;
1503}
1504
1505/**
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001506 * Suited for ASUS A7V8X: VIA KT400 + VT8235 + IT8703F-A
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001507 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001508static int board_asus_a7v8x(void)
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001509{
1510 uint16_t id, base;
1511 uint8_t tmp;
1512
1513 /* find the IT8703F */
1514 w836xx_ext_enter(0x2E);
1515 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
1516 w836xx_ext_leave(0x2E);
1517
1518 if (id != 0x8701) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001519 msg_perr("\nERROR: IT8703F Super I/O not found.\n");
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001520 return -1;
1521 }
1522
1523 /* Get the GP567 IO base */
1524 w836xx_ext_enter(0x2E);
1525 sio_write(0x2E, 0x07, 0x0C);
1526 base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
1527 w836xx_ext_leave(0x2E);
1528
1529 if (!base) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001530 msg_perr("\nERROR: Failed to read IT8703F Super I/O GPIO"
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001531 " Base.\n");
1532 return -1;
1533 }
1534
1535 /* Raise GP51. */
1536 tmp = INB(base);
1537 tmp |= 0x02;
1538 OUTB(tmp, base);
1539
1540 return 0;
1541}
1542
Luc Verhaegen72272912009-09-01 21:22:23 +00001543/*
1544 * General routine for raising/dropping GPIO lines on the ITE IT8712F.
1545 * There is only some limited checking on the port numbers.
1546 */
Uwe Hermann43959702010-03-13 17:28:29 +00001547static int it8712f_gpio_set(unsigned int line, int raise)
Luc Verhaegen72272912009-09-01 21:22:23 +00001548{
1549 unsigned int port;
1550 uint16_t id, base;
1551 uint8_t tmp;
1552
1553 port = line / 10;
1554 port--;
1555 line %= 10;
1556
1557 /* Check line */
1558 if ((port > 4) || /* also catches unsigned -1 */
1559 ((port < 4) && (line > 7)) || ((port == 4) && (line > 5))) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001560 msg_perr("\nERROR: Unsupported IT8712F GPIO Line %02d.\n", line);
Luc Verhaegen72272912009-09-01 21:22:23 +00001561 return -1;
1562 }
1563
1564 /* find the IT8712F */
1565 enter_conf_mode_ite(0x2E);
1566 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
1567 exit_conf_mode_ite(0x2E);
1568
1569 if (id != 0x8712) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001570 msg_perr("\nERROR: IT8712F Super I/O not found.\n");
Luc Verhaegen72272912009-09-01 21:22:23 +00001571 return -1;
1572 }
1573
1574 /* Get the GPIO base */
1575 enter_conf_mode_ite(0x2E);
1576 sio_write(0x2E, 0x07, 0x07);
1577 base = (sio_read(0x2E, 0x62) << 8) | sio_read(0x2E, 0x63);
1578 exit_conf_mode_ite(0x2E);
1579
1580 if (!base) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001581 msg_perr("\nERROR: Failed to read IT8712F Super I/O GPIO"
Luc Verhaegen72272912009-09-01 21:22:23 +00001582 " Base.\n");
1583 return -1;
1584 }
1585
1586 /* set GPIO. */
1587 tmp = INB(base + port);
1588 if (raise)
1589 tmp |= 1 << line;
1590 else
1591 tmp &= ~(1 << line);
1592 OUTB(tmp, base + port);
1593
1594 return 0;
1595}
1596
1597/**
Russ Dillbd622d12010-03-09 16:57:06 +00001598 * Suited for:
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001599 * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F
1600 * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F
Luc Verhaegen72272912009-09-01 21:22:23 +00001601 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001602static int it8712f_gpio3_1_raise(void)
Luc Verhaegen72272912009-09-01 21:22:23 +00001603{
1604 return it8712f_gpio_set(32, 1);
1605}
1606
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001607#endif
1608
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001609/**
Uwe Hermannd0e347d2009-10-06 13:00:00 +00001610 * Below is the list of boards which need a special "board enable" code in
1611 * flashrom before their ROM chip can be accessed/written to.
1612 *
1613 * NOTE: Please add boards that _don't_ need such enables or don't work yet
1614 * to the respective tables in print.c. Thanks!
1615 *
Uwe Hermannffec5f32007-08-23 16:08:21 +00001616 * We use 2 sets of IDs here, you're free to choose which is which. This
1617 * is to provide a very high degree of certainty when matching a board on
1618 * the basis of subsystem/card IDs. As not every vendor handles
1619 * subsystem/card IDs in a sane manner.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001620 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00001621 * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00001622 * NULLed if they don't identify the board fully and if you can't use DMI.
1623 * But please take care to provide an as complete set of pci ids as possible;
1624 * autodetection is the preferred behaviour and we would like to make sure that
1625 * matches are unique.
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001626 *
Michael Karcher6701ee82010-01-20 14:14:11 +00001627 * If PCI IDs are not sufficient for board matching, the match can be further
1628 * constrained by a string that has to be present in the DMI database for
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001629 * the baseboard or the system entry. The pattern is matched by case sensitive
Michael Karcher6701ee82010-01-20 14:14:11 +00001630 * substring match, unless it is anchored to the beginning (with a ^ in front)
1631 * or the end (with a $ at the end). Both anchors may be specified at the
1632 * same time to match the full field.
1633 *
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00001634 * When a board is matched through DMI, the first and second main PCI IDs
1635 * and the first subsystem PCI ID have to match as well. If you specify the
1636 * first subsystem ID as 0x0:0x0, the DMI matching code expects that the
1637 * subsystem ID of that device is indeed zero.
1638 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00001639 * The coreboot ids are used two fold. When running with a coreboot firmware,
1640 * the ids uniquely matches the coreboot board identification string. When a
1641 * legacy bios is installed and when autodetection is not possible, these ids
1642 * can be used to identify the board through the -m command line argument.
1643 *
1644 * When a board is identified through its coreboot ids (in both cases), the
1645 * main pci ids are still required to match, as a safeguard.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001646 */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001647
Uwe Hermanndeeebe22009-05-08 16:23:34 +00001648/* Please keep this list alphabetically ordered by vendor/board name. */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00001649const struct board_pciid_enable board_pciid_enables[] = {
Uwe Hermann5ab88892009-06-21 20:50:22 +00001650
Michael Karcher0bdc0922010-02-28 01:33:48 +00001651 /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001652#if defined(__i386__) || defined(__x86_64__)
Sean Nelsonc94746d2010-03-19 23:00:07 +00001653 {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001654 {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise},
Michael Karcherb4a3d1c2010-03-03 16:15:12 +00001655 {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise},
Sean Nelson92bc6bd2010-03-19 22:37:29 +00001656 {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, "Abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower},
Michael Karcher8f10d242010-04-11 21:01:06 +00001657 {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, "Abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise},
Michael Karcher98eff462010-03-24 22:55:56 +00001658 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, OK, via_apollo_gpo4_lower},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001659 {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001660 {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e},
Peter Lemenkov4073c092010-05-26 22:29:51 +00001661 {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001662 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x},
1663 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x},
Peter Lemenkoveb75ced2010-05-26 22:26:44 +00001664 {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise},
Russ Dillbd622d12010-03-09 16:57:06 +00001665 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise},
Peter Lemenkoveb75ced2010-05-26 22:26:44 +00001666 {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001667 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, board_asus_a7v8x},
Russ Dillbd622d12010-03-09 16:57:06 +00001668 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise},
James Lancaster998c9dc2010-03-19 22:39:24 +00001669 {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, "ASUS", "A8JM", 0, NT, intel_ich_gpio34_raise},
Sean Nelson392e05a2010-03-19 22:58:15 +00001670 {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI", NULL, NULL, "ASUS", "A8N-LA", 0, NT, nvidia_mcp_gpio0_raise},
Peter Lemenkoveb75ced2010-05-26 22:26:44 +00001671 {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N", 0, NT, board_shuttle_fn25},
Michael Karcher7af6cef2010-07-08 09:32:18 +00001672 {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, "ASUS", "A8N-VM CSM", 0, NT, w83627ehf_gpio24_raise_2e},
Michael Karcherb2184c12010-03-07 16:42:55 +00001673 {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001674 {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001675 {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise},
Peter Lemenkoveb75ced2010-05-26 22:26:44 +00001676 {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise},
Michael Karcher255a9e02010-03-19 22:52:00 +00001677 {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise},
Michael Karcher6499d5a2010-03-17 06:19:23 +00001678 {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001679 {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
1680 {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a},
1681 {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001682 {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise},
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +00001683 {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, NULL},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001684 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e},
1685 {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise},
1686 {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", "EPoX", "EP-BX3", 0, OK, board_epox_ep_bx3},
Peter Lemenkoveb75ced2010-05-26 22:26:44 +00001687 {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001688 {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise},
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +00001689 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable},
1690 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", "HP", "DL165 G6", 0, OK, board_hp_dl165_g6_enable},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001691 {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400},
Michael Karcher03b80e92010-03-07 16:32:32 +00001692 {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise},
Michael Karcher2ead2e22010-06-01 16:09:06 +00001693 {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, NULL, NULL, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise},
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001694 {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", "iBASE", "MB899", 0, NT, intel_ich_gpio26_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001695 {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455},
1696 {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi},
Michael Karcher51cd0c92010-03-19 22:35:21 +00001697 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001698 {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e},
James Lancaster998c9dc2010-03-19 22:39:24 +00001699 {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001700 {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, "Mitac", "6513WU", 0, OK, board_mitac_6513wu},
Peter Lemenkoveb75ced2010-05-26 22:26:44 +00001701 {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001702 {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v},
Michael Karcherbcd80cd2010-06-27 15:07:49 +00001703 {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio44_raise_2e},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001704 {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v},
1705 {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml},
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001706 {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001707 {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise},
Michael Karcherbcd80cd2010-06-27 15:07:49 +00001708 {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio44_raise_4e},
Michael Karcher5fdf2702010-03-07 16:52:59 +00001709 {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise},
Michael Karcherb3fe2fc2010-05-24 16:03:57 +00001710 {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001711 {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e},
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +00001712 {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, NULL},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001713 {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25},
Michael Karcher06477332010-03-19 22:49:09 +00001714 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001715 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, OK, NULL},
Daniel Brandt4ad4c742010-03-21 13:36:20 +00001716 {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e},
Peter Lemenkoveb75ced2010-05-26 22:26:44 +00001717 {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e},
Michael Karcherbcd25562010-06-12 17:27:44 +00001718 {0x1106, 0x0259, 0x1106, 0xAA07, 0x1106, 0x3227, 0x1106, 0xAA07, NULL, NULL, NULL, "VIA", "EPIA EK", 0, NT, via_vt823x_gpio9_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001719 {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise},
1720 {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise},
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001721#endif
Michael Karcher0bdc0922010-02-28 01:33:48 +00001722 { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001723};
1724
Uwe Hermannffec5f32007-08-23 16:08:21 +00001725/**
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00001726 * Match boards on coreboot table gathered vendor and part name.
Uwe Hermannffec5f32007-08-23 16:08:21 +00001727 * Require main PCI IDs to match too as extra safety.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001728 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00001729static const struct board_pciid_enable *board_match_coreboot_name(const char *vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00001730 const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001731{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00001732 const struct board_pciid_enable *board = board_pciid_enables;
1733 const struct board_pciid_enable *partmatch = NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001734
Uwe Hermanna93045c2009-05-09 00:47:04 +00001735 for (; board->vendor_name; board++) {
Uwe Hermann394131e2008-10-18 21:14:13 +00001736 if (vendor && (!board->lb_vendor
1737 || strcasecmp(board->lb_vendor, vendor)))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001738 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001739
Peter Stuge0b9c5f32008-07-02 00:47:30 +00001740 if (!board->lb_part || strcasecmp(board->lb_part, part))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001741 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001742
Uwe Hermanna7e05482007-05-09 10:17:44 +00001743 if (!pci_dev_find(board->first_vendor, board->first_device))
1744 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001745
Uwe Hermanna7e05482007-05-09 10:17:44 +00001746 if (board->second_vendor &&
Uwe Hermann394131e2008-10-18 21:14:13 +00001747 !pci_dev_find(board->second_vendor, board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001748 continue;
Peter Stuge6b53fed2008-01-27 16:21:21 +00001749
1750 if (vendor)
1751 return board;
1752
1753 if (partmatch) {
1754 /* a second entry has a matching part name */
Sean Nelson316a29f2010-05-07 20:09:04 +00001755 msg_pinfo("AMBIGUOUS BOARD NAME: %s\n", part);
1756 msg_pinfo("At least vendors '%s' and '%s' match.\n",
Uwe Hermann394131e2008-10-18 21:14:13 +00001757 partmatch->lb_vendor, board->lb_vendor);
Sean Nelson316a29f2010-05-07 20:09:04 +00001758 msg_perr("Please use the full -m vendor:part syntax.\n");
Peter Stuge6b53fed2008-01-27 16:21:21 +00001759 return NULL;
1760 }
1761 partmatch = board;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001762 }
Uwe Hermann372eeb52007-12-04 21:49:06 +00001763
Peter Stuge6b53fed2008-01-27 16:21:21 +00001764 if (partmatch)
1765 return partmatch;
1766
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00001767 if (!partvendor_from_cbtable) {
1768 /* Only warn if the mainboard type was not gathered from the
1769 * coreboot table. If it was, the coreboot implementor is
1770 * expected to fix flashrom, too.
1771 */
Sean Nelson316a29f2010-05-07 20:09:04 +00001772 msg_perr("\nUnknown vendor:board from -m option: %s:%s\n\n",
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00001773 vendor, part);
1774 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00001775 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001776}
1777
Uwe Hermannffec5f32007-08-23 16:08:21 +00001778/**
1779 * Match boards on PCI IDs and subsystem IDs.
1780 * Second set of IDs can be main only or missing completely.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001781 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00001782const static struct board_pciid_enable *board_match_pci_card_ids(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001783{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00001784 const struct board_pciid_enable *board = board_pciid_enables;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001785
Uwe Hermanna93045c2009-05-09 00:47:04 +00001786 for (; board->vendor_name; board++) {
Michael Karcher2eab70d2010-02-04 10:58:50 +00001787 if ((!board->first_card_vendor || !board->first_card_device) &&
1788 !board->dmi_pattern)
Uwe Hermanna7e05482007-05-09 10:17:44 +00001789 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001790
Uwe Hermanna7e05482007-05-09 10:17:44 +00001791 if (!pci_card_find(board->first_vendor, board->first_device,
Uwe Hermann394131e2008-10-18 21:14:13 +00001792 board->first_card_vendor,
1793 board->first_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001794 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001795
Uwe Hermanna7e05482007-05-09 10:17:44 +00001796 if (board->second_vendor) {
1797 if (board->second_card_vendor) {
1798 if (!pci_card_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00001799 board->second_device,
1800 board->second_card_vendor,
1801 board->second_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001802 continue;
1803 } else {
1804 if (!pci_dev_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00001805 board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001806 continue;
1807 }
1808 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001809
Michael Karcher6701ee82010-01-20 14:14:11 +00001810 if (board->dmi_pattern) {
1811 if (!has_dmi_support) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001812 msg_perr("WARNING: Can't autodetect %s %s,"
Michael Karcher6701ee82010-01-20 14:14:11 +00001813 " DMI info unavailable.\n",
1814 board->vendor_name, board->board_name);
1815 continue;
1816 } else {
1817 if (!dmi_match(board->dmi_pattern))
1818 continue;
1819 }
1820 }
1821
Uwe Hermanna7e05482007-05-09 10:17:44 +00001822 return board;
1823 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001824
Uwe Hermanna7e05482007-05-09 10:17:44 +00001825 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001826}
1827
Uwe Hermann372eeb52007-12-04 21:49:06 +00001828int board_flash_enable(const char *vendor, const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001829{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00001830 const struct board_pciid_enable *board = NULL;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001831 int ret = 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001832
Peter Stuge6b53fed2008-01-27 16:21:21 +00001833 if (part)
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00001834 board = board_match_coreboot_name(vendor, part);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001835
Uwe Hermanna7e05482007-05-09 10:17:44 +00001836 if (!board)
1837 board = board_match_pci_card_ids();
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001838
Michael Karcher0b9e2a72010-03-11 23:04:16 +00001839 if (board && board->status == NT) {
Uwe Hermann43959702010-03-13 17:28:29 +00001840 if (!force_boardenable) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001841 msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n"
Michael Karcher7f0c3ec2010-03-07 22:29:28 +00001842 "code has not been tested, and thus will not not be executed by default.\n"
1843 "Depending on your hardware environment, erasing, writing or even probing\n"
1844 "can fail without running the board specific code.\n\n"
1845 "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n"
Uwe Hermann43959702010-03-13 17:28:29 +00001846 "\"internal programmer\") for details.\n",
Michael Karcher7f0c3ec2010-03-07 22:29:28 +00001847 board->vendor_name, board->board_name);
1848 board = NULL;
Uwe Hermann43959702010-03-13 17:28:29 +00001849 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +00001850 msg_pinfo("NOTE: Running an untested board enable procedure.\n"
Uwe Hermann43959702010-03-13 17:28:29 +00001851 "Please report success/failure to flashrom@flashrom.org.\n");
1852 }
Michael Karcher7f0c3ec2010-03-07 22:29:28 +00001853 }
1854
Uwe Hermanna7e05482007-05-09 10:17:44 +00001855 if (board) {
Luc Verhaegen93938c32010-01-20 14:45:03 +00001856 if (board->max_rom_decode_parallel)
1857 max_rom_decode.parallel =
1858 board->max_rom_decode_parallel * 1024;
1859
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00001860 if (board->enable != NULL) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001861 msg_pinfo("Disabling flash write protection for "
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00001862 "board \"%s %s\"... ", board->vendor_name,
1863 board->board_name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001864
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001865 ret = board->enable();
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00001866 if (ret)
Sean Nelson316a29f2010-05-07 20:09:04 +00001867 msg_pinfo("FAILED!\n");
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00001868 else
Sean Nelson316a29f2010-05-07 20:09:04 +00001869 msg_pinfo("OK.\n");
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00001870 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00001871 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001872
Uwe Hermanna7e05482007-05-09 10:17:44 +00001873 return ret;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001874}