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Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +00006 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
Carl-Daniel Hailfinger92242622007-09-27 14:29:57 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000021 */
22
23/*
24 * Contains the board specific flash enables.
25 */
26
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000027#include <string.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000028#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000029#include "programmer.h"
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000030
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000031#if defined(__i386__) || defined(__x86_64__)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000032/*
Uwe Hermannffec5f32007-08-23 16:08:21 +000033 * Helper functions for many Winbond Super I/Os of the W836xx range.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000034 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000035/* Enter extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000036void w836xx_ext_enter(uint16_t port)
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000037{
Andriy Gapon65c1b862008-05-22 13:22:45 +000038 OUTB(0x87, port);
39 OUTB(0x87, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000040}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000041
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000042/* Leave extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000043void w836xx_ext_leave(uint16_t port)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000044{
Andriy Gapon65c1b862008-05-22 13:22:45 +000045 OUTB(0xAA, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000046}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000047
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000048/* Generic Super I/O helper functions */
49uint8_t sio_read(uint16_t port, uint8_t reg)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000050{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000051 OUTB(reg, port);
52 return INB(port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000053}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000054
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000055void sio_write(uint16_t port, uint8_t reg, uint8_t data)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000056{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000057 OUTB(reg, port);
58 OUTB(data, port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000059}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000060
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000061void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000062{
Ronald G. Minnichfa496922007-10-12 21:22:40 +000063 uint8_t tmp;
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000064
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000065 OUTB(reg, port);
66 tmp = INB(port + 1) & ~mask;
67 OUTB(tmp | (data & mask), port + 1);
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000068}
69
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000070/* Not used yet. */
71#if 0
72static int enable_flash_decode_superio(void)
73{
74 int ret;
75 uint8_t tmp;
76
77 switch (superio.vendor) {
78 case SUPERIO_VENDOR_NONE:
79 ret = -1;
80 break;
81 case SUPERIO_VENDOR_ITE:
82 enter_conf_mode_ite(superio.port);
Uwe Hermann43959702010-03-13 17:28:29 +000083 /* Enable flash mapping. Works for most old ITE style Super I/O. */
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000084 tmp = sio_read(superio.port, 0x24);
85 tmp |= 0xfc;
86 sio_write(superio.port, 0x24, tmp);
87 exit_conf_mode_ite(superio.port);
88 ret = 0;
89 break;
90 default:
Sean Nelson316a29f2010-05-07 20:09:04 +000091 msg_pdbg("Unhandled Super I/O type!\n");
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000092 ret = -1;
93 break;
94 }
95 return ret;
96}
97#endif
98
Uwe Hermann48ec1b12010-08-08 17:01:18 +000099/*
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000100 * SMSC FDC37B787: Raise GPIO50
101 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000102static int fdc37b787_gpio50_raise(uint16_t port)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000103{
104 uint8_t id, val;
105
106 OUTB(0x55, port); /* enter conf mode */
107 id = sio_read(port, 0x20);
108 if (id != 0x44) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000109 msg_perr("\nERROR: FDC37B787: Wrong ID 0x%02X.\n", id);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000110 OUTB(0xAA, port); /* leave conf mode */
111 return -1;
112 }
113
114 sio_write(port, 0x07, 0x08); /* Select Aux I/O subdevice */
115
116 val = sio_read(port, 0xC8); /* GP50 */
117 if ((val & 0x1B) != 0x10) /* output, no invert, GPIO */
118 {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000119 msg_perr("\nERROR: GPIO50 mode 0x%02X unexpected.\n", val);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000120 OUTB(0xAA, port);
121 return -1;
122 }
123
124 sio_mask(port, 0xF9, 0x01, 0x01);
125
126 OUTB(0xAA, port); /* Leave conf mode */
127 return 0;
128}
129
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000130/*
131 * Suited for:
132 * - Nokia IP530: Intel 440BX + PIIX4 + FDC37B787
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000133 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000134static int fdc37b787_gpio50_raise_3f0(void)
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000135{
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000136 return fdc37b787_gpio50_raise(0x3f0);
Michael Karcherb3fe2fc2010-05-24 16:03:57 +0000137}
138
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000139struct winbond_mux {
140 uint8_t reg; /* 0 if the corresponding pin is not muxed */
141 uint8_t data; /* reg/data/mask may be directly ... */
142 uint8_t mask; /* ... passed to sio_mask */
143};
144
145struct winbond_port {
146 const struct winbond_mux *mux; /* NULL or pointer to mux info for the 8 bits */
147 uint8_t ldn; /* LDN this GPIO register is located in */
148 uint8_t enable_bit; /* bit in 0x30 of that LDN to enable
149 the GPIO port */
150 uint8_t base; /* base register in that LDN for the port */
151};
152
153struct winbond_chip {
154 uint8_t device_id; /* reg 0x20 of the expected w83626x */
155 uint8_t gpio_port_count;
156 const struct winbond_port *port;
157};
158
159
160#define UNIMPLEMENTED_PORT {NULL, 0, 0, 0}
161
162enum winbond_id {
163 WINBOND_W83627HF_ID = 0x52,
Michael Karcherea36c9c2010-06-27 15:07:52 +0000164 WINBOND_W83627EHF_ID = 0x88,
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000165 WINBOND_W83627THF_ID = 0x82,
166};
167
168static const struct winbond_mux w83627hf_port2_mux[8] = {
169 {0x2A, 0x01, 0x01}, /* or MIDI */
170 {0x2B, 0x80, 0x80}, /* or SPI */
171 {0x2B, 0x40, 0x40}, /* or SPI */
172 {0x2B, 0x20, 0x20}, /* or power LED */
173 {0x2B, 0x10, 0x10}, /* or watchdog */
174 {0x2B, 0x08, 0x08}, /* or infra red */
175 {0x2B, 0x04, 0x04}, /* or infra red */
176 {0x2B, 0x03, 0x03} /* or IRQ1 input */
177};
178
179static const struct winbond_port w83627hf[3] = {
180 UNIMPLEMENTED_PORT,
181 {w83627hf_port2_mux, 0x08, 0, 0xF0},
182 UNIMPLEMENTED_PORT
183};
184
Michael Karcherea36c9c2010-06-27 15:07:52 +0000185static const struct winbond_mux w83627ehf_port2_mux[8] = {
186 {0x29, 0x06, 0x02}, /* or MIDI */
187 {0x29, 0x06, 0x02},
188 {0x24, 0x02, 0x00}, /* or SPI ROM interface */
189 {0x24, 0x02, 0x00},
190 {0x2A, 0x01, 0x01}, /* or keyboard/mouse interface */
191 {0x2A, 0x01, 0x01},
192 {0x2A, 0x01, 0x01},
193 {0x2A, 0x01, 0x01}
194};
195
196static const struct winbond_port w83627ehf[6] = {
197 UNIMPLEMENTED_PORT,
198 {w83627ehf_port2_mux, 0x09, 0, 0xE3},
199 UNIMPLEMENTED_PORT,
200 UNIMPLEMENTED_PORT,
201 UNIMPLEMENTED_PORT,
202 UNIMPLEMENTED_PORT
203};
204
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000205static const struct winbond_mux w83627thf_port4_mux[8] = {
206 {0x2D, 0x01, 0x01}, /* or watchdog or VID level strap */
207 {0x2D, 0x02, 0x02}, /* or resume reset */
208 {0x2D, 0x04, 0x04}, /* or S3 input */
209 {0x2D, 0x08, 0x08}, /* or PSON# */
210 {0x2D, 0x10, 0x10}, /* or PWROK */
211 {0x2D, 0x20, 0x20}, /* or suspend LED */
212 {0x2D, 0x40, 0x40}, /* or panel switch input */
213 {0x2D, 0x80, 0x80} /* or panel switch output */
214};
215
216static const struct winbond_port w83627thf[5] = {
217 UNIMPLEMENTED_PORT, /* GPIO1 */
218 UNIMPLEMENTED_PORT, /* GPIO2 */
219 UNIMPLEMENTED_PORT, /* GPIO3 */
220 {w83627thf_port4_mux, 0x09, 1, 0xF4},
221 UNIMPLEMENTED_PORT /* GPIO5 */
222};
223
224static const struct winbond_chip winbond_chips[] = {
225 {WINBOND_W83627HF_ID, ARRAY_SIZE(w83627hf), w83627hf },
Michael Karcherea36c9c2010-06-27 15:07:52 +0000226 {WINBOND_W83627EHF_ID, ARRAY_SIZE(w83627ehf), w83627ehf},
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000227 {WINBOND_W83627THF_ID, ARRAY_SIZE(w83627thf), w83627thf},
228};
229
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000230/*
231 * Detects which Winbond Super I/O is responding at the given base address,
232 * but takes no effort to make sure the chip is really a Winbond Super I/O.
233 */
234static const struct winbond_chip *winbond_superio_detect(uint16_t base)
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000235{
236 uint8_t chipid;
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000237 const struct winbond_chip *chip = NULL;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000238 int i;
239
240 w836xx_ext_enter(base);
241 chipid = sio_read(base, 0x20);
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000242
243 for (i = 0; i < ARRAY_SIZE(winbond_chips); i++) {
244 if (winbond_chips[i].device_id == chipid) {
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000245 chip = &winbond_chips[i];
246 break;
247 }
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000248 }
249
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000250 w836xx_ext_leave(base);
251 return chip;
252}
253
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000254/*
255 * The chipid parameter goes away as soon as we have Super I/O matching in the
256 * board enable table. The call to winbond_superio_detect() goes away as
257 * soon as we have generic Super I/O detection code.
258 */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000259static int winbond_gpio_set(uint16_t base, enum winbond_id chipid,
260 int pin, int raise)
261{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000262 const struct winbond_chip *chip = NULL;
263 const struct winbond_port *gpio;
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000264 int port = pin / 10;
265 int bit = pin % 10;
266
267 chip = winbond_superio_detect(base);
268 if (!chip) {
269 msg_perr("\nERROR: No supported Winbond Super I/O found\n");
270 return -1;
271 }
Michael Karcher979d9252010-06-29 14:44:40 +0000272 if (chip->device_id != chipid) {
273 msg_perr("\nERROR: Found Winbond chip with ID 0x%x, "
274 "expected %x\n", chip->device_id, chipid);
275 return -1;
276 }
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000277 if (bit >= 8 || port == 0 || port > chip->gpio_port_count) {
278 msg_perr("\nERROR: winbond_gpio_set: Invalid GPIO number %d\n",
279 pin);
280 return -1;
281 }
282
283 gpio = &chip->port[port - 1];
284
285 if (gpio->ldn == 0) {
286 msg_perr("\nERROR: GPIO%d is not supported yet on this"
287 " winbond chip\n", port);
288 return -1;
289 }
290
291 w836xx_ext_enter(base);
292
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000293 /* Select logical device. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000294 sio_write(base, 0x07, gpio->ldn);
295
296 /* Activate logical device. */
297 sio_mask(base, 0x30, 1 << gpio->enable_bit, 1 << gpio->enable_bit);
298
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000299 /* Select GPIO function of that pin. */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000300 if (gpio->mux && gpio->mux[bit].reg)
301 sio_mask(base, gpio->mux[bit].reg,
302 gpio->mux[bit].data, gpio->mux[bit].mask);
303
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000304 sio_mask(base, gpio->base + 0, 0, 1 << bit); /* Make pin output */
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000305 sio_mask(base, gpio->base + 2, 0, 1 << bit); /* Clear inversion */
306 sio_mask(base, gpio->base + 1, raise << bit, 1 << bit);
307
308 w836xx_ext_leave(base);
309
310 return 0;
311}
312
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000313/*
Uwe Hermannffec5f32007-08-23 16:08:21 +0000314 * Winbond W83627HF: Raise GPIO24.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000315 *
316 * Suited for:
Uwe Hermannffec5f32007-08-23 16:08:21 +0000317 * - Agami Aruma
318 * - IWILL DK8-HTX
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000319 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000320static int w83627hf_gpio24_raise_2e(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000321{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000322 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 24, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000323}
324
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000325/*
Joshua Roysf280a382010-08-07 21:49:11 +0000326 * Winbond W83627HF: Raise GPIO25.
327 *
328 * Suited for:
329 * - MSI MS-6577
330 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000331static int w83627hf_gpio25_raise_2e(void)
Joshua Roysf280a382010-08-07 21:49:11 +0000332{
333 return winbond_gpio_set(0x2e, WINBOND_W83627HF_ID, 25, 1);
334}
335
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000336/*
Michael Karcherea36c9c2010-06-27 15:07:52 +0000337 * Winbond W83627EHF: Raise GPIO24.
338 *
339 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000340 * - ASUS A8N-VM CSM: AMD Socket 939 + GeForce 6150 (C51) + MCP51
Michael Karcherea36c9c2010-06-27 15:07:52 +0000341 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000342static int w83627ehf_gpio24_raise_2e(void)
Michael Karcherea36c9c2010-06-27 15:07:52 +0000343{
344 return winbond_gpio_set(0x2e, WINBOND_W83627EHF_ID, 24, 1);
345}
346
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000347/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000348 * Winbond W83627THF: Raise GPIO 44.
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000349 *
350 * Suited for:
Peter Stugecce26822008-07-21 17:48:40 +0000351 * - MSI K8T Neo2-F
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000352 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000353static int w83627thf_gpio44_raise_2e(void)
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000354{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000355 return winbond_gpio_set(0x2e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000356}
357
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000358/*
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000359 * Winbond W83627THF: Raise GPIO 44.
360 *
361 * Suited for:
362 * - MSI K8N Neo3
363 */
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000364static int w83627thf_gpio44_raise_4e(void)
Peter Stugecce26822008-07-21 17:48:40 +0000365{
Michael Karcherbcd80cd2010-06-27 15:07:49 +0000366 return winbond_gpio_set(0x4e, WINBOND_W83627THF_ID, 44, 1);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000367}
Uwe Hermann372eeb52007-12-04 21:49:06 +0000368
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000369/*
David Borgb6417a62010-08-02 08:29:34 +0000370 * Enable MEMW# and set ROM size to max.
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000371 * Supported chips: W83L517D, W83697HF/F/HG, W83697SF/UF/UG
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000372 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000373static void w836xx_memw_enable(uint16_t port)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000374{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000375 w836xx_ext_enter(port);
376 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000377 /* Enable MEMW# and set ROM size select to max. (4M). */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000378 sio_mask(port, 0x24, 0x28, 0x28);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000379 }
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000380 w836xx_ext_leave(port);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000381}
382
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000383/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000384 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000385 * - EPoX EP-8K5A2: VIA KT333 + VT8235
386 * - Albatron PM266A Pro: VIA P4M266A + VT8235
387 * - Shuttle AK31 (all versions): VIA KT266 + VT8233
388 * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
389 * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237
Mattias Mattssone295eee2010-08-15 10:21:29 +0000390 * - MSI KM4M-V and KM4AM-V: VIA KM400/KM400A + VT8237
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000391 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000392static int w836xx_memw_enable_2e(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000393{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000394 w836xx_memw_enable(0x2E);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000395
Luc Verhaegen73d21192009-12-23 00:54:26 +0000396 return 0;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000397}
398
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000399/*
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000400 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000401 * - Termtek TK-3370 (rev. 2.5b)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000402 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000403static int w836xx_memw_enable_4e(void)
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000404{
405 w836xx_memw_enable(0x4E);
406
407 return 0;
408}
409
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000410/*
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000411 * Suited for all boards with ITE IT8705F.
412 * The SIS950 Super I/O probably requires a similar flash write enable.
Luc Verhaegen21f54962010-01-20 14:45:07 +0000413 */
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000414int it8705f_write_enable(uint8_t port)
Luc Verhaegen21f54962010-01-20 14:45:07 +0000415{
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000416 uint8_t tmp;
417 int ret = 0;
418
Luc Verhaegen21f54962010-01-20 14:45:07 +0000419 enter_conf_mode_ite(port);
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000420 tmp = sio_read(port, 0x24);
421 /* Check if at least one flash segment is enabled. */
422 if (tmp & 0xf0) {
423 /* The IT8705F will respond to LPC cycles and translate them. */
424 buses_supported = CHIP_BUSTYPE_PARALLEL;
425 /* Flash ROM I/F Writes Enable */
426 tmp |= 0x04;
427 msg_pdbg("Enabling IT8705F flash ROM interface write.\n");
428 if (tmp & 0x02) {
429 /* The data sheet contradicts itself about max size. */
430 max_rom_decode.parallel = 1024 * 1024;
431 msg_pinfo("IT8705F with very unusual settings. Please "
432 "send the output of \"flashrom -V\" to \n"
433 "flashrom@flashrom.org to help us finish "
434 "support for your Super I/O. Thanks.\n");
435 ret = 1;
436 } else if (tmp & 0x08) {
437 max_rom_decode.parallel = 512 * 1024;
438 } else {
439 max_rom_decode.parallel = 256 * 1024;
440 }
441 /* Safety checks. The data sheet is unclear here: Segments 1+3
442 * overlap, no segment seems to cover top - 1MB to top - 512kB.
443 * We assume that certain combinations make no sense.
444 */
445 if (((tmp & 0x02) && !(tmp & 0x08)) || /* 1 MB en, 512 kB dis */
446 (!(tmp & 0x10)) || /* 128 kB dis */
447 (!(tmp & 0x40))) { /* 256/512 kB dis */
448 msg_perr("Inconsistent IT8705F decode size!\n");
449 ret = 1;
450 }
451 if (sio_read(port, 0x25) != 0) {
452 msg_perr("IT8705F flash data pins disabled!\n");
453 ret = 1;
454 }
455 if (sio_read(port, 0x26) != 0) {
456 msg_perr("IT8705F flash address pins 0-7 disabled!\n");
457 ret = 1;
458 }
459 if (sio_read(port, 0x27) != 0) {
460 msg_perr("IT8705F flash address pins 8-15 disabled!\n");
461 ret = 1;
462 }
463 if ((sio_read(port, 0x29) & 0x10) != 0) {
464 msg_perr("IT8705F flash write enable pin disabled!\n");
465 ret = 1;
466 }
467 if ((sio_read(port, 0x29) & 0x08) != 0) {
468 msg_perr("IT8705F flash chip select pin disabled!\n");
469 ret = 1;
470 }
471 if ((sio_read(port, 0x29) & 0x04) != 0) {
472 msg_perr("IT8705F flash read strobe pin disabled!\n");
473 ret = 1;
474 }
475 if ((sio_read(port, 0x29) & 0x03) != 0) {
476 msg_perr("IT8705F flash address pins 16-17 disabled!\n");
477 /* Not really an error if you use flash chips smaller
478 * than 256 kByte, but such a configuration is unlikely.
479 */
480 ret = 1;
481 }
482 msg_pdbg("Maximum IT8705F parallel flash decode size is %u.\n",
483 max_rom_decode.parallel);
484 if (ret) {
485 msg_pinfo("Not enabling IT8705F flash write.\n");
486 } else {
487 sio_write(port, 0x24, tmp);
488 }
489 } else {
490 msg_pdbg("No IT8705F flash segment enabled.\n");
491 /* Not sure if this is an error or not. */
492 ret = 0;
493 }
Luc Verhaegen21f54962010-01-20 14:45:07 +0000494 exit_conf_mode_ite(port);
495
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +0000496 return ret;
Luc Verhaegen21f54962010-01-20 14:45:07 +0000497}
Luc Verhaegen73d21192009-12-23 00:54:26 +0000498
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000499static int pc87360_gpio_set(uint8_t gpio, int raise)
500{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000501 static const int bankbase[] = {0, 4, 8, 10, 12};
502 int gpio_bank = gpio / 8;
503 int gpio_pin = gpio % 8;
504 uint16_t baseport;
505 uint8_t id, val;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000506
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000507 if (gpio_bank > 4) {
508 msg_perr("PC87360: Invalid GPIO %d\n", gpio);
509 return -1;
510 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000511
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000512 id = sio_read(0x2E, 0x20);
513 if (id != 0xE1) {
514 msg_perr("PC87360: unexpected ID %02x\n", id);
515 return -1;
516 }
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000517
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000518 sio_write(0x2E, 0x07, 0x07); /* Select GPIO device. */
519 baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
520 if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) {
521 msg_perr("PC87360: invalid GPIO base address %04x\n",
522 baseport);
523 return -1;
524 }
525 sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device. */
526 sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin);
527 sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output. */
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000528
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000529 val = INB(baseport + bankbase[gpio_bank]);
530 if (raise)
531 val |= 1 << gpio_pin;
532 else
533 val &= ~(1 << gpio_pin);
534 OUTB(val, baseport + bankbase[gpio_bank]);
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000535
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000536 return 0;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000537}
538
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000539/*
540 * VIA VT823x: Set one of the GPIO pins.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000541 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000542static int via_vt823x_gpio_set(uint8_t gpio, int raise)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000543{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000544 struct pci_dev *dev;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000545 uint16_t base;
David Bartleyf58d3642009-12-09 07:53:01 +0000546 uint8_t val, bit, offset;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000547
Luc Verhaegen73d21192009-12-23 00:54:26 +0000548 dev = pci_dev_find_vendorclass(0x1106, 0x0601);
549 switch (dev->device_id) {
550 case 0x3177: /* VT8235 */
551 case 0x3227: /* VT8237R */
552 case 0x3337: /* VT8237A */
553 break;
554 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000555 msg_perr("\nERROR: VT823x ISA bridge not found.\n");
Luc Verhaegen73d21192009-12-23 00:54:26 +0000556 return -1;
557 }
558
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000559 if ((gpio >= 12) && (gpio <= 15)) {
560 /* GPIO12-15 -> output */
561 val = pci_read_byte(dev, 0xE4);
562 val |= 0x10;
563 pci_write_byte(dev, 0xE4, val);
564 } else if (gpio == 9) {
565 /* GPIO9 -> Output */
566 val = pci_read_byte(dev, 0xE4);
567 val |= 0x20;
568 pci_write_byte(dev, 0xE4, val);
David Bartleyf58d3642009-12-09 07:53:01 +0000569 } else if (gpio == 5) {
570 val = pci_read_byte(dev, 0xE4);
571 val |= 0x01;
572 pci_write_byte(dev, 0xE4, val);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000573 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000574 msg_perr("\nERROR: "
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000575 "VT823x GPIO%02d is not implemented.\n", gpio);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000576 return -1;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000577 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000578
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000579 /* We need the I/O Base Address for this board's flash enable. */
580 base = pci_read_word(dev, 0x88) & 0xff80;
581
David Bartleyf58d3642009-12-09 07:53:01 +0000582 offset = 0x4C + gpio / 8;
583 bit = 0x01 << (gpio % 8);
584
585 val = INB(base + offset);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000586 if (raise)
587 val |= bit;
588 else
589 val &= ~bit;
David Bartleyf58d3642009-12-09 07:53:01 +0000590 OUTB(val, base + offset);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000591
Uwe Hermanna7e05482007-05-09 10:17:44 +0000592 return 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000593}
594
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000595/*
596 * Suited for:
597 * - ASUS M2V-MX: VIA K8M890 + VT8237A + IT8716F
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000598 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000599static int via_vt823x_gpio5_raise(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000600{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000601 /* On M2V-MX: GPO5 is connected to WP# and TBL#. */
602 return via_vt823x_gpio_set(5, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000603}
604
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000605/*
606 * Suited for:
607 * - VIA EPIA EK & N & NL
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000608 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000609static int via_vt823x_gpio9_raise(void)
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000610{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000611 return via_vt823x_gpio_set(9, 1);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000612}
613
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000614/*
615 * Suited for:
616 * - VIA EPIA M and MII (and maybe other CLE266 based EPIAs)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000617 *
618 * We don't need to do this for EPIA M when using coreboot, GPIO15 is never
619 * lowered there.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000620 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000621static int via_vt823x_gpio15_raise(void)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000622{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000623 return via_vt823x_gpio_set(15, 1);
624}
625
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000626/*
Luc Verhaegen73d21192009-12-23 00:54:26 +0000627 * Winbond W83697HF Super I/O + VIA VT8235 southbridge
628 *
629 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000630 * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
631 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
Luc Verhaegen73d21192009-12-23 00:54:26 +0000632 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000633static int board_msi_kt4v(void)
Luc Verhaegen73d21192009-12-23 00:54:26 +0000634{
635 int ret;
636
637 ret = via_vt823x_gpio_set(12, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000638 w836xx_memw_enable(0x2E);
Luc Verhaegen97866082008-02-09 02:03:06 +0000639
Luc Verhaegen73d21192009-12-23 00:54:26 +0000640 return ret;
Luc Verhaegen97866082008-02-09 02:03:06 +0000641}
642
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000643/*
644 * Suited for:
645 * - ASUS P5A
Luc Verhaegen6b141752007-05-20 16:16:13 +0000646 *
647 * This is rather nasty code, but there's no way to do this cleanly.
648 * We're basically talking to some unknown device on SMBus, my guess
649 * is that it is the Winbond W83781D that lives near the DIP BIOS.
650 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000651static int board_asus_p5a(void)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000652{
653 uint8_t tmp;
654 int i;
655
656#define ASUSP5A_LOOP 5000
657
Andriy Gapon65c1b862008-05-22 13:22:45 +0000658 OUTB(0x00, 0xE807);
659 OUTB(0xEF, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000660
Andriy Gapon65c1b862008-05-22 13:22:45 +0000661 OUTB(0xFF, 0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000662
663 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000664 OUTB(0xE1, 0xFF);
665 if (INB(0xE800) & 0x04)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000666 break;
667 }
668
669 if (i == ASUSP5A_LOOP) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000670 msg_perr("Unable to contact device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000671 return -1;
672 }
673
Andriy Gapon65c1b862008-05-22 13:22:45 +0000674 OUTB(0x20, 0xE801);
675 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000676
Andriy Gapon65c1b862008-05-22 13:22:45 +0000677 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000678
679 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000680 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000681 if (tmp & 0x70)
682 break;
683 }
684
685 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000686 msg_perr("Failed to read device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000687 return -1;
688 }
689
Andriy Gapon65c1b862008-05-22 13:22:45 +0000690 tmp = INB(0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000691 tmp &= ~0x02;
692
Andriy Gapon65c1b862008-05-22 13:22:45 +0000693 OUTB(0x00, 0xE807);
694 OUTB(0xEE, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000695
Andriy Gapon65c1b862008-05-22 13:22:45 +0000696 OUTB(tmp, 0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000697
Andriy Gapon65c1b862008-05-22 13:22:45 +0000698 OUTB(0xFF, 0xE800);
699 OUTB(0xE1, 0xFF);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000700
Andriy Gapon65c1b862008-05-22 13:22:45 +0000701 OUTB(0x20, 0xE801);
702 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000703
Andriy Gapon65c1b862008-05-22 13:22:45 +0000704 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000705
706 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000707 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000708 if (tmp & 0x70)
709 break;
710 }
711
712 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000713 msg_perr("Failed to write to device.\n");
Luc Verhaegen6b141752007-05-20 16:16:13 +0000714 return -1;
715 }
716
717 return 0;
718}
719
Luc Verhaegena7e30502009-12-09 11:39:02 +0000720/*
721 * Set GPIO lines in the Broadcom HT-1000 southbridge.
722 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000723 * It's not a Super I/O but it uses the same index/data port method.
Luc Verhaegena7e30502009-12-09 11:39:02 +0000724 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000725static int board_hp_dl145_g3_enable(void)
Luc Verhaegena7e30502009-12-09 11:39:02 +0000726{
727 /* GPIO 0 reg from PM regs */
728 /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
729 sio_mask(0xcd6, 0x44, 0x24, 0x24);
730
731 return 0;
732}
733
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +0000734/*
735 * Set GPIO lines in the Broadcom HT-1000 southbridge.
736 *
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000737 * It's not a Super I/O but it uses the same index/data port method.
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +0000738 */
739static int board_hp_dl165_g6_enable(void)
740{
741 /* Variant of DL145, with slightly different pin placement. */
742 sio_mask(0xcd6, 0x44, 0x80, 0x80); /* TBL# */
743 sio_mask(0xcd6, 0x46, 0x04, 0x04); /* WP# */
744
745 return 0;
746}
747
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000748static int board_ibm_x3455(void)
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000749{
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000750 /* Raise GPIO13. */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +0000751 sio_mask(0xcd6, 0x45, 0x20, 0x20);
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000752
753 return 0;
754}
755
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000756/*
757 * Suited for:
758 * - Shuttle FN25 (SN25P): AMD S939 + NVIDIA CK804 (nForce4)
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000759 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000760static int board_shuttle_fn25(void)
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000761{
762 struct pci_dev *dev;
763
764 dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA Bridge. */
765 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000766 msg_perr("\nERROR: NVIDIA nForce4 ISA bridge not found.\n");
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000767 return -1;
768 }
769
770 /* one of those bits seems to be connected to TBL#, but -ENOINFO. */
771 pci_write_byte(dev, 0x92, 0);
772
773 return 0;
774}
775
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000776/*
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000777 * Very similar to AMD 8111 IO Hub.
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000778 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000779static int nvidia_mcp_gpio_set(int gpio, int raise)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000780{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000781 struct pci_dev *dev;
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000782 uint16_t base;
Michael Karcher2ead2e22010-06-01 16:09:06 +0000783 uint16_t devclass;
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000784 uint8_t tmp;
785
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000786 if ((gpio < 0) || (gpio >= 0x40)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000787 msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000788 return -1;
789 }
790
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000791 /* First, check the ISA Bridge */
792 dev = pci_dev_find_vendorclass(0x10DE, 0x0601);
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000793 switch (dev->device_id) {
794 case 0x0030: /* CK804 */
795 case 0x0050: /* MCP04 */
796 case 0x0060: /* MCP2 */
Michael Karcher5f31ebe2010-06-12 23:07:26 +0000797 case 0x00E0: /* CK8 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000798 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +0000799 case 0x0260: /* MCP51 */
800 case 0x0364: /* MCP55 */
801 /* find SMBus controller on *this* southbridge */
802 /* The infamous Tyan S2915-E has two south bridges; they are
803 easily told apart from each other by the class of the
804 LPC bridge, but have the same SMBus bridge IDs */
805 if (dev->func != 0) {
806 msg_perr("MCP LPC bridge at unexpected function"
807 " number %d\n", dev->func);
808 return -1;
809 }
810
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +0000811#if PCI_LIB_VERSION >= 0x020200
Michael Karcher2ead2e22010-06-01 16:09:06 +0000812 dev = pci_get_dev(pacc, dev->domain, dev->bus, dev->dev, 1);
Carl-Daniel Hailfinger44cd9ab2010-07-17 22:28:05 +0000813#else
814 /* pciutils/libpci before version 2.2 is too old to support
815 * PCI domains. Such old machines usually don't have domains
816 * besides domain 0, so this is not a problem.
817 */
818 dev = pci_get_dev(pacc, dev->bus, dev->dev, 1);
819#endif
Michael Karcher2ead2e22010-06-01 16:09:06 +0000820 if (!dev) {
821 msg_perr("MCP SMBus controller could not be found\n");
822 return -1;
823 }
824 devclass = pci_read_word(dev, PCI_CLASS_DEVICE);
825 if (devclass != 0x0C05) {
826 msg_perr("Unexpected device class %04x for SMBus"
827 " controller\n", devclass);
828 return -1;
829 }
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000830 break;
Michael Karcher2ead2e22010-06-01 16:09:06 +0000831 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000832 msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n");
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000833 return -1;
834 }
835
836 base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
837 base += 0xC0;
838
839 tmp = INB(base + gpio);
840 tmp &= ~0x0F; /* null lower nibble */
841 tmp |= 0x04; /* gpio -> output. */
842 if (raise)
843 tmp |= 0x01;
844 OUTB(tmp, base + gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000845
846 return 0;
847}
848
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000849/*
850 * Suited for:
Sean Nelson0a247512010-08-15 14:36:18 +0000851 * - ASUS A8N-LA (HP OEM "Nagami-GL8E"): NVIDIA MCP51
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000852 * - ASUS M2NBP-VM CSM: NVIDIA MCP51
Michael Karcherb2184c12010-03-07 16:42:55 +0000853 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000854static int nvidia_mcp_gpio0_raise(void)
Michael Karcherb2184c12010-03-07 16:42:55 +0000855{
856 return nvidia_mcp_gpio_set(0x00, 1);
857}
858
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000859/*
860 * Suited for:
861 * - abit KN8 Ultra: NVIDIA CK804
Sean Nelson92bc6bd2010-03-19 22:37:29 +0000862 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000863static int nvidia_mcp_gpio2_lower(void)
Sean Nelson92bc6bd2010-03-19 22:37:29 +0000864{
865 return nvidia_mcp_gpio_set(0x02, 0);
866}
867
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000868/*
869 * Suited for:
870 * - MSI K8N Neo4: NVIDIA CK804
871 * - MSI K8N GM2-L: NVIDIA MCP51
Luc Verhaegen6c5f7332009-12-23 03:01:36 +0000872 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000873static int nvidia_mcp_gpio2_raise(void)
Luc Verhaegen6c5f7332009-12-23 03:01:36 +0000874{
875 return nvidia_mcp_gpio_set(0x02, 1);
876}
877
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000878/*
879 * Suited for:
880 * - HP xw9400 (Tyan S2915-E OEM): Dual(!) NVIDIA MCP55
881 *
882 * Notes: a) There are two MCP55 chips, so also two SMBus bridges on that
883 * board. We can't tell the SMBus logical devices apart, but we
884 * can tell the LPC bridge functions apart.
885 * We need to choose the SMBus bridge next to the LPC bridge with
886 * ID 0x364 and the "LPC bridge" class.
887 * b) #TBL is hardwired on that board to a pull-down. It can be
888 * overridden by connecting the two solder points next to F2.
Michael Karcher2ead2e22010-06-01 16:09:06 +0000889 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000890static int nvidia_mcp_gpio5_raise(void)
Michael Karcher2ead2e22010-06-01 16:09:06 +0000891{
892 return nvidia_mcp_gpio_set(0x05, 1);
893}
894
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000895/*
896 * Suited for:
897 * - abit NF7-S: NVIDIA CK804
Michael Karcher8f10d242010-04-11 21:01:06 +0000898 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000899static int nvidia_mcp_gpio8_raise(void)
Michael Karcher8f10d242010-04-11 21:01:06 +0000900{
901 return nvidia_mcp_gpio_set(0x08, 1);
902}
903
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000904/*
905 * Suited for:
906 * - MSI K8N Neo2 Platinum: Socket 939 + nForce3 Ultra + CK8
Michael Karcher5f31ebe2010-06-12 23:07:26 +0000907 */
Michael Karcher51825082010-06-12 23:14:03 +0000908static int nvidia_mcp_gpio0c_raise(void)
Michael Karcher5f31ebe2010-06-12 23:07:26 +0000909{
910 return nvidia_mcp_gpio_set(0x0c, 1);
911}
912
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000913/*
914 * Suited for:
915 * - abit NF-M2 nView: Socket AM2 + NVIDIA MCP51
Michael Karcherefd8af32010-07-24 22:50:54 +0000916 */
917static int nvidia_mcp_gpio4_lower(void)
918{
919 return nvidia_mcp_gpio_set(0x04, 0);
920}
921
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000922/*
923 * Suited for:
924 * - ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000925 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000926static int nvidia_mcp_gpio10_raise(void)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000927{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000928 return nvidia_mcp_gpio_set(0x10, 1);
929}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000930
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000931/*
932 * Suited for:
933 * - GIGABYTE GA-K8N-SLI: AMD socket 939 + NVIDIA CK804 + ITE IT8712F
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000934 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000935static int nvidia_mcp_gpio21_raise(void)
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000936{
937 return nvidia_mcp_gpio_set(0x21, 0x01);
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000938}
939
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000940/*
941 * Suited for:
942 * - EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2
Luc Verhaegen2c04fab2009-10-05 18:46:35 +0000943 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000944static int nvidia_mcp_gpio31_raise(void)
Luc Verhaegen2c04fab2009-10-05 18:46:35 +0000945{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000946 return nvidia_mcp_gpio_set(0x31, 0x01);
Luc Verhaegen2c04fab2009-10-05 18:46:35 +0000947}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000948
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000949/*
950 * Suited for:
951 * - Artec Group DBE61 and DBE62
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000952 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +0000953static int board_artecgroup_dbe6x(void)
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000954{
955#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000956#define DBE6x_PRI_BOOT_LOC_SHIFT 2
957#define DBE6x_BOOT_OP_LATCHED_SHIFT 8
958#define DBE6x_SEC_BOOT_LOC_SHIFT 10
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000959#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
960#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
961#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000962#define DBE6x_BOOT_LOC_FLASH 2
963#define DBE6x_BOOT_LOC_FWHUB 3
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000964
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000965 msr_t msr;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000966 unsigned long boot_loc;
967
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000968 /* Geode only has a single core */
969 if (setup_cpu_msr(0))
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000970 return -1;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000971
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000972 msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000973
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000974 if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) ==
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000975 (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
976 boot_loc = DBE6x_BOOT_LOC_FWHUB;
977 else
978 boot_loc = DBE6x_BOOT_LOC_FLASH;
979
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000980 msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
981 msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
Uwe Hermann394131e2008-10-18 21:14:13 +0000982 (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000983
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000984 wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000985
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000986 cleanup_cpu_msr();
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000987
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000988 return 0;
989}
990
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000991/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000992 * Helper function to raise/drop a given gpo line on Intel PIIX4{,E,M}.
Luc Verhaegenf5226912009-12-14 10:41:58 +0000993 */
994static int intel_piix4_gpo_set(unsigned int gpo, int raise)
995{
Michael Karcher01f6d7d2010-02-24 00:00:21 +0000996 unsigned int gpo_byte, gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +0000997 struct pci_dev *dev;
998 uint32_t tmp, base;
999
1000 dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */
1001 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001002 msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001003 return -1;
1004 }
1005
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001006 /* Sanity check. */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001007 if (gpo > 30) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001008 msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001009 return -1;
1010 }
1011
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001012 /* These are dual function pins which are most likely in use already. */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001013 if (((gpo >= 1) && (gpo <= 7)) ||
1014 ((gpo >= 9) && (gpo <= 21)) || (gpo == 29)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001015 msg_perr("\nERROR: Unsupported PIIX4 GPO%d.\n", gpo);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001016 return -1;
1017 }
1018
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001019 /* Dual function that need special enable. */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001020 if ((gpo >= 22) && (gpo <= 26)) {
1021 tmp = pci_read_long(dev, 0xB0); /* GENCFG */
1022 switch (gpo) {
1023 case 22: /* XBUS: XDIR#/GPO22 */
1024 case 23: /* XBUS: XOE#/GPO23 */
1025 tmp |= 1 << 28;
1026 break;
1027 case 24: /* RTCSS#/GPO24 */
1028 tmp |= 1 << 29;
1029 break;
1030 case 25: /* RTCALE/GPO25 */
1031 tmp |= 1 << 30;
1032 break;
1033 case 26: /* KBCSS#/GPO26 */
1034 tmp |= 1 << 31;
1035 break;
1036 }
1037 pci_write_long(dev, 0xB0, tmp);
1038 }
1039
1040 /* GPO {0,8,27,28,30} are always available. */
1041
1042 dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */
1043 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001044 msg_perr("\nERROR: Intel PIIX4 PM not found.\n");
Luc Verhaegenf5226912009-12-14 10:41:58 +00001045 return -1;
1046 }
1047
1048 /* PM IO base */
1049 base = pci_read_long(dev, 0x40) & 0x0000FFC0;
1050
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001051 gpo_byte = gpo >> 3;
1052 gpo_bit = gpo & 7;
1053 tmp = INB(base + 0x34 + gpo_byte); /* GPO register */
Luc Verhaegenf5226912009-12-14 10:41:58 +00001054 if (raise)
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001055 tmp |= 0x01 << gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +00001056 else
Michael Karcher01f6d7d2010-02-24 00:00:21 +00001057 tmp &= ~(0x01 << gpo_bit);
1058 OUTB(tmp, base + 0x34 + gpo_byte);
Luc Verhaegenf5226912009-12-14 10:41:58 +00001059
1060 return 0;
1061}
1062
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001063/*
1064 * Suited for:
1065 * - EPoX EP-BX3
Luc Verhaegenf5226912009-12-14 10:41:58 +00001066 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001067static int board_epox_ep_bx3(void)
Luc Verhaegenf5226912009-12-14 10:41:58 +00001068{
1069 return intel_piix4_gpo_set(22, 1);
1070}
1071
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001072/*
1073 * Suited for:
1074 * - Intel SE440BX-2
Michael Karcher51cd0c92010-03-19 22:35:21 +00001075 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001076static int intel_piix4_gpo27_lower(void)
Michael Karcher51cd0c92010-03-19 22:35:21 +00001077{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001078 return intel_piix4_gpo_set(27, 0);
Michael Karcher51cd0c92010-03-19 22:35:21 +00001079}
1080
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001081/*
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001082 * Set a GPIO line on a given Intel ICH LPC controller.
Uwe Hermann93f66db2008-05-22 21:19:38 +00001083 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001084static int intel_ich_gpio_set(int gpio, int raise)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001085{
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001086 /* Table mapping the different Intel ICH LPC chipsets. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001087 static struct {
1088 uint16_t id;
1089 uint8_t base_reg;
1090 uint32_t bank0;
1091 uint32_t bank1;
1092 uint32_t bank2;
1093 } intel_ich_gpio_table[] = {
1094 {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */
1095 {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */
1096 {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */
1097 {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */
1098 {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */
1099 {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */
1100 {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */
1101 {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */
1102 {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */
1103 {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */
1104 {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */
1105 {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */
1106 {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */
1107 {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */
1108 {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */
1109 {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */
1110 {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */
1111 {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */
1112 {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */
1113 {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */
1114 {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */
1115 {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */
1116 {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */
1117 {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */
1118 {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */
1119 {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */
1120 {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */
1121 {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */
1122 {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */
1123 {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */
1124 {0, 0, 0, 0, 0} /* end marker */
1125 };
Uwe Hermann93f66db2008-05-22 21:19:38 +00001126
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001127 struct pci_dev *dev;
1128 uint16_t base;
1129 uint32_t tmp;
1130 int i, allowed;
1131
1132 /* First, look for a known LPC bridge */
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001133 for (dev = pacc->devices; dev; dev = dev->next) {
Carl-Daniel Hailfingerd175e062010-05-21 23:00:56 +00001134 uint16_t device_class;
1135 /* libpci before version 2.2.4 does not store class info. */
1136 device_class = pci_read_word(dev, PCI_CLASS_DEVICE);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001137 if ((dev->vendor_id == 0x8086) &&
Carl-Daniel Hailfingerd175e062010-05-21 23:00:56 +00001138 (device_class == 0x0601)) { /* ISA Bridge */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001139 /* Is this device in our list? */
1140 for (i = 0; intel_ich_gpio_table[i].id; i++)
1141 if (dev->device_id == intel_ich_gpio_table[i].id)
1142 break;
1143
1144 if (intel_ich_gpio_table[i].id)
1145 break;
1146 }
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +00001147 }
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001148
Uwe Hermann93f66db2008-05-22 21:19:38 +00001149 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001150 msg_perr("\nERROR: No Known Intel LPC Bridge found.\n");
Uwe Hermann93f66db2008-05-22 21:19:38 +00001151 return -1;
1152 }
1153
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001154 /*
1155 * According to the datasheets, all Intel ICHs have the GPIO bar 5:1
1156 * strapped to zero. From some mobile ICH9 version on, this becomes
1157 * 6:1. The mask below catches all.
1158 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001159 base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
Uwe Hermann93f66db2008-05-22 21:19:38 +00001160
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001161 /* Check whether the line is allowed. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001162 if (gpio < 32)
1163 allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01;
1164 else if (gpio < 64)
1165 allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01;
1166 else
1167 allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;
1168
1169 if (!allowed) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001170 msg_perr("\nERROR: This Intel LPC Bridge does not allow"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001171 " setting GPIO%02d\n", gpio);
1172 return -1;
1173 }
1174
Sean Nelson316a29f2010-05-07 20:09:04 +00001175 msg_pdbg("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n",
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001176 raise ? "Rais" : "Dropp", gpio);
1177
1178 if (gpio < 32) {
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001179 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001180 tmp = INL(base);
1181 /* ICH/ICH0 multiplexes 27/28 on the line set. */
1182 if ((gpio == 28) &&
1183 ((dev->device_id == 0x2410) || (dev->device_id == 0x2420)))
1184 tmp |= 1 << 27;
1185 else
1186 tmp |= 1 << gpio;
1187 OUTL(tmp, base);
1188
1189 /* As soon as we are talking to ICH8 and above, this register
1190 decides whether we can set the gpio or not. */
1191 if (dev->device_id > 0x2800) {
1192 tmp = INL(base);
1193 if (!(tmp & (1 << gpio))) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001194 msg_perr("\nERROR: This Intel LPC Bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001195 " does not allow setting GPIO%02d\n",
1196 gpio);
1197 return -1;
1198 }
1199 }
1200
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001201 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001202 tmp = INL(base + 0x04);
1203 tmp &= ~(1 << gpio);
1204 OUTL(tmp, base + 0x04);
1205
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001206 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001207 tmp = INL(base + 0x0C);
1208 if (raise)
1209 tmp |= 1 << gpio;
1210 else
1211 tmp &= ~(1 << gpio);
1212 OUTL(tmp, base + 0x0C);
1213 } else if (gpio < 64) {
1214 gpio -= 32;
1215
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001216 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001217 tmp = INL(base + 0x30);
1218 tmp |= 1 << gpio;
1219 OUTL(tmp, base + 0x30);
1220
1221 /* As soon as we are talking to ICH8 and above, this register
1222 decides whether we can set the gpio or not. */
1223 if (dev->device_id > 0x2800) {
1224 tmp = INL(base + 30);
1225 if (!(tmp & (1 << gpio))) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001226 msg_perr("\nERROR: This Intel LPC Bridge"
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001227 " does not allow setting GPIO%02d\n",
1228 gpio + 32);
1229 return -1;
1230 }
1231 }
1232
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001233 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001234 tmp = INL(base + 0x34);
1235 tmp &= ~(1 << gpio);
1236 OUTL(tmp, base + 0x34);
1237
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001238 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001239 tmp = INL(base + 0x38);
1240 if (raise)
1241 tmp |= 1 << gpio;
1242 else
1243 tmp &= ~(1 << gpio);
1244 OUTL(tmp, base + 0x38);
1245 } else {
1246 gpio -= 64;
1247
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001248 /* Set line to GPIO. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001249 tmp = INL(base + 0x40);
1250 tmp |= 1 << gpio;
1251 OUTL(tmp, base + 0x40);
1252
1253 tmp = INL(base + 40);
1254 if (!(tmp & (1 << gpio))) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001255 msg_perr("\nERROR: This Intel LPC Bridge does "
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001256 "not allow setting GPIO%02d\n", gpio + 64);
1257 return -1;
1258 }
1259
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001260 /* Set GPIO to OUTPUT. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001261 tmp = INL(base + 0x44);
1262 tmp &= ~(1 << gpio);
1263 OUTL(tmp, base + 0x44);
1264
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001265 /* Raise GPIO line. */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001266 tmp = INL(base + 0x48);
1267 if (raise)
1268 tmp |= 1 << gpio;
1269 else
1270 tmp &= ~(1 << gpio);
1271 OUTL(tmp, base + 0x48);
1272 }
Uwe Hermann93f66db2008-05-22 21:19:38 +00001273
1274 return 0;
1275}
1276
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001277/*
1278 * Suited for:
1279 * - abit IP35: Intel P35 + ICH9R
1280 * - abit IP35 Pro: Intel P35 + ICH9R
Uwe Hermann93f66db2008-05-22 21:19:38 +00001281 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001282static int intel_ich_gpio16_raise(void)
Uwe Hermann93f66db2008-05-22 21:19:38 +00001283{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001284 return intel_ich_gpio_set(16, 1);
Uwe Hermann93f66db2008-05-22 21:19:38 +00001285}
1286
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001287/*
1288 * Suited for:
1289 * - HP Puffer2-UL8E (ASUS PTGD-LA OEM): LGA775 + 915 + ICH6
Michael Karchere57957c2010-07-24 11:14:37 +00001290 */
1291static int intel_ich_gpio18_raise(void)
1292{
1293 return intel_ich_gpio_set(18, 1);
1294}
1295
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001296/*
1297 * Suited for:
1298 * - ASUS A8JM: Intel 945 + ICH7
James Lancaster998c9dc2010-03-19 22:39:24 +00001299 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001300static int intel_ich_gpio34_raise(void)
James Lancaster998c9dc2010-03-19 22:39:24 +00001301{
1302 return intel_ich_gpio_set(34, 1);
1303}
1304
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001305/*
1306 * Suited for:
1307 * - MSI MS-7046: LGA775 + 915P + ICH6
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001308 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001309static int intel_ich_gpio19_raise(void)
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001310{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001311 return intel_ich_gpio_set(19, 1);
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +00001312}
1313
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001314/*
Luc Verhaegen6c5d4cc2009-11-28 18:26:21 +00001315 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001316 * - ASUS P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2
1317 * - ASUS P4C800-E Deluxe: socket478 + 875P + ICH5
1318 * - ASUS P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R
1319 * - ASUS P5PE-VM: Intel LGA775 + 865G + ICH5
1320 * - Samsung Polaris 32: socket478 + 865P + ICH5
Peter Stuge09c13332009-02-02 22:55:26 +00001321 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001322static int intel_ich_gpio21_raise(void)
Peter Stuge09c13332009-02-02 22:55:26 +00001323{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001324 return intel_ich_gpio_set(21, 1);
Peter Stuge09c13332009-02-02 22:55:26 +00001325}
1326
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001327/*
Michael Karcher03b80e92010-03-07 16:32:32 +00001328 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001329 * - ASUS P4B266: socket478 + Intel 845D + ICH2
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001330 * - ASUS P4B533-E: socket478 + 845E + ICH4
1331 * - ASUS P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001332 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001333static int intel_ich_gpio22_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001334{
1335 return intel_ich_gpio_set(22, 1);
1336}
1337
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001338/*
1339 * Suited for:
1340 * - HP Vectra VL400: 815 + ICH + PC87360
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001341 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001342static int board_hp_vl400(void)
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001343{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001344 int ret;
1345 ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */
1346 if (!ret)
1347 ret = pc87360_gpio_set(0x09, 1); /* #WP ? */
1348 if (!ret)
1349 ret = pc87360_gpio_set(0x27, 1); /* #TBL */
1350 return ret;
Michael Karcher5fbd18d2010-02-27 18:35:54 +00001351}
1352
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001353/*
Luc Verhaegen1265d8d2009-11-28 18:16:31 +00001354 * Suited for:
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001355 * - Dell PowerEdge 1850: Intel PPGA604 + E7520 + ICH5R
1356 * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R
1357 * - ASRock 775i65G: Intel LGA 775 + 865G + ICH5
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001358 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001359static int intel_ich_gpio23_raise(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001360{
1361 return intel_ich_gpio_set(23, 1);
1362}
1363
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001364/*
1365 * Suited for:
1366 * - GIGABYTE GA-8IRML: Intel Socket478 + i845 + ICH2
Michael Karcherc7a1ffb2010-07-24 22:27:29 +00001367 */
1368static int intel_ich_gpio25_raise(void)
1369{
1370 return intel_ich_gpio_set(25, 1);
1371}
1372
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001373/*
1374 * Suited for:
1375 * - IBASE MB899: i945GM + ICH7
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001376 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001377static int intel_ich_gpio26_raise(void)
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001378{
1379 return intel_ich_gpio_set(26, 1);
1380}
1381
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001382/*
1383 * Suited for:
1384 * - P4SD-LA (HP OEM): i865 + ICH5
Michael Karcherc8613242010-08-13 12:49:01 +00001385 * - GIGABYTE GA-8PE667 Ultra 2: socket 478 + i845PE + ICH4
Michael Karcher87c90992010-07-24 11:03:48 +00001386 */
Idwer Vollering19dceac2010-07-24 18:47:45 +00001387static int intel_ich_gpio32_raise(void)
Michael Karcher87c90992010-07-24 11:03:48 +00001388{
1389 return intel_ich_gpio_set(32, 1);
1390}
1391
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001392/*
1393 * Suited for:
1394 * - Acorp 6A815EPD: socket 370 + intel 815 + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001395 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001396static int board_acorp_6a815epd(void)
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001397{
1398 int ret;
1399
1400 /* Lower Blocks Lock -- pin 7 of PLCC32 */
1401 ret = intel_ich_gpio_set(22, 1);
1402 if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */
1403 ret = intel_ich_gpio_set(23, 1);
1404
1405 return ret;
1406}
1407
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001408/*
1409 * Suited for:
1410 * - Kontron 986LCD-M: Socket478 + 915GM + ICH7R
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001411 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001412static int board_kontron_986lcd_m(void)
Stefan Reinauerac378972008-03-17 22:59:40 +00001413{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001414 int ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001415
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001416 ret = intel_ich_gpio_set(34, 1); /* #TBL */
1417 if (!ret)
1418 ret = intel_ich_gpio_set(35, 1); /* #WP */
Stefan Reinauerac378972008-03-17 22:59:40 +00001419
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001420 return ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001421}
1422
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001423/*
1424 * Suited for:
1425 * - Soyo SY-7VCA: Pro133A + VT82C686
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001426 */
Michael Karcher06477332010-03-19 22:49:09 +00001427static int via_apollo_gpo_set(int gpio, int raise)
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001428{
Michael Karcher06477332010-03-19 22:49:09 +00001429 struct pci_dev *dev;
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001430 uint32_t base;
Michael Karcher06477332010-03-19 22:49:09 +00001431 uint32_t tmp;
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001432
1433 /* VT82C686 Power management */
1434 dev = pci_dev_find(0x1106, 0x3057);
1435 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001436 msg_perr("\nERROR: VT82C686 PM device not found.\n");
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001437 return -1;
1438 }
1439
Sean Nelson316a29f2010-05-07 20:09:04 +00001440 msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n",
Michael Karcher06477332010-03-19 22:49:09 +00001441 raise ? "Rais" : "Dropp", gpio);
1442
1443 /* select GPO function on multiplexed pins */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001444 tmp = pci_read_byte(dev, 0x54);
Michael Karcher06477332010-03-19 22:49:09 +00001445 switch(gpio)
1446 {
1447 case 0:
1448 tmp &= ~0x03;
1449 break;
1450 case 1:
1451 tmp |= 0x04;
1452 break;
1453 case 2:
1454 tmp |= 0x08;
1455 break;
1456 case 3:
1457 tmp |= 0x10;
1458 break;
1459 }
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001460 pci_write_byte(dev, 0x54, tmp);
1461
1462 /* PM IO base */
1463 base = pci_read_long(dev, 0x48) & 0x0000FF00;
1464
1465 /* Drop GPO0 */
Michael Karcher06477332010-03-19 22:49:09 +00001466 tmp = INL(base + 0x4C);
1467 if (raise)
1468 tmp |= 1U << gpio;
1469 else
1470 tmp &= ~(1U << gpio);
1471 OUTL(tmp, base + 0x4C);
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001472
1473 return 0;
1474}
1475
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001476/*
1477 * Suited for:
1478 * - abit VT6X4: Pro133x + VT82C686A
Michael Karcher187a46a2010-03-19 22:30:49 +00001479 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001480static int via_apollo_gpo4_lower(void)
Michael Karcher187a46a2010-03-19 22:30:49 +00001481{
1482 return via_apollo_gpo_set(4, 0);
1483}
1484
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001485/*
1486 * Suited for:
1487 * - Soyo SY-7VCA: Pro133A + VT82C686
Michael Karcher06477332010-03-19 22:49:09 +00001488 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001489static int via_apollo_gpo0_lower(void)
Michael Karcher06477332010-03-19 22:49:09 +00001490{
1491 return via_apollo_gpo_set(0, 0);
1492}
1493
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001494/*
Michael Karcher9f9e6132010-01-09 17:36:06 +00001495 * Enable some GPIO pin on SiS southbridge.
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001496 *
1497 * Suited for:
1498 * - MSI 651M-L: SiS651 / SiS962
Michael Karcher9f9e6132010-01-09 17:36:06 +00001499 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001500static int board_msi_651ml(void)
Michael Karcher9f9e6132010-01-09 17:36:06 +00001501{
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001502 struct pci_dev *dev;
Uwe Hermann43959702010-03-13 17:28:29 +00001503 uint16_t base, temp;
Michael Karcher9f9e6132010-01-09 17:36:06 +00001504
1505 dev = pci_dev_find(0x1039, 0x0962);
1506 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001507 msg_perr("Expected south bridge not found\n");
Michael Karcher9f9e6132010-01-09 17:36:06 +00001508 return 1;
1509 }
1510
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001511 /* Registers 68 and 64 seem like bitmaps. */
Michael Karcher9f9e6132010-01-09 17:36:06 +00001512 base = pci_read_word(dev, 0x74);
1513 temp = INW(base + 0x68);
1514 temp &= ~(1 << 0); /* Make pin output? */
Michael Karcher0435dfd2010-01-09 23:31:13 +00001515 OUTW(temp, base + 0x68);
Michael Karcher9f9e6132010-01-09 17:36:06 +00001516
1517 temp = INW(base + 0x64);
1518 temp |= (1 << 0); /* Raise output? */
1519 OUTW(temp, base + 0x64);
1520
1521 w836xx_memw_enable(0x2E);
1522
1523 return 0;
1524}
1525
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001526/*
Michael Gold6d52e472009-06-19 13:00:24 +00001527 * Find the runtime registers of an SMSC Super I/O, after verifying its
1528 * chip ID.
1529 *
1530 * Returns the base port of the runtime register block, or 0 on error.
1531 */
1532static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
1533 uint8_t logical_device)
1534{
1535 uint16_t rt_port = 0;
1536
1537 /* Verify the chip ID. */
Uwe Hermann1432a602009-06-28 23:26:37 +00001538 OUTB(0x55, sio_port); /* Enable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00001539 if (sio_read(sio_port, 0x20) != chip_id) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001540 msg_perr("\nERROR: SMSC Super I/O not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00001541 goto out;
1542 }
1543
1544 /* If the runtime block is active, get its address. */
1545 sio_write(sio_port, 0x07, logical_device);
1546 if (sio_read(sio_port, 0x30) & 1) {
1547 rt_port = (sio_read(sio_port, 0x60) << 8)
1548 | sio_read(sio_port, 0x61);
1549 }
1550
1551 if (rt_port == 0) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001552 msg_perr("\nERROR: "
Michael Gold6d52e472009-06-19 13:00:24 +00001553 "Super I/O runtime interface not available.\n");
1554 }
1555out:
Uwe Hermann1432a602009-06-28 23:26:37 +00001556 OUTB(0xaa, sio_port); /* Disable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00001557 return rt_port;
1558}
1559
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001560/*
1561 * Disable write protection on the Mitac 6513WU. WP# on the FWH is
Michael Gold6d52e472009-06-19 13:00:24 +00001562 * connected to GP30 on the Super I/O, and TBL# is always high.
1563 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001564static int board_mitac_6513wu(void)
Michael Gold6d52e472009-06-19 13:00:24 +00001565{
1566 struct pci_dev *dev;
1567 uint16_t rt_port;
1568 uint8_t val;
1569
1570 dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */
1571 if (!dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001572 msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00001573 return -1;
1574 }
1575
Uwe Hermann1432a602009-06-28 23:26:37 +00001576 rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa);
Michael Gold6d52e472009-06-19 13:00:24 +00001577 if (rt_port == 0)
1578 return -1;
1579
1580 /* Configure the GPIO pin. */
1581 val = INB(rt_port + 0x33); /* GP30 config */
Uwe Hermann1432a602009-06-28 23:26:37 +00001582 val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */
Michael Gold6d52e472009-06-19 13:00:24 +00001583 OUTB(val, rt_port + 0x33);
1584
1585 /* Disable write protection. */
1586 val = INB(rt_port + 0x4d); /* GP3 values */
Uwe Hermann1432a602009-06-28 23:26:37 +00001587 val |= 0x01; /* Set GP30 high. */
Michael Gold6d52e472009-06-19 13:00:24 +00001588 OUTB(val, rt_port + 0x4d);
1589
1590 return 0;
1591}
1592
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001593/*
1594 * Suited for:
1595 * - ASUS A7V8X: VIA KT400 + VT8235 + IT8703F
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001596 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001597static int board_asus_a7v8x(void)
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001598{
1599 uint16_t id, base;
1600 uint8_t tmp;
1601
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001602 /* Find the IT8703F. */
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001603 w836xx_ext_enter(0x2E);
1604 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
1605 w836xx_ext_leave(0x2E);
1606
1607 if (id != 0x8701) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001608 msg_perr("\nERROR: IT8703F Super I/O not found.\n");
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001609 return -1;
1610 }
1611
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001612 /* Get the GP567 I/O base. */
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001613 w836xx_ext_enter(0x2E);
1614 sio_write(0x2E, 0x07, 0x0C);
1615 base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
1616 w836xx_ext_leave(0x2E);
1617
1618 if (!base) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001619 msg_perr("\nERROR: Failed to read IT8703F Super I/O GPIO"
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001620 " Base.\n");
1621 return -1;
1622 }
1623
1624 /* Raise GP51. */
1625 tmp = INB(base);
1626 tmp |= 0x02;
1627 OUTB(tmp, base);
1628
1629 return 0;
1630}
1631
Luc Verhaegen72272912009-09-01 21:22:23 +00001632/*
1633 * General routine for raising/dropping GPIO lines on the ITE IT8712F.
1634 * There is only some limited checking on the port numbers.
1635 */
Uwe Hermann43959702010-03-13 17:28:29 +00001636static int it8712f_gpio_set(unsigned int line, int raise)
Luc Verhaegen72272912009-09-01 21:22:23 +00001637{
1638 unsigned int port;
1639 uint16_t id, base;
1640 uint8_t tmp;
1641
1642 port = line / 10;
1643 port--;
1644 line %= 10;
1645
1646 /* Check line */
1647 if ((port > 4) || /* also catches unsigned -1 */
1648 ((port < 4) && (line > 7)) || ((port == 4) && (line > 5))) {
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001649 msg_perr("\nERROR: Unsupported IT8712F GPIO line %02d.\n", line);
Luc Verhaegen72272912009-09-01 21:22:23 +00001650 return -1;
1651 }
1652
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001653 /* Find the IT8712F. */
Luc Verhaegen72272912009-09-01 21:22:23 +00001654 enter_conf_mode_ite(0x2E);
1655 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
1656 exit_conf_mode_ite(0x2E);
1657
1658 if (id != 0x8712) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001659 msg_perr("\nERROR: IT8712F Super I/O not found.\n");
Luc Verhaegen72272912009-09-01 21:22:23 +00001660 return -1;
1661 }
1662
1663 /* Get the GPIO base */
1664 enter_conf_mode_ite(0x2E);
1665 sio_write(0x2E, 0x07, 0x07);
1666 base = (sio_read(0x2E, 0x62) << 8) | sio_read(0x2E, 0x63);
1667 exit_conf_mode_ite(0x2E);
1668
1669 if (!base) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001670 msg_perr("\nERROR: Failed to read IT8712F Super I/O GPIO"
Luc Verhaegen72272912009-09-01 21:22:23 +00001671 " Base.\n");
1672 return -1;
1673 }
1674
1675 /* set GPIO. */
1676 tmp = INB(base + port);
1677 if (raise)
1678 tmp |= 1 << line;
1679 else
1680 tmp &= ~(1 << line);
1681 OUTB(tmp, base + port);
1682
1683 return 0;
1684}
1685
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001686/*
Russ Dillbd622d12010-03-09 16:57:06 +00001687 * Suited for:
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001688 * - ASUS A7V600-X: VIA KT600 + VT8237 + IT8712F
1689 * - ASUS A7V8X-X: VIA KT400 + VT8235 + IT8712F
Luc Verhaegen72272912009-09-01 21:22:23 +00001690 */
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001691static int it8712f_gpio3_1_raise(void)
Luc Verhaegen72272912009-09-01 21:22:23 +00001692{
1693 return it8712f_gpio_set(32, 1);
1694}
1695
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001696#endif
1697
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001698/*
Uwe Hermannd0e347d2009-10-06 13:00:00 +00001699 * Below is the list of boards which need a special "board enable" code in
1700 * flashrom before their ROM chip can be accessed/written to.
1701 *
1702 * NOTE: Please add boards that _don't_ need such enables or don't work yet
1703 * to the respective tables in print.c. Thanks!
1704 *
Uwe Hermannffec5f32007-08-23 16:08:21 +00001705 * We use 2 sets of IDs here, you're free to choose which is which. This
1706 * is to provide a very high degree of certainty when matching a board on
1707 * the basis of subsystem/card IDs. As not every vendor handles
1708 * subsystem/card IDs in a sane manner.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001709 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00001710 * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00001711 * NULLed if they don't identify the board fully and if you can't use DMI.
1712 * But please take care to provide an as complete set of pci ids as possible;
1713 * autodetection is the preferred behaviour and we would like to make sure that
1714 * matches are unique.
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001715 *
Michael Karcher6701ee82010-01-20 14:14:11 +00001716 * If PCI IDs are not sufficient for board matching, the match can be further
1717 * constrained by a string that has to be present in the DMI database for
Uwe Hermann4e3d0b32010-03-25 23:18:41 +00001718 * the baseboard or the system entry. The pattern is matched by case sensitive
Michael Karcher6701ee82010-01-20 14:14:11 +00001719 * substring match, unless it is anchored to the beginning (with a ^ in front)
1720 * or the end (with a $ at the end). Both anchors may be specified at the
1721 * same time to match the full field.
1722 *
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00001723 * When a board is matched through DMI, the first and second main PCI IDs
1724 * and the first subsystem PCI ID have to match as well. If you specify the
1725 * first subsystem ID as 0x0:0x0, the DMI matching code expects that the
1726 * subsystem ID of that device is indeed zero.
1727 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00001728 * The coreboot ids are used two fold. When running with a coreboot firmware,
1729 * the ids uniquely matches the coreboot board identification string. When a
1730 * legacy bios is installed and when autodetection is not possible, these ids
1731 * can be used to identify the board through the -m command line argument.
1732 *
1733 * When a board is identified through its coreboot ids (in both cases), the
1734 * main pci ids are still required to match, as a safeguard.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001735 */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001736
Uwe Hermanndeeebe22009-05-08 16:23:34 +00001737/* Please keep this list alphabetically ordered by vendor/board name. */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00001738const struct board_pciid_enable board_pciid_enables[] = {
Uwe Hermann5ab88892009-06-21 20:50:22 +00001739
Michael Karcher0bdc0922010-02-28 01:33:48 +00001740 /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001741#if defined(__i386__) || defined(__x86_64__)
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001742 {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise},
1743 {0x8086, 0x24d3, 0x147b, 0x1014, 0x8086, 0x2578, 0x147b, 0x1014, NULL, NULL, NULL, "abit", "IC7", 0, NT, intel_ich_gpio23_raise},
1744 {0x8086, 0x2930, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "abit", "IP35", 0, OK, intel_ich_gpio16_raise},
1745 {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise},
1746 {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, "abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower},
1747 {0x10de, 0x01e0, 0x147b, 0x1c00, 0x10de, 0x0060, 0x147B, 0x1c00, NULL, NULL, NULL, "abit", "NF7-S", 0, OK, nvidia_mcp_gpio8_raise},
1748 {0x10de, 0x02f0, 0x147b, 0x1c26, 0x10de, 0x0240, 0x10de, 0x0222, NULL, NULL, NULL, "abit", "NF-M2 nView", 0, NT, nvidia_mcp_gpio4_lower},
1749 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "abit", "VT6X4", 0, OK, via_apollo_gpo4_lower},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001750 {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001751 {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e},
Peter Lemenkov4073c092010-05-26 22:29:51 +00001752 {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A Pro", 0, OK, w836xx_memw_enable_2e},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001753 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x},
1754 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x},
Peter Lemenkoveb75ced2010-05-26 22:26:44 +00001755 {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise},
Joshua Roys7507de42010-08-08 16:05:23 +00001756 {0x8086, 0x2570, 0x1849, 0x2570, 0x8086, 0x24d3, 0x1849, 0x24d0, NULL, NULL, NULL, "ASRock", "775i65G", 0, OK, intel_ich_gpio23_raise},
Russ Dillbd622d12010-03-09 16:57:06 +00001757 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise},
Peter Lemenkoveb75ced2010-05-26 22:26:44 +00001758 {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001759 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, board_asus_a7v8x},
Russ Dillbd622d12010-03-09 16:57:06 +00001760 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise},
James Lancaster998c9dc2010-03-19 22:39:24 +00001761 {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, "ASUS", "A8JM", 0, NT, intel_ich_gpio34_raise},
Sean Nelson0a247512010-08-15 14:36:18 +00001762 {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI2L", NULL, NULL, "ASUS", "A8N-LA (Nagami-GL8E)", 0, OK, nvidia_mcp_gpio0_raise},
Peter Lemenkoveb75ced2010-05-26 22:26:44 +00001763 {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N", 0, NT, board_shuttle_fn25},
Michael Karcher7af6cef2010-07-08 09:32:18 +00001764 {0x10de, 0x0264, 0x1043, 0x81bc, 0x10de, 0x02f0, 0x1043, 0x81cd, NULL, NULL, NULL, "ASUS", "A8N-VM CSM", 0, NT, w83627ehf_gpio24_raise_2e},
Michael Karcherb2184c12010-03-07 16:42:55 +00001765 {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001766 {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001767 {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise},
Peter Lemenkoveb75ced2010-05-26 22:26:44 +00001768 {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise},
Michael Karcher255a9e02010-03-19 22:52:00 +00001769 {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise},
Michael Karcher6499d5a2010-03-17 06:19:23 +00001770 {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001771 {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
Michael Karcher87c90992010-07-24 11:03:48 +00001772 {0x8086, 0x2570, 0x1043, 0x80A5, 0x105A, 0x24D3, 0x1043, 0x80A6, NULL, NULL, NULL, "ASUS", "P4SD-LA", 0, NT, intel_ich_gpio32_raise},
David Borgb6417a62010-08-02 08:29:34 +00001773 {0x1039, 0x0661, 0x1043, 0x8113, 0x1039, 0x5513, 0x1043, 0x8087, NULL, NULL, NULL, "ASUS", "P4S800-MX", 512, OK, w836xx_memw_enable_2e},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001774 {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a},
1775 {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise},
Michael Karcher72eeab52010-07-24 10:41:42 +00001776 {0x8086, 0x24dd, 0x1043, 0x80a6, 0x8086, 0x2570, 0x1043, 0x8157, NULL, NULL, NULL, "ASUS", "P5PE-VM", 0, OK, intel_ich_gpio21_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001777 {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise},
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +00001778 {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, NULL},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001779 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e},
1780 {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise},
1781 {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", "EPoX", "EP-BX3", 0, OK, board_epox_ep_bx3},
Peter Lemenkoveb75ced2010-05-26 22:26:44 +00001782 {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL},
Uwe Hermann51afebb2010-08-01 00:13:49 +00001783 {0x8086, 0x244b, 0x8086, 0x2442, 0x8086, 0x2445, 0x1458, 0xa002, NULL, NULL, NULL, "GIGABYTE", "GA-8IRML", 0, OK, intel_ich_gpio25_raise},
Michael Karcherc8613242010-08-13 12:49:01 +00001784 {0x8086, 0x24c3, 0x1458, 0x24c2, 0x8086, 0x24cd, 0x1458, 0x5004, NULL, NULL, NULL, "GIGABYTE", "GA-8PE667 Ultra 2", 0, OK, intel_ich_gpio32_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001785 {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise},
Arne Georg Gleditschb0bd3862010-07-01 11:16:28 +00001786 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1678, 0x103c, 0x703e, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable},
1787 {0x1166, 0x0223, 0x103c, 0x320d, 0x14e4, 0x1648, 0x103c, 0x310f, NULL, "hp", "dl165_g6", "HP", "DL165 G6", 0, OK, board_hp_dl165_g6_enable},
Michael Karchere57957c2010-07-24 11:14:37 +00001788 {0x8086, 0x2580, 0x103c, 0x2a08, 0x8086, 0x2640, 0x103c, 0x2a0a, NULL, NULL, NULL, "HP", "Puffer2-UL8E", 0, OK, intel_ich_gpio18_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001789 {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400},
Michael Karcher03b80e92010-03-07 16:32:32 +00001790 {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise},
Michael Karcher2ead2e22010-06-01 16:09:06 +00001791 {0x10de, 0x0369, 0x103c, 0x12fe, 0x10de, 0x0364, 0x103c, 0x12fe, NULL, NULL, NULL, "HP", "xw9400", 0, OK, nvidia_mcp_gpio5_raise},
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001792 {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", "IBASE", "MB899", 0, OK, intel_ich_gpio26_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001793 {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455},
1794 {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi},
Michael Karcher51cd0c92010-03-19 22:35:21 +00001795 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001796 {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e},
James Lancaster998c9dc2010-03-19 22:39:24 +00001797 {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001798 {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, "Mitac", "6513WU", 0, OK, board_mitac_6513wu},
Peter Lemenkoveb75ced2010-05-26 22:26:44 +00001799 {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise},
Joshua Roysf280a382010-08-07 21:49:11 +00001800 {0x8086, 0x2560, 0x1462, 0x5770, 0x8086, 0x2562, 0x1462, 0x5778, NULL, NULL, NULL, "MSI", "MS-6577", 0, OK, w83627hf_gpio25_raise_2e},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001801 {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v},
Michael Karcherbcd80cd2010-06-27 15:07:49 +00001802 {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio44_raise_2e},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001803 {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v},
1804 {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml},
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001805 {0x10DE, 0x00E0, 0x1462, 0x0250, 0x10DE, 0x00E1, 0x1462, 0x0250, NULL, NULL, NULL, "MSI", "MS-7025 (K8N Neo2 Platinum)", 0, OK, nvidia_mcp_gpio0c_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001806 {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise},
Mattias Mattssone295eee2010-08-15 10:21:29 +00001807 {0x1106, 0x3149, 0x1462, 0x7061, 0x1106, 0x3227, 0, 0, NULL, NULL, NULL, "MSI", "MS-7061 (KM4M-V/KM4AM-V)", 0, OK, w836xx_memw_enable_2e},
Michael Karcherbcd80cd2010-06-27 15:07:49 +00001808 {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio44_raise_4e},
Michael Karcher5fdf2702010-03-07 16:52:59 +00001809 {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise},
Michael Karcherb3fe2fc2010-05-24 16:03:57 +00001810 {0x1011, 0x0019, 0xaa55, 0xaa55, 0x8086, 0x7190, 0, 0, NULL, NULL, NULL, "Nokia", "IP530", 0, OK, fdc37b787_gpio50_raise_3f0},
Michael Karcher3b112522010-07-24 22:36:01 +00001811 {0x8086, 0x24d3, 0x144d, 0xb025, 0x8086, 0x1050, 0x144d, 0xb025, NULL, NULL, NULL, "Samsung", "Polaris 32", 0, OK, intel_ich_gpio21_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001812 {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e},
Carl-Daniel Hailfinger76d4b372010-07-10 16:56:32 +00001813 {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, NULL},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001814 {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25},
Michael Karcher06477332010-03-19 22:49:09 +00001815 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001816 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, OK, NULL},
Daniel Brandt4ad4c742010-03-21 13:36:20 +00001817 {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e},
Peter Lemenkoveb75ced2010-05-26 22:26:44 +00001818 {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e},
Michael Karcherbcd25562010-06-12 17:27:44 +00001819 {0x1106, 0x0259, 0x1106, 0xAA07, 0x1106, 0x3227, 0x1106, 0xAA07, NULL, NULL, NULL, "VIA", "EPIA EK", 0, NT, via_vt823x_gpio9_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001820 {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise},
1821 {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise},
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001822#endif
Michael Karcher0bdc0922010-02-28 01:33:48 +00001823 { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001824};
1825
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001826/*
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00001827 * Match boards on coreboot table gathered vendor and part name.
Uwe Hermannffec5f32007-08-23 16:08:21 +00001828 * Require main PCI IDs to match too as extra safety.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001829 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00001830static const struct board_pciid_enable *board_match_coreboot_name(const char *vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00001831 const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001832{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00001833 const struct board_pciid_enable *board = board_pciid_enables;
1834 const struct board_pciid_enable *partmatch = NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001835
Uwe Hermanna93045c2009-05-09 00:47:04 +00001836 for (; board->vendor_name; board++) {
Uwe Hermann394131e2008-10-18 21:14:13 +00001837 if (vendor && (!board->lb_vendor
1838 || strcasecmp(board->lb_vendor, vendor)))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001839 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001840
Peter Stuge0b9c5f32008-07-02 00:47:30 +00001841 if (!board->lb_part || strcasecmp(board->lb_part, part))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001842 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001843
Uwe Hermanna7e05482007-05-09 10:17:44 +00001844 if (!pci_dev_find(board->first_vendor, board->first_device))
1845 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001846
Uwe Hermanna7e05482007-05-09 10:17:44 +00001847 if (board->second_vendor &&
Uwe Hermann394131e2008-10-18 21:14:13 +00001848 !pci_dev_find(board->second_vendor, board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001849 continue;
Peter Stuge6b53fed2008-01-27 16:21:21 +00001850
1851 if (vendor)
1852 return board;
1853
1854 if (partmatch) {
1855 /* a second entry has a matching part name */
Sean Nelson316a29f2010-05-07 20:09:04 +00001856 msg_pinfo("AMBIGUOUS BOARD NAME: %s\n", part);
1857 msg_pinfo("At least vendors '%s' and '%s' match.\n",
Uwe Hermann394131e2008-10-18 21:14:13 +00001858 partmatch->lb_vendor, board->lb_vendor);
Sean Nelson316a29f2010-05-07 20:09:04 +00001859 msg_perr("Please use the full -m vendor:part syntax.\n");
Peter Stuge6b53fed2008-01-27 16:21:21 +00001860 return NULL;
1861 }
1862 partmatch = board;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001863 }
Uwe Hermann372eeb52007-12-04 21:49:06 +00001864
Peter Stuge6b53fed2008-01-27 16:21:21 +00001865 if (partmatch)
1866 return partmatch;
1867
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00001868 if (!partvendor_from_cbtable) {
1869 /* Only warn if the mainboard type was not gathered from the
1870 * coreboot table. If it was, the coreboot implementor is
1871 * expected to fix flashrom, too.
1872 */
Sean Nelson316a29f2010-05-07 20:09:04 +00001873 msg_perr("\nUnknown vendor:board from -m option: %s:%s\n\n",
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00001874 vendor, part);
1875 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00001876 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001877}
1878
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001879/*
Uwe Hermannffec5f32007-08-23 16:08:21 +00001880 * Match boards on PCI IDs and subsystem IDs.
1881 * Second set of IDs can be main only or missing completely.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001882 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00001883const static struct board_pciid_enable *board_match_pci_card_ids(void)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001884{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00001885 const struct board_pciid_enable *board = board_pciid_enables;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001886
Uwe Hermanna93045c2009-05-09 00:47:04 +00001887 for (; board->vendor_name; board++) {
Michael Karcher2eab70d2010-02-04 10:58:50 +00001888 if ((!board->first_card_vendor || !board->first_card_device) &&
1889 !board->dmi_pattern)
Uwe Hermanna7e05482007-05-09 10:17:44 +00001890 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001891
Uwe Hermanna7e05482007-05-09 10:17:44 +00001892 if (!pci_card_find(board->first_vendor, board->first_device,
Uwe Hermann394131e2008-10-18 21:14:13 +00001893 board->first_card_vendor,
1894 board->first_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001895 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001896
Uwe Hermanna7e05482007-05-09 10:17:44 +00001897 if (board->second_vendor) {
1898 if (board->second_card_vendor) {
1899 if (!pci_card_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00001900 board->second_device,
1901 board->second_card_vendor,
1902 board->second_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001903 continue;
1904 } else {
1905 if (!pci_dev_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00001906 board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001907 continue;
1908 }
1909 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001910
Michael Karcher6701ee82010-01-20 14:14:11 +00001911 if (board->dmi_pattern) {
1912 if (!has_dmi_support) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001913 msg_perr("WARNING: Can't autodetect %s %s,"
Michael Karcher6701ee82010-01-20 14:14:11 +00001914 " DMI info unavailable.\n",
1915 board->vendor_name, board->board_name);
1916 continue;
1917 } else {
1918 if (!dmi_match(board->dmi_pattern))
1919 continue;
1920 }
1921 }
1922
Uwe Hermanna7e05482007-05-09 10:17:44 +00001923 return board;
1924 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001925
Uwe Hermanna7e05482007-05-09 10:17:44 +00001926 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001927}
1928
Uwe Hermann372eeb52007-12-04 21:49:06 +00001929int board_flash_enable(const char *vendor, const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001930{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +00001931 const struct board_pciid_enable *board = NULL;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001932 int ret = 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001933
Peter Stuge6b53fed2008-01-27 16:21:21 +00001934 if (part)
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00001935 board = board_match_coreboot_name(vendor, part);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001936
Uwe Hermanna7e05482007-05-09 10:17:44 +00001937 if (!board)
1938 board = board_match_pci_card_ids();
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001939
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001940 if (board && board->status == NT) {
1941 if (!force_boardenable) {
1942 msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n"
1943 "code has not been tested, and thus will not not be executed by default.\n"
1944 "Depending on your hardware environment, erasing, writing or even probing\n"
1945 "can fail without running the board specific code.\n\n"
1946 "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n"
1947 "\"internal programmer\") for details.\n",
1948 board->vendor_name, board->board_name);
1949 board = NULL;
1950 } else {
1951 msg_pinfo("NOTE: Running an untested board enable procedure.\n"
1952 "Please report success/failure to flashrom@flashrom.org.\n");
Uwe Hermann43959702010-03-13 17:28:29 +00001953 }
Michael Karcher7f0c3ec2010-03-07 22:29:28 +00001954 }
1955
Uwe Hermanna7e05482007-05-09 10:17:44 +00001956 if (board) {
Luc Verhaegen93938c32010-01-20 14:45:03 +00001957 if (board->max_rom_decode_parallel)
1958 max_rom_decode.parallel =
1959 board->max_rom_decode_parallel * 1024;
1960
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00001961 if (board->enable != NULL) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001962 msg_pinfo("Disabling flash write protection for "
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001963 "board \"%s %s\"... ", board->vendor_name,
1964 board->board_name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001965
Uwe Hermann36dec8b2010-06-07 19:06:26 +00001966 ret = board->enable();
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00001967 if (ret)
Sean Nelson316a29f2010-05-07 20:09:04 +00001968 msg_pinfo("FAILED!\n");
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00001969 else
Sean Nelson316a29f2010-05-07 20:09:04 +00001970 msg_pinfo("OK.\n");
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00001971 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00001972 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001973
Uwe Hermanna7e05482007-05-09 10:17:44 +00001974 return ret;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001975}