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review.sourcearcade.org / libgfxinit / 88badbe832a3279ec85b7859e3de132788c0962f / . / common / hw-gfx-gma-registers.ads
blob: ac0f023ff58fbccf7b056b3e46169006f392d94c [file] [log] [blame]
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1--
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]2-- Copyright (C) 2015-2017 secunet Security Networks AG
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +0200[diff] [blame]6-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]8--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
15with System;
16with HW.GFX.GMA;
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]17with HW.GFX.GMA.Config;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]18
19private package HW.GFX.GMA.Registers
20with
21 Abstract_State =>
22 ((Address_State with Part_Of => GMA.State),
23 (Register_State with External, Part_Of => GMA.Device_State),
24 (GTT_State with External, Part_Of => GMA.Device_State)),
25 Initializes => Address_State
26is
Nico Huber0b2329a2018-06-09 21:14:27 +0200[diff] [blame]27
28 MMIO_GTT_32_Size : constant := 16#20_0000#;
29 MMIO_GTT_32_Offset : constant := 16#20_0000#;
30
31 -- Limit Broadwell+ to 4MiB to have a stable
32 -- interface (i.e. same number of entries):
33 MMIO_GTT_64_Size : constant := 16#40_0000#;
34 MMIO_GTT_64_Offset : constant := 16#80_0000#;
35
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]36 type Registers_Invalid_Index is
37 (Invalid_Register, -- Allow a placeholder when access is not acceptable
38
39 RCS_RING_BUFFER_TAIL,
40 RCS_RING_BUFFER_HEAD,
41 RCS_RING_BUFFER_STRT,
42 RCS_RING_BUFFER_CTL,
43 QUIRK_02084,
44 QUIRK_02090,
45 HWSTAM,
46 MI_MODE,
47 INSTPM,
48 GT_MODE,
49 CACHE_MODE_0,
50 CTX_SIZE,
51 PP_DCLV_HIGH,
52 PP_DCLV_LOW,
53 GFX_MODE,
54 ARB_MODE,
55 HWS_PGA,
56 GAM_ECOCHK,
Arthur Heymans229ed1c2018-03-28 16:45:43 +0200[diff] [blame]57 GMCH_GMBUS0,
58 GMCH_GMBUS1,
59 GMCH_GMBUS2,
60 GMCH_GMBUS3,
61 GMCH_GMBUS4,
62 GMCH_GMBUS5,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]63 GMCH_DPLL_A,
64 GMCH_DPLL_B,
65 GMCH_FPA0,
66 GMCH_FPA1,
67 GMCH_FPB0,
68 GMCH_FPB1,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]69 MBCTL,
70 UCGCTL1,
71 UCGCTL2,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]72 GMCH_CLKCFG,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]73 VCS_RING_BUFFER_TAIL,
74 VCS_RING_BUFFER_HEAD,
75 VCS_RING_BUFFER_STRT,
76 VCS_RING_BUFFER_CTL,
77 SLEEP_PSMI_CONTROL,
78 VCS_HWSTAM,
79 VCS_PP_DCLV_HIGH,
80 VCS_PP_DCLV_LOW,
81 GAC_ECO_BITS,
82 BCS_RING_BUFFER_TAIL,
83 BCS_RING_BUFFER_HEAD,
84 BCS_RING_BUFFER_STRT,
85 BCS_RING_BUFFER_CTL,
86 BCS_HWSTAM,
87 BCS_PP_DCLV_HIGH,
88 BCS_PP_DCLV_LOW,
89 GAB_CTL_REG,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]90 CPU_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]91 FUSE_STATUS,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]92 ILK_DISPLAY_CHICKEN2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]93 DSPCLK_GATE_D,
94 FBA_CFB_BASE,
95 FBC_CTL,
96 IPS_CTL,
97 DEISR,
98 DEIMR,
99 DEIIR,
100 DEIER,
101 GTISR,
102 GTIMR,
103 GTIIR,
104 GTIER,
105 IIR,
106 HOTPLUG_CTL,
107 ARB_CTL,
108 DBUF_CTL,
109 WM_PIPE_A,
110 WM_PIPE_B,
111 WM1_LP_ILK,
112 WM2_LP_ILK,
113 WM3_LP_ILK,
114 WM_PIPE_C,
115 WM_LINETIME_A,
116 WM_LINETIME_B,
117 WM_LINETIME_C,
118 PWR_WELL_CTL_BIOS,
119 PWR_WELL_CTL_DRIVER,
120 PWR_WELL_CTL_KVMR,
121 PWR_WELL_CTL_DEBUG,
122 PWR_WELL_CTL5,
123 PWR_WELL_CTL6,
124 CDCLK_CTL,
125 LCPLL1_CTL,
126 LCPLL2_CTL,
127 SPLL_CTL,
128 WRPLL_CTL_1,
129 WRPLL_CTL_2,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]130 BXT_DE_PLL_ENABLE,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]131 BXT_PORT_PLL_ENABLE_A,
132 BXT_PORT_PLL_ENABLE_B,
133 BXT_PORT_PLL_ENABLE_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]134 PORT_CLK_SEL_DDIA,
135 PORT_CLK_SEL_DDIB,
136 PORT_CLK_SEL_DDIC,
137 PORT_CLK_SEL_DDID,
138 PORT_CLK_SEL_DDIE,
139 TRANSA_CLK_SEL,
140 TRANSB_CLK_SEL,
141 TRANSC_CLK_SEL,
142 NDE_RSTWRN_OPT,
143 BLC_PWM_CPU_CTL2,
144 BLC_PWM_CPU_CTL,
145 HTOTAL_A,
146 HBLANK_A,
147 HSYNC_A,
148 VTOTAL_A,
149 VBLANK_A,
150 VSYNC_A,
151 PIPEASRC,
152 PIPE_VSYNCSHIFT_A,
153 PIPEA_DATA_M1,
154 PIPEA_DATA_N1,
155 PIPEA_LINK_M1,
156 PIPEA_LINK_N1,
157 FDI_TX_CTL_A,
158 PIPEA_DDI_FUNC_CTL,
159 PIPEA_MSA_MISC,
160 SRD_CTL_A,
161 SRD_STATUS_A,
162 HTOTAL_B,
163 HBLANK_B,
164 HSYNC_B,
165 VTOTAL_B,
166 VBLANK_B,
167 VSYNC_B,
168 PIPEBSRC,
169 PIPE_VSYNCSHIFT_B,
170 PIPEB_DATA_M1,
171 PIPEB_DATA_N1,
172 PIPEB_LINK_M1,
173 PIPEB_LINK_N1,
174 FDI_TX_CTL_B,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]175 PORT_HOTPLUG_EN,
176 PORT_HOTPLUG_STAT,
177 GMCH_SDVOB,
178 GMCH_SDVOC,
179 GMCH_LVDS,
Arthur Heymanse87d0d12018-03-28 17:02:49 +0200[diff] [blame]180 GMCH_PP_STATUS,
181 GMCH_PP_CONTROL,
182 GMCH_PP_ON_DELAYS,
183 GMCH_PP_OFF_DELAYS,
184 GMCH_PP_DIVISOR,
Arthur Heymansd5198442018-03-28 17:05:12 +0200[diff] [blame]185 GMCH_PFIT_CONTROL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]186 PIPEB_DDI_FUNC_CTL,
187 PIPEB_MSA_MISC,
188 SRD_CTL_B,
189 SRD_STATUS_B,
190 HTOTAL_C,
191 HBLANK_C,
192 HSYNC_C,
193 VTOTAL_C,
194 VBLANK_C,
195 VSYNC_C,
196 PIPECSRC,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]197 G4X_AUD_VID_DID,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]198 PIPE_VSYNCSHIFT_C,
199 PIPEC_DATA_M1,
200 PIPEC_DATA_N1,
201 PIPEC_LINK_M1,
202 PIPEC_LINK_N1,
203 FDI_TX_CTL_C,
204 PIPEC_DDI_FUNC_CTL,
205 PIPEC_MSA_MISC,
206 SRD_CTL_C,
207 SRD_STATUS_C,
208 DDI_BUF_CTL_A,
209 DDI_AUX_CTL_A,
210 DDI_AUX_DATA_A_1,
211 DDI_AUX_DATA_A_2,
212 DDI_AUX_DATA_A_3,
213 DDI_AUX_DATA_A_4,
214 DDI_AUX_DATA_A_5,
215 DDI_AUX_MUTEX_A,
216 DP_TP_CTL_A,
217 DDI_BUF_CTL_B,
218 DDI_AUX_CTL_B,
219 DDI_AUX_DATA_B_1,
220 DDI_AUX_DATA_B_2,
221 DDI_AUX_DATA_B_3,
222 DDI_AUX_DATA_B_4,
223 DDI_AUX_DATA_B_5,
224 DDI_AUX_MUTEX_B,
225 DP_TP_CTL_B,
226 DP_TP_STATUS_B,
227 DDI_BUF_CTL_C,
228 DDI_AUX_CTL_C,
229 DDI_AUX_DATA_C_1,
230 DDI_AUX_DATA_C_2,
231 DDI_AUX_DATA_C_3,
232 DDI_AUX_DATA_C_4,
233 DDI_AUX_DATA_C_5,
234 DDI_AUX_MUTEX_C,
235 DP_TP_CTL_C,
236 DP_TP_STATUS_C,
237 DDI_BUF_CTL_D,
238 DDI_AUX_CTL_D,
239 DDI_AUX_DATA_D_1,
240 DDI_AUX_DATA_D_2,
241 DDI_AUX_DATA_D_3,
242 DDI_AUX_DATA_D_4,
243 DDI_AUX_DATA_D_5,
244 DDI_AUX_MUTEX_D,
245 DP_TP_CTL_D,
246 DP_TP_STATUS_D,
247 DDI_BUF_CTL_E,
248 DP_TP_CTL_E,
249 DP_TP_STATUS_E,
250 SRD_CTL,
251 SRD_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]252 BXT_PHY_CTL_A,
253 BXT_PHY_CTL_B,
254 BXT_PHY_CTL_C,
255 BXT_PHY_CTL_FAM_EDP,
256 BXT_PHY_CTL_FAM_DDI,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]257 DDI_BUF_TRANS_A_S0T1,
258 DDI_BUF_TRANS_A_S0T2,
259 DDI_BUF_TRANS_A_S1T1,
260 DDI_BUF_TRANS_A_S1T2,
261 DDI_BUF_TRANS_A_S2T1,
262 DDI_BUF_TRANS_A_S2T2,
263 DDI_BUF_TRANS_A_S3T1,
264 DDI_BUF_TRANS_A_S3T2,
265 DDI_BUF_TRANS_A_S4T1,
266 DDI_BUF_TRANS_A_S4T2,
267 DDI_BUF_TRANS_A_S5T1,
268 DDI_BUF_TRANS_A_S5T2,
269 DDI_BUF_TRANS_A_S6T1,
270 DDI_BUF_TRANS_A_S6T2,
271 DDI_BUF_TRANS_A_S7T1,
272 DDI_BUF_TRANS_A_S7T2,
273 DDI_BUF_TRANS_A_S8T1,
274 DDI_BUF_TRANS_A_S8T2,
275 DDI_BUF_TRANS_A_S9T1,
276 DDI_BUF_TRANS_A_S9T2,
277 DDI_BUF_TRANS_B_S0T1,
278 DDI_BUF_TRANS_B_S0T2,
279 DDI_BUF_TRANS_B_S1T1,
280 DDI_BUF_TRANS_B_S1T2,
281 DDI_BUF_TRANS_B_S2T1,
282 DDI_BUF_TRANS_B_S2T2,
283 DDI_BUF_TRANS_B_S3T1,
284 DDI_BUF_TRANS_B_S3T2,
285 DDI_BUF_TRANS_B_S4T1,
286 DDI_BUF_TRANS_B_S4T2,
287 DDI_BUF_TRANS_B_S5T1,
288 DDI_BUF_TRANS_B_S5T2,
289 DDI_BUF_TRANS_B_S6T1,
290 DDI_BUF_TRANS_B_S6T2,
291 DDI_BUF_TRANS_B_S7T1,
292 DDI_BUF_TRANS_B_S7T2,
293 DDI_BUF_TRANS_B_S8T1,
294 DDI_BUF_TRANS_B_S8T2,
295 DDI_BUF_TRANS_B_S9T1,
296 DDI_BUF_TRANS_B_S9T2,
297 DDI_BUF_TRANS_C_S0T1,
298 DDI_BUF_TRANS_C_S0T2,
299 DDI_BUF_TRANS_C_S1T1,
300 DDI_BUF_TRANS_C_S1T2,
301 DDI_BUF_TRANS_C_S2T1,
302 DDI_BUF_TRANS_C_S2T2,
303 DDI_BUF_TRANS_C_S3T1,
304 DDI_BUF_TRANS_C_S3T2,
305 DDI_BUF_TRANS_C_S4T1,
306 DDI_BUF_TRANS_C_S4T2,
307 DDI_BUF_TRANS_C_S5T1,
308 DDI_BUF_TRANS_C_S5T2,
309 DDI_BUF_TRANS_C_S6T1,
310 DDI_BUF_TRANS_C_S6T2,
311 DDI_BUF_TRANS_C_S7T1,
312 DDI_BUF_TRANS_C_S7T2,
313 DDI_BUF_TRANS_C_S8T1,
314 DDI_BUF_TRANS_C_S8T2,
315 DDI_BUF_TRANS_C_S9T1,
316 DDI_BUF_TRANS_C_S9T2,
317 DDI_BUF_TRANS_D_S0T1,
318 DDI_BUF_TRANS_D_S0T2,
319 DDI_BUF_TRANS_D_S1T1,
320 DDI_BUF_TRANS_D_S1T2,
321 DDI_BUF_TRANS_D_S2T1,
322 DDI_BUF_TRANS_D_S2T2,
323 DDI_BUF_TRANS_D_S3T1,
324 DDI_BUF_TRANS_D_S3T2,
325 DDI_BUF_TRANS_D_S4T1,
326 DDI_BUF_TRANS_D_S4T2,
327 DDI_BUF_TRANS_D_S5T1,
328 DDI_BUF_TRANS_D_S5T2,
329 DDI_BUF_TRANS_D_S6T1,
330 DDI_BUF_TRANS_D_S6T2,
331 DDI_BUF_TRANS_D_S7T1,
332 DDI_BUF_TRANS_D_S7T2,
333 DDI_BUF_TRANS_D_S8T1,
334 DDI_BUF_TRANS_D_S8T2,
335 DDI_BUF_TRANS_D_S9T1,
336 DDI_BUF_TRANS_D_S9T2,
337 DDI_BUF_TRANS_E_S0T1,
338 DDI_BUF_TRANS_E_S0T2,
339 DDI_BUF_TRANS_E_S1T1,
340 DDI_BUF_TRANS_E_S1T2,
341 DDI_BUF_TRANS_E_S2T1,
342 DDI_BUF_TRANS_E_S2T2,
343 DDI_BUF_TRANS_E_S3T1,
344 DDI_BUF_TRANS_E_S3T2,
345 DDI_BUF_TRANS_E_S4T1,
346 DDI_BUF_TRANS_E_S4T2,
347 DDI_BUF_TRANS_E_S5T1,
348 DDI_BUF_TRANS_E_S5T2,
349 DDI_BUF_TRANS_E_S6T1,
350 DDI_BUF_TRANS_E_S6T2,
351 DDI_BUF_TRANS_E_S7T1,
352 DDI_BUF_TRANS_E_S7T2,
353 DDI_BUF_TRANS_E_S8T1,
354 DDI_BUF_TRANS_E_S8T2,
355 DDI_BUF_TRANS_E_S9T1,
356 DDI_BUF_TRANS_E_S9T2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]357 AUD_VID_DID,
358 PFA_WIN_POS,
359 PFA_WIN_SZ,
360 PFA_CTL_1,
361 PS_WIN_POS_1_A,
362 PS_WIN_SZ_1_A,
363 PS_CTRL_1_A,
364 PS_WIN_POS_2_A,
365 PS_WIN_SZ_2_A,
366 PS_CTRL_2_A,
367 PFB_WIN_POS,
368 PFB_WIN_SZ,
369 PFB_CTL_1,
370 PS_WIN_POS_1_B,
371 PS_WIN_SZ_1_B,
372 PS_CTRL_1_B,
373 PS_WIN_POS_2_B,
374 PS_WIN_SZ_2_B,
375 PS_CTRL_2_B,
376 PFC_WIN_POS,
377 PFC_WIN_SZ,
378 PFC_CTL_1,
379 PS_WIN_POS_1_C,
380 PS_WIN_SZ_1_C,
381 PS_CTRL_1_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]382 BXT_PORT_CL1CM_DW0_BC,
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]383 DISPIO_CR_TX_BMU_CR0,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]384 BXT_PORT_CL1CM_DW9_BC,
385 BXT_PORT_CL1CM_DW10_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]386 BXT_PORT_PLL_EBB_0_B,
387 BXT_PORT_PLL_EBB_4_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]388 DPLL1_CFGR1,
389 DPLL1_CFGR2,
390 DPLL2_CFGR1,
391 DPLL2_CFGR2,
392 DPLL3_CFGR1,
393 DPLL3_CFGR2,
394 DPLL_CTRL1,
395 DPLL_CTRL2,
396 DPLL_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]397 BXT_PORT_CL1CM_DW28_BC,
398 BXT_PORT_CL1CM_DW30_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]399 BXT_PORT_PLL_0_B,
400 BXT_PORT_PLL_1_B,
401 BXT_PORT_PLL_2_B,
402 BXT_PORT_PLL_3_B,
403 BXT_PORT_PLL_6_B,
404 BXT_PORT_PLL_8_B,
405 BXT_PORT_PLL_9_B,
406 BXT_PORT_PLL_10_B,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]407 BXT_PORT_REF_DW3_BC,
408 BXT_PORT_REF_DW6_BC,
409 BXT_PORT_REF_DW8_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]410 BXT_PORT_PLL_EBB_0_C,
411 BXT_PORT_PLL_EBB_4_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]412 BXT_PORT_CL2CM_DW6_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]413 BXT_PORT_PLL_0_C,
414 BXT_PORT_PLL_1_C,
415 BXT_PORT_PLL_2_C,
416 BXT_PORT_PLL_3_C,
417 BXT_PORT_PLL_6_C,
418 BXT_PORT_PLL_8_C,
419 BXT_PORT_PLL_9_C,
420 BXT_PORT_PLL_10_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]421 BXT_PORT_PCS_DW10_01_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]422 BXT_PORT_PCS_DW12_01_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]423 BXT_PORT_TX_DW2_LN0_B,
424 BXT_PORT_TX_DW3_LN0_B,
425 BXT_PORT_TX_DW4_LN0_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]426 BXT_PORT_TX_DW14_LN0_B,
427 BXT_PORT_TX_DW14_LN1_B,
428 BXT_PORT_TX_DW14_LN2_B,
429 BXT_PORT_TX_DW14_LN3_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]430 BXT_PORT_PCS_DW10_01_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]431 BXT_PORT_PCS_DW12_01_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]432 BXT_PORT_TX_DW2_LN0_C,
433 BXT_PORT_TX_DW3_LN0_C,
434 BXT_PORT_TX_DW4_LN0_C,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]435 BXT_PORT_TX_DW14_LN0_C,
436 BXT_PORT_TX_DW14_LN1_C,
437 BXT_PORT_TX_DW14_LN2_C,
438 BXT_PORT_TX_DW14_LN3_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]439 BXT_PORT_PCS_DW10_GRP_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]440 BXT_PORT_PCS_DW12_GRP_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]441 BXT_PORT_TX_DW2_GRP_B,
442 BXT_PORT_TX_DW3_GRP_B,
443 BXT_PORT_TX_DW4_GRP_B,
444 BXT_PORT_PCS_DW10_GRP_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]445 BXT_PORT_PCS_DW12_GRP_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]446 BXT_PORT_TX_DW2_GRP_C,
447 BXT_PORT_TX_DW3_GRP_C,
448 BXT_PORT_TX_DW4_GRP_C,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]449 BXT_DE_PLL_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]450 HTOTAL_EDP,
451 HBLANK_EDP,
452 HSYNC_EDP,
453 VTOTAL_EDP,
454 VBLANK_EDP,
455 VSYNC_EDP,
456 PIPE_EDP_DATA_M1,
457 PIPE_EDP_DATA_N1,
458 PIPE_EDP_LINK_M1,
459 PIPE_EDP_LINK_N1,
460 PIPE_EDP_DDI_FUNC_CTL,
461 PIPE_EDP_MSA_MISC,
462 SRD_CTL_EDP,
463 SRD_STATUS_EDP,
464 PIPE_SCANLINE_A,
465 PIPEACONF,
466 PIPEAMISC,
467 PIPE_FRMCNT_A,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]468 PIPEA_GMCH_DATA_M,
469 PIPEA_GMCH_DATA_N,
470 PIPEA_GMCH_LINK_M,
471 PIPEA_GMCH_LINK_N,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]472 CUR_CTL_A,
473 CUR_BASE_A,
474 CUR_POS_A,
475 CUR_FBC_CTL_A,
476 CUR_WM_A_0,
477 CUR_WM_A_1,
478 CUR_WM_A_2,
479 CUR_WM_A_3,
480 CUR_WM_A_4,
481 CUR_WM_A_5,
482 CUR_WM_A_6,
483 CUR_WM_A_7,
484 CUR_BUF_CFG_A,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]485 DSPACNTR,
486 DSPALINOFF,
487 DSPASTRIDE,
488 PLANE_POS_1_A,
489 PLANE_SIZE_1_A,
490 DSPASURF,
491 DSPATILEOFF,
492 PLANE_WM_1_A_0,
493 PLANE_WM_1_A_1,
494 PLANE_WM_1_A_2,
495 PLANE_WM_1_A_3,
496 PLANE_WM_1_A_4,
497 PLANE_WM_1_A_5,
498 PLANE_WM_1_A_6,
499 PLANE_WM_1_A_7,
500 PLANE_BUF_CFG_1_A,
501 SPACNTR,
502 PIPE_SCANLINE_B,
503 PIPEBCONF,
504 PIPEBMISC,
505 PIPE_FRMCNT_B,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]506 PIPEB_GMCH_DATA_M,
507 PIPEB_GMCH_DATA_N,
508 PIPEB_GMCH_LINK_M,
509 PIPEB_GMCH_LINK_N,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]510 CUR_CTL_B,
511 CUR_BASE_B,
512 CUR_POS_B,
513 CUR_FBC_CTL_B,
514 CUR_WM_B_0,
515 CUR_WM_B_1,
516 CUR_WM_B_2,
517 CUR_WM_B_3,
518 CUR_WM_B_4,
519 CUR_WM_B_5,
520 CUR_WM_B_6,
521 CUR_WM_B_7,
522 CUR_BUF_CFG_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]523 DSPBCNTR,
524 DSPBLINOFF,
525 DSPBSTRIDE,
526 PLANE_POS_1_B,
527 PLANE_SIZE_1_B,
528 DSPBSURF,
529 DSPBTILEOFF,
530 PLANE_WM_1_B_0,
531 PLANE_WM_1_B_1,
532 PLANE_WM_1_B_2,
533 PLANE_WM_1_B_3,
534 PLANE_WM_1_B_4,
535 PLANE_WM_1_B_5,
536 PLANE_WM_1_B_6,
537 PLANE_WM_1_B_7,
538 PLANE_BUF_CFG_1_B,
539 SPBCNTR,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]540 GMCH_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]541 PIPE_SCANLINE_C,
542 PIPECCONF,
543 PIPECMISC,
544 PIPE_FRMCNT_C,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]545 CUR_CTL_C,
546 CUR_BASE_C,
547 CUR_POS_C,
548 CUR_FBC_CTL_C,
549 CUR_WM_C_0,
550 CUR_WM_C_1,
551 CUR_WM_C_2,
552 CUR_WM_C_3,
553 CUR_WM_C_4,
554 CUR_WM_C_5,
555 CUR_WM_C_6,
556 CUR_WM_C_7,
557 CUR_BUF_CFG_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]558 DSPCCNTR,
559 DSPCLINOFF,
560 DSPCSTRIDE,
561 PLANE_POS_1_C,
562 PLANE_SIZE_1_C,
563 DSPCSURF,
564 DSPCTILEOFF,
565 PLANE_WM_1_C_0,
566 PLANE_WM_1_C_1,
567 PLANE_WM_1_C_2,
568 PLANE_WM_1_C_3,
569 PLANE_WM_1_C_4,
570 PLANE_WM_1_C_5,
571 PLANE_WM_1_C_6,
572 PLANE_WM_1_C_7,
573 PLANE_BUF_CFG_1_C,
574 SPCCNTR,
575 PIPE_EDP_CONF,
576 PCH_FDI_CHICKEN_B_C,
577 QUIRK_C2004,
578 SFUSE_STRAP,
579 PCH_DSPCLK_GATE_D,
580 SDEISR,
581 SDEIMR,
582 SDEIIR,
583 SDEIER,
584 SHOTPLUG_CTL,
585 PCH_GMBUS0,
586 PCH_GMBUS1,
587 PCH_GMBUS2,
588 PCH_GMBUS3,
589 PCH_GMBUS4,
590 PCH_GMBUS5,
591 SBI_ADDR,
592 SBI_DATA,
593 SBI_CTL_STAT,
594 PCH_DPLL_A,
595 PCH_DPLL_B,
596 PCH_PIXCLK_GATE,
597 PCH_FPA0,
598 PCH_FPA1,
599 PCH_FPB0,
600 PCH_FPB1,
601 PCH_DREF_CONTROL,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]602 PCH_RAWCLK_FREQ,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]603 PCH_DPLL_SEL,
604 PCH_PP_STATUS,
605 PCH_PP_CONTROL,
606 PCH_PP_ON_DELAYS,
607 PCH_PP_OFF_DELAYS,
608 PCH_PP_DIVISOR,
609 BLC_PWM_PCH_CTL1,
610 BLC_PWM_PCH_CTL2,
611 TRANS_HTOTAL_A,
612 TRANS_HBLANK_A,
613 TRANS_HSYNC_A,
614 TRANS_VTOTAL_A,
615 TRANS_VBLANK_A,
616 TRANS_VSYNC_A,
617 TRANS_VSYNCSHIFT_A,
618 TRANSA_DATA_M1,
619 TRANSA_DATA_N1,
620 TRANSA_DP_LINK_M1,
621 TRANSA_DP_LINK_N1,
622 TRANS_DP_CTL_A,
623 TRANS_HTOTAL_B,
624 TRANS_HBLANK_B,
625 TRANS_HSYNC_B,
626 TRANS_VTOTAL_B,
627 TRANS_VBLANK_B,
628 TRANS_VSYNC_B,
629 TRANS_VSYNCSHIFT_B,
630 TRANSB_DATA_M1,
631 TRANSB_DATA_N1,
632 TRANSB_DP_LINK_M1,
633 TRANSB_DP_LINK_N1,
634 PCH_ADPA,
635 PCH_HDMIB,
636 PCH_HDMIC,
637 PCH_HDMID,
638 PCH_LVDS,
639 TRANS_DP_CTL_B,
640 TRANS_HTOTAL_C,
641 TRANS_HBLANK_C,
642 TRANS_HSYNC_C,
643 TRANS_VTOTAL_C,
644 TRANS_VBLANK_C,
645 TRANS_VSYNC_C,
646 TRANS_VSYNCSHIFT_C,
647 TRANSC_DATA_M1,
648 TRANSC_DATA_N1,
649 TRANSC_DP_LINK_M1,
650 TRANSC_DP_LINK_N1,
651 TRANS_DP_CTL_C,
652 PCH_DP_B,
653 PCH_DP_AUX_CTL_B,
654 PCH_DP_AUX_DATA_B_1,
655 PCH_DP_AUX_DATA_B_2,
656 PCH_DP_AUX_DATA_B_3,
657 PCH_DP_AUX_DATA_B_4,
658 PCH_DP_AUX_DATA_B_5,
659 PCH_DP_C,
660 PCH_DP_AUX_CTL_C,
661 PCH_DP_AUX_DATA_C_1,
662 PCH_DP_AUX_DATA_C_2,
663 PCH_DP_AUX_DATA_C_3,
664 PCH_DP_AUX_DATA_C_4,
665 PCH_DP_AUX_DATA_C_5,
666 PCH_DP_D,
667 PCH_DP_AUX_CTL_D,
668 PCH_DP_AUX_DATA_D_1,
669 PCH_DP_AUX_DATA_D_2,
670 PCH_DP_AUX_DATA_D_3,
671 PCH_DP_AUX_DATA_D_4,
672 PCH_DP_AUX_DATA_D_5,
673 AUD_CONFIG_A,
674 PCH_AUD_VID_DID,
675 AUD_HDMIW_HDMIEDID_A,
676 AUD_CNTL_ST_A,
677 AUD_CNTRL_ST2,
678 AUD_CONFIG_B,
679 AUD_HDMIW_HDMIEDID_B,
680 AUD_CNTL_ST_B,
681 AUD_CONFIG_C,
682 AUD_HDMIW_HDMIEDID_C,
683 AUD_CNTL_ST_C,
684 TRANSACONF,
685 FDI_RXA_CTL,
686 FDI_RX_MISC_A,
687 FDI_RXA_IIR,
688 FDI_RXA_IMR,
689 FDI_RXA_TUSIZE1,
690 QUIRK_F0060,
691 TRANSA_CHICKEN2,
692 TRANSBCONF,
693 FDI_RXB_CTL,
694 FDI_RX_MISC_B,
695 FDI_RXB_IIR,
696 FDI_RXB_IMR,
697 FDI_RXB_TUSIZE1,
698 QUIRK_F1060,
699 TRANSB_CHICKEN2,
700 TRANSCCONF,
701 FDI_RXC_CTL,
702 FDI_RX_MISC_C,
703 FDI_RXC_IIR,
704 FDI_RXC_IMR,
705 FDI_RXC_TUSIZE1,
706 QUIRK_F2060,
707 TRANSC_CHICKEN2,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]708 BXT_P_CR_GT_DISP_PWRON,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]709 GT_MAILBOX,
710 GT_MAILBOX_DATA,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]711 GT_MAILBOX_DATA_1,
712 BXT_PORT_CL1CM_DW0_A,
713 BXT_PORT_CL1CM_DW9_A,
714 BXT_PORT_CL1CM_DW10_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]715 BXT_PORT_PLL_EBB_0_A,
716 BXT_PORT_PLL_EBB_4_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]717 BXT_PORT_CL1CM_DW28_A,
718 BXT_PORT_CL1CM_DW30_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]719 BXT_PORT_PLL_0_A,
720 BXT_PORT_PLL_1_A,
721 BXT_PORT_PLL_2_A,
722 BXT_PORT_PLL_3_A,
723 BXT_PORT_PLL_6_A,
724 BXT_PORT_PLL_8_A,
725 BXT_PORT_PLL_9_A,
726 BXT_PORT_PLL_10_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]727 BXT_PORT_REF_DW3_A,
728 BXT_PORT_REF_DW6_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]729 BXT_PORT_REF_DW8_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]730 BXT_PORT_PCS_DW10_01_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]731 BXT_PORT_PCS_DW12_01_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]732 BXT_PORT_TX_DW2_LN0_A,
733 BXT_PORT_TX_DW3_LN0_A,
734 BXT_PORT_TX_DW4_LN0_A,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]735 BXT_PORT_TX_DW14_LN0_A,
736 BXT_PORT_TX_DW14_LN1_A,
737 BXT_PORT_TX_DW14_LN2_A,
738 BXT_PORT_TX_DW14_LN3_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]739 BXT_PORT_PCS_DW10_GRP_A,
740 BXT_PORT_PCS_DW12_GRP_A,
741 BXT_PORT_TX_DW2_GRP_A,
742 BXT_PORT_TX_DW3_GRP_A,
743 BXT_PORT_TX_DW4_GRP_A);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]744
745 pragma Warnings
746 (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)",
747 Reason => "TODO: Should it matter?");
748 pragma Keep_Names (Registers_Invalid_Index);
749 pragma Warnings
750 (GNATprove, On, "pragma ""KEEP_NAMES"" ignored *(not yet supported)");
751
752 Register_Width : constant := 4;
753
754 for Registers_Invalid_Index use
755 (Invalid_Register => 0,
756
757 ---------------------------------------------------------------------------
758 -- Pipe A registers
759 ---------------------------------------------------------------------------
760
761 -- pipe timing registers
762
763 HTOTAL_A => 16#06_0000# / Register_Width,
764 HBLANK_A => 16#06_0004# / Register_Width,
765 HSYNC_A => 16#06_0008# / Register_Width,
766 VTOTAL_A => 16#06_000c# / Register_Width,
767 VBLANK_A => 16#06_0010# / Register_Width,
768 VSYNC_A => 16#06_0014# / Register_Width,
769 PIPEASRC => 16#06_001c# / Register_Width,
770 PIPEACONF => 16#07_0008# / Register_Width,
771 PIPEAMISC => 16#07_0030# / Register_Width,
772 TRANS_HTOTAL_A => 16#0e_0000# / Register_Width,
773 TRANS_HBLANK_A => 16#0e_0004# / Register_Width,
774 TRANS_HSYNC_A => 16#0e_0008# / Register_Width,
775 TRANS_VTOTAL_A => 16#0e_000c# / Register_Width,
776 TRANS_VBLANK_A => 16#0e_0010# / Register_Width,
777 TRANS_VSYNC_A => 16#0e_0014# / Register_Width,
778 TRANSA_DATA_M1 => 16#0e_0030# / Register_Width,
779 TRANSA_DATA_N1 => 16#0e_0034# / Register_Width,
780 TRANSA_DP_LINK_M1 => 16#0e_0040# / Register_Width,
781 TRANSA_DP_LINK_N1 => 16#0e_0044# / Register_Width,
782 PIPEA_DATA_M1 => 16#06_0030# / Register_Width,
783 PIPEA_DATA_N1 => 16#06_0034# / Register_Width,
784 PIPEA_LINK_M1 => 16#06_0040# / Register_Width,
785 PIPEA_LINK_N1 => 16#06_0044# / Register_Width,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]786 PIPEA_GMCH_DATA_M => 16#07_0050# / Register_Width,
787 PIPEA_GMCH_DATA_N => 16#07_0054# / Register_Width,
788 PIPEA_GMCH_LINK_M => 16#07_0060# / Register_Width,
789 PIPEA_GMCH_LINK_N => 16#07_0064# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]790 PIPEA_DDI_FUNC_CTL => 16#06_0400# / Register_Width,
791 PIPEA_MSA_MISC => 16#06_0410# / Register_Width,
792
793 -- PCH sideband interface registers
794 SBI_ADDR => 16#0c_6000# / Register_Width,
795 SBI_DATA => 16#0c_6004# / Register_Width,
796 SBI_CTL_STAT => 16#0c_6008# / Register_Width,
797
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]798 -- GMCH clock registers
799 GMCH_DPLL_A => 16#00_6014# / Register_Width,
800 GMCH_FPA0 => 16#00_6040# / Register_Width,
801 GMCH_FPA1 => 16#00_6044# / Register_Width,
802
803 -- PCH clock registers
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]804 PCH_DPLL_A => 16#0c_6014# / Register_Width,
805 PCH_PIXCLK_GATE => 16#0c_6020# / Register_Width,
806 PCH_FPA0 => 16#0c_6040# / Register_Width,
807 PCH_FPA1 => 16#0c_6044# / Register_Width,
808
809 -- panel fitter
810 PFA_CTL_1 => 16#06_8080# / Register_Width,
811 PFA_WIN_POS => 16#06_8070# / Register_Width,
812 PFA_WIN_SZ => 16#06_8074# / Register_Width,
813 PS_WIN_POS_1_A => 16#06_8170# / Register_Width,
814 PS_WIN_SZ_1_A => 16#06_8174# / Register_Width,
815 PS_CTRL_1_A => 16#06_8180# / Register_Width,
816 PS_WIN_POS_2_A => 16#06_8270# / Register_Width,
817 PS_WIN_SZ_2_A => 16#06_8274# / Register_Width,
818 PS_CTRL_2_A => 16#06_8280# / Register_Width,
819
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]820 -- cursor control
821 CUR_CTL_A => 16#07_0080# / Register_Width,
822 CUR_BASE_A => 16#07_0084# / Register_Width,
823 CUR_POS_A => 16#07_0088# / Register_Width,
824 CUR_FBC_CTL_A => 16#07_00a0# / Register_Width,
825
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]826 -- display control
827 DSPACNTR => 16#07_0180# / Register_Width,
828 DSPALINOFF => 16#07_0184# / Register_Width,
829 DSPASTRIDE => 16#07_0188# / Register_Width,
830 PLANE_POS_1_A => 16#07_018c# / Register_Width,
831 PLANE_SIZE_1_A => 16#07_0190# / Register_Width,
832 DSPASURF => 16#07_019c# / Register_Width,
833 DSPATILEOFF => 16#07_01a4# / Register_Width,
834
835 -- sprite control
836 SPACNTR => 16#07_0280# / Register_Width,
837
838 -- FDI and PCH transcoder control
839 FDI_TX_CTL_A => 16#06_0100# / Register_Width,
840 FDI_RXA_CTL => 16#0f_000c# / Register_Width,
841 FDI_RX_MISC_A => 16#0f_0010# / Register_Width,
842 FDI_RXA_IIR => 16#0f_0014# / Register_Width,
843 FDI_RXA_IMR => 16#0f_0018# / Register_Width,
844 FDI_RXA_TUSIZE1 => 16#0f_0030# / Register_Width,
845 TRANSACONF => 16#0f_0008# / Register_Width,
846 TRANSA_CHICKEN2 => 16#0f_0064# / Register_Width,
847
848 -- watermark registers
849 WM_LINETIME_A => 16#04_5270# / Register_Width,
850 PLANE_WM_1_A_0 => 16#07_0240# / Register_Width,
851 PLANE_WM_1_A_1 => 16#07_0244# / Register_Width,
852 PLANE_WM_1_A_2 => 16#07_0248# / Register_Width,
853 PLANE_WM_1_A_3 => 16#07_024c# / Register_Width,
854 PLANE_WM_1_A_4 => 16#07_0250# / Register_Width,
855 PLANE_WM_1_A_5 => 16#07_0254# / Register_Width,
856 PLANE_WM_1_A_6 => 16#07_0258# / Register_Width,
857 PLANE_WM_1_A_7 => 16#07_025c# / Register_Width,
858 PLANE_BUF_CFG_1_A => 16#07_027c# / Register_Width,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]859 CUR_WM_A_0 => 16#07_0140# / Register_Width,
860 CUR_WM_A_1 => 16#07_0144# / Register_Width,
861 CUR_WM_A_2 => 16#07_0148# / Register_Width,
862 CUR_WM_A_3 => 16#07_014c# / Register_Width,
863 CUR_WM_A_4 => 16#07_0150# / Register_Width,
864 CUR_WM_A_5 => 16#07_0154# / Register_Width,
865 CUR_WM_A_6 => 16#07_0158# / Register_Width,
866 CUR_WM_A_7 => 16#07_015c# / Register_Width,
867 CUR_BUF_CFG_A => 16#07_017c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]868
869 -- CPU transcoder clock select
870 TRANSA_CLK_SEL => 16#04_6140# / Register_Width,
871
872 ---------------------------------------------------------------------------
873 -- Pipe B registers
874 ---------------------------------------------------------------------------
875
876 -- pipe timing registers
877
878 HTOTAL_B => 16#06_1000# / Register_Width,
879 HBLANK_B => 16#06_1004# / Register_Width,
880 HSYNC_B => 16#06_1008# / Register_Width,
881 VTOTAL_B => 16#06_100c# / Register_Width,
882 VBLANK_B => 16#06_1010# / Register_Width,
883 VSYNC_B => 16#06_1014# / Register_Width,
884 PIPEBSRC => 16#06_101c# / Register_Width,
885 PIPEBCONF => 16#07_1008# / Register_Width,
886 PIPEBMISC => 16#07_1030# / Register_Width,
887 TRANS_HTOTAL_B => 16#0e_1000# / Register_Width,
888 TRANS_HBLANK_B => 16#0e_1004# / Register_Width,
889 TRANS_HSYNC_B => 16#0e_1008# / Register_Width,
890 TRANS_VTOTAL_B => 16#0e_100c# / Register_Width,
891 TRANS_VBLANK_B => 16#0e_1010# / Register_Width,
892 TRANS_VSYNC_B => 16#0e_1014# / Register_Width,
893 TRANSB_DATA_M1 => 16#0e_1030# / Register_Width,
894 TRANSB_DATA_N1 => 16#0e_1034# / Register_Width,
895 TRANSB_DP_LINK_M1 => 16#0e_1040# / Register_Width,
896 TRANSB_DP_LINK_N1 => 16#0e_1044# / Register_Width,
897 PIPEB_DATA_M1 => 16#06_1030# / Register_Width,
898 PIPEB_DATA_N1 => 16#06_1034# / Register_Width,
899 PIPEB_LINK_M1 => 16#06_1040# / Register_Width,
900 PIPEB_LINK_N1 => 16#06_1044# / Register_Width,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]901 PIPEB_GMCH_DATA_M => 16#07_1050# / Register_Width,
902 PIPEB_GMCH_DATA_N => 16#07_1054# / Register_Width,
903 PIPEB_GMCH_LINK_M => 16#07_1060# / Register_Width,
904 PIPEB_GMCH_LINK_N => 16#07_1064# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]905 PIPEB_DDI_FUNC_CTL => 16#06_1400# / Register_Width,
906 PIPEB_MSA_MISC => 16#06_1410# / Register_Width,
907
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]908 -- GMCH clock registers
909 GMCH_DPLL_B => 16#00_6018# / Register_Width,
910 GMCH_FPB0 => 16#00_6048# / Register_Width,
911 GMCH_FPB1 => 16#00_604c# / Register_Width,
912
913 -- PCH clock registers
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]914 PCH_DPLL_B => 16#0c_6018# / Register_Width,
915 PCH_FPB0 => 16#0c_6048# / Register_Width,
916 PCH_FPB1 => 16#0c_604c# / Register_Width,
917
918 -- panel fitter
919 PFB_CTL_1 => 16#06_8880# / Register_Width,
920 PFB_WIN_POS => 16#06_8870# / Register_Width,
921 PFB_WIN_SZ => 16#06_8874# / Register_Width,
922 PS_WIN_POS_1_B => 16#06_8970# / Register_Width,
923 PS_WIN_SZ_1_B => 16#06_8974# / Register_Width,
924 PS_CTRL_1_B => 16#06_8980# / Register_Width,
925 PS_WIN_POS_2_B => 16#06_8a70# / Register_Width,
926 PS_WIN_SZ_2_B => 16#06_8a74# / Register_Width,
927 PS_CTRL_2_B => 16#06_8a80# / Register_Width,
928
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]929 -- cursor control
930 CUR_CTL_B => 16#07_1080# / Register_Width,
931 CUR_BASE_B => 16#07_1084# / Register_Width,
932 CUR_POS_B => 16#07_1088# / Register_Width,
933 CUR_FBC_CTL_B => 16#07_10a0# / Register_Width,
934
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]935 -- display control
936 DSPBCNTR => 16#07_1180# / Register_Width,
937 DSPBLINOFF => 16#07_1184# / Register_Width,
938 DSPBSTRIDE => 16#07_1188# / Register_Width,
939 PLANE_POS_1_B => 16#07_118c# / Register_Width,
940 PLANE_SIZE_1_B => 16#07_1190# / Register_Width,
941 DSPBSURF => 16#07_119c# / Register_Width,
942 DSPBTILEOFF => 16#07_11a4# / Register_Width,
943
944 -- sprite control
945 SPBCNTR => 16#07_1280# / Register_Width,
946
947 -- FDI and PCH transcoder control
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]948 FDI_TX_CTL_B => 16#06_1100# / Register_Width, -- aliased by GMCH_ADPA
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]949 FDI_RXB_CTL => 16#0f_100c# / Register_Width,
950 FDI_RX_MISC_B => 16#0f_1010# / Register_Width,
951 FDI_RXB_IIR => 16#0f_1014# / Register_Width,
952 FDI_RXB_IMR => 16#0f_1018# / Register_Width,
953 FDI_RXB_TUSIZE1 => 16#0f_1030# / Register_Width,
954 TRANSBCONF => 16#0f_1008# / Register_Width,
955 TRANSB_CHICKEN2 => 16#0f_1064# / Register_Width,
956
957 -- watermark registers
958 WM_LINETIME_B => 16#04_5274# / Register_Width,
959 PLANE_WM_1_B_0 => 16#07_1240# / Register_Width,
960 PLANE_WM_1_B_1 => 16#07_1244# / Register_Width,
961 PLANE_WM_1_B_2 => 16#07_1248# / Register_Width,
962 PLANE_WM_1_B_3 => 16#07_124c# / Register_Width,
963 PLANE_WM_1_B_4 => 16#07_1250# / Register_Width,
964 PLANE_WM_1_B_5 => 16#07_1254# / Register_Width,
965 PLANE_WM_1_B_6 => 16#07_1258# / Register_Width,
966 PLANE_WM_1_B_7 => 16#07_125c# / Register_Width,
967 PLANE_BUF_CFG_1_B => 16#07_127c# / Register_Width,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]968 CUR_WM_B_0 => 16#07_1140# / Register_Width,
969 CUR_WM_B_1 => 16#07_1144# / Register_Width,
970 CUR_WM_B_2 => 16#07_1148# / Register_Width,
971 CUR_WM_B_3 => 16#07_114c# / Register_Width,
972 CUR_WM_B_4 => 16#07_1150# / Register_Width,
973 CUR_WM_B_5 => 16#07_1154# / Register_Width,
974 CUR_WM_B_6 => 16#07_1158# / Register_Width,
975 CUR_WM_B_7 => 16#07_115c# / Register_Width,
976 CUR_BUF_CFG_B => 16#07_117c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]977
978 -- CPU transcoder clock select
979 TRANSB_CLK_SEL => 16#04_6144# / Register_Width,
980
981 ---------------------------------------------------------------------------
982 -- Pipe C registers
983 ---------------------------------------------------------------------------
984
985 -- pipe timing registers
986
987 HTOTAL_C => 16#06_2000# / Register_Width,
988 HBLANK_C => 16#06_2004# / Register_Width,
989 HSYNC_C => 16#06_2008# / Register_Width,
990 VTOTAL_C => 16#06_200c# / Register_Width,
991 VBLANK_C => 16#06_2010# / Register_Width,
992 VSYNC_C => 16#06_2014# / Register_Width,
993 PIPECSRC => 16#06_201c# / Register_Width,
994 PIPECCONF => 16#07_2008# / Register_Width,
995 PIPECMISC => 16#07_2030# / Register_Width,
996 TRANS_HTOTAL_C => 16#0e_2000# / Register_Width,
997 TRANS_HBLANK_C => 16#0e_2004# / Register_Width,
998 TRANS_HSYNC_C => 16#0e_2008# / Register_Width,
999 TRANS_VTOTAL_C => 16#0e_200c# / Register_Width,
1000 TRANS_VBLANK_C => 16#0e_2010# / Register_Width,
1001 TRANS_VSYNC_C => 16#0e_2014# / Register_Width,
1002 TRANSC_DATA_M1 => 16#0e_2030# / Register_Width,
1003 TRANSC_DATA_N1 => 16#0e_2034# / Register_Width,
1004 TRANSC_DP_LINK_M1 => 16#0e_2040# / Register_Width,
1005 TRANSC_DP_LINK_N1 => 16#0e_2044# / Register_Width,
1006 PIPEC_DATA_M1 => 16#06_2030# / Register_Width,
1007 PIPEC_DATA_N1 => 16#06_2034# / Register_Width,
1008 PIPEC_LINK_M1 => 16#06_2040# / Register_Width,
1009 PIPEC_LINK_N1 => 16#06_2044# / Register_Width,
1010 PIPEC_DDI_FUNC_CTL => 16#06_2400# / Register_Width,
1011 PIPEC_MSA_MISC => 16#06_2410# / Register_Width,
1012
1013 -- panel fitter
1014 PFC_CTL_1 => 16#06_9080# / Register_Width,
1015 PFC_WIN_POS => 16#06_9070# / Register_Width,
1016 PFC_WIN_SZ => 16#06_9074# / Register_Width,
1017 PS_WIN_POS_1_C => 16#06_9170# / Register_Width,
1018 PS_WIN_SZ_1_C => 16#06_9174# / Register_Width,
1019 PS_CTRL_1_C => 16#06_9180# / Register_Width,
1020
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1021 -- cursor control
1022 CUR_CTL_C => 16#07_2080# / Register_Width,
1023 CUR_BASE_C => 16#07_2084# / Register_Width,
1024 CUR_POS_C => 16#07_2088# / Register_Width,
1025 CUR_FBC_CTL_C => 16#07_20a0# / Register_Width,
1026
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1027 -- display control
1028 DSPCCNTR => 16#07_2180# / Register_Width,
1029 DSPCLINOFF => 16#07_2184# / Register_Width,
1030 DSPCSTRIDE => 16#07_2188# / Register_Width,
1031 PLANE_POS_1_C => 16#07_218c# / Register_Width,
1032 PLANE_SIZE_1_C => 16#07_2190# / Register_Width,
1033 DSPCSURF => 16#07_219c# / Register_Width,
1034 DSPCTILEOFF => 16#07_21a4# / Register_Width,
1035
1036 -- sprite control
1037 SPCCNTR => 16#07_2280# / Register_Width,
1038
1039 -- PCH transcoder control
1040 FDI_TX_CTL_C => 16#06_2100# / Register_Width,
1041 FDI_RXC_CTL => 16#0f_200c# / Register_Width,
1042 FDI_RX_MISC_C => 16#0f_2010# / Register_Width,
1043 FDI_RXC_IIR => 16#0f_2014# / Register_Width,
1044 FDI_RXC_IMR => 16#0f_2018# / Register_Width,
1045 FDI_RXC_TUSIZE1 => 16#0f_2030# / Register_Width,
1046 TRANSCCONF => 16#0f_2008# / Register_Width,
1047 TRANSC_CHICKEN2 => 16#0f_2064# / Register_Width,
1048
1049 -- watermark registers
1050 WM_LINETIME_C => 16#04_5278# / Register_Width,
1051 PLANE_WM_1_C_0 => 16#07_2240# / Register_Width,
1052 PLANE_WM_1_C_1 => 16#07_2244# / Register_Width,
1053 PLANE_WM_1_C_2 => 16#07_2248# / Register_Width,
1054 PLANE_WM_1_C_3 => 16#07_224c# / Register_Width,
1055 PLANE_WM_1_C_4 => 16#07_2250# / Register_Width,
1056 PLANE_WM_1_C_5 => 16#07_2254# / Register_Width,
1057 PLANE_WM_1_C_6 => 16#07_2258# / Register_Width,
1058 PLANE_WM_1_C_7 => 16#07_225c# / Register_Width,
1059 PLANE_BUF_CFG_1_C => 16#07_227c# / Register_Width,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1060 CUR_WM_C_0 => 16#07_2140# / Register_Width,
1061 CUR_WM_C_1 => 16#07_2144# / Register_Width,
1062 CUR_WM_C_2 => 16#07_2148# / Register_Width,
1063 CUR_WM_C_3 => 16#07_214c# / Register_Width,
1064 CUR_WM_C_4 => 16#07_2150# / Register_Width,
1065 CUR_WM_C_5 => 16#07_2154# / Register_Width,
1066 CUR_WM_C_6 => 16#07_2158# / Register_Width,
1067 CUR_WM_C_7 => 16#07_215c# / Register_Width,
1068 CUR_BUF_CFG_C => 16#07_217c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1069
1070 -- CPU transcoder clock select
1071 TRANSC_CLK_SEL => 16#04_6148# / Register_Width,
1072
1073 ---------------------------------------------------------------------------
1074 -- Pipe EDP registers
1075 ---------------------------------------------------------------------------
1076
1077 -- pipe timing registers
1078
1079 HTOTAL_EDP => 16#06_f000# / Register_Width,
1080 HBLANK_EDP => 16#06_f004# / Register_Width,
1081 HSYNC_EDP => 16#06_f008# / Register_Width,
1082 VTOTAL_EDP => 16#06_f00c# / Register_Width,
1083 VBLANK_EDP => 16#06_f010# / Register_Width,
1084 VSYNC_EDP => 16#06_f014# / Register_Width,
1085 PIPE_EDP_CONF => 16#07_f008# / Register_Width,
1086 PIPE_EDP_DATA_M1 => 16#06_f030# / Register_Width,
1087 PIPE_EDP_DATA_N1 => 16#06_f034# / Register_Width,
1088 PIPE_EDP_LINK_M1 => 16#06_f040# / Register_Width,
1089 PIPE_EDP_LINK_N1 => 16#06_f044# / Register_Width,
1090 PIPE_EDP_DDI_FUNC_CTL => 16#06_f400# / Register_Width,
1091 PIPE_EDP_MSA_MISC => 16#06_f410# / Register_Width,
1092
1093 -- PSR registers
1094 SRD_CTL => 16#06_4800# / Register_Width,
1095 SRD_CTL_A => 16#06_0800# / Register_Width,
1096 SRD_CTL_B => 16#06_1800# / Register_Width,
1097 SRD_CTL_C => 16#06_2800# / Register_Width,
1098 SRD_CTL_EDP => 16#06_f800# / Register_Width,
1099 SRD_STATUS => 16#06_4840# / Register_Width,
1100 SRD_STATUS_A => 16#06_0840# / Register_Width,
1101 SRD_STATUS_B => 16#06_1840# / Register_Width,
1102 SRD_STATUS_C => 16#06_2840# / Register_Width,
1103 SRD_STATUS_EDP => 16#06_f840# / Register_Width,
1104
1105 -- DDI registers
1106 DDI_BUF_CTL_A => 16#06_4000# / Register_Width, -- aliased by DP_CTL_A
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1107 DDI_BUF_TRANS_A_S0T1 => 16#06_4e00# / Register_Width,
1108 DDI_BUF_TRANS_A_S0T2 => 16#06_4e04# / Register_Width,
1109 DDI_BUF_TRANS_A_S1T1 => 16#06_4e08# / Register_Width,
1110 DDI_BUF_TRANS_A_S1T2 => 16#06_4e0c# / Register_Width,
1111 DDI_BUF_TRANS_A_S2T1 => 16#06_4e10# / Register_Width,
1112 DDI_BUF_TRANS_A_S2T2 => 16#06_4e14# / Register_Width,
1113 DDI_BUF_TRANS_A_S3T1 => 16#06_4e18# / Register_Width,
1114 DDI_BUF_TRANS_A_S3T2 => 16#06_4e1c# / Register_Width,
1115 DDI_BUF_TRANS_A_S4T1 => 16#06_4e20# / Register_Width,
1116 DDI_BUF_TRANS_A_S4T2 => 16#06_4e24# / Register_Width,
1117 DDI_BUF_TRANS_A_S5T1 => 16#06_4e28# / Register_Width,
1118 DDI_BUF_TRANS_A_S5T2 => 16#06_4e2c# / Register_Width,
1119 DDI_BUF_TRANS_A_S6T1 => 16#06_4e30# / Register_Width,
1120 DDI_BUF_TRANS_A_S6T2 => 16#06_4e34# / Register_Width,
1121 DDI_BUF_TRANS_A_S7T1 => 16#06_4e38# / Register_Width,
1122 DDI_BUF_TRANS_A_S7T2 => 16#06_4e3c# / Register_Width,
1123 DDI_BUF_TRANS_A_S8T1 => 16#06_4e40# / Register_Width,
1124 DDI_BUF_TRANS_A_S8T2 => 16#06_4e44# / Register_Width,
1125 DDI_BUF_TRANS_A_S9T1 => 16#06_4e48# / Register_Width,
1126 DDI_BUF_TRANS_A_S9T2 => 16#06_4e4c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1127 DDI_AUX_CTL_A => 16#06_4010# / Register_Width, -- aliased by DP_AUX_CTL_A
1128 DDI_AUX_DATA_A_1 => 16#06_4014# / Register_Width, -- aliased by DP_AUX_DATA_A_1
1129 DDI_AUX_DATA_A_2 => 16#06_4018# / Register_Width, -- aliased by DP_AUX_DATA_A_2
1130 DDI_AUX_DATA_A_3 => 16#06_401c# / Register_Width, -- aliased by DP_AUX_DATA_A_3
1131 DDI_AUX_DATA_A_4 => 16#06_4020# / Register_Width, -- aliased by DP_AUX_DATA_A_4
1132 DDI_AUX_DATA_A_5 => 16#06_4024# / Register_Width, -- aliased by DP_AUX_DATA_A_5
1133 DDI_AUX_MUTEX_A => 16#06_402c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1134
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1135 DDI_BUF_CTL_B => 16#06_4100# / Register_Width, -- aliased by GMCH_DP_B
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1136 DDI_BUF_TRANS_B_S0T1 => 16#06_4e60# / Register_Width,
1137 DDI_BUF_TRANS_B_S0T2 => 16#06_4e64# / Register_Width,
1138 DDI_BUF_TRANS_B_S1T1 => 16#06_4e68# / Register_Width,
1139 DDI_BUF_TRANS_B_S1T2 => 16#06_4e6c# / Register_Width,
1140 DDI_BUF_TRANS_B_S2T1 => 16#06_4e70# / Register_Width,
1141 DDI_BUF_TRANS_B_S2T2 => 16#06_4e74# / Register_Width,
1142 DDI_BUF_TRANS_B_S3T1 => 16#06_4e78# / Register_Width,
1143 DDI_BUF_TRANS_B_S3T2 => 16#06_4e7c# / Register_Width,
1144 DDI_BUF_TRANS_B_S4T1 => 16#06_4e80# / Register_Width,
1145 DDI_BUF_TRANS_B_S4T2 => 16#06_4e84# / Register_Width,
1146 DDI_BUF_TRANS_B_S5T1 => 16#06_4e88# / Register_Width,
1147 DDI_BUF_TRANS_B_S5T2 => 16#06_4e8c# / Register_Width,
1148 DDI_BUF_TRANS_B_S6T1 => 16#06_4e90# / Register_Width,
1149 DDI_BUF_TRANS_B_S6T2 => 16#06_4e94# / Register_Width,
1150 DDI_BUF_TRANS_B_S7T1 => 16#06_4e98# / Register_Width,
1151 DDI_BUF_TRANS_B_S7T2 => 16#06_4e9c# / Register_Width,
1152 DDI_BUF_TRANS_B_S8T1 => 16#06_4ea0# / Register_Width,
1153 DDI_BUF_TRANS_B_S8T2 => 16#06_4ea4# / Register_Width,
1154 DDI_BUF_TRANS_B_S9T1 => 16#06_4ea8# / Register_Width,
1155 DDI_BUF_TRANS_B_S9T2 => 16#06_4eac# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1156 DDI_AUX_CTL_B => 16#06_4110# / Register_Width,
1157 DDI_AUX_DATA_B_1 => 16#06_4114# / Register_Width,
1158 DDI_AUX_DATA_B_2 => 16#06_4118# / Register_Width,
1159 DDI_AUX_DATA_B_3 => 16#06_411c# / Register_Width,
1160 DDI_AUX_DATA_B_4 => 16#06_4120# / Register_Width,
1161 DDI_AUX_DATA_B_5 => 16#06_4124# / Register_Width,
1162 DDI_AUX_MUTEX_B => 16#06_412c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1163
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1164 DDI_BUF_CTL_C => 16#06_4200# / Register_Width, -- aliased by GMCH_DP_C
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1165 DDI_BUF_TRANS_C_S0T1 => 16#06_4ec0# / Register_Width,
1166 DDI_BUF_TRANS_C_S0T2 => 16#06_4ec4# / Register_Width,
1167 DDI_BUF_TRANS_C_S1T1 => 16#06_4ec8# / Register_Width,
1168 DDI_BUF_TRANS_C_S1T2 => 16#06_4ecc# / Register_Width,
1169 DDI_BUF_TRANS_C_S2T1 => 16#06_4ed0# / Register_Width,
1170 DDI_BUF_TRANS_C_S2T2 => 16#06_4ed4# / Register_Width,
1171 DDI_BUF_TRANS_C_S3T1 => 16#06_4ed8# / Register_Width,
1172 DDI_BUF_TRANS_C_S3T2 => 16#06_4edc# / Register_Width,
1173 DDI_BUF_TRANS_C_S4T1 => 16#06_4ee0# / Register_Width,
1174 DDI_BUF_TRANS_C_S4T2 => 16#06_4ee4# / Register_Width,
1175 DDI_BUF_TRANS_C_S5T1 => 16#06_4ee8# / Register_Width,
1176 DDI_BUF_TRANS_C_S5T2 => 16#06_4eec# / Register_Width,
1177 DDI_BUF_TRANS_C_S6T1 => 16#06_4ef0# / Register_Width,
1178 DDI_BUF_TRANS_C_S6T2 => 16#06_4ef4# / Register_Width,
1179 DDI_BUF_TRANS_C_S7T1 => 16#06_4ef8# / Register_Width,
1180 DDI_BUF_TRANS_C_S7T2 => 16#06_4efc# / Register_Width,
1181 DDI_BUF_TRANS_C_S8T1 => 16#06_4f00# / Register_Width,
1182 DDI_BUF_TRANS_C_S8T2 => 16#06_4f04# / Register_Width,
1183 DDI_BUF_TRANS_C_S9T1 => 16#06_4f08# / Register_Width,
1184 DDI_BUF_TRANS_C_S9T2 => 16#06_4f0c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1185 DDI_AUX_CTL_C => 16#06_4210# / Register_Width,
1186 DDI_AUX_DATA_C_1 => 16#06_4214# / Register_Width,
1187 DDI_AUX_DATA_C_2 => 16#06_4218# / Register_Width,
1188 DDI_AUX_DATA_C_3 => 16#06_421c# / Register_Width,
1189 DDI_AUX_DATA_C_4 => 16#06_4220# / Register_Width,
1190 DDI_AUX_DATA_C_5 => 16#06_4224# / Register_Width,
1191 DDI_AUX_MUTEX_C => 16#06_422c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1192
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1193 DDI_BUF_CTL_D => 16#06_4300# / Register_Width, -- aliased by GMCH_DP_D
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1194 DDI_BUF_TRANS_D_S0T1 => 16#06_4f20# / Register_Width,
1195 DDI_BUF_TRANS_D_S0T2 => 16#06_4f24# / Register_Width,
1196 DDI_BUF_TRANS_D_S1T1 => 16#06_4f28# / Register_Width,
1197 DDI_BUF_TRANS_D_S1T2 => 16#06_4f2c# / Register_Width,
1198 DDI_BUF_TRANS_D_S2T1 => 16#06_4f30# / Register_Width,
1199 DDI_BUF_TRANS_D_S2T2 => 16#06_4f34# / Register_Width,
1200 DDI_BUF_TRANS_D_S3T1 => 16#06_4f38# / Register_Width,
1201 DDI_BUF_TRANS_D_S3T2 => 16#06_4f3c# / Register_Width,
1202 DDI_BUF_TRANS_D_S4T1 => 16#06_4f40# / Register_Width,
1203 DDI_BUF_TRANS_D_S4T2 => 16#06_4f44# / Register_Width,
1204 DDI_BUF_TRANS_D_S5T1 => 16#06_4f48# / Register_Width,
1205 DDI_BUF_TRANS_D_S5T2 => 16#06_4f4c# / Register_Width,
1206 DDI_BUF_TRANS_D_S6T1 => 16#06_4f50# / Register_Width,
1207 DDI_BUF_TRANS_D_S6T2 => 16#06_4f54# / Register_Width,
1208 DDI_BUF_TRANS_D_S7T1 => 16#06_4f58# / Register_Width,
1209 DDI_BUF_TRANS_D_S7T2 => 16#06_4f5c# / Register_Width,
1210 DDI_BUF_TRANS_D_S8T1 => 16#06_4f60# / Register_Width,
1211 DDI_BUF_TRANS_D_S8T2 => 16#06_4f64# / Register_Width,
1212 DDI_BUF_TRANS_D_S9T1 => 16#06_4f68# / Register_Width,
1213 DDI_BUF_TRANS_D_S9T2 => 16#06_4f6c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1214 DDI_AUX_CTL_D => 16#06_4310# / Register_Width,
1215 DDI_AUX_DATA_D_1 => 16#06_4314# / Register_Width,
1216 DDI_AUX_DATA_D_2 => 16#06_4318# / Register_Width,
1217 DDI_AUX_DATA_D_3 => 16#06_431c# / Register_Width,
1218 DDI_AUX_DATA_D_4 => 16#06_4320# / Register_Width,
1219 DDI_AUX_DATA_D_5 => 16#06_4324# / Register_Width,
1220 DDI_AUX_MUTEX_D => 16#06_432c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1221
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1222 DDI_BUF_CTL_E => 16#06_4400# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1223 DDI_BUF_TRANS_E_S0T1 => 16#06_4f80# / Register_Width,
1224 DDI_BUF_TRANS_E_S0T2 => 16#06_4f84# / Register_Width,
1225 DDI_BUF_TRANS_E_S1T1 => 16#06_4f88# / Register_Width,
1226 DDI_BUF_TRANS_E_S1T2 => 16#06_4f8c# / Register_Width,
1227 DDI_BUF_TRANS_E_S2T1 => 16#06_4f90# / Register_Width,
1228 DDI_BUF_TRANS_E_S2T2 => 16#06_4f94# / Register_Width,
1229 DDI_BUF_TRANS_E_S3T1 => 16#06_4f98# / Register_Width,
1230 DDI_BUF_TRANS_E_S3T2 => 16#06_4f9c# / Register_Width,
1231 DDI_BUF_TRANS_E_S4T1 => 16#06_4fa0# / Register_Width,
1232 DDI_BUF_TRANS_E_S4T2 => 16#06_4fa4# / Register_Width,
1233 DDI_BUF_TRANS_E_S5T1 => 16#06_4fa8# / Register_Width,
1234 DDI_BUF_TRANS_E_S5T2 => 16#06_4fac# / Register_Width,
1235 DDI_BUF_TRANS_E_S6T1 => 16#06_4fb0# / Register_Width,
1236 DDI_BUF_TRANS_E_S6T2 => 16#06_4fb4# / Register_Width,
1237 DDI_BUF_TRANS_E_S7T1 => 16#06_4fb8# / Register_Width,
1238 DDI_BUF_TRANS_E_S7T2 => 16#06_4fbc# / Register_Width,
1239 DDI_BUF_TRANS_E_S8T1 => 16#06_4fc0# / Register_Width,
1240 DDI_BUF_TRANS_E_S8T2 => 16#06_4fc4# / Register_Width,
1241 DDI_BUF_TRANS_E_S9T1 => 16#06_4fc8# / Register_Width,
1242 DDI_BUF_TRANS_E_S9T2 => 16#06_4fcc# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1243 DP_TP_CTL_A => 16#06_4040# / Register_Width,
1244 DP_TP_CTL_B => 16#06_4140# / Register_Width,
1245 DP_TP_CTL_C => 16#06_4240# / Register_Width,
1246 DP_TP_CTL_D => 16#06_4340# / Register_Width,
1247 DP_TP_CTL_E => 16#06_4440# / Register_Width,
1248 DP_TP_STATUS_B => 16#06_4144# / Register_Width,
1249 DP_TP_STATUS_C => 16#06_4244# / Register_Width,
1250 DP_TP_STATUS_D => 16#06_4344# / Register_Width,
1251 DP_TP_STATUS_E => 16#06_4444# / Register_Width,
1252 PORT_CLK_SEL_DDIA => 16#04_6100# / Register_Width,
1253 PORT_CLK_SEL_DDIB => 16#04_6104# / Register_Width,
1254 PORT_CLK_SEL_DDIC => 16#04_6108# / Register_Width,
1255 PORT_CLK_SEL_DDID => 16#04_610c# / Register_Width,
1256 PORT_CLK_SEL_DDIE => 16#04_6110# / Register_Width,
1257
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]1258 -- Skylake I_boost configuration
1259 DISPIO_CR_TX_BMU_CR0 => 16#06_c00c# / Register_Width,
1260
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1261 -- Skylake DPLL registers
1262 DPLL1_CFGR1 => 16#06_c040# / Register_Width,
1263 DPLL1_CFGR2 => 16#06_c044# / Register_Width,
1264 DPLL2_CFGR1 => 16#06_c048# / Register_Width,
1265 DPLL2_CFGR2 => 16#06_c04c# / Register_Width,
1266 DPLL3_CFGR1 => 16#06_c050# / Register_Width,
1267 DPLL3_CFGR2 => 16#06_c054# / Register_Width,
1268 DPLL_CTRL1 => 16#06_c058# / Register_Width,
1269 DPLL_CTRL2 => 16#06_c05c# / Register_Width,
1270 DPLL_STATUS => 16#06_c060# / Register_Width,
1271
1272 -- CD CLK register
1273 CDCLK_CTL => 16#04_6000# / Register_Width,
1274
1275 -- Skylake LCPLL registers
1276 LCPLL1_CTL => 16#04_6010# / Register_Width,
1277 LCPLL2_CTL => 16#04_6014# / Register_Width,
1278
1279 -- SPLL register
1280 SPLL_CTL => 16#04_6020# / Register_Width,
1281
1282 -- WRPLL registers
1283 WRPLL_CTL_1 => 16#04_6040# / Register_Width,
1284 WRPLL_CTL_2 => 16#04_6060# / Register_Width,
1285
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]1286 -- Broxton Display Engine PLL registers
1287 BXT_DE_PLL_CTL => 16#06_d000# / Register_Width,
1288 BXT_DE_PLL_ENABLE => 16#04_6070# / Register_Width,
1289
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1290 -- Broxton DDI PHY PLL registers
1291 BXT_PORT_PLL_ENABLE_A => 16#04_6074# / Register_Width,
1292 BXT_PORT_PLL_ENABLE_B => 16#04_6078# / Register_Width,
1293 BXT_PORT_PLL_ENABLE_C => 16#04_607c# / Register_Width,
1294 BXT_PORT_PLL_EBB_0_A => 16#16_2034# / Register_Width,
1295 BXT_PORT_PLL_EBB_4_A => 16#16_2038# / Register_Width,
1296 BXT_PORT_PLL_0_A => 16#16_2100# / Register_Width,
1297 BXT_PORT_PLL_1_A => 16#16_2104# / Register_Width,
1298 BXT_PORT_PLL_2_A => 16#16_2108# / Register_Width,
1299 BXT_PORT_PLL_3_A => 16#16_210c# / Register_Width,
1300 BXT_PORT_PLL_6_A => 16#16_2118# / Register_Width,
1301 BXT_PORT_PLL_8_A => 16#16_2120# / Register_Width,
1302 BXT_PORT_PLL_9_A => 16#16_2124# / Register_Width,
1303 BXT_PORT_PLL_10_A => 16#16_2128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1304 BXT_PORT_PLL_EBB_0_B => 16#06_c034# / Register_Width,
1305 BXT_PORT_PLL_EBB_4_B => 16#06_c038# / Register_Width,
1306 BXT_PORT_PLL_0_B => 16#06_c100# / Register_Width,
1307 BXT_PORT_PLL_1_B => 16#06_c104# / Register_Width,
1308 BXT_PORT_PLL_2_B => 16#06_c108# / Register_Width,
1309 BXT_PORT_PLL_3_B => 16#06_c10c# / Register_Width,
1310 BXT_PORT_PLL_6_B => 16#06_c118# / Register_Width,
1311 BXT_PORT_PLL_8_B => 16#06_c120# / Register_Width,
1312 BXT_PORT_PLL_9_B => 16#06_c124# / Register_Width,
1313 BXT_PORT_PLL_10_B => 16#06_c128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1314 BXT_PORT_PLL_EBB_0_C => 16#06_c340# / Register_Width,
1315 BXT_PORT_PLL_EBB_4_C => 16#06_c344# / Register_Width,
1316 BXT_PORT_PLL_0_C => 16#06_c380# / Register_Width,
1317 BXT_PORT_PLL_1_C => 16#06_c384# / Register_Width,
1318 BXT_PORT_PLL_2_C => 16#06_c388# / Register_Width,
1319 BXT_PORT_PLL_3_C => 16#06_c38c# / Register_Width,
1320 BXT_PORT_PLL_6_C => 16#06_c398# / Register_Width,
1321 BXT_PORT_PLL_8_C => 16#06_c3a0# / Register_Width,
1322 BXT_PORT_PLL_9_C => 16#06_c3a4# / Register_Width,
1323 BXT_PORT_PLL_10_C => 16#06_c3a8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1324
1325 -- Broxton DDI PHY PCS? registers
1326 BXT_PORT_PCS_DW10_01_A => 16#16_2428# / Register_Width,
1327 BXT_PORT_PCS_DW12_01_A => 16#16_2430# / Register_Width,
1328 BXT_PORT_PCS_DW10_GRP_A => 16#16_2c28# / Register_Width,
1329 BXT_PORT_PCS_DW12_GRP_A => 16#16_2c30# / Register_Width,
1330 BXT_PORT_PCS_DW10_01_B => 16#06_c428# / Register_Width,
1331 BXT_PORT_PCS_DW12_01_B => 16#06_c430# / Register_Width,
1332 BXT_PORT_PCS_DW10_01_C => 16#06_c828# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1333 BXT_PORT_PCS_DW12_01_C => 16#06_c830# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1334 BXT_PORT_PCS_DW10_GRP_B => 16#06_cc28# / Register_Width,
1335 BXT_PORT_PCS_DW12_GRP_B => 16#06_cc30# / Register_Width,
1336 BXT_PORT_PCS_DW10_GRP_C => 16#06_ce28# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1337 BXT_PORT_PCS_DW12_GRP_C => 16#06_ce30# / Register_Width,
1338
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1339 -- Broxton DDI PHY registers
1340 BXT_P_CR_GT_DISP_PWRON => 16#13_8090# / Register_Width,
1341 BXT_PHY_CTL_A => 16#06_4c00# / Register_Width,
1342 BXT_PHY_CTL_B => 16#06_4c10# / Register_Width,
1343 BXT_PHY_CTL_C => 16#06_4c20# / Register_Width,
1344 BXT_PHY_CTL_FAM_EDP => 16#06_4c80# / Register_Width,
1345 BXT_PHY_CTL_FAM_DDI => 16#06_4c90# / Register_Width,
1346
1347 -- Broxton DDI PHY common lane registers
1348 BXT_PORT_CL1CM_DW0_A => 16#16_2000# / Register_Width,
1349 BXT_PORT_CL1CM_DW0_BC => 16#06_c000# / Register_Width,
1350 BXT_PORT_CL1CM_DW9_A => 16#16_2024# / Register_Width,
1351 BXT_PORT_CL1CM_DW9_BC => 16#06_c024# / Register_Width,
1352 BXT_PORT_CL1CM_DW10_A => 16#16_2028# / Register_Width,
1353 BXT_PORT_CL1CM_DW10_BC => 16#06_c028# / Register_Width,
1354 BXT_PORT_CL1CM_DW28_A => 16#16_2070# / Register_Width,
1355 BXT_PORT_CL1CM_DW28_BC => 16#06_c070# / Register_Width,
1356 BXT_PORT_CL1CM_DW30_A => 16#16_2078# / Register_Width,
1357 BXT_PORT_CL1CM_DW30_BC => 16#06_c078# / Register_Width,
1358 BXT_PORT_CL2CM_DW6_BC => 16#06_c358# / Register_Width,
1359
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1360 -- Broxton DDI PHY TX lane registers
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1361 BXT_PORT_TX_DW2_LN0_A => 16#16_2508# / Register_Width,
1362 BXT_PORT_TX_DW3_LN0_A => 16#16_250c# / Register_Width,
1363 BXT_PORT_TX_DW4_LN0_A => 16#16_2510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1364 BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width,
1365 BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width,
1366 BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width,
1367 BXT_PORT_TX_DW14_LN3_A => 16#16_27b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1368 BXT_PORT_TX_DW2_GRP_A => 16#16_2d08# / Register_Width,
1369 BXT_PORT_TX_DW3_GRP_A => 16#16_2d0c# / Register_Width,
1370 BXT_PORT_TX_DW4_GRP_A => 16#16_2d10# / Register_Width,
1371 BXT_PORT_TX_DW2_LN0_B => 16#06_c508# / Register_Width,
1372 BXT_PORT_TX_DW3_LN0_B => 16#06_c50c# / Register_Width,
1373 BXT_PORT_TX_DW4_LN0_B => 16#06_c510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1374 BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width,
1375 BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width,
1376 BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width,
1377 BXT_PORT_TX_DW14_LN3_B => 16#06_c7b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1378 BXT_PORT_TX_DW2_GRP_B => 16#06_cd08# / Register_Width,
1379 BXT_PORT_TX_DW3_GRP_B => 16#06_cd0c# / Register_Width,
1380 BXT_PORT_TX_DW4_GRP_B => 16#06_cd10# / Register_Width,
1381 BXT_PORT_TX_DW2_LN0_C => 16#06_c908# / Register_Width,
1382 BXT_PORT_TX_DW3_LN0_C => 16#06_c90c# / Register_Width,
1383 BXT_PORT_TX_DW4_LN0_C => 16#06_c910# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1384 BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width,
1385 BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width,
1386 BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width,
1387 BXT_PORT_TX_DW14_LN3_C => 16#06_cbb8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1388 BXT_PORT_TX_DW2_GRP_C => 16#06_cf08# / Register_Width,
1389 BXT_PORT_TX_DW3_GRP_C => 16#06_cf0c# / Register_Width,
1390 BXT_PORT_TX_DW4_GRP_C => 16#06_cf10# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1391
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1392 -- Broxton DDI PHY ref registers
1393 BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width,
1394 BXT_PORT_REF_DW3_BC => 16#06_c18c# / Register_Width,
1395 BXT_PORT_REF_DW6_A => 16#16_2198# / Register_Width,
1396 BXT_PORT_REF_DW6_BC => 16#06_c198# / Register_Width,
1397 BXT_PORT_REF_DW8_A => 16#16_21a0# / Register_Width,
1398 BXT_PORT_REF_DW8_BC => 16#06_c1a0# / Register_Width,
1399
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1400 -- Power Down Well registers
1401 PWR_WELL_CTL_BIOS => 16#04_5400# / Register_Width,
1402 PWR_WELL_CTL_DRIVER => 16#04_5404# / Register_Width,
1403 PWR_WELL_CTL_KVMR => 16#04_5408# / Register_Width,
1404 PWR_WELL_CTL_DEBUG => 16#04_540c# / Register_Width,
1405 PWR_WELL_CTL5 => 16#04_5410# / Register_Width,
1406 PWR_WELL_CTL6 => 16#04_5414# / Register_Width,
1407
1408 -- class Panel registers
Arthur Heymanse87d0d12018-03-28 17:02:49 +0200[diff] [blame]1409 GMCH_PP_STATUS => 16#06_1200# / Register_Width,
1410 GMCH_PP_CONTROL => 16#06_1204# / Register_Width,
1411 GMCH_PP_ON_DELAYS => 16#06_1208# / Register_Width,
1412 GMCH_PP_OFF_DELAYS => 16#06_120c# / Register_Width,
1413 GMCH_PP_DIVISOR => 16#06_1210# / Register_Width,
Arthur Heymansd5198442018-03-28 17:05:12 +0200[diff] [blame]1414 GMCH_PFIT_CONTROL => 16#06_1230# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1415 PCH_PP_STATUS => 16#0c_7200# / Register_Width,
1416 PCH_PP_CONTROL => 16#0c_7204# / Register_Width,
1417 PCH_PP_ON_DELAYS => 16#0c_7208# / Register_Width,
1418 PCH_PP_OFF_DELAYS => 16#0c_720c# / Register_Width,
1419 PCH_PP_DIVISOR => 16#0c_7210# / Register_Width,
1420 BLC_PWM_CPU_CTL => 16#04_8254# / Register_Width,
1421 BLC_PWM_PCH_CTL2 => 16#0c_8254# / Register_Width,
1422
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1423 -- GMCH LVDS Connector Registers
1424 GMCH_LVDS => 16#06_1180# / Register_Width,
1425
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1426 -- PCH LVDS Connector Registers
1427 PCH_LVDS => 16#0e_1180# / Register_Width,
1428
1429 -- PCH ADPA Connector Registers
1430 PCH_ADPA => 16#0e_1100# / Register_Width,
1431
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1432 -- GMCH DVOB Connector Registers
1433 GMCH_SDVOB => 16#06_1140# / Register_Width,
1434
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1435 -- PCH HDMIB Connector Registers
1436 PCH_HDMIB => 16#0e_1140# / Register_Width,
1437
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1438 -- GMCH DVOC Connector Registers
1439 GMCH_SDVOC => 16#06_1160# / Register_Width,
1440
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1441 -- PCH HDMIC Connector Registers
1442 PCH_HDMIC => 16#0e_1150# / Register_Width,
1443
1444 -- PCH HDMID Connector Registers
1445 PCH_HDMID => 16#0e_1160# / Register_Width,
1446
1447 -- Intel Registers
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]1448 CPU_VGACNTRL => 16#04_1000# / Register_Width,
1449 GMCH_VGACNTRL => 16#07_1400# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1450 FUSE_STATUS => 16#04_2000# / Register_Width,
1451 FBA_CFB_BASE => 16#04_3200# / Register_Width,
1452 IPS_CTL => 16#04_3408# / Register_Width,
1453 ARB_CTL => 16#04_5000# / Register_Width,
1454 DBUF_CTL => 16#04_5008# / Register_Width,
1455 NDE_RSTWRN_OPT => 16#04_6408# / Register_Width,
1456 PCH_DREF_CONTROL => 16#0c_6200# / Register_Width,
1457 BLC_PWM_PCH_CTL1 => 16#0c_8250# / Register_Width,
1458 BLC_PWM_CPU_CTL2 => 16#04_8250# / Register_Width,
1459 PCH_DPLL_SEL => 16#0c_7000# / Register_Width,
1460 GT_MAILBOX => 16#13_8124# / Register_Width,
1461 GT_MAILBOX_DATA => 16#13_8128# / Register_Width,
1462 GT_MAILBOX_DATA_1 => 16#13_812c# / Register_Width,
1463
1464 PCH_DP_B => 16#0e_4100# / Register_Width,
1465 PCH_DP_AUX_CTL_B => 16#0e_4110# / Register_Width,
1466 PCH_DP_AUX_DATA_B_1 => 16#0e_4114# / Register_Width,
1467 PCH_DP_AUX_DATA_B_2 => 16#0e_4118# / Register_Width,
1468 PCH_DP_AUX_DATA_B_3 => 16#0e_411c# / Register_Width,
1469 PCH_DP_AUX_DATA_B_4 => 16#0e_4120# / Register_Width,
1470 PCH_DP_AUX_DATA_B_5 => 16#0e_4124# / Register_Width,
1471 PCH_DP_C => 16#0e_4200# / Register_Width,
1472 PCH_DP_AUX_CTL_C => 16#0e_4210# / Register_Width,
1473 PCH_DP_AUX_DATA_C_1 => 16#0e_4214# / Register_Width,
1474 PCH_DP_AUX_DATA_C_2 => 16#0e_4218# / Register_Width,
1475 PCH_DP_AUX_DATA_C_3 => 16#0e_421c# / Register_Width,
1476 PCH_DP_AUX_DATA_C_4 => 16#0e_4220# / Register_Width,
1477 PCH_DP_AUX_DATA_C_5 => 16#0e_4224# / Register_Width,
1478 PCH_DP_D => 16#0e_4300# / Register_Width,
1479 PCH_DP_AUX_CTL_D => 16#0e_4310# / Register_Width,
1480 PCH_DP_AUX_DATA_D_1 => 16#0e_4314# / Register_Width,
1481 PCH_DP_AUX_DATA_D_2 => 16#0e_4318# / Register_Width,
1482 PCH_DP_AUX_DATA_D_3 => 16#0e_431c# / Register_Width,
1483 PCH_DP_AUX_DATA_D_4 => 16#0e_4320# / Register_Width,
1484 PCH_DP_AUX_DATA_D_5 => 16#0e_4324# / Register_Width,
1485
1486 -- watermark registers
1487 WM1_LP_ILK => 16#04_5108# / Register_Width,
1488 WM2_LP_ILK => 16#04_510c# / Register_Width,
1489 WM3_LP_ILK => 16#04_5110# / Register_Width,
1490
1491 -- audio VID/DID
1492 AUD_VID_DID => 16#06_5020# / Register_Width,
1493 PCH_AUD_VID_DID => 16#0e_5020# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1494 G4X_AUD_VID_DID => 16#06_2020# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1495
1496 -- interrupt registers
1497 DEISR => 16#04_4000# / Register_Width,
1498 DEIMR => 16#04_4004# / Register_Width,
1499 DEIIR => 16#04_4008# / Register_Width,
1500 DEIER => 16#04_400c# / Register_Width,
1501 GTISR => 16#04_4010# / Register_Width,
1502 GTIMR => 16#04_4014# / Register_Width,
1503 GTIIR => 16#04_4018# / Register_Width,
1504 GTIER => 16#04_401c# / Register_Width,
1505 SDEISR => 16#0c_4000# / Register_Width,
1506 SDEIMR => 16#0c_4004# / Register_Width,
1507 SDEIIR => 16#0c_4008# / Register_Width,
1508 SDEIER => 16#0c_400c# / Register_Width,
1509
1510 -- I2C stuff
Arthur Heymans229ed1c2018-03-28 16:45:43 +0200[diff] [blame]1511 GMCH_GMBUS0 => 16#00_5100# / Register_Width,
1512 GMCH_GMBUS1 => 16#00_5104# / Register_Width,
1513 GMCH_GMBUS2 => 16#00_5108# / Register_Width,
1514 GMCH_GMBUS3 => 16#00_510c# / Register_Width,
1515 GMCH_GMBUS4 => 16#00_5110# / Register_Width,
1516 GMCH_GMBUS5 => 16#00_5120# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1517 PCH_GMBUS0 => 16#0c_5100# / Register_Width,
1518 PCH_GMBUS1 => 16#0c_5104# / Register_Width,
1519 PCH_GMBUS2 => 16#0c_5108# / Register_Width,
1520 PCH_GMBUS3 => 16#0c_510c# / Register_Width,
1521 PCH_GMBUS4 => 16#0c_5110# / Register_Width,
1522 PCH_GMBUS5 => 16#0c_5120# / Register_Width,
1523
1524 -- clock gating -- maybe have to touch this
1525 DSPCLK_GATE_D => 16#04_2020# / Register_Width,
1526 PCH_FDI_CHICKEN_B_C => 16#0c_2000# / Register_Width,
1527 PCH_DSPCLK_GATE_D => 16#0c_2020# / Register_Width,
1528
1529 -- hotplug and initial detection
1530 HOTPLUG_CTL => 16#04_4030# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1531 PORT_HOTPLUG_EN => 16#06_1110# / Register_Width,
1532 PORT_HOTPLUG_STAT => 16#06_1114# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1533 SHOTPLUG_CTL => 16#0c_4030# / Register_Width,
1534 SFUSE_STRAP => 16#0c_2014# / Register_Width,
1535
1536 -- Render Engine Command Streamer
1537 ARB_MODE => 16#00_4030# / Register_Width,
1538 HWS_PGA => 16#00_4080# / Register_Width,
1539 RCS_RING_BUFFER_TAIL => 16#00_2030# / Register_Width,
1540 VCS_RING_BUFFER_TAIL => 16#01_2030# / Register_Width,
1541 BCS_RING_BUFFER_TAIL => 16#02_2030# / Register_Width,
1542 RCS_RING_BUFFER_HEAD => 16#00_2034# / Register_Width,
1543 VCS_RING_BUFFER_HEAD => 16#01_2034# / Register_Width,
1544 BCS_RING_BUFFER_HEAD => 16#02_2034# / Register_Width,
1545 RCS_RING_BUFFER_STRT => 16#00_2038# / Register_Width,
1546 VCS_RING_BUFFER_STRT => 16#01_2038# / Register_Width,
1547 BCS_RING_BUFFER_STRT => 16#02_2038# / Register_Width,
1548 RCS_RING_BUFFER_CTL => 16#00_203c# / Register_Width,
1549 VCS_RING_BUFFER_CTL => 16#01_203c# / Register_Width,
1550 BCS_RING_BUFFER_CTL => 16#02_203c# / Register_Width,
1551 MI_MODE => 16#00_209c# / Register_Width,
1552 INSTPM => 16#00_20c0# / Register_Width,
1553 GAB_CTL_REG => 16#02_4000# / Register_Width,
1554 PP_DCLV_HIGH => 16#00_2220# / Register_Width,
1555 PP_DCLV_LOW => 16#00_2228# / Register_Width,
1556 VCS_PP_DCLV_HIGH => 16#01_2220# / Register_Width,
1557 VCS_PP_DCLV_LOW => 16#01_2228# / Register_Width,
1558 BCS_PP_DCLV_HIGH => 16#02_2220# / Register_Width,
1559 BCS_PP_DCLV_LOW => 16#02_2228# / Register_Width,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1560 ILK_DISPLAY_CHICKEN2 => 16#04_2004# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1561 UCGCTL1 => 16#00_9400# / Register_Width,
1562 UCGCTL2 => 16#00_9404# / Register_Width,
1563 MBCTL => 16#00_907c# / Register_Width,
1564 HWSTAM => 16#00_2098# / Register_Width,
1565 VCS_HWSTAM => 16#01_2098# / Register_Width,
1566 BCS_HWSTAM => 16#02_2098# / Register_Width,
1567 IIR => 16#04_4028# / Register_Width,
1568 PIPE_FRMCNT_A => 16#07_0040# / Register_Width,
1569 PIPE_FRMCNT_B => 16#07_1040# / Register_Width,
1570 PIPE_FRMCNT_C => 16#07_2040# / Register_Width,
1571 FBC_CTL => 16#04_3208# / Register_Width,
1572 PIPE_VSYNCSHIFT_A => 16#06_0028# / Register_Width,
1573 PIPE_VSYNCSHIFT_B => 16#06_1028# / Register_Width,
1574 PIPE_VSYNCSHIFT_C => 16#06_2028# / Register_Width,
1575 WM_PIPE_A => 16#04_5100# / Register_Width,
1576 WM_PIPE_B => 16#04_5104# / Register_Width,
1577 WM_PIPE_C => 16#04_5200# / Register_Width,
1578 PIPE_SCANLINE_A => 16#07_0000# / Register_Width,
1579 PIPE_SCANLINE_B => 16#07_1000# / Register_Width,
1580 PIPE_SCANLINE_C => 16#07_2000# / Register_Width,
1581 GFX_MODE => 16#00_2520# / Register_Width,
1582 CACHE_MODE_0 => 16#00_2120# / Register_Width,
1583 SLEEP_PSMI_CONTROL => 16#01_2050# / Register_Width,
1584 CTX_SIZE => 16#00_21a0# / Register_Width,
1585 GAC_ECO_BITS => 16#01_4090# / Register_Width,
1586 GAM_ECOCHK => 16#00_4090# / Register_Width,
1587 QUIRK_02084 => 16#00_2084# / Register_Width,
1588 QUIRK_02090 => 16#00_2090# / Register_Width,
1589 GT_MODE => 16#00_20d0# / Register_Width,
1590 QUIRK_F0060 => 16#0f_0060# / Register_Width,
1591 QUIRK_F1060 => 16#0f_1060# / Register_Width,
1592 QUIRK_F2060 => 16#0f_2060# / Register_Width,
1593 AUD_CNTRL_ST2 => 16#0e_50c0# / Register_Width,
1594 AUD_CNTL_ST_A => 16#0e_50b4# / Register_Width,
1595 AUD_CNTL_ST_B => 16#0e_51b4# / Register_Width,
1596 AUD_CNTL_ST_C => 16#0e_52b4# / Register_Width,
1597 AUD_HDMIW_HDMIEDID_A => 16#0e_5050# / Register_Width,
1598 AUD_HDMIW_HDMIEDID_B => 16#0e_5150# / Register_Width,
1599 AUD_HDMIW_HDMIEDID_C => 16#0e_5250# / Register_Width,
1600 AUD_CONFIG_A => 16#0e_5000# / Register_Width,
1601 AUD_CONFIG_B => 16#0e_5100# / Register_Width,
1602 AUD_CONFIG_C => 16#0e_5200# / Register_Width,
1603 TRANS_DP_CTL_A => 16#0e_0300# / Register_Width,
1604 TRANS_DP_CTL_B => 16#0e_1300# / Register_Width,
1605 TRANS_DP_CTL_C => 16#0e_2300# / Register_Width,
1606 TRANS_VSYNCSHIFT_A => 16#0e_0028# / Register_Width,
1607 TRANS_VSYNCSHIFT_B => 16#0e_1028# / Register_Width,
1608 TRANS_VSYNCSHIFT_C => 16#0e_2028# / Register_Width,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]1609 PCH_RAWCLK_FREQ => 16#0c_6204# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1610 QUIRK_C2004 => 16#0c_2004# / Register_Width,
1611
1612 -- MCHBAR Mirror
1613
1614 GMCH_CLKCFG => 16#01_0c00# / Register_Width);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1615
1616 subtype Registers_Index is Registers_Invalid_Index range
1617 Registers_Invalid_Index'Succ (Invalid_Register) ..
1618 Registers_Invalid_Index'Last;
1619
1620 -- aliased registers
1621 DP_CTL_A : constant Registers_Index := DDI_BUF_CTL_A;
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1622 GMCH_DP_B : constant Registers_Index := DDI_BUF_CTL_B;
1623 GMCH_DP_C : constant Registers_Index := DDI_BUF_CTL_C;
1624 GMCH_DP_D : constant Registers_Index := DDI_BUF_CTL_D;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1625 DP_AUX_CTL_A : constant Registers_Index := DDI_AUX_CTL_A;
1626 DP_AUX_DATA_A_1 : constant Registers_Index := DDI_AUX_DATA_A_1;
1627 DP_AUX_DATA_A_2 : constant Registers_Index := DDI_AUX_DATA_A_2;
1628 DP_AUX_DATA_A_3 : constant Registers_Index := DDI_AUX_DATA_A_3;
1629 DP_AUX_DATA_A_4 : constant Registers_Index := DDI_AUX_DATA_A_4;
1630 DP_AUX_DATA_A_5 : constant Registers_Index := DDI_AUX_DATA_A_5;
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1631 ILK_DISPLAY_CHICKEN1 : constant Registers_Index := FUSE_STATUS;
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1632 GMCH_ADPA : constant Registers_Index := FDI_TX_CTL_B;
1633 GMCH_HDMIB : constant Registers_Index := GMCH_SDVOB;
1634 GMCH_HDMIC : constant Registers_Index := GMCH_SDVOC;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1635
1636 ---------------------------------------------------------------------------
1637
1638 Default_Timeout_MS : constant := 10;
1639
1640 ---------------------------------------------------------------------------
1641
1642 procedure Posting_Read
1643 (Register : in Registers_Index)
1644 with
1645 Global => (In_Out => Register_State),
1646 Depends => (Register_State =>+ (Register)),
1647 Pre => True,
1648 Post => True;
1649
1650 pragma Warnings (GNATprove, Off, "unused variable ""Verbose""",
1651 Reason => "Only used on debugging path");
1652 procedure Read
1653 (Register : in Registers_Index;
1654 Value : out Word32;
1655 Verbose : in Boolean := True)
1656 with
1657 Global => (In_Out => Register_State),
1658 Depends => ((Value, Register_State) => (Register, Register_State),
1659 null => Verbose),
1660 Pre => True,
1661 Post => True;
1662 pragma Warnings (GNATprove, On, "unused variable ""Verbose""");
1663
1664 procedure Write
1665 (Register : Registers_Index;
1666 Value : Word32)
1667 with
1668 Global => (In_Out => Register_State),
1669 Depends => (Register_State => (Register, Register_State, Value)),
1670 Pre => True,
1671 Post => True;
1672
1673 procedure Is_Set_Mask
1674 (Register : in Registers_Index;
1675 Mask : in Word32;
1676 Result : out Boolean);
1677
1678 pragma Warnings (GNATprove, Off, "unused initial value of ""Verbose""",
1679 Reason => "Only used on debugging path");
Nico Huberbcb2c472017-02-02 16:39:26 +0100[diff] [blame]1680 procedure Wait
1681 (Register : Registers_Index;
1682 Mask : Word32;
1683 Value : Word32;
1684 TOut_MS : Natural := Default_Timeout_MS;
1685 Verbose : Boolean := False);
1686
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1687 procedure Wait_Set_Mask
1688 (Register : Registers_Index;
1689 Mask : Word32;
1690 TOut_MS : Natural := Default_Timeout_MS;
1691 Verbose : Boolean := False);
1692
1693 procedure Wait_Unset_Mask
1694 (Register : Registers_Index;
1695 Mask : Word32;
1696 TOut_MS : Natural := Default_Timeout_MS;
1697 Verbose : Boolean := False);
1698 pragma Warnings (GNATprove, On, "unused initial value of ""Verbose""");
1699
1700 procedure Set_Mask
1701 (Register : Registers_Index;
1702 Mask : Word32);
1703
1704 procedure Unset_Mask
1705 (Register : Registers_Index;
1706 Mask : Word32);
1707
1708 procedure Unset_And_Set_Mask
1709 (Register : Registers_Index;
1710 Mask_Unset : Word32;
1711 Mask_Set : Word32);
1712
Nico Huber17d64b62017-07-15 20:51:25 +0200[diff] [blame]1713 procedure Clear_Fences;
1714
Nico Huberb03c8f12017-08-25 13:29:08 +0200[diff] [blame]1715 procedure Add_Fence
1716 (First_Page : in GTT_Range;
1717 Last_Page : in GTT_Range;
1718 Tiling : in XY_Tiling;
1719 Pitch : in Natural;
1720 Success : out Boolean);
1721
1722 procedure Remove_Fence (First_Page, Last_Page : GTT_Range);
1723
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]1724 pragma Warnings (GNATprove, Off, "no check message justified by this",
1725 Reason => "see Annotate aspects.");
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1726 procedure Write_GTT
1727 (GTT_Page : GTT_Range;
1728 Device_Address : GTT_Address_Type;
1729 Valid : Boolean)
1730 with
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]1731 Global =>
1732 (Input => Config.Variable,
1733 In_Out => GTT_State),
1734 Depends =>
1735 (GTT_State =>+ (Config.Variable, GTT_Page, Device_Address, Valid)),
1736 Annotate =>
1737 (GNATprove, Intentional,
1738 """GMA.Config_State"" of ""Write_GTT"" not read",
1739 "Reading of Config_State depends on the platform configuration.");
Nico Huberceda17d2018-06-09 22:00:29 +0200[diff] [blame]1740
1741 procedure Read_GTT
1742 (Device_Address : out GTT_Address_Type;
1743 Valid : out Boolean;
1744 GTT_Page : in GTT_Range)
1745 with
Nico Huberadfe11f2018-06-10 14:59:04 +0200[diff] [blame]1746 Global =>
1747 (Input => Config.Variable,
1748 In_Out => GTT_State),
1749 Depends =>
1750 ((Device_Address, Valid, GTT_State) =>
1751 (Config.Variable, GTT_State, GTT_Page)),
1752 Annotate =>
1753 (GNATprove, Intentional,
1754 """GMA.Config_State"" of ""Read_GTT"" not read",
1755 "Reading of Config_State depends on the platform configuration.");
1756 pragma Warnings (GNATprove, On, "no check message justified by this");
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1757
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]1758 procedure Set_Register_Base (Base : Word64; GTT_Base : Word64 := 0)
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1759 with
1760 Global => (Output => Address_State),
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]1761 Depends => (Address_State => (Base, GTT_Base)),
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1762 Pre => True,
1763 Post => True;
1764
1765end HW.GFX.GMA.Registers;