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review.sourcearcade.org / libgfxinit / 718c79bb0713b5b90c9cc44e03197dc777066e3d / . / common / hw-gfx-gma-registers.ads
blob: 1220d1ab36da9ff4db026b070bf7c0d82f0b7934 [file] [log] [blame]
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1--
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]2-- Copyright (C) 2015-2017 secunet Security Networks AG
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +0200[diff] [blame]6-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]8--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
15with System;
16with HW.GFX.GMA;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]17
18private package HW.GFX.GMA.Registers
19with
20 Abstract_State =>
21 ((Address_State with Part_Of => GMA.State),
22 (Register_State with External, Part_Of => GMA.Device_State),
23 (GTT_State with External, Part_Of => GMA.Device_State)),
24 Initializes => Address_State
25is
26 type Registers_Invalid_Index is
27 (Invalid_Register, -- Allow a placeholder when access is not acceptable
28
29 RCS_RING_BUFFER_TAIL,
30 RCS_RING_BUFFER_HEAD,
31 RCS_RING_BUFFER_STRT,
32 RCS_RING_BUFFER_CTL,
33 QUIRK_02084,
34 QUIRK_02090,
35 HWSTAM,
36 MI_MODE,
37 INSTPM,
38 GT_MODE,
39 CACHE_MODE_0,
40 CTX_SIZE,
41 PP_DCLV_HIGH,
42 PP_DCLV_LOW,
43 GFX_MODE,
44 ARB_MODE,
45 HWS_PGA,
46 GAM_ECOCHK,
Arthur Heymans229ed1c2018-03-28 16:45:43 +0200[diff] [blame]47 GMCH_GMBUS0,
48 GMCH_GMBUS1,
49 GMCH_GMBUS2,
50 GMCH_GMBUS3,
51 GMCH_GMBUS4,
52 GMCH_GMBUS5,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]53 GMCH_DPLL_A,
54 GMCH_DPLL_B,
55 GMCH_FPA0,
56 GMCH_FPA1,
57 GMCH_FPB0,
58 GMCH_FPB1,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]59 MBCTL,
60 UCGCTL1,
61 UCGCTL2,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]62 GMCH_CLKCFG,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]63 VCS_RING_BUFFER_TAIL,
64 VCS_RING_BUFFER_HEAD,
65 VCS_RING_BUFFER_STRT,
66 VCS_RING_BUFFER_CTL,
67 SLEEP_PSMI_CONTROL,
68 VCS_HWSTAM,
69 VCS_PP_DCLV_HIGH,
70 VCS_PP_DCLV_LOW,
71 GAC_ECO_BITS,
72 BCS_RING_BUFFER_TAIL,
73 BCS_RING_BUFFER_HEAD,
74 BCS_RING_BUFFER_STRT,
75 BCS_RING_BUFFER_CTL,
76 BCS_HWSTAM,
77 BCS_PP_DCLV_HIGH,
78 BCS_PP_DCLV_LOW,
79 GAB_CTL_REG,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]80 CPU_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]81 FUSE_STATUS,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]82 ILK_DISPLAY_CHICKEN2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]83 DSPCLK_GATE_D,
84 FBA_CFB_BASE,
85 FBC_CTL,
86 IPS_CTL,
87 DEISR,
88 DEIMR,
89 DEIIR,
90 DEIER,
91 GTISR,
92 GTIMR,
93 GTIIR,
94 GTIER,
95 IIR,
96 HOTPLUG_CTL,
97 ARB_CTL,
98 DBUF_CTL,
99 WM_PIPE_A,
100 WM_PIPE_B,
101 WM1_LP_ILK,
102 WM2_LP_ILK,
103 WM3_LP_ILK,
104 WM_PIPE_C,
105 WM_LINETIME_A,
106 WM_LINETIME_B,
107 WM_LINETIME_C,
108 PWR_WELL_CTL_BIOS,
109 PWR_WELL_CTL_DRIVER,
110 PWR_WELL_CTL_KVMR,
111 PWR_WELL_CTL_DEBUG,
112 PWR_WELL_CTL5,
113 PWR_WELL_CTL6,
114 CDCLK_CTL,
115 LCPLL1_CTL,
116 LCPLL2_CTL,
117 SPLL_CTL,
118 WRPLL_CTL_1,
119 WRPLL_CTL_2,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]120 BXT_DE_PLL_ENABLE,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]121 BXT_PORT_PLL_ENABLE_A,
122 BXT_PORT_PLL_ENABLE_B,
123 BXT_PORT_PLL_ENABLE_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]124 PORT_CLK_SEL_DDIA,
125 PORT_CLK_SEL_DDIB,
126 PORT_CLK_SEL_DDIC,
127 PORT_CLK_SEL_DDID,
128 PORT_CLK_SEL_DDIE,
129 TRANSA_CLK_SEL,
130 TRANSB_CLK_SEL,
131 TRANSC_CLK_SEL,
132 NDE_RSTWRN_OPT,
133 BLC_PWM_CPU_CTL2,
134 BLC_PWM_CPU_CTL,
135 HTOTAL_A,
136 HBLANK_A,
137 HSYNC_A,
138 VTOTAL_A,
139 VBLANK_A,
140 VSYNC_A,
141 PIPEASRC,
142 PIPE_VSYNCSHIFT_A,
143 PIPEA_DATA_M1,
144 PIPEA_DATA_N1,
145 PIPEA_LINK_M1,
146 PIPEA_LINK_N1,
147 FDI_TX_CTL_A,
148 PIPEA_DDI_FUNC_CTL,
149 PIPEA_MSA_MISC,
150 SRD_CTL_A,
151 SRD_STATUS_A,
152 HTOTAL_B,
153 HBLANK_B,
154 HSYNC_B,
155 VTOTAL_B,
156 VBLANK_B,
157 VSYNC_B,
158 PIPEBSRC,
159 PIPE_VSYNCSHIFT_B,
160 PIPEB_DATA_M1,
161 PIPEB_DATA_N1,
162 PIPEB_LINK_M1,
163 PIPEB_LINK_N1,
164 FDI_TX_CTL_B,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]165 PORT_HOTPLUG_EN,
166 PORT_HOTPLUG_STAT,
167 GMCH_SDVOB,
168 GMCH_SDVOC,
169 GMCH_LVDS,
Arthur Heymanse87d0d12018-03-28 17:02:49 +0200[diff] [blame]170 GMCH_PP_STATUS,
171 GMCH_PP_CONTROL,
172 GMCH_PP_ON_DELAYS,
173 GMCH_PP_OFF_DELAYS,
174 GMCH_PP_DIVISOR,
Arthur Heymansd5198442018-03-28 17:05:12 +0200[diff] [blame]175 GMCH_PFIT_CONTROL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]176 PIPEB_DDI_FUNC_CTL,
177 PIPEB_MSA_MISC,
178 SRD_CTL_B,
179 SRD_STATUS_B,
180 HTOTAL_C,
181 HBLANK_C,
182 HSYNC_C,
183 VTOTAL_C,
184 VBLANK_C,
185 VSYNC_C,
186 PIPECSRC,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]187 G4X_AUD_VID_DID,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]188 PIPE_VSYNCSHIFT_C,
189 PIPEC_DATA_M1,
190 PIPEC_DATA_N1,
191 PIPEC_LINK_M1,
192 PIPEC_LINK_N1,
193 FDI_TX_CTL_C,
194 PIPEC_DDI_FUNC_CTL,
195 PIPEC_MSA_MISC,
196 SRD_CTL_C,
197 SRD_STATUS_C,
198 DDI_BUF_CTL_A,
199 DDI_AUX_CTL_A,
200 DDI_AUX_DATA_A_1,
201 DDI_AUX_DATA_A_2,
202 DDI_AUX_DATA_A_3,
203 DDI_AUX_DATA_A_4,
204 DDI_AUX_DATA_A_5,
205 DDI_AUX_MUTEX_A,
206 DP_TP_CTL_A,
207 DDI_BUF_CTL_B,
208 DDI_AUX_CTL_B,
209 DDI_AUX_DATA_B_1,
210 DDI_AUX_DATA_B_2,
211 DDI_AUX_DATA_B_3,
212 DDI_AUX_DATA_B_4,
213 DDI_AUX_DATA_B_5,
214 DDI_AUX_MUTEX_B,
215 DP_TP_CTL_B,
216 DP_TP_STATUS_B,
217 DDI_BUF_CTL_C,
218 DDI_AUX_CTL_C,
219 DDI_AUX_DATA_C_1,
220 DDI_AUX_DATA_C_2,
221 DDI_AUX_DATA_C_3,
222 DDI_AUX_DATA_C_4,
223 DDI_AUX_DATA_C_5,
224 DDI_AUX_MUTEX_C,
225 DP_TP_CTL_C,
226 DP_TP_STATUS_C,
227 DDI_BUF_CTL_D,
228 DDI_AUX_CTL_D,
229 DDI_AUX_DATA_D_1,
230 DDI_AUX_DATA_D_2,
231 DDI_AUX_DATA_D_3,
232 DDI_AUX_DATA_D_4,
233 DDI_AUX_DATA_D_5,
234 DDI_AUX_MUTEX_D,
235 DP_TP_CTL_D,
236 DP_TP_STATUS_D,
237 DDI_BUF_CTL_E,
238 DP_TP_CTL_E,
239 DP_TP_STATUS_E,
240 SRD_CTL,
241 SRD_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]242 BXT_PHY_CTL_A,
243 BXT_PHY_CTL_B,
244 BXT_PHY_CTL_C,
245 BXT_PHY_CTL_FAM_EDP,
246 BXT_PHY_CTL_FAM_DDI,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]247 DDI_BUF_TRANS_A_S0T1,
248 DDI_BUF_TRANS_A_S0T2,
249 DDI_BUF_TRANS_A_S1T1,
250 DDI_BUF_TRANS_A_S1T2,
251 DDI_BUF_TRANS_A_S2T1,
252 DDI_BUF_TRANS_A_S2T2,
253 DDI_BUF_TRANS_A_S3T1,
254 DDI_BUF_TRANS_A_S3T2,
255 DDI_BUF_TRANS_A_S4T1,
256 DDI_BUF_TRANS_A_S4T2,
257 DDI_BUF_TRANS_A_S5T1,
258 DDI_BUF_TRANS_A_S5T2,
259 DDI_BUF_TRANS_A_S6T1,
260 DDI_BUF_TRANS_A_S6T2,
261 DDI_BUF_TRANS_A_S7T1,
262 DDI_BUF_TRANS_A_S7T2,
263 DDI_BUF_TRANS_A_S8T1,
264 DDI_BUF_TRANS_A_S8T2,
265 DDI_BUF_TRANS_A_S9T1,
266 DDI_BUF_TRANS_A_S9T2,
267 DDI_BUF_TRANS_B_S0T1,
268 DDI_BUF_TRANS_B_S0T2,
269 DDI_BUF_TRANS_B_S1T1,
270 DDI_BUF_TRANS_B_S1T2,
271 DDI_BUF_TRANS_B_S2T1,
272 DDI_BUF_TRANS_B_S2T2,
273 DDI_BUF_TRANS_B_S3T1,
274 DDI_BUF_TRANS_B_S3T2,
275 DDI_BUF_TRANS_B_S4T1,
276 DDI_BUF_TRANS_B_S4T2,
277 DDI_BUF_TRANS_B_S5T1,
278 DDI_BUF_TRANS_B_S5T2,
279 DDI_BUF_TRANS_B_S6T1,
280 DDI_BUF_TRANS_B_S6T2,
281 DDI_BUF_TRANS_B_S7T1,
282 DDI_BUF_TRANS_B_S7T2,
283 DDI_BUF_TRANS_B_S8T1,
284 DDI_BUF_TRANS_B_S8T2,
285 DDI_BUF_TRANS_B_S9T1,
286 DDI_BUF_TRANS_B_S9T2,
287 DDI_BUF_TRANS_C_S0T1,
288 DDI_BUF_TRANS_C_S0T2,
289 DDI_BUF_TRANS_C_S1T1,
290 DDI_BUF_TRANS_C_S1T2,
291 DDI_BUF_TRANS_C_S2T1,
292 DDI_BUF_TRANS_C_S2T2,
293 DDI_BUF_TRANS_C_S3T1,
294 DDI_BUF_TRANS_C_S3T2,
295 DDI_BUF_TRANS_C_S4T1,
296 DDI_BUF_TRANS_C_S4T2,
297 DDI_BUF_TRANS_C_S5T1,
298 DDI_BUF_TRANS_C_S5T2,
299 DDI_BUF_TRANS_C_S6T1,
300 DDI_BUF_TRANS_C_S6T2,
301 DDI_BUF_TRANS_C_S7T1,
302 DDI_BUF_TRANS_C_S7T2,
303 DDI_BUF_TRANS_C_S8T1,
304 DDI_BUF_TRANS_C_S8T2,
305 DDI_BUF_TRANS_C_S9T1,
306 DDI_BUF_TRANS_C_S9T2,
307 DDI_BUF_TRANS_D_S0T1,
308 DDI_BUF_TRANS_D_S0T2,
309 DDI_BUF_TRANS_D_S1T1,
310 DDI_BUF_TRANS_D_S1T2,
311 DDI_BUF_TRANS_D_S2T1,
312 DDI_BUF_TRANS_D_S2T2,
313 DDI_BUF_TRANS_D_S3T1,
314 DDI_BUF_TRANS_D_S3T2,
315 DDI_BUF_TRANS_D_S4T1,
316 DDI_BUF_TRANS_D_S4T2,
317 DDI_BUF_TRANS_D_S5T1,
318 DDI_BUF_TRANS_D_S5T2,
319 DDI_BUF_TRANS_D_S6T1,
320 DDI_BUF_TRANS_D_S6T2,
321 DDI_BUF_TRANS_D_S7T1,
322 DDI_BUF_TRANS_D_S7T2,
323 DDI_BUF_TRANS_D_S8T1,
324 DDI_BUF_TRANS_D_S8T2,
325 DDI_BUF_TRANS_D_S9T1,
326 DDI_BUF_TRANS_D_S9T2,
327 DDI_BUF_TRANS_E_S0T1,
328 DDI_BUF_TRANS_E_S0T2,
329 DDI_BUF_TRANS_E_S1T1,
330 DDI_BUF_TRANS_E_S1T2,
331 DDI_BUF_TRANS_E_S2T1,
332 DDI_BUF_TRANS_E_S2T2,
333 DDI_BUF_TRANS_E_S3T1,
334 DDI_BUF_TRANS_E_S3T2,
335 DDI_BUF_TRANS_E_S4T1,
336 DDI_BUF_TRANS_E_S4T2,
337 DDI_BUF_TRANS_E_S5T1,
338 DDI_BUF_TRANS_E_S5T2,
339 DDI_BUF_TRANS_E_S6T1,
340 DDI_BUF_TRANS_E_S6T2,
341 DDI_BUF_TRANS_E_S7T1,
342 DDI_BUF_TRANS_E_S7T2,
343 DDI_BUF_TRANS_E_S8T1,
344 DDI_BUF_TRANS_E_S8T2,
345 DDI_BUF_TRANS_E_S9T1,
346 DDI_BUF_TRANS_E_S9T2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]347 AUD_VID_DID,
348 PFA_WIN_POS,
349 PFA_WIN_SZ,
350 PFA_CTL_1,
351 PS_WIN_POS_1_A,
352 PS_WIN_SZ_1_A,
353 PS_CTRL_1_A,
354 PS_WIN_POS_2_A,
355 PS_WIN_SZ_2_A,
356 PS_CTRL_2_A,
357 PFB_WIN_POS,
358 PFB_WIN_SZ,
359 PFB_CTL_1,
360 PS_WIN_POS_1_B,
361 PS_WIN_SZ_1_B,
362 PS_CTRL_1_B,
363 PS_WIN_POS_2_B,
364 PS_WIN_SZ_2_B,
365 PS_CTRL_2_B,
366 PFC_WIN_POS,
367 PFC_WIN_SZ,
368 PFC_CTL_1,
369 PS_WIN_POS_1_C,
370 PS_WIN_SZ_1_C,
371 PS_CTRL_1_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]372 BXT_PORT_CL1CM_DW0_BC,
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]373 DISPIO_CR_TX_BMU_CR0,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]374 BXT_PORT_CL1CM_DW9_BC,
375 BXT_PORT_CL1CM_DW10_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]376 BXT_PORT_PLL_EBB_0_B,
377 BXT_PORT_PLL_EBB_4_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]378 DPLL1_CFGR1,
379 DPLL1_CFGR2,
380 DPLL2_CFGR1,
381 DPLL2_CFGR2,
382 DPLL3_CFGR1,
383 DPLL3_CFGR2,
384 DPLL_CTRL1,
385 DPLL_CTRL2,
386 DPLL_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]387 BXT_PORT_CL1CM_DW28_BC,
388 BXT_PORT_CL1CM_DW30_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]389 BXT_PORT_PLL_0_B,
390 BXT_PORT_PLL_1_B,
391 BXT_PORT_PLL_2_B,
392 BXT_PORT_PLL_3_B,
393 BXT_PORT_PLL_6_B,
394 BXT_PORT_PLL_8_B,
395 BXT_PORT_PLL_9_B,
396 BXT_PORT_PLL_10_B,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]397 BXT_PORT_REF_DW3_BC,
398 BXT_PORT_REF_DW6_BC,
399 BXT_PORT_REF_DW8_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]400 BXT_PORT_PLL_EBB_0_C,
401 BXT_PORT_PLL_EBB_4_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]402 BXT_PORT_CL2CM_DW6_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]403 BXT_PORT_PLL_0_C,
404 BXT_PORT_PLL_1_C,
405 BXT_PORT_PLL_2_C,
406 BXT_PORT_PLL_3_C,
407 BXT_PORT_PLL_6_C,
408 BXT_PORT_PLL_8_C,
409 BXT_PORT_PLL_9_C,
410 BXT_PORT_PLL_10_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]411 BXT_PORT_PCS_DW10_01_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]412 BXT_PORT_PCS_DW12_01_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]413 BXT_PORT_TX_DW2_LN0_B,
414 BXT_PORT_TX_DW3_LN0_B,
415 BXT_PORT_TX_DW4_LN0_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]416 BXT_PORT_TX_DW14_LN0_B,
417 BXT_PORT_TX_DW14_LN1_B,
418 BXT_PORT_TX_DW14_LN2_B,
419 BXT_PORT_TX_DW14_LN3_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]420 BXT_PORT_PCS_DW10_01_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]421 BXT_PORT_PCS_DW12_01_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]422 BXT_PORT_TX_DW2_LN0_C,
423 BXT_PORT_TX_DW3_LN0_C,
424 BXT_PORT_TX_DW4_LN0_C,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]425 BXT_PORT_TX_DW14_LN0_C,
426 BXT_PORT_TX_DW14_LN1_C,
427 BXT_PORT_TX_DW14_LN2_C,
428 BXT_PORT_TX_DW14_LN3_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]429 BXT_PORT_PCS_DW10_GRP_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]430 BXT_PORT_PCS_DW12_GRP_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]431 BXT_PORT_TX_DW2_GRP_B,
432 BXT_PORT_TX_DW3_GRP_B,
433 BXT_PORT_TX_DW4_GRP_B,
434 BXT_PORT_PCS_DW10_GRP_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]435 BXT_PORT_PCS_DW12_GRP_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]436 BXT_PORT_TX_DW2_GRP_C,
437 BXT_PORT_TX_DW3_GRP_C,
438 BXT_PORT_TX_DW4_GRP_C,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]439 BXT_DE_PLL_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]440 HTOTAL_EDP,
441 HBLANK_EDP,
442 HSYNC_EDP,
443 VTOTAL_EDP,
444 VBLANK_EDP,
445 VSYNC_EDP,
446 PIPE_EDP_DATA_M1,
447 PIPE_EDP_DATA_N1,
448 PIPE_EDP_LINK_M1,
449 PIPE_EDP_LINK_N1,
450 PIPE_EDP_DDI_FUNC_CTL,
451 PIPE_EDP_MSA_MISC,
452 SRD_CTL_EDP,
453 SRD_STATUS_EDP,
454 PIPE_SCANLINE_A,
455 PIPEACONF,
456 PIPEAMISC,
457 PIPE_FRMCNT_A,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]458 PIPEA_GMCH_DATA_M,
459 PIPEA_GMCH_DATA_N,
460 PIPEA_GMCH_LINK_M,
461 PIPEA_GMCH_LINK_N,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]462 CUR_CTL_A,
463 CUR_BASE_A,
464 CUR_POS_A,
465 CUR_FBC_CTL_A,
466 CUR_WM_A_0,
467 CUR_WM_A_1,
468 CUR_WM_A_2,
469 CUR_WM_A_3,
470 CUR_WM_A_4,
471 CUR_WM_A_5,
472 CUR_WM_A_6,
473 CUR_WM_A_7,
474 CUR_BUF_CFG_A,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]475 DSPACNTR,
476 DSPALINOFF,
477 DSPASTRIDE,
478 PLANE_POS_1_A,
479 PLANE_SIZE_1_A,
480 DSPASURF,
481 DSPATILEOFF,
482 PLANE_WM_1_A_0,
483 PLANE_WM_1_A_1,
484 PLANE_WM_1_A_2,
485 PLANE_WM_1_A_3,
486 PLANE_WM_1_A_4,
487 PLANE_WM_1_A_5,
488 PLANE_WM_1_A_6,
489 PLANE_WM_1_A_7,
490 PLANE_BUF_CFG_1_A,
491 SPACNTR,
492 PIPE_SCANLINE_B,
493 PIPEBCONF,
494 PIPEBMISC,
495 PIPE_FRMCNT_B,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]496 PIPEB_GMCH_DATA_M,
497 PIPEB_GMCH_DATA_N,
498 PIPEB_GMCH_LINK_M,
499 PIPEB_GMCH_LINK_N,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]500 CUR_CTL_B,
501 CUR_BASE_B,
502 CUR_POS_B,
503 CUR_FBC_CTL_B,
504 CUR_WM_B_0,
505 CUR_WM_B_1,
506 CUR_WM_B_2,
507 CUR_WM_B_3,
508 CUR_WM_B_4,
509 CUR_WM_B_5,
510 CUR_WM_B_6,
511 CUR_WM_B_7,
512 CUR_BUF_CFG_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]513 DSPBCNTR,
514 DSPBLINOFF,
515 DSPBSTRIDE,
516 PLANE_POS_1_B,
517 PLANE_SIZE_1_B,
518 DSPBSURF,
519 DSPBTILEOFF,
520 PLANE_WM_1_B_0,
521 PLANE_WM_1_B_1,
522 PLANE_WM_1_B_2,
523 PLANE_WM_1_B_3,
524 PLANE_WM_1_B_4,
525 PLANE_WM_1_B_5,
526 PLANE_WM_1_B_6,
527 PLANE_WM_1_B_7,
528 PLANE_BUF_CFG_1_B,
529 SPBCNTR,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]530 GMCH_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]531 PIPE_SCANLINE_C,
532 PIPECCONF,
533 PIPECMISC,
534 PIPE_FRMCNT_C,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]535 CUR_CTL_C,
536 CUR_BASE_C,
537 CUR_POS_C,
538 CUR_FBC_CTL_C,
539 CUR_WM_C_0,
540 CUR_WM_C_1,
541 CUR_WM_C_2,
542 CUR_WM_C_3,
543 CUR_WM_C_4,
544 CUR_WM_C_5,
545 CUR_WM_C_6,
546 CUR_WM_C_7,
547 CUR_BUF_CFG_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]548 DSPCCNTR,
549 DSPCLINOFF,
550 DSPCSTRIDE,
551 PLANE_POS_1_C,
552 PLANE_SIZE_1_C,
553 DSPCSURF,
554 DSPCTILEOFF,
555 PLANE_WM_1_C_0,
556 PLANE_WM_1_C_1,
557 PLANE_WM_1_C_2,
558 PLANE_WM_1_C_3,
559 PLANE_WM_1_C_4,
560 PLANE_WM_1_C_5,
561 PLANE_WM_1_C_6,
562 PLANE_WM_1_C_7,
563 PLANE_BUF_CFG_1_C,
564 SPCCNTR,
565 PIPE_EDP_CONF,
566 PCH_FDI_CHICKEN_B_C,
567 QUIRK_C2004,
568 SFUSE_STRAP,
569 PCH_DSPCLK_GATE_D,
570 SDEISR,
571 SDEIMR,
572 SDEIIR,
573 SDEIER,
574 SHOTPLUG_CTL,
575 PCH_GMBUS0,
576 PCH_GMBUS1,
577 PCH_GMBUS2,
578 PCH_GMBUS3,
579 PCH_GMBUS4,
580 PCH_GMBUS5,
581 SBI_ADDR,
582 SBI_DATA,
583 SBI_CTL_STAT,
584 PCH_DPLL_A,
585 PCH_DPLL_B,
586 PCH_PIXCLK_GATE,
587 PCH_FPA0,
588 PCH_FPA1,
589 PCH_FPB0,
590 PCH_FPB1,
591 PCH_DREF_CONTROL,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]592 PCH_RAWCLK_FREQ,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]593 PCH_DPLL_SEL,
594 PCH_PP_STATUS,
595 PCH_PP_CONTROL,
596 PCH_PP_ON_DELAYS,
597 PCH_PP_OFF_DELAYS,
598 PCH_PP_DIVISOR,
599 BLC_PWM_PCH_CTL1,
600 BLC_PWM_PCH_CTL2,
601 TRANS_HTOTAL_A,
602 TRANS_HBLANK_A,
603 TRANS_HSYNC_A,
604 TRANS_VTOTAL_A,
605 TRANS_VBLANK_A,
606 TRANS_VSYNC_A,
607 TRANS_VSYNCSHIFT_A,
608 TRANSA_DATA_M1,
609 TRANSA_DATA_N1,
610 TRANSA_DP_LINK_M1,
611 TRANSA_DP_LINK_N1,
612 TRANS_DP_CTL_A,
613 TRANS_HTOTAL_B,
614 TRANS_HBLANK_B,
615 TRANS_HSYNC_B,
616 TRANS_VTOTAL_B,
617 TRANS_VBLANK_B,
618 TRANS_VSYNC_B,
619 TRANS_VSYNCSHIFT_B,
620 TRANSB_DATA_M1,
621 TRANSB_DATA_N1,
622 TRANSB_DP_LINK_M1,
623 TRANSB_DP_LINK_N1,
624 PCH_ADPA,
625 PCH_HDMIB,
626 PCH_HDMIC,
627 PCH_HDMID,
628 PCH_LVDS,
629 TRANS_DP_CTL_B,
630 TRANS_HTOTAL_C,
631 TRANS_HBLANK_C,
632 TRANS_HSYNC_C,
633 TRANS_VTOTAL_C,
634 TRANS_VBLANK_C,
635 TRANS_VSYNC_C,
636 TRANS_VSYNCSHIFT_C,
637 TRANSC_DATA_M1,
638 TRANSC_DATA_N1,
639 TRANSC_DP_LINK_M1,
640 TRANSC_DP_LINK_N1,
641 TRANS_DP_CTL_C,
642 PCH_DP_B,
643 PCH_DP_AUX_CTL_B,
644 PCH_DP_AUX_DATA_B_1,
645 PCH_DP_AUX_DATA_B_2,
646 PCH_DP_AUX_DATA_B_3,
647 PCH_DP_AUX_DATA_B_4,
648 PCH_DP_AUX_DATA_B_5,
649 PCH_DP_C,
650 PCH_DP_AUX_CTL_C,
651 PCH_DP_AUX_DATA_C_1,
652 PCH_DP_AUX_DATA_C_2,
653 PCH_DP_AUX_DATA_C_3,
654 PCH_DP_AUX_DATA_C_4,
655 PCH_DP_AUX_DATA_C_5,
656 PCH_DP_D,
657 PCH_DP_AUX_CTL_D,
658 PCH_DP_AUX_DATA_D_1,
659 PCH_DP_AUX_DATA_D_2,
660 PCH_DP_AUX_DATA_D_3,
661 PCH_DP_AUX_DATA_D_4,
662 PCH_DP_AUX_DATA_D_5,
663 AUD_CONFIG_A,
664 PCH_AUD_VID_DID,
665 AUD_HDMIW_HDMIEDID_A,
666 AUD_CNTL_ST_A,
667 AUD_CNTRL_ST2,
668 AUD_CONFIG_B,
669 AUD_HDMIW_HDMIEDID_B,
670 AUD_CNTL_ST_B,
671 AUD_CONFIG_C,
672 AUD_HDMIW_HDMIEDID_C,
673 AUD_CNTL_ST_C,
674 TRANSACONF,
675 FDI_RXA_CTL,
676 FDI_RX_MISC_A,
677 FDI_RXA_IIR,
678 FDI_RXA_IMR,
679 FDI_RXA_TUSIZE1,
680 QUIRK_F0060,
681 TRANSA_CHICKEN2,
682 TRANSBCONF,
683 FDI_RXB_CTL,
684 FDI_RX_MISC_B,
685 FDI_RXB_IIR,
686 FDI_RXB_IMR,
687 FDI_RXB_TUSIZE1,
688 QUIRK_F1060,
689 TRANSB_CHICKEN2,
690 TRANSCCONF,
691 FDI_RXC_CTL,
692 FDI_RX_MISC_C,
693 FDI_RXC_IIR,
694 FDI_RXC_IMR,
695 FDI_RXC_TUSIZE1,
696 QUIRK_F2060,
697 TRANSC_CHICKEN2,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]698 BXT_P_CR_GT_DISP_PWRON,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]699 GT_MAILBOX,
700 GT_MAILBOX_DATA,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]701 GT_MAILBOX_DATA_1,
702 BXT_PORT_CL1CM_DW0_A,
703 BXT_PORT_CL1CM_DW9_A,
704 BXT_PORT_CL1CM_DW10_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]705 BXT_PORT_PLL_EBB_0_A,
706 BXT_PORT_PLL_EBB_4_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]707 BXT_PORT_CL1CM_DW28_A,
708 BXT_PORT_CL1CM_DW30_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]709 BXT_PORT_PLL_0_A,
710 BXT_PORT_PLL_1_A,
711 BXT_PORT_PLL_2_A,
712 BXT_PORT_PLL_3_A,
713 BXT_PORT_PLL_6_A,
714 BXT_PORT_PLL_8_A,
715 BXT_PORT_PLL_9_A,
716 BXT_PORT_PLL_10_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]717 BXT_PORT_REF_DW3_A,
718 BXT_PORT_REF_DW6_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]719 BXT_PORT_REF_DW8_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]720 BXT_PORT_PCS_DW10_01_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]721 BXT_PORT_PCS_DW12_01_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]722 BXT_PORT_TX_DW2_LN0_A,
723 BXT_PORT_TX_DW3_LN0_A,
724 BXT_PORT_TX_DW4_LN0_A,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]725 BXT_PORT_TX_DW14_LN0_A,
726 BXT_PORT_TX_DW14_LN1_A,
727 BXT_PORT_TX_DW14_LN2_A,
728 BXT_PORT_TX_DW14_LN3_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]729 BXT_PORT_PCS_DW10_GRP_A,
730 BXT_PORT_PCS_DW12_GRP_A,
731 BXT_PORT_TX_DW2_GRP_A,
732 BXT_PORT_TX_DW3_GRP_A,
733 BXT_PORT_TX_DW4_GRP_A);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]734
735 pragma Warnings
736 (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)",
737 Reason => "TODO: Should it matter?");
738 pragma Keep_Names (Registers_Invalid_Index);
739 pragma Warnings
740 (GNATprove, On, "pragma ""KEEP_NAMES"" ignored *(not yet supported)");
741
742 Register_Width : constant := 4;
743
744 for Registers_Invalid_Index use
745 (Invalid_Register => 0,
746
747 ---------------------------------------------------------------------------
748 -- Pipe A registers
749 ---------------------------------------------------------------------------
750
751 -- pipe timing registers
752
753 HTOTAL_A => 16#06_0000# / Register_Width,
754 HBLANK_A => 16#06_0004# / Register_Width,
755 HSYNC_A => 16#06_0008# / Register_Width,
756 VTOTAL_A => 16#06_000c# / Register_Width,
757 VBLANK_A => 16#06_0010# / Register_Width,
758 VSYNC_A => 16#06_0014# / Register_Width,
759 PIPEASRC => 16#06_001c# / Register_Width,
760 PIPEACONF => 16#07_0008# / Register_Width,
761 PIPEAMISC => 16#07_0030# / Register_Width,
762 TRANS_HTOTAL_A => 16#0e_0000# / Register_Width,
763 TRANS_HBLANK_A => 16#0e_0004# / Register_Width,
764 TRANS_HSYNC_A => 16#0e_0008# / Register_Width,
765 TRANS_VTOTAL_A => 16#0e_000c# / Register_Width,
766 TRANS_VBLANK_A => 16#0e_0010# / Register_Width,
767 TRANS_VSYNC_A => 16#0e_0014# / Register_Width,
768 TRANSA_DATA_M1 => 16#0e_0030# / Register_Width,
769 TRANSA_DATA_N1 => 16#0e_0034# / Register_Width,
770 TRANSA_DP_LINK_M1 => 16#0e_0040# / Register_Width,
771 TRANSA_DP_LINK_N1 => 16#0e_0044# / Register_Width,
772 PIPEA_DATA_M1 => 16#06_0030# / Register_Width,
773 PIPEA_DATA_N1 => 16#06_0034# / Register_Width,
774 PIPEA_LINK_M1 => 16#06_0040# / Register_Width,
775 PIPEA_LINK_N1 => 16#06_0044# / Register_Width,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]776 PIPEA_GMCH_DATA_M => 16#07_0050# / Register_Width,
777 PIPEA_GMCH_DATA_N => 16#07_0054# / Register_Width,
778 PIPEA_GMCH_LINK_M => 16#07_0060# / Register_Width,
779 PIPEA_GMCH_LINK_N => 16#07_0064# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]780 PIPEA_DDI_FUNC_CTL => 16#06_0400# / Register_Width,
781 PIPEA_MSA_MISC => 16#06_0410# / Register_Width,
782
783 -- PCH sideband interface registers
784 SBI_ADDR => 16#0c_6000# / Register_Width,
785 SBI_DATA => 16#0c_6004# / Register_Width,
786 SBI_CTL_STAT => 16#0c_6008# / Register_Width,
787
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]788 -- GMCH clock registers
789 GMCH_DPLL_A => 16#00_6014# / Register_Width,
790 GMCH_FPA0 => 16#00_6040# / Register_Width,
791 GMCH_FPA1 => 16#00_6044# / Register_Width,
792
793 -- PCH clock registers
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]794 PCH_DPLL_A => 16#0c_6014# / Register_Width,
795 PCH_PIXCLK_GATE => 16#0c_6020# / Register_Width,
796 PCH_FPA0 => 16#0c_6040# / Register_Width,
797 PCH_FPA1 => 16#0c_6044# / Register_Width,
798
799 -- panel fitter
800 PFA_CTL_1 => 16#06_8080# / Register_Width,
801 PFA_WIN_POS => 16#06_8070# / Register_Width,
802 PFA_WIN_SZ => 16#06_8074# / Register_Width,
803 PS_WIN_POS_1_A => 16#06_8170# / Register_Width,
804 PS_WIN_SZ_1_A => 16#06_8174# / Register_Width,
805 PS_CTRL_1_A => 16#06_8180# / Register_Width,
806 PS_WIN_POS_2_A => 16#06_8270# / Register_Width,
807 PS_WIN_SZ_2_A => 16#06_8274# / Register_Width,
808 PS_CTRL_2_A => 16#06_8280# / Register_Width,
809
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]810 -- cursor control
811 CUR_CTL_A => 16#07_0080# / Register_Width,
812 CUR_BASE_A => 16#07_0084# / Register_Width,
813 CUR_POS_A => 16#07_0088# / Register_Width,
814 CUR_FBC_CTL_A => 16#07_00a0# / Register_Width,
815
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]816 -- display control
817 DSPACNTR => 16#07_0180# / Register_Width,
818 DSPALINOFF => 16#07_0184# / Register_Width,
819 DSPASTRIDE => 16#07_0188# / Register_Width,
820 PLANE_POS_1_A => 16#07_018c# / Register_Width,
821 PLANE_SIZE_1_A => 16#07_0190# / Register_Width,
822 DSPASURF => 16#07_019c# / Register_Width,
823 DSPATILEOFF => 16#07_01a4# / Register_Width,
824
825 -- sprite control
826 SPACNTR => 16#07_0280# / Register_Width,
827
828 -- FDI and PCH transcoder control
829 FDI_TX_CTL_A => 16#06_0100# / Register_Width,
830 FDI_RXA_CTL => 16#0f_000c# / Register_Width,
831 FDI_RX_MISC_A => 16#0f_0010# / Register_Width,
832 FDI_RXA_IIR => 16#0f_0014# / Register_Width,
833 FDI_RXA_IMR => 16#0f_0018# / Register_Width,
834 FDI_RXA_TUSIZE1 => 16#0f_0030# / Register_Width,
835 TRANSACONF => 16#0f_0008# / Register_Width,
836 TRANSA_CHICKEN2 => 16#0f_0064# / Register_Width,
837
838 -- watermark registers
839 WM_LINETIME_A => 16#04_5270# / Register_Width,
840 PLANE_WM_1_A_0 => 16#07_0240# / Register_Width,
841 PLANE_WM_1_A_1 => 16#07_0244# / Register_Width,
842 PLANE_WM_1_A_2 => 16#07_0248# / Register_Width,
843 PLANE_WM_1_A_3 => 16#07_024c# / Register_Width,
844 PLANE_WM_1_A_4 => 16#07_0250# / Register_Width,
845 PLANE_WM_1_A_5 => 16#07_0254# / Register_Width,
846 PLANE_WM_1_A_6 => 16#07_0258# / Register_Width,
847 PLANE_WM_1_A_7 => 16#07_025c# / Register_Width,
848 PLANE_BUF_CFG_1_A => 16#07_027c# / Register_Width,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]849 CUR_WM_A_0 => 16#07_0140# / Register_Width,
850 CUR_WM_A_1 => 16#07_0144# / Register_Width,
851 CUR_WM_A_2 => 16#07_0148# / Register_Width,
852 CUR_WM_A_3 => 16#07_014c# / Register_Width,
853 CUR_WM_A_4 => 16#07_0150# / Register_Width,
854 CUR_WM_A_5 => 16#07_0154# / Register_Width,
855 CUR_WM_A_6 => 16#07_0158# / Register_Width,
856 CUR_WM_A_7 => 16#07_015c# / Register_Width,
857 CUR_BUF_CFG_A => 16#07_017c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]858
859 -- CPU transcoder clock select
860 TRANSA_CLK_SEL => 16#04_6140# / Register_Width,
861
862 ---------------------------------------------------------------------------
863 -- Pipe B registers
864 ---------------------------------------------------------------------------
865
866 -- pipe timing registers
867
868 HTOTAL_B => 16#06_1000# / Register_Width,
869 HBLANK_B => 16#06_1004# / Register_Width,
870 HSYNC_B => 16#06_1008# / Register_Width,
871 VTOTAL_B => 16#06_100c# / Register_Width,
872 VBLANK_B => 16#06_1010# / Register_Width,
873 VSYNC_B => 16#06_1014# / Register_Width,
874 PIPEBSRC => 16#06_101c# / Register_Width,
875 PIPEBCONF => 16#07_1008# / Register_Width,
876 PIPEBMISC => 16#07_1030# / Register_Width,
877 TRANS_HTOTAL_B => 16#0e_1000# / Register_Width,
878 TRANS_HBLANK_B => 16#0e_1004# / Register_Width,
879 TRANS_HSYNC_B => 16#0e_1008# / Register_Width,
880 TRANS_VTOTAL_B => 16#0e_100c# / Register_Width,
881 TRANS_VBLANK_B => 16#0e_1010# / Register_Width,
882 TRANS_VSYNC_B => 16#0e_1014# / Register_Width,
883 TRANSB_DATA_M1 => 16#0e_1030# / Register_Width,
884 TRANSB_DATA_N1 => 16#0e_1034# / Register_Width,
885 TRANSB_DP_LINK_M1 => 16#0e_1040# / Register_Width,
886 TRANSB_DP_LINK_N1 => 16#0e_1044# / Register_Width,
887 PIPEB_DATA_M1 => 16#06_1030# / Register_Width,
888 PIPEB_DATA_N1 => 16#06_1034# / Register_Width,
889 PIPEB_LINK_M1 => 16#06_1040# / Register_Width,
890 PIPEB_LINK_N1 => 16#06_1044# / Register_Width,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]891 PIPEB_GMCH_DATA_M => 16#07_1050# / Register_Width,
892 PIPEB_GMCH_DATA_N => 16#07_1054# / Register_Width,
893 PIPEB_GMCH_LINK_M => 16#07_1060# / Register_Width,
894 PIPEB_GMCH_LINK_N => 16#07_1064# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]895 PIPEB_DDI_FUNC_CTL => 16#06_1400# / Register_Width,
896 PIPEB_MSA_MISC => 16#06_1410# / Register_Width,
897
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]898 -- GMCH clock registers
899 GMCH_DPLL_B => 16#00_6018# / Register_Width,
900 GMCH_FPB0 => 16#00_6048# / Register_Width,
901 GMCH_FPB1 => 16#00_604c# / Register_Width,
902
903 -- PCH clock registers
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]904 PCH_DPLL_B => 16#0c_6018# / Register_Width,
905 PCH_FPB0 => 16#0c_6048# / Register_Width,
906 PCH_FPB1 => 16#0c_604c# / Register_Width,
907
908 -- panel fitter
909 PFB_CTL_1 => 16#06_8880# / Register_Width,
910 PFB_WIN_POS => 16#06_8870# / Register_Width,
911 PFB_WIN_SZ => 16#06_8874# / Register_Width,
912 PS_WIN_POS_1_B => 16#06_8970# / Register_Width,
913 PS_WIN_SZ_1_B => 16#06_8974# / Register_Width,
914 PS_CTRL_1_B => 16#06_8980# / Register_Width,
915 PS_WIN_POS_2_B => 16#06_8a70# / Register_Width,
916 PS_WIN_SZ_2_B => 16#06_8a74# / Register_Width,
917 PS_CTRL_2_B => 16#06_8a80# / Register_Width,
918
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]919 -- cursor control
920 CUR_CTL_B => 16#07_1080# / Register_Width,
921 CUR_BASE_B => 16#07_1084# / Register_Width,
922 CUR_POS_B => 16#07_1088# / Register_Width,
923 CUR_FBC_CTL_B => 16#07_10a0# / Register_Width,
924
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]925 -- display control
926 DSPBCNTR => 16#07_1180# / Register_Width,
927 DSPBLINOFF => 16#07_1184# / Register_Width,
928 DSPBSTRIDE => 16#07_1188# / Register_Width,
929 PLANE_POS_1_B => 16#07_118c# / Register_Width,
930 PLANE_SIZE_1_B => 16#07_1190# / Register_Width,
931 DSPBSURF => 16#07_119c# / Register_Width,
932 DSPBTILEOFF => 16#07_11a4# / Register_Width,
933
934 -- sprite control
935 SPBCNTR => 16#07_1280# / Register_Width,
936
937 -- FDI and PCH transcoder control
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]938 FDI_TX_CTL_B => 16#06_1100# / Register_Width, -- aliased by GMCH_ADPA
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]939 FDI_RXB_CTL => 16#0f_100c# / Register_Width,
940 FDI_RX_MISC_B => 16#0f_1010# / Register_Width,
941 FDI_RXB_IIR => 16#0f_1014# / Register_Width,
942 FDI_RXB_IMR => 16#0f_1018# / Register_Width,
943 FDI_RXB_TUSIZE1 => 16#0f_1030# / Register_Width,
944 TRANSBCONF => 16#0f_1008# / Register_Width,
945 TRANSB_CHICKEN2 => 16#0f_1064# / Register_Width,
946
947 -- watermark registers
948 WM_LINETIME_B => 16#04_5274# / Register_Width,
949 PLANE_WM_1_B_0 => 16#07_1240# / Register_Width,
950 PLANE_WM_1_B_1 => 16#07_1244# / Register_Width,
951 PLANE_WM_1_B_2 => 16#07_1248# / Register_Width,
952 PLANE_WM_1_B_3 => 16#07_124c# / Register_Width,
953 PLANE_WM_1_B_4 => 16#07_1250# / Register_Width,
954 PLANE_WM_1_B_5 => 16#07_1254# / Register_Width,
955 PLANE_WM_1_B_6 => 16#07_1258# / Register_Width,
956 PLANE_WM_1_B_7 => 16#07_125c# / Register_Width,
957 PLANE_BUF_CFG_1_B => 16#07_127c# / Register_Width,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]958 CUR_WM_B_0 => 16#07_1140# / Register_Width,
959 CUR_WM_B_1 => 16#07_1144# / Register_Width,
960 CUR_WM_B_2 => 16#07_1148# / Register_Width,
961 CUR_WM_B_3 => 16#07_114c# / Register_Width,
962 CUR_WM_B_4 => 16#07_1150# / Register_Width,
963 CUR_WM_B_5 => 16#07_1154# / Register_Width,
964 CUR_WM_B_6 => 16#07_1158# / Register_Width,
965 CUR_WM_B_7 => 16#07_115c# / Register_Width,
966 CUR_BUF_CFG_B => 16#07_117c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]967
968 -- CPU transcoder clock select
969 TRANSB_CLK_SEL => 16#04_6144# / Register_Width,
970
971 ---------------------------------------------------------------------------
972 -- Pipe C registers
973 ---------------------------------------------------------------------------
974
975 -- pipe timing registers
976
977 HTOTAL_C => 16#06_2000# / Register_Width,
978 HBLANK_C => 16#06_2004# / Register_Width,
979 HSYNC_C => 16#06_2008# / Register_Width,
980 VTOTAL_C => 16#06_200c# / Register_Width,
981 VBLANK_C => 16#06_2010# / Register_Width,
982 VSYNC_C => 16#06_2014# / Register_Width,
983 PIPECSRC => 16#06_201c# / Register_Width,
984 PIPECCONF => 16#07_2008# / Register_Width,
985 PIPECMISC => 16#07_2030# / Register_Width,
986 TRANS_HTOTAL_C => 16#0e_2000# / Register_Width,
987 TRANS_HBLANK_C => 16#0e_2004# / Register_Width,
988 TRANS_HSYNC_C => 16#0e_2008# / Register_Width,
989 TRANS_VTOTAL_C => 16#0e_200c# / Register_Width,
990 TRANS_VBLANK_C => 16#0e_2010# / Register_Width,
991 TRANS_VSYNC_C => 16#0e_2014# / Register_Width,
992 TRANSC_DATA_M1 => 16#0e_2030# / Register_Width,
993 TRANSC_DATA_N1 => 16#0e_2034# / Register_Width,
994 TRANSC_DP_LINK_M1 => 16#0e_2040# / Register_Width,
995 TRANSC_DP_LINK_N1 => 16#0e_2044# / Register_Width,
996 PIPEC_DATA_M1 => 16#06_2030# / Register_Width,
997 PIPEC_DATA_N1 => 16#06_2034# / Register_Width,
998 PIPEC_LINK_M1 => 16#06_2040# / Register_Width,
999 PIPEC_LINK_N1 => 16#06_2044# / Register_Width,
1000 PIPEC_DDI_FUNC_CTL => 16#06_2400# / Register_Width,
1001 PIPEC_MSA_MISC => 16#06_2410# / Register_Width,
1002
1003 -- panel fitter
1004 PFC_CTL_1 => 16#06_9080# / Register_Width,
1005 PFC_WIN_POS => 16#06_9070# / Register_Width,
1006 PFC_WIN_SZ => 16#06_9074# / Register_Width,
1007 PS_WIN_POS_1_C => 16#06_9170# / Register_Width,
1008 PS_WIN_SZ_1_C => 16#06_9174# / Register_Width,
1009 PS_CTRL_1_C => 16#06_9180# / Register_Width,
1010
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1011 -- cursor control
1012 CUR_CTL_C => 16#07_2080# / Register_Width,
1013 CUR_BASE_C => 16#07_2084# / Register_Width,
1014 CUR_POS_C => 16#07_2088# / Register_Width,
1015 CUR_FBC_CTL_C => 16#07_20a0# / Register_Width,
1016
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1017 -- display control
1018 DSPCCNTR => 16#07_2180# / Register_Width,
1019 DSPCLINOFF => 16#07_2184# / Register_Width,
1020 DSPCSTRIDE => 16#07_2188# / Register_Width,
1021 PLANE_POS_1_C => 16#07_218c# / Register_Width,
1022 PLANE_SIZE_1_C => 16#07_2190# / Register_Width,
1023 DSPCSURF => 16#07_219c# / Register_Width,
1024 DSPCTILEOFF => 16#07_21a4# / Register_Width,
1025
1026 -- sprite control
1027 SPCCNTR => 16#07_2280# / Register_Width,
1028
1029 -- PCH transcoder control
1030 FDI_TX_CTL_C => 16#06_2100# / Register_Width,
1031 FDI_RXC_CTL => 16#0f_200c# / Register_Width,
1032 FDI_RX_MISC_C => 16#0f_2010# / Register_Width,
1033 FDI_RXC_IIR => 16#0f_2014# / Register_Width,
1034 FDI_RXC_IMR => 16#0f_2018# / Register_Width,
1035 FDI_RXC_TUSIZE1 => 16#0f_2030# / Register_Width,
1036 TRANSCCONF => 16#0f_2008# / Register_Width,
1037 TRANSC_CHICKEN2 => 16#0f_2064# / Register_Width,
1038
1039 -- watermark registers
1040 WM_LINETIME_C => 16#04_5278# / Register_Width,
1041 PLANE_WM_1_C_0 => 16#07_2240# / Register_Width,
1042 PLANE_WM_1_C_1 => 16#07_2244# / Register_Width,
1043 PLANE_WM_1_C_2 => 16#07_2248# / Register_Width,
1044 PLANE_WM_1_C_3 => 16#07_224c# / Register_Width,
1045 PLANE_WM_1_C_4 => 16#07_2250# / Register_Width,
1046 PLANE_WM_1_C_5 => 16#07_2254# / Register_Width,
1047 PLANE_WM_1_C_6 => 16#07_2258# / Register_Width,
1048 PLANE_WM_1_C_7 => 16#07_225c# / Register_Width,
1049 PLANE_BUF_CFG_1_C => 16#07_227c# / Register_Width,
Nico Huber4dc4c612018-01-10 15:55:09 +0100[diff] [blame]1050 CUR_WM_C_0 => 16#07_2140# / Register_Width,
1051 CUR_WM_C_1 => 16#07_2144# / Register_Width,
1052 CUR_WM_C_2 => 16#07_2148# / Register_Width,
1053 CUR_WM_C_3 => 16#07_214c# / Register_Width,
1054 CUR_WM_C_4 => 16#07_2150# / Register_Width,
1055 CUR_WM_C_5 => 16#07_2154# / Register_Width,
1056 CUR_WM_C_6 => 16#07_2158# / Register_Width,
1057 CUR_WM_C_7 => 16#07_215c# / Register_Width,
1058 CUR_BUF_CFG_C => 16#07_217c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1059
1060 -- CPU transcoder clock select
1061 TRANSC_CLK_SEL => 16#04_6148# / Register_Width,
1062
1063 ---------------------------------------------------------------------------
1064 -- Pipe EDP registers
1065 ---------------------------------------------------------------------------
1066
1067 -- pipe timing registers
1068
1069 HTOTAL_EDP => 16#06_f000# / Register_Width,
1070 HBLANK_EDP => 16#06_f004# / Register_Width,
1071 HSYNC_EDP => 16#06_f008# / Register_Width,
1072 VTOTAL_EDP => 16#06_f00c# / Register_Width,
1073 VBLANK_EDP => 16#06_f010# / Register_Width,
1074 VSYNC_EDP => 16#06_f014# / Register_Width,
1075 PIPE_EDP_CONF => 16#07_f008# / Register_Width,
1076 PIPE_EDP_DATA_M1 => 16#06_f030# / Register_Width,
1077 PIPE_EDP_DATA_N1 => 16#06_f034# / Register_Width,
1078 PIPE_EDP_LINK_M1 => 16#06_f040# / Register_Width,
1079 PIPE_EDP_LINK_N1 => 16#06_f044# / Register_Width,
1080 PIPE_EDP_DDI_FUNC_CTL => 16#06_f400# / Register_Width,
1081 PIPE_EDP_MSA_MISC => 16#06_f410# / Register_Width,
1082
1083 -- PSR registers
1084 SRD_CTL => 16#06_4800# / Register_Width,
1085 SRD_CTL_A => 16#06_0800# / Register_Width,
1086 SRD_CTL_B => 16#06_1800# / Register_Width,
1087 SRD_CTL_C => 16#06_2800# / Register_Width,
1088 SRD_CTL_EDP => 16#06_f800# / Register_Width,
1089 SRD_STATUS => 16#06_4840# / Register_Width,
1090 SRD_STATUS_A => 16#06_0840# / Register_Width,
1091 SRD_STATUS_B => 16#06_1840# / Register_Width,
1092 SRD_STATUS_C => 16#06_2840# / Register_Width,
1093 SRD_STATUS_EDP => 16#06_f840# / Register_Width,
1094
1095 -- DDI registers
1096 DDI_BUF_CTL_A => 16#06_4000# / Register_Width, -- aliased by DP_CTL_A
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1097 DDI_BUF_TRANS_A_S0T1 => 16#06_4e00# / Register_Width,
1098 DDI_BUF_TRANS_A_S0T2 => 16#06_4e04# / Register_Width,
1099 DDI_BUF_TRANS_A_S1T1 => 16#06_4e08# / Register_Width,
1100 DDI_BUF_TRANS_A_S1T2 => 16#06_4e0c# / Register_Width,
1101 DDI_BUF_TRANS_A_S2T1 => 16#06_4e10# / Register_Width,
1102 DDI_BUF_TRANS_A_S2T2 => 16#06_4e14# / Register_Width,
1103 DDI_BUF_TRANS_A_S3T1 => 16#06_4e18# / Register_Width,
1104 DDI_BUF_TRANS_A_S3T2 => 16#06_4e1c# / Register_Width,
1105 DDI_BUF_TRANS_A_S4T1 => 16#06_4e20# / Register_Width,
1106 DDI_BUF_TRANS_A_S4T2 => 16#06_4e24# / Register_Width,
1107 DDI_BUF_TRANS_A_S5T1 => 16#06_4e28# / Register_Width,
1108 DDI_BUF_TRANS_A_S5T2 => 16#06_4e2c# / Register_Width,
1109 DDI_BUF_TRANS_A_S6T1 => 16#06_4e30# / Register_Width,
1110 DDI_BUF_TRANS_A_S6T2 => 16#06_4e34# / Register_Width,
1111 DDI_BUF_TRANS_A_S7T1 => 16#06_4e38# / Register_Width,
1112 DDI_BUF_TRANS_A_S7T2 => 16#06_4e3c# / Register_Width,
1113 DDI_BUF_TRANS_A_S8T1 => 16#06_4e40# / Register_Width,
1114 DDI_BUF_TRANS_A_S8T2 => 16#06_4e44# / Register_Width,
1115 DDI_BUF_TRANS_A_S9T1 => 16#06_4e48# / Register_Width,
1116 DDI_BUF_TRANS_A_S9T2 => 16#06_4e4c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1117 DDI_AUX_CTL_A => 16#06_4010# / Register_Width, -- aliased by DP_AUX_CTL_A
1118 DDI_AUX_DATA_A_1 => 16#06_4014# / Register_Width, -- aliased by DP_AUX_DATA_A_1
1119 DDI_AUX_DATA_A_2 => 16#06_4018# / Register_Width, -- aliased by DP_AUX_DATA_A_2
1120 DDI_AUX_DATA_A_3 => 16#06_401c# / Register_Width, -- aliased by DP_AUX_DATA_A_3
1121 DDI_AUX_DATA_A_4 => 16#06_4020# / Register_Width, -- aliased by DP_AUX_DATA_A_4
1122 DDI_AUX_DATA_A_5 => 16#06_4024# / Register_Width, -- aliased by DP_AUX_DATA_A_5
1123 DDI_AUX_MUTEX_A => 16#06_402c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1124
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1125 DDI_BUF_CTL_B => 16#06_4100# / Register_Width, -- aliased by GMCH_DP_B
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1126 DDI_BUF_TRANS_B_S0T1 => 16#06_4e60# / Register_Width,
1127 DDI_BUF_TRANS_B_S0T2 => 16#06_4e64# / Register_Width,
1128 DDI_BUF_TRANS_B_S1T1 => 16#06_4e68# / Register_Width,
1129 DDI_BUF_TRANS_B_S1T2 => 16#06_4e6c# / Register_Width,
1130 DDI_BUF_TRANS_B_S2T1 => 16#06_4e70# / Register_Width,
1131 DDI_BUF_TRANS_B_S2T2 => 16#06_4e74# / Register_Width,
1132 DDI_BUF_TRANS_B_S3T1 => 16#06_4e78# / Register_Width,
1133 DDI_BUF_TRANS_B_S3T2 => 16#06_4e7c# / Register_Width,
1134 DDI_BUF_TRANS_B_S4T1 => 16#06_4e80# / Register_Width,
1135 DDI_BUF_TRANS_B_S4T2 => 16#06_4e84# / Register_Width,
1136 DDI_BUF_TRANS_B_S5T1 => 16#06_4e88# / Register_Width,
1137 DDI_BUF_TRANS_B_S5T2 => 16#06_4e8c# / Register_Width,
1138 DDI_BUF_TRANS_B_S6T1 => 16#06_4e90# / Register_Width,
1139 DDI_BUF_TRANS_B_S6T2 => 16#06_4e94# / Register_Width,
1140 DDI_BUF_TRANS_B_S7T1 => 16#06_4e98# / Register_Width,
1141 DDI_BUF_TRANS_B_S7T2 => 16#06_4e9c# / Register_Width,
1142 DDI_BUF_TRANS_B_S8T1 => 16#06_4ea0# / Register_Width,
1143 DDI_BUF_TRANS_B_S8T2 => 16#06_4ea4# / Register_Width,
1144 DDI_BUF_TRANS_B_S9T1 => 16#06_4ea8# / Register_Width,
1145 DDI_BUF_TRANS_B_S9T2 => 16#06_4eac# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1146 DDI_AUX_CTL_B => 16#06_4110# / Register_Width,
1147 DDI_AUX_DATA_B_1 => 16#06_4114# / Register_Width,
1148 DDI_AUX_DATA_B_2 => 16#06_4118# / Register_Width,
1149 DDI_AUX_DATA_B_3 => 16#06_411c# / Register_Width,
1150 DDI_AUX_DATA_B_4 => 16#06_4120# / Register_Width,
1151 DDI_AUX_DATA_B_5 => 16#06_4124# / Register_Width,
1152 DDI_AUX_MUTEX_B => 16#06_412c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1153
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1154 DDI_BUF_CTL_C => 16#06_4200# / Register_Width, -- aliased by GMCH_DP_C
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1155 DDI_BUF_TRANS_C_S0T1 => 16#06_4ec0# / Register_Width,
1156 DDI_BUF_TRANS_C_S0T2 => 16#06_4ec4# / Register_Width,
1157 DDI_BUF_TRANS_C_S1T1 => 16#06_4ec8# / Register_Width,
1158 DDI_BUF_TRANS_C_S1T2 => 16#06_4ecc# / Register_Width,
1159 DDI_BUF_TRANS_C_S2T1 => 16#06_4ed0# / Register_Width,
1160 DDI_BUF_TRANS_C_S2T2 => 16#06_4ed4# / Register_Width,
1161 DDI_BUF_TRANS_C_S3T1 => 16#06_4ed8# / Register_Width,
1162 DDI_BUF_TRANS_C_S3T2 => 16#06_4edc# / Register_Width,
1163 DDI_BUF_TRANS_C_S4T1 => 16#06_4ee0# / Register_Width,
1164 DDI_BUF_TRANS_C_S4T2 => 16#06_4ee4# / Register_Width,
1165 DDI_BUF_TRANS_C_S5T1 => 16#06_4ee8# / Register_Width,
1166 DDI_BUF_TRANS_C_S5T2 => 16#06_4eec# / Register_Width,
1167 DDI_BUF_TRANS_C_S6T1 => 16#06_4ef0# / Register_Width,
1168 DDI_BUF_TRANS_C_S6T2 => 16#06_4ef4# / Register_Width,
1169 DDI_BUF_TRANS_C_S7T1 => 16#06_4ef8# / Register_Width,
1170 DDI_BUF_TRANS_C_S7T2 => 16#06_4efc# / Register_Width,
1171 DDI_BUF_TRANS_C_S8T1 => 16#06_4f00# / Register_Width,
1172 DDI_BUF_TRANS_C_S8T2 => 16#06_4f04# / Register_Width,
1173 DDI_BUF_TRANS_C_S9T1 => 16#06_4f08# / Register_Width,
1174 DDI_BUF_TRANS_C_S9T2 => 16#06_4f0c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1175 DDI_AUX_CTL_C => 16#06_4210# / Register_Width,
1176 DDI_AUX_DATA_C_1 => 16#06_4214# / Register_Width,
1177 DDI_AUX_DATA_C_2 => 16#06_4218# / Register_Width,
1178 DDI_AUX_DATA_C_3 => 16#06_421c# / Register_Width,
1179 DDI_AUX_DATA_C_4 => 16#06_4220# / Register_Width,
1180 DDI_AUX_DATA_C_5 => 16#06_4224# / Register_Width,
1181 DDI_AUX_MUTEX_C => 16#06_422c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1182
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1183 DDI_BUF_CTL_D => 16#06_4300# / Register_Width, -- aliased by GMCH_DP_D
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1184 DDI_BUF_TRANS_D_S0T1 => 16#06_4f20# / Register_Width,
1185 DDI_BUF_TRANS_D_S0T2 => 16#06_4f24# / Register_Width,
1186 DDI_BUF_TRANS_D_S1T1 => 16#06_4f28# / Register_Width,
1187 DDI_BUF_TRANS_D_S1T2 => 16#06_4f2c# / Register_Width,
1188 DDI_BUF_TRANS_D_S2T1 => 16#06_4f30# / Register_Width,
1189 DDI_BUF_TRANS_D_S2T2 => 16#06_4f34# / Register_Width,
1190 DDI_BUF_TRANS_D_S3T1 => 16#06_4f38# / Register_Width,
1191 DDI_BUF_TRANS_D_S3T2 => 16#06_4f3c# / Register_Width,
1192 DDI_BUF_TRANS_D_S4T1 => 16#06_4f40# / Register_Width,
1193 DDI_BUF_TRANS_D_S4T2 => 16#06_4f44# / Register_Width,
1194 DDI_BUF_TRANS_D_S5T1 => 16#06_4f48# / Register_Width,
1195 DDI_BUF_TRANS_D_S5T2 => 16#06_4f4c# / Register_Width,
1196 DDI_BUF_TRANS_D_S6T1 => 16#06_4f50# / Register_Width,
1197 DDI_BUF_TRANS_D_S6T2 => 16#06_4f54# / Register_Width,
1198 DDI_BUF_TRANS_D_S7T1 => 16#06_4f58# / Register_Width,
1199 DDI_BUF_TRANS_D_S7T2 => 16#06_4f5c# / Register_Width,
1200 DDI_BUF_TRANS_D_S8T1 => 16#06_4f60# / Register_Width,
1201 DDI_BUF_TRANS_D_S8T2 => 16#06_4f64# / Register_Width,
1202 DDI_BUF_TRANS_D_S9T1 => 16#06_4f68# / Register_Width,
1203 DDI_BUF_TRANS_D_S9T2 => 16#06_4f6c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1204 DDI_AUX_CTL_D => 16#06_4310# / Register_Width,
1205 DDI_AUX_DATA_D_1 => 16#06_4314# / Register_Width,
1206 DDI_AUX_DATA_D_2 => 16#06_4318# / Register_Width,
1207 DDI_AUX_DATA_D_3 => 16#06_431c# / Register_Width,
1208 DDI_AUX_DATA_D_4 => 16#06_4320# / Register_Width,
1209 DDI_AUX_DATA_D_5 => 16#06_4324# / Register_Width,
1210 DDI_AUX_MUTEX_D => 16#06_432c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1211
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1212 DDI_BUF_CTL_E => 16#06_4400# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1213 DDI_BUF_TRANS_E_S0T1 => 16#06_4f80# / Register_Width,
1214 DDI_BUF_TRANS_E_S0T2 => 16#06_4f84# / Register_Width,
1215 DDI_BUF_TRANS_E_S1T1 => 16#06_4f88# / Register_Width,
1216 DDI_BUF_TRANS_E_S1T2 => 16#06_4f8c# / Register_Width,
1217 DDI_BUF_TRANS_E_S2T1 => 16#06_4f90# / Register_Width,
1218 DDI_BUF_TRANS_E_S2T2 => 16#06_4f94# / Register_Width,
1219 DDI_BUF_TRANS_E_S3T1 => 16#06_4f98# / Register_Width,
1220 DDI_BUF_TRANS_E_S3T2 => 16#06_4f9c# / Register_Width,
1221 DDI_BUF_TRANS_E_S4T1 => 16#06_4fa0# / Register_Width,
1222 DDI_BUF_TRANS_E_S4T2 => 16#06_4fa4# / Register_Width,
1223 DDI_BUF_TRANS_E_S5T1 => 16#06_4fa8# / Register_Width,
1224 DDI_BUF_TRANS_E_S5T2 => 16#06_4fac# / Register_Width,
1225 DDI_BUF_TRANS_E_S6T1 => 16#06_4fb0# / Register_Width,
1226 DDI_BUF_TRANS_E_S6T2 => 16#06_4fb4# / Register_Width,
1227 DDI_BUF_TRANS_E_S7T1 => 16#06_4fb8# / Register_Width,
1228 DDI_BUF_TRANS_E_S7T2 => 16#06_4fbc# / Register_Width,
1229 DDI_BUF_TRANS_E_S8T1 => 16#06_4fc0# / Register_Width,
1230 DDI_BUF_TRANS_E_S8T2 => 16#06_4fc4# / Register_Width,
1231 DDI_BUF_TRANS_E_S9T1 => 16#06_4fc8# / Register_Width,
1232 DDI_BUF_TRANS_E_S9T2 => 16#06_4fcc# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1233 DP_TP_CTL_A => 16#06_4040# / Register_Width,
1234 DP_TP_CTL_B => 16#06_4140# / Register_Width,
1235 DP_TP_CTL_C => 16#06_4240# / Register_Width,
1236 DP_TP_CTL_D => 16#06_4340# / Register_Width,
1237 DP_TP_CTL_E => 16#06_4440# / Register_Width,
1238 DP_TP_STATUS_B => 16#06_4144# / Register_Width,
1239 DP_TP_STATUS_C => 16#06_4244# / Register_Width,
1240 DP_TP_STATUS_D => 16#06_4344# / Register_Width,
1241 DP_TP_STATUS_E => 16#06_4444# / Register_Width,
1242 PORT_CLK_SEL_DDIA => 16#04_6100# / Register_Width,
1243 PORT_CLK_SEL_DDIB => 16#04_6104# / Register_Width,
1244 PORT_CLK_SEL_DDIC => 16#04_6108# / Register_Width,
1245 PORT_CLK_SEL_DDID => 16#04_610c# / Register_Width,
1246 PORT_CLK_SEL_DDIE => 16#04_6110# / Register_Width,
1247
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]1248 -- Skylake I_boost configuration
1249 DISPIO_CR_TX_BMU_CR0 => 16#06_c00c# / Register_Width,
1250
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1251 -- Skylake DPLL registers
1252 DPLL1_CFGR1 => 16#06_c040# / Register_Width,
1253 DPLL1_CFGR2 => 16#06_c044# / Register_Width,
1254 DPLL2_CFGR1 => 16#06_c048# / Register_Width,
1255 DPLL2_CFGR2 => 16#06_c04c# / Register_Width,
1256 DPLL3_CFGR1 => 16#06_c050# / Register_Width,
1257 DPLL3_CFGR2 => 16#06_c054# / Register_Width,
1258 DPLL_CTRL1 => 16#06_c058# / Register_Width,
1259 DPLL_CTRL2 => 16#06_c05c# / Register_Width,
1260 DPLL_STATUS => 16#06_c060# / Register_Width,
1261
1262 -- CD CLK register
1263 CDCLK_CTL => 16#04_6000# / Register_Width,
1264
1265 -- Skylake LCPLL registers
1266 LCPLL1_CTL => 16#04_6010# / Register_Width,
1267 LCPLL2_CTL => 16#04_6014# / Register_Width,
1268
1269 -- SPLL register
1270 SPLL_CTL => 16#04_6020# / Register_Width,
1271
1272 -- WRPLL registers
1273 WRPLL_CTL_1 => 16#04_6040# / Register_Width,
1274 WRPLL_CTL_2 => 16#04_6060# / Register_Width,
1275
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]1276 -- Broxton Display Engine PLL registers
1277 BXT_DE_PLL_CTL => 16#06_d000# / Register_Width,
1278 BXT_DE_PLL_ENABLE => 16#04_6070# / Register_Width,
1279
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1280 -- Broxton DDI PHY PLL registers
1281 BXT_PORT_PLL_ENABLE_A => 16#04_6074# / Register_Width,
1282 BXT_PORT_PLL_ENABLE_B => 16#04_6078# / Register_Width,
1283 BXT_PORT_PLL_ENABLE_C => 16#04_607c# / Register_Width,
1284 BXT_PORT_PLL_EBB_0_A => 16#16_2034# / Register_Width,
1285 BXT_PORT_PLL_EBB_4_A => 16#16_2038# / Register_Width,
1286 BXT_PORT_PLL_0_A => 16#16_2100# / Register_Width,
1287 BXT_PORT_PLL_1_A => 16#16_2104# / Register_Width,
1288 BXT_PORT_PLL_2_A => 16#16_2108# / Register_Width,
1289 BXT_PORT_PLL_3_A => 16#16_210c# / Register_Width,
1290 BXT_PORT_PLL_6_A => 16#16_2118# / Register_Width,
1291 BXT_PORT_PLL_8_A => 16#16_2120# / Register_Width,
1292 BXT_PORT_PLL_9_A => 16#16_2124# / Register_Width,
1293 BXT_PORT_PLL_10_A => 16#16_2128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1294 BXT_PORT_PLL_EBB_0_B => 16#06_c034# / Register_Width,
1295 BXT_PORT_PLL_EBB_4_B => 16#06_c038# / Register_Width,
1296 BXT_PORT_PLL_0_B => 16#06_c100# / Register_Width,
1297 BXT_PORT_PLL_1_B => 16#06_c104# / Register_Width,
1298 BXT_PORT_PLL_2_B => 16#06_c108# / Register_Width,
1299 BXT_PORT_PLL_3_B => 16#06_c10c# / Register_Width,
1300 BXT_PORT_PLL_6_B => 16#06_c118# / Register_Width,
1301 BXT_PORT_PLL_8_B => 16#06_c120# / Register_Width,
1302 BXT_PORT_PLL_9_B => 16#06_c124# / Register_Width,
1303 BXT_PORT_PLL_10_B => 16#06_c128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1304 BXT_PORT_PLL_EBB_0_C => 16#06_c340# / Register_Width,
1305 BXT_PORT_PLL_EBB_4_C => 16#06_c344# / Register_Width,
1306 BXT_PORT_PLL_0_C => 16#06_c380# / Register_Width,
1307 BXT_PORT_PLL_1_C => 16#06_c384# / Register_Width,
1308 BXT_PORT_PLL_2_C => 16#06_c388# / Register_Width,
1309 BXT_PORT_PLL_3_C => 16#06_c38c# / Register_Width,
1310 BXT_PORT_PLL_6_C => 16#06_c398# / Register_Width,
1311 BXT_PORT_PLL_8_C => 16#06_c3a0# / Register_Width,
1312 BXT_PORT_PLL_9_C => 16#06_c3a4# / Register_Width,
1313 BXT_PORT_PLL_10_C => 16#06_c3a8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1314
1315 -- Broxton DDI PHY PCS? registers
1316 BXT_PORT_PCS_DW10_01_A => 16#16_2428# / Register_Width,
1317 BXT_PORT_PCS_DW12_01_A => 16#16_2430# / Register_Width,
1318 BXT_PORT_PCS_DW10_GRP_A => 16#16_2c28# / Register_Width,
1319 BXT_PORT_PCS_DW12_GRP_A => 16#16_2c30# / Register_Width,
1320 BXT_PORT_PCS_DW10_01_B => 16#06_c428# / Register_Width,
1321 BXT_PORT_PCS_DW12_01_B => 16#06_c430# / Register_Width,
1322 BXT_PORT_PCS_DW10_01_C => 16#06_c828# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1323 BXT_PORT_PCS_DW12_01_C => 16#06_c830# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1324 BXT_PORT_PCS_DW10_GRP_B => 16#06_cc28# / Register_Width,
1325 BXT_PORT_PCS_DW12_GRP_B => 16#06_cc30# / Register_Width,
1326 BXT_PORT_PCS_DW10_GRP_C => 16#06_ce28# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1327 BXT_PORT_PCS_DW12_GRP_C => 16#06_ce30# / Register_Width,
1328
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1329 -- Broxton DDI PHY registers
1330 BXT_P_CR_GT_DISP_PWRON => 16#13_8090# / Register_Width,
1331 BXT_PHY_CTL_A => 16#06_4c00# / Register_Width,
1332 BXT_PHY_CTL_B => 16#06_4c10# / Register_Width,
1333 BXT_PHY_CTL_C => 16#06_4c20# / Register_Width,
1334 BXT_PHY_CTL_FAM_EDP => 16#06_4c80# / Register_Width,
1335 BXT_PHY_CTL_FAM_DDI => 16#06_4c90# / Register_Width,
1336
1337 -- Broxton DDI PHY common lane registers
1338 BXT_PORT_CL1CM_DW0_A => 16#16_2000# / Register_Width,
1339 BXT_PORT_CL1CM_DW0_BC => 16#06_c000# / Register_Width,
1340 BXT_PORT_CL1CM_DW9_A => 16#16_2024# / Register_Width,
1341 BXT_PORT_CL1CM_DW9_BC => 16#06_c024# / Register_Width,
1342 BXT_PORT_CL1CM_DW10_A => 16#16_2028# / Register_Width,
1343 BXT_PORT_CL1CM_DW10_BC => 16#06_c028# / Register_Width,
1344 BXT_PORT_CL1CM_DW28_A => 16#16_2070# / Register_Width,
1345 BXT_PORT_CL1CM_DW28_BC => 16#06_c070# / Register_Width,
1346 BXT_PORT_CL1CM_DW30_A => 16#16_2078# / Register_Width,
1347 BXT_PORT_CL1CM_DW30_BC => 16#06_c078# / Register_Width,
1348 BXT_PORT_CL2CM_DW6_BC => 16#06_c358# / Register_Width,
1349
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1350 -- Broxton DDI PHY TX lane registers
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1351 BXT_PORT_TX_DW2_LN0_A => 16#16_2508# / Register_Width,
1352 BXT_PORT_TX_DW3_LN0_A => 16#16_250c# / Register_Width,
1353 BXT_PORT_TX_DW4_LN0_A => 16#16_2510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1354 BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width,
1355 BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width,
1356 BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width,
1357 BXT_PORT_TX_DW14_LN3_A => 16#16_27b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1358 BXT_PORT_TX_DW2_GRP_A => 16#16_2d08# / Register_Width,
1359 BXT_PORT_TX_DW3_GRP_A => 16#16_2d0c# / Register_Width,
1360 BXT_PORT_TX_DW4_GRP_A => 16#16_2d10# / Register_Width,
1361 BXT_PORT_TX_DW2_LN0_B => 16#06_c508# / Register_Width,
1362 BXT_PORT_TX_DW3_LN0_B => 16#06_c50c# / Register_Width,
1363 BXT_PORT_TX_DW4_LN0_B => 16#06_c510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1364 BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width,
1365 BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width,
1366 BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width,
1367 BXT_PORT_TX_DW14_LN3_B => 16#06_c7b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1368 BXT_PORT_TX_DW2_GRP_B => 16#06_cd08# / Register_Width,
1369 BXT_PORT_TX_DW3_GRP_B => 16#06_cd0c# / Register_Width,
1370 BXT_PORT_TX_DW4_GRP_B => 16#06_cd10# / Register_Width,
1371 BXT_PORT_TX_DW2_LN0_C => 16#06_c908# / Register_Width,
1372 BXT_PORT_TX_DW3_LN0_C => 16#06_c90c# / Register_Width,
1373 BXT_PORT_TX_DW4_LN0_C => 16#06_c910# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1374 BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width,
1375 BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width,
1376 BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width,
1377 BXT_PORT_TX_DW14_LN3_C => 16#06_cbb8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1378 BXT_PORT_TX_DW2_GRP_C => 16#06_cf08# / Register_Width,
1379 BXT_PORT_TX_DW3_GRP_C => 16#06_cf0c# / Register_Width,
1380 BXT_PORT_TX_DW4_GRP_C => 16#06_cf10# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1381
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1382 -- Broxton DDI PHY ref registers
1383 BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width,
1384 BXT_PORT_REF_DW3_BC => 16#06_c18c# / Register_Width,
1385 BXT_PORT_REF_DW6_A => 16#16_2198# / Register_Width,
1386 BXT_PORT_REF_DW6_BC => 16#06_c198# / Register_Width,
1387 BXT_PORT_REF_DW8_A => 16#16_21a0# / Register_Width,
1388 BXT_PORT_REF_DW8_BC => 16#06_c1a0# / Register_Width,
1389
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1390 -- Power Down Well registers
1391 PWR_WELL_CTL_BIOS => 16#04_5400# / Register_Width,
1392 PWR_WELL_CTL_DRIVER => 16#04_5404# / Register_Width,
1393 PWR_WELL_CTL_KVMR => 16#04_5408# / Register_Width,
1394 PWR_WELL_CTL_DEBUG => 16#04_540c# / Register_Width,
1395 PWR_WELL_CTL5 => 16#04_5410# / Register_Width,
1396 PWR_WELL_CTL6 => 16#04_5414# / Register_Width,
1397
1398 -- class Panel registers
Arthur Heymanse87d0d12018-03-28 17:02:49 +0200[diff] [blame]1399 GMCH_PP_STATUS => 16#06_1200# / Register_Width,
1400 GMCH_PP_CONTROL => 16#06_1204# / Register_Width,
1401 GMCH_PP_ON_DELAYS => 16#06_1208# / Register_Width,
1402 GMCH_PP_OFF_DELAYS => 16#06_120c# / Register_Width,
1403 GMCH_PP_DIVISOR => 16#06_1210# / Register_Width,
Arthur Heymansd5198442018-03-28 17:05:12 +0200[diff] [blame]1404 GMCH_PFIT_CONTROL => 16#06_1230# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1405 PCH_PP_STATUS => 16#0c_7200# / Register_Width,
1406 PCH_PP_CONTROL => 16#0c_7204# / Register_Width,
1407 PCH_PP_ON_DELAYS => 16#0c_7208# / Register_Width,
1408 PCH_PP_OFF_DELAYS => 16#0c_720c# / Register_Width,
1409 PCH_PP_DIVISOR => 16#0c_7210# / Register_Width,
1410 BLC_PWM_CPU_CTL => 16#04_8254# / Register_Width,
1411 BLC_PWM_PCH_CTL2 => 16#0c_8254# / Register_Width,
1412
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1413 -- GMCH LVDS Connector Registers
1414 GMCH_LVDS => 16#06_1180# / Register_Width,
1415
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1416 -- PCH LVDS Connector Registers
1417 PCH_LVDS => 16#0e_1180# / Register_Width,
1418
1419 -- PCH ADPA Connector Registers
1420 PCH_ADPA => 16#0e_1100# / Register_Width,
1421
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1422 -- GMCH DVOB Connector Registers
1423 GMCH_SDVOB => 16#06_1140# / Register_Width,
1424
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1425 -- PCH HDMIB Connector Registers
1426 PCH_HDMIB => 16#0e_1140# / Register_Width,
1427
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1428 -- GMCH DVOC Connector Registers
1429 GMCH_SDVOC => 16#06_1160# / Register_Width,
1430
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1431 -- PCH HDMIC Connector Registers
1432 PCH_HDMIC => 16#0e_1150# / Register_Width,
1433
1434 -- PCH HDMID Connector Registers
1435 PCH_HDMID => 16#0e_1160# / Register_Width,
1436
1437 -- Intel Registers
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]1438 CPU_VGACNTRL => 16#04_1000# / Register_Width,
1439 GMCH_VGACNTRL => 16#07_1400# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1440 FUSE_STATUS => 16#04_2000# / Register_Width,
1441 FBA_CFB_BASE => 16#04_3200# / Register_Width,
1442 IPS_CTL => 16#04_3408# / Register_Width,
1443 ARB_CTL => 16#04_5000# / Register_Width,
1444 DBUF_CTL => 16#04_5008# / Register_Width,
1445 NDE_RSTWRN_OPT => 16#04_6408# / Register_Width,
1446 PCH_DREF_CONTROL => 16#0c_6200# / Register_Width,
1447 BLC_PWM_PCH_CTL1 => 16#0c_8250# / Register_Width,
1448 BLC_PWM_CPU_CTL2 => 16#04_8250# / Register_Width,
1449 PCH_DPLL_SEL => 16#0c_7000# / Register_Width,
1450 GT_MAILBOX => 16#13_8124# / Register_Width,
1451 GT_MAILBOX_DATA => 16#13_8128# / Register_Width,
1452 GT_MAILBOX_DATA_1 => 16#13_812c# / Register_Width,
1453
1454 PCH_DP_B => 16#0e_4100# / Register_Width,
1455 PCH_DP_AUX_CTL_B => 16#0e_4110# / Register_Width,
1456 PCH_DP_AUX_DATA_B_1 => 16#0e_4114# / Register_Width,
1457 PCH_DP_AUX_DATA_B_2 => 16#0e_4118# / Register_Width,
1458 PCH_DP_AUX_DATA_B_3 => 16#0e_411c# / Register_Width,
1459 PCH_DP_AUX_DATA_B_4 => 16#0e_4120# / Register_Width,
1460 PCH_DP_AUX_DATA_B_5 => 16#0e_4124# / Register_Width,
1461 PCH_DP_C => 16#0e_4200# / Register_Width,
1462 PCH_DP_AUX_CTL_C => 16#0e_4210# / Register_Width,
1463 PCH_DP_AUX_DATA_C_1 => 16#0e_4214# / Register_Width,
1464 PCH_DP_AUX_DATA_C_2 => 16#0e_4218# / Register_Width,
1465 PCH_DP_AUX_DATA_C_3 => 16#0e_421c# / Register_Width,
1466 PCH_DP_AUX_DATA_C_4 => 16#0e_4220# / Register_Width,
1467 PCH_DP_AUX_DATA_C_5 => 16#0e_4224# / Register_Width,
1468 PCH_DP_D => 16#0e_4300# / Register_Width,
1469 PCH_DP_AUX_CTL_D => 16#0e_4310# / Register_Width,
1470 PCH_DP_AUX_DATA_D_1 => 16#0e_4314# / Register_Width,
1471 PCH_DP_AUX_DATA_D_2 => 16#0e_4318# / Register_Width,
1472 PCH_DP_AUX_DATA_D_3 => 16#0e_431c# / Register_Width,
1473 PCH_DP_AUX_DATA_D_4 => 16#0e_4320# / Register_Width,
1474 PCH_DP_AUX_DATA_D_5 => 16#0e_4324# / Register_Width,
1475
1476 -- watermark registers
1477 WM1_LP_ILK => 16#04_5108# / Register_Width,
1478 WM2_LP_ILK => 16#04_510c# / Register_Width,
1479 WM3_LP_ILK => 16#04_5110# / Register_Width,
1480
1481 -- audio VID/DID
1482 AUD_VID_DID => 16#06_5020# / Register_Width,
1483 PCH_AUD_VID_DID => 16#0e_5020# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1484 G4X_AUD_VID_DID => 16#06_2020# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1485
1486 -- interrupt registers
1487 DEISR => 16#04_4000# / Register_Width,
1488 DEIMR => 16#04_4004# / Register_Width,
1489 DEIIR => 16#04_4008# / Register_Width,
1490 DEIER => 16#04_400c# / Register_Width,
1491 GTISR => 16#04_4010# / Register_Width,
1492 GTIMR => 16#04_4014# / Register_Width,
1493 GTIIR => 16#04_4018# / Register_Width,
1494 GTIER => 16#04_401c# / Register_Width,
1495 SDEISR => 16#0c_4000# / Register_Width,
1496 SDEIMR => 16#0c_4004# / Register_Width,
1497 SDEIIR => 16#0c_4008# / Register_Width,
1498 SDEIER => 16#0c_400c# / Register_Width,
1499
1500 -- I2C stuff
Arthur Heymans229ed1c2018-03-28 16:45:43 +0200[diff] [blame]1501 GMCH_GMBUS0 => 16#00_5100# / Register_Width,
1502 GMCH_GMBUS1 => 16#00_5104# / Register_Width,
1503 GMCH_GMBUS2 => 16#00_5108# / Register_Width,
1504 GMCH_GMBUS3 => 16#00_510c# / Register_Width,
1505 GMCH_GMBUS4 => 16#00_5110# / Register_Width,
1506 GMCH_GMBUS5 => 16#00_5120# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1507 PCH_GMBUS0 => 16#0c_5100# / Register_Width,
1508 PCH_GMBUS1 => 16#0c_5104# / Register_Width,
1509 PCH_GMBUS2 => 16#0c_5108# / Register_Width,
1510 PCH_GMBUS3 => 16#0c_510c# / Register_Width,
1511 PCH_GMBUS4 => 16#0c_5110# / Register_Width,
1512 PCH_GMBUS5 => 16#0c_5120# / Register_Width,
1513
1514 -- clock gating -- maybe have to touch this
1515 DSPCLK_GATE_D => 16#04_2020# / Register_Width,
1516 PCH_FDI_CHICKEN_B_C => 16#0c_2000# / Register_Width,
1517 PCH_DSPCLK_GATE_D => 16#0c_2020# / Register_Width,
1518
1519 -- hotplug and initial detection
1520 HOTPLUG_CTL => 16#04_4030# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1521 PORT_HOTPLUG_EN => 16#06_1110# / Register_Width,
1522 PORT_HOTPLUG_STAT => 16#06_1114# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1523 SHOTPLUG_CTL => 16#0c_4030# / Register_Width,
1524 SFUSE_STRAP => 16#0c_2014# / Register_Width,
1525
1526 -- Render Engine Command Streamer
1527 ARB_MODE => 16#00_4030# / Register_Width,
1528 HWS_PGA => 16#00_4080# / Register_Width,
1529 RCS_RING_BUFFER_TAIL => 16#00_2030# / Register_Width,
1530 VCS_RING_BUFFER_TAIL => 16#01_2030# / Register_Width,
1531 BCS_RING_BUFFER_TAIL => 16#02_2030# / Register_Width,
1532 RCS_RING_BUFFER_HEAD => 16#00_2034# / Register_Width,
1533 VCS_RING_BUFFER_HEAD => 16#01_2034# / Register_Width,
1534 BCS_RING_BUFFER_HEAD => 16#02_2034# / Register_Width,
1535 RCS_RING_BUFFER_STRT => 16#00_2038# / Register_Width,
1536 VCS_RING_BUFFER_STRT => 16#01_2038# / Register_Width,
1537 BCS_RING_BUFFER_STRT => 16#02_2038# / Register_Width,
1538 RCS_RING_BUFFER_CTL => 16#00_203c# / Register_Width,
1539 VCS_RING_BUFFER_CTL => 16#01_203c# / Register_Width,
1540 BCS_RING_BUFFER_CTL => 16#02_203c# / Register_Width,
1541 MI_MODE => 16#00_209c# / Register_Width,
1542 INSTPM => 16#00_20c0# / Register_Width,
1543 GAB_CTL_REG => 16#02_4000# / Register_Width,
1544 PP_DCLV_HIGH => 16#00_2220# / Register_Width,
1545 PP_DCLV_LOW => 16#00_2228# / Register_Width,
1546 VCS_PP_DCLV_HIGH => 16#01_2220# / Register_Width,
1547 VCS_PP_DCLV_LOW => 16#01_2228# / Register_Width,
1548 BCS_PP_DCLV_HIGH => 16#02_2220# / Register_Width,
1549 BCS_PP_DCLV_LOW => 16#02_2228# / Register_Width,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1550 ILK_DISPLAY_CHICKEN2 => 16#04_2004# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1551 UCGCTL1 => 16#00_9400# / Register_Width,
1552 UCGCTL2 => 16#00_9404# / Register_Width,
1553 MBCTL => 16#00_907c# / Register_Width,
1554 HWSTAM => 16#00_2098# / Register_Width,
1555 VCS_HWSTAM => 16#01_2098# / Register_Width,
1556 BCS_HWSTAM => 16#02_2098# / Register_Width,
1557 IIR => 16#04_4028# / Register_Width,
1558 PIPE_FRMCNT_A => 16#07_0040# / Register_Width,
1559 PIPE_FRMCNT_B => 16#07_1040# / Register_Width,
1560 PIPE_FRMCNT_C => 16#07_2040# / Register_Width,
1561 FBC_CTL => 16#04_3208# / Register_Width,
1562 PIPE_VSYNCSHIFT_A => 16#06_0028# / Register_Width,
1563 PIPE_VSYNCSHIFT_B => 16#06_1028# / Register_Width,
1564 PIPE_VSYNCSHIFT_C => 16#06_2028# / Register_Width,
1565 WM_PIPE_A => 16#04_5100# / Register_Width,
1566 WM_PIPE_B => 16#04_5104# / Register_Width,
1567 WM_PIPE_C => 16#04_5200# / Register_Width,
1568 PIPE_SCANLINE_A => 16#07_0000# / Register_Width,
1569 PIPE_SCANLINE_B => 16#07_1000# / Register_Width,
1570 PIPE_SCANLINE_C => 16#07_2000# / Register_Width,
1571 GFX_MODE => 16#00_2520# / Register_Width,
1572 CACHE_MODE_0 => 16#00_2120# / Register_Width,
1573 SLEEP_PSMI_CONTROL => 16#01_2050# / Register_Width,
1574 CTX_SIZE => 16#00_21a0# / Register_Width,
1575 GAC_ECO_BITS => 16#01_4090# / Register_Width,
1576 GAM_ECOCHK => 16#00_4090# / Register_Width,
1577 QUIRK_02084 => 16#00_2084# / Register_Width,
1578 QUIRK_02090 => 16#00_2090# / Register_Width,
1579 GT_MODE => 16#00_20d0# / Register_Width,
1580 QUIRK_F0060 => 16#0f_0060# / Register_Width,
1581 QUIRK_F1060 => 16#0f_1060# / Register_Width,
1582 QUIRK_F2060 => 16#0f_2060# / Register_Width,
1583 AUD_CNTRL_ST2 => 16#0e_50c0# / Register_Width,
1584 AUD_CNTL_ST_A => 16#0e_50b4# / Register_Width,
1585 AUD_CNTL_ST_B => 16#0e_51b4# / Register_Width,
1586 AUD_CNTL_ST_C => 16#0e_52b4# / Register_Width,
1587 AUD_HDMIW_HDMIEDID_A => 16#0e_5050# / Register_Width,
1588 AUD_HDMIW_HDMIEDID_B => 16#0e_5150# / Register_Width,
1589 AUD_HDMIW_HDMIEDID_C => 16#0e_5250# / Register_Width,
1590 AUD_CONFIG_A => 16#0e_5000# / Register_Width,
1591 AUD_CONFIG_B => 16#0e_5100# / Register_Width,
1592 AUD_CONFIG_C => 16#0e_5200# / Register_Width,
1593 TRANS_DP_CTL_A => 16#0e_0300# / Register_Width,
1594 TRANS_DP_CTL_B => 16#0e_1300# / Register_Width,
1595 TRANS_DP_CTL_C => 16#0e_2300# / Register_Width,
1596 TRANS_VSYNCSHIFT_A => 16#0e_0028# / Register_Width,
1597 TRANS_VSYNCSHIFT_B => 16#0e_1028# / Register_Width,
1598 TRANS_VSYNCSHIFT_C => 16#0e_2028# / Register_Width,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]1599 PCH_RAWCLK_FREQ => 16#0c_6204# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1600 QUIRK_C2004 => 16#0c_2004# / Register_Width,
1601
1602 -- MCHBAR Mirror
1603
1604 GMCH_CLKCFG => 16#01_0c00# / Register_Width);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1605
1606 subtype Registers_Index is Registers_Invalid_Index range
1607 Registers_Invalid_Index'Succ (Invalid_Register) ..
1608 Registers_Invalid_Index'Last;
1609
1610 -- aliased registers
1611 DP_CTL_A : constant Registers_Index := DDI_BUF_CTL_A;
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1612 GMCH_DP_B : constant Registers_Index := DDI_BUF_CTL_B;
1613 GMCH_DP_C : constant Registers_Index := DDI_BUF_CTL_C;
1614 GMCH_DP_D : constant Registers_Index := DDI_BUF_CTL_D;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1615 DP_AUX_CTL_A : constant Registers_Index := DDI_AUX_CTL_A;
1616 DP_AUX_DATA_A_1 : constant Registers_Index := DDI_AUX_DATA_A_1;
1617 DP_AUX_DATA_A_2 : constant Registers_Index := DDI_AUX_DATA_A_2;
1618 DP_AUX_DATA_A_3 : constant Registers_Index := DDI_AUX_DATA_A_3;
1619 DP_AUX_DATA_A_4 : constant Registers_Index := DDI_AUX_DATA_A_4;
1620 DP_AUX_DATA_A_5 : constant Registers_Index := DDI_AUX_DATA_A_5;
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1621 ILK_DISPLAY_CHICKEN1 : constant Registers_Index := FUSE_STATUS;
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1622 GMCH_ADPA : constant Registers_Index := FDI_TX_CTL_B;
1623 GMCH_HDMIB : constant Registers_Index := GMCH_SDVOB;
1624 GMCH_HDMIC : constant Registers_Index := GMCH_SDVOC;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1625
1626 ---------------------------------------------------------------------------
1627
1628 Default_Timeout_MS : constant := 10;
1629
1630 ---------------------------------------------------------------------------
1631
1632 procedure Posting_Read
1633 (Register : in Registers_Index)
1634 with
1635 Global => (In_Out => Register_State),
1636 Depends => (Register_State =>+ (Register)),
1637 Pre => True,
1638 Post => True;
1639
1640 pragma Warnings (GNATprove, Off, "unused variable ""Verbose""",
1641 Reason => "Only used on debugging path");
1642 procedure Read
1643 (Register : in Registers_Index;
1644 Value : out Word32;
1645 Verbose : in Boolean := True)
1646 with
1647 Global => (In_Out => Register_State),
1648 Depends => ((Value, Register_State) => (Register, Register_State),
1649 null => Verbose),
1650 Pre => True,
1651 Post => True;
1652 pragma Warnings (GNATprove, On, "unused variable ""Verbose""");
1653
1654 procedure Write
1655 (Register : Registers_Index;
1656 Value : Word32)
1657 with
1658 Global => (In_Out => Register_State),
1659 Depends => (Register_State => (Register, Register_State, Value)),
1660 Pre => True,
1661 Post => True;
1662
1663 procedure Is_Set_Mask
1664 (Register : in Registers_Index;
1665 Mask : in Word32;
1666 Result : out Boolean);
1667
1668 pragma Warnings (GNATprove, Off, "unused initial value of ""Verbose""",
1669 Reason => "Only used on debugging path");
Nico Huberbcb2c472017-02-02 16:39:26 +0100[diff] [blame]1670 procedure Wait
1671 (Register : Registers_Index;
1672 Mask : Word32;
1673 Value : Word32;
1674 TOut_MS : Natural := Default_Timeout_MS;
1675 Verbose : Boolean := False);
1676
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1677 procedure Wait_Set_Mask
1678 (Register : Registers_Index;
1679 Mask : Word32;
1680 TOut_MS : Natural := Default_Timeout_MS;
1681 Verbose : Boolean := False);
1682
1683 procedure Wait_Unset_Mask
1684 (Register : Registers_Index;
1685 Mask : Word32;
1686 TOut_MS : Natural := Default_Timeout_MS;
1687 Verbose : Boolean := False);
1688 pragma Warnings (GNATprove, On, "unused initial value of ""Verbose""");
1689
1690 procedure Set_Mask
1691 (Register : Registers_Index;
1692 Mask : Word32);
1693
1694 procedure Unset_Mask
1695 (Register : Registers_Index;
1696 Mask : Word32);
1697
1698 procedure Unset_And_Set_Mask
1699 (Register : Registers_Index;
1700 Mask_Unset : Word32;
1701 Mask_Set : Word32);
1702
Nico Huber17d64b62017-07-15 20:51:25 +0200[diff] [blame]1703 procedure Clear_Fences;
1704
Nico Huberb03c8f12017-08-25 13:29:08 +0200[diff] [blame]1705 procedure Add_Fence
1706 (First_Page : in GTT_Range;
1707 Last_Page : in GTT_Range;
1708 Tiling : in XY_Tiling;
1709 Pitch : in Natural;
1710 Success : out Boolean);
1711
1712 procedure Remove_Fence (First_Page, Last_Page : GTT_Range);
1713
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1714 pragma Warnings (Off, "declaration of ""Write_GTT"" hides one at *");
1715 procedure Write_GTT
1716 (GTT_Page : GTT_Range;
1717 Device_Address : GTT_Address_Type;
1718 Valid : Boolean)
1719 with
1720 Global => (In_Out => GTT_State),
1721 Depends => (GTT_State =>+ (GTT_Page, Device_Address, Valid)),
1722 Pre => True,
1723 Post => True;
1724 pragma Warnings (On, "declaration of ""Write_GTT"" hides one at *");
1725
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]1726 procedure Set_Register_Base (Base : Word64; GTT_Base : Word64 := 0)
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1727 with
1728 Global => (Output => Address_State),
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]1729 Depends => (Address_State => (Base, GTT_Base)),
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1730 Pre => True,
1731 Post => True;
1732
1733end HW.GFX.GMA.Registers;