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review.sourcearcade.org / libgfxinit / a02b2c699b736a97773c2e8ca17aa2886a72131c / . / common / hw-gfx-gma-registers.ads
blob: da100ce2aea248dda1fce12ac258071a87ce49a5 [file] [log] [blame]
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1--
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]2-- Copyright (C) 2015-2017 secunet Security Networks AG
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +0200[diff] [blame]6-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]8--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
15with System;
16with HW.GFX.GMA;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]17
18private package HW.GFX.GMA.Registers
19with
20 Abstract_State =>
21 ((Address_State with Part_Of => GMA.State),
22 (Register_State with External, Part_Of => GMA.Device_State),
23 (GTT_State with External, Part_Of => GMA.Device_State)),
24 Initializes => Address_State
25is
26 type Registers_Invalid_Index is
27 (Invalid_Register, -- Allow a placeholder when access is not acceptable
28
29 RCS_RING_BUFFER_TAIL,
30 RCS_RING_BUFFER_HEAD,
31 RCS_RING_BUFFER_STRT,
32 RCS_RING_BUFFER_CTL,
33 QUIRK_02084,
34 QUIRK_02090,
35 HWSTAM,
36 MI_MODE,
37 INSTPM,
38 GT_MODE,
39 CACHE_MODE_0,
40 CTX_SIZE,
41 PP_DCLV_HIGH,
42 PP_DCLV_LOW,
43 GFX_MODE,
44 ARB_MODE,
45 HWS_PGA,
46 GAM_ECOCHK,
Arthur Heymans229ed1c2018-03-28 16:45:43 +0200[diff] [blame]47 GMCH_GMBUS0,
48 GMCH_GMBUS1,
49 GMCH_GMBUS2,
50 GMCH_GMBUS3,
51 GMCH_GMBUS4,
52 GMCH_GMBUS5,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]53 GMCH_DPLL_A,
54 GMCH_DPLL_B,
55 GMCH_FPA0,
56 GMCH_FPA1,
57 GMCH_FPB0,
58 GMCH_FPB1,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]59 MBCTL,
60 UCGCTL1,
61 UCGCTL2,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]62 GMCH_CLKCFG,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]63 VCS_RING_BUFFER_TAIL,
64 VCS_RING_BUFFER_HEAD,
65 VCS_RING_BUFFER_STRT,
66 VCS_RING_BUFFER_CTL,
67 SLEEP_PSMI_CONTROL,
68 VCS_HWSTAM,
69 VCS_PP_DCLV_HIGH,
70 VCS_PP_DCLV_LOW,
71 GAC_ECO_BITS,
72 BCS_RING_BUFFER_TAIL,
73 BCS_RING_BUFFER_HEAD,
74 BCS_RING_BUFFER_STRT,
75 BCS_RING_BUFFER_CTL,
76 BCS_HWSTAM,
77 BCS_PP_DCLV_HIGH,
78 BCS_PP_DCLV_LOW,
79 GAB_CTL_REG,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]80 CPU_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]81 FUSE_STATUS,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]82 ILK_DISPLAY_CHICKEN2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]83 DSPCLK_GATE_D,
84 FBA_CFB_BASE,
85 FBC_CTL,
86 IPS_CTL,
87 DEISR,
88 DEIMR,
89 DEIIR,
90 DEIER,
91 GTISR,
92 GTIMR,
93 GTIIR,
94 GTIER,
95 IIR,
96 HOTPLUG_CTL,
97 ARB_CTL,
98 DBUF_CTL,
99 WM_PIPE_A,
100 WM_PIPE_B,
101 WM1_LP_ILK,
102 WM2_LP_ILK,
103 WM3_LP_ILK,
104 WM_PIPE_C,
105 WM_LINETIME_A,
106 WM_LINETIME_B,
107 WM_LINETIME_C,
108 PWR_WELL_CTL_BIOS,
109 PWR_WELL_CTL_DRIVER,
110 PWR_WELL_CTL_KVMR,
111 PWR_WELL_CTL_DEBUG,
112 PWR_WELL_CTL5,
113 PWR_WELL_CTL6,
114 CDCLK_CTL,
115 LCPLL1_CTL,
116 LCPLL2_CTL,
117 SPLL_CTL,
118 WRPLL_CTL_1,
119 WRPLL_CTL_2,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]120 BXT_DE_PLL_ENABLE,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]121 BXT_PORT_PLL_ENABLE_A,
122 BXT_PORT_PLL_ENABLE_B,
123 BXT_PORT_PLL_ENABLE_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]124 PORT_CLK_SEL_DDIA,
125 PORT_CLK_SEL_DDIB,
126 PORT_CLK_SEL_DDIC,
127 PORT_CLK_SEL_DDID,
128 PORT_CLK_SEL_DDIE,
129 TRANSA_CLK_SEL,
130 TRANSB_CLK_SEL,
131 TRANSC_CLK_SEL,
132 NDE_RSTWRN_OPT,
133 BLC_PWM_CPU_CTL2,
134 BLC_PWM_CPU_CTL,
135 HTOTAL_A,
136 HBLANK_A,
137 HSYNC_A,
138 VTOTAL_A,
139 VBLANK_A,
140 VSYNC_A,
141 PIPEASRC,
142 PIPE_VSYNCSHIFT_A,
143 PIPEA_DATA_M1,
144 PIPEA_DATA_N1,
145 PIPEA_LINK_M1,
146 PIPEA_LINK_N1,
147 FDI_TX_CTL_A,
148 PIPEA_DDI_FUNC_CTL,
149 PIPEA_MSA_MISC,
150 SRD_CTL_A,
151 SRD_STATUS_A,
152 HTOTAL_B,
153 HBLANK_B,
154 HSYNC_B,
155 VTOTAL_B,
156 VBLANK_B,
157 VSYNC_B,
158 PIPEBSRC,
159 PIPE_VSYNCSHIFT_B,
160 PIPEB_DATA_M1,
161 PIPEB_DATA_N1,
162 PIPEB_LINK_M1,
163 PIPEB_LINK_N1,
164 FDI_TX_CTL_B,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]165 PORT_HOTPLUG_EN,
166 PORT_HOTPLUG_STAT,
167 GMCH_SDVOB,
168 GMCH_SDVOC,
169 GMCH_LVDS,
Arthur Heymanse87d0d12018-03-28 17:02:49 +0200[diff] [blame]170 GMCH_PP_STATUS,
171 GMCH_PP_CONTROL,
172 GMCH_PP_ON_DELAYS,
173 GMCH_PP_OFF_DELAYS,
174 GMCH_PP_DIVISOR,
Arthur Heymansd5198442018-03-28 17:05:12 +0200[diff] [blame]175 GMCH_PFIT_CONTROL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]176 PIPEB_DDI_FUNC_CTL,
177 PIPEB_MSA_MISC,
178 SRD_CTL_B,
179 SRD_STATUS_B,
180 HTOTAL_C,
181 HBLANK_C,
182 HSYNC_C,
183 VTOTAL_C,
184 VBLANK_C,
185 VSYNC_C,
186 PIPECSRC,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]187 G4X_AUD_VID_DID,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]188 PIPE_VSYNCSHIFT_C,
189 PIPEC_DATA_M1,
190 PIPEC_DATA_N1,
191 PIPEC_LINK_M1,
192 PIPEC_LINK_N1,
193 FDI_TX_CTL_C,
194 PIPEC_DDI_FUNC_CTL,
195 PIPEC_MSA_MISC,
196 SRD_CTL_C,
197 SRD_STATUS_C,
198 DDI_BUF_CTL_A,
199 DDI_AUX_CTL_A,
200 DDI_AUX_DATA_A_1,
201 DDI_AUX_DATA_A_2,
202 DDI_AUX_DATA_A_3,
203 DDI_AUX_DATA_A_4,
204 DDI_AUX_DATA_A_5,
205 DDI_AUX_MUTEX_A,
206 DP_TP_CTL_A,
207 DDI_BUF_CTL_B,
208 DDI_AUX_CTL_B,
209 DDI_AUX_DATA_B_1,
210 DDI_AUX_DATA_B_2,
211 DDI_AUX_DATA_B_3,
212 DDI_AUX_DATA_B_4,
213 DDI_AUX_DATA_B_5,
214 DDI_AUX_MUTEX_B,
215 DP_TP_CTL_B,
216 DP_TP_STATUS_B,
217 DDI_BUF_CTL_C,
218 DDI_AUX_CTL_C,
219 DDI_AUX_DATA_C_1,
220 DDI_AUX_DATA_C_2,
221 DDI_AUX_DATA_C_3,
222 DDI_AUX_DATA_C_4,
223 DDI_AUX_DATA_C_5,
224 DDI_AUX_MUTEX_C,
225 DP_TP_CTL_C,
226 DP_TP_STATUS_C,
227 DDI_BUF_CTL_D,
228 DDI_AUX_CTL_D,
229 DDI_AUX_DATA_D_1,
230 DDI_AUX_DATA_D_2,
231 DDI_AUX_DATA_D_3,
232 DDI_AUX_DATA_D_4,
233 DDI_AUX_DATA_D_5,
234 DDI_AUX_MUTEX_D,
235 DP_TP_CTL_D,
236 DP_TP_STATUS_D,
237 DDI_BUF_CTL_E,
238 DP_TP_CTL_E,
239 DP_TP_STATUS_E,
240 SRD_CTL,
241 SRD_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]242 BXT_PHY_CTL_A,
243 BXT_PHY_CTL_B,
244 BXT_PHY_CTL_C,
245 BXT_PHY_CTL_FAM_EDP,
246 BXT_PHY_CTL_FAM_DDI,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]247 DDI_BUF_TRANS_A_S0T1,
248 DDI_BUF_TRANS_A_S0T2,
249 DDI_BUF_TRANS_A_S1T1,
250 DDI_BUF_TRANS_A_S1T2,
251 DDI_BUF_TRANS_A_S2T1,
252 DDI_BUF_TRANS_A_S2T2,
253 DDI_BUF_TRANS_A_S3T1,
254 DDI_BUF_TRANS_A_S3T2,
255 DDI_BUF_TRANS_A_S4T1,
256 DDI_BUF_TRANS_A_S4T2,
257 DDI_BUF_TRANS_A_S5T1,
258 DDI_BUF_TRANS_A_S5T2,
259 DDI_BUF_TRANS_A_S6T1,
260 DDI_BUF_TRANS_A_S6T2,
261 DDI_BUF_TRANS_A_S7T1,
262 DDI_BUF_TRANS_A_S7T2,
263 DDI_BUF_TRANS_A_S8T1,
264 DDI_BUF_TRANS_A_S8T2,
265 DDI_BUF_TRANS_A_S9T1,
266 DDI_BUF_TRANS_A_S9T2,
267 DDI_BUF_TRANS_B_S0T1,
268 DDI_BUF_TRANS_B_S0T2,
269 DDI_BUF_TRANS_B_S1T1,
270 DDI_BUF_TRANS_B_S1T2,
271 DDI_BUF_TRANS_B_S2T1,
272 DDI_BUF_TRANS_B_S2T2,
273 DDI_BUF_TRANS_B_S3T1,
274 DDI_BUF_TRANS_B_S3T2,
275 DDI_BUF_TRANS_B_S4T1,
276 DDI_BUF_TRANS_B_S4T2,
277 DDI_BUF_TRANS_B_S5T1,
278 DDI_BUF_TRANS_B_S5T2,
279 DDI_BUF_TRANS_B_S6T1,
280 DDI_BUF_TRANS_B_S6T2,
281 DDI_BUF_TRANS_B_S7T1,
282 DDI_BUF_TRANS_B_S7T2,
283 DDI_BUF_TRANS_B_S8T1,
284 DDI_BUF_TRANS_B_S8T2,
285 DDI_BUF_TRANS_B_S9T1,
286 DDI_BUF_TRANS_B_S9T2,
287 DDI_BUF_TRANS_C_S0T1,
288 DDI_BUF_TRANS_C_S0T2,
289 DDI_BUF_TRANS_C_S1T1,
290 DDI_BUF_TRANS_C_S1T2,
291 DDI_BUF_TRANS_C_S2T1,
292 DDI_BUF_TRANS_C_S2T2,
293 DDI_BUF_TRANS_C_S3T1,
294 DDI_BUF_TRANS_C_S3T2,
295 DDI_BUF_TRANS_C_S4T1,
296 DDI_BUF_TRANS_C_S4T2,
297 DDI_BUF_TRANS_C_S5T1,
298 DDI_BUF_TRANS_C_S5T2,
299 DDI_BUF_TRANS_C_S6T1,
300 DDI_BUF_TRANS_C_S6T2,
301 DDI_BUF_TRANS_C_S7T1,
302 DDI_BUF_TRANS_C_S7T2,
303 DDI_BUF_TRANS_C_S8T1,
304 DDI_BUF_TRANS_C_S8T2,
305 DDI_BUF_TRANS_C_S9T1,
306 DDI_BUF_TRANS_C_S9T2,
307 DDI_BUF_TRANS_D_S0T1,
308 DDI_BUF_TRANS_D_S0T2,
309 DDI_BUF_TRANS_D_S1T1,
310 DDI_BUF_TRANS_D_S1T2,
311 DDI_BUF_TRANS_D_S2T1,
312 DDI_BUF_TRANS_D_S2T2,
313 DDI_BUF_TRANS_D_S3T1,
314 DDI_BUF_TRANS_D_S3T2,
315 DDI_BUF_TRANS_D_S4T1,
316 DDI_BUF_TRANS_D_S4T2,
317 DDI_BUF_TRANS_D_S5T1,
318 DDI_BUF_TRANS_D_S5T2,
319 DDI_BUF_TRANS_D_S6T1,
320 DDI_BUF_TRANS_D_S6T2,
321 DDI_BUF_TRANS_D_S7T1,
322 DDI_BUF_TRANS_D_S7T2,
323 DDI_BUF_TRANS_D_S8T1,
324 DDI_BUF_TRANS_D_S8T2,
325 DDI_BUF_TRANS_D_S9T1,
326 DDI_BUF_TRANS_D_S9T2,
327 DDI_BUF_TRANS_E_S0T1,
328 DDI_BUF_TRANS_E_S0T2,
329 DDI_BUF_TRANS_E_S1T1,
330 DDI_BUF_TRANS_E_S1T2,
331 DDI_BUF_TRANS_E_S2T1,
332 DDI_BUF_TRANS_E_S2T2,
333 DDI_BUF_TRANS_E_S3T1,
334 DDI_BUF_TRANS_E_S3T2,
335 DDI_BUF_TRANS_E_S4T1,
336 DDI_BUF_TRANS_E_S4T2,
337 DDI_BUF_TRANS_E_S5T1,
338 DDI_BUF_TRANS_E_S5T2,
339 DDI_BUF_TRANS_E_S6T1,
340 DDI_BUF_TRANS_E_S6T2,
341 DDI_BUF_TRANS_E_S7T1,
342 DDI_BUF_TRANS_E_S7T2,
343 DDI_BUF_TRANS_E_S8T1,
344 DDI_BUF_TRANS_E_S8T2,
345 DDI_BUF_TRANS_E_S9T1,
346 DDI_BUF_TRANS_E_S9T2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]347 AUD_VID_DID,
348 PFA_WIN_POS,
349 PFA_WIN_SZ,
350 PFA_CTL_1,
351 PS_WIN_POS_1_A,
352 PS_WIN_SZ_1_A,
353 PS_CTRL_1_A,
354 PS_WIN_POS_2_A,
355 PS_WIN_SZ_2_A,
356 PS_CTRL_2_A,
357 PFB_WIN_POS,
358 PFB_WIN_SZ,
359 PFB_CTL_1,
360 PS_WIN_POS_1_B,
361 PS_WIN_SZ_1_B,
362 PS_CTRL_1_B,
363 PS_WIN_POS_2_B,
364 PS_WIN_SZ_2_B,
365 PS_CTRL_2_B,
366 PFC_WIN_POS,
367 PFC_WIN_SZ,
368 PFC_CTL_1,
369 PS_WIN_POS_1_C,
370 PS_WIN_SZ_1_C,
371 PS_CTRL_1_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]372 BXT_PORT_CL1CM_DW0_BC,
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]373 DISPIO_CR_TX_BMU_CR0,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]374 BXT_PORT_CL1CM_DW9_BC,
375 BXT_PORT_CL1CM_DW10_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]376 BXT_PORT_PLL_EBB_0_B,
377 BXT_PORT_PLL_EBB_4_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]378 DPLL1_CFGR1,
379 DPLL1_CFGR2,
380 DPLL2_CFGR1,
381 DPLL2_CFGR2,
382 DPLL3_CFGR1,
383 DPLL3_CFGR2,
384 DPLL_CTRL1,
385 DPLL_CTRL2,
386 DPLL_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]387 BXT_PORT_CL1CM_DW28_BC,
388 BXT_PORT_CL1CM_DW30_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]389 BXT_PORT_PLL_0_B,
390 BXT_PORT_PLL_1_B,
391 BXT_PORT_PLL_2_B,
392 BXT_PORT_PLL_3_B,
393 BXT_PORT_PLL_6_B,
394 BXT_PORT_PLL_8_B,
395 BXT_PORT_PLL_9_B,
396 BXT_PORT_PLL_10_B,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]397 BXT_PORT_REF_DW3_BC,
398 BXT_PORT_REF_DW6_BC,
399 BXT_PORT_REF_DW8_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]400 BXT_PORT_PLL_EBB_0_C,
401 BXT_PORT_PLL_EBB_4_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]402 BXT_PORT_CL2CM_DW6_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]403 BXT_PORT_PLL_0_C,
404 BXT_PORT_PLL_1_C,
405 BXT_PORT_PLL_2_C,
406 BXT_PORT_PLL_3_C,
407 BXT_PORT_PLL_6_C,
408 BXT_PORT_PLL_8_C,
409 BXT_PORT_PLL_9_C,
410 BXT_PORT_PLL_10_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]411 BXT_PORT_PCS_DW10_01_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]412 BXT_PORT_PCS_DW12_01_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]413 BXT_PORT_TX_DW2_LN0_B,
414 BXT_PORT_TX_DW3_LN0_B,
415 BXT_PORT_TX_DW4_LN0_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]416 BXT_PORT_TX_DW14_LN0_B,
417 BXT_PORT_TX_DW14_LN1_B,
418 BXT_PORT_TX_DW14_LN2_B,
419 BXT_PORT_TX_DW14_LN3_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]420 BXT_PORT_PCS_DW10_01_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]421 BXT_PORT_PCS_DW12_01_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]422 BXT_PORT_TX_DW2_LN0_C,
423 BXT_PORT_TX_DW3_LN0_C,
424 BXT_PORT_TX_DW4_LN0_C,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]425 BXT_PORT_TX_DW14_LN0_C,
426 BXT_PORT_TX_DW14_LN1_C,
427 BXT_PORT_TX_DW14_LN2_C,
428 BXT_PORT_TX_DW14_LN3_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]429 BXT_PORT_PCS_DW10_GRP_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]430 BXT_PORT_PCS_DW12_GRP_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]431 BXT_PORT_TX_DW2_GRP_B,
432 BXT_PORT_TX_DW3_GRP_B,
433 BXT_PORT_TX_DW4_GRP_B,
434 BXT_PORT_PCS_DW10_GRP_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]435 BXT_PORT_PCS_DW12_GRP_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]436 BXT_PORT_TX_DW2_GRP_C,
437 BXT_PORT_TX_DW3_GRP_C,
438 BXT_PORT_TX_DW4_GRP_C,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]439 BXT_DE_PLL_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]440 HTOTAL_EDP,
441 HBLANK_EDP,
442 HSYNC_EDP,
443 VTOTAL_EDP,
444 VBLANK_EDP,
445 VSYNC_EDP,
446 PIPE_EDP_DATA_M1,
447 PIPE_EDP_DATA_N1,
448 PIPE_EDP_LINK_M1,
449 PIPE_EDP_LINK_N1,
450 PIPE_EDP_DDI_FUNC_CTL,
451 PIPE_EDP_MSA_MISC,
452 SRD_CTL_EDP,
453 SRD_STATUS_EDP,
454 PIPE_SCANLINE_A,
455 PIPEACONF,
456 PIPEAMISC,
457 PIPE_FRMCNT_A,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]458 PIPEA_GMCH_DATA_M,
459 PIPEA_GMCH_DATA_N,
460 PIPEA_GMCH_LINK_M,
461 PIPEA_GMCH_LINK_N,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]462 DSPACNTR,
463 DSPALINOFF,
464 DSPASTRIDE,
465 PLANE_POS_1_A,
466 PLANE_SIZE_1_A,
467 DSPASURF,
468 DSPATILEOFF,
469 PLANE_WM_1_A_0,
470 PLANE_WM_1_A_1,
471 PLANE_WM_1_A_2,
472 PLANE_WM_1_A_3,
473 PLANE_WM_1_A_4,
474 PLANE_WM_1_A_5,
475 PLANE_WM_1_A_6,
476 PLANE_WM_1_A_7,
477 PLANE_BUF_CFG_1_A,
478 SPACNTR,
479 PIPE_SCANLINE_B,
480 PIPEBCONF,
481 PIPEBMISC,
482 PIPE_FRMCNT_B,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]483 PIPEB_GMCH_DATA_M,
484 PIPEB_GMCH_DATA_N,
485 PIPEB_GMCH_LINK_M,
486 PIPEB_GMCH_LINK_N,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]487 DSPBCNTR,
488 DSPBLINOFF,
489 DSPBSTRIDE,
490 PLANE_POS_1_B,
491 PLANE_SIZE_1_B,
492 DSPBSURF,
493 DSPBTILEOFF,
494 PLANE_WM_1_B_0,
495 PLANE_WM_1_B_1,
496 PLANE_WM_1_B_2,
497 PLANE_WM_1_B_3,
498 PLANE_WM_1_B_4,
499 PLANE_WM_1_B_5,
500 PLANE_WM_1_B_6,
501 PLANE_WM_1_B_7,
502 PLANE_BUF_CFG_1_B,
503 SPBCNTR,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]504 GMCH_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]505 PIPE_SCANLINE_C,
506 PIPECCONF,
507 PIPECMISC,
508 PIPE_FRMCNT_C,
509 DSPCCNTR,
510 DSPCLINOFF,
511 DSPCSTRIDE,
512 PLANE_POS_1_C,
513 PLANE_SIZE_1_C,
514 DSPCSURF,
515 DSPCTILEOFF,
516 PLANE_WM_1_C_0,
517 PLANE_WM_1_C_1,
518 PLANE_WM_1_C_2,
519 PLANE_WM_1_C_3,
520 PLANE_WM_1_C_4,
521 PLANE_WM_1_C_5,
522 PLANE_WM_1_C_6,
523 PLANE_WM_1_C_7,
524 PLANE_BUF_CFG_1_C,
525 SPCCNTR,
526 PIPE_EDP_CONF,
527 PCH_FDI_CHICKEN_B_C,
528 QUIRK_C2004,
529 SFUSE_STRAP,
530 PCH_DSPCLK_GATE_D,
531 SDEISR,
532 SDEIMR,
533 SDEIIR,
534 SDEIER,
535 SHOTPLUG_CTL,
536 PCH_GMBUS0,
537 PCH_GMBUS1,
538 PCH_GMBUS2,
539 PCH_GMBUS3,
540 PCH_GMBUS4,
541 PCH_GMBUS5,
542 SBI_ADDR,
543 SBI_DATA,
544 SBI_CTL_STAT,
545 PCH_DPLL_A,
546 PCH_DPLL_B,
547 PCH_PIXCLK_GATE,
548 PCH_FPA0,
549 PCH_FPA1,
550 PCH_FPB0,
551 PCH_FPB1,
552 PCH_DREF_CONTROL,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]553 PCH_RAWCLK_FREQ,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]554 PCH_DPLL_SEL,
555 PCH_PP_STATUS,
556 PCH_PP_CONTROL,
557 PCH_PP_ON_DELAYS,
558 PCH_PP_OFF_DELAYS,
559 PCH_PP_DIVISOR,
560 BLC_PWM_PCH_CTL1,
561 BLC_PWM_PCH_CTL2,
562 TRANS_HTOTAL_A,
563 TRANS_HBLANK_A,
564 TRANS_HSYNC_A,
565 TRANS_VTOTAL_A,
566 TRANS_VBLANK_A,
567 TRANS_VSYNC_A,
568 TRANS_VSYNCSHIFT_A,
569 TRANSA_DATA_M1,
570 TRANSA_DATA_N1,
571 TRANSA_DP_LINK_M1,
572 TRANSA_DP_LINK_N1,
573 TRANS_DP_CTL_A,
574 TRANS_HTOTAL_B,
575 TRANS_HBLANK_B,
576 TRANS_HSYNC_B,
577 TRANS_VTOTAL_B,
578 TRANS_VBLANK_B,
579 TRANS_VSYNC_B,
580 TRANS_VSYNCSHIFT_B,
581 TRANSB_DATA_M1,
582 TRANSB_DATA_N1,
583 TRANSB_DP_LINK_M1,
584 TRANSB_DP_LINK_N1,
585 PCH_ADPA,
586 PCH_HDMIB,
587 PCH_HDMIC,
588 PCH_HDMID,
589 PCH_LVDS,
590 TRANS_DP_CTL_B,
591 TRANS_HTOTAL_C,
592 TRANS_HBLANK_C,
593 TRANS_HSYNC_C,
594 TRANS_VTOTAL_C,
595 TRANS_VBLANK_C,
596 TRANS_VSYNC_C,
597 TRANS_VSYNCSHIFT_C,
598 TRANSC_DATA_M1,
599 TRANSC_DATA_N1,
600 TRANSC_DP_LINK_M1,
601 TRANSC_DP_LINK_N1,
602 TRANS_DP_CTL_C,
603 PCH_DP_B,
604 PCH_DP_AUX_CTL_B,
605 PCH_DP_AUX_DATA_B_1,
606 PCH_DP_AUX_DATA_B_2,
607 PCH_DP_AUX_DATA_B_3,
608 PCH_DP_AUX_DATA_B_4,
609 PCH_DP_AUX_DATA_B_5,
610 PCH_DP_C,
611 PCH_DP_AUX_CTL_C,
612 PCH_DP_AUX_DATA_C_1,
613 PCH_DP_AUX_DATA_C_2,
614 PCH_DP_AUX_DATA_C_3,
615 PCH_DP_AUX_DATA_C_4,
616 PCH_DP_AUX_DATA_C_5,
617 PCH_DP_D,
618 PCH_DP_AUX_CTL_D,
619 PCH_DP_AUX_DATA_D_1,
620 PCH_DP_AUX_DATA_D_2,
621 PCH_DP_AUX_DATA_D_3,
622 PCH_DP_AUX_DATA_D_4,
623 PCH_DP_AUX_DATA_D_5,
624 AUD_CONFIG_A,
625 PCH_AUD_VID_DID,
626 AUD_HDMIW_HDMIEDID_A,
627 AUD_CNTL_ST_A,
628 AUD_CNTRL_ST2,
629 AUD_CONFIG_B,
630 AUD_HDMIW_HDMIEDID_B,
631 AUD_CNTL_ST_B,
632 AUD_CONFIG_C,
633 AUD_HDMIW_HDMIEDID_C,
634 AUD_CNTL_ST_C,
635 TRANSACONF,
636 FDI_RXA_CTL,
637 FDI_RX_MISC_A,
638 FDI_RXA_IIR,
639 FDI_RXA_IMR,
640 FDI_RXA_TUSIZE1,
641 QUIRK_F0060,
642 TRANSA_CHICKEN2,
643 TRANSBCONF,
644 FDI_RXB_CTL,
645 FDI_RX_MISC_B,
646 FDI_RXB_IIR,
647 FDI_RXB_IMR,
648 FDI_RXB_TUSIZE1,
649 QUIRK_F1060,
650 TRANSB_CHICKEN2,
651 TRANSCCONF,
652 FDI_RXC_CTL,
653 FDI_RX_MISC_C,
654 FDI_RXC_IIR,
655 FDI_RXC_IMR,
656 FDI_RXC_TUSIZE1,
657 QUIRK_F2060,
658 TRANSC_CHICKEN2,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]659 BXT_P_CR_GT_DISP_PWRON,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]660 GT_MAILBOX,
661 GT_MAILBOX_DATA,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]662 GT_MAILBOX_DATA_1,
663 BXT_PORT_CL1CM_DW0_A,
664 BXT_PORT_CL1CM_DW9_A,
665 BXT_PORT_CL1CM_DW10_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]666 BXT_PORT_PLL_EBB_0_A,
667 BXT_PORT_PLL_EBB_4_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]668 BXT_PORT_CL1CM_DW28_A,
669 BXT_PORT_CL1CM_DW30_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]670 BXT_PORT_PLL_0_A,
671 BXT_PORT_PLL_1_A,
672 BXT_PORT_PLL_2_A,
673 BXT_PORT_PLL_3_A,
674 BXT_PORT_PLL_6_A,
675 BXT_PORT_PLL_8_A,
676 BXT_PORT_PLL_9_A,
677 BXT_PORT_PLL_10_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]678 BXT_PORT_REF_DW3_A,
679 BXT_PORT_REF_DW6_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]680 BXT_PORT_REF_DW8_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]681 BXT_PORT_PCS_DW10_01_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]682 BXT_PORT_PCS_DW12_01_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]683 BXT_PORT_TX_DW2_LN0_A,
684 BXT_PORT_TX_DW3_LN0_A,
685 BXT_PORT_TX_DW4_LN0_A,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]686 BXT_PORT_TX_DW14_LN0_A,
687 BXT_PORT_TX_DW14_LN1_A,
688 BXT_PORT_TX_DW14_LN2_A,
689 BXT_PORT_TX_DW14_LN3_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]690 BXT_PORT_PCS_DW10_GRP_A,
691 BXT_PORT_PCS_DW12_GRP_A,
692 BXT_PORT_TX_DW2_GRP_A,
693 BXT_PORT_TX_DW3_GRP_A,
694 BXT_PORT_TX_DW4_GRP_A);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]695
696 pragma Warnings
697 (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)",
698 Reason => "TODO: Should it matter?");
699 pragma Keep_Names (Registers_Invalid_Index);
700 pragma Warnings
701 (GNATprove, On, "pragma ""KEEP_NAMES"" ignored *(not yet supported)");
702
703 Register_Width : constant := 4;
704
705 for Registers_Invalid_Index use
706 (Invalid_Register => 0,
707
708 ---------------------------------------------------------------------------
709 -- Pipe A registers
710 ---------------------------------------------------------------------------
711
712 -- pipe timing registers
713
714 HTOTAL_A => 16#06_0000# / Register_Width,
715 HBLANK_A => 16#06_0004# / Register_Width,
716 HSYNC_A => 16#06_0008# / Register_Width,
717 VTOTAL_A => 16#06_000c# / Register_Width,
718 VBLANK_A => 16#06_0010# / Register_Width,
719 VSYNC_A => 16#06_0014# / Register_Width,
720 PIPEASRC => 16#06_001c# / Register_Width,
721 PIPEACONF => 16#07_0008# / Register_Width,
722 PIPEAMISC => 16#07_0030# / Register_Width,
723 TRANS_HTOTAL_A => 16#0e_0000# / Register_Width,
724 TRANS_HBLANK_A => 16#0e_0004# / Register_Width,
725 TRANS_HSYNC_A => 16#0e_0008# / Register_Width,
726 TRANS_VTOTAL_A => 16#0e_000c# / Register_Width,
727 TRANS_VBLANK_A => 16#0e_0010# / Register_Width,
728 TRANS_VSYNC_A => 16#0e_0014# / Register_Width,
729 TRANSA_DATA_M1 => 16#0e_0030# / Register_Width,
730 TRANSA_DATA_N1 => 16#0e_0034# / Register_Width,
731 TRANSA_DP_LINK_M1 => 16#0e_0040# / Register_Width,
732 TRANSA_DP_LINK_N1 => 16#0e_0044# / Register_Width,
733 PIPEA_DATA_M1 => 16#06_0030# / Register_Width,
734 PIPEA_DATA_N1 => 16#06_0034# / Register_Width,
735 PIPEA_LINK_M1 => 16#06_0040# / Register_Width,
736 PIPEA_LINK_N1 => 16#06_0044# / Register_Width,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]737 PIPEA_GMCH_DATA_M => 16#07_0050# / Register_Width,
738 PIPEA_GMCH_DATA_N => 16#07_0054# / Register_Width,
739 PIPEA_GMCH_LINK_M => 16#07_0060# / Register_Width,
740 PIPEA_GMCH_LINK_N => 16#07_0064# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]741 PIPEA_DDI_FUNC_CTL => 16#06_0400# / Register_Width,
742 PIPEA_MSA_MISC => 16#06_0410# / Register_Width,
743
744 -- PCH sideband interface registers
745 SBI_ADDR => 16#0c_6000# / Register_Width,
746 SBI_DATA => 16#0c_6004# / Register_Width,
747 SBI_CTL_STAT => 16#0c_6008# / Register_Width,
748
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]749 -- GMCH clock registers
750 GMCH_DPLL_A => 16#00_6014# / Register_Width,
751 GMCH_FPA0 => 16#00_6040# / Register_Width,
752 GMCH_FPA1 => 16#00_6044# / Register_Width,
753
754 -- PCH clock registers
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]755 PCH_DPLL_A => 16#0c_6014# / Register_Width,
756 PCH_PIXCLK_GATE => 16#0c_6020# / Register_Width,
757 PCH_FPA0 => 16#0c_6040# / Register_Width,
758 PCH_FPA1 => 16#0c_6044# / Register_Width,
759
760 -- panel fitter
761 PFA_CTL_1 => 16#06_8080# / Register_Width,
762 PFA_WIN_POS => 16#06_8070# / Register_Width,
763 PFA_WIN_SZ => 16#06_8074# / Register_Width,
764 PS_WIN_POS_1_A => 16#06_8170# / Register_Width,
765 PS_WIN_SZ_1_A => 16#06_8174# / Register_Width,
766 PS_CTRL_1_A => 16#06_8180# / Register_Width,
767 PS_WIN_POS_2_A => 16#06_8270# / Register_Width,
768 PS_WIN_SZ_2_A => 16#06_8274# / Register_Width,
769 PS_CTRL_2_A => 16#06_8280# / Register_Width,
770
771 -- display control
772 DSPACNTR => 16#07_0180# / Register_Width,
773 DSPALINOFF => 16#07_0184# / Register_Width,
774 DSPASTRIDE => 16#07_0188# / Register_Width,
775 PLANE_POS_1_A => 16#07_018c# / Register_Width,
776 PLANE_SIZE_1_A => 16#07_0190# / Register_Width,
777 DSPASURF => 16#07_019c# / Register_Width,
778 DSPATILEOFF => 16#07_01a4# / Register_Width,
779
780 -- sprite control
781 SPACNTR => 16#07_0280# / Register_Width,
782
783 -- FDI and PCH transcoder control
784 FDI_TX_CTL_A => 16#06_0100# / Register_Width,
785 FDI_RXA_CTL => 16#0f_000c# / Register_Width,
786 FDI_RX_MISC_A => 16#0f_0010# / Register_Width,
787 FDI_RXA_IIR => 16#0f_0014# / Register_Width,
788 FDI_RXA_IMR => 16#0f_0018# / Register_Width,
789 FDI_RXA_TUSIZE1 => 16#0f_0030# / Register_Width,
790 TRANSACONF => 16#0f_0008# / Register_Width,
791 TRANSA_CHICKEN2 => 16#0f_0064# / Register_Width,
792
793 -- watermark registers
794 WM_LINETIME_A => 16#04_5270# / Register_Width,
795 PLANE_WM_1_A_0 => 16#07_0240# / Register_Width,
796 PLANE_WM_1_A_1 => 16#07_0244# / Register_Width,
797 PLANE_WM_1_A_2 => 16#07_0248# / Register_Width,
798 PLANE_WM_1_A_3 => 16#07_024c# / Register_Width,
799 PLANE_WM_1_A_4 => 16#07_0250# / Register_Width,
800 PLANE_WM_1_A_5 => 16#07_0254# / Register_Width,
801 PLANE_WM_1_A_6 => 16#07_0258# / Register_Width,
802 PLANE_WM_1_A_7 => 16#07_025c# / Register_Width,
803 PLANE_BUF_CFG_1_A => 16#07_027c# / Register_Width,
804
805 -- CPU transcoder clock select
806 TRANSA_CLK_SEL => 16#04_6140# / Register_Width,
807
808 ---------------------------------------------------------------------------
809 -- Pipe B registers
810 ---------------------------------------------------------------------------
811
812 -- pipe timing registers
813
814 HTOTAL_B => 16#06_1000# / Register_Width,
815 HBLANK_B => 16#06_1004# / Register_Width,
816 HSYNC_B => 16#06_1008# / Register_Width,
817 VTOTAL_B => 16#06_100c# / Register_Width,
818 VBLANK_B => 16#06_1010# / Register_Width,
819 VSYNC_B => 16#06_1014# / Register_Width,
820 PIPEBSRC => 16#06_101c# / Register_Width,
821 PIPEBCONF => 16#07_1008# / Register_Width,
822 PIPEBMISC => 16#07_1030# / Register_Width,
823 TRANS_HTOTAL_B => 16#0e_1000# / Register_Width,
824 TRANS_HBLANK_B => 16#0e_1004# / Register_Width,
825 TRANS_HSYNC_B => 16#0e_1008# / Register_Width,
826 TRANS_VTOTAL_B => 16#0e_100c# / Register_Width,
827 TRANS_VBLANK_B => 16#0e_1010# / Register_Width,
828 TRANS_VSYNC_B => 16#0e_1014# / Register_Width,
829 TRANSB_DATA_M1 => 16#0e_1030# / Register_Width,
830 TRANSB_DATA_N1 => 16#0e_1034# / Register_Width,
831 TRANSB_DP_LINK_M1 => 16#0e_1040# / Register_Width,
832 TRANSB_DP_LINK_N1 => 16#0e_1044# / Register_Width,
833 PIPEB_DATA_M1 => 16#06_1030# / Register_Width,
834 PIPEB_DATA_N1 => 16#06_1034# / Register_Width,
835 PIPEB_LINK_M1 => 16#06_1040# / Register_Width,
836 PIPEB_LINK_N1 => 16#06_1044# / Register_Width,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]837 PIPEB_GMCH_DATA_M => 16#07_1050# / Register_Width,
838 PIPEB_GMCH_DATA_N => 16#07_1054# / Register_Width,
839 PIPEB_GMCH_LINK_M => 16#07_1060# / Register_Width,
840 PIPEB_GMCH_LINK_N => 16#07_1064# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]841 PIPEB_DDI_FUNC_CTL => 16#06_1400# / Register_Width,
842 PIPEB_MSA_MISC => 16#06_1410# / Register_Width,
843
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]844 -- GMCH clock registers
845 GMCH_DPLL_B => 16#00_6018# / Register_Width,
846 GMCH_FPB0 => 16#00_6048# / Register_Width,
847 GMCH_FPB1 => 16#00_604c# / Register_Width,
848
849 -- PCH clock registers
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]850 PCH_DPLL_B => 16#0c_6018# / Register_Width,
851 PCH_FPB0 => 16#0c_6048# / Register_Width,
852 PCH_FPB1 => 16#0c_604c# / Register_Width,
853
854 -- panel fitter
855 PFB_CTL_1 => 16#06_8880# / Register_Width,
856 PFB_WIN_POS => 16#06_8870# / Register_Width,
857 PFB_WIN_SZ => 16#06_8874# / Register_Width,
858 PS_WIN_POS_1_B => 16#06_8970# / Register_Width,
859 PS_WIN_SZ_1_B => 16#06_8974# / Register_Width,
860 PS_CTRL_1_B => 16#06_8980# / Register_Width,
861 PS_WIN_POS_2_B => 16#06_8a70# / Register_Width,
862 PS_WIN_SZ_2_B => 16#06_8a74# / Register_Width,
863 PS_CTRL_2_B => 16#06_8a80# / Register_Width,
864
865 -- display control
866 DSPBCNTR => 16#07_1180# / Register_Width,
867 DSPBLINOFF => 16#07_1184# / Register_Width,
868 DSPBSTRIDE => 16#07_1188# / Register_Width,
869 PLANE_POS_1_B => 16#07_118c# / Register_Width,
870 PLANE_SIZE_1_B => 16#07_1190# / Register_Width,
871 DSPBSURF => 16#07_119c# / Register_Width,
872 DSPBTILEOFF => 16#07_11a4# / Register_Width,
873
874 -- sprite control
875 SPBCNTR => 16#07_1280# / Register_Width,
876
877 -- FDI and PCH transcoder control
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]878 FDI_TX_CTL_B => 16#06_1100# / Register_Width, -- aliased by GMCH_ADPA
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]879 FDI_RXB_CTL => 16#0f_100c# / Register_Width,
880 FDI_RX_MISC_B => 16#0f_1010# / Register_Width,
881 FDI_RXB_IIR => 16#0f_1014# / Register_Width,
882 FDI_RXB_IMR => 16#0f_1018# / Register_Width,
883 FDI_RXB_TUSIZE1 => 16#0f_1030# / Register_Width,
884 TRANSBCONF => 16#0f_1008# / Register_Width,
885 TRANSB_CHICKEN2 => 16#0f_1064# / Register_Width,
886
887 -- watermark registers
888 WM_LINETIME_B => 16#04_5274# / Register_Width,
889 PLANE_WM_1_B_0 => 16#07_1240# / Register_Width,
890 PLANE_WM_1_B_1 => 16#07_1244# / Register_Width,
891 PLANE_WM_1_B_2 => 16#07_1248# / Register_Width,
892 PLANE_WM_1_B_3 => 16#07_124c# / Register_Width,
893 PLANE_WM_1_B_4 => 16#07_1250# / Register_Width,
894 PLANE_WM_1_B_5 => 16#07_1254# / Register_Width,
895 PLANE_WM_1_B_6 => 16#07_1258# / Register_Width,
896 PLANE_WM_1_B_7 => 16#07_125c# / Register_Width,
897 PLANE_BUF_CFG_1_B => 16#07_127c# / Register_Width,
898
899 -- CPU transcoder clock select
900 TRANSB_CLK_SEL => 16#04_6144# / Register_Width,
901
902 ---------------------------------------------------------------------------
903 -- Pipe C registers
904 ---------------------------------------------------------------------------
905
906 -- pipe timing registers
907
908 HTOTAL_C => 16#06_2000# / Register_Width,
909 HBLANK_C => 16#06_2004# / Register_Width,
910 HSYNC_C => 16#06_2008# / Register_Width,
911 VTOTAL_C => 16#06_200c# / Register_Width,
912 VBLANK_C => 16#06_2010# / Register_Width,
913 VSYNC_C => 16#06_2014# / Register_Width,
914 PIPECSRC => 16#06_201c# / Register_Width,
915 PIPECCONF => 16#07_2008# / Register_Width,
916 PIPECMISC => 16#07_2030# / Register_Width,
917 TRANS_HTOTAL_C => 16#0e_2000# / Register_Width,
918 TRANS_HBLANK_C => 16#0e_2004# / Register_Width,
919 TRANS_HSYNC_C => 16#0e_2008# / Register_Width,
920 TRANS_VTOTAL_C => 16#0e_200c# / Register_Width,
921 TRANS_VBLANK_C => 16#0e_2010# / Register_Width,
922 TRANS_VSYNC_C => 16#0e_2014# / Register_Width,
923 TRANSC_DATA_M1 => 16#0e_2030# / Register_Width,
924 TRANSC_DATA_N1 => 16#0e_2034# / Register_Width,
925 TRANSC_DP_LINK_M1 => 16#0e_2040# / Register_Width,
926 TRANSC_DP_LINK_N1 => 16#0e_2044# / Register_Width,
927 PIPEC_DATA_M1 => 16#06_2030# / Register_Width,
928 PIPEC_DATA_N1 => 16#06_2034# / Register_Width,
929 PIPEC_LINK_M1 => 16#06_2040# / Register_Width,
930 PIPEC_LINK_N1 => 16#06_2044# / Register_Width,
931 PIPEC_DDI_FUNC_CTL => 16#06_2400# / Register_Width,
932 PIPEC_MSA_MISC => 16#06_2410# / Register_Width,
933
934 -- panel fitter
935 PFC_CTL_1 => 16#06_9080# / Register_Width,
936 PFC_WIN_POS => 16#06_9070# / Register_Width,
937 PFC_WIN_SZ => 16#06_9074# / Register_Width,
938 PS_WIN_POS_1_C => 16#06_9170# / Register_Width,
939 PS_WIN_SZ_1_C => 16#06_9174# / Register_Width,
940 PS_CTRL_1_C => 16#06_9180# / Register_Width,
941
942 -- display control
943 DSPCCNTR => 16#07_2180# / Register_Width,
944 DSPCLINOFF => 16#07_2184# / Register_Width,
945 DSPCSTRIDE => 16#07_2188# / Register_Width,
946 PLANE_POS_1_C => 16#07_218c# / Register_Width,
947 PLANE_SIZE_1_C => 16#07_2190# / Register_Width,
948 DSPCSURF => 16#07_219c# / Register_Width,
949 DSPCTILEOFF => 16#07_21a4# / Register_Width,
950
951 -- sprite control
952 SPCCNTR => 16#07_2280# / Register_Width,
953
954 -- PCH transcoder control
955 FDI_TX_CTL_C => 16#06_2100# / Register_Width,
956 FDI_RXC_CTL => 16#0f_200c# / Register_Width,
957 FDI_RX_MISC_C => 16#0f_2010# / Register_Width,
958 FDI_RXC_IIR => 16#0f_2014# / Register_Width,
959 FDI_RXC_IMR => 16#0f_2018# / Register_Width,
960 FDI_RXC_TUSIZE1 => 16#0f_2030# / Register_Width,
961 TRANSCCONF => 16#0f_2008# / Register_Width,
962 TRANSC_CHICKEN2 => 16#0f_2064# / Register_Width,
963
964 -- watermark registers
965 WM_LINETIME_C => 16#04_5278# / Register_Width,
966 PLANE_WM_1_C_0 => 16#07_2240# / Register_Width,
967 PLANE_WM_1_C_1 => 16#07_2244# / Register_Width,
968 PLANE_WM_1_C_2 => 16#07_2248# / Register_Width,
969 PLANE_WM_1_C_3 => 16#07_224c# / Register_Width,
970 PLANE_WM_1_C_4 => 16#07_2250# / Register_Width,
971 PLANE_WM_1_C_5 => 16#07_2254# / Register_Width,
972 PLANE_WM_1_C_6 => 16#07_2258# / Register_Width,
973 PLANE_WM_1_C_7 => 16#07_225c# / Register_Width,
974 PLANE_BUF_CFG_1_C => 16#07_227c# / Register_Width,
975
976 -- CPU transcoder clock select
977 TRANSC_CLK_SEL => 16#04_6148# / Register_Width,
978
979 ---------------------------------------------------------------------------
980 -- Pipe EDP registers
981 ---------------------------------------------------------------------------
982
983 -- pipe timing registers
984
985 HTOTAL_EDP => 16#06_f000# / Register_Width,
986 HBLANK_EDP => 16#06_f004# / Register_Width,
987 HSYNC_EDP => 16#06_f008# / Register_Width,
988 VTOTAL_EDP => 16#06_f00c# / Register_Width,
989 VBLANK_EDP => 16#06_f010# / Register_Width,
990 VSYNC_EDP => 16#06_f014# / Register_Width,
991 PIPE_EDP_CONF => 16#07_f008# / Register_Width,
992 PIPE_EDP_DATA_M1 => 16#06_f030# / Register_Width,
993 PIPE_EDP_DATA_N1 => 16#06_f034# / Register_Width,
994 PIPE_EDP_LINK_M1 => 16#06_f040# / Register_Width,
995 PIPE_EDP_LINK_N1 => 16#06_f044# / Register_Width,
996 PIPE_EDP_DDI_FUNC_CTL => 16#06_f400# / Register_Width,
997 PIPE_EDP_MSA_MISC => 16#06_f410# / Register_Width,
998
999 -- PSR registers
1000 SRD_CTL => 16#06_4800# / Register_Width,
1001 SRD_CTL_A => 16#06_0800# / Register_Width,
1002 SRD_CTL_B => 16#06_1800# / Register_Width,
1003 SRD_CTL_C => 16#06_2800# / Register_Width,
1004 SRD_CTL_EDP => 16#06_f800# / Register_Width,
1005 SRD_STATUS => 16#06_4840# / Register_Width,
1006 SRD_STATUS_A => 16#06_0840# / Register_Width,
1007 SRD_STATUS_B => 16#06_1840# / Register_Width,
1008 SRD_STATUS_C => 16#06_2840# / Register_Width,
1009 SRD_STATUS_EDP => 16#06_f840# / Register_Width,
1010
1011 -- DDI registers
1012 DDI_BUF_CTL_A => 16#06_4000# / Register_Width, -- aliased by DP_CTL_A
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1013 DDI_BUF_TRANS_A_S0T1 => 16#06_4e00# / Register_Width,
1014 DDI_BUF_TRANS_A_S0T2 => 16#06_4e04# / Register_Width,
1015 DDI_BUF_TRANS_A_S1T1 => 16#06_4e08# / Register_Width,
1016 DDI_BUF_TRANS_A_S1T2 => 16#06_4e0c# / Register_Width,
1017 DDI_BUF_TRANS_A_S2T1 => 16#06_4e10# / Register_Width,
1018 DDI_BUF_TRANS_A_S2T2 => 16#06_4e14# / Register_Width,
1019 DDI_BUF_TRANS_A_S3T1 => 16#06_4e18# / Register_Width,
1020 DDI_BUF_TRANS_A_S3T2 => 16#06_4e1c# / Register_Width,
1021 DDI_BUF_TRANS_A_S4T1 => 16#06_4e20# / Register_Width,
1022 DDI_BUF_TRANS_A_S4T2 => 16#06_4e24# / Register_Width,
1023 DDI_BUF_TRANS_A_S5T1 => 16#06_4e28# / Register_Width,
1024 DDI_BUF_TRANS_A_S5T2 => 16#06_4e2c# / Register_Width,
1025 DDI_BUF_TRANS_A_S6T1 => 16#06_4e30# / Register_Width,
1026 DDI_BUF_TRANS_A_S6T2 => 16#06_4e34# / Register_Width,
1027 DDI_BUF_TRANS_A_S7T1 => 16#06_4e38# / Register_Width,
1028 DDI_BUF_TRANS_A_S7T2 => 16#06_4e3c# / Register_Width,
1029 DDI_BUF_TRANS_A_S8T1 => 16#06_4e40# / Register_Width,
1030 DDI_BUF_TRANS_A_S8T2 => 16#06_4e44# / Register_Width,
1031 DDI_BUF_TRANS_A_S9T1 => 16#06_4e48# / Register_Width,
1032 DDI_BUF_TRANS_A_S9T2 => 16#06_4e4c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1033 DDI_AUX_CTL_A => 16#06_4010# / Register_Width, -- aliased by DP_AUX_CTL_A
1034 DDI_AUX_DATA_A_1 => 16#06_4014# / Register_Width, -- aliased by DP_AUX_DATA_A_1
1035 DDI_AUX_DATA_A_2 => 16#06_4018# / Register_Width, -- aliased by DP_AUX_DATA_A_2
1036 DDI_AUX_DATA_A_3 => 16#06_401c# / Register_Width, -- aliased by DP_AUX_DATA_A_3
1037 DDI_AUX_DATA_A_4 => 16#06_4020# / Register_Width, -- aliased by DP_AUX_DATA_A_4
1038 DDI_AUX_DATA_A_5 => 16#06_4024# / Register_Width, -- aliased by DP_AUX_DATA_A_5
1039 DDI_AUX_MUTEX_A => 16#06_402c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1040
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1041 DDI_BUF_CTL_B => 16#06_4100# / Register_Width, -- aliased by GMCH_DP_B
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1042 DDI_BUF_TRANS_B_S0T1 => 16#06_4e60# / Register_Width,
1043 DDI_BUF_TRANS_B_S0T2 => 16#06_4e64# / Register_Width,
1044 DDI_BUF_TRANS_B_S1T1 => 16#06_4e68# / Register_Width,
1045 DDI_BUF_TRANS_B_S1T2 => 16#06_4e6c# / Register_Width,
1046 DDI_BUF_TRANS_B_S2T1 => 16#06_4e70# / Register_Width,
1047 DDI_BUF_TRANS_B_S2T2 => 16#06_4e74# / Register_Width,
1048 DDI_BUF_TRANS_B_S3T1 => 16#06_4e78# / Register_Width,
1049 DDI_BUF_TRANS_B_S3T2 => 16#06_4e7c# / Register_Width,
1050 DDI_BUF_TRANS_B_S4T1 => 16#06_4e80# / Register_Width,
1051 DDI_BUF_TRANS_B_S4T2 => 16#06_4e84# / Register_Width,
1052 DDI_BUF_TRANS_B_S5T1 => 16#06_4e88# / Register_Width,
1053 DDI_BUF_TRANS_B_S5T2 => 16#06_4e8c# / Register_Width,
1054 DDI_BUF_TRANS_B_S6T1 => 16#06_4e90# / Register_Width,
1055 DDI_BUF_TRANS_B_S6T2 => 16#06_4e94# / Register_Width,
1056 DDI_BUF_TRANS_B_S7T1 => 16#06_4e98# / Register_Width,
1057 DDI_BUF_TRANS_B_S7T2 => 16#06_4e9c# / Register_Width,
1058 DDI_BUF_TRANS_B_S8T1 => 16#06_4ea0# / Register_Width,
1059 DDI_BUF_TRANS_B_S8T2 => 16#06_4ea4# / Register_Width,
1060 DDI_BUF_TRANS_B_S9T1 => 16#06_4ea8# / Register_Width,
1061 DDI_BUF_TRANS_B_S9T2 => 16#06_4eac# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1062 DDI_AUX_CTL_B => 16#06_4110# / Register_Width,
1063 DDI_AUX_DATA_B_1 => 16#06_4114# / Register_Width,
1064 DDI_AUX_DATA_B_2 => 16#06_4118# / Register_Width,
1065 DDI_AUX_DATA_B_3 => 16#06_411c# / Register_Width,
1066 DDI_AUX_DATA_B_4 => 16#06_4120# / Register_Width,
1067 DDI_AUX_DATA_B_5 => 16#06_4124# / Register_Width,
1068 DDI_AUX_MUTEX_B => 16#06_412c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1069
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1070 DDI_BUF_CTL_C => 16#06_4200# / Register_Width, -- aliased by GMCH_DP_C
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1071 DDI_BUF_TRANS_C_S0T1 => 16#06_4ec0# / Register_Width,
1072 DDI_BUF_TRANS_C_S0T2 => 16#06_4ec4# / Register_Width,
1073 DDI_BUF_TRANS_C_S1T1 => 16#06_4ec8# / Register_Width,
1074 DDI_BUF_TRANS_C_S1T2 => 16#06_4ecc# / Register_Width,
1075 DDI_BUF_TRANS_C_S2T1 => 16#06_4ed0# / Register_Width,
1076 DDI_BUF_TRANS_C_S2T2 => 16#06_4ed4# / Register_Width,
1077 DDI_BUF_TRANS_C_S3T1 => 16#06_4ed8# / Register_Width,
1078 DDI_BUF_TRANS_C_S3T2 => 16#06_4edc# / Register_Width,
1079 DDI_BUF_TRANS_C_S4T1 => 16#06_4ee0# / Register_Width,
1080 DDI_BUF_TRANS_C_S4T2 => 16#06_4ee4# / Register_Width,
1081 DDI_BUF_TRANS_C_S5T1 => 16#06_4ee8# / Register_Width,
1082 DDI_BUF_TRANS_C_S5T2 => 16#06_4eec# / Register_Width,
1083 DDI_BUF_TRANS_C_S6T1 => 16#06_4ef0# / Register_Width,
1084 DDI_BUF_TRANS_C_S6T2 => 16#06_4ef4# / Register_Width,
1085 DDI_BUF_TRANS_C_S7T1 => 16#06_4ef8# / Register_Width,
1086 DDI_BUF_TRANS_C_S7T2 => 16#06_4efc# / Register_Width,
1087 DDI_BUF_TRANS_C_S8T1 => 16#06_4f00# / Register_Width,
1088 DDI_BUF_TRANS_C_S8T2 => 16#06_4f04# / Register_Width,
1089 DDI_BUF_TRANS_C_S9T1 => 16#06_4f08# / Register_Width,
1090 DDI_BUF_TRANS_C_S9T2 => 16#06_4f0c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1091 DDI_AUX_CTL_C => 16#06_4210# / Register_Width,
1092 DDI_AUX_DATA_C_1 => 16#06_4214# / Register_Width,
1093 DDI_AUX_DATA_C_2 => 16#06_4218# / Register_Width,
1094 DDI_AUX_DATA_C_3 => 16#06_421c# / Register_Width,
1095 DDI_AUX_DATA_C_4 => 16#06_4220# / Register_Width,
1096 DDI_AUX_DATA_C_5 => 16#06_4224# / Register_Width,
1097 DDI_AUX_MUTEX_C => 16#06_422c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1098
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1099 DDI_BUF_CTL_D => 16#06_4300# / Register_Width, -- aliased by GMCH_DP_D
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1100 DDI_BUF_TRANS_D_S0T1 => 16#06_4f20# / Register_Width,
1101 DDI_BUF_TRANS_D_S0T2 => 16#06_4f24# / Register_Width,
1102 DDI_BUF_TRANS_D_S1T1 => 16#06_4f28# / Register_Width,
1103 DDI_BUF_TRANS_D_S1T2 => 16#06_4f2c# / Register_Width,
1104 DDI_BUF_TRANS_D_S2T1 => 16#06_4f30# / Register_Width,
1105 DDI_BUF_TRANS_D_S2T2 => 16#06_4f34# / Register_Width,
1106 DDI_BUF_TRANS_D_S3T1 => 16#06_4f38# / Register_Width,
1107 DDI_BUF_TRANS_D_S3T2 => 16#06_4f3c# / Register_Width,
1108 DDI_BUF_TRANS_D_S4T1 => 16#06_4f40# / Register_Width,
1109 DDI_BUF_TRANS_D_S4T2 => 16#06_4f44# / Register_Width,
1110 DDI_BUF_TRANS_D_S5T1 => 16#06_4f48# / Register_Width,
1111 DDI_BUF_TRANS_D_S5T2 => 16#06_4f4c# / Register_Width,
1112 DDI_BUF_TRANS_D_S6T1 => 16#06_4f50# / Register_Width,
1113 DDI_BUF_TRANS_D_S6T2 => 16#06_4f54# / Register_Width,
1114 DDI_BUF_TRANS_D_S7T1 => 16#06_4f58# / Register_Width,
1115 DDI_BUF_TRANS_D_S7T2 => 16#06_4f5c# / Register_Width,
1116 DDI_BUF_TRANS_D_S8T1 => 16#06_4f60# / Register_Width,
1117 DDI_BUF_TRANS_D_S8T2 => 16#06_4f64# / Register_Width,
1118 DDI_BUF_TRANS_D_S9T1 => 16#06_4f68# / Register_Width,
1119 DDI_BUF_TRANS_D_S9T2 => 16#06_4f6c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1120 DDI_AUX_CTL_D => 16#06_4310# / Register_Width,
1121 DDI_AUX_DATA_D_1 => 16#06_4314# / Register_Width,
1122 DDI_AUX_DATA_D_2 => 16#06_4318# / Register_Width,
1123 DDI_AUX_DATA_D_3 => 16#06_431c# / Register_Width,
1124 DDI_AUX_DATA_D_4 => 16#06_4320# / Register_Width,
1125 DDI_AUX_DATA_D_5 => 16#06_4324# / Register_Width,
1126 DDI_AUX_MUTEX_D => 16#06_432c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1127
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1128 DDI_BUF_CTL_E => 16#06_4400# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1129 DDI_BUF_TRANS_E_S0T1 => 16#06_4f80# / Register_Width,
1130 DDI_BUF_TRANS_E_S0T2 => 16#06_4f84# / Register_Width,
1131 DDI_BUF_TRANS_E_S1T1 => 16#06_4f88# / Register_Width,
1132 DDI_BUF_TRANS_E_S1T2 => 16#06_4f8c# / Register_Width,
1133 DDI_BUF_TRANS_E_S2T1 => 16#06_4f90# / Register_Width,
1134 DDI_BUF_TRANS_E_S2T2 => 16#06_4f94# / Register_Width,
1135 DDI_BUF_TRANS_E_S3T1 => 16#06_4f98# / Register_Width,
1136 DDI_BUF_TRANS_E_S3T2 => 16#06_4f9c# / Register_Width,
1137 DDI_BUF_TRANS_E_S4T1 => 16#06_4fa0# / Register_Width,
1138 DDI_BUF_TRANS_E_S4T2 => 16#06_4fa4# / Register_Width,
1139 DDI_BUF_TRANS_E_S5T1 => 16#06_4fa8# / Register_Width,
1140 DDI_BUF_TRANS_E_S5T2 => 16#06_4fac# / Register_Width,
1141 DDI_BUF_TRANS_E_S6T1 => 16#06_4fb0# / Register_Width,
1142 DDI_BUF_TRANS_E_S6T2 => 16#06_4fb4# / Register_Width,
1143 DDI_BUF_TRANS_E_S7T1 => 16#06_4fb8# / Register_Width,
1144 DDI_BUF_TRANS_E_S7T2 => 16#06_4fbc# / Register_Width,
1145 DDI_BUF_TRANS_E_S8T1 => 16#06_4fc0# / Register_Width,
1146 DDI_BUF_TRANS_E_S8T2 => 16#06_4fc4# / Register_Width,
1147 DDI_BUF_TRANS_E_S9T1 => 16#06_4fc8# / Register_Width,
1148 DDI_BUF_TRANS_E_S9T2 => 16#06_4fcc# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1149 DP_TP_CTL_A => 16#06_4040# / Register_Width,
1150 DP_TP_CTL_B => 16#06_4140# / Register_Width,
1151 DP_TP_CTL_C => 16#06_4240# / Register_Width,
1152 DP_TP_CTL_D => 16#06_4340# / Register_Width,
1153 DP_TP_CTL_E => 16#06_4440# / Register_Width,
1154 DP_TP_STATUS_B => 16#06_4144# / Register_Width,
1155 DP_TP_STATUS_C => 16#06_4244# / Register_Width,
1156 DP_TP_STATUS_D => 16#06_4344# / Register_Width,
1157 DP_TP_STATUS_E => 16#06_4444# / Register_Width,
1158 PORT_CLK_SEL_DDIA => 16#04_6100# / Register_Width,
1159 PORT_CLK_SEL_DDIB => 16#04_6104# / Register_Width,
1160 PORT_CLK_SEL_DDIC => 16#04_6108# / Register_Width,
1161 PORT_CLK_SEL_DDID => 16#04_610c# / Register_Width,
1162 PORT_CLK_SEL_DDIE => 16#04_6110# / Register_Width,
1163
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]1164 -- Skylake I_boost configuration
1165 DISPIO_CR_TX_BMU_CR0 => 16#06_c00c# / Register_Width,
1166
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1167 -- Skylake DPLL registers
1168 DPLL1_CFGR1 => 16#06_c040# / Register_Width,
1169 DPLL1_CFGR2 => 16#06_c044# / Register_Width,
1170 DPLL2_CFGR1 => 16#06_c048# / Register_Width,
1171 DPLL2_CFGR2 => 16#06_c04c# / Register_Width,
1172 DPLL3_CFGR1 => 16#06_c050# / Register_Width,
1173 DPLL3_CFGR2 => 16#06_c054# / Register_Width,
1174 DPLL_CTRL1 => 16#06_c058# / Register_Width,
1175 DPLL_CTRL2 => 16#06_c05c# / Register_Width,
1176 DPLL_STATUS => 16#06_c060# / Register_Width,
1177
1178 -- CD CLK register
1179 CDCLK_CTL => 16#04_6000# / Register_Width,
1180
1181 -- Skylake LCPLL registers
1182 LCPLL1_CTL => 16#04_6010# / Register_Width,
1183 LCPLL2_CTL => 16#04_6014# / Register_Width,
1184
1185 -- SPLL register
1186 SPLL_CTL => 16#04_6020# / Register_Width,
1187
1188 -- WRPLL registers
1189 WRPLL_CTL_1 => 16#04_6040# / Register_Width,
1190 WRPLL_CTL_2 => 16#04_6060# / Register_Width,
1191
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]1192 -- Broxton Display Engine PLL registers
1193 BXT_DE_PLL_CTL => 16#06_d000# / Register_Width,
1194 BXT_DE_PLL_ENABLE => 16#04_6070# / Register_Width,
1195
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1196 -- Broxton DDI PHY PLL registers
1197 BXT_PORT_PLL_ENABLE_A => 16#04_6074# / Register_Width,
1198 BXT_PORT_PLL_ENABLE_B => 16#04_6078# / Register_Width,
1199 BXT_PORT_PLL_ENABLE_C => 16#04_607c# / Register_Width,
1200 BXT_PORT_PLL_EBB_0_A => 16#16_2034# / Register_Width,
1201 BXT_PORT_PLL_EBB_4_A => 16#16_2038# / Register_Width,
1202 BXT_PORT_PLL_0_A => 16#16_2100# / Register_Width,
1203 BXT_PORT_PLL_1_A => 16#16_2104# / Register_Width,
1204 BXT_PORT_PLL_2_A => 16#16_2108# / Register_Width,
1205 BXT_PORT_PLL_3_A => 16#16_210c# / Register_Width,
1206 BXT_PORT_PLL_6_A => 16#16_2118# / Register_Width,
1207 BXT_PORT_PLL_8_A => 16#16_2120# / Register_Width,
1208 BXT_PORT_PLL_9_A => 16#16_2124# / Register_Width,
1209 BXT_PORT_PLL_10_A => 16#16_2128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1210 BXT_PORT_PLL_EBB_0_B => 16#06_c034# / Register_Width,
1211 BXT_PORT_PLL_EBB_4_B => 16#06_c038# / Register_Width,
1212 BXT_PORT_PLL_0_B => 16#06_c100# / Register_Width,
1213 BXT_PORT_PLL_1_B => 16#06_c104# / Register_Width,
1214 BXT_PORT_PLL_2_B => 16#06_c108# / Register_Width,
1215 BXT_PORT_PLL_3_B => 16#06_c10c# / Register_Width,
1216 BXT_PORT_PLL_6_B => 16#06_c118# / Register_Width,
1217 BXT_PORT_PLL_8_B => 16#06_c120# / Register_Width,
1218 BXT_PORT_PLL_9_B => 16#06_c124# / Register_Width,
1219 BXT_PORT_PLL_10_B => 16#06_c128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1220 BXT_PORT_PLL_EBB_0_C => 16#06_c340# / Register_Width,
1221 BXT_PORT_PLL_EBB_4_C => 16#06_c344# / Register_Width,
1222 BXT_PORT_PLL_0_C => 16#06_c380# / Register_Width,
1223 BXT_PORT_PLL_1_C => 16#06_c384# / Register_Width,
1224 BXT_PORT_PLL_2_C => 16#06_c388# / Register_Width,
1225 BXT_PORT_PLL_3_C => 16#06_c38c# / Register_Width,
1226 BXT_PORT_PLL_6_C => 16#06_c398# / Register_Width,
1227 BXT_PORT_PLL_8_C => 16#06_c3a0# / Register_Width,
1228 BXT_PORT_PLL_9_C => 16#06_c3a4# / Register_Width,
1229 BXT_PORT_PLL_10_C => 16#06_c3a8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1230
1231 -- Broxton DDI PHY PCS? registers
1232 BXT_PORT_PCS_DW10_01_A => 16#16_2428# / Register_Width,
1233 BXT_PORT_PCS_DW12_01_A => 16#16_2430# / Register_Width,
1234 BXT_PORT_PCS_DW10_GRP_A => 16#16_2c28# / Register_Width,
1235 BXT_PORT_PCS_DW12_GRP_A => 16#16_2c30# / Register_Width,
1236 BXT_PORT_PCS_DW10_01_B => 16#06_c428# / Register_Width,
1237 BXT_PORT_PCS_DW12_01_B => 16#06_c430# / Register_Width,
1238 BXT_PORT_PCS_DW10_01_C => 16#06_c828# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1239 BXT_PORT_PCS_DW12_01_C => 16#06_c830# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1240 BXT_PORT_PCS_DW10_GRP_B => 16#06_cc28# / Register_Width,
1241 BXT_PORT_PCS_DW12_GRP_B => 16#06_cc30# / Register_Width,
1242 BXT_PORT_PCS_DW10_GRP_C => 16#06_ce28# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1243 BXT_PORT_PCS_DW12_GRP_C => 16#06_ce30# / Register_Width,
1244
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1245 -- Broxton DDI PHY registers
1246 BXT_P_CR_GT_DISP_PWRON => 16#13_8090# / Register_Width,
1247 BXT_PHY_CTL_A => 16#06_4c00# / Register_Width,
1248 BXT_PHY_CTL_B => 16#06_4c10# / Register_Width,
1249 BXT_PHY_CTL_C => 16#06_4c20# / Register_Width,
1250 BXT_PHY_CTL_FAM_EDP => 16#06_4c80# / Register_Width,
1251 BXT_PHY_CTL_FAM_DDI => 16#06_4c90# / Register_Width,
1252
1253 -- Broxton DDI PHY common lane registers
1254 BXT_PORT_CL1CM_DW0_A => 16#16_2000# / Register_Width,
1255 BXT_PORT_CL1CM_DW0_BC => 16#06_c000# / Register_Width,
1256 BXT_PORT_CL1CM_DW9_A => 16#16_2024# / Register_Width,
1257 BXT_PORT_CL1CM_DW9_BC => 16#06_c024# / Register_Width,
1258 BXT_PORT_CL1CM_DW10_A => 16#16_2028# / Register_Width,
1259 BXT_PORT_CL1CM_DW10_BC => 16#06_c028# / Register_Width,
1260 BXT_PORT_CL1CM_DW28_A => 16#16_2070# / Register_Width,
1261 BXT_PORT_CL1CM_DW28_BC => 16#06_c070# / Register_Width,
1262 BXT_PORT_CL1CM_DW30_A => 16#16_2078# / Register_Width,
1263 BXT_PORT_CL1CM_DW30_BC => 16#06_c078# / Register_Width,
1264 BXT_PORT_CL2CM_DW6_BC => 16#06_c358# / Register_Width,
1265
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1266 -- Broxton DDI PHY TX lane registers
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1267 BXT_PORT_TX_DW2_LN0_A => 16#16_2508# / Register_Width,
1268 BXT_PORT_TX_DW3_LN0_A => 16#16_250c# / Register_Width,
1269 BXT_PORT_TX_DW4_LN0_A => 16#16_2510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1270 BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width,
1271 BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width,
1272 BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width,
1273 BXT_PORT_TX_DW14_LN3_A => 16#16_27b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1274 BXT_PORT_TX_DW2_GRP_A => 16#16_2d08# / Register_Width,
1275 BXT_PORT_TX_DW3_GRP_A => 16#16_2d0c# / Register_Width,
1276 BXT_PORT_TX_DW4_GRP_A => 16#16_2d10# / Register_Width,
1277 BXT_PORT_TX_DW2_LN0_B => 16#06_c508# / Register_Width,
1278 BXT_PORT_TX_DW3_LN0_B => 16#06_c50c# / Register_Width,
1279 BXT_PORT_TX_DW4_LN0_B => 16#06_c510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1280 BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width,
1281 BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width,
1282 BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width,
1283 BXT_PORT_TX_DW14_LN3_B => 16#06_c7b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1284 BXT_PORT_TX_DW2_GRP_B => 16#06_cd08# / Register_Width,
1285 BXT_PORT_TX_DW3_GRP_B => 16#06_cd0c# / Register_Width,
1286 BXT_PORT_TX_DW4_GRP_B => 16#06_cd10# / Register_Width,
1287 BXT_PORT_TX_DW2_LN0_C => 16#06_c908# / Register_Width,
1288 BXT_PORT_TX_DW3_LN0_C => 16#06_c90c# / Register_Width,
1289 BXT_PORT_TX_DW4_LN0_C => 16#06_c910# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1290 BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width,
1291 BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width,
1292 BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width,
1293 BXT_PORT_TX_DW14_LN3_C => 16#06_cbb8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1294 BXT_PORT_TX_DW2_GRP_C => 16#06_cf08# / Register_Width,
1295 BXT_PORT_TX_DW3_GRP_C => 16#06_cf0c# / Register_Width,
1296 BXT_PORT_TX_DW4_GRP_C => 16#06_cf10# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1297
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1298 -- Broxton DDI PHY ref registers
1299 BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width,
1300 BXT_PORT_REF_DW3_BC => 16#06_c18c# / Register_Width,
1301 BXT_PORT_REF_DW6_A => 16#16_2198# / Register_Width,
1302 BXT_PORT_REF_DW6_BC => 16#06_c198# / Register_Width,
1303 BXT_PORT_REF_DW8_A => 16#16_21a0# / Register_Width,
1304 BXT_PORT_REF_DW8_BC => 16#06_c1a0# / Register_Width,
1305
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1306 -- Power Down Well registers
1307 PWR_WELL_CTL_BIOS => 16#04_5400# / Register_Width,
1308 PWR_WELL_CTL_DRIVER => 16#04_5404# / Register_Width,
1309 PWR_WELL_CTL_KVMR => 16#04_5408# / Register_Width,
1310 PWR_WELL_CTL_DEBUG => 16#04_540c# / Register_Width,
1311 PWR_WELL_CTL5 => 16#04_5410# / Register_Width,
1312 PWR_WELL_CTL6 => 16#04_5414# / Register_Width,
1313
1314 -- class Panel registers
Arthur Heymanse87d0d12018-03-28 17:02:49 +0200[diff] [blame]1315 GMCH_PP_STATUS => 16#06_1200# / Register_Width,
1316 GMCH_PP_CONTROL => 16#06_1204# / Register_Width,
1317 GMCH_PP_ON_DELAYS => 16#06_1208# / Register_Width,
1318 GMCH_PP_OFF_DELAYS => 16#06_120c# / Register_Width,
1319 GMCH_PP_DIVISOR => 16#06_1210# / Register_Width,
Arthur Heymansd5198442018-03-28 17:05:12 +0200[diff] [blame]1320 GMCH_PFIT_CONTROL => 16#06_1230# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1321 PCH_PP_STATUS => 16#0c_7200# / Register_Width,
1322 PCH_PP_CONTROL => 16#0c_7204# / Register_Width,
1323 PCH_PP_ON_DELAYS => 16#0c_7208# / Register_Width,
1324 PCH_PP_OFF_DELAYS => 16#0c_720c# / Register_Width,
1325 PCH_PP_DIVISOR => 16#0c_7210# / Register_Width,
1326 BLC_PWM_CPU_CTL => 16#04_8254# / Register_Width,
1327 BLC_PWM_PCH_CTL2 => 16#0c_8254# / Register_Width,
1328
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1329 -- GMCH LVDS Connector Registers
1330 GMCH_LVDS => 16#06_1180# / Register_Width,
1331
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1332 -- PCH LVDS Connector Registers
1333 PCH_LVDS => 16#0e_1180# / Register_Width,
1334
1335 -- PCH ADPA Connector Registers
1336 PCH_ADPA => 16#0e_1100# / Register_Width,
1337
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1338 -- GMCH DVOB Connector Registers
1339 GMCH_SDVOB => 16#06_1140# / Register_Width,
1340
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1341 -- PCH HDMIB Connector Registers
1342 PCH_HDMIB => 16#0e_1140# / Register_Width,
1343
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1344 -- GMCH DVOC Connector Registers
1345 GMCH_SDVOC => 16#06_1160# / Register_Width,
1346
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1347 -- PCH HDMIC Connector Registers
1348 PCH_HDMIC => 16#0e_1150# / Register_Width,
1349
1350 -- PCH HDMID Connector Registers
1351 PCH_HDMID => 16#0e_1160# / Register_Width,
1352
1353 -- Intel Registers
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]1354 CPU_VGACNTRL => 16#04_1000# / Register_Width,
1355 GMCH_VGACNTRL => 16#07_1400# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1356 FUSE_STATUS => 16#04_2000# / Register_Width,
1357 FBA_CFB_BASE => 16#04_3200# / Register_Width,
1358 IPS_CTL => 16#04_3408# / Register_Width,
1359 ARB_CTL => 16#04_5000# / Register_Width,
1360 DBUF_CTL => 16#04_5008# / Register_Width,
1361 NDE_RSTWRN_OPT => 16#04_6408# / Register_Width,
1362 PCH_DREF_CONTROL => 16#0c_6200# / Register_Width,
1363 BLC_PWM_PCH_CTL1 => 16#0c_8250# / Register_Width,
1364 BLC_PWM_CPU_CTL2 => 16#04_8250# / Register_Width,
1365 PCH_DPLL_SEL => 16#0c_7000# / Register_Width,
1366 GT_MAILBOX => 16#13_8124# / Register_Width,
1367 GT_MAILBOX_DATA => 16#13_8128# / Register_Width,
1368 GT_MAILBOX_DATA_1 => 16#13_812c# / Register_Width,
1369
1370 PCH_DP_B => 16#0e_4100# / Register_Width,
1371 PCH_DP_AUX_CTL_B => 16#0e_4110# / Register_Width,
1372 PCH_DP_AUX_DATA_B_1 => 16#0e_4114# / Register_Width,
1373 PCH_DP_AUX_DATA_B_2 => 16#0e_4118# / Register_Width,
1374 PCH_DP_AUX_DATA_B_3 => 16#0e_411c# / Register_Width,
1375 PCH_DP_AUX_DATA_B_4 => 16#0e_4120# / Register_Width,
1376 PCH_DP_AUX_DATA_B_5 => 16#0e_4124# / Register_Width,
1377 PCH_DP_C => 16#0e_4200# / Register_Width,
1378 PCH_DP_AUX_CTL_C => 16#0e_4210# / Register_Width,
1379 PCH_DP_AUX_DATA_C_1 => 16#0e_4214# / Register_Width,
1380 PCH_DP_AUX_DATA_C_2 => 16#0e_4218# / Register_Width,
1381 PCH_DP_AUX_DATA_C_3 => 16#0e_421c# / Register_Width,
1382 PCH_DP_AUX_DATA_C_4 => 16#0e_4220# / Register_Width,
1383 PCH_DP_AUX_DATA_C_5 => 16#0e_4224# / Register_Width,
1384 PCH_DP_D => 16#0e_4300# / Register_Width,
1385 PCH_DP_AUX_CTL_D => 16#0e_4310# / Register_Width,
1386 PCH_DP_AUX_DATA_D_1 => 16#0e_4314# / Register_Width,
1387 PCH_DP_AUX_DATA_D_2 => 16#0e_4318# / Register_Width,
1388 PCH_DP_AUX_DATA_D_3 => 16#0e_431c# / Register_Width,
1389 PCH_DP_AUX_DATA_D_4 => 16#0e_4320# / Register_Width,
1390 PCH_DP_AUX_DATA_D_5 => 16#0e_4324# / Register_Width,
1391
1392 -- watermark registers
1393 WM1_LP_ILK => 16#04_5108# / Register_Width,
1394 WM2_LP_ILK => 16#04_510c# / Register_Width,
1395 WM3_LP_ILK => 16#04_5110# / Register_Width,
1396
1397 -- audio VID/DID
1398 AUD_VID_DID => 16#06_5020# / Register_Width,
1399 PCH_AUD_VID_DID => 16#0e_5020# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1400 G4X_AUD_VID_DID => 16#06_2020# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1401
1402 -- interrupt registers
1403 DEISR => 16#04_4000# / Register_Width,
1404 DEIMR => 16#04_4004# / Register_Width,
1405 DEIIR => 16#04_4008# / Register_Width,
1406 DEIER => 16#04_400c# / Register_Width,
1407 GTISR => 16#04_4010# / Register_Width,
1408 GTIMR => 16#04_4014# / Register_Width,
1409 GTIIR => 16#04_4018# / Register_Width,
1410 GTIER => 16#04_401c# / Register_Width,
1411 SDEISR => 16#0c_4000# / Register_Width,
1412 SDEIMR => 16#0c_4004# / Register_Width,
1413 SDEIIR => 16#0c_4008# / Register_Width,
1414 SDEIER => 16#0c_400c# / Register_Width,
1415
1416 -- I2C stuff
Arthur Heymans229ed1c2018-03-28 16:45:43 +0200[diff] [blame]1417 GMCH_GMBUS0 => 16#00_5100# / Register_Width,
1418 GMCH_GMBUS1 => 16#00_5104# / Register_Width,
1419 GMCH_GMBUS2 => 16#00_5108# / Register_Width,
1420 GMCH_GMBUS3 => 16#00_510c# / Register_Width,
1421 GMCH_GMBUS4 => 16#00_5110# / Register_Width,
1422 GMCH_GMBUS5 => 16#00_5120# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1423 PCH_GMBUS0 => 16#0c_5100# / Register_Width,
1424 PCH_GMBUS1 => 16#0c_5104# / Register_Width,
1425 PCH_GMBUS2 => 16#0c_5108# / Register_Width,
1426 PCH_GMBUS3 => 16#0c_510c# / Register_Width,
1427 PCH_GMBUS4 => 16#0c_5110# / Register_Width,
1428 PCH_GMBUS5 => 16#0c_5120# / Register_Width,
1429
1430 -- clock gating -- maybe have to touch this
1431 DSPCLK_GATE_D => 16#04_2020# / Register_Width,
1432 PCH_FDI_CHICKEN_B_C => 16#0c_2000# / Register_Width,
1433 PCH_DSPCLK_GATE_D => 16#0c_2020# / Register_Width,
1434
1435 -- hotplug and initial detection
1436 HOTPLUG_CTL => 16#04_4030# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1437 PORT_HOTPLUG_EN => 16#06_1110# / Register_Width,
1438 PORT_HOTPLUG_STAT => 16#06_1114# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1439 SHOTPLUG_CTL => 16#0c_4030# / Register_Width,
1440 SFUSE_STRAP => 16#0c_2014# / Register_Width,
1441
1442 -- Render Engine Command Streamer
1443 ARB_MODE => 16#00_4030# / Register_Width,
1444 HWS_PGA => 16#00_4080# / Register_Width,
1445 RCS_RING_BUFFER_TAIL => 16#00_2030# / Register_Width,
1446 VCS_RING_BUFFER_TAIL => 16#01_2030# / Register_Width,
1447 BCS_RING_BUFFER_TAIL => 16#02_2030# / Register_Width,
1448 RCS_RING_BUFFER_HEAD => 16#00_2034# / Register_Width,
1449 VCS_RING_BUFFER_HEAD => 16#01_2034# / Register_Width,
1450 BCS_RING_BUFFER_HEAD => 16#02_2034# / Register_Width,
1451 RCS_RING_BUFFER_STRT => 16#00_2038# / Register_Width,
1452 VCS_RING_BUFFER_STRT => 16#01_2038# / Register_Width,
1453 BCS_RING_BUFFER_STRT => 16#02_2038# / Register_Width,
1454 RCS_RING_BUFFER_CTL => 16#00_203c# / Register_Width,
1455 VCS_RING_BUFFER_CTL => 16#01_203c# / Register_Width,
1456 BCS_RING_BUFFER_CTL => 16#02_203c# / Register_Width,
1457 MI_MODE => 16#00_209c# / Register_Width,
1458 INSTPM => 16#00_20c0# / Register_Width,
1459 GAB_CTL_REG => 16#02_4000# / Register_Width,
1460 PP_DCLV_HIGH => 16#00_2220# / Register_Width,
1461 PP_DCLV_LOW => 16#00_2228# / Register_Width,
1462 VCS_PP_DCLV_HIGH => 16#01_2220# / Register_Width,
1463 VCS_PP_DCLV_LOW => 16#01_2228# / Register_Width,
1464 BCS_PP_DCLV_HIGH => 16#02_2220# / Register_Width,
1465 BCS_PP_DCLV_LOW => 16#02_2228# / Register_Width,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1466 ILK_DISPLAY_CHICKEN2 => 16#04_2004# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1467 UCGCTL1 => 16#00_9400# / Register_Width,
1468 UCGCTL2 => 16#00_9404# / Register_Width,
1469 MBCTL => 16#00_907c# / Register_Width,
1470 HWSTAM => 16#00_2098# / Register_Width,
1471 VCS_HWSTAM => 16#01_2098# / Register_Width,
1472 BCS_HWSTAM => 16#02_2098# / Register_Width,
1473 IIR => 16#04_4028# / Register_Width,
1474 PIPE_FRMCNT_A => 16#07_0040# / Register_Width,
1475 PIPE_FRMCNT_B => 16#07_1040# / Register_Width,
1476 PIPE_FRMCNT_C => 16#07_2040# / Register_Width,
1477 FBC_CTL => 16#04_3208# / Register_Width,
1478 PIPE_VSYNCSHIFT_A => 16#06_0028# / Register_Width,
1479 PIPE_VSYNCSHIFT_B => 16#06_1028# / Register_Width,
1480 PIPE_VSYNCSHIFT_C => 16#06_2028# / Register_Width,
1481 WM_PIPE_A => 16#04_5100# / Register_Width,
1482 WM_PIPE_B => 16#04_5104# / Register_Width,
1483 WM_PIPE_C => 16#04_5200# / Register_Width,
1484 PIPE_SCANLINE_A => 16#07_0000# / Register_Width,
1485 PIPE_SCANLINE_B => 16#07_1000# / Register_Width,
1486 PIPE_SCANLINE_C => 16#07_2000# / Register_Width,
1487 GFX_MODE => 16#00_2520# / Register_Width,
1488 CACHE_MODE_0 => 16#00_2120# / Register_Width,
1489 SLEEP_PSMI_CONTROL => 16#01_2050# / Register_Width,
1490 CTX_SIZE => 16#00_21a0# / Register_Width,
1491 GAC_ECO_BITS => 16#01_4090# / Register_Width,
1492 GAM_ECOCHK => 16#00_4090# / Register_Width,
1493 QUIRK_02084 => 16#00_2084# / Register_Width,
1494 QUIRK_02090 => 16#00_2090# / Register_Width,
1495 GT_MODE => 16#00_20d0# / Register_Width,
1496 QUIRK_F0060 => 16#0f_0060# / Register_Width,
1497 QUIRK_F1060 => 16#0f_1060# / Register_Width,
1498 QUIRK_F2060 => 16#0f_2060# / Register_Width,
1499 AUD_CNTRL_ST2 => 16#0e_50c0# / Register_Width,
1500 AUD_CNTL_ST_A => 16#0e_50b4# / Register_Width,
1501 AUD_CNTL_ST_B => 16#0e_51b4# / Register_Width,
1502 AUD_CNTL_ST_C => 16#0e_52b4# / Register_Width,
1503 AUD_HDMIW_HDMIEDID_A => 16#0e_5050# / Register_Width,
1504 AUD_HDMIW_HDMIEDID_B => 16#0e_5150# / Register_Width,
1505 AUD_HDMIW_HDMIEDID_C => 16#0e_5250# / Register_Width,
1506 AUD_CONFIG_A => 16#0e_5000# / Register_Width,
1507 AUD_CONFIG_B => 16#0e_5100# / Register_Width,
1508 AUD_CONFIG_C => 16#0e_5200# / Register_Width,
1509 TRANS_DP_CTL_A => 16#0e_0300# / Register_Width,
1510 TRANS_DP_CTL_B => 16#0e_1300# / Register_Width,
1511 TRANS_DP_CTL_C => 16#0e_2300# / Register_Width,
1512 TRANS_VSYNCSHIFT_A => 16#0e_0028# / Register_Width,
1513 TRANS_VSYNCSHIFT_B => 16#0e_1028# / Register_Width,
1514 TRANS_VSYNCSHIFT_C => 16#0e_2028# / Register_Width,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]1515 PCH_RAWCLK_FREQ => 16#0c_6204# / Register_Width,
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1516 QUIRK_C2004 => 16#0c_2004# / Register_Width,
1517
1518 -- MCHBAR Mirror
1519
1520 GMCH_CLKCFG => 16#01_0c00# / Register_Width);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1521
1522 subtype Registers_Index is Registers_Invalid_Index range
1523 Registers_Invalid_Index'Succ (Invalid_Register) ..
1524 Registers_Invalid_Index'Last;
1525
1526 -- aliased registers
1527 DP_CTL_A : constant Registers_Index := DDI_BUF_CTL_A;
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1528 GMCH_DP_B : constant Registers_Index := DDI_BUF_CTL_B;
1529 GMCH_DP_C : constant Registers_Index := DDI_BUF_CTL_C;
1530 GMCH_DP_D : constant Registers_Index := DDI_BUF_CTL_D;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1531 DP_AUX_CTL_A : constant Registers_Index := DDI_AUX_CTL_A;
1532 DP_AUX_DATA_A_1 : constant Registers_Index := DDI_AUX_DATA_A_1;
1533 DP_AUX_DATA_A_2 : constant Registers_Index := DDI_AUX_DATA_A_2;
1534 DP_AUX_DATA_A_3 : constant Registers_Index := DDI_AUX_DATA_A_3;
1535 DP_AUX_DATA_A_4 : constant Registers_Index := DDI_AUX_DATA_A_4;
1536 DP_AUX_DATA_A_5 : constant Registers_Index := DDI_AUX_DATA_A_5;
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1537 ILK_DISPLAY_CHICKEN1 : constant Registers_Index := FUSE_STATUS;
Arthur Heymans73ea0322018-03-28 17:17:07 +0200[diff] [blame]1538 GMCH_ADPA : constant Registers_Index := FDI_TX_CTL_B;
1539 GMCH_HDMIB : constant Registers_Index := GMCH_SDVOB;
1540 GMCH_HDMIC : constant Registers_Index := GMCH_SDVOC;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1541
1542 ---------------------------------------------------------------------------
1543
1544 Default_Timeout_MS : constant := 10;
1545
1546 ---------------------------------------------------------------------------
1547
1548 procedure Posting_Read
1549 (Register : in Registers_Index)
1550 with
1551 Global => (In_Out => Register_State),
1552 Depends => (Register_State =>+ (Register)),
1553 Pre => True,
1554 Post => True;
1555
1556 pragma Warnings (GNATprove, Off, "unused variable ""Verbose""",
1557 Reason => "Only used on debugging path");
1558 procedure Read
1559 (Register : in Registers_Index;
1560 Value : out Word32;
1561 Verbose : in Boolean := True)
1562 with
1563 Global => (In_Out => Register_State),
1564 Depends => ((Value, Register_State) => (Register, Register_State),
1565 null => Verbose),
1566 Pre => True,
1567 Post => True;
1568 pragma Warnings (GNATprove, On, "unused variable ""Verbose""");
1569
1570 procedure Write
1571 (Register : Registers_Index;
1572 Value : Word32)
1573 with
1574 Global => (In_Out => Register_State),
1575 Depends => (Register_State => (Register, Register_State, Value)),
1576 Pre => True,
1577 Post => True;
1578
1579 procedure Is_Set_Mask
1580 (Register : in Registers_Index;
1581 Mask : in Word32;
1582 Result : out Boolean);
1583
1584 pragma Warnings (GNATprove, Off, "unused initial value of ""Verbose""",
1585 Reason => "Only used on debugging path");
Nico Huberbcb2c472017-02-02 16:39:26 +0100[diff] [blame]1586 procedure Wait
1587 (Register : Registers_Index;
1588 Mask : Word32;
1589 Value : Word32;
1590 TOut_MS : Natural := Default_Timeout_MS;
1591 Verbose : Boolean := False);
1592
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1593 procedure Wait_Set_Mask
1594 (Register : Registers_Index;
1595 Mask : Word32;
1596 TOut_MS : Natural := Default_Timeout_MS;
1597 Verbose : Boolean := False);
1598
1599 procedure Wait_Unset_Mask
1600 (Register : Registers_Index;
1601 Mask : Word32;
1602 TOut_MS : Natural := Default_Timeout_MS;
1603 Verbose : Boolean := False);
1604 pragma Warnings (GNATprove, On, "unused initial value of ""Verbose""");
1605
1606 procedure Set_Mask
1607 (Register : Registers_Index;
1608 Mask : Word32);
1609
1610 procedure Unset_Mask
1611 (Register : Registers_Index;
1612 Mask : Word32);
1613
1614 procedure Unset_And_Set_Mask
1615 (Register : Registers_Index;
1616 Mask_Unset : Word32;
1617 Mask_Set : Word32);
1618
Nico Huber17d64b62017-07-15 20:51:25 +0200[diff] [blame]1619 procedure Clear_Fences;
1620
Nico Huberb03c8f12017-08-25 13:29:08 +0200[diff] [blame]1621 procedure Add_Fence
1622 (First_Page : in GTT_Range;
1623 Last_Page : in GTT_Range;
1624 Tiling : in XY_Tiling;
1625 Pitch : in Natural;
1626 Success : out Boolean);
1627
1628 procedure Remove_Fence (First_Page, Last_Page : GTT_Range);
1629
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1630 pragma Warnings (Off, "declaration of ""Write_GTT"" hides one at *");
1631 procedure Write_GTT
1632 (GTT_Page : GTT_Range;
1633 Device_Address : GTT_Address_Type;
1634 Valid : Boolean)
1635 with
1636 Global => (In_Out => GTT_State),
1637 Depends => (GTT_State =>+ (GTT_Page, Device_Address, Valid)),
1638 Pre => True,
1639 Post => True;
1640 pragma Warnings (On, "declaration of ""Write_GTT"" hides one at *");
1641
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]1642 procedure Set_Register_Base (Base : Word64; GTT_Base : Word64 := 0)
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1643 with
1644 Global => (Output => Address_State),
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]1645 Depends => (Address_State => (Base, GTT_Base)),
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1646 Pre => True,
1647 Post => True;
1648
1649end HW.GFX.GMA.Registers;