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review.sourcearcade.org / libgfxinit / 98a673dc57d90cc79e64c53bd02cfcc1c48ea1aa / . / common / hw-gfx-gma-registers.ads
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Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1--
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]2-- Copyright (C) 2015-2017 secunet Security Networks AG
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +0200[diff] [blame]6-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]8--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
15with System;
16with HW.GFX.GMA;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]17
18private package HW.GFX.GMA.Registers
19with
20 Abstract_State =>
21 ((Address_State with Part_Of => GMA.State),
22 (Register_State with External, Part_Of => GMA.Device_State),
23 (GTT_State with External, Part_Of => GMA.Device_State)),
24 Initializes => Address_State
25is
26 type Registers_Invalid_Index is
27 (Invalid_Register, -- Allow a placeholder when access is not acceptable
28
29 RCS_RING_BUFFER_TAIL,
30 RCS_RING_BUFFER_HEAD,
31 RCS_RING_BUFFER_STRT,
32 RCS_RING_BUFFER_CTL,
33 QUIRK_02084,
34 QUIRK_02090,
35 HWSTAM,
36 MI_MODE,
37 INSTPM,
38 GT_MODE,
39 CACHE_MODE_0,
40 CTX_SIZE,
41 PP_DCLV_HIGH,
42 PP_DCLV_LOW,
43 GFX_MODE,
44 ARB_MODE,
45 HWS_PGA,
46 GAM_ECOCHK,
Arthur Heymans229ed1c2018-03-28 16:45:43 +0200[diff] [blame]47 GMCH_GMBUS0,
48 GMCH_GMBUS1,
49 GMCH_GMBUS2,
50 GMCH_GMBUS3,
51 GMCH_GMBUS4,
52 GMCH_GMBUS5,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]53 MBCTL,
54 UCGCTL1,
55 UCGCTL2,
56 VCS_RING_BUFFER_TAIL,
57 VCS_RING_BUFFER_HEAD,
58 VCS_RING_BUFFER_STRT,
59 VCS_RING_BUFFER_CTL,
60 SLEEP_PSMI_CONTROL,
61 VCS_HWSTAM,
62 VCS_PP_DCLV_HIGH,
63 VCS_PP_DCLV_LOW,
64 GAC_ECO_BITS,
65 BCS_RING_BUFFER_TAIL,
66 BCS_RING_BUFFER_HEAD,
67 BCS_RING_BUFFER_STRT,
68 BCS_RING_BUFFER_CTL,
69 BCS_HWSTAM,
70 BCS_PP_DCLV_HIGH,
71 BCS_PP_DCLV_LOW,
72 GAB_CTL_REG,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]73 CPU_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]74 FUSE_STATUS,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]75 ILK_DISPLAY_CHICKEN2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]76 DSPCLK_GATE_D,
77 FBA_CFB_BASE,
78 FBC_CTL,
79 IPS_CTL,
80 DEISR,
81 DEIMR,
82 DEIIR,
83 DEIER,
84 GTISR,
85 GTIMR,
86 GTIIR,
87 GTIER,
88 IIR,
89 HOTPLUG_CTL,
90 ARB_CTL,
91 DBUF_CTL,
92 WM_PIPE_A,
93 WM_PIPE_B,
94 WM1_LP_ILK,
95 WM2_LP_ILK,
96 WM3_LP_ILK,
97 WM_PIPE_C,
98 WM_LINETIME_A,
99 WM_LINETIME_B,
100 WM_LINETIME_C,
101 PWR_WELL_CTL_BIOS,
102 PWR_WELL_CTL_DRIVER,
103 PWR_WELL_CTL_KVMR,
104 PWR_WELL_CTL_DEBUG,
105 PWR_WELL_CTL5,
106 PWR_WELL_CTL6,
107 CDCLK_CTL,
108 LCPLL1_CTL,
109 LCPLL2_CTL,
110 SPLL_CTL,
111 WRPLL_CTL_1,
112 WRPLL_CTL_2,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]113 BXT_DE_PLL_ENABLE,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]114 BXT_PORT_PLL_ENABLE_A,
115 BXT_PORT_PLL_ENABLE_B,
116 BXT_PORT_PLL_ENABLE_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]117 PORT_CLK_SEL_DDIA,
118 PORT_CLK_SEL_DDIB,
119 PORT_CLK_SEL_DDIC,
120 PORT_CLK_SEL_DDID,
121 PORT_CLK_SEL_DDIE,
122 TRANSA_CLK_SEL,
123 TRANSB_CLK_SEL,
124 TRANSC_CLK_SEL,
125 NDE_RSTWRN_OPT,
126 BLC_PWM_CPU_CTL2,
127 BLC_PWM_CPU_CTL,
128 HTOTAL_A,
129 HBLANK_A,
130 HSYNC_A,
131 VTOTAL_A,
132 VBLANK_A,
133 VSYNC_A,
134 PIPEASRC,
135 PIPE_VSYNCSHIFT_A,
136 PIPEA_DATA_M1,
137 PIPEA_DATA_N1,
138 PIPEA_LINK_M1,
139 PIPEA_LINK_N1,
140 FDI_TX_CTL_A,
141 PIPEA_DDI_FUNC_CTL,
142 PIPEA_MSA_MISC,
143 SRD_CTL_A,
144 SRD_STATUS_A,
145 HTOTAL_B,
146 HBLANK_B,
147 HSYNC_B,
148 VTOTAL_B,
149 VBLANK_B,
150 VSYNC_B,
151 PIPEBSRC,
152 PIPE_VSYNCSHIFT_B,
153 PIPEB_DATA_M1,
154 PIPEB_DATA_N1,
155 PIPEB_LINK_M1,
156 PIPEB_LINK_N1,
157 FDI_TX_CTL_B,
Arthur Heymanse87d0d12018-03-28 17:02:49 +0200[diff] [blame]158 GMCH_PP_STATUS,
159 GMCH_PP_CONTROL,
160 GMCH_PP_ON_DELAYS,
161 GMCH_PP_OFF_DELAYS,
162 GMCH_PP_DIVISOR,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]163 PIPEB_DDI_FUNC_CTL,
164 PIPEB_MSA_MISC,
165 SRD_CTL_B,
166 SRD_STATUS_B,
167 HTOTAL_C,
168 HBLANK_C,
169 HSYNC_C,
170 VTOTAL_C,
171 VBLANK_C,
172 VSYNC_C,
173 PIPECSRC,
174 PIPE_VSYNCSHIFT_C,
175 PIPEC_DATA_M1,
176 PIPEC_DATA_N1,
177 PIPEC_LINK_M1,
178 PIPEC_LINK_N1,
179 FDI_TX_CTL_C,
180 PIPEC_DDI_FUNC_CTL,
181 PIPEC_MSA_MISC,
182 SRD_CTL_C,
183 SRD_STATUS_C,
184 DDI_BUF_CTL_A,
185 DDI_AUX_CTL_A,
186 DDI_AUX_DATA_A_1,
187 DDI_AUX_DATA_A_2,
188 DDI_AUX_DATA_A_3,
189 DDI_AUX_DATA_A_4,
190 DDI_AUX_DATA_A_5,
191 DDI_AUX_MUTEX_A,
192 DP_TP_CTL_A,
193 DDI_BUF_CTL_B,
194 DDI_AUX_CTL_B,
195 DDI_AUX_DATA_B_1,
196 DDI_AUX_DATA_B_2,
197 DDI_AUX_DATA_B_3,
198 DDI_AUX_DATA_B_4,
199 DDI_AUX_DATA_B_5,
200 DDI_AUX_MUTEX_B,
201 DP_TP_CTL_B,
202 DP_TP_STATUS_B,
203 DDI_BUF_CTL_C,
204 DDI_AUX_CTL_C,
205 DDI_AUX_DATA_C_1,
206 DDI_AUX_DATA_C_2,
207 DDI_AUX_DATA_C_3,
208 DDI_AUX_DATA_C_4,
209 DDI_AUX_DATA_C_5,
210 DDI_AUX_MUTEX_C,
211 DP_TP_CTL_C,
212 DP_TP_STATUS_C,
213 DDI_BUF_CTL_D,
214 DDI_AUX_CTL_D,
215 DDI_AUX_DATA_D_1,
216 DDI_AUX_DATA_D_2,
217 DDI_AUX_DATA_D_3,
218 DDI_AUX_DATA_D_4,
219 DDI_AUX_DATA_D_5,
220 DDI_AUX_MUTEX_D,
221 DP_TP_CTL_D,
222 DP_TP_STATUS_D,
223 DDI_BUF_CTL_E,
224 DP_TP_CTL_E,
225 DP_TP_STATUS_E,
226 SRD_CTL,
227 SRD_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]228 BXT_PHY_CTL_A,
229 BXT_PHY_CTL_B,
230 BXT_PHY_CTL_C,
231 BXT_PHY_CTL_FAM_EDP,
232 BXT_PHY_CTL_FAM_DDI,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]233 DDI_BUF_TRANS_A_S0T1,
234 DDI_BUF_TRANS_A_S0T2,
235 DDI_BUF_TRANS_A_S1T1,
236 DDI_BUF_TRANS_A_S1T2,
237 DDI_BUF_TRANS_A_S2T1,
238 DDI_BUF_TRANS_A_S2T2,
239 DDI_BUF_TRANS_A_S3T1,
240 DDI_BUF_TRANS_A_S3T2,
241 DDI_BUF_TRANS_A_S4T1,
242 DDI_BUF_TRANS_A_S4T2,
243 DDI_BUF_TRANS_A_S5T1,
244 DDI_BUF_TRANS_A_S5T2,
245 DDI_BUF_TRANS_A_S6T1,
246 DDI_BUF_TRANS_A_S6T2,
247 DDI_BUF_TRANS_A_S7T1,
248 DDI_BUF_TRANS_A_S7T2,
249 DDI_BUF_TRANS_A_S8T1,
250 DDI_BUF_TRANS_A_S8T2,
251 DDI_BUF_TRANS_A_S9T1,
252 DDI_BUF_TRANS_A_S9T2,
253 DDI_BUF_TRANS_B_S0T1,
254 DDI_BUF_TRANS_B_S0T2,
255 DDI_BUF_TRANS_B_S1T1,
256 DDI_BUF_TRANS_B_S1T2,
257 DDI_BUF_TRANS_B_S2T1,
258 DDI_BUF_TRANS_B_S2T2,
259 DDI_BUF_TRANS_B_S3T1,
260 DDI_BUF_TRANS_B_S3T2,
261 DDI_BUF_TRANS_B_S4T1,
262 DDI_BUF_TRANS_B_S4T2,
263 DDI_BUF_TRANS_B_S5T1,
264 DDI_BUF_TRANS_B_S5T2,
265 DDI_BUF_TRANS_B_S6T1,
266 DDI_BUF_TRANS_B_S6T2,
267 DDI_BUF_TRANS_B_S7T1,
268 DDI_BUF_TRANS_B_S7T2,
269 DDI_BUF_TRANS_B_S8T1,
270 DDI_BUF_TRANS_B_S8T2,
271 DDI_BUF_TRANS_B_S9T1,
272 DDI_BUF_TRANS_B_S9T2,
273 DDI_BUF_TRANS_C_S0T1,
274 DDI_BUF_TRANS_C_S0T2,
275 DDI_BUF_TRANS_C_S1T1,
276 DDI_BUF_TRANS_C_S1T2,
277 DDI_BUF_TRANS_C_S2T1,
278 DDI_BUF_TRANS_C_S2T2,
279 DDI_BUF_TRANS_C_S3T1,
280 DDI_BUF_TRANS_C_S3T2,
281 DDI_BUF_TRANS_C_S4T1,
282 DDI_BUF_TRANS_C_S4T2,
283 DDI_BUF_TRANS_C_S5T1,
284 DDI_BUF_TRANS_C_S5T2,
285 DDI_BUF_TRANS_C_S6T1,
286 DDI_BUF_TRANS_C_S6T2,
287 DDI_BUF_TRANS_C_S7T1,
288 DDI_BUF_TRANS_C_S7T2,
289 DDI_BUF_TRANS_C_S8T1,
290 DDI_BUF_TRANS_C_S8T2,
291 DDI_BUF_TRANS_C_S9T1,
292 DDI_BUF_TRANS_C_S9T2,
293 DDI_BUF_TRANS_D_S0T1,
294 DDI_BUF_TRANS_D_S0T2,
295 DDI_BUF_TRANS_D_S1T1,
296 DDI_BUF_TRANS_D_S1T2,
297 DDI_BUF_TRANS_D_S2T1,
298 DDI_BUF_TRANS_D_S2T2,
299 DDI_BUF_TRANS_D_S3T1,
300 DDI_BUF_TRANS_D_S3T2,
301 DDI_BUF_TRANS_D_S4T1,
302 DDI_BUF_TRANS_D_S4T2,
303 DDI_BUF_TRANS_D_S5T1,
304 DDI_BUF_TRANS_D_S5T2,
305 DDI_BUF_TRANS_D_S6T1,
306 DDI_BUF_TRANS_D_S6T2,
307 DDI_BUF_TRANS_D_S7T1,
308 DDI_BUF_TRANS_D_S7T2,
309 DDI_BUF_TRANS_D_S8T1,
310 DDI_BUF_TRANS_D_S8T2,
311 DDI_BUF_TRANS_D_S9T1,
312 DDI_BUF_TRANS_D_S9T2,
313 DDI_BUF_TRANS_E_S0T1,
314 DDI_BUF_TRANS_E_S0T2,
315 DDI_BUF_TRANS_E_S1T1,
316 DDI_BUF_TRANS_E_S1T2,
317 DDI_BUF_TRANS_E_S2T1,
318 DDI_BUF_TRANS_E_S2T2,
319 DDI_BUF_TRANS_E_S3T1,
320 DDI_BUF_TRANS_E_S3T2,
321 DDI_BUF_TRANS_E_S4T1,
322 DDI_BUF_TRANS_E_S4T2,
323 DDI_BUF_TRANS_E_S5T1,
324 DDI_BUF_TRANS_E_S5T2,
325 DDI_BUF_TRANS_E_S6T1,
326 DDI_BUF_TRANS_E_S6T2,
327 DDI_BUF_TRANS_E_S7T1,
328 DDI_BUF_TRANS_E_S7T2,
329 DDI_BUF_TRANS_E_S8T1,
330 DDI_BUF_TRANS_E_S8T2,
331 DDI_BUF_TRANS_E_S9T1,
332 DDI_BUF_TRANS_E_S9T2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]333 AUD_VID_DID,
334 PFA_WIN_POS,
335 PFA_WIN_SZ,
336 PFA_CTL_1,
337 PS_WIN_POS_1_A,
338 PS_WIN_SZ_1_A,
339 PS_CTRL_1_A,
340 PS_WIN_POS_2_A,
341 PS_WIN_SZ_2_A,
342 PS_CTRL_2_A,
343 PFB_WIN_POS,
344 PFB_WIN_SZ,
345 PFB_CTL_1,
346 PS_WIN_POS_1_B,
347 PS_WIN_SZ_1_B,
348 PS_CTRL_1_B,
349 PS_WIN_POS_2_B,
350 PS_WIN_SZ_2_B,
351 PS_CTRL_2_B,
352 PFC_WIN_POS,
353 PFC_WIN_SZ,
354 PFC_CTL_1,
355 PS_WIN_POS_1_C,
356 PS_WIN_SZ_1_C,
357 PS_CTRL_1_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]358 BXT_PORT_CL1CM_DW0_BC,
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]359 DISPIO_CR_TX_BMU_CR0,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]360 BXT_PORT_CL1CM_DW9_BC,
361 BXT_PORT_CL1CM_DW10_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]362 BXT_PORT_PLL_EBB_0_B,
363 BXT_PORT_PLL_EBB_4_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]364 DPLL1_CFGR1,
365 DPLL1_CFGR2,
366 DPLL2_CFGR1,
367 DPLL2_CFGR2,
368 DPLL3_CFGR1,
369 DPLL3_CFGR2,
370 DPLL_CTRL1,
371 DPLL_CTRL2,
372 DPLL_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]373 BXT_PORT_CL1CM_DW28_BC,
374 BXT_PORT_CL1CM_DW30_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]375 BXT_PORT_PLL_0_B,
376 BXT_PORT_PLL_1_B,
377 BXT_PORT_PLL_2_B,
378 BXT_PORT_PLL_3_B,
379 BXT_PORT_PLL_6_B,
380 BXT_PORT_PLL_8_B,
381 BXT_PORT_PLL_9_B,
382 BXT_PORT_PLL_10_B,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]383 BXT_PORT_REF_DW3_BC,
384 BXT_PORT_REF_DW6_BC,
385 BXT_PORT_REF_DW8_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]386 BXT_PORT_PLL_EBB_0_C,
387 BXT_PORT_PLL_EBB_4_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]388 BXT_PORT_CL2CM_DW6_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]389 BXT_PORT_PLL_0_C,
390 BXT_PORT_PLL_1_C,
391 BXT_PORT_PLL_2_C,
392 BXT_PORT_PLL_3_C,
393 BXT_PORT_PLL_6_C,
394 BXT_PORT_PLL_8_C,
395 BXT_PORT_PLL_9_C,
396 BXT_PORT_PLL_10_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]397 BXT_PORT_PCS_DW10_01_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]398 BXT_PORT_PCS_DW12_01_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]399 BXT_PORT_TX_DW2_LN0_B,
400 BXT_PORT_TX_DW3_LN0_B,
401 BXT_PORT_TX_DW4_LN0_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]402 BXT_PORT_TX_DW14_LN0_B,
403 BXT_PORT_TX_DW14_LN1_B,
404 BXT_PORT_TX_DW14_LN2_B,
405 BXT_PORT_TX_DW14_LN3_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]406 BXT_PORT_PCS_DW10_01_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]407 BXT_PORT_PCS_DW12_01_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]408 BXT_PORT_TX_DW2_LN0_C,
409 BXT_PORT_TX_DW3_LN0_C,
410 BXT_PORT_TX_DW4_LN0_C,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]411 BXT_PORT_TX_DW14_LN0_C,
412 BXT_PORT_TX_DW14_LN1_C,
413 BXT_PORT_TX_DW14_LN2_C,
414 BXT_PORT_TX_DW14_LN3_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]415 BXT_PORT_PCS_DW10_GRP_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]416 BXT_PORT_PCS_DW12_GRP_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]417 BXT_PORT_TX_DW2_GRP_B,
418 BXT_PORT_TX_DW3_GRP_B,
419 BXT_PORT_TX_DW4_GRP_B,
420 BXT_PORT_PCS_DW10_GRP_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]421 BXT_PORT_PCS_DW12_GRP_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]422 BXT_PORT_TX_DW2_GRP_C,
423 BXT_PORT_TX_DW3_GRP_C,
424 BXT_PORT_TX_DW4_GRP_C,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]425 BXT_DE_PLL_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]426 HTOTAL_EDP,
427 HBLANK_EDP,
428 HSYNC_EDP,
429 VTOTAL_EDP,
430 VBLANK_EDP,
431 VSYNC_EDP,
432 PIPE_EDP_DATA_M1,
433 PIPE_EDP_DATA_N1,
434 PIPE_EDP_LINK_M1,
435 PIPE_EDP_LINK_N1,
436 PIPE_EDP_DDI_FUNC_CTL,
437 PIPE_EDP_MSA_MISC,
438 SRD_CTL_EDP,
439 SRD_STATUS_EDP,
440 PIPE_SCANLINE_A,
441 PIPEACONF,
442 PIPEAMISC,
443 PIPE_FRMCNT_A,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]444 PIPEA_GMCH_DATA_M,
445 PIPEA_GMCH_DATA_N,
446 PIPEA_GMCH_LINK_M,
447 PIPEA_GMCH_LINK_N,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]448 DSPACNTR,
449 DSPALINOFF,
450 DSPASTRIDE,
451 PLANE_POS_1_A,
452 PLANE_SIZE_1_A,
453 DSPASURF,
454 DSPATILEOFF,
455 PLANE_WM_1_A_0,
456 PLANE_WM_1_A_1,
457 PLANE_WM_1_A_2,
458 PLANE_WM_1_A_3,
459 PLANE_WM_1_A_4,
460 PLANE_WM_1_A_5,
461 PLANE_WM_1_A_6,
462 PLANE_WM_1_A_7,
463 PLANE_BUF_CFG_1_A,
464 SPACNTR,
465 PIPE_SCANLINE_B,
466 PIPEBCONF,
467 PIPEBMISC,
468 PIPE_FRMCNT_B,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]469 PIPEB_GMCH_DATA_M,
470 PIPEB_GMCH_DATA_N,
471 PIPEB_GMCH_LINK_M,
472 PIPEB_GMCH_LINK_N,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]473 DSPBCNTR,
474 DSPBLINOFF,
475 DSPBSTRIDE,
476 PLANE_POS_1_B,
477 PLANE_SIZE_1_B,
478 DSPBSURF,
479 DSPBTILEOFF,
480 PLANE_WM_1_B_0,
481 PLANE_WM_1_B_1,
482 PLANE_WM_1_B_2,
483 PLANE_WM_1_B_3,
484 PLANE_WM_1_B_4,
485 PLANE_WM_1_B_5,
486 PLANE_WM_1_B_6,
487 PLANE_WM_1_B_7,
488 PLANE_BUF_CFG_1_B,
489 SPBCNTR,
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]490 GMCH_VGACNTRL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]491 PIPE_SCANLINE_C,
492 PIPECCONF,
493 PIPECMISC,
494 PIPE_FRMCNT_C,
495 DSPCCNTR,
496 DSPCLINOFF,
497 DSPCSTRIDE,
498 PLANE_POS_1_C,
499 PLANE_SIZE_1_C,
500 DSPCSURF,
501 DSPCTILEOFF,
502 PLANE_WM_1_C_0,
503 PLANE_WM_1_C_1,
504 PLANE_WM_1_C_2,
505 PLANE_WM_1_C_3,
506 PLANE_WM_1_C_4,
507 PLANE_WM_1_C_5,
508 PLANE_WM_1_C_6,
509 PLANE_WM_1_C_7,
510 PLANE_BUF_CFG_1_C,
511 SPCCNTR,
512 PIPE_EDP_CONF,
513 PCH_FDI_CHICKEN_B_C,
514 QUIRK_C2004,
515 SFUSE_STRAP,
516 PCH_DSPCLK_GATE_D,
517 SDEISR,
518 SDEIMR,
519 SDEIIR,
520 SDEIER,
521 SHOTPLUG_CTL,
522 PCH_GMBUS0,
523 PCH_GMBUS1,
524 PCH_GMBUS2,
525 PCH_GMBUS3,
526 PCH_GMBUS4,
527 PCH_GMBUS5,
528 SBI_ADDR,
529 SBI_DATA,
530 SBI_CTL_STAT,
531 PCH_DPLL_A,
532 PCH_DPLL_B,
533 PCH_PIXCLK_GATE,
534 PCH_FPA0,
535 PCH_FPA1,
536 PCH_FPB0,
537 PCH_FPB1,
538 PCH_DREF_CONTROL,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]539 PCH_RAWCLK_FREQ,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]540 PCH_DPLL_SEL,
541 PCH_PP_STATUS,
542 PCH_PP_CONTROL,
543 PCH_PP_ON_DELAYS,
544 PCH_PP_OFF_DELAYS,
545 PCH_PP_DIVISOR,
546 BLC_PWM_PCH_CTL1,
547 BLC_PWM_PCH_CTL2,
548 TRANS_HTOTAL_A,
549 TRANS_HBLANK_A,
550 TRANS_HSYNC_A,
551 TRANS_VTOTAL_A,
552 TRANS_VBLANK_A,
553 TRANS_VSYNC_A,
554 TRANS_VSYNCSHIFT_A,
555 TRANSA_DATA_M1,
556 TRANSA_DATA_N1,
557 TRANSA_DP_LINK_M1,
558 TRANSA_DP_LINK_N1,
559 TRANS_DP_CTL_A,
560 TRANS_HTOTAL_B,
561 TRANS_HBLANK_B,
562 TRANS_HSYNC_B,
563 TRANS_VTOTAL_B,
564 TRANS_VBLANK_B,
565 TRANS_VSYNC_B,
566 TRANS_VSYNCSHIFT_B,
567 TRANSB_DATA_M1,
568 TRANSB_DATA_N1,
569 TRANSB_DP_LINK_M1,
570 TRANSB_DP_LINK_N1,
571 PCH_ADPA,
572 PCH_HDMIB,
573 PCH_HDMIC,
574 PCH_HDMID,
575 PCH_LVDS,
576 TRANS_DP_CTL_B,
577 TRANS_HTOTAL_C,
578 TRANS_HBLANK_C,
579 TRANS_HSYNC_C,
580 TRANS_VTOTAL_C,
581 TRANS_VBLANK_C,
582 TRANS_VSYNC_C,
583 TRANS_VSYNCSHIFT_C,
584 TRANSC_DATA_M1,
585 TRANSC_DATA_N1,
586 TRANSC_DP_LINK_M1,
587 TRANSC_DP_LINK_N1,
588 TRANS_DP_CTL_C,
589 PCH_DP_B,
590 PCH_DP_AUX_CTL_B,
591 PCH_DP_AUX_DATA_B_1,
592 PCH_DP_AUX_DATA_B_2,
593 PCH_DP_AUX_DATA_B_3,
594 PCH_DP_AUX_DATA_B_4,
595 PCH_DP_AUX_DATA_B_5,
596 PCH_DP_C,
597 PCH_DP_AUX_CTL_C,
598 PCH_DP_AUX_DATA_C_1,
599 PCH_DP_AUX_DATA_C_2,
600 PCH_DP_AUX_DATA_C_3,
601 PCH_DP_AUX_DATA_C_4,
602 PCH_DP_AUX_DATA_C_5,
603 PCH_DP_D,
604 PCH_DP_AUX_CTL_D,
605 PCH_DP_AUX_DATA_D_1,
606 PCH_DP_AUX_DATA_D_2,
607 PCH_DP_AUX_DATA_D_3,
608 PCH_DP_AUX_DATA_D_4,
609 PCH_DP_AUX_DATA_D_5,
610 AUD_CONFIG_A,
611 PCH_AUD_VID_DID,
612 AUD_HDMIW_HDMIEDID_A,
613 AUD_CNTL_ST_A,
614 AUD_CNTRL_ST2,
615 AUD_CONFIG_B,
616 AUD_HDMIW_HDMIEDID_B,
617 AUD_CNTL_ST_B,
618 AUD_CONFIG_C,
619 AUD_HDMIW_HDMIEDID_C,
620 AUD_CNTL_ST_C,
621 TRANSACONF,
622 FDI_RXA_CTL,
623 FDI_RX_MISC_A,
624 FDI_RXA_IIR,
625 FDI_RXA_IMR,
626 FDI_RXA_TUSIZE1,
627 QUIRK_F0060,
628 TRANSA_CHICKEN2,
629 TRANSBCONF,
630 FDI_RXB_CTL,
631 FDI_RX_MISC_B,
632 FDI_RXB_IIR,
633 FDI_RXB_IMR,
634 FDI_RXB_TUSIZE1,
635 QUIRK_F1060,
636 TRANSB_CHICKEN2,
637 TRANSCCONF,
638 FDI_RXC_CTL,
639 FDI_RX_MISC_C,
640 FDI_RXC_IIR,
641 FDI_RXC_IMR,
642 FDI_RXC_TUSIZE1,
643 QUIRK_F2060,
644 TRANSC_CHICKEN2,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]645 BXT_P_CR_GT_DISP_PWRON,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]646 GT_MAILBOX,
647 GT_MAILBOX_DATA,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]648 GT_MAILBOX_DATA_1,
649 BXT_PORT_CL1CM_DW0_A,
650 BXT_PORT_CL1CM_DW9_A,
651 BXT_PORT_CL1CM_DW10_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]652 BXT_PORT_PLL_EBB_0_A,
653 BXT_PORT_PLL_EBB_4_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]654 BXT_PORT_CL1CM_DW28_A,
655 BXT_PORT_CL1CM_DW30_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]656 BXT_PORT_PLL_0_A,
657 BXT_PORT_PLL_1_A,
658 BXT_PORT_PLL_2_A,
659 BXT_PORT_PLL_3_A,
660 BXT_PORT_PLL_6_A,
661 BXT_PORT_PLL_8_A,
662 BXT_PORT_PLL_9_A,
663 BXT_PORT_PLL_10_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]664 BXT_PORT_REF_DW3_A,
665 BXT_PORT_REF_DW6_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]666 BXT_PORT_REF_DW8_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]667 BXT_PORT_PCS_DW10_01_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]668 BXT_PORT_PCS_DW12_01_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]669 BXT_PORT_TX_DW2_LN0_A,
670 BXT_PORT_TX_DW3_LN0_A,
671 BXT_PORT_TX_DW4_LN0_A,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]672 BXT_PORT_TX_DW14_LN0_A,
673 BXT_PORT_TX_DW14_LN1_A,
674 BXT_PORT_TX_DW14_LN2_A,
675 BXT_PORT_TX_DW14_LN3_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]676 BXT_PORT_PCS_DW10_GRP_A,
677 BXT_PORT_PCS_DW12_GRP_A,
678 BXT_PORT_TX_DW2_GRP_A,
679 BXT_PORT_TX_DW3_GRP_A,
680 BXT_PORT_TX_DW4_GRP_A);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]681
682 pragma Warnings
683 (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)",
684 Reason => "TODO: Should it matter?");
685 pragma Keep_Names (Registers_Invalid_Index);
686 pragma Warnings
687 (GNATprove, On, "pragma ""KEEP_NAMES"" ignored *(not yet supported)");
688
689 Register_Width : constant := 4;
690
691 for Registers_Invalid_Index use
692 (Invalid_Register => 0,
693
694 ---------------------------------------------------------------------------
695 -- Pipe A registers
696 ---------------------------------------------------------------------------
697
698 -- pipe timing registers
699
700 HTOTAL_A => 16#06_0000# / Register_Width,
701 HBLANK_A => 16#06_0004# / Register_Width,
702 HSYNC_A => 16#06_0008# / Register_Width,
703 VTOTAL_A => 16#06_000c# / Register_Width,
704 VBLANK_A => 16#06_0010# / Register_Width,
705 VSYNC_A => 16#06_0014# / Register_Width,
706 PIPEASRC => 16#06_001c# / Register_Width,
707 PIPEACONF => 16#07_0008# / Register_Width,
708 PIPEAMISC => 16#07_0030# / Register_Width,
709 TRANS_HTOTAL_A => 16#0e_0000# / Register_Width,
710 TRANS_HBLANK_A => 16#0e_0004# / Register_Width,
711 TRANS_HSYNC_A => 16#0e_0008# / Register_Width,
712 TRANS_VTOTAL_A => 16#0e_000c# / Register_Width,
713 TRANS_VBLANK_A => 16#0e_0010# / Register_Width,
714 TRANS_VSYNC_A => 16#0e_0014# / Register_Width,
715 TRANSA_DATA_M1 => 16#0e_0030# / Register_Width,
716 TRANSA_DATA_N1 => 16#0e_0034# / Register_Width,
717 TRANSA_DP_LINK_M1 => 16#0e_0040# / Register_Width,
718 TRANSA_DP_LINK_N1 => 16#0e_0044# / Register_Width,
719 PIPEA_DATA_M1 => 16#06_0030# / Register_Width,
720 PIPEA_DATA_N1 => 16#06_0034# / Register_Width,
721 PIPEA_LINK_M1 => 16#06_0040# / Register_Width,
722 PIPEA_LINK_N1 => 16#06_0044# / Register_Width,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]723 PIPEA_GMCH_DATA_M => 16#07_0050# / Register_Width,
724 PIPEA_GMCH_DATA_N => 16#07_0054# / Register_Width,
725 PIPEA_GMCH_LINK_M => 16#07_0060# / Register_Width,
726 PIPEA_GMCH_LINK_N => 16#07_0064# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]727 PIPEA_DDI_FUNC_CTL => 16#06_0400# / Register_Width,
728 PIPEA_MSA_MISC => 16#06_0410# / Register_Width,
729
730 -- PCH sideband interface registers
731 SBI_ADDR => 16#0c_6000# / Register_Width,
732 SBI_DATA => 16#0c_6004# / Register_Width,
733 SBI_CTL_STAT => 16#0c_6008# / Register_Width,
734
735 -- clock registers
736 PCH_DPLL_A => 16#0c_6014# / Register_Width,
737 PCH_PIXCLK_GATE => 16#0c_6020# / Register_Width,
738 PCH_FPA0 => 16#0c_6040# / Register_Width,
739 PCH_FPA1 => 16#0c_6044# / Register_Width,
740
741 -- panel fitter
742 PFA_CTL_1 => 16#06_8080# / Register_Width,
743 PFA_WIN_POS => 16#06_8070# / Register_Width,
744 PFA_WIN_SZ => 16#06_8074# / Register_Width,
745 PS_WIN_POS_1_A => 16#06_8170# / Register_Width,
746 PS_WIN_SZ_1_A => 16#06_8174# / Register_Width,
747 PS_CTRL_1_A => 16#06_8180# / Register_Width,
748 PS_WIN_POS_2_A => 16#06_8270# / Register_Width,
749 PS_WIN_SZ_2_A => 16#06_8274# / Register_Width,
750 PS_CTRL_2_A => 16#06_8280# / Register_Width,
751
752 -- display control
753 DSPACNTR => 16#07_0180# / Register_Width,
754 DSPALINOFF => 16#07_0184# / Register_Width,
755 DSPASTRIDE => 16#07_0188# / Register_Width,
756 PLANE_POS_1_A => 16#07_018c# / Register_Width,
757 PLANE_SIZE_1_A => 16#07_0190# / Register_Width,
758 DSPASURF => 16#07_019c# / Register_Width,
759 DSPATILEOFF => 16#07_01a4# / Register_Width,
760
761 -- sprite control
762 SPACNTR => 16#07_0280# / Register_Width,
763
764 -- FDI and PCH transcoder control
765 FDI_TX_CTL_A => 16#06_0100# / Register_Width,
766 FDI_RXA_CTL => 16#0f_000c# / Register_Width,
767 FDI_RX_MISC_A => 16#0f_0010# / Register_Width,
768 FDI_RXA_IIR => 16#0f_0014# / Register_Width,
769 FDI_RXA_IMR => 16#0f_0018# / Register_Width,
770 FDI_RXA_TUSIZE1 => 16#0f_0030# / Register_Width,
771 TRANSACONF => 16#0f_0008# / Register_Width,
772 TRANSA_CHICKEN2 => 16#0f_0064# / Register_Width,
773
774 -- watermark registers
775 WM_LINETIME_A => 16#04_5270# / Register_Width,
776 PLANE_WM_1_A_0 => 16#07_0240# / Register_Width,
777 PLANE_WM_1_A_1 => 16#07_0244# / Register_Width,
778 PLANE_WM_1_A_2 => 16#07_0248# / Register_Width,
779 PLANE_WM_1_A_3 => 16#07_024c# / Register_Width,
780 PLANE_WM_1_A_4 => 16#07_0250# / Register_Width,
781 PLANE_WM_1_A_5 => 16#07_0254# / Register_Width,
782 PLANE_WM_1_A_6 => 16#07_0258# / Register_Width,
783 PLANE_WM_1_A_7 => 16#07_025c# / Register_Width,
784 PLANE_BUF_CFG_1_A => 16#07_027c# / Register_Width,
785
786 -- CPU transcoder clock select
787 TRANSA_CLK_SEL => 16#04_6140# / Register_Width,
788
789 ---------------------------------------------------------------------------
790 -- Pipe B registers
791 ---------------------------------------------------------------------------
792
793 -- pipe timing registers
794
795 HTOTAL_B => 16#06_1000# / Register_Width,
796 HBLANK_B => 16#06_1004# / Register_Width,
797 HSYNC_B => 16#06_1008# / Register_Width,
798 VTOTAL_B => 16#06_100c# / Register_Width,
799 VBLANK_B => 16#06_1010# / Register_Width,
800 VSYNC_B => 16#06_1014# / Register_Width,
801 PIPEBSRC => 16#06_101c# / Register_Width,
802 PIPEBCONF => 16#07_1008# / Register_Width,
803 PIPEBMISC => 16#07_1030# / Register_Width,
804 TRANS_HTOTAL_B => 16#0e_1000# / Register_Width,
805 TRANS_HBLANK_B => 16#0e_1004# / Register_Width,
806 TRANS_HSYNC_B => 16#0e_1008# / Register_Width,
807 TRANS_VTOTAL_B => 16#0e_100c# / Register_Width,
808 TRANS_VBLANK_B => 16#0e_1010# / Register_Width,
809 TRANS_VSYNC_B => 16#0e_1014# / Register_Width,
810 TRANSB_DATA_M1 => 16#0e_1030# / Register_Width,
811 TRANSB_DATA_N1 => 16#0e_1034# / Register_Width,
812 TRANSB_DP_LINK_M1 => 16#0e_1040# / Register_Width,
813 TRANSB_DP_LINK_N1 => 16#0e_1044# / Register_Width,
814 PIPEB_DATA_M1 => 16#06_1030# / Register_Width,
815 PIPEB_DATA_N1 => 16#06_1034# / Register_Width,
816 PIPEB_LINK_M1 => 16#06_1040# / Register_Width,
817 PIPEB_LINK_N1 => 16#06_1044# / Register_Width,
Arthur Heymans636390c2018-03-28 16:52:13 +0200[diff] [blame]818 PIPEB_GMCH_DATA_M => 16#07_1050# / Register_Width,
819 PIPEB_GMCH_DATA_N => 16#07_1054# / Register_Width,
820 PIPEB_GMCH_LINK_M => 16#07_1060# / Register_Width,
821 PIPEB_GMCH_LINK_N => 16#07_1064# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]822 PIPEB_DDI_FUNC_CTL => 16#06_1400# / Register_Width,
823 PIPEB_MSA_MISC => 16#06_1410# / Register_Width,
824
825 -- clock registers
826 PCH_DPLL_B => 16#0c_6018# / Register_Width,
827 PCH_FPB0 => 16#0c_6048# / Register_Width,
828 PCH_FPB1 => 16#0c_604c# / Register_Width,
829
830 -- panel fitter
831 PFB_CTL_1 => 16#06_8880# / Register_Width,
832 PFB_WIN_POS => 16#06_8870# / Register_Width,
833 PFB_WIN_SZ => 16#06_8874# / Register_Width,
834 PS_WIN_POS_1_B => 16#06_8970# / Register_Width,
835 PS_WIN_SZ_1_B => 16#06_8974# / Register_Width,
836 PS_CTRL_1_B => 16#06_8980# / Register_Width,
837 PS_WIN_POS_2_B => 16#06_8a70# / Register_Width,
838 PS_WIN_SZ_2_B => 16#06_8a74# / Register_Width,
839 PS_CTRL_2_B => 16#06_8a80# / Register_Width,
840
841 -- display control
842 DSPBCNTR => 16#07_1180# / Register_Width,
843 DSPBLINOFF => 16#07_1184# / Register_Width,
844 DSPBSTRIDE => 16#07_1188# / Register_Width,
845 PLANE_POS_1_B => 16#07_118c# / Register_Width,
846 PLANE_SIZE_1_B => 16#07_1190# / Register_Width,
847 DSPBSURF => 16#07_119c# / Register_Width,
848 DSPBTILEOFF => 16#07_11a4# / Register_Width,
849
850 -- sprite control
851 SPBCNTR => 16#07_1280# / Register_Width,
852
853 -- FDI and PCH transcoder control
854 FDI_TX_CTL_B => 16#06_1100# / Register_Width,
855 FDI_RXB_CTL => 16#0f_100c# / Register_Width,
856 FDI_RX_MISC_B => 16#0f_1010# / Register_Width,
857 FDI_RXB_IIR => 16#0f_1014# / Register_Width,
858 FDI_RXB_IMR => 16#0f_1018# / Register_Width,
859 FDI_RXB_TUSIZE1 => 16#0f_1030# / Register_Width,
860 TRANSBCONF => 16#0f_1008# / Register_Width,
861 TRANSB_CHICKEN2 => 16#0f_1064# / Register_Width,
862
863 -- watermark registers
864 WM_LINETIME_B => 16#04_5274# / Register_Width,
865 PLANE_WM_1_B_0 => 16#07_1240# / Register_Width,
866 PLANE_WM_1_B_1 => 16#07_1244# / Register_Width,
867 PLANE_WM_1_B_2 => 16#07_1248# / Register_Width,
868 PLANE_WM_1_B_3 => 16#07_124c# / Register_Width,
869 PLANE_WM_1_B_4 => 16#07_1250# / Register_Width,
870 PLANE_WM_1_B_5 => 16#07_1254# / Register_Width,
871 PLANE_WM_1_B_6 => 16#07_1258# / Register_Width,
872 PLANE_WM_1_B_7 => 16#07_125c# / Register_Width,
873 PLANE_BUF_CFG_1_B => 16#07_127c# / Register_Width,
874
875 -- CPU transcoder clock select
876 TRANSB_CLK_SEL => 16#04_6144# / Register_Width,
877
878 ---------------------------------------------------------------------------
879 -- Pipe C registers
880 ---------------------------------------------------------------------------
881
882 -- pipe timing registers
883
884 HTOTAL_C => 16#06_2000# / Register_Width,
885 HBLANK_C => 16#06_2004# / Register_Width,
886 HSYNC_C => 16#06_2008# / Register_Width,
887 VTOTAL_C => 16#06_200c# / Register_Width,
888 VBLANK_C => 16#06_2010# / Register_Width,
889 VSYNC_C => 16#06_2014# / Register_Width,
890 PIPECSRC => 16#06_201c# / Register_Width,
891 PIPECCONF => 16#07_2008# / Register_Width,
892 PIPECMISC => 16#07_2030# / Register_Width,
893 TRANS_HTOTAL_C => 16#0e_2000# / Register_Width,
894 TRANS_HBLANK_C => 16#0e_2004# / Register_Width,
895 TRANS_HSYNC_C => 16#0e_2008# / Register_Width,
896 TRANS_VTOTAL_C => 16#0e_200c# / Register_Width,
897 TRANS_VBLANK_C => 16#0e_2010# / Register_Width,
898 TRANS_VSYNC_C => 16#0e_2014# / Register_Width,
899 TRANSC_DATA_M1 => 16#0e_2030# / Register_Width,
900 TRANSC_DATA_N1 => 16#0e_2034# / Register_Width,
901 TRANSC_DP_LINK_M1 => 16#0e_2040# / Register_Width,
902 TRANSC_DP_LINK_N1 => 16#0e_2044# / Register_Width,
903 PIPEC_DATA_M1 => 16#06_2030# / Register_Width,
904 PIPEC_DATA_N1 => 16#06_2034# / Register_Width,
905 PIPEC_LINK_M1 => 16#06_2040# / Register_Width,
906 PIPEC_LINK_N1 => 16#06_2044# / Register_Width,
907 PIPEC_DDI_FUNC_CTL => 16#06_2400# / Register_Width,
908 PIPEC_MSA_MISC => 16#06_2410# / Register_Width,
909
910 -- panel fitter
911 PFC_CTL_1 => 16#06_9080# / Register_Width,
912 PFC_WIN_POS => 16#06_9070# / Register_Width,
913 PFC_WIN_SZ => 16#06_9074# / Register_Width,
914 PS_WIN_POS_1_C => 16#06_9170# / Register_Width,
915 PS_WIN_SZ_1_C => 16#06_9174# / Register_Width,
916 PS_CTRL_1_C => 16#06_9180# / Register_Width,
917
918 -- display control
919 DSPCCNTR => 16#07_2180# / Register_Width,
920 DSPCLINOFF => 16#07_2184# / Register_Width,
921 DSPCSTRIDE => 16#07_2188# / Register_Width,
922 PLANE_POS_1_C => 16#07_218c# / Register_Width,
923 PLANE_SIZE_1_C => 16#07_2190# / Register_Width,
924 DSPCSURF => 16#07_219c# / Register_Width,
925 DSPCTILEOFF => 16#07_21a4# / Register_Width,
926
927 -- sprite control
928 SPCCNTR => 16#07_2280# / Register_Width,
929
930 -- PCH transcoder control
931 FDI_TX_CTL_C => 16#06_2100# / Register_Width,
932 FDI_RXC_CTL => 16#0f_200c# / Register_Width,
933 FDI_RX_MISC_C => 16#0f_2010# / Register_Width,
934 FDI_RXC_IIR => 16#0f_2014# / Register_Width,
935 FDI_RXC_IMR => 16#0f_2018# / Register_Width,
936 FDI_RXC_TUSIZE1 => 16#0f_2030# / Register_Width,
937 TRANSCCONF => 16#0f_2008# / Register_Width,
938 TRANSC_CHICKEN2 => 16#0f_2064# / Register_Width,
939
940 -- watermark registers
941 WM_LINETIME_C => 16#04_5278# / Register_Width,
942 PLANE_WM_1_C_0 => 16#07_2240# / Register_Width,
943 PLANE_WM_1_C_1 => 16#07_2244# / Register_Width,
944 PLANE_WM_1_C_2 => 16#07_2248# / Register_Width,
945 PLANE_WM_1_C_3 => 16#07_224c# / Register_Width,
946 PLANE_WM_1_C_4 => 16#07_2250# / Register_Width,
947 PLANE_WM_1_C_5 => 16#07_2254# / Register_Width,
948 PLANE_WM_1_C_6 => 16#07_2258# / Register_Width,
949 PLANE_WM_1_C_7 => 16#07_225c# / Register_Width,
950 PLANE_BUF_CFG_1_C => 16#07_227c# / Register_Width,
951
952 -- CPU transcoder clock select
953 TRANSC_CLK_SEL => 16#04_6148# / Register_Width,
954
955 ---------------------------------------------------------------------------
956 -- Pipe EDP registers
957 ---------------------------------------------------------------------------
958
959 -- pipe timing registers
960
961 HTOTAL_EDP => 16#06_f000# / Register_Width,
962 HBLANK_EDP => 16#06_f004# / Register_Width,
963 HSYNC_EDP => 16#06_f008# / Register_Width,
964 VTOTAL_EDP => 16#06_f00c# / Register_Width,
965 VBLANK_EDP => 16#06_f010# / Register_Width,
966 VSYNC_EDP => 16#06_f014# / Register_Width,
967 PIPE_EDP_CONF => 16#07_f008# / Register_Width,
968 PIPE_EDP_DATA_M1 => 16#06_f030# / Register_Width,
969 PIPE_EDP_DATA_N1 => 16#06_f034# / Register_Width,
970 PIPE_EDP_LINK_M1 => 16#06_f040# / Register_Width,
971 PIPE_EDP_LINK_N1 => 16#06_f044# / Register_Width,
972 PIPE_EDP_DDI_FUNC_CTL => 16#06_f400# / Register_Width,
973 PIPE_EDP_MSA_MISC => 16#06_f410# / Register_Width,
974
975 -- PSR registers
976 SRD_CTL => 16#06_4800# / Register_Width,
977 SRD_CTL_A => 16#06_0800# / Register_Width,
978 SRD_CTL_B => 16#06_1800# / Register_Width,
979 SRD_CTL_C => 16#06_2800# / Register_Width,
980 SRD_CTL_EDP => 16#06_f800# / Register_Width,
981 SRD_STATUS => 16#06_4840# / Register_Width,
982 SRD_STATUS_A => 16#06_0840# / Register_Width,
983 SRD_STATUS_B => 16#06_1840# / Register_Width,
984 SRD_STATUS_C => 16#06_2840# / Register_Width,
985 SRD_STATUS_EDP => 16#06_f840# / Register_Width,
986
987 -- DDI registers
988 DDI_BUF_CTL_A => 16#06_4000# / Register_Width, -- aliased by DP_CTL_A
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]989 DDI_BUF_TRANS_A_S0T1 => 16#06_4e00# / Register_Width,
990 DDI_BUF_TRANS_A_S0T2 => 16#06_4e04# / Register_Width,
991 DDI_BUF_TRANS_A_S1T1 => 16#06_4e08# / Register_Width,
992 DDI_BUF_TRANS_A_S1T2 => 16#06_4e0c# / Register_Width,
993 DDI_BUF_TRANS_A_S2T1 => 16#06_4e10# / Register_Width,
994 DDI_BUF_TRANS_A_S2T2 => 16#06_4e14# / Register_Width,
995 DDI_BUF_TRANS_A_S3T1 => 16#06_4e18# / Register_Width,
996 DDI_BUF_TRANS_A_S3T2 => 16#06_4e1c# / Register_Width,
997 DDI_BUF_TRANS_A_S4T1 => 16#06_4e20# / Register_Width,
998 DDI_BUF_TRANS_A_S4T2 => 16#06_4e24# / Register_Width,
999 DDI_BUF_TRANS_A_S5T1 => 16#06_4e28# / Register_Width,
1000 DDI_BUF_TRANS_A_S5T2 => 16#06_4e2c# / Register_Width,
1001 DDI_BUF_TRANS_A_S6T1 => 16#06_4e30# / Register_Width,
1002 DDI_BUF_TRANS_A_S6T2 => 16#06_4e34# / Register_Width,
1003 DDI_BUF_TRANS_A_S7T1 => 16#06_4e38# / Register_Width,
1004 DDI_BUF_TRANS_A_S7T2 => 16#06_4e3c# / Register_Width,
1005 DDI_BUF_TRANS_A_S8T1 => 16#06_4e40# / Register_Width,
1006 DDI_BUF_TRANS_A_S8T2 => 16#06_4e44# / Register_Width,
1007 DDI_BUF_TRANS_A_S9T1 => 16#06_4e48# / Register_Width,
1008 DDI_BUF_TRANS_A_S9T2 => 16#06_4e4c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1009 DDI_AUX_CTL_A => 16#06_4010# / Register_Width, -- aliased by DP_AUX_CTL_A
1010 DDI_AUX_DATA_A_1 => 16#06_4014# / Register_Width, -- aliased by DP_AUX_DATA_A_1
1011 DDI_AUX_DATA_A_2 => 16#06_4018# / Register_Width, -- aliased by DP_AUX_DATA_A_2
1012 DDI_AUX_DATA_A_3 => 16#06_401c# / Register_Width, -- aliased by DP_AUX_DATA_A_3
1013 DDI_AUX_DATA_A_4 => 16#06_4020# / Register_Width, -- aliased by DP_AUX_DATA_A_4
1014 DDI_AUX_DATA_A_5 => 16#06_4024# / Register_Width, -- aliased by DP_AUX_DATA_A_5
1015 DDI_AUX_MUTEX_A => 16#06_402c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1016
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1017 DDI_BUF_CTL_B => 16#06_4100# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1018 DDI_BUF_TRANS_B_S0T1 => 16#06_4e60# / Register_Width,
1019 DDI_BUF_TRANS_B_S0T2 => 16#06_4e64# / Register_Width,
1020 DDI_BUF_TRANS_B_S1T1 => 16#06_4e68# / Register_Width,
1021 DDI_BUF_TRANS_B_S1T2 => 16#06_4e6c# / Register_Width,
1022 DDI_BUF_TRANS_B_S2T1 => 16#06_4e70# / Register_Width,
1023 DDI_BUF_TRANS_B_S2T2 => 16#06_4e74# / Register_Width,
1024 DDI_BUF_TRANS_B_S3T1 => 16#06_4e78# / Register_Width,
1025 DDI_BUF_TRANS_B_S3T2 => 16#06_4e7c# / Register_Width,
1026 DDI_BUF_TRANS_B_S4T1 => 16#06_4e80# / Register_Width,
1027 DDI_BUF_TRANS_B_S4T2 => 16#06_4e84# / Register_Width,
1028 DDI_BUF_TRANS_B_S5T1 => 16#06_4e88# / Register_Width,
1029 DDI_BUF_TRANS_B_S5T2 => 16#06_4e8c# / Register_Width,
1030 DDI_BUF_TRANS_B_S6T1 => 16#06_4e90# / Register_Width,
1031 DDI_BUF_TRANS_B_S6T2 => 16#06_4e94# / Register_Width,
1032 DDI_BUF_TRANS_B_S7T1 => 16#06_4e98# / Register_Width,
1033 DDI_BUF_TRANS_B_S7T2 => 16#06_4e9c# / Register_Width,
1034 DDI_BUF_TRANS_B_S8T1 => 16#06_4ea0# / Register_Width,
1035 DDI_BUF_TRANS_B_S8T2 => 16#06_4ea4# / Register_Width,
1036 DDI_BUF_TRANS_B_S9T1 => 16#06_4ea8# / Register_Width,
1037 DDI_BUF_TRANS_B_S9T2 => 16#06_4eac# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1038 DDI_AUX_CTL_B => 16#06_4110# / Register_Width,
1039 DDI_AUX_DATA_B_1 => 16#06_4114# / Register_Width,
1040 DDI_AUX_DATA_B_2 => 16#06_4118# / Register_Width,
1041 DDI_AUX_DATA_B_3 => 16#06_411c# / Register_Width,
1042 DDI_AUX_DATA_B_4 => 16#06_4120# / Register_Width,
1043 DDI_AUX_DATA_B_5 => 16#06_4124# / Register_Width,
1044 DDI_AUX_MUTEX_B => 16#06_412c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1045
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1046 DDI_BUF_CTL_C => 16#06_4200# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1047 DDI_BUF_TRANS_C_S0T1 => 16#06_4ec0# / Register_Width,
1048 DDI_BUF_TRANS_C_S0T2 => 16#06_4ec4# / Register_Width,
1049 DDI_BUF_TRANS_C_S1T1 => 16#06_4ec8# / Register_Width,
1050 DDI_BUF_TRANS_C_S1T2 => 16#06_4ecc# / Register_Width,
1051 DDI_BUF_TRANS_C_S2T1 => 16#06_4ed0# / Register_Width,
1052 DDI_BUF_TRANS_C_S2T2 => 16#06_4ed4# / Register_Width,
1053 DDI_BUF_TRANS_C_S3T1 => 16#06_4ed8# / Register_Width,
1054 DDI_BUF_TRANS_C_S3T2 => 16#06_4edc# / Register_Width,
1055 DDI_BUF_TRANS_C_S4T1 => 16#06_4ee0# / Register_Width,
1056 DDI_BUF_TRANS_C_S4T2 => 16#06_4ee4# / Register_Width,
1057 DDI_BUF_TRANS_C_S5T1 => 16#06_4ee8# / Register_Width,
1058 DDI_BUF_TRANS_C_S5T2 => 16#06_4eec# / Register_Width,
1059 DDI_BUF_TRANS_C_S6T1 => 16#06_4ef0# / Register_Width,
1060 DDI_BUF_TRANS_C_S6T2 => 16#06_4ef4# / Register_Width,
1061 DDI_BUF_TRANS_C_S7T1 => 16#06_4ef8# / Register_Width,
1062 DDI_BUF_TRANS_C_S7T2 => 16#06_4efc# / Register_Width,
1063 DDI_BUF_TRANS_C_S8T1 => 16#06_4f00# / Register_Width,
1064 DDI_BUF_TRANS_C_S8T2 => 16#06_4f04# / Register_Width,
1065 DDI_BUF_TRANS_C_S9T1 => 16#06_4f08# / Register_Width,
1066 DDI_BUF_TRANS_C_S9T2 => 16#06_4f0c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1067 DDI_AUX_CTL_C => 16#06_4210# / Register_Width,
1068 DDI_AUX_DATA_C_1 => 16#06_4214# / Register_Width,
1069 DDI_AUX_DATA_C_2 => 16#06_4218# / Register_Width,
1070 DDI_AUX_DATA_C_3 => 16#06_421c# / Register_Width,
1071 DDI_AUX_DATA_C_4 => 16#06_4220# / Register_Width,
1072 DDI_AUX_DATA_C_5 => 16#06_4224# / Register_Width,
1073 DDI_AUX_MUTEX_C => 16#06_422c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1074
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1075 DDI_BUF_CTL_D => 16#06_4300# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1076 DDI_BUF_TRANS_D_S0T1 => 16#06_4f20# / Register_Width,
1077 DDI_BUF_TRANS_D_S0T2 => 16#06_4f24# / Register_Width,
1078 DDI_BUF_TRANS_D_S1T1 => 16#06_4f28# / Register_Width,
1079 DDI_BUF_TRANS_D_S1T2 => 16#06_4f2c# / Register_Width,
1080 DDI_BUF_TRANS_D_S2T1 => 16#06_4f30# / Register_Width,
1081 DDI_BUF_TRANS_D_S2T2 => 16#06_4f34# / Register_Width,
1082 DDI_BUF_TRANS_D_S3T1 => 16#06_4f38# / Register_Width,
1083 DDI_BUF_TRANS_D_S3T2 => 16#06_4f3c# / Register_Width,
1084 DDI_BUF_TRANS_D_S4T1 => 16#06_4f40# / Register_Width,
1085 DDI_BUF_TRANS_D_S4T2 => 16#06_4f44# / Register_Width,
1086 DDI_BUF_TRANS_D_S5T1 => 16#06_4f48# / Register_Width,
1087 DDI_BUF_TRANS_D_S5T2 => 16#06_4f4c# / Register_Width,
1088 DDI_BUF_TRANS_D_S6T1 => 16#06_4f50# / Register_Width,
1089 DDI_BUF_TRANS_D_S6T2 => 16#06_4f54# / Register_Width,
1090 DDI_BUF_TRANS_D_S7T1 => 16#06_4f58# / Register_Width,
1091 DDI_BUF_TRANS_D_S7T2 => 16#06_4f5c# / Register_Width,
1092 DDI_BUF_TRANS_D_S8T1 => 16#06_4f60# / Register_Width,
1093 DDI_BUF_TRANS_D_S8T2 => 16#06_4f64# / Register_Width,
1094 DDI_BUF_TRANS_D_S9T1 => 16#06_4f68# / Register_Width,
1095 DDI_BUF_TRANS_D_S9T2 => 16#06_4f6c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1096 DDI_AUX_CTL_D => 16#06_4310# / Register_Width,
1097 DDI_AUX_DATA_D_1 => 16#06_4314# / Register_Width,
1098 DDI_AUX_DATA_D_2 => 16#06_4318# / Register_Width,
1099 DDI_AUX_DATA_D_3 => 16#06_431c# / Register_Width,
1100 DDI_AUX_DATA_D_4 => 16#06_4320# / Register_Width,
1101 DDI_AUX_DATA_D_5 => 16#06_4324# / Register_Width,
1102 DDI_AUX_MUTEX_D => 16#06_432c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1103
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1104 DDI_BUF_CTL_E => 16#06_4400# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1105 DDI_BUF_TRANS_E_S0T1 => 16#06_4f80# / Register_Width,
1106 DDI_BUF_TRANS_E_S0T2 => 16#06_4f84# / Register_Width,
1107 DDI_BUF_TRANS_E_S1T1 => 16#06_4f88# / Register_Width,
1108 DDI_BUF_TRANS_E_S1T2 => 16#06_4f8c# / Register_Width,
1109 DDI_BUF_TRANS_E_S2T1 => 16#06_4f90# / Register_Width,
1110 DDI_BUF_TRANS_E_S2T2 => 16#06_4f94# / Register_Width,
1111 DDI_BUF_TRANS_E_S3T1 => 16#06_4f98# / Register_Width,
1112 DDI_BUF_TRANS_E_S3T2 => 16#06_4f9c# / Register_Width,
1113 DDI_BUF_TRANS_E_S4T1 => 16#06_4fa0# / Register_Width,
1114 DDI_BUF_TRANS_E_S4T2 => 16#06_4fa4# / Register_Width,
1115 DDI_BUF_TRANS_E_S5T1 => 16#06_4fa8# / Register_Width,
1116 DDI_BUF_TRANS_E_S5T2 => 16#06_4fac# / Register_Width,
1117 DDI_BUF_TRANS_E_S6T1 => 16#06_4fb0# / Register_Width,
1118 DDI_BUF_TRANS_E_S6T2 => 16#06_4fb4# / Register_Width,
1119 DDI_BUF_TRANS_E_S7T1 => 16#06_4fb8# / Register_Width,
1120 DDI_BUF_TRANS_E_S7T2 => 16#06_4fbc# / Register_Width,
1121 DDI_BUF_TRANS_E_S8T1 => 16#06_4fc0# / Register_Width,
1122 DDI_BUF_TRANS_E_S8T2 => 16#06_4fc4# / Register_Width,
1123 DDI_BUF_TRANS_E_S9T1 => 16#06_4fc8# / Register_Width,
1124 DDI_BUF_TRANS_E_S9T2 => 16#06_4fcc# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1125 DP_TP_CTL_A => 16#06_4040# / Register_Width,
1126 DP_TP_CTL_B => 16#06_4140# / Register_Width,
1127 DP_TP_CTL_C => 16#06_4240# / Register_Width,
1128 DP_TP_CTL_D => 16#06_4340# / Register_Width,
1129 DP_TP_CTL_E => 16#06_4440# / Register_Width,
1130 DP_TP_STATUS_B => 16#06_4144# / Register_Width,
1131 DP_TP_STATUS_C => 16#06_4244# / Register_Width,
1132 DP_TP_STATUS_D => 16#06_4344# / Register_Width,
1133 DP_TP_STATUS_E => 16#06_4444# / Register_Width,
1134 PORT_CLK_SEL_DDIA => 16#04_6100# / Register_Width,
1135 PORT_CLK_SEL_DDIB => 16#04_6104# / Register_Width,
1136 PORT_CLK_SEL_DDIC => 16#04_6108# / Register_Width,
1137 PORT_CLK_SEL_DDID => 16#04_610c# / Register_Width,
1138 PORT_CLK_SEL_DDIE => 16#04_6110# / Register_Width,
1139
Nico Huber58afc202017-06-12 21:34:55 +0200[diff] [blame]1140 -- Skylake I_boost configuration
1141 DISPIO_CR_TX_BMU_CR0 => 16#06_c00c# / Register_Width,
1142
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1143 -- Skylake DPLL registers
1144 DPLL1_CFGR1 => 16#06_c040# / Register_Width,
1145 DPLL1_CFGR2 => 16#06_c044# / Register_Width,
1146 DPLL2_CFGR1 => 16#06_c048# / Register_Width,
1147 DPLL2_CFGR2 => 16#06_c04c# / Register_Width,
1148 DPLL3_CFGR1 => 16#06_c050# / Register_Width,
1149 DPLL3_CFGR2 => 16#06_c054# / Register_Width,
1150 DPLL_CTRL1 => 16#06_c058# / Register_Width,
1151 DPLL_CTRL2 => 16#06_c05c# / Register_Width,
1152 DPLL_STATUS => 16#06_c060# / Register_Width,
1153
1154 -- CD CLK register
1155 CDCLK_CTL => 16#04_6000# / Register_Width,
1156
1157 -- Skylake LCPLL registers
1158 LCPLL1_CTL => 16#04_6010# / Register_Width,
1159 LCPLL2_CTL => 16#04_6014# / Register_Width,
1160
1161 -- SPLL register
1162 SPLL_CTL => 16#04_6020# / Register_Width,
1163
1164 -- WRPLL registers
1165 WRPLL_CTL_1 => 16#04_6040# / Register_Width,
1166 WRPLL_CTL_2 => 16#04_6060# / Register_Width,
1167
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]1168 -- Broxton Display Engine PLL registers
1169 BXT_DE_PLL_CTL => 16#06_d000# / Register_Width,
1170 BXT_DE_PLL_ENABLE => 16#04_6070# / Register_Width,
1171
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1172 -- Broxton DDI PHY PLL registers
1173 BXT_PORT_PLL_ENABLE_A => 16#04_6074# / Register_Width,
1174 BXT_PORT_PLL_ENABLE_B => 16#04_6078# / Register_Width,
1175 BXT_PORT_PLL_ENABLE_C => 16#04_607c# / Register_Width,
1176 BXT_PORT_PLL_EBB_0_A => 16#16_2034# / Register_Width,
1177 BXT_PORT_PLL_EBB_4_A => 16#16_2038# / Register_Width,
1178 BXT_PORT_PLL_0_A => 16#16_2100# / Register_Width,
1179 BXT_PORT_PLL_1_A => 16#16_2104# / Register_Width,
1180 BXT_PORT_PLL_2_A => 16#16_2108# / Register_Width,
1181 BXT_PORT_PLL_3_A => 16#16_210c# / Register_Width,
1182 BXT_PORT_PLL_6_A => 16#16_2118# / Register_Width,
1183 BXT_PORT_PLL_8_A => 16#16_2120# / Register_Width,
1184 BXT_PORT_PLL_9_A => 16#16_2124# / Register_Width,
1185 BXT_PORT_PLL_10_A => 16#16_2128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1186 BXT_PORT_PLL_EBB_0_B => 16#06_c034# / Register_Width,
1187 BXT_PORT_PLL_EBB_4_B => 16#06_c038# / Register_Width,
1188 BXT_PORT_PLL_0_B => 16#06_c100# / Register_Width,
1189 BXT_PORT_PLL_1_B => 16#06_c104# / Register_Width,
1190 BXT_PORT_PLL_2_B => 16#06_c108# / Register_Width,
1191 BXT_PORT_PLL_3_B => 16#06_c10c# / Register_Width,
1192 BXT_PORT_PLL_6_B => 16#06_c118# / Register_Width,
1193 BXT_PORT_PLL_8_B => 16#06_c120# / Register_Width,
1194 BXT_PORT_PLL_9_B => 16#06_c124# / Register_Width,
1195 BXT_PORT_PLL_10_B => 16#06_c128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1196 BXT_PORT_PLL_EBB_0_C => 16#06_c340# / Register_Width,
1197 BXT_PORT_PLL_EBB_4_C => 16#06_c344# / Register_Width,
1198 BXT_PORT_PLL_0_C => 16#06_c380# / Register_Width,
1199 BXT_PORT_PLL_1_C => 16#06_c384# / Register_Width,
1200 BXT_PORT_PLL_2_C => 16#06_c388# / Register_Width,
1201 BXT_PORT_PLL_3_C => 16#06_c38c# / Register_Width,
1202 BXT_PORT_PLL_6_C => 16#06_c398# / Register_Width,
1203 BXT_PORT_PLL_8_C => 16#06_c3a0# / Register_Width,
1204 BXT_PORT_PLL_9_C => 16#06_c3a4# / Register_Width,
1205 BXT_PORT_PLL_10_C => 16#06_c3a8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1206
1207 -- Broxton DDI PHY PCS? registers
1208 BXT_PORT_PCS_DW10_01_A => 16#16_2428# / Register_Width,
1209 BXT_PORT_PCS_DW12_01_A => 16#16_2430# / Register_Width,
1210 BXT_PORT_PCS_DW10_GRP_A => 16#16_2c28# / Register_Width,
1211 BXT_PORT_PCS_DW12_GRP_A => 16#16_2c30# / Register_Width,
1212 BXT_PORT_PCS_DW10_01_B => 16#06_c428# / Register_Width,
1213 BXT_PORT_PCS_DW12_01_B => 16#06_c430# / Register_Width,
1214 BXT_PORT_PCS_DW10_01_C => 16#06_c828# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1215 BXT_PORT_PCS_DW12_01_C => 16#06_c830# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1216 BXT_PORT_PCS_DW10_GRP_B => 16#06_cc28# / Register_Width,
1217 BXT_PORT_PCS_DW12_GRP_B => 16#06_cc30# / Register_Width,
1218 BXT_PORT_PCS_DW10_GRP_C => 16#06_ce28# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1219 BXT_PORT_PCS_DW12_GRP_C => 16#06_ce30# / Register_Width,
1220
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1221 -- Broxton DDI PHY registers
1222 BXT_P_CR_GT_DISP_PWRON => 16#13_8090# / Register_Width,
1223 BXT_PHY_CTL_A => 16#06_4c00# / Register_Width,
1224 BXT_PHY_CTL_B => 16#06_4c10# / Register_Width,
1225 BXT_PHY_CTL_C => 16#06_4c20# / Register_Width,
1226 BXT_PHY_CTL_FAM_EDP => 16#06_4c80# / Register_Width,
1227 BXT_PHY_CTL_FAM_DDI => 16#06_4c90# / Register_Width,
1228
1229 -- Broxton DDI PHY common lane registers
1230 BXT_PORT_CL1CM_DW0_A => 16#16_2000# / Register_Width,
1231 BXT_PORT_CL1CM_DW0_BC => 16#06_c000# / Register_Width,
1232 BXT_PORT_CL1CM_DW9_A => 16#16_2024# / Register_Width,
1233 BXT_PORT_CL1CM_DW9_BC => 16#06_c024# / Register_Width,
1234 BXT_PORT_CL1CM_DW10_A => 16#16_2028# / Register_Width,
1235 BXT_PORT_CL1CM_DW10_BC => 16#06_c028# / Register_Width,
1236 BXT_PORT_CL1CM_DW28_A => 16#16_2070# / Register_Width,
1237 BXT_PORT_CL1CM_DW28_BC => 16#06_c070# / Register_Width,
1238 BXT_PORT_CL1CM_DW30_A => 16#16_2078# / Register_Width,
1239 BXT_PORT_CL1CM_DW30_BC => 16#06_c078# / Register_Width,
1240 BXT_PORT_CL2CM_DW6_BC => 16#06_c358# / Register_Width,
1241
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1242 -- Broxton DDI PHY TX lane registers
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1243 BXT_PORT_TX_DW2_LN0_A => 16#16_2508# / Register_Width,
1244 BXT_PORT_TX_DW3_LN0_A => 16#16_250c# / Register_Width,
1245 BXT_PORT_TX_DW4_LN0_A => 16#16_2510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1246 BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width,
1247 BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width,
1248 BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width,
1249 BXT_PORT_TX_DW14_LN3_A => 16#16_27b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1250 BXT_PORT_TX_DW2_GRP_A => 16#16_2d08# / Register_Width,
1251 BXT_PORT_TX_DW3_GRP_A => 16#16_2d0c# / Register_Width,
1252 BXT_PORT_TX_DW4_GRP_A => 16#16_2d10# / Register_Width,
1253 BXT_PORT_TX_DW2_LN0_B => 16#06_c508# / Register_Width,
1254 BXT_PORT_TX_DW3_LN0_B => 16#06_c50c# / Register_Width,
1255 BXT_PORT_TX_DW4_LN0_B => 16#06_c510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1256 BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width,
1257 BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width,
1258 BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width,
1259 BXT_PORT_TX_DW14_LN3_B => 16#06_c7b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1260 BXT_PORT_TX_DW2_GRP_B => 16#06_cd08# / Register_Width,
1261 BXT_PORT_TX_DW3_GRP_B => 16#06_cd0c# / Register_Width,
1262 BXT_PORT_TX_DW4_GRP_B => 16#06_cd10# / Register_Width,
1263 BXT_PORT_TX_DW2_LN0_C => 16#06_c908# / Register_Width,
1264 BXT_PORT_TX_DW3_LN0_C => 16#06_c90c# / Register_Width,
1265 BXT_PORT_TX_DW4_LN0_C => 16#06_c910# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1266 BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width,
1267 BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width,
1268 BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width,
1269 BXT_PORT_TX_DW14_LN3_C => 16#06_cbb8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1270 BXT_PORT_TX_DW2_GRP_C => 16#06_cf08# / Register_Width,
1271 BXT_PORT_TX_DW3_GRP_C => 16#06_cf0c# / Register_Width,
1272 BXT_PORT_TX_DW4_GRP_C => 16#06_cf10# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1273
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1274 -- Broxton DDI PHY ref registers
1275 BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width,
1276 BXT_PORT_REF_DW3_BC => 16#06_c18c# / Register_Width,
1277 BXT_PORT_REF_DW6_A => 16#16_2198# / Register_Width,
1278 BXT_PORT_REF_DW6_BC => 16#06_c198# / Register_Width,
1279 BXT_PORT_REF_DW8_A => 16#16_21a0# / Register_Width,
1280 BXT_PORT_REF_DW8_BC => 16#06_c1a0# / Register_Width,
1281
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1282 -- Power Down Well registers
1283 PWR_WELL_CTL_BIOS => 16#04_5400# / Register_Width,
1284 PWR_WELL_CTL_DRIVER => 16#04_5404# / Register_Width,
1285 PWR_WELL_CTL_KVMR => 16#04_5408# / Register_Width,
1286 PWR_WELL_CTL_DEBUG => 16#04_540c# / Register_Width,
1287 PWR_WELL_CTL5 => 16#04_5410# / Register_Width,
1288 PWR_WELL_CTL6 => 16#04_5414# / Register_Width,
1289
1290 -- class Panel registers
Arthur Heymanse87d0d12018-03-28 17:02:49 +0200[diff] [blame]1291 GMCH_PP_STATUS => 16#06_1200# / Register_Width,
1292 GMCH_PP_CONTROL => 16#06_1204# / Register_Width,
1293 GMCH_PP_ON_DELAYS => 16#06_1208# / Register_Width,
1294 GMCH_PP_OFF_DELAYS => 16#06_120c# / Register_Width,
1295 GMCH_PP_DIVISOR => 16#06_1210# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1296 PCH_PP_STATUS => 16#0c_7200# / Register_Width,
1297 PCH_PP_CONTROL => 16#0c_7204# / Register_Width,
1298 PCH_PP_ON_DELAYS => 16#0c_7208# / Register_Width,
1299 PCH_PP_OFF_DELAYS => 16#0c_720c# / Register_Width,
1300 PCH_PP_DIVISOR => 16#0c_7210# / Register_Width,
1301 BLC_PWM_CPU_CTL => 16#04_8254# / Register_Width,
1302 BLC_PWM_PCH_CTL2 => 16#0c_8254# / Register_Width,
1303
1304 -- PCH LVDS Connector Registers
1305 PCH_LVDS => 16#0e_1180# / Register_Width,
1306
1307 -- PCH ADPA Connector Registers
1308 PCH_ADPA => 16#0e_1100# / Register_Width,
1309
1310 -- PCH HDMIB Connector Registers
1311 PCH_HDMIB => 16#0e_1140# / Register_Width,
1312
1313 -- PCH HDMIC Connector Registers
1314 PCH_HDMIC => 16#0e_1150# / Register_Width,
1315
1316 -- PCH HDMID Connector Registers
1317 PCH_HDMID => 16#0e_1160# / Register_Width,
1318
1319 -- Intel Registers
Arthur Heymansdfcdd772018-03-28 16:42:50 +0200[diff] [blame]1320 CPU_VGACNTRL => 16#04_1000# / Register_Width,
1321 GMCH_VGACNTRL => 16#07_1400# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1322 FUSE_STATUS => 16#04_2000# / Register_Width,
1323 FBA_CFB_BASE => 16#04_3200# / Register_Width,
1324 IPS_CTL => 16#04_3408# / Register_Width,
1325 ARB_CTL => 16#04_5000# / Register_Width,
1326 DBUF_CTL => 16#04_5008# / Register_Width,
1327 NDE_RSTWRN_OPT => 16#04_6408# / Register_Width,
1328 PCH_DREF_CONTROL => 16#0c_6200# / Register_Width,
1329 BLC_PWM_PCH_CTL1 => 16#0c_8250# / Register_Width,
1330 BLC_PWM_CPU_CTL2 => 16#04_8250# / Register_Width,
1331 PCH_DPLL_SEL => 16#0c_7000# / Register_Width,
1332 GT_MAILBOX => 16#13_8124# / Register_Width,
1333 GT_MAILBOX_DATA => 16#13_8128# / Register_Width,
1334 GT_MAILBOX_DATA_1 => 16#13_812c# / Register_Width,
1335
1336 PCH_DP_B => 16#0e_4100# / Register_Width,
1337 PCH_DP_AUX_CTL_B => 16#0e_4110# / Register_Width,
1338 PCH_DP_AUX_DATA_B_1 => 16#0e_4114# / Register_Width,
1339 PCH_DP_AUX_DATA_B_2 => 16#0e_4118# / Register_Width,
1340 PCH_DP_AUX_DATA_B_3 => 16#0e_411c# / Register_Width,
1341 PCH_DP_AUX_DATA_B_4 => 16#0e_4120# / Register_Width,
1342 PCH_DP_AUX_DATA_B_5 => 16#0e_4124# / Register_Width,
1343 PCH_DP_C => 16#0e_4200# / Register_Width,
1344 PCH_DP_AUX_CTL_C => 16#0e_4210# / Register_Width,
1345 PCH_DP_AUX_DATA_C_1 => 16#0e_4214# / Register_Width,
1346 PCH_DP_AUX_DATA_C_2 => 16#0e_4218# / Register_Width,
1347 PCH_DP_AUX_DATA_C_3 => 16#0e_421c# / Register_Width,
1348 PCH_DP_AUX_DATA_C_4 => 16#0e_4220# / Register_Width,
1349 PCH_DP_AUX_DATA_C_5 => 16#0e_4224# / Register_Width,
1350 PCH_DP_D => 16#0e_4300# / Register_Width,
1351 PCH_DP_AUX_CTL_D => 16#0e_4310# / Register_Width,
1352 PCH_DP_AUX_DATA_D_1 => 16#0e_4314# / Register_Width,
1353 PCH_DP_AUX_DATA_D_2 => 16#0e_4318# / Register_Width,
1354 PCH_DP_AUX_DATA_D_3 => 16#0e_431c# / Register_Width,
1355 PCH_DP_AUX_DATA_D_4 => 16#0e_4320# / Register_Width,
1356 PCH_DP_AUX_DATA_D_5 => 16#0e_4324# / Register_Width,
1357
1358 -- watermark registers
1359 WM1_LP_ILK => 16#04_5108# / Register_Width,
1360 WM2_LP_ILK => 16#04_510c# / Register_Width,
1361 WM3_LP_ILK => 16#04_5110# / Register_Width,
1362
1363 -- audio VID/DID
1364 AUD_VID_DID => 16#06_5020# / Register_Width,
1365 PCH_AUD_VID_DID => 16#0e_5020# / Register_Width,
1366
1367 -- interrupt registers
1368 DEISR => 16#04_4000# / Register_Width,
1369 DEIMR => 16#04_4004# / Register_Width,
1370 DEIIR => 16#04_4008# / Register_Width,
1371 DEIER => 16#04_400c# / Register_Width,
1372 GTISR => 16#04_4010# / Register_Width,
1373 GTIMR => 16#04_4014# / Register_Width,
1374 GTIIR => 16#04_4018# / Register_Width,
1375 GTIER => 16#04_401c# / Register_Width,
1376 SDEISR => 16#0c_4000# / Register_Width,
1377 SDEIMR => 16#0c_4004# / Register_Width,
1378 SDEIIR => 16#0c_4008# / Register_Width,
1379 SDEIER => 16#0c_400c# / Register_Width,
1380
1381 -- I2C stuff
Arthur Heymans229ed1c2018-03-28 16:45:43 +0200[diff] [blame]1382 GMCH_GMBUS0 => 16#00_5100# / Register_Width,
1383 GMCH_GMBUS1 => 16#00_5104# / Register_Width,
1384 GMCH_GMBUS2 => 16#00_5108# / Register_Width,
1385 GMCH_GMBUS3 => 16#00_510c# / Register_Width,
1386 GMCH_GMBUS4 => 16#00_5110# / Register_Width,
1387 GMCH_GMBUS5 => 16#00_5120# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1388 PCH_GMBUS0 => 16#0c_5100# / Register_Width,
1389 PCH_GMBUS1 => 16#0c_5104# / Register_Width,
1390 PCH_GMBUS2 => 16#0c_5108# / Register_Width,
1391 PCH_GMBUS3 => 16#0c_510c# / Register_Width,
1392 PCH_GMBUS4 => 16#0c_5110# / Register_Width,
1393 PCH_GMBUS5 => 16#0c_5120# / Register_Width,
1394
1395 -- clock gating -- maybe have to touch this
1396 DSPCLK_GATE_D => 16#04_2020# / Register_Width,
1397 PCH_FDI_CHICKEN_B_C => 16#0c_2000# / Register_Width,
1398 PCH_DSPCLK_GATE_D => 16#0c_2020# / Register_Width,
1399
1400 -- hotplug and initial detection
1401 HOTPLUG_CTL => 16#04_4030# / Register_Width,
1402 SHOTPLUG_CTL => 16#0c_4030# / Register_Width,
1403 SFUSE_STRAP => 16#0c_2014# / Register_Width,
1404
1405 -- Render Engine Command Streamer
1406 ARB_MODE => 16#00_4030# / Register_Width,
1407 HWS_PGA => 16#00_4080# / Register_Width,
1408 RCS_RING_BUFFER_TAIL => 16#00_2030# / Register_Width,
1409 VCS_RING_BUFFER_TAIL => 16#01_2030# / Register_Width,
1410 BCS_RING_BUFFER_TAIL => 16#02_2030# / Register_Width,
1411 RCS_RING_BUFFER_HEAD => 16#00_2034# / Register_Width,
1412 VCS_RING_BUFFER_HEAD => 16#01_2034# / Register_Width,
1413 BCS_RING_BUFFER_HEAD => 16#02_2034# / Register_Width,
1414 RCS_RING_BUFFER_STRT => 16#00_2038# / Register_Width,
1415 VCS_RING_BUFFER_STRT => 16#01_2038# / Register_Width,
1416 BCS_RING_BUFFER_STRT => 16#02_2038# / Register_Width,
1417 RCS_RING_BUFFER_CTL => 16#00_203c# / Register_Width,
1418 VCS_RING_BUFFER_CTL => 16#01_203c# / Register_Width,
1419 BCS_RING_BUFFER_CTL => 16#02_203c# / Register_Width,
1420 MI_MODE => 16#00_209c# / Register_Width,
1421 INSTPM => 16#00_20c0# / Register_Width,
1422 GAB_CTL_REG => 16#02_4000# / Register_Width,
1423 PP_DCLV_HIGH => 16#00_2220# / Register_Width,
1424 PP_DCLV_LOW => 16#00_2228# / Register_Width,
1425 VCS_PP_DCLV_HIGH => 16#01_2220# / Register_Width,
1426 VCS_PP_DCLV_LOW => 16#01_2228# / Register_Width,
1427 BCS_PP_DCLV_HIGH => 16#02_2220# / Register_Width,
1428 BCS_PP_DCLV_LOW => 16#02_2228# / Register_Width,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1429 ILK_DISPLAY_CHICKEN2 => 16#04_2004# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1430 UCGCTL1 => 16#00_9400# / Register_Width,
1431 UCGCTL2 => 16#00_9404# / Register_Width,
1432 MBCTL => 16#00_907c# / Register_Width,
1433 HWSTAM => 16#00_2098# / Register_Width,
1434 VCS_HWSTAM => 16#01_2098# / Register_Width,
1435 BCS_HWSTAM => 16#02_2098# / Register_Width,
1436 IIR => 16#04_4028# / Register_Width,
1437 PIPE_FRMCNT_A => 16#07_0040# / Register_Width,
1438 PIPE_FRMCNT_B => 16#07_1040# / Register_Width,
1439 PIPE_FRMCNT_C => 16#07_2040# / Register_Width,
1440 FBC_CTL => 16#04_3208# / Register_Width,
1441 PIPE_VSYNCSHIFT_A => 16#06_0028# / Register_Width,
1442 PIPE_VSYNCSHIFT_B => 16#06_1028# / Register_Width,
1443 PIPE_VSYNCSHIFT_C => 16#06_2028# / Register_Width,
1444 WM_PIPE_A => 16#04_5100# / Register_Width,
1445 WM_PIPE_B => 16#04_5104# / Register_Width,
1446 WM_PIPE_C => 16#04_5200# / Register_Width,
1447 PIPE_SCANLINE_A => 16#07_0000# / Register_Width,
1448 PIPE_SCANLINE_B => 16#07_1000# / Register_Width,
1449 PIPE_SCANLINE_C => 16#07_2000# / Register_Width,
1450 GFX_MODE => 16#00_2520# / Register_Width,
1451 CACHE_MODE_0 => 16#00_2120# / Register_Width,
1452 SLEEP_PSMI_CONTROL => 16#01_2050# / Register_Width,
1453 CTX_SIZE => 16#00_21a0# / Register_Width,
1454 GAC_ECO_BITS => 16#01_4090# / Register_Width,
1455 GAM_ECOCHK => 16#00_4090# / Register_Width,
1456 QUIRK_02084 => 16#00_2084# / Register_Width,
1457 QUIRK_02090 => 16#00_2090# / Register_Width,
1458 GT_MODE => 16#00_20d0# / Register_Width,
1459 QUIRK_F0060 => 16#0f_0060# / Register_Width,
1460 QUIRK_F1060 => 16#0f_1060# / Register_Width,
1461 QUIRK_F2060 => 16#0f_2060# / Register_Width,
1462 AUD_CNTRL_ST2 => 16#0e_50c0# / Register_Width,
1463 AUD_CNTL_ST_A => 16#0e_50b4# / Register_Width,
1464 AUD_CNTL_ST_B => 16#0e_51b4# / Register_Width,
1465 AUD_CNTL_ST_C => 16#0e_52b4# / Register_Width,
1466 AUD_HDMIW_HDMIEDID_A => 16#0e_5050# / Register_Width,
1467 AUD_HDMIW_HDMIEDID_B => 16#0e_5150# / Register_Width,
1468 AUD_HDMIW_HDMIEDID_C => 16#0e_5250# / Register_Width,
1469 AUD_CONFIG_A => 16#0e_5000# / Register_Width,
1470 AUD_CONFIG_B => 16#0e_5100# / Register_Width,
1471 AUD_CONFIG_C => 16#0e_5200# / Register_Width,
1472 TRANS_DP_CTL_A => 16#0e_0300# / Register_Width,
1473 TRANS_DP_CTL_B => 16#0e_1300# / Register_Width,
1474 TRANS_DP_CTL_C => 16#0e_2300# / Register_Width,
1475 TRANS_VSYNCSHIFT_A => 16#0e_0028# / Register_Width,
1476 TRANS_VSYNCSHIFT_B => 16#0e_1028# / Register_Width,
1477 TRANS_VSYNCSHIFT_C => 16#0e_2028# / Register_Width,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]1478 PCH_RAWCLK_FREQ => 16#0c_6204# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1479 QUIRK_C2004 => 16#0c_2004# / Register_Width);
1480
1481 subtype Registers_Index is Registers_Invalid_Index range
1482 Registers_Invalid_Index'Succ (Invalid_Register) ..
1483 Registers_Invalid_Index'Last;
1484
1485 -- aliased registers
1486 DP_CTL_A : constant Registers_Index := DDI_BUF_CTL_A;
1487 DP_AUX_CTL_A : constant Registers_Index := DDI_AUX_CTL_A;
1488 DP_AUX_DATA_A_1 : constant Registers_Index := DDI_AUX_DATA_A_1;
1489 DP_AUX_DATA_A_2 : constant Registers_Index := DDI_AUX_DATA_A_2;
1490 DP_AUX_DATA_A_3 : constant Registers_Index := DDI_AUX_DATA_A_3;
1491 DP_AUX_DATA_A_4 : constant Registers_Index := DDI_AUX_DATA_A_4;
1492 DP_AUX_DATA_A_5 : constant Registers_Index := DDI_AUX_DATA_A_5;
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1493 ILK_DISPLAY_CHICKEN1 : constant Registers_Index := FUSE_STATUS;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1494
1495 ---------------------------------------------------------------------------
1496
1497 Default_Timeout_MS : constant := 10;
1498
1499 ---------------------------------------------------------------------------
1500
1501 procedure Posting_Read
1502 (Register : in Registers_Index)
1503 with
1504 Global => (In_Out => Register_State),
1505 Depends => (Register_State =>+ (Register)),
1506 Pre => True,
1507 Post => True;
1508
1509 pragma Warnings (GNATprove, Off, "unused variable ""Verbose""",
1510 Reason => "Only used on debugging path");
1511 procedure Read
1512 (Register : in Registers_Index;
1513 Value : out Word32;
1514 Verbose : in Boolean := True)
1515 with
1516 Global => (In_Out => Register_State),
1517 Depends => ((Value, Register_State) => (Register, Register_State),
1518 null => Verbose),
1519 Pre => True,
1520 Post => True;
1521 pragma Warnings (GNATprove, On, "unused variable ""Verbose""");
1522
1523 procedure Write
1524 (Register : Registers_Index;
1525 Value : Word32)
1526 with
1527 Global => (In_Out => Register_State),
1528 Depends => (Register_State => (Register, Register_State, Value)),
1529 Pre => True,
1530 Post => True;
1531
1532 procedure Is_Set_Mask
1533 (Register : in Registers_Index;
1534 Mask : in Word32;
1535 Result : out Boolean);
1536
1537 pragma Warnings (GNATprove, Off, "unused initial value of ""Verbose""",
1538 Reason => "Only used on debugging path");
Nico Huberbcb2c472017-02-02 16:39:26 +0100[diff] [blame]1539 procedure Wait
1540 (Register : Registers_Index;
1541 Mask : Word32;
1542 Value : Word32;
1543 TOut_MS : Natural := Default_Timeout_MS;
1544 Verbose : Boolean := False);
1545
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1546 procedure Wait_Set_Mask
1547 (Register : Registers_Index;
1548 Mask : Word32;
1549 TOut_MS : Natural := Default_Timeout_MS;
1550 Verbose : Boolean := False);
1551
1552 procedure Wait_Unset_Mask
1553 (Register : Registers_Index;
1554 Mask : Word32;
1555 TOut_MS : Natural := Default_Timeout_MS;
1556 Verbose : Boolean := False);
1557 pragma Warnings (GNATprove, On, "unused initial value of ""Verbose""");
1558
1559 procedure Set_Mask
1560 (Register : Registers_Index;
1561 Mask : Word32);
1562
1563 procedure Unset_Mask
1564 (Register : Registers_Index;
1565 Mask : Word32);
1566
1567 procedure Unset_And_Set_Mask
1568 (Register : Registers_Index;
1569 Mask_Unset : Word32;
1570 Mask_Set : Word32);
1571
Nico Huber17d64b62017-07-15 20:51:25 +0200[diff] [blame]1572 procedure Clear_Fences;
1573
Nico Huberb03c8f12017-08-25 13:29:08 +0200[diff] [blame]1574 procedure Add_Fence
1575 (First_Page : in GTT_Range;
1576 Last_Page : in GTT_Range;
1577 Tiling : in XY_Tiling;
1578 Pitch : in Natural;
1579 Success : out Boolean);
1580
1581 procedure Remove_Fence (First_Page, Last_Page : GTT_Range);
1582
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1583 pragma Warnings (Off, "declaration of ""Write_GTT"" hides one at *");
1584 procedure Write_GTT
1585 (GTT_Page : GTT_Range;
1586 Device_Address : GTT_Address_Type;
1587 Valid : Boolean)
1588 with
1589 Global => (In_Out => GTT_State),
1590 Depends => (GTT_State =>+ (GTT_Page, Device_Address, Valid)),
1591 Pre => True,
1592 Post => True;
1593 pragma Warnings (On, "declaration of ""Write_GTT"" hides one at *");
1594
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]1595 procedure Set_Register_Base (Base : Word64; GTT_Base : Word64 := 0)
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1596 with
1597 Global => (Output => Address_State),
Nico Huber2b6f6992017-07-09 18:11:34 +0200[diff] [blame]1598 Depends => (Address_State => (Base, GTT_Base)),
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1599 Pre => True,
1600 Post => True;
1601
1602end HW.GFX.GMA.Registers;