blob: 403d7632b6b2a9eddc0793b8fe27735d40d97e14 [file] [log] [blame]
Dominik Geyerb46acba2008-05-16 12:55:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
5 * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
6 * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
Stefan Reinauera9424d52008-06-27 16:28:34 +00007 * Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00008 * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
Stefan Tauner8b391b82011-08-09 01:49:34 +00009 * Copyright (C) 2011 Stefan Tauner
Dominik Geyerb46acba2008-05-16 12:55:55 +000010 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Dominik Geyerb46acba2008-05-16 12:55:55 +000024 */
25
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000026#if defined(__i386__) || defined(__x86_64__)
27
Dominik Geyerb46acba2008-05-16 12:55:55 +000028#include <string.h>
Stefan Taunerd0c5dc22011-10-20 12:57:14 +000029#include <stdlib.h>
Dominik Geyerb46acba2008-05-16 12:55:55 +000030#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000031#include "programmer.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000032#include "spi.h"
Stefan Tauner1e146392011-09-15 23:52:55 +000033#include "ich_descriptors.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000034
Stefan Reinauera9424d52008-06-27 16:28:34 +000035/* ICH9 controller register definition */
Stefan Tauner55206942011-06-11 09:53:22 +000036#define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */
37#define HSFS_FDONE_OFF 0 /* 0: Flash Cycle Done */
38#define HSFS_FDONE (0x1 << HSFS_FDONE_OFF)
39#define HSFS_FCERR_OFF 1 /* 1: Flash Cycle Error */
40#define HSFS_FCERR (0x1 << HSFS_FCERR_OFF)
41#define HSFS_AEL_OFF 2 /* 2: Access Error Log */
42#define HSFS_AEL (0x1 << HSFS_AEL_OFF)
43#define HSFS_BERASE_OFF 3 /* 3-4: Block/Sector Erase Size */
44#define HSFS_BERASE (0x3 << HSFS_BERASE_OFF)
45#define HSFS_SCIP_OFF 5 /* 5: SPI Cycle In Progress */
46#define HSFS_SCIP (0x1 << HSFS_SCIP_OFF)
47 /* 6-12: reserved */
48#define HSFS_FDOPSS_OFF 13 /* 13: Flash Descriptor Override Pin-Strap Status */
49#define HSFS_FDOPSS (0x1 << HSFS_FDOPSS_OFF)
50#define HSFS_FDV_OFF 14 /* 14: Flash Descriptor Valid */
51#define HSFS_FDV (0x1 << HSFS_FDV_OFF)
52#define HSFS_FLOCKDN_OFF 15 /* 15: Flash Configuration Lock-Down */
53#define HSFS_FLOCKDN (0x1 << HSFS_FLOCKDN_OFF)
54
55#define ICH9_REG_HSFC 0x06 /* 16 Bits Hardware Sequencing Flash Control */
56#define HSFC_FGO_OFF 0 /* 0: Flash Cycle Go */
57#define HSFC_FGO (0x1 << HSFC_FGO_OFF)
58#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
59#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
60 /* 3-7: reserved */
61#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
62#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
63 /* 14: reserved */
64#define HSFC_SME_OFF 15 /* 15: SPI SMI# Enable */
65#define HSFC_SME (0x1 << HSFC_SME_OFF)
66
Stefan Taunerc0aaf952011-05-19 02:58:17 +000067#define ICH9_REG_FADDR 0x08 /* 32 Bits */
68#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
Stefan Reinauera9424d52008-06-27 16:28:34 +000069
Stefan Tauner29c80832011-06-12 08:14:10 +000070#define ICH9_REG_FRAP 0x50 /* 32 Bytes Flash Region Access Permissions */
71#define ICH9_REG_FREG0 0x54 /* 32 Bytes Flash Region 0 */
72
73#define ICH9_REG_PR0 0x74 /* 32 Bytes Protected Range 0 */
Stefan Taunerbf69aaa2011-09-17 21:21:48 +000074#define PR_WP_OFF 31 /* 31: write protection enable */
75#define PR_RP_OFF 15 /* 15: read protection enable */
Stefan Tauner29c80832011-06-12 08:14:10 +000076
Stefan Taunerc0aaf952011-05-19 02:58:17 +000077#define ICH9_REG_SSFS 0x90 /* 08 Bits */
Stefan Tauner0c1ec452011-06-11 09:53:09 +000078#define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */
79#define SSFS_SCIP (0x1 << SSFS_SCIP_OFF)
80#define SSFS_FDONE_OFF 2 /* Cycle Done Status */
81#define SSFS_FDONE (0x1 << SSFS_FDONE_OFF)
82#define SSFS_FCERR_OFF 3 /* Flash Cycle Error */
83#define SSFS_FCERR (0x1 << SSFS_FCERR_OFF)
84#define SSFS_AEL_OFF 4 /* Access Error Log */
85#define SSFS_AEL (0x1 << SSFS_AEL_OFF)
Stefan Taunerc0aaf952011-05-19 02:58:17 +000086/* The following bits are reserved in SSFS: 1,5-7. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +000087#define SSFS_RESERVED_MASK 0x000000e2
Stefan Reinauera9424d52008-06-27 16:28:34 +000088
Stefan Taunerc0aaf952011-05-19 02:58:17 +000089#define ICH9_REG_SSFC 0x91 /* 24 Bits */
Stefan Taunerc0aaf952011-05-19 02:58:17 +000090/* We combine SSFS and SSFC to one 32-bit word,
Stefan Tauner0c1ec452011-06-11 09:53:09 +000091 * therefore SSFC bits are off by 8. */
92 /* 0: reserved */
93#define SSFC_SCGO_OFF (1 + 8) /* 1: SPI Cycle Go */
94#define SSFC_SCGO (0x1 << SSFC_SCGO_OFF)
95#define SSFC_ACS_OFF (2 + 8) /* 2: Atomic Cycle Sequence */
96#define SSFC_ACS (0x1 << SSFC_ACS_OFF)
97#define SSFC_SPOP_OFF (3 + 8) /* 3: Sequence Prefix Opcode Pointer */
98#define SSFC_SPOP (0x1 << SSFC_SPOP_OFF)
99#define SSFC_COP_OFF (4 + 8) /* 4-6: Cycle Opcode Pointer */
100#define SSFC_COP (0x7 << SSFC_COP_OFF)
101 /* 7: reserved */
102#define SSFC_DBC_OFF (8 + 8) /* 8-13: Data Byte Count */
103#define SSFC_DBC (0x3f << SSFC_DBC_OFF)
104#define SSFC_DS_OFF (14 + 8) /* 14: Data Cycle */
105#define SSFC_DS (0x1 << SSFC_DS_OFF)
106#define SSFC_SME_OFF (15 + 8) /* 15: SPI SMI# Enable */
107#define SSFC_SME (0x1 << SSFC_SME_OFF)
108#define SSFC_SCF_OFF (16 + 8) /* 16-18: SPI Cycle Frequency */
109#define SSFC_SCF (0x7 << SSFC_SCF_OFF)
110#define SSFC_SCF_20MHZ 0x00000000
111#define SSFC_SCF_33MHZ 0x01000000
112 /* 19-23: reserved */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000113#define SSFC_RESERVED_MASK 0xf8008100
Stefan Reinauera9424d52008-06-27 16:28:34 +0000114
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000115#define ICH9_REG_PREOP 0x94 /* 16 Bits */
116#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
117#define ICH9_REG_OPMENU 0x98 /* 64 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000118
Stefan Tauner29c80832011-06-12 08:14:10 +0000119#define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */
120#define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */
121
Stefan Tauner1e146392011-09-15 23:52:55 +0000122#define ICH8_REG_VSCC 0xC1 /* 32 Bits Vendor Specific Component Capabilities */
123#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */
124#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */
125/* The individual fields of the VSCC registers are defined in the file
126 * ich_descriptors.h. The reason is that the same layout is also used in the
127 * flash descriptor to define the properties of the different flash chips
128 * supported. The BIOS (or the ME?) is responsible to populate the ICH registers
129 * with the information from the descriptor on startup depending on the actual
130 * chip(s) detected. */
131
Stefan Taunerbd649e42011-07-01 00:39:16 +0000132#define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */
133#define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */
134#define FPB_FPBA (0x1FFF << FPB_FPBA_OFF)
135
Dominik Geyerb46acba2008-05-16 12:55:55 +0000136// ICH9R SPI commands
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000137#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
138#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
139#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
140#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
Dominik Geyerb46acba2008-05-16 12:55:55 +0000141
Stefan Reinauera9424d52008-06-27 16:28:34 +0000142// ICH7 registers
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000143#define ICH7_REG_SPIS 0x00 /* 16 Bits */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000144#define SPIS_SCIP 0x0001
145#define SPIS_GRANT 0x0002
146#define SPIS_CDS 0x0004
147#define SPIS_FCERR 0x0008
148#define SPIS_RESERVED_MASK 0x7ff0
Stefan Reinauera9424d52008-06-27 16:28:34 +0000149
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000150/* VIA SPI is compatible with ICH7, but maxdata
151 to transfer is 16 bytes.
152
153 DATA byte count on ICH7 is 8:13, on VIA 8:11
154
155 bit 12 is port select CS0 CS1
156 bit 13 is FAST READ enable
157 bit 7 is used with fast read and one shot controls CS de-assert?
158*/
159
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000160#define ICH7_REG_SPIC 0x02 /* 16 Bits */
161#define SPIC_SCGO 0x0002
162#define SPIC_ACS 0x0004
163#define SPIC_SPOP 0x0008
164#define SPIC_DS 0x4000
Stefan Reinauera9424d52008-06-27 16:28:34 +0000165
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000166#define ICH7_REG_SPIA 0x04 /* 32 Bits */
167#define ICH7_REG_SPID0 0x08 /* 64 Bytes */
168#define ICH7_REG_PREOP 0x54 /* 16 Bits */
169#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
170#define ICH7_REG_OPMENU 0x58 /* 64 Bits */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000171
FENG yu ningc05a2952008-12-08 18:16:58 +0000172/* ICH SPI configuration lock-down. May be set during chipset enabling. */
Michael Karchera4448d92010-07-22 18:04:15 +0000173static int ichspi_lock = 0;
FENG yu ningc05a2952008-12-08 18:16:58 +0000174
Stefan Taunera8d838d2011-11-06 23:51:09 +0000175static enum ich_chipset ich_generation = CHIPSET_ICH_UNKNOWN;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000176uint32_t ichspi_bbar = 0;
177
Michael Karchera4448d92010-07-22 18:04:15 +0000178static void *ich_spibar = NULL;
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000179
Dominik Geyerb46acba2008-05-16 12:55:55 +0000180typedef struct _OPCODE {
181 uint8_t opcode; //This commands spi opcode
182 uint8_t spi_type; //This commands spi type
183 uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1
184} OPCODE;
185
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000186/* Suggested opcode definition:
Dominik Geyerb46acba2008-05-16 12:55:55 +0000187 * Preop 1: Write Enable
188 * Preop 2: Write Status register enable
189 *
190 * OP 0: Write address
191 * OP 1: Read Address
192 * OP 2: ERASE block
193 * OP 3: Read Status register
194 * OP 4: Read ID
195 * OP 5: Write Status register
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000196 * OP 6: chip private (read JEDEC id)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000197 * OP 7: Chip erase
198 */
199typedef struct _OPCODES {
200 uint8_t preop[2];
201 OPCODE opcode[8];
202} OPCODES;
203
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000204static OPCODES *curopcodes = NULL;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000205
206/* HW access functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000207static uint32_t REGREAD32(int X)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000208{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000209 return mmio_readl(ich_spibar + X);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000210}
211
Uwe Hermann09e04f72009-05-16 22:36:00 +0000212static uint16_t REGREAD16(int X)
Stefan Reinauera9424d52008-06-27 16:28:34 +0000213{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000214 return mmio_readw(ich_spibar + X);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000215}
216
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000217static uint16_t REGREAD8(int X)
218{
219 return mmio_readb(ich_spibar + X);
220}
221
Stefan Taunerccd92a12011-07-01 00:39:01 +0000222#define REGWRITE32(off, val) mmio_writel(val, ich_spibar+(off))
223#define REGWRITE16(off, val) mmio_writew(val, ich_spibar+(off))
224#define REGWRITE8(off, val) mmio_writeb(val, ich_spibar+(off))
Dominik Geyerb46acba2008-05-16 12:55:55 +0000225
Dominik Geyerb46acba2008-05-16 12:55:55 +0000226/* Common SPI functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000227static int find_opcode(OPCODES *op, uint8_t opcode);
228static int find_preop(OPCODES *op, uint8_t preop);
FENG yu ningf041e9b2008-12-15 02:32:11 +0000229static int generate_opcodes(OPCODES * op);
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000230static int program_opcodes(OPCODES *op, int enable_undo);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000231static int run_opcode(const struct flashctx *flash, OPCODE op, uint32_t offset,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000232 uint8_t datalength, uint8_t * data);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000233
FENG yu ningf041e9b2008-12-15 02:32:11 +0000234/* for pairing opcodes with their required preop */
235struct preop_opcode_pair {
236 uint8_t preop;
237 uint8_t opcode;
238};
239
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000240/* List of opcodes which need preopcodes and matching preopcodes. Unused. */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000241const struct preop_opcode_pair pops[] = {
FENG yu ningf041e9b2008-12-15 02:32:11 +0000242 {JEDEC_WREN, JEDEC_BYTE_PROGRAM},
243 {JEDEC_WREN, JEDEC_SE}, /* sector erase */
244 {JEDEC_WREN, JEDEC_BE_52}, /* block erase */
245 {JEDEC_WREN, JEDEC_BE_D8}, /* block erase */
246 {JEDEC_WREN, JEDEC_CE_60}, /* chip erase */
247 {JEDEC_WREN, JEDEC_CE_C7}, /* chip erase */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000248 /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */
249 {JEDEC_WREN, JEDEC_WRSR},
FENG yu ningf041e9b2008-12-15 02:32:11 +0000250 {JEDEC_EWSR, JEDEC_WRSR},
251 {0,}
252};
253
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000254/* Reasonable default configuration. Needs ad-hoc modifications if we
255 * encounter unlisted opcodes. Fun.
256 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000257static OPCODES O_ST_M25P = {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000258 {
259 JEDEC_WREN,
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000260 JEDEC_EWSR,
261 },
Dominik Geyerb46acba2008-05-16 12:55:55 +0000262 {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000263 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000264 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000265 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000266 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
Carl-Daniel Hailfinger15aa7c62009-05-26 21:25:08 +0000267 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000268 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000269 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000270 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
271 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000272};
273
Helge Wagner738e2522010-10-05 22:06:05 +0000274/* List of opcodes with their corresponding spi_type
275 * It is used to reprogram the chipset OPCODE table on-the-fly if an opcode
276 * is needed which is currently not in the chipset OPCODE table
277 */
278static OPCODE POSSIBLE_OPCODES[] = {
279 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
280 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
281 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
282 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
283 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
284 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
285 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
286 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
287 {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Sector erase
288 {JEDEC_BE_52, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Block erase
289 {JEDEC_AAI_WORD_PROGRAM, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Auto Address Increment
290};
291
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000292static OPCODES O_EXISTING = {};
FENG yu ningc05a2952008-12-08 18:16:58 +0000293
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000294/* pretty printing functions */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000295static void prettyprint_opcodes(OPCODES *ops)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000296{
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000297 OPCODE oc;
298 const char *t;
299 const char *a;
300 uint8_t i;
301 static const char *const spi_type[4] = {
302 "read w/o addr",
303 "write w/o addr",
304 "read w/ addr",
305 "write w/ addr"
306 };
307 static const char *const atomic_type[3] = {
308 "none",
309 " 0 ",
310 " 1 "
311 };
312
313 if (ops == NULL)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000314 return;
315
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000316 msg_pdbg2(" OP Type Pre-OP\n");
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000317 for (i = 0; i < 8; i++) {
318 oc = ops->opcode[i];
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000319 t = (oc.spi_type > 3) ? "invalid" : spi_type[oc.spi_type];
320 a = (oc.atomic > 2) ? "invalid" : atomic_type[oc.atomic];
321 msg_pdbg2("op[%d]: 0x%02x, %s, %s\n", i, oc.opcode, t, a);
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000322 }
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000323 msg_pdbg2("Pre-OP 0: 0x%02x, Pre-OP 1: 0x%02x\n", ops->preop[0],
324 ops->preop[1]);
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000325}
326
327#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF)
328
Stefan Tauner55206942011-06-11 09:53:22 +0000329static void prettyprint_ich9_reg_hsfs(uint16_t reg_val)
330{
331 msg_pdbg("HSFS: ");
332 pprint_reg(HSFS, FDONE, reg_val, ", ");
333 pprint_reg(HSFS, FCERR, reg_val, ", ");
334 pprint_reg(HSFS, AEL, reg_val, ", ");
335 pprint_reg(HSFS, BERASE, reg_val, ", ");
336 pprint_reg(HSFS, SCIP, reg_val, ", ");
337 pprint_reg(HSFS, FDOPSS, reg_val, ", ");
338 pprint_reg(HSFS, FDV, reg_val, ", ");
339 pprint_reg(HSFS, FLOCKDN, reg_val, "\n");
340}
341
342static void prettyprint_ich9_reg_hsfc(uint16_t reg_val)
343{
344 msg_pdbg("HSFC: ");
345 pprint_reg(HSFC, FGO, reg_val, ", ");
346 pprint_reg(HSFC, FCYCLE, reg_val, ", ");
347 pprint_reg(HSFC, FDBC, reg_val, ", ");
348 pprint_reg(HSFC, SME, reg_val, "\n");
349}
350
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000351static void prettyprint_ich9_reg_ssfs(uint32_t reg_val)
352{
353 msg_pdbg("SSFS: ");
354 pprint_reg(SSFS, SCIP, reg_val, ", ");
355 pprint_reg(SSFS, FDONE, reg_val, ", ");
356 pprint_reg(SSFS, FCERR, reg_val, ", ");
357 pprint_reg(SSFS, AEL, reg_val, "\n");
358}
359
360static void prettyprint_ich9_reg_ssfc(uint32_t reg_val)
361{
362 msg_pdbg("SSFC: ");
363 pprint_reg(SSFC, SCGO, reg_val, ", ");
364 pprint_reg(SSFC, ACS, reg_val, ", ");
365 pprint_reg(SSFC, SPOP, reg_val, ", ");
366 pprint_reg(SSFC, COP, reg_val, ", ");
367 pprint_reg(SSFC, DBC, reg_val, ", ");
368 pprint_reg(SSFC, SME, reg_val, ", ");
369 pprint_reg(SSFC, SCF, reg_val, "\n");
370}
371
Helge Wagner738e2522010-10-05 22:06:05 +0000372static uint8_t lookup_spi_type(uint8_t opcode)
373{
374 int a;
375
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000376 for (a = 0; a < ARRAY_SIZE(POSSIBLE_OPCODES); a++) {
Helge Wagner738e2522010-10-05 22:06:05 +0000377 if (POSSIBLE_OPCODES[a].opcode == opcode)
378 return POSSIBLE_OPCODES[a].spi_type;
379 }
380
381 return 0xFF;
382}
383
384static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt)
385{
386 uint8_t spi_type;
387
388 spi_type = lookup_spi_type(opcode);
389 if (spi_type > 3) {
390 /* Try to guess spi type from read/write sizes.
391 * The following valid writecnt/readcnt combinations exist:
392 * writecnt = 4, readcnt >= 0
393 * writecnt = 1, readcnt >= 0
394 * writecnt >= 4, readcnt = 0
395 * writecnt >= 1, readcnt = 0
396 * writecnt >= 1 is guaranteed for all commands.
397 */
398 if (readcnt == 0)
399 /* if readcnt=0 and writecount >= 4, we don't know if it is WRITE_NO_ADDRESS
400 * or WRITE_WITH_ADDRESS. But if we use WRITE_NO_ADDRESS and the first 3 data
401 * bytes are actual the address, they go to the bus anyhow
402 */
403 spi_type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
404 else if (writecnt == 1) // and readcnt is > 0
405 spi_type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
406 else if (writecnt == 4) // and readcnt is > 0
407 spi_type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
408 // else we have an invalid case, will be handled below
409 }
410 if (spi_type <= 3) {
411 int oppos=2; // use original JEDEC_BE_D8 offset
412 curopcodes->opcode[oppos].opcode = opcode;
413 curopcodes->opcode[oppos].spi_type = spi_type;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000414 program_opcodes(curopcodes, 0);
Helge Wagner738e2522010-10-05 22:06:05 +0000415 oppos = find_opcode(curopcodes, opcode);
416 msg_pdbg ("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos);
417 return oppos;
418 }
419 return -1;
420}
421
Uwe Hermann09e04f72009-05-16 22:36:00 +0000422static int find_opcode(OPCODES *op, uint8_t opcode)
FENG yu ningc05a2952008-12-08 18:16:58 +0000423{
424 int a;
425
Stefan Tauner50e7c602011-11-08 10:55:54 +0000426 if (op == NULL) {
427 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
428 return -1;
429 }
430
FENG yu ningc05a2952008-12-08 18:16:58 +0000431 for (a = 0; a < 8; a++) {
432 if (op->opcode[a].opcode == opcode)
433 return a;
434 }
435
436 return -1;
437}
438
Uwe Hermann09e04f72009-05-16 22:36:00 +0000439static int find_preop(OPCODES *op, uint8_t preop)
FENG yu ningc05a2952008-12-08 18:16:58 +0000440{
441 int a;
442
Stefan Tauner50e7c602011-11-08 10:55:54 +0000443 if (op == NULL) {
444 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
445 return -1;
446 }
447
FENG yu ningc05a2952008-12-08 18:16:58 +0000448 for (a = 0; a < 2; a++) {
449 if (op->preop[a] == preop)
450 return a;
451 }
452
453 return -1;
454}
455
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000456/* Create a struct OPCODES based on what we find in the locked down chipset. */
FENG yu ningf041e9b2008-12-15 02:32:11 +0000457static int generate_opcodes(OPCODES * op)
FENG yu ningc05a2952008-12-08 18:16:58 +0000458{
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000459 int a;
FENG yu ningc05a2952008-12-08 18:16:58 +0000460 uint16_t preop, optype;
461 uint32_t opmenu[2];
FENG yu ningc05a2952008-12-08 18:16:58 +0000462
463 if (op == NULL) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000464 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
FENG yu ningc05a2952008-12-08 18:16:58 +0000465 return -1;
466 }
467
Stefan Taunera8d838d2011-11-06 23:51:09 +0000468 switch (ich_generation) {
469 case CHIPSET_ICH7:
FENG yu ningc05a2952008-12-08 18:16:58 +0000470 preop = REGREAD16(ICH7_REG_PREOP);
471 optype = REGREAD16(ICH7_REG_OPTYPE);
472 opmenu[0] = REGREAD32(ICH7_REG_OPMENU);
473 opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4);
474 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000475 case CHIPSET_ICH8:
476 default: /* Future version might behave the same */
FENG yu ningc05a2952008-12-08 18:16:58 +0000477 preop = REGREAD16(ICH9_REG_PREOP);
478 optype = REGREAD16(ICH9_REG_OPTYPE);
479 opmenu[0] = REGREAD32(ICH9_REG_OPMENU);
480 opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4);
481 break;
FENG yu ningc05a2952008-12-08 18:16:58 +0000482 }
483
484 op->preop[0] = (uint8_t) preop;
485 op->preop[1] = (uint8_t) (preop >> 8);
486
487 for (a = 0; a < 8; a++) {
488 op->opcode[a].spi_type = (uint8_t) (optype & 0x3);
489 optype >>= 2;
490 }
491
492 for (a = 0; a < 4; a++) {
493 op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff);
494 opmenu[0] >>= 8;
495 }
496
497 for (a = 4; a < 8; a++) {
498 op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff);
499 opmenu[1] >>= 8;
500 }
501
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000502 /* No preopcodes used by default. */
503 for (a = 0; a < 8; a++)
FENG yu ningc05a2952008-12-08 18:16:58 +0000504 op->opcode[a].atomic = 0;
505
FENG yu ningc05a2952008-12-08 18:16:58 +0000506 return 0;
507}
508
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000509static int program_opcodes(OPCODES *op, int enable_undo)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000510{
511 uint8_t a;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000512 uint16_t preop, optype;
513 uint32_t opmenu[2];
Dominik Geyerb46acba2008-05-16 12:55:55 +0000514
515 /* Program Prefix Opcodes */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000516 /* 0:7 Prefix Opcode 1 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000517 preop = (op->preop[0]);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000518 /* 8:16 Prefix Opcode 2 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000519 preop |= ((uint16_t) op->preop[1]) << 8;
Uwe Hermann394131e2008-10-18 21:14:13 +0000520
Stefan Reinauera9424d52008-06-27 16:28:34 +0000521 /* Program Opcode Types 0 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000522 optype = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000523 for (a = 0; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000524 optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000525 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000526
Stefan Reinauera9424d52008-06-27 16:28:34 +0000527 /* Program Allowable Opcodes 0 - 3 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000528 opmenu[0] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000529 for (a = 0; a < 4; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000530 opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000531 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000532
Dominik Geyerb46acba2008-05-16 12:55:55 +0000533 /*Program Allowable Opcodes 4 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000534 opmenu[1] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000535 for (a = 4; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000536 opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000537 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000538
Sean Nelson316a29f2010-05-07 20:09:04 +0000539 msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]);
Stefan Taunera8d838d2011-11-06 23:51:09 +0000540 switch (ich_generation) {
541 case CHIPSET_ICH7:
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000542 /* Register undo only for enable_undo=1, i.e. first call. */
543 if (enable_undo) {
544 rmmio_valw(ich_spibar + ICH7_REG_PREOP);
545 rmmio_valw(ich_spibar + ICH7_REG_OPTYPE);
546 rmmio_vall(ich_spibar + ICH7_REG_OPMENU);
547 rmmio_vall(ich_spibar + ICH7_REG_OPMENU + 4);
548 }
549 mmio_writew(preop, ich_spibar + ICH7_REG_PREOP);
550 mmio_writew(optype, ich_spibar + ICH7_REG_OPTYPE);
551 mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU);
552 mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000553 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000554 case CHIPSET_ICH8:
555 default: /* Future version might behave the same */
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000556 /* Register undo only for enable_undo=1, i.e. first call. */
557 if (enable_undo) {
558 rmmio_valw(ich_spibar + ICH9_REG_PREOP);
559 rmmio_valw(ich_spibar + ICH9_REG_OPTYPE);
560 rmmio_vall(ich_spibar + ICH9_REG_OPMENU);
561 rmmio_vall(ich_spibar + ICH9_REG_OPMENU + 4);
562 }
563 mmio_writew(preop, ich_spibar + ICH9_REG_PREOP);
564 mmio_writew(optype, ich_spibar + ICH9_REG_OPTYPE);
565 mmio_writel(opmenu[0], ich_spibar + ICH9_REG_OPMENU);
566 mmio_writel(opmenu[1], ich_spibar + ICH9_REG_OPMENU + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000567 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000568 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000569
570 return 0;
571}
572
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000573/*
Stefan Tauner50e7c602011-11-08 10:55:54 +0000574 * Returns -1 if at least one mandatory opcode is inaccessible, 0 otherwise.
575 * FIXME: this should also check for
576 * - at least one probing opcode (RDID (incl. AT25F variants?), REMS, RES?)
577 * - at least one erasing opcode (lots.)
578 * - at least one program opcode (BYTE_PROGRAM, AAI_WORD_PROGRAM, ...?)
579 * - necessary preops? (EWSR, WREN, ...?)
580 */
581static int ich_missing_opcodes()
582{
583 uint8_t ops[] = {
584 JEDEC_READ,
585 JEDEC_RDSR,
586 0
587 };
588 int i = 0;
589 while (ops[i] != 0) {
590 msg_pspew("checking for opcode 0x%02x\n", ops[i]);
591 if (find_opcode(curopcodes, ops[i]) == -1)
592 return -1;
593 i++;
594 }
595 return 0;
596}
597
598/*
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000599 * Try to set BBAR (BIOS Base Address Register), but read back the value in case
600 * it didn't stick.
601 */
Stefan Taunera8d838d2011-11-06 23:51:09 +0000602static void ich_set_bbar(uint32_t min_addr)
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000603{
Stefan Taunere27b2d42011-07-01 00:39:09 +0000604 int bbar_off;
Stefan Tauner7783f312011-09-17 21:21:42 +0000605 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +0000606 case CHIPSET_ICH7:
Stefan Taunere27b2d42011-07-01 00:39:09 +0000607 bbar_off = 0x50;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000608 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000609 case CHIPSET_ICH8:
Stefan Tauner7783f312011-09-17 21:21:42 +0000610 msg_perr("BBAR offset is unknown on ICH8!\n");
611 return;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000612 case CHIPSET_ICH9:
Stefan Tauner7783f312011-09-17 21:21:42 +0000613 default: /* Future version might behave the same */
Stefan Taunere27b2d42011-07-01 00:39:09 +0000614 bbar_off = ICH9_REG_BBAR;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000615 break;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000616 }
Stefan Taunere27b2d42011-07-01 00:39:09 +0000617
618 ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK;
619 if (ichspi_bbar) {
620 msg_pdbg("Reserved bits in BBAR not zero: 0x%08x\n",
621 ichspi_bbar);
622 }
623 min_addr &= BBAR_MASK;
624 ichspi_bbar |= min_addr;
625 rmmio_writel(ichspi_bbar, ich_spibar + bbar_off);
626 ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & BBAR_MASK;
627
628 /* We don't have any option except complaining. And if the write
629 * failed, the restore will fail as well, so no problem there.
630 */
631 if (ichspi_bbar != min_addr)
Stefan Tauner7783f312011-09-17 21:21:42 +0000632 msg_perr("Setting BBAR to 0x%08x failed! New value: 0x%08x.\n",
633 min_addr, ichspi_bbar);
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000634}
635
Stefan Tauner8b391b82011-08-09 01:49:34 +0000636/* Read len bytes from the fdata/spid register into the data array.
637 *
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +0000638 * Note that using len > flash->pgm->spi.max_data_read will return garbage or
Stefan Tauner8b391b82011-08-09 01:49:34 +0000639 * may even crash.
640 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000641static void ich_read_data(uint8_t *data, int len, int reg0_off)
Stefan Tauner8b391b82011-08-09 01:49:34 +0000642 {
643 int i;
644 uint32_t temp32 = 0;
645
646 for (i = 0; i < len; i++) {
647 if ((i % 4) == 0)
648 temp32 = REGREAD32(reg0_off + i);
649
650 data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
651 }
652}
653
654/* Fill len bytes from the data array into the fdata/spid registers.
655 *
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +0000656 * Note that using len > flash->pgm->spi.max_data_write will trash the registers
Stefan Tauner8b391b82011-08-09 01:49:34 +0000657 * following the data registers.
658 */
659static void ich_fill_data(const uint8_t *data, int len, int reg0_off)
660{
661 uint32_t temp32 = 0;
662 int i;
663
664 if (len <= 0)
665 return;
666
667 for (i = 0; i < len; i++) {
668 if ((i % 4) == 0)
669 temp32 = 0;
670
671 temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
672
673 if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
674 REGWRITE32(reg0_off + (i - (i % 4)), temp32);
675 }
676 i--;
677 if ((i % 4) != 3) /* Write remaining data to regs. */
678 REGWRITE32(reg0_off + (i - (i % 4)), temp32);
679}
680
FENG yu ningf041e9b2008-12-15 02:32:11 +0000681/* This function generates OPCODES from or programs OPCODES to ICH according to
682 * the chipset's SPI configuration lock.
FENG yu ningc05a2952008-12-08 18:16:58 +0000683 *
FENG yu ningf041e9b2008-12-15 02:32:11 +0000684 * It should be called before ICH sends any spi command.
FENG yu ningc05a2952008-12-08 18:16:58 +0000685 */
Michael Karchera4448d92010-07-22 18:04:15 +0000686static int ich_init_opcodes(void)
FENG yu ningc05a2952008-12-08 18:16:58 +0000687{
688 int rc = 0;
689 OPCODES *curopcodes_done;
690
691 if (curopcodes)
692 return 0;
693
694 if (ichspi_lock) {
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000695 msg_pdbg("Reading OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000696 curopcodes_done = &O_EXISTING;
FENG yu ningf041e9b2008-12-15 02:32:11 +0000697 rc = generate_opcodes(curopcodes_done);
FENG yu ningc05a2952008-12-08 18:16:58 +0000698 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000699 msg_pdbg("Programming OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000700 curopcodes_done = &O_ST_M25P;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000701 rc = program_opcodes(curopcodes_done, 1);
FENG yu ningc05a2952008-12-08 18:16:58 +0000702 }
703
704 if (rc) {
705 curopcodes = NULL;
Sean Nelson316a29f2010-05-07 20:09:04 +0000706 msg_perr("failed\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000707 return 1;
708 } else {
709 curopcodes = curopcodes_done;
Sean Nelson316a29f2010-05-07 20:09:04 +0000710 msg_pdbg("done\n");
Stefan Tauner8b391b82011-08-09 01:49:34 +0000711 prettyprint_opcodes(curopcodes);
FENG yu ningc05a2952008-12-08 18:16:58 +0000712 return 0;
713 }
714}
715
Stefan Reinauer43119562008-11-02 19:51:50 +0000716static int ich7_run_opcode(OPCODE op, uint32_t offset,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000717 uint8_t datalength, uint8_t * data, int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000718{
719 int write_cmd = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000720 int timeout;
Stefan Tauner8b391b82011-08-09 01:49:34 +0000721 uint32_t temp32;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000722 uint16_t temp16;
Stefan Reinauer43119562008-11-02 19:51:50 +0000723 uint64_t opmenu;
724 int opcode_index;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000725
726 /* Is it a write command? */
727 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
728 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
729 write_cmd = 1;
730 }
731
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000732 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
733 while ((REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) && --timeout) {
734 programmer_delay(10);
735 }
736 if (!timeout) {
737 msg_perr("Error: SCIP never cleared!\n");
738 return 1;
739 }
740
Stefan Tauner10b3e222011-07-01 00:39:23 +0000741 /* Program offset in flash into SPIA while preserving reserved bits. */
742 temp32 = REGREAD32(ICH7_REG_SPIA) & ~0x00FFFFFF;
743 REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000744
Stefan Tauner10b3e222011-07-01 00:39:23 +0000745 /* Program data into SPID0 to N */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000746 if (write_cmd && (datalength != 0))
747 ich_fill_data(data, datalength, ICH7_REG_SPID0);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000748
749 /* Assemble SPIS */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000750 temp16 = REGREAD16(ICH7_REG_SPIS);
751 /* keep reserved bits */
752 temp16 &= SPIS_RESERVED_MASK;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000753 /* clear error status registers */
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000754 temp16 |= (SPIS_CDS | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000755 REGWRITE16(ICH7_REG_SPIS, temp16);
756
757 /* Assemble SPIC */
758 temp16 = 0;
759
760 if (datalength != 0) {
761 temp16 |= SPIC_DS;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000762 temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000763 }
764
765 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000766 opmenu = REGREAD32(ICH7_REG_OPMENU);
767 opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32;
768
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000769 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
770 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000771 break;
772 }
773 opmenu >>= 8;
774 }
775 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000776 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000777 return 1;
778 }
779 temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000780
Michael Karcher136125a2011-04-29 22:11:36 +0000781 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
782 /* Handle Atomic. Atomic commands include three steps:
783 - sending the preop (mainly EWSR or WREN)
784 - sending the main command
785 - waiting for the busy bit (WIP) to be cleared
786 This means the timeout must be sufficient for chip erase
787 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000788 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000789 switch (op.atomic) {
790 case 2:
791 /* Select second preop. */
792 temp16 |= SPIC_SPOP;
793 /* And fall through. */
794 case 1:
795 /* Atomic command (preop+op) */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000796 temp16 |= SPIC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +0000797 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000798 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000799 }
800
801 /* Start */
802 temp16 |= SPIC_SCGO;
803
804 /* write it */
805 REGWRITE16(ICH7_REG_SPIC, temp16);
806
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000807 /* Wait for Cycle Done Status or Flash Cycle Error. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000808 while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) &&
809 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000810 programmer_delay(10);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000811 }
812 if (!timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000813 msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n",
814 REGREAD16(ICH7_REG_SPIS));
815 return 1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000816 }
817
Sean Nelson316a29f2010-05-07 20:09:04 +0000818 /* FIXME: make sure we do not needlessly cause transaction errors. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000819 temp16 = REGREAD16(ICH7_REG_SPIS);
820 if (temp16 & SPIS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +0000821 msg_perr("Transaction error!\n");
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000822 /* keep reserved bits */
823 temp16 &= SPIS_RESERVED_MASK;
824 REGWRITE16(ICH7_REG_SPIS, temp16 | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000825 return 1;
826 }
827
Stefan Tauner8b391b82011-08-09 01:49:34 +0000828 if ((!write_cmd) && (datalength != 0))
829 ich_read_data(data, datalength, ICH7_REG_SPID0);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000830
831 return 0;
832}
833
Stefan Reinauer43119562008-11-02 19:51:50 +0000834static int ich9_run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000835 uint8_t datalength, uint8_t * data)
836{
837 int write_cmd = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000838 int timeout;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000839 uint32_t temp32;
Stefan Reinauer43119562008-11-02 19:51:50 +0000840 uint64_t opmenu;
841 int opcode_index;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000842
843 /* Is it a write command? */
844 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
845 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
846 write_cmd = 1;
847 }
848
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000849 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
850 while ((REGREAD8(ICH9_REG_SSFS) & SSFS_SCIP) && --timeout) {
851 programmer_delay(10);
852 }
853 if (!timeout) {
854 msg_perr("Error: SCIP never cleared!\n");
855 return 1;
856 }
857
Stefan Tauner10b3e222011-07-01 00:39:23 +0000858 /* Program offset in flash into FADDR while preserve the reserved bits
859 * and clearing the 25. address bit which is only useable in hwseq. */
860 temp32 = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF;
861 REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000862
863 /* Program data into FDATA0 to N */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000864 if (write_cmd && (datalength != 0))
865 ich_fill_data(data, datalength, ICH9_REG_FDATA0);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000866
867 /* Assemble SSFS + SSFC */
Helge Wagnera319be12010-08-11 21:06:10 +0000868 temp32 = REGREAD32(ICH9_REG_SSFS);
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000869 /* Keep reserved bits only */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000870 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000871 /* Clear cycle done and cycle error status registers */
872 temp32 |= (SSFS_FDONE | SSFS_FCERR);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000873 REGWRITE32(ICH9_REG_SSFS, temp32);
874
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000875 /* Use 20 MHz */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000876 temp32 |= SSFC_SCF_20MHZ;
877
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000878 /* Set data byte count (DBC) and data cycle bit (DS) */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000879 if (datalength != 0) {
880 uint32_t datatemp;
881 temp32 |= SSFC_DS;
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000882 datatemp = ((((uint32_t)datalength - 1) << SSFC_DBC_OFF) &
883 SSFC_DBC);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000884 temp32 |= datatemp;
885 }
886
887 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000888 opmenu = REGREAD32(ICH9_REG_OPMENU);
889 opmenu |= ((uint64_t)REGREAD32(ICH9_REG_OPMENU + 4)) << 32;
890
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000891 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
892 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000893 break;
894 }
895 opmenu >>= 8;
896 }
897 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000898 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000899 return 1;
900 }
901 temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000902
Michael Karcher136125a2011-04-29 22:11:36 +0000903 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
904 /* Handle Atomic. Atomic commands include three steps:
905 - sending the preop (mainly EWSR or WREN)
906 - sending the main command
907 - waiting for the busy bit (WIP) to be cleared
908 This means the timeout must be sufficient for chip erase
909 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000910 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000911 switch (op.atomic) {
912 case 2:
913 /* Select second preop. */
914 temp32 |= SSFC_SPOP;
915 /* And fall through. */
916 case 1:
917 /* Atomic command (preop+op) */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000918 temp32 |= SSFC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +0000919 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000920 break;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000921 }
922
923 /* Start */
924 temp32 |= SSFC_SCGO;
925
926 /* write it */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000927 REGWRITE32(ICH9_REG_SSFS, temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000928
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000929 /* Wait for Cycle Done Status or Flash Cycle Error. */
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000930 while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_FDONE | SSFS_FCERR)) == 0) &&
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000931 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000932 programmer_delay(10);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000933 }
934 if (!timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000935 msg_perr("timeout, ICH9_REG_SSFS=0x%08x\n",
936 REGREAD32(ICH9_REG_SSFS));
937 return 1;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000938 }
939
Sean Nelson316a29f2010-05-07 20:09:04 +0000940 /* FIXME make sure we do not needlessly cause transaction errors. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000941 temp32 = REGREAD32(ICH9_REG_SSFS);
942 if (temp32 & SSFS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +0000943 msg_perr("Transaction error!\n");
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000944 prettyprint_ich9_reg_ssfs(temp32);
945 prettyprint_ich9_reg_ssfc(temp32);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000946 /* keep reserved bits */
947 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
948 /* Clear the transaction error. */
949 REGWRITE32(ICH9_REG_SSFS, temp32 | SSFS_FCERR);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000950 return 1;
951 }
952
Stefan Tauner8b391b82011-08-09 01:49:34 +0000953 if ((!write_cmd) && (datalength != 0))
954 ich_read_data(data, datalength, ICH9_REG_FDATA0);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000955
956 return 0;
957}
958
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000959static int run_opcode(const struct flashctx *flash, OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000960 uint8_t datalength, uint8_t * data)
961{
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000962 /* max_data_read == max_data_write for all Intel/VIA SPI masters */
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +0000963 uint8_t maxlength = flash->pgm->spi.max_data_read;
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000964
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +0000965 if (ich_generation == CHIPSET_ICH_UNKNOWN) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000966 msg_perr("%s: unsupported chipset\n", __func__);
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000967 return -1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000968 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000969
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000970 if (datalength > maxlength) {
971 msg_perr("%s: Internal command size error for "
972 "opcode 0x%02x, got datalength=%i, want <=%i\n",
973 __func__, op.opcode, datalength, maxlength);
974 return SPI_INVALID_LENGTH;
975 }
976
Stefan Taunera8d838d2011-11-06 23:51:09 +0000977 switch (ich_generation) {
978 case CHIPSET_ICH7:
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000979 return ich7_run_opcode(op, offset, datalength, data, maxlength);
Stefan Taunera8d838d2011-11-06 23:51:09 +0000980 case CHIPSET_ICH8:
981 default: /* Future version might behave the same */
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000982 return ich9_run_opcode(op, offset, datalength, data);
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000983 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000984}
985
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000986static int ich_spi_send_command(struct flashctx *flash, unsigned int writecnt,
987 unsigned int readcnt,
988 const unsigned char *writearr,
989 unsigned char *readarr)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000990{
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000991 int result;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000992 int opcode_index = -1;
993 const unsigned char cmd = *writearr;
994 OPCODE *opcode;
995 uint32_t addr = 0;
996 uint8_t *data;
997 int count;
998
Dominik Geyerb46acba2008-05-16 12:55:55 +0000999 /* find cmd in opcodes-table */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001000 opcode_index = find_opcode(curopcodes, cmd);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001001 if (opcode_index == -1) {
Helge Wagner738e2522010-10-05 22:06:05 +00001002 if (!ichspi_lock)
1003 opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt);
1004 if (opcode_index == -1) {
Stefan Tauner355cbfd2011-05-28 02:37:14 +00001005 msg_pdbg("Invalid OPCODE 0x%02x, will not execute.\n",
1006 cmd);
Helge Wagner738e2522010-10-05 22:06:05 +00001007 return SPI_INVALID_OPCODE;
1008 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001009 }
1010
1011 opcode = &(curopcodes->opcode[opcode_index]);
1012
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001013 /* The following valid writecnt/readcnt combinations exist:
1014 * writecnt = 4, readcnt >= 0
1015 * writecnt = 1, readcnt >= 0
1016 * writecnt >= 4, readcnt = 0
1017 * writecnt >= 1, readcnt = 0
1018 * writecnt >= 1 is guaranteed for all commands.
1019 */
1020 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) &&
1021 (writecnt != 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001022 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001023 "0x%02x, got writecnt=%i, want =4\n", __func__, cmd,
1024 writecnt);
1025 return SPI_INVALID_LENGTH;
1026 }
1027 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) &&
1028 (writecnt != 1)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001029 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001030 "0x%02x, got writecnt=%i, want =1\n", __func__, cmd,
1031 writecnt);
1032 return SPI_INVALID_LENGTH;
1033 }
1034 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) &&
1035 (writecnt < 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001036 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001037 "0x%02x, got writecnt=%i, want >=4\n", __func__, cmd,
1038 writecnt);
1039 return SPI_INVALID_LENGTH;
1040 }
1041 if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1042 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) &&
1043 (readcnt)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001044 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001045 "0x%02x, got readcnt=%i, want =0\n", __func__, cmd,
1046 readcnt);
1047 return SPI_INVALID_LENGTH;
1048 }
1049
Dominik Geyerb46acba2008-05-16 12:55:55 +00001050 /* if opcode-type requires an address */
1051 if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS ||
1052 opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001053 addr = (writearr[1] << 16) |
1054 (writearr[2] << 8) | (writearr[3] << 0);
Stefan Taunera8d838d2011-11-06 23:51:09 +00001055 if (addr < ichspi_bbar) {
1056 msg_perr("%s: Address 0x%06x below allowed "
1057 "range 0x%06x-0xffffff\n", __func__,
1058 addr, ichspi_bbar);
1059 return SPI_INVALID_ADDRESS;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +00001060 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001061 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001062
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001063 /* Translate read/write array/count.
1064 * The maximum data length is identical for the maximum read length and
1065 * for the maximum write length excluding opcode and address. Opcode and
1066 * address are stored in separate registers, not in the data registers
1067 * and are thus not counted towards data length. The only exception
1068 * applies if the opcode definition (un)intentionally classifies said
1069 * opcode incorrectly as non-address opcode or vice versa. */
Dominik Geyerb46acba2008-05-16 12:55:55 +00001070 if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001071 data = (uint8_t *) (writearr + 1);
1072 count = writecnt - 1;
1073 } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
1074 data = (uint8_t *) (writearr + 4);
1075 count = writecnt - 4;
1076 } else {
1077 data = (uint8_t *) readarr;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001078 count = readcnt;
1079 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001080
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001081 result = run_opcode(flash, *opcode, addr, count, data);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001082 if (result) {
Stefan Tauner8ed29342011-04-29 23:53:09 +00001083 msg_pdbg("Running OPCODE 0x%02x failed ", opcode->opcode);
1084 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1085 (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS)) {
1086 msg_pdbg("at address 0x%06x ", addr);
1087 }
1088 msg_pdbg("(payload length was %d).\n", count);
1089
1090 /* Print out the data array if it contains data to write.
1091 * Errors are detected before the received data is read back into
1092 * the array so it won't make sense to print it then. */
1093 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1094 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) {
1095 int i;
1096 msg_pspew("The data was:\n");
Stefan Taunerf382e352011-11-08 11:55:24 +00001097 for (i = 0; i < count; i++){
Stefan Tauner8ed29342011-04-29 23:53:09 +00001098 msg_pspew("%3d: 0x%02x\n", i, data[i]);
1099 }
1100 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001101 }
1102
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001103 return result;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001104}
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001105
Stefan Tauner50e7c602011-11-08 10:55:54 +00001106static struct hwseq_data {
1107 uint32_t size_comp0;
1108 uint32_t size_comp1;
1109} hwseq_data;
1110
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001111/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */
1112static void ich_hwseq_set_addr(uint32_t addr)
1113{
1114 uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF;
1115 REGWRITE32(ICH9_REG_FADDR, (addr & 0x01FFFFFF) | addr_old);
1116}
1117
1118/* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes
1119 * of the block containing this address. May return nonsense if the address is
1120 * not valid. The erase block size for a specific address depends on the flash
1121 * partition layout as specified by FPB and the partition properties as defined
1122 * by UVSCC and LVSCC respectively. An alternative to implement this method
1123 * would be by querying FPB and the respective VSCC register directly.
1124 */
1125static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr)
1126{
1127 uint8_t enc_berase;
1128 static const uint32_t const dec_berase[4] = {
1129 256,
1130 4 * 1024,
1131 8 * 1024,
1132 64 * 1024
1133 };
1134
1135 ich_hwseq_set_addr(addr);
1136 enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >>
1137 HSFS_BERASE_OFF;
1138 return dec_berase[enc_berase];
1139}
1140
1141/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
1142 Resets all error flags in HSFS.
1143 Returns 0 if the cycle completes successfully without errors within
1144 timeout us, 1 on errors. */
1145static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
1146 unsigned int len)
1147{
1148 uint16_t hsfs;
1149 uint32_t addr;
1150
1151 timeout /= 8; /* scale timeout duration to counter */
1152 while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) &
1153 (HSFS_FDONE | HSFS_FCERR)) == 0) &&
1154 --timeout) {
1155 programmer_delay(8);
1156 }
1157 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1158 if (!timeout) {
1159 addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF;
1160 msg_perr("Timeout error between offset 0x%08x and "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001161 "0x%08x (= 0x%08x + %d)!\n",
1162 addr, addr + len - 1, addr, len - 1);
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001163 prettyprint_ich9_reg_hsfs(hsfs);
1164 prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC));
1165 return 1;
1166 }
1167
1168 if (hsfs & HSFS_FCERR) {
1169 addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF;
1170 msg_perr("Transaction error between offset 0x%08x and "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001171 "0x%08x (= 0x%08x + %d)!\n",
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001172 addr, addr + len - 1, addr, len - 1);
1173 prettyprint_ich9_reg_hsfs(hsfs);
1174 prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC));
1175 return 1;
1176 }
1177 return 0;
1178}
Stefan Tauner50e7c602011-11-08 10:55:54 +00001179
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001180static int ich_hwseq_probe(struct flashctx *flash)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001181{
1182 uint32_t total_size, boundary;
1183 uint32_t erase_size_low, size_low, erase_size_high, size_high;
1184 struct block_eraser *eraser;
1185
1186 total_size = hwseq_data.size_comp0 + hwseq_data.size_comp1;
1187 msg_cdbg("Found %d attached SPI flash chip",
1188 (hwseq_data.size_comp1 != 0) ? 2 : 1);
1189 if (hwseq_data.size_comp1 != 0)
1190 msg_cdbg("s with a combined");
1191 else
1192 msg_cdbg(" with a");
1193 msg_cdbg(" density of %d kB.\n", total_size / 1024);
1194 flash->total_size = total_size / 1024;
1195
1196 eraser = &(flash->block_erasers[0]);
1197 boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12;
1198 size_high = total_size - boundary;
1199 erase_size_high = ich_hwseq_get_erase_block_size(boundary);
1200
1201 if (boundary == 0) {
1202 msg_cdbg("There is only one partition containing the whole "
1203 "address space (0x%06x - 0x%06x).\n", 0, size_high-1);
1204 eraser->eraseblocks[0].size = erase_size_high;
1205 eraser->eraseblocks[0].count = size_high / erase_size_high;
1206 msg_cdbg("There are %d erase blocks with %d B each.\n",
1207 size_high / erase_size_high, erase_size_high);
1208 } else {
1209 msg_cdbg("The flash address space (0x%06x - 0x%06x) is divided "
1210 "at address 0x%06x in two partitions.\n",
1211 0, size_high-1, boundary);
1212 size_low = total_size - size_high;
1213 erase_size_low = ich_hwseq_get_erase_block_size(0);
1214
1215 eraser->eraseblocks[0].size = erase_size_low;
1216 eraser->eraseblocks[0].count = size_low / erase_size_low;
1217 msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n",
1218 0, size_low-1);
1219 msg_cdbg("In that range are %d erase blocks with %d B each.\n",
1220 size_low / erase_size_low, erase_size_low);
1221
1222 eraser->eraseblocks[1].size = erase_size_high;
1223 eraser->eraseblocks[1].count = size_high / erase_size_high;
1224 msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n",
1225 boundary, size_high-1);
1226 msg_cdbg("In that range are %d erase blocks with %d B each.\n",
1227 size_high / erase_size_high, erase_size_high);
1228 }
1229 flash->tested = TEST_OK_PREW;
1230 return 1;
1231}
1232
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001233static int ich_hwseq_block_erase(struct flashctx *flash, unsigned int addr,
1234 unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001235{
1236 uint32_t erase_block;
1237 uint16_t hsfc;
1238 uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */
1239
1240 erase_block = ich_hwseq_get_erase_block_size(addr);
1241 if (len != erase_block) {
1242 msg_cerr("Erase block size for address 0x%06x is %d B, "
1243 "but requested erase block size is %d B. "
1244 "Not erasing anything.\n", addr, erase_block, len);
1245 return -1;
1246 }
1247
1248 /* Although the hardware supports this (it would erase the whole block
1249 * containing the address) we play safe here. */
1250 if (addr % erase_block != 0) {
1251 msg_cerr("Erase address 0x%06x is not aligned to the erase "
1252 "block boundary (any multiple of %d). "
1253 "Not erasing anything.\n", addr, erase_block);
1254 return -1;
1255 }
1256
1257 if (addr + len > flash->total_size * 1024) {
1258 msg_perr("Request to erase some inaccessible memory address(es)"
1259 " (addr=0x%x, len=%d). "
1260 "Not erasing anything.\n", addr, len);
1261 return -1;
1262 }
1263
1264 msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr);
1265
1266 /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
1267 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1268
1269 hsfc = REGREAD16(ICH9_REG_HSFC);
1270 hsfc &= ~HSFC_FCYCLE; /* clear operation */
1271 hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
1272 hsfc |= HSFC_FGO; /* start */
1273 msg_pdbg("HSFC used for block erasing: ");
1274 prettyprint_ich9_reg_hsfc(hsfc);
1275 REGWRITE16(ICH9_REG_HSFC, hsfc);
1276
1277 if (ich_hwseq_wait_for_cycle_complete(timeout, len))
1278 return -1;
1279 return 0;
1280}
1281
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001282static int ich_hwseq_read(struct flashctx *flash, uint8_t *buf,
1283 unsigned int addr, unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001284{
1285 uint16_t hsfc;
1286 uint16_t timeout = 100 * 60;
1287 uint8_t block_len;
1288
Paul Menzelac427b22012-02-16 21:07:07 +00001289 if (addr + len > flash->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001290 msg_perr("Request to read from an inaccessible memory address "
1291 "(addr=0x%x, len=%d).\n", addr, len);
1292 return -1;
1293 }
1294
1295 msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr);
1296 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
1297 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1298
1299 while (len > 0) {
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +00001300 block_len = min(len, flash->pgm->opaque.max_data_read);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001301 ich_hwseq_set_addr(addr);
1302 hsfc = REGREAD16(ICH9_REG_HSFC);
1303 hsfc &= ~HSFC_FCYCLE; /* set read operation */
1304 hsfc &= ~HSFC_FDBC; /* clear byte count */
1305 /* set byte count */
1306 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
1307 hsfc |= HSFC_FGO; /* start */
1308 REGWRITE16(ICH9_REG_HSFC, hsfc);
1309
1310 if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
1311 return 1;
1312 ich_read_data(buf, block_len, ICH9_REG_FDATA0);
1313 addr += block_len;
1314 buf += block_len;
1315 len -= block_len;
1316 }
1317 return 0;
1318}
1319
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001320static int ich_hwseq_write(struct flashctx *flash, uint8_t *buf,
1321 unsigned int addr, unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001322{
1323 uint16_t hsfc;
1324 uint16_t timeout = 100 * 60;
1325 uint8_t block_len;
1326
Paul Menzelac427b22012-02-16 21:07:07 +00001327 if (addr + len > flash->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001328 msg_perr("Request to write to an inaccessible memory address "
1329 "(addr=0x%x, len=%d).\n", addr, len);
1330 return -1;
1331 }
1332
1333 msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr);
1334 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
1335 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1336
1337 while (len > 0) {
1338 ich_hwseq_set_addr(addr);
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +00001339 block_len = min(len, flash->pgm->opaque.max_data_write);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001340 ich_fill_data(buf, block_len, ICH9_REG_FDATA0);
1341 hsfc = REGREAD16(ICH9_REG_HSFC);
1342 hsfc &= ~HSFC_FCYCLE; /* clear operation */
1343 hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */
1344 hsfc &= ~HSFC_FDBC; /* clear byte count */
1345 /* set byte count */
1346 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
1347 hsfc |= HSFC_FGO; /* start */
1348 REGWRITE16(ICH9_REG_HSFC, hsfc);
1349
1350 if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
1351 return -1;
1352 addr += block_len;
1353 buf += block_len;
1354 len -= block_len;
1355 }
1356 return 0;
1357}
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001358
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001359static int ich_spi_send_multicommand(struct flashctx *flash,
1360 struct spi_command *cmds)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001361{
1362 int ret = 0;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001363 int i;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001364 int oppos, preoppos;
1365 for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) {
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001366 if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001367 /* Next command is valid. */
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001368 preoppos = find_preop(curopcodes, cmds->writearr[0]);
1369 oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001370 if ((oppos == -1) && (preoppos != -1)) {
1371 /* Current command is listed as preopcode in
1372 * ICH struct OPCODES, but next command is not
1373 * listed as opcode in that struct.
1374 * Check for command sanity, then
1375 * try to reprogram the ICH opcode list.
1376 */
1377 if (find_preop(curopcodes,
1378 (cmds + 1)->writearr[0]) != -1) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001379 msg_perr("%s: Two subsequent "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001380 "preopcodes 0x%02x and 0x%02x, "
1381 "ignoring the first.\n",
1382 __func__, cmds->writearr[0],
1383 (cmds + 1)->writearr[0]);
1384 continue;
1385 }
1386 /* If the chipset is locked down, we'll fail
1387 * during execution of the next command anyway.
1388 * No need to bother with fixups.
1389 */
1390 if (!ichspi_lock) {
Helge Wagner738e2522010-10-05 22:06:05 +00001391 oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt);
1392 if (oppos == -1)
1393 continue;
1394 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001395 continue;
1396 }
1397 }
1398 if ((oppos != -1) && (preoppos != -1)) {
1399 /* Current command is listed as preopcode in
1400 * ICH struct OPCODES and next command is listed
1401 * as opcode in that struct. Match them up.
1402 */
1403 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001404 continue;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001405 }
1406 /* If none of the above if-statements about oppos or
1407 * preoppos matched, this is a normal opcode.
1408 */
1409 }
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001410 ret = ich_spi_send_command(flash, cmds->writecnt, cmds->readcnt,
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001411 cmds->writearr, cmds->readarr);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001412 /* Reset the type of all opcodes to non-atomic. */
1413 for (i = 0; i < 8; i++)
1414 curopcodes->opcode[i].atomic = 0;
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001415 }
1416 return ret;
1417}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001418
Michael Karchera4448d92010-07-22 18:04:15 +00001419#define ICH_BMWAG(x) ((x >> 24) & 0xff)
1420#define ICH_BMRAG(x) ((x >> 16) & 0xff)
1421#define ICH_BRWA(x) ((x >> 8) & 0xff)
1422#define ICH_BRRA(x) ((x >> 0) & 0xff)
1423
Stefan Tauner5210e722012-02-16 01:13:00 +00001424/* returns 0 if region is unused or r/w */
1425static int ich9_handle_frap(uint32_t frap, int i)
Michael Karchera4448d92010-07-22 18:04:15 +00001426{
Mathias Krausea60faab2011-01-17 07:50:42 +00001427 static const char *const access_names[4] = {
Michael Karchera4448d92010-07-22 18:04:15 +00001428 "locked", "read-only", "write-only", "read-write"
1429 };
Mathias Krausea60faab2011-01-17 07:50:42 +00001430 static const char *const region_names[5] = {
Michael Karchera4448d92010-07-22 18:04:15 +00001431 "Flash Descriptor", "BIOS", "Management Engine",
1432 "Gigabit Ethernet", "Platform Data"
1433 };
1434 uint32_t base, limit;
1435 int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) |
1436 (((ICH_BRRA(frap) >> i) & 1) << 0);
Stefan Tauner29c80832011-06-12 08:14:10 +00001437 int offset = ICH9_REG_FREG0 + i * 4;
Michael Karchera4448d92010-07-22 18:04:15 +00001438 uint32_t freg = mmio_readl(ich_spibar + offset);
1439
Michael Karchera4448d92010-07-22 18:04:15 +00001440 base = ICH_FREG_BASE(freg);
1441 limit = ICH_FREG_LIMIT(freg);
Joshua Roysd172ecd2011-05-26 13:30:51 +00001442 if (base > limit) {
Michael Karchera4448d92010-07-22 18:04:15 +00001443 /* this FREG is disabled */
Stefan Tauner5210e722012-02-16 01:13:00 +00001444 msg_pdbg2("0x%02X: 0x%08x FREG%i: %s region is unused.\n",
1445 offset, freg, i, region_names[i]);
1446 return 0;
1447 }
1448 msg_pdbg("0x%02X: 0x%08x ", offset, freg);
1449 if (rwperms == 0x3) {
1450 msg_pdbg("FREG%i: %s region (0x%08x-0x%08x) is %s.\n", i,
1451 region_names[i], base, (limit | 0x0fff),
1452 access_names[rwperms]);
1453 return 0;
Michael Karchera4448d92010-07-22 18:04:15 +00001454 }
1455
Stefan Tauner5210e722012-02-16 01:13:00 +00001456 msg_pinfo("FREG%i: WARNING: %s region (0x%08x-0x%08x) is %s.\n", i,
1457 region_names[i], base, (limit | 0x0fff),
1458 access_names[rwperms]);
1459 return 1;
Michael Karchera4448d92010-07-22 18:04:15 +00001460}
1461
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001462 /* In contrast to FRAP and the master section of the descriptor the bits
1463 * in the PR registers have an inverted meaning. The bits in FRAP
1464 * indicate read and write access _grant_. Here they indicate read
1465 * and write _protection_ respectively. If both bits are 0 the address
1466 * bits are ignored.
1467 */
1468#define ICH_PR_PERMS(pr) (((~((pr) >> PR_RP_OFF) & 1) << 0) | \
1469 ((~((pr) >> PR_WP_OFF) & 1) << 1))
1470
Stefan Tauner5210e722012-02-16 01:13:00 +00001471/* returns 0 if range is unused (i.e. r/w) */
1472static int ich9_handle_pr(int i)
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001473{
Stefan Tauner5210e722012-02-16 01:13:00 +00001474 static const char *const access_names[3] = {
1475 "locked", "read-only", "write-only"
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001476 };
1477 uint8_t off = ICH9_REG_PR0 + (i * 4);
1478 uint32_t pr = mmio_readl(ich_spibar + off);
Stefan Tauner5210e722012-02-16 01:13:00 +00001479 unsigned int rwperms = ICH_PR_PERMS(pr);
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001480
Stefan Tauner5210e722012-02-16 01:13:00 +00001481 if (rwperms == 0x3) {
1482 msg_pdbg2("0x%02X: 0x%08x (PR%u is unused)\n", off, pr, i);
1483 return 0;
1484 }
1485
1486 msg_pdbg("0x%02X: 0x%08x ", off, pr);
1487 msg_pinfo("PR%u: WARNING: 0x%08x-0x%08x is %s.\n", i, ICH_FREG_BASE(pr),
1488 ICH_FREG_LIMIT(pr) | 0x0fff, access_names[rwperms]);
1489 return 1;
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001490}
1491
Stefan Tauner75da80c2011-09-17 22:21:55 +00001492/* Set/Clear the read and write protection enable bits of PR register @i
1493 * according to @read_prot and @write_prot. */
1494static void ich9_set_pr(int i, int read_prot, int write_prot)
1495{
1496 void *addr = ich_spibar + ICH9_REG_PR0 + (i * 4);
1497 uint32_t old = mmio_readl(addr);
1498 uint32_t new;
1499
1500 msg_gspew("PR%u is 0x%08x", i, old);
1501 new = old & ~((1 << PR_RP_OFF) | (1 << PR_WP_OFF));
1502 if (read_prot)
1503 new |= (1 << PR_RP_OFF);
1504 if (write_prot)
1505 new |= (1 << PR_WP_OFF);
1506 if (old == new) {
1507 msg_gspew(" already.\n");
1508 return;
1509 }
1510 msg_gspew(", trying to set it to 0x%08x ", new);
1511 rmmio_writel(new, addr);
1512 msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr));
1513}
1514
Michael Karcherb9dbe482011-05-11 17:07:07 +00001515static const struct spi_programmer spi_programmer_ich7 = {
1516 .type = SPI_CONTROLLER_ICH7,
1517 .max_data_read = 64,
1518 .max_data_write = 64,
1519 .command = ich_spi_send_command,
1520 .multicommand = ich_spi_send_multicommand,
1521 .read = default_spi_read,
1522 .write_256 = default_spi_write_256,
1523};
1524
1525static const struct spi_programmer spi_programmer_ich9 = {
1526 .type = SPI_CONTROLLER_ICH9,
1527 .max_data_read = 64,
1528 .max_data_write = 64,
1529 .command = ich_spi_send_command,
1530 .multicommand = ich_spi_send_multicommand,
1531 .read = default_spi_read,
1532 .write_256 = default_spi_write_256,
1533};
1534
Stefan Tauner50e7c602011-11-08 10:55:54 +00001535static const struct opaque_programmer opaque_programmer_ich_hwseq = {
1536 .max_data_read = 64,
1537 .max_data_write = 64,
1538 .probe = ich_hwseq_probe,
1539 .read = ich_hwseq_read,
1540 .write = ich_hwseq_write,
1541 .erase = ich_hwseq_block_erase,
1542};
1543
Michael Karchera4448d92010-07-22 18:04:15 +00001544int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
Stefan Taunera8d838d2011-11-06 23:51:09 +00001545 enum ich_chipset ich_gen)
Michael Karchera4448d92010-07-22 18:04:15 +00001546{
1547 int i;
1548 uint8_t old, new;
1549 uint16_t spibar_offset, tmp2;
1550 uint32_t tmp;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001551 char *arg;
Stefan Tauner5210e722012-02-16 01:13:00 +00001552 int ich_spi_force = 0;
1553 int ich_spi_rw_restricted = 0;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001554 int desc_valid = 0;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001555 struct ich_descriptors desc = {{ 0 }};
1556 enum ich_spi_mode {
1557 ich_auto,
1558 ich_hwseq,
1559 ich_swseq
1560 } ich_spi_mode = ich_auto;
Michael Karchera4448d92010-07-22 18:04:15 +00001561
Stefan Taunera8d838d2011-11-06 23:51:09 +00001562 ich_generation = ich_gen;
1563
Michael Karchera4448d92010-07-22 18:04:15 +00001564 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +00001565 case CHIPSET_ICH_UNKNOWN:
Stefan Tauner50e7c602011-11-08 10:55:54 +00001566 return ERROR_FATAL;
Stefan Taunera8d838d2011-11-06 23:51:09 +00001567 case CHIPSET_ICH7:
1568 case CHIPSET_ICH8:
Michael Karchera4448d92010-07-22 18:04:15 +00001569 spibar_offset = 0x3020;
1570 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +00001571 case CHIPSET_ICH9:
Michael Karchera4448d92010-07-22 18:04:15 +00001572 default: /* Future version might behave the same */
Michael Karchera4448d92010-07-22 18:04:15 +00001573 spibar_offset = 0x3800;
1574 break;
1575 }
1576
1577 /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
1578 msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", base, spibar_offset);
1579
1580 /* Assign Virtual Address */
1581 ich_spibar = rcrb + spibar_offset;
1582
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001583 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +00001584 case CHIPSET_ICH7:
Michael Karchera4448d92010-07-22 18:04:15 +00001585 msg_pdbg("0x00: 0x%04x (SPIS)\n",
1586 mmio_readw(ich_spibar + 0));
1587 msg_pdbg("0x02: 0x%04x (SPIC)\n",
1588 mmio_readw(ich_spibar + 2));
1589 msg_pdbg("0x04: 0x%08x (SPIA)\n",
1590 mmio_readl(ich_spibar + 4));
1591 for (i = 0; i < 8; i++) {
1592 int offs;
1593 offs = 8 + (i * 8);
1594 msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs,
1595 mmio_readl(ich_spibar + offs), i);
1596 msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
1597 mmio_readl(ich_spibar + offs + 4), i);
1598 }
1599 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
1600 msg_pdbg("0x50: 0x%08x (BBAR)\n",
1601 ichspi_bbar);
1602 msg_pdbg("0x54: 0x%04x (PREOP)\n",
1603 mmio_readw(ich_spibar + 0x54));
1604 msg_pdbg("0x56: 0x%04x (OPTYPE)\n",
1605 mmio_readw(ich_spibar + 0x56));
1606 msg_pdbg("0x58: 0x%08x (OPMENU)\n",
1607 mmio_readl(ich_spibar + 0x58));
1608 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n",
1609 mmio_readl(ich_spibar + 0x5c));
Stefan Tauner122dd122011-07-24 15:34:56 +00001610 for (i = 0; i < 3; i++) {
Michael Karchera4448d92010-07-22 18:04:15 +00001611 int offs;
1612 offs = 0x60 + (i * 4);
1613 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
1614 mmio_readl(ich_spibar + offs), i);
1615 }
Michael Karchera4448d92010-07-22 18:04:15 +00001616 if (mmio_readw(ich_spibar) & (1 << 15)) {
1617 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
1618 ichspi_lock = 1;
1619 }
Stefan Tauner745f6bb2011-11-13 15:17:10 +00001620 ich_init_opcodes();
Stefan Taunera8d838d2011-11-06 23:51:09 +00001621 ich_set_bbar(0);
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001622 register_spi_programmer(&spi_programmer_ich7);
Michael Karchera4448d92010-07-22 18:04:15 +00001623 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +00001624 case CHIPSET_ICH8:
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001625 default: /* Future version might behave the same */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001626 arg = extract_programmer_param("ich_spi_mode");
1627 if (arg && !strcmp(arg, "hwseq")) {
1628 ich_spi_mode = ich_hwseq;
1629 msg_pspew("user selected hwseq\n");
1630 } else if (arg && !strcmp(arg, "swseq")) {
1631 ich_spi_mode = ich_swseq;
1632 msg_pspew("user selected swseq\n");
1633 } else if (arg && !strcmp(arg, "auto")) {
1634 msg_pspew("user selected auto\n");
1635 ich_spi_mode = ich_auto;
1636 } else if (arg && !strlen(arg)) {
1637 msg_perr("Missing argument for ich_spi_mode.\n");
1638 free(arg);
1639 return ERROR_FATAL;
1640 } else if (arg) {
1641 msg_perr("Unknown argument for ich_spi_mode: %s\n",
1642 arg);
1643 free(arg);
1644 return ERROR_FATAL;
1645 }
1646 free(arg);
1647
Stefan Tauner5210e722012-02-16 01:13:00 +00001648 arg = extract_programmer_param("ich_spi_force");
1649 if (arg && !strcmp(arg, "yes")) {
1650 ich_spi_force = 1;
1651 msg_pspew("ich_spi_force enabled.\n");
1652 } else if (arg && !strlen(arg)) {
1653 msg_perr("Missing argument for ich_spi_force.\n");
1654 free(arg);
1655 return ERROR_FATAL;
1656 } else if (arg) {
1657 msg_perr("Unknown argument for ich_spi_force: \"%s\" "
1658 "(not \"yes\").\n", arg);
1659 free(arg);
1660 return ERROR_FATAL;
1661 }
1662 free(arg);
1663
Stefan Tauner29c80832011-06-12 08:14:10 +00001664 tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS);
Michael Karchera4448d92010-07-22 18:04:15 +00001665 msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2);
Stefan Tauner55206942011-06-11 09:53:22 +00001666 prettyprint_ich9_reg_hsfs(tmp2);
Stefan Tauner29c80832011-06-12 08:14:10 +00001667 if (tmp2 & HSFS_FLOCKDN) {
Stefan Tauner55206942011-06-11 09:53:22 +00001668 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
1669 ichspi_lock = 1;
1670 }
Stefan Tauner1e146392011-09-15 23:52:55 +00001671 if (tmp2 & HSFS_FDV)
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001672 desc_valid = 1;
1673 if (!(tmp2 & HSFS_FDOPSS) && desc_valid)
Stefan Taunere3185c02011-09-18 15:15:31 +00001674 msg_pinfo("The Flash Descriptor Security Override "
1675 "Strap-Pin is set. Restrictions implied\n"
1676 "by the FRAP and FREG registers are NOT in "
1677 "effect. Please note that Protected\n"
1678 "Range (PR) restrictions still apply.\n");
Stefan Tauner745f6bb2011-11-13 15:17:10 +00001679 ich_init_opcodes();
Stefan Tauner55206942011-06-11 09:53:22 +00001680
Stefan Taunerf382e352011-11-08 11:55:24 +00001681 if (desc_valid) {
1682 tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC);
1683 msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2);
1684 prettyprint_ich9_reg_hsfc(tmp2);
1685 }
Michael Karchera4448d92010-07-22 18:04:15 +00001686
Stefan Tauner5ffe65b2011-07-07 04:10:57 +00001687 tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR);
1688 msg_pdbg("0x08: 0x%08x (FADDR)\n", tmp);
Michael Karchera4448d92010-07-22 18:04:15 +00001689
Stefan Taunerf382e352011-11-08 11:55:24 +00001690 if (desc_valid) {
1691 tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP);
1692 msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp);
1693 msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp));
1694 msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp));
1695 msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp));
1696 msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp));
1697
Stefan Tauner5210e722012-02-16 01:13:00 +00001698 /* Handle FREGx and FRAP registers */
Stefan Taunerf382e352011-11-08 11:55:24 +00001699 for (i = 0; i < 5; i++)
Stefan Tauner5210e722012-02-16 01:13:00 +00001700 ich_spi_rw_restricted |= ich9_handle_frap(tmp, i);
Stefan Taunerf382e352011-11-08 11:55:24 +00001701 }
Michael Karchera4448d92010-07-22 18:04:15 +00001702
Stefan Tauner5210e722012-02-16 01:13:00 +00001703 for (i = 0; i < 5; i++) {
1704 /* if not locked down try to disable PR locks first */
1705 if (!ichspi_lock)
Stefan Tauner75da80c2011-09-17 22:21:55 +00001706 ich9_set_pr(i, 0, 0);
Stefan Tauner5210e722012-02-16 01:13:00 +00001707 ich_spi_rw_restricted |= ich9_handle_pr(i);
1708 }
1709
1710 if (ich_spi_rw_restricted) {
1711 msg_pinfo("Please send a verbose log to "
1712 "flashrom@flashrom.org if this board is not "
1713 "listed on\n"
1714 "http://flashrom.org/Supported_hardware#Supported_mainboards "
1715 "yet.\n");
1716 if (!ich_spi_force)
1717 programmer_may_write = 0;
1718 msg_pinfo("Writes have been disabled. You can enforce "
1719 "write support with the\nich_spi_force "
1720 "programmer option, but it will most likely "
1721 "harm your hardware!\nIf you force flashrom "
1722 "you will get no support if something "
1723 "breaks.\n");
1724 if (ich_spi_force)
1725 msg_pinfo("Continuing with write support "
1726 "because the user forced us to!\n");
1727 }
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001728
Stefan Tauner29c80832011-06-12 08:14:10 +00001729 tmp = mmio_readl(ich_spibar + ICH9_REG_SSFS);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001730 msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff);
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001731 prettyprint_ich9_reg_ssfs(tmp);
Stefan Tauner29c80832011-06-12 08:14:10 +00001732 if (tmp & SSFS_FCERR) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001733 msg_pdbg("Clearing SSFS.FCERR\n");
Stefan Tauner29c80832011-06-12 08:14:10 +00001734 mmio_writeb(SSFS_FCERR, ich_spibar + ICH9_REG_SSFS);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001735 }
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001736 msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp >> 8);
1737 prettyprint_ich9_reg_ssfc(tmp);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001738
Michael Karchera4448d92010-07-22 18:04:15 +00001739 msg_pdbg("0x94: 0x%04x (PREOP)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001740 mmio_readw(ich_spibar + ICH9_REG_PREOP));
Michael Karchera4448d92010-07-22 18:04:15 +00001741 msg_pdbg("0x96: 0x%04x (OPTYPE)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001742 mmio_readw(ich_spibar + ICH9_REG_OPTYPE));
Michael Karchera4448d92010-07-22 18:04:15 +00001743 msg_pdbg("0x98: 0x%08x (OPMENU)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001744 mmio_readl(ich_spibar + ICH9_REG_OPMENU));
Michael Karchera4448d92010-07-22 18:04:15 +00001745 msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001746 mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4));
Stefan Taunerf382e352011-11-08 11:55:24 +00001747 if (ich_generation == CHIPSET_ICH8 && desc_valid) {
Stefan Tauner1e146392011-09-15 23:52:55 +00001748 tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC);
1749 msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp);
1750 msg_pdbg("VSCC: ");
1751 prettyprint_ich_reg_vscc(tmp, MSG_DEBUG);
1752 } else {
1753 ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR);
1754 msg_pdbg("0xA0: 0x%08x (BBAR)\n",
1755 ichspi_bbar);
Stefan Taunerbd649e42011-07-01 00:39:16 +00001756
Stefan Taunerf382e352011-11-08 11:55:24 +00001757 if (desc_valid) {
1758 tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC);
1759 msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp);
1760 msg_pdbg("LVSCC: ");
1761 prettyprint_ich_reg_vscc(tmp, MSG_DEBUG);
Stefan Tauner1e146392011-09-15 23:52:55 +00001762
Stefan Taunerf382e352011-11-08 11:55:24 +00001763 tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC);
1764 msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp);
1765 msg_pdbg("UVSCC: ");
1766 prettyprint_ich_reg_vscc(tmp, MSG_DEBUG);
Stefan Tauner1e146392011-09-15 23:52:55 +00001767
Stefan Taunerf382e352011-11-08 11:55:24 +00001768 tmp = mmio_readl(ich_spibar + ICH9_REG_FPB);
1769 msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp);
1770 }
Stefan Taunera8d838d2011-11-06 23:51:09 +00001771 ich_set_bbar(0);
Stefan Tauner1e146392011-09-15 23:52:55 +00001772 }
1773
1774 msg_pdbg("\n");
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001775 if (desc_valid) {
Stefan Tauner1e146392011-09-15 23:52:55 +00001776 if (read_ich_descriptors_via_fdo(ich_spibar, &desc) ==
1777 ICH_RET_OK)
1778 prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN,
1779 &desc);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001780 /* If the descriptor is valid and indicates multiple
1781 * flash devices we need to use hwseq to be able to
1782 * access the second flash device.
1783 */
1784 if (ich_spi_mode == ich_auto && desc.content.NC != 0) {
1785 msg_pinfo("Enabling hardware sequencing due to "
1786 "multiple flash chips detected.\n");
1787 ich_spi_mode = ich_hwseq;
1788 }
Stefan Tauner1e146392011-09-15 23:52:55 +00001789 }
Stefan Tauner50e7c602011-11-08 10:55:54 +00001790
1791 if (ich_spi_mode == ich_auto && ichspi_lock &&
1792 ich_missing_opcodes()) {
1793 msg_pinfo("Enabling hardware sequencing because "
1794 "some important opcode is locked.\n");
1795 ich_spi_mode = ich_hwseq;
1796 }
1797
1798 if (ich_spi_mode == ich_hwseq) {
1799 if (!desc_valid) {
1800 msg_perr("Hardware sequencing was requested "
1801 "but the flash descriptor is not "
1802 "valid. Aborting.\n");
1803 return ERROR_FATAL;
1804 }
1805 hwseq_data.size_comp0 = getFCBA_component_density(&desc, 0);
1806 hwseq_data.size_comp1 = getFCBA_component_density(&desc, 1);
1807 register_opaque_programmer(&opaque_programmer_ich_hwseq);
1808 } else {
1809 register_spi_programmer(&spi_programmer_ich9);
1810 }
Michael Karchera4448d92010-07-22 18:04:15 +00001811 break;
Michael Karchera4448d92010-07-22 18:04:15 +00001812 }
1813
1814 old = pci_read_byte(dev, 0xdc);
1815 msg_pdbg("SPI Read Configuration: ");
1816 new = (old >> 2) & 0x3;
1817 switch (new) {
1818 case 0:
1819 case 1:
1820 case 2:
1821 msg_pdbg("prefetching %sabled, caching %sabled, ",
1822 (new & 0x2) ? "en" : "dis",
1823 (new & 0x1) ? "dis" : "en");
1824 break;
1825 default:
1826 msg_pdbg("invalid prefetching/caching settings, ");
1827 break;
1828 }
1829 return 0;
1830}
1831
Michael Karcherb9dbe482011-05-11 17:07:07 +00001832static const struct spi_programmer spi_programmer_via = {
1833 .type = SPI_CONTROLLER_VIA,
1834 .max_data_read = 16,
1835 .max_data_write = 16,
1836 .command = ich_spi_send_command,
1837 .multicommand = ich_spi_send_multicommand,
1838 .read = default_spi_read,
1839 .write_256 = default_spi_write_256,
1840};
1841
Michael Karchera4448d92010-07-22 18:04:15 +00001842int via_init_spi(struct pci_dev *dev)
1843{
1844 uint32_t mmio_base;
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00001845 int i;
Michael Karchera4448d92010-07-22 18:04:15 +00001846
1847 mmio_base = (pci_read_long(dev, 0xbc)) << 8;
1848 msg_pdbg("MMIO base at = 0x%x\n", mmio_base);
1849 ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70);
1850
Michael Karchera4448d92010-07-22 18:04:15 +00001851 /* Not sure if it speaks all these bus protocols. */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001852 internal_buses_supported = BUS_LPC | BUS_FWH;
Stefan Taunera8d838d2011-11-06 23:51:09 +00001853 ich_generation = CHIPSET_ICH7;
Michael Karcherb9dbe482011-05-11 17:07:07 +00001854 register_spi_programmer(&spi_programmer_via);
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00001855
1856 msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0));
1857 msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2));
1858 msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(ich_spibar + 4));
1859 for (i = 0; i < 2; i++) {
1860 int offs;
1861 offs = 8 + (i * 8);
1862 msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs,
1863 mmio_readl(ich_spibar + offs), i);
1864 msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
1865 mmio_readl(ich_spibar + offs + 4), i);
1866 }
1867 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
1868 msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar);
1869 msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x54));
1870 msg_pdbg("0x56: 0x%04x (OPTYPE)\n", mmio_readw(ich_spibar + 0x56));
1871 msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(ich_spibar + 0x58));
1872 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + 0x5c));
1873 for (i = 0; i < 3; i++) {
1874 int offs;
1875 offs = 0x60 + (i * 4);
1876 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
1877 mmio_readl(ich_spibar + offs), i);
1878 }
1879 msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n",
1880 mmio_readw(ich_spibar + 0x6c));
1881 if (mmio_readw(ich_spibar) & (1 << 15)) {
1882 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
1883 ichspi_lock = 1;
1884 }
1885
Stefan Taunera8d838d2011-11-06 23:51:09 +00001886 ich_set_bbar(0);
Michael Karchera4448d92010-07-22 18:04:15 +00001887 ich_init_opcodes();
1888
1889 return 0;
1890}
1891
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001892#endif