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Ollie Lho184a4042005-11-26 21:55:36 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ollie Lho184a4042005-11-26 21:55:36 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Stefan Reinauer8fa64812009-08-12 09:27:45 +00005 * Copyright (C) 2005-2009 coresystems GmbH
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00007 * Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger
Adam Jurkowskie4984102009-12-21 15:30:46 +00008 * Copyright (C) 2009 Kontron Modular Computers GmbH
Ollie Lho184a4042005-11-26 21:55:36 +00009 *
Uwe Hermannd1107642007-08-29 17:52:32 +000010 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
Ollie Lho184a4042005-11-26 21:55:36 +000013 *
Uwe Hermannd1107642007-08-29 17:52:32 +000014 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24/*
25 * Contains the chipset specific flash enables.
Ollie Lho184a4042005-11-26 21:55:36 +000026 */
27
Lane Brooksd54958a2007-11-13 16:45:22 +000028#define _LARGEFILE64_SOURCE
29
Ollie Lhocbbf1252004-03-17 22:22:08 +000030#include <stdlib.h>
Uwe Hermanne8ba5382009-05-22 11:37:27 +000031#include <string.h>
Carl-Daniel Hailfingerdcef67e2010-06-21 23:20:15 +000032#include <unistd.h>
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +000033#include <inttypes.h>
34#include <errno.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000035#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000036#include "programmer.h"
Stefan Reinauer86de2832006-03-31 11:26:55 +000037
Michael Karcher89bed6d2010-06-13 10:16:12 +000038#define NOT_DONE_YET 1
39
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +000040#if defined(__i386__) || defined(__x86_64__)
41
Uwe Hermann372eeb52007-12-04 21:49:06 +000042static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
Luc Verhaegen6b141752007-05-20 16:16:13 +000043{
44 uint8_t tmp;
45
Uwe Hermann372eeb52007-12-04 21:49:06 +000046 /*
47 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
48 * 0xFFFE0000-0xFFFFFFFF ROM select enable.
49 */
Luc Verhaegen6b141752007-05-20 16:16:13 +000050 tmp = pci_read_byte(dev, 0x47);
51 tmp |= 0x46;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000052 rpci_write_byte(dev, 0x47, tmp);
Luc Verhaegen6b141752007-05-20 16:16:13 +000053
54 return 0;
55}
56
Rudolf Marek23907d82012-02-07 21:29:48 +000057static int enable_flash_rdc_r8610(struct pci_dev *dev, const char *name)
58{
59 uint8_t tmp;
60
61 /* enable ROMCS for writes */
62 tmp = pci_read_byte(dev, 0x43);
63 tmp |= 0x80;
64 pci_write_byte(dev, 0x43, tmp);
65
66 /* read the bootstrapping register */
67 tmp = pci_read_byte(dev, 0x40) & 0x3;
68 switch (tmp) {
69 case 3:
70 internal_buses_supported = BUS_FWH;
71 break;
72 case 2:
73 internal_buses_supported = BUS_LPC;
74 break;
75 default:
76 internal_buses_supported = BUS_PARALLEL;
77 break;
78 }
79
80 return 0;
81}
82
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000083static int enable_flash_sis85c496(struct pci_dev *dev, const char *name)
84{
85 uint8_t tmp;
86
87 tmp = pci_read_byte(dev, 0xd0);
88 tmp |= 0xf8;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000089 rpci_write_byte(dev, 0xd0, tmp);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000090
91 return 0;
92}
93
94static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name)
95{
96 uint8_t new, newer;
97
98 /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
99 /* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
100 new = pci_read_byte(dev, 0x40);
101 new &= (~0x04); /* No idea why we clear bit 2. */
102 new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000103 rpci_write_byte(dev, 0x40, new);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000104 newer = pci_read_byte(dev, 0x40);
105 if (newer != new) {
Stefan Tauneraf882e72011-08-04 17:37:58 +0000106 msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
107 "(WARNING ONLY).\n", 0x40, new, name);
Sean Nelson316a29f2010-05-07 20:09:04 +0000108 msg_pinfo("Stuck at 0x%x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000109 return -1;
110 }
111 return 0;
112}
113
114static struct pci_dev *find_southbridge(uint16_t vendor, const char *name)
115{
116 struct pci_dev *sbdev;
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000117
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000118 sbdev = pci_dev_find_vendorclass(vendor, 0x0601);
119 if (!sbdev)
120 sbdev = pci_dev_find_vendorclass(vendor, 0x0680);
121 if (!sbdev)
122 sbdev = pci_dev_find_vendorclass(vendor, 0x0000);
123 if (!sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +0000124 msg_perr("No southbridge found for %s!\n", name);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000125 if (sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +0000126 msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000127 sbdev->vendor_id, sbdev->device_id,
128 sbdev->bus, sbdev->dev, sbdev->func);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000129 return sbdev;
130}
131
132static int enable_flash_sis501(struct pci_dev *dev, const char *name)
133{
134 uint8_t tmp;
135 int ret = 0;
136 struct pci_dev *sbdev;
137
138 sbdev = find_southbridge(dev->vendor_id, name);
139 if (!sbdev)
140 return -1;
141
142 ret = enable_flash_sis_mapping(sbdev, name);
143
144 tmp = sio_read(0x22, 0x80);
145 tmp &= (~0x20);
146 tmp |= 0x4;
147 sio_write(0x22, 0x80, tmp);
148
149 tmp = sio_read(0x22, 0x70);
150 tmp &= (~0x20);
151 tmp |= 0x4;
152 sio_write(0x22, 0x70, tmp);
153
154 return ret;
155}
156
157static int enable_flash_sis5511(struct pci_dev *dev, const char *name)
158{
159 uint8_t tmp;
160 int ret = 0;
161 struct pci_dev *sbdev;
162
163 sbdev = find_southbridge(dev->vendor_id, name);
164 if (!sbdev)
165 return -1;
166
167 ret = enable_flash_sis_mapping(sbdev, name);
168
169 tmp = sio_read(0x22, 0x50);
170 tmp &= (~0x20);
171 tmp |= 0x4;
172 sio_write(0x22, 0x50, tmp);
173
174 return ret;
175}
176
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000177static int enable_flash_sis530(struct pci_dev *dev, const char *name)
178{
179 uint8_t new, newer;
180 int ret = 0;
181 struct pci_dev *sbdev;
182
183 sbdev = find_southbridge(dev->vendor_id, name);
184 if (!sbdev)
185 return -1;
186
187 ret = enable_flash_sis_mapping(sbdev, name);
188
189 new = pci_read_byte(sbdev, 0x45);
190 new &= (~0x20);
191 new |= 0x4;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000192 rpci_write_byte(sbdev, 0x45, new);
Luc Verhaegen9cce2f52010-01-10 15:01:08 +0000193 newer = pci_read_byte(sbdev, 0x45);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000194 if (newer != new) {
Stefan Tauneraf882e72011-08-04 17:37:58 +0000195 msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
196 "(WARNING ONLY).\n", 0x45, new, name);
Sean Nelson316a29f2010-05-07 20:09:04 +0000197 msg_pinfo("Stuck at 0x%x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000198 ret = -1;
199 }
200
201 return ret;
202}
203
204static int enable_flash_sis540(struct pci_dev *dev, const char *name)
205{
206 uint8_t new, newer;
207 int ret = 0;
208 struct pci_dev *sbdev;
209
210 sbdev = find_southbridge(dev->vendor_id, name);
211 if (!sbdev)
212 return -1;
213
214 ret = enable_flash_sis_mapping(sbdev, name);
215
216 new = pci_read_byte(sbdev, 0x45);
217 new &= (~0x80);
218 new |= 0x40;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000219 rpci_write_byte(sbdev, 0x45, new);
Luc Verhaegen9cce2f52010-01-10 15:01:08 +0000220 newer = pci_read_byte(sbdev, 0x45);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000221 if (newer != new) {
Stefan Tauneraf882e72011-08-04 17:37:58 +0000222 msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
223 "(WARNING ONLY).\n", 0x45, new, name);
Sean Nelson316a29f2010-05-07 20:09:04 +0000224 msg_pinfo("Stuck at 0x%x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000225 ret = -1;
226 }
227
228 return ret;
229}
230
Uwe Hermann987942d2006-11-07 11:16:21 +0000231/* Datasheet:
232 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
233 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
234 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
235 * - Order Number: 290562-001
236 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000237static int enable_flash_piix4(struct pci_dev *dev, const char *name)
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000238{
239 uint16_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000240 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000241
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000242 internal_buses_supported = BUS_PARALLEL;
Maciej Pijankaa661e152009-12-08 17:26:24 +0000243
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000244 old = pci_read_word(dev, xbcs);
245
246 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
Uwe Hermanna7e05482007-05-09 10:17:44 +0000247 * FFF00000-FFF7FFFF are forwarded to ISA).
Uwe Hermannc556d322008-10-28 11:50:05 +0000248 * Note: This bit is reserved on PIIX/PIIX3/MPIIX.
Uwe Hermanna7e05482007-05-09 10:17:44 +0000249 * Set bit 7: Extended BIOS Enable (PCI master accesses to
250 * FFF80000-FFFDFFFF are forwarded to ISA).
251 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
252 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
253 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
254 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
255 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
256 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
257 */
Uwe Hermannc556d322008-10-28 11:50:05 +0000258 if (dev->device_id == 0x122e || dev->device_id == 0x7000
259 || dev->device_id == 0x1234)
260 new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
Uwe Hermann87203452008-10-26 18:40:42 +0000261 else
262 new = old | 0x02c4;
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000263
264 if (new == old)
265 return 0;
266
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000267 rpci_write_word(dev, xbcs, new);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000268
269 if (pci_read_word(dev, xbcs) != new) {
Stefan Tauneraf882e72011-08-04 17:37:58 +0000270 msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
271 "(WARNING ONLY).\n", xbcs, new, name);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000272 return -1;
273 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000274
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000275 return 0;
276}
277
Uwe Hermann372eeb52007-12-04 21:49:06 +0000278/*
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000279 * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet"
280 * http://download.intel.com/design/chipsets/datashts/30701303.pdf
Uwe Hermann372eeb52007-12-04 21:49:06 +0000281 */
282static int enable_flash_ich(struct pci_dev *dev, const char *name,
283 int bios_cntl)
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000284{
Stefan Taunerd5c4ab42011-09-09 12:46:32 +0000285 uint8_t old, new, wanted;
Stefan Reinauereb366472006-09-06 15:48:48 +0000286
Uwe Hermann372eeb52007-12-04 21:49:06 +0000287 /*
288 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
Uwe Hermanna7e05482007-05-09 10:17:44 +0000289 * just treating it as 8 bit wide seems to work fine in practice.
Stefan Reinauereb366472006-09-06 15:48:48 +0000290 */
Stefan Reinauer86de2832006-03-31 11:26:55 +0000291 old = pci_read_byte(dev, bios_cntl);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000292
Sean Nelson316a29f2010-05-07 20:09:04 +0000293 msg_pdbg("\nBIOS Lock Enable: %sabled, ",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000294 (old & (1 << 1)) ? "en" : "dis");
Sean Nelson316a29f2010-05-07 20:09:04 +0000295 msg_pdbg("BIOS Write Enable: %sabled, ",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000296 (old & (1 << 0)) ? "en" : "dis");
Sean Nelson316a29f2010-05-07 20:09:04 +0000297 msg_pdbg("BIOS_CNTL is 0x%x\n", old);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000298
Stefan Taunerf9a8da52011-06-11 18:16:50 +0000299 /*
300 * Quote from the 6 Series datasheet (Document Number: 324645-004):
301 * "Bit 5: SMM BIOS Write Protect Disable (SMM_BWP)
302 * 1 = BIOS region SMM protection is enabled.
303 * The BIOS Region is not writable unless all processors are in SMM."
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000304 * In earlier chipsets this bit is reserved.
305 */
306 if (old & (1 << 5))
Stefan Taunerf9a8da52011-06-11 18:16:50 +0000307 msg_pinfo("WARNING: BIOS region SMM protection is enabled!\n");
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000308
Stefan Taunerd5c4ab42011-09-09 12:46:32 +0000309 wanted = old | 1;
310 if (wanted == old)
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000311 return 0;
312
Stefan Taunerd5c4ab42011-09-09 12:46:32 +0000313 rpci_write_byte(dev, bios_cntl, wanted);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000314
Stefan Taunerd5c4ab42011-09-09 12:46:32 +0000315 if ((new = pci_read_byte(dev, bios_cntl)) != wanted) {
316 msg_pinfo("WARNING: Setting 0x%x from 0x%x to 0x%x on %s "
317 "failed. New value is 0x%x.\n",
318 bios_cntl, old, wanted, name, new);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000319 return -1;
320 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000321
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000322 return 0;
323}
324
Uwe Hermann372eeb52007-12-04 21:49:06 +0000325static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000326{
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000327 /*
328 * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and
329 * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and
330 * FB_DEC_EN2.
331 */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000332 internal_buses_supported = BUS_FWH;
Stefan Reinauereb366472006-09-06 15:48:48 +0000333 return enable_flash_ich(dev, name, 0x4e);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000334}
335
Uwe Hermann372eeb52007-12-04 21:49:06 +0000336static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000337{
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000338 uint32_t fwh_conf;
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +0000339 int i, tmp;
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000340 char *idsel = NULL;
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +0000341 int max_decode_fwh_idsel = 0, max_decode_fwh_decode = 0;
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000342 int contiguous = 1;
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000343
Carl-Daniel Hailfinger2b6dcb32010-07-08 10:13:37 +0000344 idsel = extract_programmer_param("fwh_idsel");
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000345 if (idsel && strlen(idsel)) {
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000346 uint64_t fwh_idsel_old, fwh_idsel;
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000347 errno = 0;
348 /* Base 16, nothing else makes sense. */
349 fwh_idsel = (uint64_t)strtoull(idsel, NULL, 16);
350 if (errno) {
351 msg_perr("Error: fwh_idsel= specified, but value could "
352 "not be converted.\n");
353 goto idsel_garbage_out;
354 }
355 if (fwh_idsel & 0xffff000000000000ULL) {
356 msg_perr("Error: fwh_idsel= specified, but value had "
Sylvain "ythier" Hitier3093f8f2011-09-03 11:22:27 +0000357 "unused bits set.\n");
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000358 goto idsel_garbage_out;
359 }
360 fwh_idsel_old = pci_read_long(dev, 0xd0);
361 fwh_idsel_old <<= 16;
362 fwh_idsel_old |= pci_read_word(dev, 0xd4);
363 msg_pdbg("\nSetting IDSEL from 0x%012" PRIx64 " to "
364 "0x%012" PRIx64 " for top 16 MB.", fwh_idsel_old,
365 fwh_idsel);
366 rpci_write_long(dev, 0xd0, (fwh_idsel >> 16) & 0xffffffff);
367 rpci_write_word(dev, 0xd4, fwh_idsel & 0xffff);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000368 /* FIXME: Decode settings are not changed. */
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000369 } else if (idsel) {
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000370 msg_perr("Error: fwh_idsel= specified, but no value given.\n");
Sylvain "ythier" Hitier3093f8f2011-09-03 11:22:27 +0000371idsel_garbage_out:
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000372 free(idsel);
Tadas Slotkus0e3f1cf2011-09-06 18:49:31 +0000373 return ERROR_FATAL;
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000374 }
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000375 free(idsel);
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000376
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000377 /* Ignore all legacy ranges below 1 MB.
378 * We currently only support flashing the chip which responds to
379 * IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations
380 * have to be adjusted.
381 */
382 /* FWH_SEL1 */
383 fwh_conf = pci_read_long(dev, 0xd0);
384 for (i = 7; i >= 0; i--) {
385 tmp = (fwh_conf >> (i * 4)) & 0xf;
Sean Nelson316a29f2010-05-07 20:09:04 +0000386 msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000387 (0x1ff8 + i) * 0x80000,
388 (0x1ff0 + i) * 0x80000,
389 tmp);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000390 if ((tmp == 0) && contiguous) {
391 max_decode_fwh_idsel = (8 - i) * 0x80000;
392 } else {
393 contiguous = 0;
394 }
395 }
396 /* FWH_SEL2 */
397 fwh_conf = pci_read_word(dev, 0xd4);
398 for (i = 3; i >= 0; i--) {
399 tmp = (fwh_conf >> (i * 4)) & 0xf;
Sean Nelson316a29f2010-05-07 20:09:04 +0000400 msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000401 (0xff4 + i) * 0x100000,
402 (0xff0 + i) * 0x100000,
403 tmp);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000404 if ((tmp == 0) && contiguous) {
405 max_decode_fwh_idsel = (8 - i) * 0x100000;
406 } else {
407 contiguous = 0;
408 }
409 }
410 contiguous = 1;
411 /* FWH_DEC_EN1 */
412 fwh_conf = pci_read_word(dev, 0xd8);
413 for (i = 7; i >= 0; i--) {
414 tmp = (fwh_conf >> (i + 0x8)) & 0x1;
Sean Nelson316a29f2010-05-07 20:09:04 +0000415 msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000416 (0x1ff8 + i) * 0x80000,
417 (0x1ff0 + i) * 0x80000,
418 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000419 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000420 max_decode_fwh_decode = (8 - i) * 0x80000;
421 } else {
422 contiguous = 0;
423 }
424 }
425 for (i = 3; i >= 0; i--) {
426 tmp = (fwh_conf >> i) & 0x1;
Sean Nelson316a29f2010-05-07 20:09:04 +0000427 msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000428 (0xff4 + i) * 0x100000,
429 (0xff0 + i) * 0x100000,
430 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000431 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000432 max_decode_fwh_decode = (8 - i) * 0x100000;
433 } else {
434 contiguous = 0;
435 }
436 }
437 max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode);
Sean Nelson316a29f2010-05-07 20:09:04 +0000438 msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000439
440 /* If we're called by enable_flash_ich_dc_spi, it will override
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000441 * internal_buses_supported anyway.
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000442 */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000443 internal_buses_supported = BUS_FWH;
Stefan Reinauereb366472006-09-06 15:48:48 +0000444 return enable_flash_ich(dev, name, 0xdc);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000445}
446
Adam Jurkowskie4984102009-12-21 15:30:46 +0000447static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
448{
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000449 uint16_t old, new;
450 int err;
Adam Jurkowskie4984102009-12-21 15:30:46 +0000451
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000452 if ((err = enable_flash_ich(dev, name, 0xd8)) != 0)
453 return err;
Adam Jurkowskie4984102009-12-21 15:30:46 +0000454
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000455 old = pci_read_byte(dev, 0xd9);
456 msg_pdbg("BIOS Prefetch Enable: %sabled, ",
457 (old & 1) ? "en" : "dis");
458 new = old & ~1;
Adam Jurkowskie4984102009-12-21 15:30:46 +0000459
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000460 if (new != old)
461 rpci_write_byte(dev, 0xd9, new);
Adam Jurkowskie4984102009-12-21 15:30:46 +0000462
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000463 internal_buses_supported = BUS_FWH;
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000464 return 0;
Adam Jurkowskie4984102009-12-21 15:30:46 +0000465}
466
Ingo Feldschmiddadc0a62011-09-07 19:18:25 +0000467static int enable_flash_tunnelcreek(struct pci_dev *dev, const char *name)
468{
469 uint16_t old, new;
470 uint32_t tmp, bnt;
471 void *rcrb;
472 int ret;
473
474 /* Enable Flash Writes */
475 ret = enable_flash_ich(dev, name, 0xd8);
476 if (ret == ERROR_FATAL)
477 return ret;
478
479 /* Make sure BIOS prefetch mechanism is disabled */
480 old = pci_read_byte(dev, 0xd9);
481 msg_pdbg("BIOS Prefetch Enable: %sabled, ", (old & 1) ? "en" : "dis");
482 new = old & ~1;
483 if (new != old)
484 rpci_write_byte(dev, 0xd9, new);
485
486 /* Get physical address of Root Complex Register Block */
487 tmp = pci_read_long(dev, 0xf0) & 0xffffc000;
488 msg_pdbg("\nRoot Complex Register Block address = 0x%x\n", tmp);
489
490 /* Map RCBA to virtual memory */
491 rcrb = physmap("ICH RCRB", tmp, 0x4000);
492
493 /* Test Boot BIOS Strap Status */
494 bnt = mmio_readl(rcrb + 0x3410);
495 if (bnt & 0x02) {
496 /* If strapped to LPC, no SPI initialization is required */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000497 internal_buses_supported = BUS_FWH;
Ingo Feldschmiddadc0a62011-09-07 19:18:25 +0000498 return 0;
499 }
500
501 /* This adds BUS_SPI */
Ingo Feldschmiddadc0a62011-09-07 19:18:25 +0000502 if (ich_init_spi(dev, tmp, rcrb, 7) != 0) {
503 if (!ret)
504 ret = ERROR_NONFATAL;
505 }
506
507 return ret;
508}
509
Uwe Hermann394131e2008-10-18 21:14:13 +0000510static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
511{
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000512 /* Do we really need no write enable? */
Michael Karchera4448d92010-07-22 18:04:15 +0000513 return via_init_spi(dev);
Joshua Roysf93b36a2010-07-01 17:45:54 +0000514}
515
Uwe Hermann394131e2008-10-18 21:14:13 +0000516static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
Stefan Taunera8d838d2011-11-06 23:51:09 +0000517 enum ich_chipset ich_generation)
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000518{
Stefan Tauner50e7c602011-11-08 10:55:54 +0000519 int ret, ret_spi;
Michael Karchera4448d92010-07-22 18:04:15 +0000520 uint8_t bbs, buc;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000521 uint32_t tmp, gcs;
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000522 void *rcrb;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000523 const char *const *straps_names;
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000524
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000525 static const char *const straps_names_EP80579[] = { "SPI", "reserved", "reserved", "LPC" };
526 static const char *const straps_names_ich7_nm10[] = { "reserved", "SPI", "PCI", "LPC" };
527 static const char *const straps_names_ich8910[] = { "SPI", "SPI", "PCI", "LPC" };
528 static const char *const straps_names_pch56[] = { "LPC", "reserved", "PCI", "SPI" };
529 static const char *const straps_names_unknown[] = { "unknown", "unknown", "unknown", "unknown" };
530
531 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +0000532 case CHIPSET_ICH7:
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000533 /* EP80579 may need further changes, but this is the least
534 * intrusive way to get correct BOOT Strap printing without
535 * changing the rest of its code path). */
536 if (strcmp(name, "EP80579") == 0)
537 straps_names = straps_names_EP80579;
538 else
539 straps_names = straps_names_ich7_nm10;
540 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000541 case CHIPSET_ICH8:
542 case CHIPSET_ICH9:
543 case CHIPSET_ICH10:
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000544 straps_names = straps_names_ich8910;
545 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000546 case CHIPSET_5_SERIES_IBEX_PEAK:
547 case CHIPSET_6_SERIES_COUGAR_POINT:
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000548 straps_names = straps_names_pch56;
549 break;
550 default:
551 msg_gerr("%s: unknown ICH generation. Please report!\n",
552 __func__);
553 straps_names = straps_names_unknown;
554 break;
555 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000556
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000557 /* Enable Flash Writes */
558 ret = enable_flash_ich_dc(dev, name);
Tadas Slotkus0e3f1cf2011-09-06 18:49:31 +0000559 if (ret == ERROR_FATAL)
560 return ret;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000561
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000562 /* Get physical address of Root Complex Register Block */
563 tmp = pci_read_long(dev, 0xf0) & 0xffffc000;
Paul Menzel018d4822011-10-21 12:33:07 +0000564 msg_pdbg("Root Complex Register Block address = 0x%x\n", tmp);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000565
566 /* Map RCBA to virtual memory */
Stefan Reinauer0593f212009-01-26 01:10:48 +0000567 rcrb = physmap("ICH RCRB", tmp, 0x4000);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000568
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000569 gcs = mmio_readl(rcrb + 0x3410);
Sean Nelson316a29f2010-05-07 20:09:04 +0000570 msg_pdbg("GCS = 0x%x: ", gcs);
571 msg_pdbg("BIOS Interface Lock-Down: %sabled, ",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000572 (gcs & 0x1) ? "en" : "dis");
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000573 bbs = (gcs >> 10) & 0x3;
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000574 msg_pdbg("Boot BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000575
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000576 buc = mmio_readb(rcrb + 0x3414);
Sean Nelson316a29f2010-05-07 20:09:04 +0000577 msg_pdbg("Top Swap : %s\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000578 (buc & 1) ? "enabled (A16 inverted)" : "not enabled");
Stefan Reinauera9424d52008-06-27 16:28:34 +0000579
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000580 /* It seems the ICH7 does not support SPI and LPC chips at the same
581 * time. At least not with our current code. So we prevent searching
582 * on ICH7 when the southbridge is strapped to LPC
583 */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000584 internal_buses_supported = BUS_FWH;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000585 if (ich_generation == CHIPSET_ICH7) {
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000586 if (bbs == 0x03) {
587 /* If strapped to LPC, no further SPI initialization is
588 * required. */
Michael Karchera4448d92010-07-22 18:04:15 +0000589 return ret;
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000590 } else {
Michael Karchera4448d92010-07-22 18:04:15 +0000591 /* Disable LPC/FWH if strapped to PCI or SPI */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000592 internal_buses_supported = BUS_NONE;
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000593 }
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000594 }
595
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000596 /* This adds BUS_SPI */
Stefan Tauner50e7c602011-11-08 10:55:54 +0000597 ret_spi = ich_init_spi(dev, tmp, rcrb, ich_generation);
598 if (ret_spi == ERROR_FATAL)
599 return ret_spi;
600
601 if (ret || ret_spi)
602 ret = ERROR_NONFATAL;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000603
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000604 return ret;
605}
Stefan Reinauera9424d52008-06-27 16:28:34 +0000606
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000607static int enable_flash_ich7(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000608{
Stefan Taunera8d838d2011-11-06 23:51:09 +0000609 return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH7);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000610}
611
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000612static int enable_flash_ich8(struct pci_dev *dev, const char *name)
613{
Stefan Taunera8d838d2011-11-06 23:51:09 +0000614 return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH8);
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000615}
616
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000617static int enable_flash_ich9(struct pci_dev *dev, const char *name)
618{
Stefan Taunera8d838d2011-11-06 23:51:09 +0000619 return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH9);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000620}
621
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000622static int enable_flash_ich10(struct pci_dev *dev, const char *name)
623{
Stefan Taunera8d838d2011-11-06 23:51:09 +0000624 return enable_flash_ich_dc_spi(dev, name, CHIPSET_ICH10);
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000625}
626
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000627/* Ibex Peak aka. 5 series & 3400 series */
628static int enable_flash_pch5(struct pci_dev *dev, const char *name)
629{
Stefan Taunera8d838d2011-11-06 23:51:09 +0000630 return enable_flash_ich_dc_spi(dev, name, CHIPSET_5_SERIES_IBEX_PEAK);
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000631}
632
633/* Cougar Point aka. 6 series & c200 series */
634static int enable_flash_pch6(struct pci_dev *dev, const char *name)
635{
Stefan Taunera8d838d2011-11-06 23:51:09 +0000636 return enable_flash_ich_dc_spi(dev, name, CHIPSET_6_SERIES_COUGAR_POINT);
Stefan Taunerbd0c70a2011-08-27 21:19:56 +0000637}
638
Michael Karcher89bed6d2010-06-13 10:16:12 +0000639static int via_no_byte_merge(struct pci_dev *dev, const char *name)
640{
641 uint8_t val;
642
643 val = pci_read_byte(dev, 0x71);
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000644 if (val & 0x40) {
Michael Karcher89bed6d2010-06-13 10:16:12 +0000645 msg_pdbg("Disabling byte merging\n");
646 val &= ~0x40;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000647 rpci_write_byte(dev, 0x71, val);
Michael Karcher89bed6d2010-06-13 10:16:12 +0000648 }
649 return NOT_DONE_YET; /* need to find south bridge, too */
650}
651
Uwe Hermann372eeb52007-12-04 21:49:06 +0000652static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000653{
Ollie Lho184a4042005-11-26 21:55:36 +0000654 uint8_t val;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000655
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000656 /* Enable ROM decode range (1MB) FFC00000 - FFFFFFFF. */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000657 rpci_write_byte(dev, 0x41, 0x7f);
Bari Ari9477c4e2008-04-29 13:46:38 +0000658
Uwe Hermannffec5f32007-08-23 16:08:21 +0000659 /* ROM write enable */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000660 val = pci_read_byte(dev, 0x40);
661 val |= 0x10;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000662 rpci_write_byte(dev, 0x40, val);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000663
664 if (pci_read_byte(dev, 0x40) != val) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000665 msg_pinfo("\nWARNING: Failed to enable flash write on \"%s\"\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000666 name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000667 return -1;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000668 }
Luc Verhaegen6382b442007-03-02 22:16:38 +0000669
Luc Verhaegen73d21192009-12-23 00:54:26 +0000670 if (dev->device_id == 0x3227) { /* VT8237R */
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000671 /* All memory cycles, not just ROM ones, go to LPC. */
672 val = pci_read_byte(dev, 0x59);
673 val &= ~0x80;
674 rpci_write_byte(dev, 0x59, val);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000675 }
676
Uwe Hermanna7e05482007-05-09 10:17:44 +0000677 return 0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000678}
679
Uwe Hermann372eeb52007-12-04 21:49:06 +0000680static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000681{
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000682 uint8_t reg8;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000683
Uwe Hermann394131e2008-10-18 21:14:13 +0000684#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
685#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000686#define CS5530_RESET_CONTROL_REG 0x44 /* F0 index 0x44 */
687#define CS5530_USB_SHADOW_REG 0x43 /* F0 index 0x43 */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000688
Uwe Hermann394131e2008-10-18 21:14:13 +0000689#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
690#define ROM_WRITE_ENABLE (1 << 1)
691#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
692#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000693#define CS5530_ISA_MASTER (1 << 7)
694#define CS5530_ENABLE_SA2320 (1 << 2)
695#define CS5530_ENABLE_SA20 (1 << 6)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000696
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000697 internal_buses_supported = BUS_PARALLEL;
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000698 /* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and
699 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB.
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000700 * FIXME: Should we really touch the low mapping below 1 MB? Flashrom
701 * ignores that region completely.
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000702 * Make the configured ROM areas writable.
703 */
704 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
705 reg8 |= LOWER_ROM_ADDRESS_RANGE;
706 reg8 |= UPPER_ROM_ADDRESS_RANGE;
707 reg8 |= ROM_WRITE_ENABLE;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000708 rpci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000709
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000710 /* Set positive decode on ROM. */
711 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
712 reg8 |= BIOS_ROM_POSITIVE_DECODE;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000713 rpci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000714
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000715 reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG);
716 if (reg8 & CS5530_ISA_MASTER) {
717 /* We have A0-A23 available. */
718 max_rom_decode.parallel = 16 * 1024 * 1024;
719 } else {
720 reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG);
721 if (reg8 & CS5530_ENABLE_SA2320) {
722 /* We have A0-19, A20-A23 available. */
723 max_rom_decode.parallel = 16 * 1024 * 1024;
724 } else if (reg8 & CS5530_ENABLE_SA20) {
725 /* We have A0-19, A20 available. */
726 max_rom_decode.parallel = 2 * 1024 * 1024;
727 } else {
728 /* A20 and above are not active. */
729 max_rom_decode.parallel = 1024 * 1024;
730 }
731 }
732
Ollie Lhocbbf1252004-03-17 22:22:08 +0000733 return 0;
734}
735
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000736/*
Mart Raudseppe1344da2008-02-08 10:10:57 +0000737 * Geode systems write protect the BIOS via RCONFs (cache settings similar
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000738 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
Mart Raudseppe1344da2008-02-08 10:10:57 +0000739 *
740 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
741 * To enable write to NOR Boot flash for the benefit of systems that have such
742 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
Mart Raudseppe1344da2008-02-08 10:10:57 +0000743 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000744static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
Lane Brooksd54958a2007-11-13 16:45:22 +0000745{
Uwe Hermann394131e2008-10-18 21:14:13 +0000746#define MSR_RCONF_DEFAULT 0x1808
747#define MSR_NORF_CTL 0x51400018
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000748
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000749 msr_t msr;
Lane Brooksd54958a2007-11-13 16:45:22 +0000750
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000751 /* Geode only has a single core */
752 if (setup_cpu_msr(0))
Lane Brooksd54958a2007-11-13 16:45:22 +0000753 return -1;
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000754
755 msr = rdmsr(MSR_RCONF_DEFAULT);
756 if ((msr.hi >> 24) != 0x22) {
757 msr.hi &= 0xfbffffff;
758 wrmsr(MSR_RCONF_DEFAULT, msr);
Lane Brooksd54958a2007-11-13 16:45:22 +0000759 }
Mart Raudseppe1344da2008-02-08 10:10:57 +0000760
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000761 msr = rdmsr(MSR_NORF_CTL);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000762 /* Raise WE_CS3 bit. */
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000763 msr.lo |= 0x08;
764 wrmsr(MSR_NORF_CTL, msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000765
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000766 cleanup_cpu_msr();
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000767
Uwe Hermann394131e2008-10-18 21:14:13 +0000768#undef MSR_RCONF_DEFAULT
769#undef MSR_NORF_CTL
Lane Brooksd54958a2007-11-13 16:45:22 +0000770 return 0;
771}
772
Uwe Hermann372eeb52007-12-04 21:49:06 +0000773static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000774{
Ollie Lho184a4042005-11-26 21:55:36 +0000775 uint8_t new;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000776
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000777 rpci_write_byte(dev, 0x52, 0xee);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000778
779 new = pci_read_byte(dev, 0x52);
780
781 if (new != 0xee) {
Stefan Tauneraf882e72011-08-04 17:37:58 +0000782 msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
783 "(WARNING ONLY).\n", 0x52, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000784 return -1;
785 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000786
Ollie Lhocbbf1252004-03-17 22:22:08 +0000787 return 0;
788}
789
Uwe Hermann190f8492008-10-25 18:03:50 +0000790/* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000791static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000792{
Ollie Lho184a4042005-11-26 21:55:36 +0000793 uint8_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000794
Uwe Hermann372eeb52007-12-04 21:49:06 +0000795 /* Enable decoding at 0xffb00000 to 0xffffffff. */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000796 old = pci_read_byte(dev, 0x43);
Ollie Lhod11f3612004-12-07 17:19:04 +0000797 new = old | 0xC0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000798 if (new != old) {
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000799 rpci_write_byte(dev, 0x43, new);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000800 if (pci_read_byte(dev, 0x43) != new) {
Stefan Tauneraf882e72011-08-04 17:37:58 +0000801 msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
802 "(WARNING ONLY).\n", 0x43, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000803 }
804 }
805
Uwe Hermann190f8492008-10-25 18:03:50 +0000806 /* Enable 'ROM write' bit. */
Ollie Lho761bf1b2004-03-20 16:46:10 +0000807 old = pci_read_byte(dev, 0x40);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000808 new = old | 0x01;
809 if (new == old)
810 return 0;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000811 rpci_write_byte(dev, 0x40, new);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000812
813 if (pci_read_byte(dev, 0x40) != new) {
Stefan Tauneraf882e72011-08-04 17:37:58 +0000814 msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
815 "(WARNING ONLY).\n", 0x40, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000816 return -1;
817 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000818
Ollie Lhocbbf1252004-03-17 22:22:08 +0000819 return 0;
820}
821
Marc Jones3af487d2008-10-15 17:50:29 +0000822static int enable_flash_sb600(struct pci_dev *dev, const char *name)
823{
Michael Karcherb05b9e12010-07-22 18:04:19 +0000824 uint32_t prot;
Marc Jones3af487d2008-10-15 17:50:29 +0000825 uint8_t reg;
Michael Karcherb05b9e12010-07-22 18:04:19 +0000826 int ret;
Marc Jones3af487d2008-10-15 17:50:29 +0000827
Jason Wanga3f04be2008-11-28 21:36:51 +0000828 /* Clear ROM protect 0-3. */
829 for (reg = 0x50; reg < 0x60; reg += 4) {
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000830 prot = pci_read_long(dev, reg);
831 /* No protection flags for this region?*/
832 if ((prot & 0x3) == 0)
833 continue;
Mathias Krause9fbdc032011-01-01 10:54:09 +0000834 msg_pinfo("SB600 %s%sprotected from 0x%08x to 0x%08x\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000835 (prot & 0x1) ? "write " : "",
836 (prot & 0x2) ? "read " : "",
837 (prot & 0xfffff800),
838 (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000839 prot &= 0xfffffffc;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000840 rpci_write_byte(dev, reg, prot);
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000841 prot = pci_read_long(dev, reg);
Carl-Daniel Hailfinger9bb88ac2009-05-06 13:51:44 +0000842 if (prot & 0x3)
Mathias Krause9fbdc032011-01-01 10:54:09 +0000843 msg_perr("SB600 %s%sunprotect failed from 0x%08x to 0x%08x\n",
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000844 (prot & 0x1) ? "write " : "",
845 (prot & 0x2) ? "read " : "",
846 (prot & 0xfffff800),
847 (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
Jason Wanga3f04be2008-11-28 21:36:51 +0000848 }
849
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000850 internal_buses_supported = BUS_LPC | BUS_FWH;
Michael Karcherb05b9e12010-07-22 18:04:19 +0000851
852 ret = sb600_probe_spi(dev);
Jason Wanga3f04be2008-11-28 21:36:51 +0000853
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000854 /* Read ROM strap override register. */
855 OUTB(0x8f, 0xcd6);
856 reg = INB(0xcd7);
857 reg &= 0x0e;
Sean Nelson316a29f2010-05-07 20:09:04 +0000858 msg_pdbg("ROM strap override is %sactive", (reg & 0x02) ? "" : "not ");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000859 if (reg & 0x02) {
860 switch ((reg & 0x0c) >> 2) {
861 case 0x00:
Sean Nelson316a29f2010-05-07 20:09:04 +0000862 msg_pdbg(": LPC");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000863 break;
864 case 0x01:
Sean Nelson316a29f2010-05-07 20:09:04 +0000865 msg_pdbg(": PCI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000866 break;
867 case 0x02:
Sean Nelson316a29f2010-05-07 20:09:04 +0000868 msg_pdbg(": FWH");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000869 break;
870 case 0x03:
Sean Nelson316a29f2010-05-07 20:09:04 +0000871 msg_pdbg(": SPI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000872 break;
873 }
874 }
Sean Nelson316a29f2010-05-07 20:09:04 +0000875 msg_pdbg("\n");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000876
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000877 /* Force enable SPI ROM in SB600 PM register.
878 * If we enable SPI ROM here, we have to disable it after we leave.
Zheng Bao284a6002009-05-04 22:33:50 +0000879 * But how can we know which ROM we are going to handle? So we have
880 * to trade off. We only access LPC ROM if we boot via LPC ROM. And
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000881 * only SPI ROM if we boot via SPI ROM. If you want to access SPI on
882 * boards with LPC straps, you have to use the code below.
Zheng Bao284a6002009-05-04 22:33:50 +0000883 */
884 /*
Jason Wanga3f04be2008-11-28 21:36:51 +0000885 OUTB(0x8f, 0xcd6);
886 OUTB(0x0e, 0xcd7);
Zheng Bao284a6002009-05-04 22:33:50 +0000887 */
Marc Jones3af487d2008-10-15 17:50:29 +0000888
Michael Karcherb05b9e12010-07-22 18:04:19 +0000889 return ret;
Marc Jones3af487d2008-10-15 17:50:29 +0000890}
891
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000892static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name)
893{
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000894 uint8_t tmp;
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000895
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000896 rpci_write_byte(dev, 0x92, 0);
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000897
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000898 tmp = pci_read_byte(dev, 0x6d);
899 tmp |= 0x01;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000900 rpci_write_byte(dev, 0x6d, tmp);
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000901
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000902 return 0;
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000903}
904
Uwe Hermann372eeb52007-12-04 21:49:06 +0000905static int enable_flash_ck804(struct pci_dev *dev, const char *name)
Yinghai Lu952dfce2005-07-06 17:13:46 +0000906{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000907 uint8_t old, new;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000908
Jonathan Kollasch9ce498e2011-08-06 12:45:21 +0000909 pci_write_byte(dev, 0x92, 0x00);
910 if (pci_read_byte(dev, 0x92) != 0x00) {
911 msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
912 "(WARNING ONLY).\n", 0x92, 0x00, name);
913 }
914
Uwe Hermanna7e05482007-05-09 10:17:44 +0000915 old = pci_read_byte(dev, 0x88);
916 new = old | 0xc0;
917 if (new != old) {
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000918 rpci_write_byte(dev, 0x88, new);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000919 if (pci_read_byte(dev, 0x88) != new) {
Sylvain "ythier" Hitier3093f8f2011-09-03 11:22:27 +0000920 msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
921 "(WARNING ONLY).\n", 0x88, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000922 }
923 }
Yinghai Lu952dfce2005-07-06 17:13:46 +0000924
Uwe Hermanna7e05482007-05-09 10:17:44 +0000925 old = pci_read_byte(dev, 0x6d);
926 new = old | 0x01;
927 if (new == old)
928 return 0;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000929 rpci_write_byte(dev, 0x6d, new);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000930
931 if (pci_read_byte(dev, 0x6d) != new) {
Stefan Tauneraf882e72011-08-04 17:37:58 +0000932 msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
933 "(WARNING ONLY).\n", 0x6d, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000934 return -1;
935 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000936
Uwe Hermanna7e05482007-05-09 10:17:44 +0000937 return 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000938}
939
Joshua Roys85835d82010-09-15 14:47:56 +0000940static int enable_flash_osb4(struct pci_dev *dev, const char *name)
941{
942 uint8_t tmp;
943
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +0000944 internal_buses_supported = BUS_PARALLEL;
Joshua Roys85835d82010-09-15 14:47:56 +0000945
946 tmp = INB(0xc06);
947 tmp |= 0x1;
948 OUTB(tmp, 0xc06);
949
950 tmp = INB(0xc6f);
951 tmp |= 0x40;
952 OUTB(tmp, 0xc6f);
953
954 return 0;
955}
956
Uwe Hermann372eeb52007-12-04 21:49:06 +0000957/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
958static int enable_flash_sb400(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000959{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000960 uint8_t tmp;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000961 struct pci_dev *smbusdev;
962
Uwe Hermann372eeb52007-12-04 21:49:06 +0000963 /* Look for the SMBus device. */
Carl-Daniel Hailfingerf6e3efb2009-05-06 00:35:31 +0000964 smbusdev = pci_dev_find(0x1002, 0x4372);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000965
Uwe Hermanna7e05482007-05-09 10:17:44 +0000966 if (!smbusdev) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000967 msg_perr("ERROR: SMBus device not found. Aborting.\n");
Tadas Slotkus0e3f1cf2011-09-06 18:49:31 +0000968 return ERROR_FATAL;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000969 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000970
Uwe Hermann372eeb52007-12-04 21:49:06 +0000971 /* Enable some SMBus stuff. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000972 tmp = pci_read_byte(smbusdev, 0x79);
973 tmp |= 0x01;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000974 rpci_write_byte(smbusdev, 0x79, tmp);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000975
Uwe Hermann372eeb52007-12-04 21:49:06 +0000976 /* Change southbridge. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000977 tmp = pci_read_byte(dev, 0x48);
978 tmp |= 0x21;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000979 rpci_write_byte(dev, 0x48, tmp);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000980
Uwe Hermann372eeb52007-12-04 21:49:06 +0000981 /* Now become a bit silly. */
Andriy Gapon65c1b862008-05-22 13:22:45 +0000982 tmp = INB(0xc6f);
983 OUTB(tmp, 0xeb);
984 OUTB(tmp, 0xeb);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000985 tmp |= 0x40;
Andriy Gapon65c1b862008-05-22 13:22:45 +0000986 OUTB(tmp, 0xc6f);
987 OUTB(tmp, 0xeb);
988 OUTB(tmp, 0xeb);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000989
990 return 0;
991}
992
Uwe Hermann372eeb52007-12-04 21:49:06 +0000993static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
Yinghai Luca782972007-01-22 20:21:17 +0000994{
Michael Karcher4e2fb0e2010-01-12 23:29:26 +0000995 uint8_t old, new, val;
996 uint16_t wordval;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000997
Uwe Hermann372eeb52007-12-04 21:49:06 +0000998 /* Set the 0-16 MB enable bits. */
Michael Karcher4e2fb0e2010-01-12 23:29:26 +0000999 val = pci_read_byte(dev, 0x88);
1000 val |= 0xff; /* 256K */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001001 rpci_write_byte(dev, 0x88, val);
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001002 val = pci_read_byte(dev, 0x8c);
1003 val |= 0xff; /* 1M */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001004 rpci_write_byte(dev, 0x8c, val);
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001005 wordval = pci_read_word(dev, 0x90);
1006 wordval |= 0x7fff; /* 16M */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001007 rpci_write_word(dev, 0x90, wordval);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001008
Uwe Hermanna7e05482007-05-09 10:17:44 +00001009 old = pci_read_byte(dev, 0x6d);
1010 new = old | 0x01;
1011 if (new == old)
1012 return 0;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001013 rpci_write_byte(dev, 0x6d, new);
Yinghai Luca782972007-01-22 20:21:17 +00001014
Uwe Hermanna7e05482007-05-09 10:17:44 +00001015 if (pci_read_byte(dev, 0x6d) != new) {
Stefan Tauneraf882e72011-08-04 17:37:58 +00001016 msg_pinfo("Setting register 0x%x to 0x%x on %s failed "
1017 "(WARNING ONLY).\n", 0x6d, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001018 return -1;
1019 }
Yinghai Luca782972007-01-22 20:21:17 +00001020
1021 return 0;
Yinghai Luca782972007-01-22 20:21:17 +00001022}
1023
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001024/*
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001025 * The MCP6x/MCP7x code is based on cleanroom reverse engineering.
1026 * It is assumed that LPC chips need the MCP55 code and SPI chips need the
1027 * code provided in enable_flash_mcp6x_7x_common.
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001028 */
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001029static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001030{
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001031 int ret = 0, want_spi = 0;
Michael Karchercfa674f2010-02-25 11:38:23 +00001032 uint8_t val;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001033
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001034 msg_pinfo("This chipset is not really supported yet. Guesswork...\n");
1035
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001036 /* dev is the ISA bridge. No idea what the stuff below does. */
Michael Karchercfa674f2010-02-25 11:38:23 +00001037 val = pci_read_byte(dev, 0x8a);
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001038 msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 "
Michael Karchercfa674f2010-02-25 11:38:23 +00001039 "is %i\n", val, (val >> 6) & 0x1, (val >> 5) & 0x1);
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001040
Michael Karchercfa674f2010-02-25 11:38:23 +00001041 switch ((val >> 5) & 0x3) {
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001042 case 0x0:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001043 ret = enable_flash_mcp55(dev, name);
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001044 internal_buses_supported = BUS_LPC;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001045 msg_pdbg("Flash bus type is LPC\n");
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001046 break;
1047 case 0x2:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001048 want_spi = 1;
1049 /* SPI is added in mcp6x_spi_init if it works.
1050 * Do we really want to disable LPC in this case?
1051 */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001052 internal_buses_supported = BUS_NONE;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001053 msg_pdbg("Flash bus type is SPI\n");
Stefan Tauner25b5a592011-07-13 20:48:54 +00001054 msg_pinfo("SPI on this chipset is WIP. Please report any "
1055 "success or failure by mailing us the verbose "
1056 "output to flashrom@flashrom.org, thanks!\n");
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001057 break;
1058 default:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001059 /* Should not happen. */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001060 internal_buses_supported = BUS_NONE;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001061 msg_pdbg("Flash bus type is unknown (none)\n");
1062 msg_pinfo("Something went wrong with bus type detection.\n");
1063 goto out_msg;
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001064 break;
1065 }
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001066
1067 /* Force enable SPI and disable LPC? Not a good idea. */
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001068#if 0
Michael Karchercfa674f2010-02-25 11:38:23 +00001069 val |= (1 << 6);
1070 val &= ~(1 << 5);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001071 rpci_write_byte(dev, 0x8a, val);
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001072#endif
1073
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001074 if (mcp6x_spi_init(want_spi))
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001075 ret = 1;
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001076
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001077out_msg:
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001078 msg_pinfo("Please send the output of \"flashrom -V\" to "
Paul Menzelab6328f2010-10-08 11:03:02 +00001079 "flashrom@flashrom.org with\n"
1080 "your board name: flashrom -V as the subject to help us "
1081 "finish support for your\n"
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001082 "chipset. Thanks.\n");
1083
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001084 return ret;
1085}
1086
Uwe Hermann372eeb52007-12-04 21:49:06 +00001087static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001088{
Michael Karchercfa674f2010-02-25 11:38:23 +00001089 uint8_t val;
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001090
Uwe Hermanne823ee02007-06-05 15:02:18 +00001091 /* Set the 4MB enable bit. */
Michael Karchercfa674f2010-02-25 11:38:23 +00001092 val = pci_read_byte(dev, 0x41);
1093 val |= 0x0e;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001094 rpci_write_byte(dev, 0x41, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001095
Michael Karchercfa674f2010-02-25 11:38:23 +00001096 val = pci_read_byte(dev, 0x43);
1097 val |= (1 << 4);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +00001098 rpci_write_byte(dev, 0x43, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001099
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001100 return 0;
1101}
1102
Uwe Hermann48ec1b12010-08-08 17:01:18 +00001103/*
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001104 * Usually on the x86 architectures (and on other PC-like platforms like some
1105 * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
1106 * Elan SC520 only a small piece of the system flash is mapped there, but the
1107 * complete flash is mapped somewhere below 1G. The position can be determined
1108 * by the BOOTCS PAR register.
1109 */
1110static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
1111{
1112 int i, bootcs_found = 0;
1113 uint32_t parx = 0;
1114 void *mmcr;
1115
1116 /* 1. Map MMCR */
Stefan Reinauer0593f212009-01-26 01:10:48 +00001117 mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001118
1119 /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for
1120 * BOOTCS region (PARx[31:29] = 100b)e
1121 */
1122 for (i = 0x88; i <= 0xc4; i += 4) {
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +00001123 parx = mmio_readl(mmcr + i);
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001124 if ((parx >> 29) == 4) {
1125 bootcs_found = 1;
1126 break; /* BOOTCS found */
1127 }
1128 }
1129
1130 /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0]
1131 * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0]
1132 */
1133 if (bootcs_found) {
1134 if (parx & (1 << 25)) {
1135 parx &= (1 << 14) - 1; /* Mask [13:0] */
1136 flashbase = parx << 16;
1137 } else {
1138 parx &= (1 << 18) - 1; /* Mask [17:0] */
1139 flashbase = parx << 12;
1140 }
1141 } else {
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001142 msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. "
Carl-Daniel Hailfinger082c8b52011-08-15 19:54:20 +00001143 "Assuming flash at 4G.\n");
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001144 }
1145
1146 /* 4. Clean up */
Carl-Daniel Hailfingerbe726812009-08-09 12:44:08 +00001147 physunmap(mmcr, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001148 return 0;
1149}
1150
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001151#endif
1152
Idwer Vollering326a0602011-06-18 18:45:41 +00001153/* Please keep this list numerically sorted by vendor/device ID. */
Uwe Hermann05fab752009-05-16 23:42:17 +00001154const struct penable chipset_enables[] = {
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001155#if defined(__i386__) || defined(__x86_64__)
Idwer Vollering326a0602011-06-18 18:45:41 +00001156 {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400},
Idwer Vollering570dcc72011-06-18 18:45:50 +00001157 {0x1002, 0x438d, OK, "AMD", "SB600", enable_flash_sb600},
Paul Menzelac427b22012-02-16 21:07:07 +00001158 {0x1002, 0x439d, OK, "AMD", "SB7x0/SB8x0/SB9x0", enable_flash_sb600},
Uwe Hermann4179d292009-05-08 17:50:51 +00001159 {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100},
Idwer Vollering326a0602011-06-18 18:45:41 +00001160 {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536},
1161 {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536},
1162 {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520},
1163 {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111},
1164 {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111},
Wang Qing Pei6e9e2ee2011-08-26 21:11:41 +00001165 {0x1022, 0x780e, OK, "AMD", "Hudson", enable_flash_sb600},
Idwer Vollering326a0602011-06-18 18:45:41 +00001166 {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501},
1167 {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496},
Paul Menzel018d4822011-10-21 12:33:07 +00001168 {0x1039, 0x0530, OK, "SiS", "530", enable_flash_sis530},
Idwer Vollering326a0602011-06-18 18:45:41 +00001169 {0x1039, 0x0540, NT, "SiS", "540", enable_flash_sis540},
1170 {0x1039, 0x0620, NT, "SiS", "620", enable_flash_sis530},
1171 {0x1039, 0x0630, NT, "SiS", "630", enable_flash_sis540},
1172 {0x1039, 0x0635, NT, "SiS", "635", enable_flash_sis540},
1173 {0x1039, 0x0640, NT, "SiS", "640", enable_flash_sis540},
1174 {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis540},
Stefan Tauner716e0982011-07-25 20:38:52 +00001175 {0x1039, 0x0646, OK, "SiS", "645DX", enable_flash_sis540},
Idwer Vollering326a0602011-06-18 18:45:41 +00001176 {0x1039, 0x0648, NT, "SiS", "648", enable_flash_sis540},
1177 {0x1039, 0x0650, NT, "SiS", "650", enable_flash_sis540},
Stefan Tauner716e0982011-07-25 20:38:52 +00001178 {0x1039, 0x0651, OK, "SiS", "651", enable_flash_sis540},
Idwer Vollering326a0602011-06-18 18:45:41 +00001179 {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis540},
1180 {0x1039, 0x0661, OK, "SiS", "661", enable_flash_sis540},
Paul Menzelac427b22012-02-16 21:07:07 +00001181 {0x1039, 0x0730, OK, "SiS", "730", enable_flash_sis540},
Idwer Vollering326a0602011-06-18 18:45:41 +00001182 {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis540},
1183 {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis540},
1184 {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis540},
1185 {0x1039, 0x0741, OK, "SiS", "741", enable_flash_sis540},
1186 {0x1039, 0x0745, OK, "SiS", "745", enable_flash_sis540},
1187 {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540},
1188 {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540},
1189 {0x1039, 0x0755, NT, "SiS", "755", enable_flash_sis540},
1190 {0x1039, 0x5511, NT, "SiS", "5511", enable_flash_sis5511},
1191 {0x1039, 0x5571, NT, "SiS", "5571", enable_flash_sis530},
1192 {0x1039, 0x5591, NT, "SiS", "5591/5592", enable_flash_sis530},
1193 {0x1039, 0x5596, NT, "SiS", "5596", enable_flash_sis5511},
1194 {0x1039, 0x5597, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530},
1195 {0x1039, 0x5600, NT, "SiS", "600", enable_flash_sis530},
1196 {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530},
Idwer Vollering570dcc72011-06-18 18:45:50 +00001197 {0x10b9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533},
Stefan Taunerd06d9412011-06-12 19:47:55 +00001198 {0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2},
Uwe Hermannb0039912009-05-07 13:24:49 +00001199 {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */
1200 {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */
Stefan Taunerd06d9412011-06-12 19:47:55 +00001201 {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2},
1202 {0x10de, 0x00e0, OK, "NVIDIA", "NForce3", enable_flash_nvidia_nforce2},
Uwe Hermanneac10162008-03-13 18:52:51 +00001203 /* Slave, should not be here, to fix known bug for A01. */
Uwe Hermannb0039912009-05-07 13:24:49 +00001204 {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804},
Stefan Taunera9cbbac2011-08-07 13:17:20 +00001205 {0x10de, 0x0260, OK, "NVIDIA", "MCP51", enable_flash_ck804},
Uwe Hermannb0039912009-05-07 13:24:49 +00001206 {0x10de, 0x0261, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1207 {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1208 {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1209 {0x10de, 0x0360, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/
Carl-Daniel Hailfinger33d7b6a2010-05-22 07:27:16 +00001210 /* 10de:0361 is present in Tyan S2915 OEM systems, but not connected to
1211 * the flash chip. Instead, 10de:0364 is connected to the flash chip.
1212 * Until we have PCI device class matching or some fallback mechanism,
1213 * this is needed to get flashrom working on Tyan S2915 and maybe other
1214 * dual-MCP55 boards.
1215 */
1216#if 0
1217 {0x10de, 0x0361, NT, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1218#endif
Uwe Hermannb0039912009-05-07 13:24:49 +00001219 {0x10de, 0x0362, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1220 {0x10de, 0x0363, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1221 {0x10de, 0x0364, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1222 {0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1223 {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1224 {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */
Paul Menzelac427b22012-02-16 21:07:07 +00001225 {0x10de, 0x03e0, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
Sylvain "ythier" Hitier3093f8f2011-09-03 11:22:27 +00001226 {0x10de, 0x03e1, OK, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001227 {0x10de, 0x03e2, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1228 {0x10de, 0x03e3, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1229 {0x10de, 0x0440, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1230 {0x10de, 0x0441, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1231 {0x10de, 0x0442, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1232 {0x10de, 0x0443, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1233 {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp6x_7x},
1234 {0x10de, 0x075c, NT, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x},
Paul Menzel018d4822011-10-21 12:33:07 +00001235 {0x10de, 0x075d, OK, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x},
Paul Menzelac427b22012-02-16 21:07:07 +00001236 {0x10de, 0x07d7, OK, "NVIDIA", "MCP73", enable_flash_mcp6x_7x},
1237 {0x10de, 0x0aac, OK, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001238 {0x10de, 0x0aad, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1239 {0x10de, 0x0aae, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1240 {0x10de, 0x0aaf, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
Michael Karcher89bed6d2010-06-13 10:16:12 +00001241 /* VIA northbridges */
1242 {0x1106, 0x0585, NT, "VIA", "VT82C585VPX", via_no_byte_merge},
1243 {0x1106, 0x0595, NT, "VIA", "VT82C595", via_no_byte_merge},
1244 {0x1106, 0x0597, NT, "VIA", "VT82C597", via_no_byte_merge},
Michael Karcher89bed6d2010-06-13 10:16:12 +00001245 {0x1106, 0x0601, NT, "VIA", "VT8601/VT8601A", via_no_byte_merge},
Paul Menzelac427b22012-02-16 21:07:07 +00001246 {0x1106, 0x0691, OK, "VIA", "VT82C69x", via_no_byte_merge},
Michael Karcher89bed6d2010-06-13 10:16:12 +00001247 {0x1106, 0x8601, NT, "VIA", "VT8601T", via_no_byte_merge},
1248 /* VIA southbridges */
Idwer Vollering326a0602011-06-18 18:45:41 +00001249 {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111},
1250 {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111},
Paul Menzelac427b22012-02-16 21:07:07 +00001251 {0x1106, 0x0686, OK, "VIA", "VT82C686A/B", enable_flash_amd8111},
Paul Menzel018d4822011-10-21 12:33:07 +00001252 {0x1106, 0x3074, OK, "VIA", "VT8233", enable_flash_vt823x},
Raúl Sorianocd8404d2009-12-23 21:29:18 +00001253 {0x1106, 0x3147, OK, "VIA", "VT8233A", enable_flash_vt823x},
Uwe Hermann4179d292009-05-08 17:50:51 +00001254 {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x},
1255 {0x1106, 0x3227, OK, "VIA", "VT8237", enable_flash_vt823x},
1256 {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x},
1257 {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi},
Idwer Vollering326a0602011-06-18 18:45:41 +00001258 {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x},
1259 {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x},
Idwer Vollering570dcc72011-06-18 18:45:50 +00001260 {0x1106, 0x8353, OK, "VIA", "VX800/VX820", enable_flash_vt8237s_spi},
1261 {0x1106, 0x8409, OK, "VIA", "VX855/VX875", enable_flash_vt823x},
Idwer Vollering326a0602011-06-18 18:45:41 +00001262 {0x1166, 0x0200, OK, "Broadcom", "OSB4", enable_flash_osb4},
1263 {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000},
Rudolf Marek23907d82012-02-07 21:29:48 +00001264 {0x17f3, 0x6030, OK, "RDC", "R8610/R3210", enable_flash_rdc_r8610},
Idwer Vollering326a0602011-06-18 18:45:41 +00001265 {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4},
1266 {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4},
Paul Menzel018d4822011-10-21 12:33:07 +00001267 {0x8086, 0x1c44, OK, "Intel", "Z68", enable_flash_pch6},
1268 {0x8086, 0x1c46, OK, "Intel", "P67", enable_flash_pch6},
Stefan Taunerbd0c70a2011-08-27 21:19:56 +00001269 {0x8086, 0x1c47, NT, "Intel", "UM67", enable_flash_pch6},
1270 {0x8086, 0x1c49, NT, "Intel", "HM65", enable_flash_pch6},
Sylvain "ythier" Hitier3093f8f2011-09-03 11:22:27 +00001271 {0x8086, 0x1c4a, OK, "Intel", "H67", enable_flash_pch6},
Stefan Taunerbd0c70a2011-08-27 21:19:56 +00001272 {0x8086, 0x1c4b, NT, "Intel", "HM67", enable_flash_pch6},
1273 {0x8086, 0x1c4c, NT, "Intel", "Q65", enable_flash_pch6},
1274 {0x8086, 0x1c4d, NT, "Intel", "QS67", enable_flash_pch6},
1275 {0x8086, 0x1c4e, NT, "Intel", "Q67", enable_flash_pch6},
1276 {0x8086, 0x1c4f, NT, "Intel", "QM67", enable_flash_pch6},
1277 {0x8086, 0x1c50, NT, "Intel", "B65", enable_flash_pch6},
1278 {0x8086, 0x1c52, NT, "Intel", "C202", enable_flash_pch6},
1279 {0x8086, 0x1c54, NT, "Intel", "C204", enable_flash_pch6},
1280 {0x8086, 0x1c56, NT, "Intel", "C206", enable_flash_pch6},
1281 {0x8086, 0x1c5c, NT, "Intel", "H61", enable_flash_pch6},
Paul Menzelac427b22012-02-16 21:07:07 +00001282 {0x8086, 0x1d40, OK, "Intel", "X79", enable_flash_pch6},
1283 {0x8086, 0x1d41, NT, "Intel", "X79", enable_flash_pch6},
Idwer Vollering326a0602011-06-18 18:45:41 +00001284 {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e},
1285 {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e},
1286 {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e},
1287 {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich_4e},
Idwer Vollering570dcc72011-06-18 18:45:50 +00001288 {0x8086, 0x2450, NT, "Intel", "C-ICH", enable_flash_ich_4e},
Idwer Vollering326a0602011-06-18 18:45:41 +00001289 {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich_4e},
1290 {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich_4e},
1291 {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich_4e},
1292 {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich_4e},
1293 {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich_4e},
1294 {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich_4e},
1295 {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich_dc},
1296 {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich_dc},
Idwer Vollering570dcc72011-06-18 18:45:50 +00001297 {0x8086, 0x2642, NT, "Intel", "ICH6W/ICH6RW", enable_flash_ich_dc},
Idwer Vollering326a0602011-06-18 18:45:41 +00001298 {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich_dc},
1299 {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7},
1300 {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7},
1301 {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7},
1302 {0x8086, 0x27bc, OK, "Intel", "NM10", enable_flash_ich7},
1303 {0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7},
1304 {0x8086, 0x2810, OK, "Intel", "ICH8/ICH8R", enable_flash_ich8},
1305 {0x8086, 0x2811, OK, "Intel", "ICH8M-E", enable_flash_ich8},
1306 {0x8086, 0x2812, OK, "Intel", "ICH8DH", enable_flash_ich8},
1307 {0x8086, 0x2814, OK, "Intel", "ICH8DO", enable_flash_ich8},
1308 {0x8086, 0x2815, OK, "Intel", "ICH8M", enable_flash_ich8},
1309 {0x8086, 0x2910, OK, "Intel", "ICH9 Engineering Sample", enable_flash_ich9},
1310 {0x8086, 0x2912, OK, "Intel", "ICH9DH", enable_flash_ich9},
1311 {0x8086, 0x2914, OK, "Intel", "ICH9DO", enable_flash_ich9},
1312 {0x8086, 0x2916, OK, "Intel", "ICH9R", enable_flash_ich9},
1313 {0x8086, 0x2917, OK, "Intel", "ICH9M-E", enable_flash_ich9},
1314 {0x8086, 0x2918, OK, "Intel", "ICH9", enable_flash_ich9},
1315 {0x8086, 0x2919, OK, "Intel", "ICH9M", enable_flash_ich9},
Idwer Vollering570dcc72011-06-18 18:45:50 +00001316 {0x8086, 0x3a10, NT, "Intel", "ICH10R Engineering Sample", enable_flash_ich10},
Idwer Vollering326a0602011-06-18 18:45:41 +00001317 {0x8086, 0x3a14, OK, "Intel", "ICH10DO", enable_flash_ich10},
1318 {0x8086, 0x3a16, OK, "Intel", "ICH10R", enable_flash_ich10},
1319 {0x8086, 0x3a18, OK, "Intel", "ICH10", enable_flash_ich10},
1320 {0x8086, 0x3a1a, OK, "Intel", "ICH10D", enable_flash_ich10},
Idwer Vollering570dcc72011-06-18 18:45:50 +00001321 {0x8086, 0x3a1e, NT, "Intel", "ICH10 Engineering Sample", enable_flash_ich10},
Stefan Taunerbd0c70a2011-08-27 21:19:56 +00001322 {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_pch5},
1323 {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_pch5},
1324 {0x8086, 0x3b02, NT, "Intel", "P55", enable_flash_pch5},
1325 {0x8086, 0x3b03, NT, "Intel", "PM55", enable_flash_pch5},
Sylvain "ythier" Hitier3093f8f2011-09-03 11:22:27 +00001326 {0x8086, 0x3b06, OK, "Intel", "H55", enable_flash_pch5},
Stefan Taunerbd0c70a2011-08-27 21:19:56 +00001327 {0x8086, 0x3b07, OK, "Intel", "QM57", enable_flash_pch5},
1328 {0x8086, 0x3b08, NT, "Intel", "H57", enable_flash_pch5},
1329 {0x8086, 0x3b09, NT, "Intel", "HM55", enable_flash_pch5},
1330 {0x8086, 0x3b0a, NT, "Intel", "Q57", enable_flash_pch5},
1331 {0x8086, 0x3b0b, NT, "Intel", "HM57", enable_flash_pch5},
1332 {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_pch5},
1333 {0x8086, 0x3b0e, NT, "Intel", "B55", enable_flash_pch5},
1334 {0x8086, 0x3b0f, OK, "Intel", "QS57", enable_flash_pch5},
1335 {0x8086, 0x3b12, NT, "Intel", "3400", enable_flash_pch5},
1336 {0x8086, 0x3b14, NT, "Intel", "3420", enable_flash_pch5},
1337 {0x8086, 0x3b16, NT, "Intel", "3450", enable_flash_pch5},
1338 {0x8086, 0x3b1e, NT, "Intel", "B55", enable_flash_pch5},
Idwer Vollering326a0602011-06-18 18:45:41 +00001339 {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7},
1340 {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4},
1341 {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4},
1342 {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4},
Idwer Vollering570dcc72011-06-18 18:45:50 +00001343 {0x8086, 0x8119, OK, "Intel", "SCH Poulsbo", enable_flash_poulsbo},
Ingo Feldschmiddadc0a62011-09-07 19:18:25 +00001344 {0x8086, 0x8186, OK, "Intel", "Atom E6xx(T)/Tunnel Creek", enable_flash_tunnelcreek},
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001345#endif
Uwe Hermann05fab752009-05-16 23:42:17 +00001346 {},
Ollie Lhocbbf1252004-03-17 22:22:08 +00001347};
Ollie Lho761bf1b2004-03-20 16:46:10 +00001348
Uwe Hermanna7e05482007-05-09 10:17:44 +00001349int chipset_flash_enable(void)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001350{
Peter Huewe73f8ec82011-01-24 19:15:51 +00001351 struct pci_dev *dev = NULL;
Uwe Hermann372eeb52007-12-04 21:49:06 +00001352 int ret = -2; /* Nothing! */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001353 int i;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001354
Uwe Hermann372eeb52007-12-04 21:49:06 +00001355 /* Now let's try to find the chipset we have... */
Uwe Hermann05fab752009-05-16 23:42:17 +00001356 for (i = 0; chipset_enables[i].vendor_name != NULL; i++) {
1357 dev = pci_dev_find(chipset_enables[i].vendor_id,
1358 chipset_enables[i].device_id);
Michael Karcher89bed6d2010-06-13 10:16:12 +00001359 if (!dev)
1360 continue;
1361 if (ret != -2) {
1362 msg_pinfo("WARNING: unexpected second chipset match: "
Paul Menzelab6328f2010-10-08 11:03:02 +00001363 "\"%s %s\"\n"
1364 "ignoring, please report lspci and board URL "
1365 "to flashrom@flashrom.org\n"
Stefan Reinauerbf282b12011-03-29 21:41:41 +00001366 "with \'CHIPSET: your board name\' in the "
Paul Menzelab6328f2010-10-08 11:03:02 +00001367 "subject line.\n",
Michael Karcher89bed6d2010-06-13 10:16:12 +00001368 chipset_enables[i].vendor_name,
1369 chipset_enables[i].device_name);
1370 continue;
1371 }
Stefan Taunerec8c2482011-07-21 19:59:34 +00001372 msg_pinfo("Found chipset \"%s %s\"",
1373 chipset_enables[i].vendor_name,
1374 chipset_enables[i].device_name);
Stefan Tauner716e0982011-07-25 20:38:52 +00001375 msg_pdbg(" with PCI ID %04x:%04x",
Carl-Daniel Hailfingerf469c272010-05-22 07:31:50 +00001376 chipset_enables[i].vendor_id,
1377 chipset_enables[i].device_id);
Stefan Taunerec8c2482011-07-21 19:59:34 +00001378 msg_pinfo(". ");
Uwe Hermanna7e05482007-05-09 10:17:44 +00001379
Stefan Taunerec8c2482011-07-21 19:59:34 +00001380 if (chipset_enables[i].status == NT) {
1381 msg_pinfo("\nThis chipset is marked as untested. If "
1382 "you are using an up-to-date version\nof "
1383 "flashrom please email a report to "
1384 "flashrom@flashrom.org including a\nverbose "
1385 "(-V) log. Thank you!\n");
1386 }
1387 msg_pinfo("Enabling flash write... ");
Uwe Hermann05fab752009-05-16 23:42:17 +00001388 ret = chipset_enables[i].doit(dev,
1389 chipset_enables[i].device_name);
Michael Karcher89bed6d2010-06-13 10:16:12 +00001390 if (ret == NOT_DONE_YET) {
1391 ret = -2;
1392 msg_pinfo("OK - searching further chips.\n");
1393 } else if (ret < 0)
Sean Nelson316a29f2010-05-07 20:09:04 +00001394 msg_pinfo("FAILED!\n");
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001395 else if (ret == 0)
Sean Nelson316a29f2010-05-07 20:09:04 +00001396 msg_pinfo("OK.\n");
Uwe Hermann91f4afa2011-07-28 08:13:25 +00001397 else if (ret == ERROR_NONFATAL)
Michael Karchera4448d92010-07-22 18:04:15 +00001398 msg_pinfo("PROBLEMS, continuing anyway\n");
Tadas Slotkusad470342011-09-03 17:15:00 +00001399 if (ret == ERROR_FATAL) {
1400 msg_perr("FATAL ERROR!\n");
1401 return ret;
1402 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00001403 }
Michael Karcher89bed6d2010-06-13 10:16:12 +00001404
Uwe Hermanna7e05482007-05-09 10:17:44 +00001405 return ret;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001406}