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Dominik Geyerb46acba2008-05-16 12:55:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
5 * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
6 * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
Stefan Reinauera9424d52008-06-27 16:28:34 +00007 * Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00008 * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
Stefan Tauner8b391b82011-08-09 01:49:34 +00009 * Copyright (C) 2011 Stefan Tauner
Dominik Geyerb46acba2008-05-16 12:55:55 +000010 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Dominik Geyerb46acba2008-05-16 12:55:55 +000024 */
25
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000026#if defined(__i386__) || defined(__x86_64__)
27
Dominik Geyerb46acba2008-05-16 12:55:55 +000028#include <string.h>
Stefan Taunerd0c5dc22011-10-20 12:57:14 +000029#include <stdlib.h>
Dominik Geyerb46acba2008-05-16 12:55:55 +000030#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000031#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000032#include "hwaccess.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000033#include "spi.h"
Stefan Tauner1e146392011-09-15 23:52:55 +000034#include "ich_descriptors.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000035
Stefan Reinauera9424d52008-06-27 16:28:34 +000036/* ICH9 controller register definition */
Stefan Tauner55206942011-06-11 09:53:22 +000037#define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */
38#define HSFS_FDONE_OFF 0 /* 0: Flash Cycle Done */
39#define HSFS_FDONE (0x1 << HSFS_FDONE_OFF)
40#define HSFS_FCERR_OFF 1 /* 1: Flash Cycle Error */
41#define HSFS_FCERR (0x1 << HSFS_FCERR_OFF)
42#define HSFS_AEL_OFF 2 /* 2: Access Error Log */
43#define HSFS_AEL (0x1 << HSFS_AEL_OFF)
44#define HSFS_BERASE_OFF 3 /* 3-4: Block/Sector Erase Size */
45#define HSFS_BERASE (0x3 << HSFS_BERASE_OFF)
46#define HSFS_SCIP_OFF 5 /* 5: SPI Cycle In Progress */
47#define HSFS_SCIP (0x1 << HSFS_SCIP_OFF)
48 /* 6-12: reserved */
49#define HSFS_FDOPSS_OFF 13 /* 13: Flash Descriptor Override Pin-Strap Status */
50#define HSFS_FDOPSS (0x1 << HSFS_FDOPSS_OFF)
51#define HSFS_FDV_OFF 14 /* 14: Flash Descriptor Valid */
52#define HSFS_FDV (0x1 << HSFS_FDV_OFF)
53#define HSFS_FLOCKDN_OFF 15 /* 15: Flash Configuration Lock-Down */
54#define HSFS_FLOCKDN (0x1 << HSFS_FLOCKDN_OFF)
55
56#define ICH9_REG_HSFC 0x06 /* 16 Bits Hardware Sequencing Flash Control */
57#define HSFC_FGO_OFF 0 /* 0: Flash Cycle Go */
58#define HSFC_FGO (0x1 << HSFC_FGO_OFF)
59#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
60#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
61 /* 3-7: reserved */
62#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
63#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
64 /* 14: reserved */
65#define HSFC_SME_OFF 15 /* 15: SPI SMI# Enable */
66#define HSFC_SME (0x1 << HSFC_SME_OFF)
67
Stefan Taunerc0aaf952011-05-19 02:58:17 +000068#define ICH9_REG_FADDR 0x08 /* 32 Bits */
69#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
Stefan Reinauera9424d52008-06-27 16:28:34 +000070
Stefan Tauner29c80832011-06-12 08:14:10 +000071#define ICH9_REG_FRAP 0x50 /* 32 Bytes Flash Region Access Permissions */
72#define ICH9_REG_FREG0 0x54 /* 32 Bytes Flash Region 0 */
73
74#define ICH9_REG_PR0 0x74 /* 32 Bytes Protected Range 0 */
Stefan Taunerbf69aaa2011-09-17 21:21:48 +000075#define PR_WP_OFF 31 /* 31: write protection enable */
76#define PR_RP_OFF 15 /* 15: read protection enable */
Stefan Tauner29c80832011-06-12 08:14:10 +000077
Stefan Taunerc0aaf952011-05-19 02:58:17 +000078#define ICH9_REG_SSFS 0x90 /* 08 Bits */
Stefan Tauner0c1ec452011-06-11 09:53:09 +000079#define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */
80#define SSFS_SCIP (0x1 << SSFS_SCIP_OFF)
81#define SSFS_FDONE_OFF 2 /* Cycle Done Status */
82#define SSFS_FDONE (0x1 << SSFS_FDONE_OFF)
83#define SSFS_FCERR_OFF 3 /* Flash Cycle Error */
84#define SSFS_FCERR (0x1 << SSFS_FCERR_OFF)
85#define SSFS_AEL_OFF 4 /* Access Error Log */
86#define SSFS_AEL (0x1 << SSFS_AEL_OFF)
Stefan Taunerc0aaf952011-05-19 02:58:17 +000087/* The following bits are reserved in SSFS: 1,5-7. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +000088#define SSFS_RESERVED_MASK 0x000000e2
Stefan Reinauera9424d52008-06-27 16:28:34 +000089
Stefan Taunerc0aaf952011-05-19 02:58:17 +000090#define ICH9_REG_SSFC 0x91 /* 24 Bits */
Stefan Taunerc0aaf952011-05-19 02:58:17 +000091/* We combine SSFS and SSFC to one 32-bit word,
Stefan Tauner0c1ec452011-06-11 09:53:09 +000092 * therefore SSFC bits are off by 8. */
93 /* 0: reserved */
94#define SSFC_SCGO_OFF (1 + 8) /* 1: SPI Cycle Go */
95#define SSFC_SCGO (0x1 << SSFC_SCGO_OFF)
96#define SSFC_ACS_OFF (2 + 8) /* 2: Atomic Cycle Sequence */
97#define SSFC_ACS (0x1 << SSFC_ACS_OFF)
98#define SSFC_SPOP_OFF (3 + 8) /* 3: Sequence Prefix Opcode Pointer */
99#define SSFC_SPOP (0x1 << SSFC_SPOP_OFF)
100#define SSFC_COP_OFF (4 + 8) /* 4-6: Cycle Opcode Pointer */
101#define SSFC_COP (0x7 << SSFC_COP_OFF)
102 /* 7: reserved */
103#define SSFC_DBC_OFF (8 + 8) /* 8-13: Data Byte Count */
104#define SSFC_DBC (0x3f << SSFC_DBC_OFF)
105#define SSFC_DS_OFF (14 + 8) /* 14: Data Cycle */
106#define SSFC_DS (0x1 << SSFC_DS_OFF)
107#define SSFC_SME_OFF (15 + 8) /* 15: SPI SMI# Enable */
108#define SSFC_SME (0x1 << SSFC_SME_OFF)
109#define SSFC_SCF_OFF (16 + 8) /* 16-18: SPI Cycle Frequency */
110#define SSFC_SCF (0x7 << SSFC_SCF_OFF)
111#define SSFC_SCF_20MHZ 0x00000000
112#define SSFC_SCF_33MHZ 0x01000000
113 /* 19-23: reserved */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000114#define SSFC_RESERVED_MASK 0xf8008100
Stefan Reinauera9424d52008-06-27 16:28:34 +0000115
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000116#define ICH9_REG_PREOP 0x94 /* 16 Bits */
117#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
118#define ICH9_REG_OPMENU 0x98 /* 64 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000119
Stefan Tauner29c80832011-06-12 08:14:10 +0000120#define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */
121#define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */
122
Stefan Tauner1e146392011-09-15 23:52:55 +0000123#define ICH8_REG_VSCC 0xC1 /* 32 Bits Vendor Specific Component Capabilities */
124#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */
125#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */
126/* The individual fields of the VSCC registers are defined in the file
127 * ich_descriptors.h. The reason is that the same layout is also used in the
128 * flash descriptor to define the properties of the different flash chips
129 * supported. The BIOS (or the ME?) is responsible to populate the ICH registers
130 * with the information from the descriptor on startup depending on the actual
131 * chip(s) detected. */
132
Stefan Taunerbd649e42011-07-01 00:39:16 +0000133#define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */
134#define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */
135#define FPB_FPBA (0x1FFF << FPB_FPBA_OFF)
136
Dominik Geyerb46acba2008-05-16 12:55:55 +0000137// ICH9R SPI commands
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000138#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
139#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
140#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
141#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
Dominik Geyerb46acba2008-05-16 12:55:55 +0000142
Stefan Reinauera9424d52008-06-27 16:28:34 +0000143// ICH7 registers
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000144#define ICH7_REG_SPIS 0x00 /* 16 Bits */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000145#define SPIS_SCIP 0x0001
146#define SPIS_GRANT 0x0002
147#define SPIS_CDS 0x0004
148#define SPIS_FCERR 0x0008
149#define SPIS_RESERVED_MASK 0x7ff0
Stefan Reinauera9424d52008-06-27 16:28:34 +0000150
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000151/* VIA SPI is compatible with ICH7, but maxdata
152 to transfer is 16 bytes.
153
154 DATA byte count on ICH7 is 8:13, on VIA 8:11
155
156 bit 12 is port select CS0 CS1
157 bit 13 is FAST READ enable
158 bit 7 is used with fast read and one shot controls CS de-assert?
159*/
160
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000161#define ICH7_REG_SPIC 0x02 /* 16 Bits */
162#define SPIC_SCGO 0x0002
163#define SPIC_ACS 0x0004
164#define SPIC_SPOP 0x0008
165#define SPIC_DS 0x4000
Stefan Reinauera9424d52008-06-27 16:28:34 +0000166
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000167#define ICH7_REG_SPIA 0x04 /* 32 Bits */
168#define ICH7_REG_SPID0 0x08 /* 64 Bytes */
169#define ICH7_REG_PREOP 0x54 /* 16 Bits */
170#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
171#define ICH7_REG_OPMENU 0x58 /* 64 Bits */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000172
FENG yu ningc05a2952008-12-08 18:16:58 +0000173/* ICH SPI configuration lock-down. May be set during chipset enabling. */
Michael Karchera4448d92010-07-22 18:04:15 +0000174static int ichspi_lock = 0;
FENG yu ningc05a2952008-12-08 18:16:58 +0000175
Stefan Taunera8d838d2011-11-06 23:51:09 +0000176static enum ich_chipset ich_generation = CHIPSET_ICH_UNKNOWN;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000177uint32_t ichspi_bbar = 0;
178
Michael Karchera4448d92010-07-22 18:04:15 +0000179static void *ich_spibar = NULL;
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000180
Dominik Geyerb46acba2008-05-16 12:55:55 +0000181typedef struct _OPCODE {
182 uint8_t opcode; //This commands spi opcode
183 uint8_t spi_type; //This commands spi type
184 uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1
185} OPCODE;
186
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000187/* Suggested opcode definition:
Dominik Geyerb46acba2008-05-16 12:55:55 +0000188 * Preop 1: Write Enable
189 * Preop 2: Write Status register enable
190 *
191 * OP 0: Write address
192 * OP 1: Read Address
193 * OP 2: ERASE block
194 * OP 3: Read Status register
195 * OP 4: Read ID
196 * OP 5: Write Status register
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000197 * OP 6: chip private (read JEDEC id)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000198 * OP 7: Chip erase
199 */
200typedef struct _OPCODES {
201 uint8_t preop[2];
202 OPCODE opcode[8];
203} OPCODES;
204
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000205static OPCODES *curopcodes = NULL;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000206
207/* HW access functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000208static uint32_t REGREAD32(int X)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000209{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000210 return mmio_readl(ich_spibar + X);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000211}
212
Uwe Hermann09e04f72009-05-16 22:36:00 +0000213static uint16_t REGREAD16(int X)
Stefan Reinauera9424d52008-06-27 16:28:34 +0000214{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000215 return mmio_readw(ich_spibar + X);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000216}
217
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000218static uint16_t REGREAD8(int X)
219{
220 return mmio_readb(ich_spibar + X);
221}
222
Stefan Taunerccd92a12011-07-01 00:39:01 +0000223#define REGWRITE32(off, val) mmio_writel(val, ich_spibar+(off))
224#define REGWRITE16(off, val) mmio_writew(val, ich_spibar+(off))
225#define REGWRITE8(off, val) mmio_writeb(val, ich_spibar+(off))
Dominik Geyerb46acba2008-05-16 12:55:55 +0000226
Dominik Geyerb46acba2008-05-16 12:55:55 +0000227/* Common SPI functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000228static int find_opcode(OPCODES *op, uint8_t opcode);
229static int find_preop(OPCODES *op, uint8_t preop);
FENG yu ningf041e9b2008-12-15 02:32:11 +0000230static int generate_opcodes(OPCODES * op);
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000231static int program_opcodes(OPCODES *op, int enable_undo);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000232static int run_opcode(const struct flashctx *flash, OPCODE op, uint32_t offset,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000233 uint8_t datalength, uint8_t * data);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000234
FENG yu ningf041e9b2008-12-15 02:32:11 +0000235/* for pairing opcodes with their required preop */
236struct preop_opcode_pair {
237 uint8_t preop;
238 uint8_t opcode;
239};
240
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000241/* List of opcodes which need preopcodes and matching preopcodes. Unused. */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000242const struct preop_opcode_pair pops[] = {
FENG yu ningf041e9b2008-12-15 02:32:11 +0000243 {JEDEC_WREN, JEDEC_BYTE_PROGRAM},
244 {JEDEC_WREN, JEDEC_SE}, /* sector erase */
245 {JEDEC_WREN, JEDEC_BE_52}, /* block erase */
246 {JEDEC_WREN, JEDEC_BE_D8}, /* block erase */
247 {JEDEC_WREN, JEDEC_CE_60}, /* chip erase */
248 {JEDEC_WREN, JEDEC_CE_C7}, /* chip erase */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000249 /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */
250 {JEDEC_WREN, JEDEC_WRSR},
FENG yu ningf041e9b2008-12-15 02:32:11 +0000251 {JEDEC_EWSR, JEDEC_WRSR},
252 {0,}
253};
254
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000255/* Reasonable default configuration. Needs ad-hoc modifications if we
256 * encounter unlisted opcodes. Fun.
257 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000258static OPCODES O_ST_M25P = {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000259 {
260 JEDEC_WREN,
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000261 JEDEC_EWSR,
262 },
Dominik Geyerb46acba2008-05-16 12:55:55 +0000263 {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000264 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000265 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000266 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000267 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
Carl-Daniel Hailfinger15aa7c62009-05-26 21:25:08 +0000268 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000269 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000270 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000271 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
272 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000273};
274
Helge Wagner738e2522010-10-05 22:06:05 +0000275/* List of opcodes with their corresponding spi_type
276 * It is used to reprogram the chipset OPCODE table on-the-fly if an opcode
277 * is needed which is currently not in the chipset OPCODE table
278 */
279static OPCODE POSSIBLE_OPCODES[] = {
280 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
281 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
282 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
283 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
284 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
285 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
286 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
287 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
288 {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Sector erase
289 {JEDEC_BE_52, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Block erase
290 {JEDEC_AAI_WORD_PROGRAM, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Auto Address Increment
291};
292
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000293static OPCODES O_EXISTING = {};
FENG yu ningc05a2952008-12-08 18:16:58 +0000294
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000295/* pretty printing functions */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000296static void prettyprint_opcodes(OPCODES *ops)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000297{
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000298 OPCODE oc;
299 const char *t;
300 const char *a;
301 uint8_t i;
302 static const char *const spi_type[4] = {
303 "read w/o addr",
304 "write w/o addr",
305 "read w/ addr",
306 "write w/ addr"
307 };
308 static const char *const atomic_type[3] = {
309 "none",
310 " 0 ",
311 " 1 "
312 };
313
314 if (ops == NULL)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000315 return;
316
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000317 msg_pdbg2(" OP Type Pre-OP\n");
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000318 for (i = 0; i < 8; i++) {
319 oc = ops->opcode[i];
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000320 t = (oc.spi_type > 3) ? "invalid" : spi_type[oc.spi_type];
321 a = (oc.atomic > 2) ? "invalid" : atomic_type[oc.atomic];
322 msg_pdbg2("op[%d]: 0x%02x, %s, %s\n", i, oc.opcode, t, a);
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000323 }
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000324 msg_pdbg2("Pre-OP 0: 0x%02x, Pre-OP 1: 0x%02x\n", ops->preop[0],
325 ops->preop[1]);
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000326}
327
328#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF)
329
Stefan Tauner55206942011-06-11 09:53:22 +0000330static void prettyprint_ich9_reg_hsfs(uint16_t reg_val)
331{
332 msg_pdbg("HSFS: ");
333 pprint_reg(HSFS, FDONE, reg_val, ", ");
334 pprint_reg(HSFS, FCERR, reg_val, ", ");
335 pprint_reg(HSFS, AEL, reg_val, ", ");
336 pprint_reg(HSFS, BERASE, reg_val, ", ");
337 pprint_reg(HSFS, SCIP, reg_val, ", ");
338 pprint_reg(HSFS, FDOPSS, reg_val, ", ");
339 pprint_reg(HSFS, FDV, reg_val, ", ");
340 pprint_reg(HSFS, FLOCKDN, reg_val, "\n");
341}
342
343static void prettyprint_ich9_reg_hsfc(uint16_t reg_val)
344{
345 msg_pdbg("HSFC: ");
346 pprint_reg(HSFC, FGO, reg_val, ", ");
347 pprint_reg(HSFC, FCYCLE, reg_val, ", ");
348 pprint_reg(HSFC, FDBC, reg_val, ", ");
349 pprint_reg(HSFC, SME, reg_val, "\n");
350}
351
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000352static void prettyprint_ich9_reg_ssfs(uint32_t reg_val)
353{
354 msg_pdbg("SSFS: ");
355 pprint_reg(SSFS, SCIP, reg_val, ", ");
356 pprint_reg(SSFS, FDONE, reg_val, ", ");
357 pprint_reg(SSFS, FCERR, reg_val, ", ");
358 pprint_reg(SSFS, AEL, reg_val, "\n");
359}
360
361static void prettyprint_ich9_reg_ssfc(uint32_t reg_val)
362{
363 msg_pdbg("SSFC: ");
364 pprint_reg(SSFC, SCGO, reg_val, ", ");
365 pprint_reg(SSFC, ACS, reg_val, ", ");
366 pprint_reg(SSFC, SPOP, reg_val, ", ");
367 pprint_reg(SSFC, COP, reg_val, ", ");
368 pprint_reg(SSFC, DBC, reg_val, ", ");
369 pprint_reg(SSFC, SME, reg_val, ", ");
370 pprint_reg(SSFC, SCF, reg_val, "\n");
371}
372
Helge Wagner738e2522010-10-05 22:06:05 +0000373static uint8_t lookup_spi_type(uint8_t opcode)
374{
375 int a;
376
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000377 for (a = 0; a < ARRAY_SIZE(POSSIBLE_OPCODES); a++) {
Helge Wagner738e2522010-10-05 22:06:05 +0000378 if (POSSIBLE_OPCODES[a].opcode == opcode)
379 return POSSIBLE_OPCODES[a].spi_type;
380 }
381
382 return 0xFF;
383}
384
385static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt)
386{
387 uint8_t spi_type;
388
389 spi_type = lookup_spi_type(opcode);
390 if (spi_type > 3) {
391 /* Try to guess spi type from read/write sizes.
392 * The following valid writecnt/readcnt combinations exist:
393 * writecnt = 4, readcnt >= 0
394 * writecnt = 1, readcnt >= 0
395 * writecnt >= 4, readcnt = 0
396 * writecnt >= 1, readcnt = 0
397 * writecnt >= 1 is guaranteed for all commands.
398 */
399 if (readcnt == 0)
400 /* if readcnt=0 and writecount >= 4, we don't know if it is WRITE_NO_ADDRESS
401 * or WRITE_WITH_ADDRESS. But if we use WRITE_NO_ADDRESS and the first 3 data
402 * bytes are actual the address, they go to the bus anyhow
403 */
404 spi_type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
405 else if (writecnt == 1) // and readcnt is > 0
406 spi_type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
407 else if (writecnt == 4) // and readcnt is > 0
408 spi_type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
Stefan Taunerdc704ed2012-05-06 15:11:26 +0000409 else // we have an invalid case
410 return SPI_INVALID_LENGTH;
Helge Wagner738e2522010-10-05 22:06:05 +0000411 }
Stefan Taunerdc704ed2012-05-06 15:11:26 +0000412 int oppos = 2; // use original JEDEC_BE_D8 offset
413 curopcodes->opcode[oppos].opcode = opcode;
414 curopcodes->opcode[oppos].spi_type = spi_type;
415 program_opcodes(curopcodes, 0);
416 oppos = find_opcode(curopcodes, opcode);
417 msg_pdbg ("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos);
418 return oppos;
Helge Wagner738e2522010-10-05 22:06:05 +0000419}
420
Uwe Hermann09e04f72009-05-16 22:36:00 +0000421static int find_opcode(OPCODES *op, uint8_t opcode)
FENG yu ningc05a2952008-12-08 18:16:58 +0000422{
423 int a;
424
Stefan Tauner50e7c602011-11-08 10:55:54 +0000425 if (op == NULL) {
426 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
427 return -1;
428 }
429
FENG yu ningc05a2952008-12-08 18:16:58 +0000430 for (a = 0; a < 8; a++) {
431 if (op->opcode[a].opcode == opcode)
432 return a;
433 }
434
435 return -1;
436}
437
Uwe Hermann09e04f72009-05-16 22:36:00 +0000438static int find_preop(OPCODES *op, uint8_t preop)
FENG yu ningc05a2952008-12-08 18:16:58 +0000439{
440 int a;
441
Stefan Tauner50e7c602011-11-08 10:55:54 +0000442 if (op == NULL) {
443 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
444 return -1;
445 }
446
FENG yu ningc05a2952008-12-08 18:16:58 +0000447 for (a = 0; a < 2; a++) {
448 if (op->preop[a] == preop)
449 return a;
450 }
451
452 return -1;
453}
454
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000455/* Create a struct OPCODES based on what we find in the locked down chipset. */
FENG yu ningf041e9b2008-12-15 02:32:11 +0000456static int generate_opcodes(OPCODES * op)
FENG yu ningc05a2952008-12-08 18:16:58 +0000457{
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000458 int a;
FENG yu ningc05a2952008-12-08 18:16:58 +0000459 uint16_t preop, optype;
460 uint32_t opmenu[2];
FENG yu ningc05a2952008-12-08 18:16:58 +0000461
462 if (op == NULL) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000463 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
FENG yu ningc05a2952008-12-08 18:16:58 +0000464 return -1;
465 }
466
Stefan Taunera8d838d2011-11-06 23:51:09 +0000467 switch (ich_generation) {
468 case CHIPSET_ICH7:
FENG yu ningc05a2952008-12-08 18:16:58 +0000469 preop = REGREAD16(ICH7_REG_PREOP);
470 optype = REGREAD16(ICH7_REG_OPTYPE);
471 opmenu[0] = REGREAD32(ICH7_REG_OPMENU);
472 opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4);
473 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000474 case CHIPSET_ICH8:
475 default: /* Future version might behave the same */
FENG yu ningc05a2952008-12-08 18:16:58 +0000476 preop = REGREAD16(ICH9_REG_PREOP);
477 optype = REGREAD16(ICH9_REG_OPTYPE);
478 opmenu[0] = REGREAD32(ICH9_REG_OPMENU);
479 opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4);
480 break;
FENG yu ningc05a2952008-12-08 18:16:58 +0000481 }
482
483 op->preop[0] = (uint8_t) preop;
484 op->preop[1] = (uint8_t) (preop >> 8);
485
486 for (a = 0; a < 8; a++) {
487 op->opcode[a].spi_type = (uint8_t) (optype & 0x3);
488 optype >>= 2;
489 }
490
491 for (a = 0; a < 4; a++) {
492 op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff);
493 opmenu[0] >>= 8;
494 }
495
496 for (a = 4; a < 8; a++) {
497 op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff);
498 opmenu[1] >>= 8;
499 }
500
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000501 /* No preopcodes used by default. */
502 for (a = 0; a < 8; a++)
FENG yu ningc05a2952008-12-08 18:16:58 +0000503 op->opcode[a].atomic = 0;
504
FENG yu ningc05a2952008-12-08 18:16:58 +0000505 return 0;
506}
507
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000508static int program_opcodes(OPCODES *op, int enable_undo)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000509{
510 uint8_t a;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000511 uint16_t preop, optype;
512 uint32_t opmenu[2];
Dominik Geyerb46acba2008-05-16 12:55:55 +0000513
514 /* Program Prefix Opcodes */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000515 /* 0:7 Prefix Opcode 1 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000516 preop = (op->preop[0]);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000517 /* 8:16 Prefix Opcode 2 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000518 preop |= ((uint16_t) op->preop[1]) << 8;
Uwe Hermann394131e2008-10-18 21:14:13 +0000519
Stefan Reinauera9424d52008-06-27 16:28:34 +0000520 /* Program Opcode Types 0 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000521 optype = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000522 for (a = 0; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000523 optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000524 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000525
Stefan Reinauera9424d52008-06-27 16:28:34 +0000526 /* Program Allowable Opcodes 0 - 3 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000527 opmenu[0] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000528 for (a = 0; a < 4; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000529 opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000530 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000531
Dominik Geyerb46acba2008-05-16 12:55:55 +0000532 /*Program Allowable Opcodes 4 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000533 opmenu[1] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000534 for (a = 4; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000535 opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000536 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000537
Sean Nelson316a29f2010-05-07 20:09:04 +0000538 msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]);
Stefan Taunera8d838d2011-11-06 23:51:09 +0000539 switch (ich_generation) {
540 case CHIPSET_ICH7:
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000541 /* Register undo only for enable_undo=1, i.e. first call. */
542 if (enable_undo) {
543 rmmio_valw(ich_spibar + ICH7_REG_PREOP);
544 rmmio_valw(ich_spibar + ICH7_REG_OPTYPE);
545 rmmio_vall(ich_spibar + ICH7_REG_OPMENU);
546 rmmio_vall(ich_spibar + ICH7_REG_OPMENU + 4);
547 }
548 mmio_writew(preop, ich_spibar + ICH7_REG_PREOP);
549 mmio_writew(optype, ich_spibar + ICH7_REG_OPTYPE);
550 mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU);
551 mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000552 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000553 case CHIPSET_ICH8:
554 default: /* Future version might behave the same */
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000555 /* Register undo only for enable_undo=1, i.e. first call. */
556 if (enable_undo) {
557 rmmio_valw(ich_spibar + ICH9_REG_PREOP);
558 rmmio_valw(ich_spibar + ICH9_REG_OPTYPE);
559 rmmio_vall(ich_spibar + ICH9_REG_OPMENU);
560 rmmio_vall(ich_spibar + ICH9_REG_OPMENU + 4);
561 }
562 mmio_writew(preop, ich_spibar + ICH9_REG_PREOP);
563 mmio_writew(optype, ich_spibar + ICH9_REG_OPTYPE);
564 mmio_writel(opmenu[0], ich_spibar + ICH9_REG_OPMENU);
565 mmio_writel(opmenu[1], ich_spibar + ICH9_REG_OPMENU + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000566 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000567 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000568
569 return 0;
570}
571
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000572/*
Stefan Tauner50e7c602011-11-08 10:55:54 +0000573 * Returns -1 if at least one mandatory opcode is inaccessible, 0 otherwise.
574 * FIXME: this should also check for
575 * - at least one probing opcode (RDID (incl. AT25F variants?), REMS, RES?)
576 * - at least one erasing opcode (lots.)
577 * - at least one program opcode (BYTE_PROGRAM, AAI_WORD_PROGRAM, ...?)
578 * - necessary preops? (EWSR, WREN, ...?)
579 */
580static int ich_missing_opcodes()
581{
582 uint8_t ops[] = {
583 JEDEC_READ,
584 JEDEC_RDSR,
585 0
586 };
587 int i = 0;
588 while (ops[i] != 0) {
589 msg_pspew("checking for opcode 0x%02x\n", ops[i]);
590 if (find_opcode(curopcodes, ops[i]) == -1)
591 return -1;
592 i++;
593 }
594 return 0;
595}
596
597/*
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000598 * Try to set BBAR (BIOS Base Address Register), but read back the value in case
599 * it didn't stick.
600 */
Stefan Taunera8d838d2011-11-06 23:51:09 +0000601static void ich_set_bbar(uint32_t min_addr)
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000602{
Stefan Taunere27b2d42011-07-01 00:39:09 +0000603 int bbar_off;
Stefan Tauner7783f312011-09-17 21:21:42 +0000604 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +0000605 case CHIPSET_ICH7:
Stefan Taunere27b2d42011-07-01 00:39:09 +0000606 bbar_off = 0x50;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000607 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000608 case CHIPSET_ICH8:
Stefan Tauner7783f312011-09-17 21:21:42 +0000609 msg_perr("BBAR offset is unknown on ICH8!\n");
610 return;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000611 case CHIPSET_ICH9:
Stefan Tauner7783f312011-09-17 21:21:42 +0000612 default: /* Future version might behave the same */
Stefan Taunere27b2d42011-07-01 00:39:09 +0000613 bbar_off = ICH9_REG_BBAR;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000614 break;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000615 }
Stefan Taunere27b2d42011-07-01 00:39:09 +0000616
617 ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK;
618 if (ichspi_bbar) {
619 msg_pdbg("Reserved bits in BBAR not zero: 0x%08x\n",
620 ichspi_bbar);
621 }
622 min_addr &= BBAR_MASK;
623 ichspi_bbar |= min_addr;
624 rmmio_writel(ichspi_bbar, ich_spibar + bbar_off);
625 ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & BBAR_MASK;
626
627 /* We don't have any option except complaining. And if the write
628 * failed, the restore will fail as well, so no problem there.
629 */
630 if (ichspi_bbar != min_addr)
Stefan Tauner7783f312011-09-17 21:21:42 +0000631 msg_perr("Setting BBAR to 0x%08x failed! New value: 0x%08x.\n",
632 min_addr, ichspi_bbar);
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000633}
634
Stefan Tauner8b391b82011-08-09 01:49:34 +0000635/* Read len bytes from the fdata/spid register into the data array.
636 *
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +0000637 * Note that using len > flash->pgm->spi.max_data_read will return garbage or
Stefan Tauner8b391b82011-08-09 01:49:34 +0000638 * may even crash.
639 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000640static void ich_read_data(uint8_t *data, int len, int reg0_off)
Stefan Tauner8b391b82011-08-09 01:49:34 +0000641 {
642 int i;
643 uint32_t temp32 = 0;
644
645 for (i = 0; i < len; i++) {
646 if ((i % 4) == 0)
647 temp32 = REGREAD32(reg0_off + i);
648
649 data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
650 }
651}
652
653/* Fill len bytes from the data array into the fdata/spid registers.
654 *
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +0000655 * Note that using len > flash->pgm->spi.max_data_write will trash the registers
Stefan Tauner8b391b82011-08-09 01:49:34 +0000656 * following the data registers.
657 */
658static void ich_fill_data(const uint8_t *data, int len, int reg0_off)
659{
660 uint32_t temp32 = 0;
661 int i;
662
663 if (len <= 0)
664 return;
665
666 for (i = 0; i < len; i++) {
667 if ((i % 4) == 0)
668 temp32 = 0;
669
670 temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
671
672 if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
673 REGWRITE32(reg0_off + (i - (i % 4)), temp32);
674 }
675 i--;
676 if ((i % 4) != 3) /* Write remaining data to regs. */
677 REGWRITE32(reg0_off + (i - (i % 4)), temp32);
678}
679
FENG yu ningf041e9b2008-12-15 02:32:11 +0000680/* This function generates OPCODES from or programs OPCODES to ICH according to
681 * the chipset's SPI configuration lock.
FENG yu ningc05a2952008-12-08 18:16:58 +0000682 *
FENG yu ningf041e9b2008-12-15 02:32:11 +0000683 * It should be called before ICH sends any spi command.
FENG yu ningc05a2952008-12-08 18:16:58 +0000684 */
Michael Karchera4448d92010-07-22 18:04:15 +0000685static int ich_init_opcodes(void)
FENG yu ningc05a2952008-12-08 18:16:58 +0000686{
687 int rc = 0;
688 OPCODES *curopcodes_done;
689
690 if (curopcodes)
691 return 0;
692
693 if (ichspi_lock) {
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000694 msg_pdbg("Reading OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000695 curopcodes_done = &O_EXISTING;
FENG yu ningf041e9b2008-12-15 02:32:11 +0000696 rc = generate_opcodes(curopcodes_done);
FENG yu ningc05a2952008-12-08 18:16:58 +0000697 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000698 msg_pdbg("Programming OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000699 curopcodes_done = &O_ST_M25P;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000700 rc = program_opcodes(curopcodes_done, 1);
FENG yu ningc05a2952008-12-08 18:16:58 +0000701 }
702
703 if (rc) {
704 curopcodes = NULL;
Sean Nelson316a29f2010-05-07 20:09:04 +0000705 msg_perr("failed\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000706 return 1;
707 } else {
708 curopcodes = curopcodes_done;
Sean Nelson316a29f2010-05-07 20:09:04 +0000709 msg_pdbg("done\n");
Stefan Tauner8b391b82011-08-09 01:49:34 +0000710 prettyprint_opcodes(curopcodes);
FENG yu ningc05a2952008-12-08 18:16:58 +0000711 return 0;
712 }
713}
714
Stefan Reinauer43119562008-11-02 19:51:50 +0000715static int ich7_run_opcode(OPCODE op, uint32_t offset,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000716 uint8_t datalength, uint8_t * data, int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000717{
718 int write_cmd = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000719 int timeout;
Stefan Tauner8b391b82011-08-09 01:49:34 +0000720 uint32_t temp32;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000721 uint16_t temp16;
Stefan Reinauer43119562008-11-02 19:51:50 +0000722 uint64_t opmenu;
723 int opcode_index;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000724
725 /* Is it a write command? */
726 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
727 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
728 write_cmd = 1;
729 }
730
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000731 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
732 while ((REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) && --timeout) {
733 programmer_delay(10);
734 }
735 if (!timeout) {
736 msg_perr("Error: SCIP never cleared!\n");
737 return 1;
738 }
739
Stefan Tauner10b3e222011-07-01 00:39:23 +0000740 /* Program offset in flash into SPIA while preserving reserved bits. */
741 temp32 = REGREAD32(ICH7_REG_SPIA) & ~0x00FFFFFF;
742 REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000743
Stefan Tauner10b3e222011-07-01 00:39:23 +0000744 /* Program data into SPID0 to N */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000745 if (write_cmd && (datalength != 0))
746 ich_fill_data(data, datalength, ICH7_REG_SPID0);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000747
748 /* Assemble SPIS */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000749 temp16 = REGREAD16(ICH7_REG_SPIS);
750 /* keep reserved bits */
751 temp16 &= SPIS_RESERVED_MASK;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000752 /* clear error status registers */
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000753 temp16 |= (SPIS_CDS | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000754 REGWRITE16(ICH7_REG_SPIS, temp16);
755
756 /* Assemble SPIC */
757 temp16 = 0;
758
759 if (datalength != 0) {
760 temp16 |= SPIC_DS;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000761 temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000762 }
763
764 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000765 opmenu = REGREAD32(ICH7_REG_OPMENU);
766 opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32;
767
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000768 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
769 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000770 break;
771 }
772 opmenu >>= 8;
773 }
774 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000775 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000776 return 1;
777 }
778 temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000779
Michael Karcher136125a2011-04-29 22:11:36 +0000780 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
781 /* Handle Atomic. Atomic commands include three steps:
782 - sending the preop (mainly EWSR or WREN)
783 - sending the main command
784 - waiting for the busy bit (WIP) to be cleared
785 This means the timeout must be sufficient for chip erase
786 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000787 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000788 switch (op.atomic) {
789 case 2:
790 /* Select second preop. */
791 temp16 |= SPIC_SPOP;
792 /* And fall through. */
793 case 1:
794 /* Atomic command (preop+op) */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000795 temp16 |= SPIC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +0000796 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000797 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000798 }
799
800 /* Start */
801 temp16 |= SPIC_SCGO;
802
803 /* write it */
804 REGWRITE16(ICH7_REG_SPIC, temp16);
805
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000806 /* Wait for Cycle Done Status or Flash Cycle Error. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000807 while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) &&
808 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000809 programmer_delay(10);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000810 }
811 if (!timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000812 msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n",
813 REGREAD16(ICH7_REG_SPIS));
814 return 1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000815 }
816
Sean Nelson316a29f2010-05-07 20:09:04 +0000817 /* FIXME: make sure we do not needlessly cause transaction errors. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000818 temp16 = REGREAD16(ICH7_REG_SPIS);
819 if (temp16 & SPIS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +0000820 msg_perr("Transaction error!\n");
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000821 /* keep reserved bits */
822 temp16 &= SPIS_RESERVED_MASK;
823 REGWRITE16(ICH7_REG_SPIS, temp16 | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000824 return 1;
825 }
826
Stefan Tauner8b391b82011-08-09 01:49:34 +0000827 if ((!write_cmd) && (datalength != 0))
828 ich_read_data(data, datalength, ICH7_REG_SPID0);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000829
830 return 0;
831}
832
Stefan Reinauer43119562008-11-02 19:51:50 +0000833static int ich9_run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000834 uint8_t datalength, uint8_t * data)
835{
836 int write_cmd = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000837 int timeout;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000838 uint32_t temp32;
Stefan Reinauer43119562008-11-02 19:51:50 +0000839 uint64_t opmenu;
840 int opcode_index;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000841
842 /* Is it a write command? */
843 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
844 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
845 write_cmd = 1;
846 }
847
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000848 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
849 while ((REGREAD8(ICH9_REG_SSFS) & SSFS_SCIP) && --timeout) {
850 programmer_delay(10);
851 }
852 if (!timeout) {
853 msg_perr("Error: SCIP never cleared!\n");
854 return 1;
855 }
856
Stefan Tauner10b3e222011-07-01 00:39:23 +0000857 /* Program offset in flash into FADDR while preserve the reserved bits
858 * and clearing the 25. address bit which is only useable in hwseq. */
859 temp32 = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF;
860 REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000861
862 /* Program data into FDATA0 to N */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000863 if (write_cmd && (datalength != 0))
864 ich_fill_data(data, datalength, ICH9_REG_FDATA0);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000865
866 /* Assemble SSFS + SSFC */
Helge Wagnera319be12010-08-11 21:06:10 +0000867 temp32 = REGREAD32(ICH9_REG_SSFS);
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000868 /* Keep reserved bits only */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000869 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000870 /* Clear cycle done and cycle error status registers */
871 temp32 |= (SSFS_FDONE | SSFS_FCERR);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000872 REGWRITE32(ICH9_REG_SSFS, temp32);
873
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000874 /* Use 20 MHz */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000875 temp32 |= SSFC_SCF_20MHZ;
876
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000877 /* Set data byte count (DBC) and data cycle bit (DS) */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000878 if (datalength != 0) {
879 uint32_t datatemp;
880 temp32 |= SSFC_DS;
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000881 datatemp = ((((uint32_t)datalength - 1) << SSFC_DBC_OFF) &
882 SSFC_DBC);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000883 temp32 |= datatemp;
884 }
885
886 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000887 opmenu = REGREAD32(ICH9_REG_OPMENU);
888 opmenu |= ((uint64_t)REGREAD32(ICH9_REG_OPMENU + 4)) << 32;
889
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000890 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
891 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000892 break;
893 }
894 opmenu >>= 8;
895 }
896 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000897 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000898 return 1;
899 }
900 temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000901
Michael Karcher136125a2011-04-29 22:11:36 +0000902 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
903 /* Handle Atomic. Atomic commands include three steps:
904 - sending the preop (mainly EWSR or WREN)
905 - sending the main command
906 - waiting for the busy bit (WIP) to be cleared
907 This means the timeout must be sufficient for chip erase
908 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000909 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000910 switch (op.atomic) {
911 case 2:
912 /* Select second preop. */
913 temp32 |= SSFC_SPOP;
914 /* And fall through. */
915 case 1:
916 /* Atomic command (preop+op) */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000917 temp32 |= SSFC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +0000918 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000919 break;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000920 }
921
922 /* Start */
923 temp32 |= SSFC_SCGO;
924
925 /* write it */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000926 REGWRITE32(ICH9_REG_SSFS, temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000927
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000928 /* Wait for Cycle Done Status or Flash Cycle Error. */
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000929 while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_FDONE | SSFS_FCERR)) == 0) &&
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000930 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000931 programmer_delay(10);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000932 }
933 if (!timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000934 msg_perr("timeout, ICH9_REG_SSFS=0x%08x\n",
935 REGREAD32(ICH9_REG_SSFS));
936 return 1;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000937 }
938
Sean Nelson316a29f2010-05-07 20:09:04 +0000939 /* FIXME make sure we do not needlessly cause transaction errors. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000940 temp32 = REGREAD32(ICH9_REG_SSFS);
941 if (temp32 & SSFS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +0000942 msg_perr("Transaction error!\n");
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000943 prettyprint_ich9_reg_ssfs(temp32);
944 prettyprint_ich9_reg_ssfc(temp32);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000945 /* keep reserved bits */
946 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
947 /* Clear the transaction error. */
948 REGWRITE32(ICH9_REG_SSFS, temp32 | SSFS_FCERR);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000949 return 1;
950 }
951
Stefan Tauner8b391b82011-08-09 01:49:34 +0000952 if ((!write_cmd) && (datalength != 0))
953 ich_read_data(data, datalength, ICH9_REG_FDATA0);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000954
955 return 0;
956}
957
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000958static int run_opcode(const struct flashctx *flash, OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000959 uint8_t datalength, uint8_t * data)
960{
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000961 /* max_data_read == max_data_write for all Intel/VIA SPI masters */
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +0000962 uint8_t maxlength = flash->pgm->spi.max_data_read;
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000963
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +0000964 if (ich_generation == CHIPSET_ICH_UNKNOWN) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000965 msg_perr("%s: unsupported chipset\n", __func__);
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000966 return -1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000967 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000968
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000969 if (datalength > maxlength) {
970 msg_perr("%s: Internal command size error for "
971 "opcode 0x%02x, got datalength=%i, want <=%i\n",
972 __func__, op.opcode, datalength, maxlength);
973 return SPI_INVALID_LENGTH;
974 }
975
Stefan Taunera8d838d2011-11-06 23:51:09 +0000976 switch (ich_generation) {
977 case CHIPSET_ICH7:
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000978 return ich7_run_opcode(op, offset, datalength, data, maxlength);
Stefan Taunera8d838d2011-11-06 23:51:09 +0000979 case CHIPSET_ICH8:
980 default: /* Future version might behave the same */
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000981 return ich9_run_opcode(op, offset, datalength, data);
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000982 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000983}
984
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000985static int ich_spi_send_command(struct flashctx *flash, unsigned int writecnt,
986 unsigned int readcnt,
987 const unsigned char *writearr,
988 unsigned char *readarr)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000989{
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000990 int result;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000991 int opcode_index = -1;
992 const unsigned char cmd = *writearr;
993 OPCODE *opcode;
994 uint32_t addr = 0;
995 uint8_t *data;
996 int count;
997
Dominik Geyerb46acba2008-05-16 12:55:55 +0000998 /* find cmd in opcodes-table */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000999 opcode_index = find_opcode(curopcodes, cmd);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001000 if (opcode_index == -1) {
Helge Wagner738e2522010-10-05 22:06:05 +00001001 if (!ichspi_lock)
1002 opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt);
Stefan Taunerdc704ed2012-05-06 15:11:26 +00001003 if (opcode_index == SPI_INVALID_LENGTH) {
1004 msg_pdbg("OPCODE 0x%02x has unsupported length, will not execute.\n", cmd);
1005 return SPI_INVALID_LENGTH;
1006 } else if (opcode_index == -1) {
Stefan Tauner355cbfd2011-05-28 02:37:14 +00001007 msg_pdbg("Invalid OPCODE 0x%02x, will not execute.\n",
1008 cmd);
Helge Wagner738e2522010-10-05 22:06:05 +00001009 return SPI_INVALID_OPCODE;
1010 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001011 }
1012
1013 opcode = &(curopcodes->opcode[opcode_index]);
1014
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001015 /* The following valid writecnt/readcnt combinations exist:
1016 * writecnt = 4, readcnt >= 0
1017 * writecnt = 1, readcnt >= 0
1018 * writecnt >= 4, readcnt = 0
1019 * writecnt >= 1, readcnt = 0
1020 * writecnt >= 1 is guaranteed for all commands.
1021 */
1022 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) &&
1023 (writecnt != 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001024 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001025 "0x%02x, got writecnt=%i, want =4\n", __func__, cmd,
1026 writecnt);
1027 return SPI_INVALID_LENGTH;
1028 }
1029 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) &&
1030 (writecnt != 1)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001031 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001032 "0x%02x, got writecnt=%i, want =1\n", __func__, cmd,
1033 writecnt);
1034 return SPI_INVALID_LENGTH;
1035 }
1036 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) &&
1037 (writecnt < 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001038 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001039 "0x%02x, got writecnt=%i, want >=4\n", __func__, cmd,
1040 writecnt);
1041 return SPI_INVALID_LENGTH;
1042 }
1043 if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1044 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) &&
1045 (readcnt)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001046 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001047 "0x%02x, got readcnt=%i, want =0\n", __func__, cmd,
1048 readcnt);
1049 return SPI_INVALID_LENGTH;
1050 }
1051
Dominik Geyerb46acba2008-05-16 12:55:55 +00001052 /* if opcode-type requires an address */
1053 if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS ||
1054 opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001055 addr = (writearr[1] << 16) |
1056 (writearr[2] << 8) | (writearr[3] << 0);
Stefan Taunera8d838d2011-11-06 23:51:09 +00001057 if (addr < ichspi_bbar) {
1058 msg_perr("%s: Address 0x%06x below allowed "
1059 "range 0x%06x-0xffffff\n", __func__,
1060 addr, ichspi_bbar);
1061 return SPI_INVALID_ADDRESS;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +00001062 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001063 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001064
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001065 /* Translate read/write array/count.
1066 * The maximum data length is identical for the maximum read length and
1067 * for the maximum write length excluding opcode and address. Opcode and
1068 * address are stored in separate registers, not in the data registers
1069 * and are thus not counted towards data length. The only exception
1070 * applies if the opcode definition (un)intentionally classifies said
1071 * opcode incorrectly as non-address opcode or vice versa. */
Dominik Geyerb46acba2008-05-16 12:55:55 +00001072 if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001073 data = (uint8_t *) (writearr + 1);
1074 count = writecnt - 1;
1075 } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
1076 data = (uint8_t *) (writearr + 4);
1077 count = writecnt - 4;
1078 } else {
1079 data = (uint8_t *) readarr;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001080 count = readcnt;
1081 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001082
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001083 result = run_opcode(flash, *opcode, addr, count, data);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001084 if (result) {
Stefan Tauner8ed29342011-04-29 23:53:09 +00001085 msg_pdbg("Running OPCODE 0x%02x failed ", opcode->opcode);
1086 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1087 (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS)) {
1088 msg_pdbg("at address 0x%06x ", addr);
1089 }
1090 msg_pdbg("(payload length was %d).\n", count);
1091
1092 /* Print out the data array if it contains data to write.
1093 * Errors are detected before the received data is read back into
1094 * the array so it won't make sense to print it then. */
1095 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1096 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) {
1097 int i;
1098 msg_pspew("The data was:\n");
Stefan Taunerf382e352011-11-08 11:55:24 +00001099 for (i = 0; i < count; i++){
Stefan Tauner8ed29342011-04-29 23:53:09 +00001100 msg_pspew("%3d: 0x%02x\n", i, data[i]);
1101 }
1102 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001103 }
1104
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001105 return result;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001106}
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001107
Stefan Tauner50e7c602011-11-08 10:55:54 +00001108static struct hwseq_data {
1109 uint32_t size_comp0;
1110 uint32_t size_comp1;
1111} hwseq_data;
1112
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001113/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */
1114static void ich_hwseq_set_addr(uint32_t addr)
1115{
1116 uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF;
1117 REGWRITE32(ICH9_REG_FADDR, (addr & 0x01FFFFFF) | addr_old);
1118}
1119
1120/* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes
1121 * of the block containing this address. May return nonsense if the address is
1122 * not valid. The erase block size for a specific address depends on the flash
1123 * partition layout as specified by FPB and the partition properties as defined
1124 * by UVSCC and LVSCC respectively. An alternative to implement this method
1125 * would be by querying FPB and the respective VSCC register directly.
1126 */
1127static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr)
1128{
1129 uint8_t enc_berase;
1130 static const uint32_t const dec_berase[4] = {
1131 256,
1132 4 * 1024,
1133 8 * 1024,
1134 64 * 1024
1135 };
1136
1137 ich_hwseq_set_addr(addr);
1138 enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >>
1139 HSFS_BERASE_OFF;
1140 return dec_berase[enc_berase];
1141}
1142
1143/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
1144 Resets all error flags in HSFS.
1145 Returns 0 if the cycle completes successfully without errors within
1146 timeout us, 1 on errors. */
1147static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
1148 unsigned int len)
1149{
1150 uint16_t hsfs;
1151 uint32_t addr;
1152
1153 timeout /= 8; /* scale timeout duration to counter */
1154 while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) &
1155 (HSFS_FDONE | HSFS_FCERR)) == 0) &&
1156 --timeout) {
1157 programmer_delay(8);
1158 }
1159 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1160 if (!timeout) {
1161 addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF;
1162 msg_perr("Timeout error between offset 0x%08x and "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001163 "0x%08x (= 0x%08x + %d)!\n",
1164 addr, addr + len - 1, addr, len - 1);
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001165 prettyprint_ich9_reg_hsfs(hsfs);
1166 prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC));
1167 return 1;
1168 }
1169
1170 if (hsfs & HSFS_FCERR) {
1171 addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF;
1172 msg_perr("Transaction error between offset 0x%08x and "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001173 "0x%08x (= 0x%08x + %d)!\n",
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001174 addr, addr + len - 1, addr, len - 1);
1175 prettyprint_ich9_reg_hsfs(hsfs);
1176 prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC));
1177 return 1;
1178 }
1179 return 0;
1180}
Stefan Tauner50e7c602011-11-08 10:55:54 +00001181
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001182static int ich_hwseq_probe(struct flashctx *flash)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001183{
1184 uint32_t total_size, boundary;
1185 uint32_t erase_size_low, size_low, erase_size_high, size_high;
1186 struct block_eraser *eraser;
1187
1188 total_size = hwseq_data.size_comp0 + hwseq_data.size_comp1;
1189 msg_cdbg("Found %d attached SPI flash chip",
1190 (hwseq_data.size_comp1 != 0) ? 2 : 1);
1191 if (hwseq_data.size_comp1 != 0)
1192 msg_cdbg("s with a combined");
1193 else
1194 msg_cdbg(" with a");
1195 msg_cdbg(" density of %d kB.\n", total_size / 1024);
1196 flash->total_size = total_size / 1024;
1197
1198 eraser = &(flash->block_erasers[0]);
1199 boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12;
1200 size_high = total_size - boundary;
1201 erase_size_high = ich_hwseq_get_erase_block_size(boundary);
1202
1203 if (boundary == 0) {
1204 msg_cdbg("There is only one partition containing the whole "
1205 "address space (0x%06x - 0x%06x).\n", 0, size_high-1);
1206 eraser->eraseblocks[0].size = erase_size_high;
1207 eraser->eraseblocks[0].count = size_high / erase_size_high;
1208 msg_cdbg("There are %d erase blocks with %d B each.\n",
1209 size_high / erase_size_high, erase_size_high);
1210 } else {
1211 msg_cdbg("The flash address space (0x%06x - 0x%06x) is divided "
1212 "at address 0x%06x in two partitions.\n",
1213 0, size_high-1, boundary);
1214 size_low = total_size - size_high;
1215 erase_size_low = ich_hwseq_get_erase_block_size(0);
1216
1217 eraser->eraseblocks[0].size = erase_size_low;
1218 eraser->eraseblocks[0].count = size_low / erase_size_low;
1219 msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n",
1220 0, size_low-1);
1221 msg_cdbg("In that range are %d erase blocks with %d B each.\n",
1222 size_low / erase_size_low, erase_size_low);
1223
1224 eraser->eraseblocks[1].size = erase_size_high;
1225 eraser->eraseblocks[1].count = size_high / erase_size_high;
1226 msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n",
1227 boundary, size_high-1);
1228 msg_cdbg("In that range are %d erase blocks with %d B each.\n",
1229 size_high / erase_size_high, erase_size_high);
1230 }
1231 flash->tested = TEST_OK_PREW;
1232 return 1;
1233}
1234
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001235static int ich_hwseq_block_erase(struct flashctx *flash, unsigned int addr,
1236 unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001237{
1238 uint32_t erase_block;
1239 uint16_t hsfc;
1240 uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */
1241
1242 erase_block = ich_hwseq_get_erase_block_size(addr);
1243 if (len != erase_block) {
1244 msg_cerr("Erase block size for address 0x%06x is %d B, "
1245 "but requested erase block size is %d B. "
1246 "Not erasing anything.\n", addr, erase_block, len);
1247 return -1;
1248 }
1249
1250 /* Although the hardware supports this (it would erase the whole block
1251 * containing the address) we play safe here. */
1252 if (addr % erase_block != 0) {
1253 msg_cerr("Erase address 0x%06x is not aligned to the erase "
1254 "block boundary (any multiple of %d). "
1255 "Not erasing anything.\n", addr, erase_block);
1256 return -1;
1257 }
1258
1259 if (addr + len > flash->total_size * 1024) {
1260 msg_perr("Request to erase some inaccessible memory address(es)"
1261 " (addr=0x%x, len=%d). "
1262 "Not erasing anything.\n", addr, len);
1263 return -1;
1264 }
1265
1266 msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr);
1267
1268 /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
1269 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1270
1271 hsfc = REGREAD16(ICH9_REG_HSFC);
1272 hsfc &= ~HSFC_FCYCLE; /* clear operation */
1273 hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
1274 hsfc |= HSFC_FGO; /* start */
1275 msg_pdbg("HSFC used for block erasing: ");
1276 prettyprint_ich9_reg_hsfc(hsfc);
1277 REGWRITE16(ICH9_REG_HSFC, hsfc);
1278
1279 if (ich_hwseq_wait_for_cycle_complete(timeout, len))
1280 return -1;
1281 return 0;
1282}
1283
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001284static int ich_hwseq_read(struct flashctx *flash, uint8_t *buf,
1285 unsigned int addr, unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001286{
1287 uint16_t hsfc;
1288 uint16_t timeout = 100 * 60;
1289 uint8_t block_len;
1290
Paul Menzelac427b22012-02-16 21:07:07 +00001291 if (addr + len > flash->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001292 msg_perr("Request to read from an inaccessible memory address "
1293 "(addr=0x%x, len=%d).\n", addr, len);
1294 return -1;
1295 }
1296
1297 msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr);
1298 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
1299 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1300
1301 while (len > 0) {
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +00001302 block_len = min(len, flash->pgm->opaque.max_data_read);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001303 ich_hwseq_set_addr(addr);
1304 hsfc = REGREAD16(ICH9_REG_HSFC);
1305 hsfc &= ~HSFC_FCYCLE; /* set read operation */
1306 hsfc &= ~HSFC_FDBC; /* clear byte count */
1307 /* set byte count */
1308 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
1309 hsfc |= HSFC_FGO; /* start */
1310 REGWRITE16(ICH9_REG_HSFC, hsfc);
1311
1312 if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
1313 return 1;
1314 ich_read_data(buf, block_len, ICH9_REG_FDATA0);
1315 addr += block_len;
1316 buf += block_len;
1317 len -= block_len;
1318 }
1319 return 0;
1320}
1321
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001322static int ich_hwseq_write(struct flashctx *flash, uint8_t *buf,
1323 unsigned int addr, unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001324{
1325 uint16_t hsfc;
1326 uint16_t timeout = 100 * 60;
1327 uint8_t block_len;
1328
Paul Menzelac427b22012-02-16 21:07:07 +00001329 if (addr + len > flash->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001330 msg_perr("Request to write to an inaccessible memory address "
1331 "(addr=0x%x, len=%d).\n", addr, len);
1332 return -1;
1333 }
1334
1335 msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr);
1336 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
1337 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1338
1339 while (len > 0) {
1340 ich_hwseq_set_addr(addr);
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +00001341 block_len = min(len, flash->pgm->opaque.max_data_write);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001342 ich_fill_data(buf, block_len, ICH9_REG_FDATA0);
1343 hsfc = REGREAD16(ICH9_REG_HSFC);
1344 hsfc &= ~HSFC_FCYCLE; /* clear operation */
1345 hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */
1346 hsfc &= ~HSFC_FDBC; /* clear byte count */
1347 /* set byte count */
1348 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
1349 hsfc |= HSFC_FGO; /* start */
1350 REGWRITE16(ICH9_REG_HSFC, hsfc);
1351
1352 if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
1353 return -1;
1354 addr += block_len;
1355 buf += block_len;
1356 len -= block_len;
1357 }
1358 return 0;
1359}
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001360
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001361static int ich_spi_send_multicommand(struct flashctx *flash,
1362 struct spi_command *cmds)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001363{
1364 int ret = 0;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001365 int i;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001366 int oppos, preoppos;
1367 for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) {
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001368 if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001369 /* Next command is valid. */
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001370 preoppos = find_preop(curopcodes, cmds->writearr[0]);
1371 oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001372 if ((oppos == -1) && (preoppos != -1)) {
1373 /* Current command is listed as preopcode in
1374 * ICH struct OPCODES, but next command is not
1375 * listed as opcode in that struct.
1376 * Check for command sanity, then
1377 * try to reprogram the ICH opcode list.
1378 */
1379 if (find_preop(curopcodes,
1380 (cmds + 1)->writearr[0]) != -1) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001381 msg_perr("%s: Two subsequent "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001382 "preopcodes 0x%02x and 0x%02x, "
1383 "ignoring the first.\n",
1384 __func__, cmds->writearr[0],
1385 (cmds + 1)->writearr[0]);
1386 continue;
1387 }
1388 /* If the chipset is locked down, we'll fail
1389 * during execution of the next command anyway.
1390 * No need to bother with fixups.
1391 */
1392 if (!ichspi_lock) {
Helge Wagner738e2522010-10-05 22:06:05 +00001393 oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt);
1394 if (oppos == -1)
1395 continue;
1396 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001397 continue;
1398 }
1399 }
1400 if ((oppos != -1) && (preoppos != -1)) {
1401 /* Current command is listed as preopcode in
1402 * ICH struct OPCODES and next command is listed
1403 * as opcode in that struct. Match them up.
1404 */
1405 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001406 continue;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001407 }
1408 /* If none of the above if-statements about oppos or
1409 * preoppos matched, this is a normal opcode.
1410 */
1411 }
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001412 ret = ich_spi_send_command(flash, cmds->writecnt, cmds->readcnt,
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001413 cmds->writearr, cmds->readarr);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001414 /* Reset the type of all opcodes to non-atomic. */
1415 for (i = 0; i < 8; i++)
1416 curopcodes->opcode[i].atomic = 0;
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001417 }
1418 return ret;
1419}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001420
Michael Karchera4448d92010-07-22 18:04:15 +00001421#define ICH_BMWAG(x) ((x >> 24) & 0xff)
1422#define ICH_BMRAG(x) ((x >> 16) & 0xff)
1423#define ICH_BRWA(x) ((x >> 8) & 0xff)
1424#define ICH_BRRA(x) ((x >> 0) & 0xff)
1425
Stefan Tauner5210e722012-02-16 01:13:00 +00001426/* returns 0 if region is unused or r/w */
1427static int ich9_handle_frap(uint32_t frap, int i)
Michael Karchera4448d92010-07-22 18:04:15 +00001428{
Mathias Krausea60faab2011-01-17 07:50:42 +00001429 static const char *const access_names[4] = {
Michael Karchera4448d92010-07-22 18:04:15 +00001430 "locked", "read-only", "write-only", "read-write"
1431 };
Mathias Krausea60faab2011-01-17 07:50:42 +00001432 static const char *const region_names[5] = {
Michael Karchera4448d92010-07-22 18:04:15 +00001433 "Flash Descriptor", "BIOS", "Management Engine",
1434 "Gigabit Ethernet", "Platform Data"
1435 };
1436 uint32_t base, limit;
1437 int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) |
1438 (((ICH_BRRA(frap) >> i) & 1) << 0);
Stefan Tauner29c80832011-06-12 08:14:10 +00001439 int offset = ICH9_REG_FREG0 + i * 4;
Michael Karchera4448d92010-07-22 18:04:15 +00001440 uint32_t freg = mmio_readl(ich_spibar + offset);
1441
Michael Karchera4448d92010-07-22 18:04:15 +00001442 base = ICH_FREG_BASE(freg);
1443 limit = ICH_FREG_LIMIT(freg);
Joshua Roysd172ecd2011-05-26 13:30:51 +00001444 if (base > limit) {
Michael Karchera4448d92010-07-22 18:04:15 +00001445 /* this FREG is disabled */
Stefan Tauner5210e722012-02-16 01:13:00 +00001446 msg_pdbg2("0x%02X: 0x%08x FREG%i: %s region is unused.\n",
1447 offset, freg, i, region_names[i]);
1448 return 0;
1449 }
1450 msg_pdbg("0x%02X: 0x%08x ", offset, freg);
1451 if (rwperms == 0x3) {
1452 msg_pdbg("FREG%i: %s region (0x%08x-0x%08x) is %s.\n", i,
1453 region_names[i], base, (limit | 0x0fff),
1454 access_names[rwperms]);
1455 return 0;
Michael Karchera4448d92010-07-22 18:04:15 +00001456 }
1457
Stefan Tauner5210e722012-02-16 01:13:00 +00001458 msg_pinfo("FREG%i: WARNING: %s region (0x%08x-0x%08x) is %s.\n", i,
1459 region_names[i], base, (limit | 0x0fff),
1460 access_names[rwperms]);
1461 return 1;
Michael Karchera4448d92010-07-22 18:04:15 +00001462}
1463
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001464 /* In contrast to FRAP and the master section of the descriptor the bits
1465 * in the PR registers have an inverted meaning. The bits in FRAP
1466 * indicate read and write access _grant_. Here they indicate read
1467 * and write _protection_ respectively. If both bits are 0 the address
1468 * bits are ignored.
1469 */
1470#define ICH_PR_PERMS(pr) (((~((pr) >> PR_RP_OFF) & 1) << 0) | \
1471 ((~((pr) >> PR_WP_OFF) & 1) << 1))
1472
Stefan Tauner5210e722012-02-16 01:13:00 +00001473/* returns 0 if range is unused (i.e. r/w) */
1474static int ich9_handle_pr(int i)
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001475{
Stefan Tauner5210e722012-02-16 01:13:00 +00001476 static const char *const access_names[3] = {
1477 "locked", "read-only", "write-only"
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001478 };
1479 uint8_t off = ICH9_REG_PR0 + (i * 4);
1480 uint32_t pr = mmio_readl(ich_spibar + off);
Stefan Tauner5210e722012-02-16 01:13:00 +00001481 unsigned int rwperms = ICH_PR_PERMS(pr);
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001482
Stefan Tauner5210e722012-02-16 01:13:00 +00001483 if (rwperms == 0x3) {
1484 msg_pdbg2("0x%02X: 0x%08x (PR%u is unused)\n", off, pr, i);
1485 return 0;
1486 }
1487
1488 msg_pdbg("0x%02X: 0x%08x ", off, pr);
1489 msg_pinfo("PR%u: WARNING: 0x%08x-0x%08x is %s.\n", i, ICH_FREG_BASE(pr),
1490 ICH_FREG_LIMIT(pr) | 0x0fff, access_names[rwperms]);
1491 return 1;
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001492}
1493
Stefan Tauner75da80c2011-09-17 22:21:55 +00001494/* Set/Clear the read and write protection enable bits of PR register @i
1495 * according to @read_prot and @write_prot. */
1496static void ich9_set_pr(int i, int read_prot, int write_prot)
1497{
1498 void *addr = ich_spibar + ICH9_REG_PR0 + (i * 4);
1499 uint32_t old = mmio_readl(addr);
1500 uint32_t new;
1501
1502 msg_gspew("PR%u is 0x%08x", i, old);
1503 new = old & ~((1 << PR_RP_OFF) | (1 << PR_WP_OFF));
1504 if (read_prot)
1505 new |= (1 << PR_RP_OFF);
1506 if (write_prot)
1507 new |= (1 << PR_WP_OFF);
1508 if (old == new) {
1509 msg_gspew(" already.\n");
1510 return;
1511 }
1512 msg_gspew(", trying to set it to 0x%08x ", new);
1513 rmmio_writel(new, addr);
1514 msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr));
1515}
1516
Michael Karcherb9dbe482011-05-11 17:07:07 +00001517static const struct spi_programmer spi_programmer_ich7 = {
1518 .type = SPI_CONTROLLER_ICH7,
1519 .max_data_read = 64,
1520 .max_data_write = 64,
1521 .command = ich_spi_send_command,
1522 .multicommand = ich_spi_send_multicommand,
1523 .read = default_spi_read,
1524 .write_256 = default_spi_write_256,
Nico Huber7bca1262012-06-15 22:28:12 +00001525 .write_aai = default_spi_write_aai,
Michael Karcherb9dbe482011-05-11 17:07:07 +00001526};
1527
1528static const struct spi_programmer spi_programmer_ich9 = {
1529 .type = SPI_CONTROLLER_ICH9,
1530 .max_data_read = 64,
1531 .max_data_write = 64,
1532 .command = ich_spi_send_command,
1533 .multicommand = ich_spi_send_multicommand,
1534 .read = default_spi_read,
1535 .write_256 = default_spi_write_256,
Nico Huber7bca1262012-06-15 22:28:12 +00001536 .write_aai = default_spi_write_aai,
Michael Karcherb9dbe482011-05-11 17:07:07 +00001537};
1538
Stefan Tauner50e7c602011-11-08 10:55:54 +00001539static const struct opaque_programmer opaque_programmer_ich_hwseq = {
1540 .max_data_read = 64,
1541 .max_data_write = 64,
1542 .probe = ich_hwseq_probe,
1543 .read = ich_hwseq_read,
1544 .write = ich_hwseq_write,
1545 .erase = ich_hwseq_block_erase,
1546};
1547
Michael Karchera4448d92010-07-22 18:04:15 +00001548int ich_init_spi(struct pci_dev *dev, uint32_t base, void *rcrb,
Stefan Taunera8d838d2011-11-06 23:51:09 +00001549 enum ich_chipset ich_gen)
Michael Karchera4448d92010-07-22 18:04:15 +00001550{
1551 int i;
1552 uint8_t old, new;
1553 uint16_t spibar_offset, tmp2;
1554 uint32_t tmp;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001555 char *arg;
Stefan Tauner5210e722012-02-16 01:13:00 +00001556 int ich_spi_force = 0;
1557 int ich_spi_rw_restricted = 0;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001558 int desc_valid = 0;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001559 struct ich_descriptors desc = {{ 0 }};
1560 enum ich_spi_mode {
1561 ich_auto,
1562 ich_hwseq,
1563 ich_swseq
1564 } ich_spi_mode = ich_auto;
Michael Karchera4448d92010-07-22 18:04:15 +00001565
Stefan Taunera8d838d2011-11-06 23:51:09 +00001566 ich_generation = ich_gen;
1567
Michael Karchera4448d92010-07-22 18:04:15 +00001568 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +00001569 case CHIPSET_ICH_UNKNOWN:
Stefan Tauner50e7c602011-11-08 10:55:54 +00001570 return ERROR_FATAL;
Stefan Taunera8d838d2011-11-06 23:51:09 +00001571 case CHIPSET_ICH7:
1572 case CHIPSET_ICH8:
Michael Karchera4448d92010-07-22 18:04:15 +00001573 spibar_offset = 0x3020;
1574 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +00001575 case CHIPSET_ICH9:
Michael Karchera4448d92010-07-22 18:04:15 +00001576 default: /* Future version might behave the same */
Michael Karchera4448d92010-07-22 18:04:15 +00001577 spibar_offset = 0x3800;
1578 break;
1579 }
1580
1581 /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
1582 msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", base, spibar_offset);
1583
1584 /* Assign Virtual Address */
1585 ich_spibar = rcrb + spibar_offset;
1586
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001587 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +00001588 case CHIPSET_ICH7:
Michael Karchera4448d92010-07-22 18:04:15 +00001589 msg_pdbg("0x00: 0x%04x (SPIS)\n",
1590 mmio_readw(ich_spibar + 0));
1591 msg_pdbg("0x02: 0x%04x (SPIC)\n",
1592 mmio_readw(ich_spibar + 2));
1593 msg_pdbg("0x04: 0x%08x (SPIA)\n",
1594 mmio_readl(ich_spibar + 4));
1595 for (i = 0; i < 8; i++) {
1596 int offs;
1597 offs = 8 + (i * 8);
1598 msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs,
1599 mmio_readl(ich_spibar + offs), i);
1600 msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
1601 mmio_readl(ich_spibar + offs + 4), i);
1602 }
1603 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
1604 msg_pdbg("0x50: 0x%08x (BBAR)\n",
1605 ichspi_bbar);
1606 msg_pdbg("0x54: 0x%04x (PREOP)\n",
1607 mmio_readw(ich_spibar + 0x54));
1608 msg_pdbg("0x56: 0x%04x (OPTYPE)\n",
1609 mmio_readw(ich_spibar + 0x56));
1610 msg_pdbg("0x58: 0x%08x (OPMENU)\n",
1611 mmio_readl(ich_spibar + 0x58));
1612 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n",
1613 mmio_readl(ich_spibar + 0x5c));
Stefan Tauner122dd122011-07-24 15:34:56 +00001614 for (i = 0; i < 3; i++) {
Michael Karchera4448d92010-07-22 18:04:15 +00001615 int offs;
1616 offs = 0x60 + (i * 4);
1617 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
1618 mmio_readl(ich_spibar + offs), i);
1619 }
Michael Karchera4448d92010-07-22 18:04:15 +00001620 if (mmio_readw(ich_spibar) & (1 << 15)) {
1621 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
1622 ichspi_lock = 1;
1623 }
Stefan Tauner745f6bb2011-11-13 15:17:10 +00001624 ich_init_opcodes();
Stefan Taunera8d838d2011-11-06 23:51:09 +00001625 ich_set_bbar(0);
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001626 register_spi_programmer(&spi_programmer_ich7);
Michael Karchera4448d92010-07-22 18:04:15 +00001627 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +00001628 case CHIPSET_ICH8:
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001629 default: /* Future version might behave the same */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001630 arg = extract_programmer_param("ich_spi_mode");
1631 if (arg && !strcmp(arg, "hwseq")) {
1632 ich_spi_mode = ich_hwseq;
1633 msg_pspew("user selected hwseq\n");
1634 } else if (arg && !strcmp(arg, "swseq")) {
1635 ich_spi_mode = ich_swseq;
1636 msg_pspew("user selected swseq\n");
1637 } else if (arg && !strcmp(arg, "auto")) {
1638 msg_pspew("user selected auto\n");
1639 ich_spi_mode = ich_auto;
1640 } else if (arg && !strlen(arg)) {
1641 msg_perr("Missing argument for ich_spi_mode.\n");
1642 free(arg);
1643 return ERROR_FATAL;
1644 } else if (arg) {
1645 msg_perr("Unknown argument for ich_spi_mode: %s\n",
1646 arg);
1647 free(arg);
1648 return ERROR_FATAL;
1649 }
1650 free(arg);
1651
Stefan Tauner5210e722012-02-16 01:13:00 +00001652 arg = extract_programmer_param("ich_spi_force");
1653 if (arg && !strcmp(arg, "yes")) {
1654 ich_spi_force = 1;
1655 msg_pspew("ich_spi_force enabled.\n");
1656 } else if (arg && !strlen(arg)) {
1657 msg_perr("Missing argument for ich_spi_force.\n");
1658 free(arg);
1659 return ERROR_FATAL;
1660 } else if (arg) {
1661 msg_perr("Unknown argument for ich_spi_force: \"%s\" "
1662 "(not \"yes\").\n", arg);
1663 free(arg);
1664 return ERROR_FATAL;
1665 }
1666 free(arg);
1667
Stefan Tauner29c80832011-06-12 08:14:10 +00001668 tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS);
Michael Karchera4448d92010-07-22 18:04:15 +00001669 msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2);
Stefan Tauner55206942011-06-11 09:53:22 +00001670 prettyprint_ich9_reg_hsfs(tmp2);
Stefan Tauner29c80832011-06-12 08:14:10 +00001671 if (tmp2 & HSFS_FLOCKDN) {
Stefan Tauner55206942011-06-11 09:53:22 +00001672 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
1673 ichspi_lock = 1;
1674 }
Stefan Tauner1e146392011-09-15 23:52:55 +00001675 if (tmp2 & HSFS_FDV)
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001676 desc_valid = 1;
1677 if (!(tmp2 & HSFS_FDOPSS) && desc_valid)
Stefan Taunere3185c02011-09-18 15:15:31 +00001678 msg_pinfo("The Flash Descriptor Security Override "
1679 "Strap-Pin is set. Restrictions implied\n"
1680 "by the FRAP and FREG registers are NOT in "
1681 "effect. Please note that Protected\n"
1682 "Range (PR) restrictions still apply.\n");
Stefan Tauner745f6bb2011-11-13 15:17:10 +00001683 ich_init_opcodes();
Stefan Tauner55206942011-06-11 09:53:22 +00001684
Stefan Taunerf382e352011-11-08 11:55:24 +00001685 if (desc_valid) {
1686 tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC);
1687 msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2);
1688 prettyprint_ich9_reg_hsfc(tmp2);
1689 }
Michael Karchera4448d92010-07-22 18:04:15 +00001690
Stefan Tauner5ffe65b2011-07-07 04:10:57 +00001691 tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR);
1692 msg_pdbg("0x08: 0x%08x (FADDR)\n", tmp);
Michael Karchera4448d92010-07-22 18:04:15 +00001693
Stefan Taunerf382e352011-11-08 11:55:24 +00001694 if (desc_valid) {
1695 tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP);
1696 msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp);
1697 msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp));
1698 msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp));
1699 msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp));
1700 msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp));
1701
Stefan Tauner5210e722012-02-16 01:13:00 +00001702 /* Handle FREGx and FRAP registers */
Stefan Taunerf382e352011-11-08 11:55:24 +00001703 for (i = 0; i < 5; i++)
Stefan Tauner5210e722012-02-16 01:13:00 +00001704 ich_spi_rw_restricted |= ich9_handle_frap(tmp, i);
Stefan Taunerf382e352011-11-08 11:55:24 +00001705 }
Michael Karchera4448d92010-07-22 18:04:15 +00001706
Stefan Tauner5210e722012-02-16 01:13:00 +00001707 for (i = 0; i < 5; i++) {
1708 /* if not locked down try to disable PR locks first */
1709 if (!ichspi_lock)
Stefan Tauner75da80c2011-09-17 22:21:55 +00001710 ich9_set_pr(i, 0, 0);
Stefan Tauner5210e722012-02-16 01:13:00 +00001711 ich_spi_rw_restricted |= ich9_handle_pr(i);
1712 }
1713
1714 if (ich_spi_rw_restricted) {
1715 msg_pinfo("Please send a verbose log to "
1716 "flashrom@flashrom.org if this board is not "
1717 "listed on\n"
1718 "http://flashrom.org/Supported_hardware#Supported_mainboards "
1719 "yet.\n");
1720 if (!ich_spi_force)
1721 programmer_may_write = 0;
1722 msg_pinfo("Writes have been disabled. You can enforce "
1723 "write support with the\nich_spi_force "
1724 "programmer option, but it will most likely "
1725 "harm your hardware!\nIf you force flashrom "
1726 "you will get no support if something "
1727 "breaks.\n");
1728 if (ich_spi_force)
1729 msg_pinfo("Continuing with write support "
1730 "because the user forced us to!\n");
1731 }
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001732
Stefan Tauner29c80832011-06-12 08:14:10 +00001733 tmp = mmio_readl(ich_spibar + ICH9_REG_SSFS);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001734 msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff);
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001735 prettyprint_ich9_reg_ssfs(tmp);
Stefan Tauner29c80832011-06-12 08:14:10 +00001736 if (tmp & SSFS_FCERR) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001737 msg_pdbg("Clearing SSFS.FCERR\n");
Stefan Tauner29c80832011-06-12 08:14:10 +00001738 mmio_writeb(SSFS_FCERR, ich_spibar + ICH9_REG_SSFS);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001739 }
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001740 msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp >> 8);
1741 prettyprint_ich9_reg_ssfc(tmp);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001742
Michael Karchera4448d92010-07-22 18:04:15 +00001743 msg_pdbg("0x94: 0x%04x (PREOP)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001744 mmio_readw(ich_spibar + ICH9_REG_PREOP));
Michael Karchera4448d92010-07-22 18:04:15 +00001745 msg_pdbg("0x96: 0x%04x (OPTYPE)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001746 mmio_readw(ich_spibar + ICH9_REG_OPTYPE));
Michael Karchera4448d92010-07-22 18:04:15 +00001747 msg_pdbg("0x98: 0x%08x (OPMENU)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001748 mmio_readl(ich_spibar + ICH9_REG_OPMENU));
Michael Karchera4448d92010-07-22 18:04:15 +00001749 msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001750 mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4));
Stefan Taunerf382e352011-11-08 11:55:24 +00001751 if (ich_generation == CHIPSET_ICH8 && desc_valid) {
Stefan Tauner1e146392011-09-15 23:52:55 +00001752 tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC);
1753 msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp);
1754 msg_pdbg("VSCC: ");
1755 prettyprint_ich_reg_vscc(tmp, MSG_DEBUG);
1756 } else {
1757 ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR);
1758 msg_pdbg("0xA0: 0x%08x (BBAR)\n",
1759 ichspi_bbar);
Stefan Taunerbd649e42011-07-01 00:39:16 +00001760
Stefan Taunerf382e352011-11-08 11:55:24 +00001761 if (desc_valid) {
1762 tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC);
1763 msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp);
1764 msg_pdbg("LVSCC: ");
1765 prettyprint_ich_reg_vscc(tmp, MSG_DEBUG);
Stefan Tauner1e146392011-09-15 23:52:55 +00001766
Stefan Taunerf382e352011-11-08 11:55:24 +00001767 tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC);
1768 msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp);
1769 msg_pdbg("UVSCC: ");
1770 prettyprint_ich_reg_vscc(tmp, MSG_DEBUG);
Stefan Tauner1e146392011-09-15 23:52:55 +00001771
Stefan Taunerf382e352011-11-08 11:55:24 +00001772 tmp = mmio_readl(ich_spibar + ICH9_REG_FPB);
1773 msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp);
1774 }
Stefan Taunera8d838d2011-11-06 23:51:09 +00001775 ich_set_bbar(0);
Stefan Tauner1e146392011-09-15 23:52:55 +00001776 }
1777
1778 msg_pdbg("\n");
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001779 if (desc_valid) {
Stefan Tauner1e146392011-09-15 23:52:55 +00001780 if (read_ich_descriptors_via_fdo(ich_spibar, &desc) ==
1781 ICH_RET_OK)
1782 prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN,
1783 &desc);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001784 /* If the descriptor is valid and indicates multiple
1785 * flash devices we need to use hwseq to be able to
1786 * access the second flash device.
1787 */
1788 if (ich_spi_mode == ich_auto && desc.content.NC != 0) {
1789 msg_pinfo("Enabling hardware sequencing due to "
1790 "multiple flash chips detected.\n");
1791 ich_spi_mode = ich_hwseq;
1792 }
Stefan Tauner1e146392011-09-15 23:52:55 +00001793 }
Stefan Tauner50e7c602011-11-08 10:55:54 +00001794
1795 if (ich_spi_mode == ich_auto && ichspi_lock &&
1796 ich_missing_opcodes()) {
1797 msg_pinfo("Enabling hardware sequencing because "
1798 "some important opcode is locked.\n");
1799 ich_spi_mode = ich_hwseq;
1800 }
1801
1802 if (ich_spi_mode == ich_hwseq) {
1803 if (!desc_valid) {
1804 msg_perr("Hardware sequencing was requested "
1805 "but the flash descriptor is not "
1806 "valid. Aborting.\n");
1807 return ERROR_FATAL;
1808 }
1809 hwseq_data.size_comp0 = getFCBA_component_density(&desc, 0);
1810 hwseq_data.size_comp1 = getFCBA_component_density(&desc, 1);
1811 register_opaque_programmer(&opaque_programmer_ich_hwseq);
1812 } else {
1813 register_spi_programmer(&spi_programmer_ich9);
1814 }
Michael Karchera4448d92010-07-22 18:04:15 +00001815 break;
Michael Karchera4448d92010-07-22 18:04:15 +00001816 }
1817
1818 old = pci_read_byte(dev, 0xdc);
1819 msg_pdbg("SPI Read Configuration: ");
1820 new = (old >> 2) & 0x3;
1821 switch (new) {
1822 case 0:
1823 case 1:
1824 case 2:
1825 msg_pdbg("prefetching %sabled, caching %sabled, ",
1826 (new & 0x2) ? "en" : "dis",
1827 (new & 0x1) ? "dis" : "en");
1828 break;
1829 default:
1830 msg_pdbg("invalid prefetching/caching settings, ");
1831 break;
1832 }
1833 return 0;
1834}
1835
Michael Karcherb9dbe482011-05-11 17:07:07 +00001836static const struct spi_programmer spi_programmer_via = {
1837 .type = SPI_CONTROLLER_VIA,
1838 .max_data_read = 16,
1839 .max_data_write = 16,
1840 .command = ich_spi_send_command,
1841 .multicommand = ich_spi_send_multicommand,
1842 .read = default_spi_read,
1843 .write_256 = default_spi_write_256,
Nico Huber7bca1262012-06-15 22:28:12 +00001844 .write_aai = default_spi_write_aai,
Michael Karcherb9dbe482011-05-11 17:07:07 +00001845};
1846
Michael Karchera4448d92010-07-22 18:04:15 +00001847int via_init_spi(struct pci_dev *dev)
1848{
1849 uint32_t mmio_base;
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00001850 int i;
Michael Karchera4448d92010-07-22 18:04:15 +00001851
1852 mmio_base = (pci_read_long(dev, 0xbc)) << 8;
1853 msg_pdbg("MMIO base at = 0x%x\n", mmio_base);
1854 ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70);
1855
Michael Karchera4448d92010-07-22 18:04:15 +00001856 /* Not sure if it speaks all these bus protocols. */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001857 internal_buses_supported = BUS_LPC | BUS_FWH;
Stefan Taunera8d838d2011-11-06 23:51:09 +00001858 ich_generation = CHIPSET_ICH7;
Michael Karcherb9dbe482011-05-11 17:07:07 +00001859 register_spi_programmer(&spi_programmer_via);
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00001860
1861 msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0));
1862 msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2));
1863 msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(ich_spibar + 4));
1864 for (i = 0; i < 2; i++) {
1865 int offs;
1866 offs = 8 + (i * 8);
1867 msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs,
1868 mmio_readl(ich_spibar + offs), i);
1869 msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
1870 mmio_readl(ich_spibar + offs + 4), i);
1871 }
1872 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
1873 msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar);
1874 msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x54));
1875 msg_pdbg("0x56: 0x%04x (OPTYPE)\n", mmio_readw(ich_spibar + 0x56));
1876 msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(ich_spibar + 0x58));
1877 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + 0x5c));
1878 for (i = 0; i < 3; i++) {
1879 int offs;
1880 offs = 0x60 + (i * 4);
1881 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
1882 mmio_readl(ich_spibar + offs), i);
1883 }
1884 msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n",
1885 mmio_readw(ich_spibar + 0x6c));
1886 if (mmio_readw(ich_spibar) & (1 << 15)) {
1887 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
1888 ichspi_lock = 1;
1889 }
1890
Stefan Taunera8d838d2011-11-06 23:51:09 +00001891 ich_set_bbar(0);
Michael Karchera4448d92010-07-22 18:04:15 +00001892 ich_init_opcodes();
1893
1894 return 0;
1895}
1896
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001897#endif