blob: 90bb0de7e27def4aa383608d151a7048d10065d5 [file] [log] [blame]
Dominik Geyerb46acba2008-05-16 12:55:55 +00001/*
2 * This file is part of the flashrom project.
3 *
4 * Copyright (C) 2008 Stefan Wildemann <stefan.wildemann@kontron.com>
5 * Copyright (C) 2008 Claus Gindhart <claus.gindhart@kontron.com>
6 * Copyright (C) 2008 Dominik Geyer <dominik.geyer@kontron.com>
Stefan Reinauera9424d52008-06-27 16:28:34 +00007 * Copyright (C) 2008 coresystems GmbH <info@coresystems.de>
Carl-Daniel Hailfinger5824fbf2010-05-21 23:09:42 +00008 * Copyright (C) 2009, 2010 Carl-Daniel Hailfinger
Stefan Tauner8b391b82011-08-09 01:49:34 +00009 * Copyright (C) 2011 Stefan Tauner
Dominik Geyerb46acba2008-05-16 12:55:55 +000010 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Dominik Geyerb46acba2008-05-16 12:55:55 +000024 */
25
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000026#if defined(__i386__) || defined(__x86_64__)
27
Dominik Geyerb46acba2008-05-16 12:55:55 +000028#include <string.h>
Stefan Taunerd0c5dc22011-10-20 12:57:14 +000029#include <stdlib.h>
Dominik Geyerb46acba2008-05-16 12:55:55 +000030#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000031#include "programmer.h"
Patrick Georgi32508eb2012-07-20 20:35:14 +000032#include "hwaccess.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000033#include "spi.h"
Stefan Tauner1e146392011-09-15 23:52:55 +000034#include "ich_descriptors.h"
Dominik Geyerb46acba2008-05-16 12:55:55 +000035
Stefan Reinauera9424d52008-06-27 16:28:34 +000036/* ICH9 controller register definition */
Stefan Tauner55206942011-06-11 09:53:22 +000037#define ICH9_REG_HSFS 0x04 /* 16 Bits Hardware Sequencing Flash Status */
38#define HSFS_FDONE_OFF 0 /* 0: Flash Cycle Done */
39#define HSFS_FDONE (0x1 << HSFS_FDONE_OFF)
40#define HSFS_FCERR_OFF 1 /* 1: Flash Cycle Error */
41#define HSFS_FCERR (0x1 << HSFS_FCERR_OFF)
42#define HSFS_AEL_OFF 2 /* 2: Access Error Log */
43#define HSFS_AEL (0x1 << HSFS_AEL_OFF)
44#define HSFS_BERASE_OFF 3 /* 3-4: Block/Sector Erase Size */
45#define HSFS_BERASE (0x3 << HSFS_BERASE_OFF)
46#define HSFS_SCIP_OFF 5 /* 5: SPI Cycle In Progress */
47#define HSFS_SCIP (0x1 << HSFS_SCIP_OFF)
48 /* 6-12: reserved */
49#define HSFS_FDOPSS_OFF 13 /* 13: Flash Descriptor Override Pin-Strap Status */
50#define HSFS_FDOPSS (0x1 << HSFS_FDOPSS_OFF)
51#define HSFS_FDV_OFF 14 /* 14: Flash Descriptor Valid */
52#define HSFS_FDV (0x1 << HSFS_FDV_OFF)
53#define HSFS_FLOCKDN_OFF 15 /* 15: Flash Configuration Lock-Down */
54#define HSFS_FLOCKDN (0x1 << HSFS_FLOCKDN_OFF)
55
56#define ICH9_REG_HSFC 0x06 /* 16 Bits Hardware Sequencing Flash Control */
57#define HSFC_FGO_OFF 0 /* 0: Flash Cycle Go */
58#define HSFC_FGO (0x1 << HSFC_FGO_OFF)
59#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
60#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
61 /* 3-7: reserved */
62#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
63#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF)
64 /* 14: reserved */
65#define HSFC_SME_OFF 15 /* 15: SPI SMI# Enable */
66#define HSFC_SME (0x1 << HSFC_SME_OFF)
67
Stefan Taunerc0aaf952011-05-19 02:58:17 +000068#define ICH9_REG_FADDR 0x08 /* 32 Bits */
69#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
Stefan Reinauera9424d52008-06-27 16:28:34 +000070
Stefan Tauner29c80832011-06-12 08:14:10 +000071#define ICH9_REG_FRAP 0x50 /* 32 Bytes Flash Region Access Permissions */
72#define ICH9_REG_FREG0 0x54 /* 32 Bytes Flash Region 0 */
73
74#define ICH9_REG_PR0 0x74 /* 32 Bytes Protected Range 0 */
Stefan Taunerbf69aaa2011-09-17 21:21:48 +000075#define PR_WP_OFF 31 /* 31: write protection enable */
76#define PR_RP_OFF 15 /* 15: read protection enable */
Stefan Tauner29c80832011-06-12 08:14:10 +000077
Stefan Taunerc0aaf952011-05-19 02:58:17 +000078#define ICH9_REG_SSFS 0x90 /* 08 Bits */
Stefan Tauner0c1ec452011-06-11 09:53:09 +000079#define SSFS_SCIP_OFF 0 /* SPI Cycle In Progress */
80#define SSFS_SCIP (0x1 << SSFS_SCIP_OFF)
81#define SSFS_FDONE_OFF 2 /* Cycle Done Status */
82#define SSFS_FDONE (0x1 << SSFS_FDONE_OFF)
83#define SSFS_FCERR_OFF 3 /* Flash Cycle Error */
84#define SSFS_FCERR (0x1 << SSFS_FCERR_OFF)
85#define SSFS_AEL_OFF 4 /* Access Error Log */
86#define SSFS_AEL (0x1 << SSFS_AEL_OFF)
Stefan Taunerc0aaf952011-05-19 02:58:17 +000087/* The following bits are reserved in SSFS: 1,5-7. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +000088#define SSFS_RESERVED_MASK 0x000000e2
Stefan Reinauera9424d52008-06-27 16:28:34 +000089
Stefan Taunerc0aaf952011-05-19 02:58:17 +000090#define ICH9_REG_SSFC 0x91 /* 24 Bits */
Stefan Taunerc0aaf952011-05-19 02:58:17 +000091/* We combine SSFS and SSFC to one 32-bit word,
Stefan Tauner0c1ec452011-06-11 09:53:09 +000092 * therefore SSFC bits are off by 8. */
93 /* 0: reserved */
94#define SSFC_SCGO_OFF (1 + 8) /* 1: SPI Cycle Go */
95#define SSFC_SCGO (0x1 << SSFC_SCGO_OFF)
96#define SSFC_ACS_OFF (2 + 8) /* 2: Atomic Cycle Sequence */
97#define SSFC_ACS (0x1 << SSFC_ACS_OFF)
98#define SSFC_SPOP_OFF (3 + 8) /* 3: Sequence Prefix Opcode Pointer */
99#define SSFC_SPOP (0x1 << SSFC_SPOP_OFF)
100#define SSFC_COP_OFF (4 + 8) /* 4-6: Cycle Opcode Pointer */
101#define SSFC_COP (0x7 << SSFC_COP_OFF)
102 /* 7: reserved */
103#define SSFC_DBC_OFF (8 + 8) /* 8-13: Data Byte Count */
104#define SSFC_DBC (0x3f << SSFC_DBC_OFF)
105#define SSFC_DS_OFF (14 + 8) /* 14: Data Cycle */
106#define SSFC_DS (0x1 << SSFC_DS_OFF)
107#define SSFC_SME_OFF (15 + 8) /* 15: SPI SMI# Enable */
108#define SSFC_SME (0x1 << SSFC_SME_OFF)
109#define SSFC_SCF_OFF (16 + 8) /* 16-18: SPI Cycle Frequency */
110#define SSFC_SCF (0x7 << SSFC_SCF_OFF)
111#define SSFC_SCF_20MHZ 0x00000000
112#define SSFC_SCF_33MHZ 0x01000000
113 /* 19-23: reserved */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000114#define SSFC_RESERVED_MASK 0xf8008100
Stefan Reinauera9424d52008-06-27 16:28:34 +0000115
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000116#define ICH9_REG_PREOP 0x94 /* 16 Bits */
117#define ICH9_REG_OPTYPE 0x96 /* 16 Bits */
118#define ICH9_REG_OPMENU 0x98 /* 64 Bits */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000119
Stefan Tauner29c80832011-06-12 08:14:10 +0000120#define ICH9_REG_BBAR 0xA0 /* 32 Bits BIOS Base Address Configuration */
121#define BBAR_MASK 0x00ffff00 /* 8-23: Bottom of System Flash */
122
Stefan Tauner1e146392011-09-15 23:52:55 +0000123#define ICH8_REG_VSCC 0xC1 /* 32 Bits Vendor Specific Component Capabilities */
124#define ICH9_REG_LVSCC 0xC4 /* 32 Bits Host Lower Vendor Specific Component Capabilities */
125#define ICH9_REG_UVSCC 0xC8 /* 32 Bits Host Upper Vendor Specific Component Capabilities */
126/* The individual fields of the VSCC registers are defined in the file
127 * ich_descriptors.h. The reason is that the same layout is also used in the
128 * flash descriptor to define the properties of the different flash chips
129 * supported. The BIOS (or the ME?) is responsible to populate the ICH registers
130 * with the information from the descriptor on startup depending on the actual
131 * chip(s) detected. */
132
Stefan Taunerbd649e42011-07-01 00:39:16 +0000133#define ICH9_REG_FPB 0xD0 /* 32 Bits Flash Partition Boundary */
134#define FPB_FPBA_OFF 0 /* 0-12: Block/Sector Erase Size */
135#define FPB_FPBA (0x1FFF << FPB_FPBA_OFF)
136
Dominik Geyerb46acba2008-05-16 12:55:55 +0000137// ICH9R SPI commands
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000138#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
139#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
140#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
141#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
Dominik Geyerb46acba2008-05-16 12:55:55 +0000142
Stefan Reinauera9424d52008-06-27 16:28:34 +0000143// ICH7 registers
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000144#define ICH7_REG_SPIS 0x00 /* 16 Bits */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000145#define SPIS_SCIP 0x0001
146#define SPIS_GRANT 0x0002
147#define SPIS_CDS 0x0004
148#define SPIS_FCERR 0x0008
149#define SPIS_RESERVED_MASK 0x7ff0
Stefan Reinauera9424d52008-06-27 16:28:34 +0000150
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000151/* VIA SPI is compatible with ICH7, but maxdata
152 to transfer is 16 bytes.
153
154 DATA byte count on ICH7 is 8:13, on VIA 8:11
155
156 bit 12 is port select CS0 CS1
157 bit 13 is FAST READ enable
158 bit 7 is used with fast read and one shot controls CS de-assert?
159*/
160
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000161#define ICH7_REG_SPIC 0x02 /* 16 Bits */
162#define SPIC_SCGO 0x0002
163#define SPIC_ACS 0x0004
164#define SPIC_SPOP 0x0008
165#define SPIC_DS 0x4000
Stefan Reinauera9424d52008-06-27 16:28:34 +0000166
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000167#define ICH7_REG_SPIA 0x04 /* 32 Bits */
168#define ICH7_REG_SPID0 0x08 /* 64 Bytes */
169#define ICH7_REG_PREOP 0x54 /* 16 Bits */
170#define ICH7_REG_OPTYPE 0x56 /* 16 Bits */
171#define ICH7_REG_OPMENU 0x58 /* 64 Bits */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000172
FENG yu ningc05a2952008-12-08 18:16:58 +0000173/* ICH SPI configuration lock-down. May be set during chipset enabling. */
Michael Karchera4448d92010-07-22 18:04:15 +0000174static int ichspi_lock = 0;
FENG yu ningc05a2952008-12-08 18:16:58 +0000175
Stefan Taunera8d838d2011-11-06 23:51:09 +0000176static enum ich_chipset ich_generation = CHIPSET_ICH_UNKNOWN;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000177uint32_t ichspi_bbar = 0;
178
Michael Karchera4448d92010-07-22 18:04:15 +0000179static void *ich_spibar = NULL;
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000180
Dominik Geyerb46acba2008-05-16 12:55:55 +0000181typedef struct _OPCODE {
182 uint8_t opcode; //This commands spi opcode
183 uint8_t spi_type; //This commands spi type
184 uint8_t atomic; //Use preop: (0: none, 1: preop0, 2: preop1
185} OPCODE;
186
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000187/* Suggested opcode definition:
Dominik Geyerb46acba2008-05-16 12:55:55 +0000188 * Preop 1: Write Enable
189 * Preop 2: Write Status register enable
190 *
191 * OP 0: Write address
192 * OP 1: Read Address
193 * OP 2: ERASE block
194 * OP 3: Read Status register
195 * OP 4: Read ID
196 * OP 5: Write Status register
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000197 * OP 6: chip private (read JEDEC id)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000198 * OP 7: Chip erase
199 */
200typedef struct _OPCODES {
201 uint8_t preop[2];
202 OPCODE opcode[8];
203} OPCODES;
204
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000205static OPCODES *curopcodes = NULL;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000206
207/* HW access functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000208static uint32_t REGREAD32(int X)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000209{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000210 return mmio_readl(ich_spibar + X);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000211}
212
Uwe Hermann09e04f72009-05-16 22:36:00 +0000213static uint16_t REGREAD16(int X)
Stefan Reinauera9424d52008-06-27 16:28:34 +0000214{
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000215 return mmio_readw(ich_spibar + X);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000216}
217
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000218static uint16_t REGREAD8(int X)
219{
220 return mmio_readb(ich_spibar + X);
221}
222
Stefan Taunerccd92a12011-07-01 00:39:01 +0000223#define REGWRITE32(off, val) mmio_writel(val, ich_spibar+(off))
224#define REGWRITE16(off, val) mmio_writew(val, ich_spibar+(off))
225#define REGWRITE8(off, val) mmio_writeb(val, ich_spibar+(off))
Dominik Geyerb46acba2008-05-16 12:55:55 +0000226
Dominik Geyerb46acba2008-05-16 12:55:55 +0000227/* Common SPI functions */
Uwe Hermann09e04f72009-05-16 22:36:00 +0000228static int find_opcode(OPCODES *op, uint8_t opcode);
229static int find_preop(OPCODES *op, uint8_t preop);
FENG yu ningf041e9b2008-12-15 02:32:11 +0000230static int generate_opcodes(OPCODES * op);
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000231static int program_opcodes(OPCODES *op, int enable_undo);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000232static int run_opcode(const struct flashctx *flash, OPCODE op, uint32_t offset,
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000233 uint8_t datalength, uint8_t * data);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000234
FENG yu ningf041e9b2008-12-15 02:32:11 +0000235/* for pairing opcodes with their required preop */
236struct preop_opcode_pair {
237 uint8_t preop;
238 uint8_t opcode;
239};
240
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000241/* List of opcodes which need preopcodes and matching preopcodes. Unused. */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000242const struct preop_opcode_pair pops[] = {
FENG yu ningf041e9b2008-12-15 02:32:11 +0000243 {JEDEC_WREN, JEDEC_BYTE_PROGRAM},
244 {JEDEC_WREN, JEDEC_SE}, /* sector erase */
245 {JEDEC_WREN, JEDEC_BE_52}, /* block erase */
246 {JEDEC_WREN, JEDEC_BE_D8}, /* block erase */
247 {JEDEC_WREN, JEDEC_CE_60}, /* chip erase */
248 {JEDEC_WREN, JEDEC_CE_C7}, /* chip erase */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000249 /* FIXME: WRSR requires either EWSR or WREN depending on chip type. */
250 {JEDEC_WREN, JEDEC_WRSR},
FENG yu ningf041e9b2008-12-15 02:32:11 +0000251 {JEDEC_EWSR, JEDEC_WRSR},
252 {0,}
253};
254
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000255/* Reasonable default configuration. Needs ad-hoc modifications if we
256 * encounter unlisted opcodes. Fun.
257 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000258static OPCODES O_ST_M25P = {
Dominik Geyerb46acba2008-05-16 12:55:55 +0000259 {
260 JEDEC_WREN,
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000261 JEDEC_EWSR,
262 },
Dominik Geyerb46acba2008-05-16 12:55:55 +0000263 {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000264 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000265 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000266 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000267 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
Carl-Daniel Hailfinger15aa7c62009-05-26 21:25:08 +0000268 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000269 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
Stefan Reinauer325b5d42008-06-27 15:18:20 +0000270 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000271 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
272 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000273};
274
Helge Wagner738e2522010-10-05 22:06:05 +0000275/* List of opcodes with their corresponding spi_type
276 * It is used to reprogram the chipset OPCODE table on-the-fly if an opcode
277 * is needed which is currently not in the chipset OPCODE table
278 */
279static OPCODE POSSIBLE_OPCODES[] = {
280 {JEDEC_BYTE_PROGRAM, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Write Byte
281 {JEDEC_READ, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Data
282 {JEDEC_BE_D8, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Erase Sector
283 {JEDEC_RDSR, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read Device Status Reg
284 {JEDEC_REMS, SPI_OPCODE_TYPE_READ_WITH_ADDRESS, 0}, // Read Electronic Manufacturer Signature
285 {JEDEC_WRSR, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Write Status Register
286 {JEDEC_RDID, SPI_OPCODE_TYPE_READ_NO_ADDRESS, 0}, // Read JDEC ID
287 {JEDEC_CE_C7, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Bulk erase
288 {JEDEC_SE, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Sector erase
289 {JEDEC_BE_52, SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS, 0}, // Block erase
290 {JEDEC_AAI_WORD_PROGRAM, SPI_OPCODE_TYPE_WRITE_NO_ADDRESS, 0}, // Auto Address Increment
291};
292
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000293static OPCODES O_EXISTING = {};
FENG yu ningc05a2952008-12-08 18:16:58 +0000294
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000295/* pretty printing functions */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000296static void prettyprint_opcodes(OPCODES *ops)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000297{
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000298 OPCODE oc;
299 const char *t;
300 const char *a;
301 uint8_t i;
302 static const char *const spi_type[4] = {
303 "read w/o addr",
304 "write w/o addr",
305 "read w/ addr",
306 "write w/ addr"
307 };
308 static const char *const atomic_type[3] = {
309 "none",
310 " 0 ",
311 " 1 "
312 };
313
314 if (ops == NULL)
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000315 return;
316
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000317 msg_pdbg2(" OP Type Pre-OP\n");
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000318 for (i = 0; i < 8; i++) {
319 oc = ops->opcode[i];
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000320 t = (oc.spi_type > 3) ? "invalid" : spi_type[oc.spi_type];
321 a = (oc.atomic > 2) ? "invalid" : atomic_type[oc.atomic];
322 msg_pdbg2("op[%d]: 0x%02x, %s, %s\n", i, oc.opcode, t, a);
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000323 }
Stefan Tauner84e1dde2011-09-17 19:53:11 +0000324 msg_pdbg2("Pre-OP 0: 0x%02x, Pre-OP 1: 0x%02x\n", ops->preop[0],
325 ops->preop[1]);
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000326}
327
328#define pprint_reg(reg, bit, val, sep) msg_pdbg("%s=%d" sep, #bit, (val & reg##_##bit)>>reg##_##bit##_OFF)
329
Stefan Tauner55206942011-06-11 09:53:22 +0000330static void prettyprint_ich9_reg_hsfs(uint16_t reg_val)
331{
332 msg_pdbg("HSFS: ");
333 pprint_reg(HSFS, FDONE, reg_val, ", ");
334 pprint_reg(HSFS, FCERR, reg_val, ", ");
335 pprint_reg(HSFS, AEL, reg_val, ", ");
336 pprint_reg(HSFS, BERASE, reg_val, ", ");
337 pprint_reg(HSFS, SCIP, reg_val, ", ");
338 pprint_reg(HSFS, FDOPSS, reg_val, ", ");
339 pprint_reg(HSFS, FDV, reg_val, ", ");
340 pprint_reg(HSFS, FLOCKDN, reg_val, "\n");
341}
342
343static void prettyprint_ich9_reg_hsfc(uint16_t reg_val)
344{
345 msg_pdbg("HSFC: ");
346 pprint_reg(HSFC, FGO, reg_val, ", ");
347 pprint_reg(HSFC, FCYCLE, reg_val, ", ");
348 pprint_reg(HSFC, FDBC, reg_val, ", ");
349 pprint_reg(HSFC, SME, reg_val, "\n");
350}
351
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000352static void prettyprint_ich9_reg_ssfs(uint32_t reg_val)
353{
354 msg_pdbg("SSFS: ");
355 pprint_reg(SSFS, SCIP, reg_val, ", ");
356 pprint_reg(SSFS, FDONE, reg_val, ", ");
357 pprint_reg(SSFS, FCERR, reg_val, ", ");
358 pprint_reg(SSFS, AEL, reg_val, "\n");
359}
360
361static void prettyprint_ich9_reg_ssfc(uint32_t reg_val)
362{
363 msg_pdbg("SSFC: ");
364 pprint_reg(SSFC, SCGO, reg_val, ", ");
365 pprint_reg(SSFC, ACS, reg_val, ", ");
366 pprint_reg(SSFC, SPOP, reg_val, ", ");
367 pprint_reg(SSFC, COP, reg_val, ", ");
368 pprint_reg(SSFC, DBC, reg_val, ", ");
369 pprint_reg(SSFC, SME, reg_val, ", ");
370 pprint_reg(SSFC, SCF, reg_val, "\n");
371}
372
Helge Wagner738e2522010-10-05 22:06:05 +0000373static uint8_t lookup_spi_type(uint8_t opcode)
374{
375 int a;
376
Uwe Hermann91f4afa2011-07-28 08:13:25 +0000377 for (a = 0; a < ARRAY_SIZE(POSSIBLE_OPCODES); a++) {
Helge Wagner738e2522010-10-05 22:06:05 +0000378 if (POSSIBLE_OPCODES[a].opcode == opcode)
379 return POSSIBLE_OPCODES[a].spi_type;
380 }
381
382 return 0xFF;
383}
384
385static int reprogram_opcode_on_the_fly(uint8_t opcode, unsigned int writecnt, unsigned int readcnt)
386{
387 uint8_t spi_type;
388
389 spi_type = lookup_spi_type(opcode);
390 if (spi_type > 3) {
391 /* Try to guess spi type from read/write sizes.
392 * The following valid writecnt/readcnt combinations exist:
393 * writecnt = 4, readcnt >= 0
394 * writecnt = 1, readcnt >= 0
395 * writecnt >= 4, readcnt = 0
396 * writecnt >= 1, readcnt = 0
397 * writecnt >= 1 is guaranteed for all commands.
398 */
399 if (readcnt == 0)
400 /* if readcnt=0 and writecount >= 4, we don't know if it is WRITE_NO_ADDRESS
401 * or WRITE_WITH_ADDRESS. But if we use WRITE_NO_ADDRESS and the first 3 data
402 * bytes are actual the address, they go to the bus anyhow
403 */
404 spi_type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
405 else if (writecnt == 1) // and readcnt is > 0
406 spi_type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
407 else if (writecnt == 4) // and readcnt is > 0
408 spi_type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
Stefan Taunerdc704ed2012-05-06 15:11:26 +0000409 else // we have an invalid case
410 return SPI_INVALID_LENGTH;
Helge Wagner738e2522010-10-05 22:06:05 +0000411 }
Stefan Taunerdc704ed2012-05-06 15:11:26 +0000412 int oppos = 2; // use original JEDEC_BE_D8 offset
413 curopcodes->opcode[oppos].opcode = opcode;
414 curopcodes->opcode[oppos].spi_type = spi_type;
415 program_opcodes(curopcodes, 0);
416 oppos = find_opcode(curopcodes, opcode);
Stefan Taunerd94d25d2012-07-28 03:17:15 +0000417 msg_pdbg2("on-the-fly OPCODE (0x%02X) re-programmed, op-pos=%d\n", opcode, oppos);
Stefan Taunerdc704ed2012-05-06 15:11:26 +0000418 return oppos;
Helge Wagner738e2522010-10-05 22:06:05 +0000419}
420
Uwe Hermann09e04f72009-05-16 22:36:00 +0000421static int find_opcode(OPCODES *op, uint8_t opcode)
FENG yu ningc05a2952008-12-08 18:16:58 +0000422{
423 int a;
424
Stefan Tauner50e7c602011-11-08 10:55:54 +0000425 if (op == NULL) {
426 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
427 return -1;
428 }
429
FENG yu ningc05a2952008-12-08 18:16:58 +0000430 for (a = 0; a < 8; a++) {
431 if (op->opcode[a].opcode == opcode)
432 return a;
433 }
434
435 return -1;
436}
437
Uwe Hermann09e04f72009-05-16 22:36:00 +0000438static int find_preop(OPCODES *op, uint8_t preop)
FENG yu ningc05a2952008-12-08 18:16:58 +0000439{
440 int a;
441
Stefan Tauner50e7c602011-11-08 10:55:54 +0000442 if (op == NULL) {
443 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
444 return -1;
445 }
446
FENG yu ningc05a2952008-12-08 18:16:58 +0000447 for (a = 0; a < 2; a++) {
448 if (op->preop[a] == preop)
449 return a;
450 }
451
452 return -1;
453}
454
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000455/* Create a struct OPCODES based on what we find in the locked down chipset. */
FENG yu ningf041e9b2008-12-15 02:32:11 +0000456static int generate_opcodes(OPCODES * op)
FENG yu ningc05a2952008-12-08 18:16:58 +0000457{
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000458 int a;
FENG yu ningc05a2952008-12-08 18:16:58 +0000459 uint16_t preop, optype;
460 uint32_t opmenu[2];
FENG yu ningc05a2952008-12-08 18:16:58 +0000461
462 if (op == NULL) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000463 msg_perr("\n%s: null OPCODES pointer!\n", __func__);
FENG yu ningc05a2952008-12-08 18:16:58 +0000464 return -1;
465 }
466
Stefan Taunera8d838d2011-11-06 23:51:09 +0000467 switch (ich_generation) {
468 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000469 case CHIPSET_TUNNEL_CREEK:
470 case CHIPSET_CENTERTON:
FENG yu ningc05a2952008-12-08 18:16:58 +0000471 preop = REGREAD16(ICH7_REG_PREOP);
472 optype = REGREAD16(ICH7_REG_OPTYPE);
473 opmenu[0] = REGREAD32(ICH7_REG_OPMENU);
474 opmenu[1] = REGREAD32(ICH7_REG_OPMENU + 4);
475 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000476 case CHIPSET_ICH8:
477 default: /* Future version might behave the same */
FENG yu ningc05a2952008-12-08 18:16:58 +0000478 preop = REGREAD16(ICH9_REG_PREOP);
479 optype = REGREAD16(ICH9_REG_OPTYPE);
480 opmenu[0] = REGREAD32(ICH9_REG_OPMENU);
481 opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4);
482 break;
FENG yu ningc05a2952008-12-08 18:16:58 +0000483 }
484
485 op->preop[0] = (uint8_t) preop;
486 op->preop[1] = (uint8_t) (preop >> 8);
487
488 for (a = 0; a < 8; a++) {
489 op->opcode[a].spi_type = (uint8_t) (optype & 0x3);
490 optype >>= 2;
491 }
492
493 for (a = 0; a < 4; a++) {
494 op->opcode[a].opcode = (uint8_t) (opmenu[0] & 0xff);
495 opmenu[0] >>= 8;
496 }
497
498 for (a = 4; a < 8; a++) {
499 op->opcode[a].opcode = (uint8_t) (opmenu[1] & 0xff);
500 opmenu[1] >>= 8;
501 }
502
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000503 /* No preopcodes used by default. */
504 for (a = 0; a < 8; a++)
FENG yu ningc05a2952008-12-08 18:16:58 +0000505 op->opcode[a].atomic = 0;
506
FENG yu ningc05a2952008-12-08 18:16:58 +0000507 return 0;
508}
509
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000510static int program_opcodes(OPCODES *op, int enable_undo)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000511{
512 uint8_t a;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000513 uint16_t preop, optype;
514 uint32_t opmenu[2];
Dominik Geyerb46acba2008-05-16 12:55:55 +0000515
516 /* Program Prefix Opcodes */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000517 /* 0:7 Prefix Opcode 1 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000518 preop = (op->preop[0]);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000519 /* 8:16 Prefix Opcode 2 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000520 preop |= ((uint16_t) op->preop[1]) << 8;
Uwe Hermann394131e2008-10-18 21:14:13 +0000521
Stefan Reinauera9424d52008-06-27 16:28:34 +0000522 /* Program Opcode Types 0 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000523 optype = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000524 for (a = 0; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000525 optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000526 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000527
Stefan Reinauera9424d52008-06-27 16:28:34 +0000528 /* Program Allowable Opcodes 0 - 3 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000529 opmenu[0] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000530 for (a = 0; a < 4; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000531 opmenu[0] |= ((uint32_t) op->opcode[a].opcode) << (a * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000532 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000533
Stefan Tauner92d6a862013-10-25 00:33:37 +0000534 /* Program Allowable Opcodes 4 - 7 */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000535 opmenu[1] = 0;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000536 for (a = 4; a < 8; a++) {
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000537 opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000538 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000539
Stefan Taunerd94d25d2012-07-28 03:17:15 +0000540 msg_pdbg2("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]);
Stefan Taunera8d838d2011-11-06 23:51:09 +0000541 switch (ich_generation) {
542 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000543 case CHIPSET_TUNNEL_CREEK:
544 case CHIPSET_CENTERTON:
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000545 /* Register undo only for enable_undo=1, i.e. first call. */
546 if (enable_undo) {
547 rmmio_valw(ich_spibar + ICH7_REG_PREOP);
548 rmmio_valw(ich_spibar + ICH7_REG_OPTYPE);
549 rmmio_vall(ich_spibar + ICH7_REG_OPMENU);
550 rmmio_vall(ich_spibar + ICH7_REG_OPMENU + 4);
551 }
552 mmio_writew(preop, ich_spibar + ICH7_REG_PREOP);
553 mmio_writew(optype, ich_spibar + ICH7_REG_OPTYPE);
554 mmio_writel(opmenu[0], ich_spibar + ICH7_REG_OPMENU);
555 mmio_writel(opmenu[1], ich_spibar + ICH7_REG_OPMENU + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000556 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000557 case CHIPSET_ICH8:
558 default: /* Future version might behave the same */
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000559 /* Register undo only for enable_undo=1, i.e. first call. */
560 if (enable_undo) {
561 rmmio_valw(ich_spibar + ICH9_REG_PREOP);
562 rmmio_valw(ich_spibar + ICH9_REG_OPTYPE);
563 rmmio_vall(ich_spibar + ICH9_REG_OPMENU);
564 rmmio_vall(ich_spibar + ICH9_REG_OPMENU + 4);
565 }
566 mmio_writew(preop, ich_spibar + ICH9_REG_PREOP);
567 mmio_writew(optype, ich_spibar + ICH9_REG_OPTYPE);
568 mmio_writel(opmenu[0], ich_spibar + ICH9_REG_OPMENU);
569 mmio_writel(opmenu[1], ich_spibar + ICH9_REG_OPMENU + 4);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000570 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000571 }
Dominik Geyerb46acba2008-05-16 12:55:55 +0000572
573 return 0;
574}
575
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000576/*
Stefan Tauner50e7c602011-11-08 10:55:54 +0000577 * Returns -1 if at least one mandatory opcode is inaccessible, 0 otherwise.
578 * FIXME: this should also check for
579 * - at least one probing opcode (RDID (incl. AT25F variants?), REMS, RES?)
580 * - at least one erasing opcode (lots.)
581 * - at least one program opcode (BYTE_PROGRAM, AAI_WORD_PROGRAM, ...?)
582 * - necessary preops? (EWSR, WREN, ...?)
583 */
584static int ich_missing_opcodes()
585{
586 uint8_t ops[] = {
587 JEDEC_READ,
588 JEDEC_RDSR,
589 0
590 };
591 int i = 0;
592 while (ops[i] != 0) {
593 msg_pspew("checking for opcode 0x%02x\n", ops[i]);
594 if (find_opcode(curopcodes, ops[i]) == -1)
595 return -1;
596 i++;
597 }
598 return 0;
599}
600
601/*
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000602 * Try to set BBAR (BIOS Base Address Register), but read back the value in case
603 * it didn't stick.
604 */
Stefan Taunera8d838d2011-11-06 23:51:09 +0000605static void ich_set_bbar(uint32_t min_addr)
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000606{
Stefan Taunere27b2d42011-07-01 00:39:09 +0000607 int bbar_off;
Stefan Tauner7783f312011-09-17 21:21:42 +0000608 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +0000609 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000610 case CHIPSET_TUNNEL_CREEK:
611 case CHIPSET_CENTERTON:
Stefan Taunere27b2d42011-07-01 00:39:09 +0000612 bbar_off = 0x50;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000613 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000614 case CHIPSET_ICH8:
Stefan Tauner7783f312011-09-17 21:21:42 +0000615 msg_perr("BBAR offset is unknown on ICH8!\n");
616 return;
Stefan Taunera8d838d2011-11-06 23:51:09 +0000617 case CHIPSET_ICH9:
Stefan Tauner7783f312011-09-17 21:21:42 +0000618 default: /* Future version might behave the same */
Stefan Taunere27b2d42011-07-01 00:39:09 +0000619 bbar_off = ICH9_REG_BBAR;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000620 break;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000621 }
Stefan Taunere27b2d42011-07-01 00:39:09 +0000622
623 ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & ~BBAR_MASK;
624 if (ichspi_bbar) {
625 msg_pdbg("Reserved bits in BBAR not zero: 0x%08x\n",
626 ichspi_bbar);
627 }
628 min_addr &= BBAR_MASK;
629 ichspi_bbar |= min_addr;
630 rmmio_writel(ichspi_bbar, ich_spibar + bbar_off);
631 ichspi_bbar = mmio_readl(ich_spibar + bbar_off) & BBAR_MASK;
632
633 /* We don't have any option except complaining. And if the write
634 * failed, the restore will fail as well, so no problem there.
635 */
636 if (ichspi_bbar != min_addr)
Stefan Tauner7783f312011-09-17 21:21:42 +0000637 msg_perr("Setting BBAR to 0x%08x failed! New value: 0x%08x.\n",
638 min_addr, ichspi_bbar);
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000639}
640
Stefan Tauner8b391b82011-08-09 01:49:34 +0000641/* Read len bytes from the fdata/spid register into the data array.
642 *
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000643 * Note that using len > flash->mst->spi.max_data_read will return garbage or
Stefan Tauner8b391b82011-08-09 01:49:34 +0000644 * may even crash.
645 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000646static void ich_read_data(uint8_t *data, int len, int reg0_off)
Stefan Tauner8b391b82011-08-09 01:49:34 +0000647 {
648 int i;
649 uint32_t temp32 = 0;
650
651 for (i = 0; i < len; i++) {
652 if ((i % 4) == 0)
653 temp32 = REGREAD32(reg0_off + i);
654
655 data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
656 }
657}
658
659/* Fill len bytes from the data array into the fdata/spid registers.
660 *
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000661 * Note that using len > flash->mst->spi.max_data_write will trash the registers
Stefan Tauner8b391b82011-08-09 01:49:34 +0000662 * following the data registers.
663 */
664static void ich_fill_data(const uint8_t *data, int len, int reg0_off)
665{
666 uint32_t temp32 = 0;
667 int i;
668
669 if (len <= 0)
670 return;
671
672 for (i = 0; i < len; i++) {
673 if ((i % 4) == 0)
674 temp32 = 0;
675
676 temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
677
678 if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
679 REGWRITE32(reg0_off + (i - (i % 4)), temp32);
680 }
681 i--;
682 if ((i % 4) != 3) /* Write remaining data to regs. */
683 REGWRITE32(reg0_off + (i - (i % 4)), temp32);
684}
685
FENG yu ningf041e9b2008-12-15 02:32:11 +0000686/* This function generates OPCODES from or programs OPCODES to ICH according to
687 * the chipset's SPI configuration lock.
FENG yu ningc05a2952008-12-08 18:16:58 +0000688 *
FENG yu ningf041e9b2008-12-15 02:32:11 +0000689 * It should be called before ICH sends any spi command.
FENG yu ningc05a2952008-12-08 18:16:58 +0000690 */
Michael Karchera4448d92010-07-22 18:04:15 +0000691static int ich_init_opcodes(void)
FENG yu ningc05a2952008-12-08 18:16:58 +0000692{
693 int rc = 0;
694 OPCODES *curopcodes_done;
695
696 if (curopcodes)
697 return 0;
698
699 if (ichspi_lock) {
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000700 msg_pdbg("Reading OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000701 curopcodes_done = &O_EXISTING;
FENG yu ningf041e9b2008-12-15 02:32:11 +0000702 rc = generate_opcodes(curopcodes_done);
FENG yu ningc05a2952008-12-08 18:16:58 +0000703 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000704 msg_pdbg("Programming OPCODES... ");
FENG yu ningc05a2952008-12-08 18:16:58 +0000705 curopcodes_done = &O_ST_M25P;
Carl-Daniel Hailfinger54ce73a2011-05-03 21:49:41 +0000706 rc = program_opcodes(curopcodes_done, 1);
FENG yu ningc05a2952008-12-08 18:16:58 +0000707 }
708
709 if (rc) {
710 curopcodes = NULL;
Sean Nelson316a29f2010-05-07 20:09:04 +0000711 msg_perr("failed\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000712 return 1;
713 } else {
714 curopcodes = curopcodes_done;
Sean Nelson316a29f2010-05-07 20:09:04 +0000715 msg_pdbg("done\n");
Stefan Tauner8b391b82011-08-09 01:49:34 +0000716 prettyprint_opcodes(curopcodes);
FENG yu ningc05a2952008-12-08 18:16:58 +0000717 return 0;
718 }
719}
720
Stefan Reinauer43119562008-11-02 19:51:50 +0000721static int ich7_run_opcode(OPCODE op, uint32_t offset,
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000722 uint8_t datalength, uint8_t * data, int maxdata)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000723{
724 int write_cmd = 0;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000725 int timeout;
Stefan Tauner8b391b82011-08-09 01:49:34 +0000726 uint32_t temp32;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000727 uint16_t temp16;
Stefan Reinauer43119562008-11-02 19:51:50 +0000728 uint64_t opmenu;
729 int opcode_index;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000730
731 /* Is it a write command? */
732 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
733 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
734 write_cmd = 1;
735 }
736
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000737 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
738 while ((REGREAD16(ICH7_REG_SPIS) & SPIS_SCIP) && --timeout) {
739 programmer_delay(10);
740 }
741 if (!timeout) {
742 msg_perr("Error: SCIP never cleared!\n");
743 return 1;
744 }
745
Stefan Tauner10b3e222011-07-01 00:39:23 +0000746 /* Program offset in flash into SPIA while preserving reserved bits. */
747 temp32 = REGREAD32(ICH7_REG_SPIA) & ~0x00FFFFFF;
748 REGWRITE32(ICH7_REG_SPIA, (offset & 0x00FFFFFF) | temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000749
Stefan Tauner10b3e222011-07-01 00:39:23 +0000750 /* Program data into SPID0 to N */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000751 if (write_cmd && (datalength != 0))
752 ich_fill_data(data, datalength, ICH7_REG_SPID0);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000753
754 /* Assemble SPIS */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000755 temp16 = REGREAD16(ICH7_REG_SPIS);
756 /* keep reserved bits */
757 temp16 &= SPIS_RESERVED_MASK;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000758 /* clear error status registers */
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000759 temp16 |= (SPIS_CDS | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000760 REGWRITE16(ICH7_REG_SPIS, temp16);
761
762 /* Assemble SPIC */
763 temp16 = 0;
764
765 if (datalength != 0) {
766 temp16 |= SPIC_DS;
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000767 temp16 |= ((uint32_t) ((datalength - 1) & (maxdata - 1))) << 8;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000768 }
769
770 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000771 opmenu = REGREAD32(ICH7_REG_OPMENU);
772 opmenu |= ((uint64_t)REGREAD32(ICH7_REG_OPMENU + 4)) << 32;
773
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000774 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
775 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000776 break;
777 }
778 opmenu >>= 8;
779 }
780 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000781 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000782 return 1;
783 }
784 temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000785
Michael Karcher136125a2011-04-29 22:11:36 +0000786 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
787 /* Handle Atomic. Atomic commands include three steps:
788 - sending the preop (mainly EWSR or WREN)
789 - sending the main command
790 - waiting for the busy bit (WIP) to be cleared
791 This means the timeout must be sufficient for chip erase
792 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000793 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000794 switch (op.atomic) {
795 case 2:
796 /* Select second preop. */
797 temp16 |= SPIC_SPOP;
798 /* And fall through. */
799 case 1:
800 /* Atomic command (preop+op) */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000801 temp16 |= SPIC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +0000802 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000803 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000804 }
805
806 /* Start */
807 temp16 |= SPIC_SCGO;
808
809 /* write it */
810 REGWRITE16(ICH7_REG_SPIC, temp16);
811
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000812 /* Wait for Cycle Done Status or Flash Cycle Error. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000813 while (((REGREAD16(ICH7_REG_SPIS) & (SPIS_CDS | SPIS_FCERR)) == 0) &&
814 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000815 programmer_delay(10);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000816 }
817 if (!timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000818 msg_perr("timeout, ICH7_REG_SPIS=0x%04x\n",
819 REGREAD16(ICH7_REG_SPIS));
820 return 1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000821 }
822
Sean Nelson316a29f2010-05-07 20:09:04 +0000823 /* FIXME: make sure we do not needlessly cause transaction errors. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000824 temp16 = REGREAD16(ICH7_REG_SPIS);
825 if (temp16 & SPIS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +0000826 msg_perr("Transaction error!\n");
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000827 /* keep reserved bits */
828 temp16 &= SPIS_RESERVED_MASK;
829 REGWRITE16(ICH7_REG_SPIS, temp16 | SPIS_FCERR);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000830 return 1;
831 }
832
Stefan Tauner8b391b82011-08-09 01:49:34 +0000833 if ((!write_cmd) && (datalength != 0))
834 ich_read_data(data, datalength, ICH7_REG_SPID0);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000835
836 return 0;
837}
838
Stefan Reinauer43119562008-11-02 19:51:50 +0000839static int ich9_run_opcode(OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000840 uint8_t datalength, uint8_t * data)
841{
842 int write_cmd = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000843 int timeout;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000844 uint32_t temp32;
Stefan Reinauer43119562008-11-02 19:51:50 +0000845 uint64_t opmenu;
846 int opcode_index;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000847
848 /* Is it a write command? */
849 if ((op.spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)
850 || (op.spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS)) {
851 write_cmd = 1;
852 }
853
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000854 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
855 while ((REGREAD8(ICH9_REG_SSFS) & SSFS_SCIP) && --timeout) {
856 programmer_delay(10);
857 }
858 if (!timeout) {
859 msg_perr("Error: SCIP never cleared!\n");
860 return 1;
861 }
862
Stefan Tauner10b3e222011-07-01 00:39:23 +0000863 /* Program offset in flash into FADDR while preserve the reserved bits
864 * and clearing the 25. address bit which is only useable in hwseq. */
865 temp32 = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF;
866 REGWRITE32(ICH9_REG_FADDR, (offset & 0x00FFFFFF) | temp32);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000867
868 /* Program data into FDATA0 to N */
Stefan Tauner8b391b82011-08-09 01:49:34 +0000869 if (write_cmd && (datalength != 0))
870 ich_fill_data(data, datalength, ICH9_REG_FDATA0);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000871
872 /* Assemble SSFS + SSFC */
Helge Wagnera319be12010-08-11 21:06:10 +0000873 temp32 = REGREAD32(ICH9_REG_SSFS);
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000874 /* Keep reserved bits only */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000875 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000876 /* Clear cycle done and cycle error status registers */
877 temp32 |= (SSFS_FDONE | SSFS_FCERR);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000878 REGWRITE32(ICH9_REG_SSFS, temp32);
879
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000880 /* Use 20 MHz */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000881 temp32 |= SSFC_SCF_20MHZ;
882
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000883 /* Set data byte count (DBC) and data cycle bit (DS) */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000884 if (datalength != 0) {
885 uint32_t datatemp;
886 temp32 |= SSFC_DS;
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000887 datatemp = ((((uint32_t)datalength - 1) << SSFC_DBC_OFF) &
888 SSFC_DBC);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000889 temp32 |= datatemp;
890 }
891
892 /* Select opcode */
Stefan Reinauer43119562008-11-02 19:51:50 +0000893 opmenu = REGREAD32(ICH9_REG_OPMENU);
894 opmenu |= ((uint64_t)REGREAD32(ICH9_REG_OPMENU + 4)) << 32;
895
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000896 for (opcode_index = 0; opcode_index < 8; opcode_index++) {
897 if ((opmenu & 0xff) == op.opcode) {
Stefan Reinauer43119562008-11-02 19:51:50 +0000898 break;
899 }
900 opmenu >>= 8;
901 }
902 if (opcode_index == 8) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000903 msg_pdbg("Opcode %x not found.\n", op.opcode);
Stefan Reinauer43119562008-11-02 19:51:50 +0000904 return 1;
905 }
906 temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000907
Michael Karcher136125a2011-04-29 22:11:36 +0000908 timeout = 100 * 60; /* 60 ms are 9.6 million cycles at 16 MHz. */
909 /* Handle Atomic. Atomic commands include three steps:
910 - sending the preop (mainly EWSR or WREN)
911 - sending the main command
912 - waiting for the busy bit (WIP) to be cleared
913 This means the timeout must be sufficient for chip erase
914 of slow high-capacity chips.
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000915 */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000916 switch (op.atomic) {
917 case 2:
918 /* Select second preop. */
919 temp32 |= SSFC_SPOP;
920 /* And fall through. */
921 case 1:
922 /* Atomic command (preop+op) */
Dominik Geyerb46acba2008-05-16 12:55:55 +0000923 temp32 |= SSFC_ACS;
Michael Karcher136125a2011-04-29 22:11:36 +0000924 timeout = 100 * 1000 * 60; /* 60 seconds */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +0000925 break;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000926 }
927
928 /* Start */
929 temp32 |= SSFC_SCGO;
930
931 /* write it */
Stefan Reinauera9424d52008-06-27 16:28:34 +0000932 REGWRITE32(ICH9_REG_SSFS, temp32);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000933
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000934 /* Wait for Cycle Done Status or Flash Cycle Error. */
Stefan Tauner0c1ec452011-06-11 09:53:09 +0000935 while (((REGREAD32(ICH9_REG_SSFS) & (SSFS_FDONE | SSFS_FCERR)) == 0) &&
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000936 --timeout) {
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000937 programmer_delay(10);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000938 }
939 if (!timeout) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000940 msg_perr("timeout, ICH9_REG_SSFS=0x%08x\n",
941 REGREAD32(ICH9_REG_SSFS));
942 return 1;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000943 }
944
Sean Nelson316a29f2010-05-07 20:09:04 +0000945 /* FIXME make sure we do not needlessly cause transaction errors. */
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000946 temp32 = REGREAD32(ICH9_REG_SSFS);
947 if (temp32 & SSFS_FCERR) {
Stefan Tauner8ed29342011-04-29 23:53:09 +0000948 msg_perr("Transaction error!\n");
Stefan Tauner2a8b2622011-06-11 09:53:16 +0000949 prettyprint_ich9_reg_ssfs(temp32);
950 prettyprint_ich9_reg_ssfc(temp32);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +0000951 /* keep reserved bits */
952 temp32 &= SSFS_RESERVED_MASK | SSFC_RESERVED_MASK;
953 /* Clear the transaction error. */
954 REGWRITE32(ICH9_REG_SSFS, temp32 | SSFS_FCERR);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000955 return 1;
956 }
957
Stefan Tauner8b391b82011-08-09 01:49:34 +0000958 if ((!write_cmd) && (datalength != 0))
959 ich_read_data(data, datalength, ICH9_REG_FDATA0);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000960
961 return 0;
962}
963
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000964static int run_opcode(const struct flashctx *flash, OPCODE op, uint32_t offset,
Stefan Reinauera9424d52008-06-27 16:28:34 +0000965 uint8_t datalength, uint8_t * data)
966{
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000967 /* max_data_read == max_data_write for all Intel/VIA SPI masters */
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +0000968 uint8_t maxlength = flash->mst->spi.max_data_read;
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000969
Carl-Daniel Hailfingerc40cff72011-12-20 00:19:29 +0000970 if (ich_generation == CHIPSET_ICH_UNKNOWN) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000971 msg_perr("%s: unsupported chipset\n", __func__);
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000972 return -1;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000973 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000974
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000975 if (datalength > maxlength) {
976 msg_perr("%s: Internal command size error for "
977 "opcode 0x%02x, got datalength=%i, want <=%i\n",
978 __func__, op.opcode, datalength, maxlength);
979 return SPI_INVALID_LENGTH;
980 }
981
Stefan Taunera8d838d2011-11-06 23:51:09 +0000982 switch (ich_generation) {
983 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +0000984 case CHIPSET_TUNNEL_CREEK:
985 case CHIPSET_CENTERTON:
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000986 return ich7_run_opcode(op, offset, datalength, data, maxlength);
Stefan Taunera8d838d2011-11-06 23:51:09 +0000987 case CHIPSET_ICH8:
988 default: /* Future version might behave the same */
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000989 return ich9_run_opcode(op, offset, datalength, data);
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +0000990 }
Stefan Reinauera9424d52008-06-27 16:28:34 +0000991}
992
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000993static int ich_spi_send_command(struct flashctx *flash, unsigned int writecnt,
994 unsigned int readcnt,
995 const unsigned char *writearr,
996 unsigned char *readarr)
Dominik Geyerb46acba2008-05-16 12:55:55 +0000997{
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +0000998 int result;
Dominik Geyerb46acba2008-05-16 12:55:55 +0000999 int opcode_index = -1;
1000 const unsigned char cmd = *writearr;
1001 OPCODE *opcode;
1002 uint32_t addr = 0;
1003 uint8_t *data;
1004 int count;
1005
Dominik Geyerb46acba2008-05-16 12:55:55 +00001006 /* find cmd in opcodes-table */
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001007 opcode_index = find_opcode(curopcodes, cmd);
Dominik Geyerb46acba2008-05-16 12:55:55 +00001008 if (opcode_index == -1) {
Helge Wagner738e2522010-10-05 22:06:05 +00001009 if (!ichspi_lock)
1010 opcode_index = reprogram_opcode_on_the_fly(cmd, writecnt, readcnt);
Stefan Taunerdc704ed2012-05-06 15:11:26 +00001011 if (opcode_index == SPI_INVALID_LENGTH) {
1012 msg_pdbg("OPCODE 0x%02x has unsupported length, will not execute.\n", cmd);
1013 return SPI_INVALID_LENGTH;
1014 } else if (opcode_index == -1) {
Stefan Tauner355cbfd2011-05-28 02:37:14 +00001015 msg_pdbg("Invalid OPCODE 0x%02x, will not execute.\n",
1016 cmd);
Helge Wagner738e2522010-10-05 22:06:05 +00001017 return SPI_INVALID_OPCODE;
1018 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001019 }
1020
1021 opcode = &(curopcodes->opcode[opcode_index]);
1022
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001023 /* The following valid writecnt/readcnt combinations exist:
1024 * writecnt = 4, readcnt >= 0
1025 * writecnt = 1, readcnt >= 0
1026 * writecnt >= 4, readcnt = 0
1027 * writecnt >= 1, readcnt = 0
1028 * writecnt >= 1 is guaranteed for all commands.
1029 */
1030 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) &&
1031 (writecnt != 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001032 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001033 "0x%02x, got writecnt=%i, want =4\n", __func__, cmd,
1034 writecnt);
1035 return SPI_INVALID_LENGTH;
1036 }
1037 if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) &&
1038 (writecnt != 1)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001039 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001040 "0x%02x, got writecnt=%i, want =1\n", __func__, cmd,
1041 writecnt);
1042 return SPI_INVALID_LENGTH;
1043 }
1044 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) &&
1045 (writecnt < 4)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001046 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001047 "0x%02x, got writecnt=%i, want >=4\n", __func__, cmd,
1048 writecnt);
1049 return SPI_INVALID_LENGTH;
1050 }
1051 if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1052 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) &&
1053 (readcnt)) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001054 msg_perr("%s: Internal command size error for opcode "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001055 "0x%02x, got readcnt=%i, want =0\n", __func__, cmd,
1056 readcnt);
1057 return SPI_INVALID_LENGTH;
1058 }
1059
Dominik Geyerb46acba2008-05-16 12:55:55 +00001060 /* if opcode-type requires an address */
1061 if (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS ||
1062 opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001063 addr = (writearr[1] << 16) |
1064 (writearr[2] << 8) | (writearr[3] << 0);
Stefan Taunera8d838d2011-11-06 23:51:09 +00001065 if (addr < ichspi_bbar) {
1066 msg_perr("%s: Address 0x%06x below allowed "
1067 "range 0x%06x-0xffffff\n", __func__,
1068 addr, ichspi_bbar);
1069 return SPI_INVALID_ADDRESS;
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +00001070 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001071 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001072
Stefan Taunerb2d5f6a2011-06-11 19:44:31 +00001073 /* Translate read/write array/count.
1074 * The maximum data length is identical for the maximum read length and
1075 * for the maximum write length excluding opcode and address. Opcode and
1076 * address are stored in separate registers, not in the data registers
1077 * and are thus not counted towards data length. The only exception
1078 * applies if the opcode definition (un)intentionally classifies said
1079 * opcode incorrectly as non-address opcode or vice versa. */
Dominik Geyerb46acba2008-05-16 12:55:55 +00001080 if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS) {
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001081 data = (uint8_t *) (writearr + 1);
1082 count = writecnt - 1;
1083 } else if (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) {
1084 data = (uint8_t *) (writearr + 4);
1085 count = writecnt - 4;
1086 } else {
1087 data = (uint8_t *) readarr;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001088 count = readcnt;
1089 }
Stefan Reinauer325b5d42008-06-27 15:18:20 +00001090
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001091 result = run_opcode(flash, *opcode, addr, count, data);
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001092 if (result) {
Stefan Tauner8ed29342011-04-29 23:53:09 +00001093 msg_pdbg("Running OPCODE 0x%02x failed ", opcode->opcode);
1094 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1095 (opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS)) {
1096 msg_pdbg("at address 0x%06x ", addr);
1097 }
1098 msg_pdbg("(payload length was %d).\n", count);
1099
1100 /* Print out the data array if it contains data to write.
1101 * Errors are detected before the received data is read back into
1102 * the array so it won't make sense to print it then. */
1103 if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
1104 (opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) {
1105 int i;
1106 msg_pspew("The data was:\n");
Stefan Taunerf382e352011-11-08 11:55:24 +00001107 for (i = 0; i < count; i++){
Stefan Tauner8ed29342011-04-29 23:53:09 +00001108 msg_pspew("%3d: 0x%02x\n", i, data[i]);
1109 }
1110 }
Dominik Geyerb46acba2008-05-16 12:55:55 +00001111 }
1112
Carl-Daniel Hailfinger142e30f2009-07-14 10:26:56 +00001113 return result;
Dominik Geyerb46acba2008-05-16 12:55:55 +00001114}
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001115
Stefan Tauner50e7c602011-11-08 10:55:54 +00001116static struct hwseq_data {
1117 uint32_t size_comp0;
1118 uint32_t size_comp1;
1119} hwseq_data;
1120
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001121/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */
1122static void ich_hwseq_set_addr(uint32_t addr)
1123{
1124 uint32_t addr_old = REGREAD32(ICH9_REG_FADDR) & ~0x01FFFFFF;
1125 REGWRITE32(ICH9_REG_FADDR, (addr & 0x01FFFFFF) | addr_old);
1126}
1127
1128/* Sets FADDR.FLA to 'addr' and returns the erase block size in bytes
1129 * of the block containing this address. May return nonsense if the address is
1130 * not valid. The erase block size for a specific address depends on the flash
1131 * partition layout as specified by FPB and the partition properties as defined
1132 * by UVSCC and LVSCC respectively. An alternative to implement this method
1133 * would be by querying FPB and the respective VSCC register directly.
1134 */
1135static uint32_t ich_hwseq_get_erase_block_size(unsigned int addr)
1136{
1137 uint8_t enc_berase;
Stefan Tauner67d163d2013-01-15 17:37:48 +00001138 static const uint32_t dec_berase[4] = {
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001139 256,
1140 4 * 1024,
1141 8 * 1024,
1142 64 * 1024
1143 };
1144
1145 ich_hwseq_set_addr(addr);
1146 enc_berase = (REGREAD16(ICH9_REG_HSFS) & HSFS_BERASE) >>
1147 HSFS_BERASE_OFF;
1148 return dec_berase[enc_berase];
1149}
1150
1151/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
1152 Resets all error flags in HSFS.
1153 Returns 0 if the cycle completes successfully without errors within
1154 timeout us, 1 on errors. */
1155static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
1156 unsigned int len)
1157{
1158 uint16_t hsfs;
1159 uint32_t addr;
1160
1161 timeout /= 8; /* scale timeout duration to counter */
1162 while ((((hsfs = REGREAD16(ICH9_REG_HSFS)) &
1163 (HSFS_FDONE | HSFS_FCERR)) == 0) &&
1164 --timeout) {
1165 programmer_delay(8);
1166 }
1167 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1168 if (!timeout) {
1169 addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF;
1170 msg_perr("Timeout error between offset 0x%08x and "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001171 "0x%08x (= 0x%08x + %d)!\n",
1172 addr, addr + len - 1, addr, len - 1);
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001173 prettyprint_ich9_reg_hsfs(hsfs);
1174 prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC));
1175 return 1;
1176 }
1177
1178 if (hsfs & HSFS_FCERR) {
1179 addr = REGREAD32(ICH9_REG_FADDR) & 0x01FFFFFF;
1180 msg_perr("Transaction error between offset 0x%08x and "
Stefan Tauner50e7c602011-11-08 10:55:54 +00001181 "0x%08x (= 0x%08x + %d)!\n",
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001182 addr, addr + len - 1, addr, len - 1);
1183 prettyprint_ich9_reg_hsfs(hsfs);
1184 prettyprint_ich9_reg_hsfc(REGREAD16(ICH9_REG_HSFC));
1185 return 1;
1186 }
1187 return 0;
1188}
Stefan Tauner50e7c602011-11-08 10:55:54 +00001189
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001190static int ich_hwseq_probe(struct flashctx *flash)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001191{
1192 uint32_t total_size, boundary;
1193 uint32_t erase_size_low, size_low, erase_size_high, size_high;
1194 struct block_eraser *eraser;
1195
1196 total_size = hwseq_data.size_comp0 + hwseq_data.size_comp1;
1197 msg_cdbg("Found %d attached SPI flash chip",
1198 (hwseq_data.size_comp1 != 0) ? 2 : 1);
1199 if (hwseq_data.size_comp1 != 0)
1200 msg_cdbg("s with a combined");
1201 else
1202 msg_cdbg(" with a");
1203 msg_cdbg(" density of %d kB.\n", total_size / 1024);
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001204 flash->chip->total_size = total_size / 1024;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001205
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001206 eraser = &(flash->chip->block_erasers[0]);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001207 boundary = (REGREAD32(ICH9_REG_FPB) & FPB_FPBA) << 12;
1208 size_high = total_size - boundary;
1209 erase_size_high = ich_hwseq_get_erase_block_size(boundary);
1210
1211 if (boundary == 0) {
1212 msg_cdbg("There is only one partition containing the whole "
1213 "address space (0x%06x - 0x%06x).\n", 0, size_high-1);
1214 eraser->eraseblocks[0].size = erase_size_high;
1215 eraser->eraseblocks[0].count = size_high / erase_size_high;
1216 msg_cdbg("There are %d erase blocks with %d B each.\n",
1217 size_high / erase_size_high, erase_size_high);
1218 } else {
1219 msg_cdbg("The flash address space (0x%06x - 0x%06x) is divided "
1220 "at address 0x%06x in two partitions.\n",
Stefan Taunerdbac46c2013-08-13 22:10:41 +00001221 0, total_size-1, boundary);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001222 size_low = total_size - size_high;
1223 erase_size_low = ich_hwseq_get_erase_block_size(0);
1224
1225 eraser->eraseblocks[0].size = erase_size_low;
1226 eraser->eraseblocks[0].count = size_low / erase_size_low;
1227 msg_cdbg("The first partition ranges from 0x%06x to 0x%06x.\n",
1228 0, size_low-1);
1229 msg_cdbg("In that range are %d erase blocks with %d B each.\n",
1230 size_low / erase_size_low, erase_size_low);
1231
1232 eraser->eraseblocks[1].size = erase_size_high;
1233 eraser->eraseblocks[1].count = size_high / erase_size_high;
1234 msg_cdbg("The second partition ranges from 0x%06x to 0x%06x.\n",
Stefan Taunerdbac46c2013-08-13 22:10:41 +00001235 boundary, total_size-1);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001236 msg_cdbg("In that range are %d erase blocks with %d B each.\n",
1237 size_high / erase_size_high, erase_size_high);
1238 }
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001239 flash->chip->tested = TEST_OK_PREW;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001240 return 1;
1241}
1242
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001243static int ich_hwseq_block_erase(struct flashctx *flash, unsigned int addr,
1244 unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001245{
1246 uint32_t erase_block;
1247 uint16_t hsfc;
1248 uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */
1249
1250 erase_block = ich_hwseq_get_erase_block_size(addr);
1251 if (len != erase_block) {
1252 msg_cerr("Erase block size for address 0x%06x is %d B, "
1253 "but requested erase block size is %d B. "
1254 "Not erasing anything.\n", addr, erase_block, len);
1255 return -1;
1256 }
1257
1258 /* Although the hardware supports this (it would erase the whole block
1259 * containing the address) we play safe here. */
1260 if (addr % erase_block != 0) {
1261 msg_cerr("Erase address 0x%06x is not aligned to the erase "
1262 "block boundary (any multiple of %d). "
1263 "Not erasing anything.\n", addr, erase_block);
1264 return -1;
1265 }
1266
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001267 if (addr + len > flash->chip->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001268 msg_perr("Request to erase some inaccessible memory address(es)"
1269 " (addr=0x%x, len=%d). "
1270 "Not erasing anything.\n", addr, len);
1271 return -1;
1272 }
1273
1274 msg_pdbg("Erasing %d bytes starting at 0x%06x.\n", len, addr);
1275
1276 /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
1277 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1278
1279 hsfc = REGREAD16(ICH9_REG_HSFC);
1280 hsfc &= ~HSFC_FCYCLE; /* clear operation */
1281 hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
1282 hsfc |= HSFC_FGO; /* start */
1283 msg_pdbg("HSFC used for block erasing: ");
1284 prettyprint_ich9_reg_hsfc(hsfc);
1285 REGWRITE16(ICH9_REG_HSFC, hsfc);
1286
1287 if (ich_hwseq_wait_for_cycle_complete(timeout, len))
1288 return -1;
1289 return 0;
1290}
1291
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001292static int ich_hwseq_read(struct flashctx *flash, uint8_t *buf,
1293 unsigned int addr, unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001294{
1295 uint16_t hsfc;
1296 uint16_t timeout = 100 * 60;
1297 uint8_t block_len;
1298
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001299 if (addr + len > flash->chip->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001300 msg_perr("Request to read from an inaccessible memory address "
1301 "(addr=0x%x, len=%d).\n", addr, len);
1302 return -1;
1303 }
1304
1305 msg_pdbg("Reading %d bytes starting at 0x%06x.\n", len, addr);
1306 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
1307 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1308
1309 while (len > 0) {
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001310 block_len = min(len, flash->mst->opaque.max_data_read);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001311 ich_hwseq_set_addr(addr);
1312 hsfc = REGREAD16(ICH9_REG_HSFC);
1313 hsfc &= ~HSFC_FCYCLE; /* set read operation */
1314 hsfc &= ~HSFC_FDBC; /* clear byte count */
1315 /* set byte count */
1316 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
1317 hsfc |= HSFC_FGO; /* start */
1318 REGWRITE16(ICH9_REG_HSFC, hsfc);
1319
1320 if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
1321 return 1;
1322 ich_read_data(buf, block_len, ICH9_REG_FDATA0);
1323 addr += block_len;
1324 buf += block_len;
1325 len -= block_len;
1326 }
1327 return 0;
1328}
1329
Mark Marshallf20b7be2014-05-09 21:16:21 +00001330static int ich_hwseq_write(struct flashctx *flash, const uint8_t *buf, unsigned int addr, unsigned int len)
Stefan Tauner50e7c602011-11-08 10:55:54 +00001331{
1332 uint16_t hsfc;
1333 uint16_t timeout = 100 * 60;
1334 uint8_t block_len;
1335
Carl-Daniel Hailfinger5a7cb842012-08-25 01:17:58 +00001336 if (addr + len > flash->chip->total_size * 1024) {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001337 msg_perr("Request to write to an inaccessible memory address "
1338 "(addr=0x%x, len=%d).\n", addr, len);
1339 return -1;
1340 }
1341
1342 msg_pdbg("Writing %d bytes starting at 0x%06x.\n", len, addr);
1343 /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
1344 REGWRITE16(ICH9_REG_HSFS, REGREAD16(ICH9_REG_HSFS));
1345
1346 while (len > 0) {
1347 ich_hwseq_set_addr(addr);
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001348 block_len = min(len, flash->mst->opaque.max_data_write);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001349 ich_fill_data(buf, block_len, ICH9_REG_FDATA0);
1350 hsfc = REGREAD16(ICH9_REG_HSFC);
1351 hsfc &= ~HSFC_FCYCLE; /* clear operation */
1352 hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */
1353 hsfc &= ~HSFC_FDBC; /* clear byte count */
1354 /* set byte count */
1355 hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
1356 hsfc |= HSFC_FGO; /* start */
1357 REGWRITE16(ICH9_REG_HSFC, hsfc);
1358
1359 if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
1360 return -1;
1361 addr += block_len;
1362 buf += block_len;
1363 len -= block_len;
1364 }
1365 return 0;
1366}
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001367
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001368static int ich_spi_send_multicommand(struct flashctx *flash,
1369 struct spi_command *cmds)
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001370{
1371 int ret = 0;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001372 int i;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001373 int oppos, preoppos;
1374 for (; (cmds->writecnt || cmds->readcnt) && !ret; cmds++) {
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001375 if ((cmds + 1)->writecnt || (cmds + 1)->readcnt) {
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001376 /* Next command is valid. */
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001377 preoppos = find_preop(curopcodes, cmds->writearr[0]);
1378 oppos = find_opcode(curopcodes, (cmds + 1)->writearr[0]);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001379 if ((oppos == -1) && (preoppos != -1)) {
1380 /* Current command is listed as preopcode in
1381 * ICH struct OPCODES, but next command is not
1382 * listed as opcode in that struct.
1383 * Check for command sanity, then
1384 * try to reprogram the ICH opcode list.
1385 */
1386 if (find_preop(curopcodes,
1387 (cmds + 1)->writearr[0]) != -1) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001388 msg_perr("%s: Two subsequent "
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001389 "preopcodes 0x%02x and 0x%02x, "
1390 "ignoring the first.\n",
1391 __func__, cmds->writearr[0],
1392 (cmds + 1)->writearr[0]);
1393 continue;
1394 }
1395 /* If the chipset is locked down, we'll fail
1396 * during execution of the next command anyway.
1397 * No need to bother with fixups.
1398 */
1399 if (!ichspi_lock) {
Helge Wagner738e2522010-10-05 22:06:05 +00001400 oppos = reprogram_opcode_on_the_fly((cmds + 1)->writearr[0], (cmds + 1)->writecnt, (cmds + 1)->readcnt);
1401 if (oppos == -1)
1402 continue;
1403 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001404 continue;
1405 }
1406 }
1407 if ((oppos != -1) && (preoppos != -1)) {
1408 /* Current command is listed as preopcode in
1409 * ICH struct OPCODES and next command is listed
1410 * as opcode in that struct. Match them up.
1411 */
1412 curopcodes->opcode[oppos].atomic = preoppos + 1;
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001413 continue;
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001414 }
1415 /* If none of the above if-statements about oppos or
1416 * preoppos matched, this is a normal opcode.
1417 */
1418 }
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +00001419 ret = ich_spi_send_command(flash, cmds->writecnt, cmds->readcnt,
Carl-Daniel Hailfinger26f7e642009-09-18 15:50:56 +00001420 cmds->writearr, cmds->readarr);
Carl-Daniel Hailfingerf15e1ab2010-02-11 11:28:37 +00001421 /* Reset the type of all opcodes to non-atomic. */
1422 for (i = 0; i < 8; i++)
1423 curopcodes->opcode[i].atomic = 0;
Carl-Daniel Hailfinger02487aa2009-07-22 15:36:50 +00001424 }
1425 return ret;
1426}
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001427
Michael Karchera4448d92010-07-22 18:04:15 +00001428#define ICH_BMWAG(x) ((x >> 24) & 0xff)
1429#define ICH_BMRAG(x) ((x >> 16) & 0xff)
1430#define ICH_BRWA(x) ((x >> 8) & 0xff)
1431#define ICH_BRRA(x) ((x >> 0) & 0xff)
1432
Stefan Tauner5210e722012-02-16 01:13:00 +00001433/* returns 0 if region is unused or r/w */
1434static int ich9_handle_frap(uint32_t frap, int i)
Michael Karchera4448d92010-07-22 18:04:15 +00001435{
Mathias Krausea60faab2011-01-17 07:50:42 +00001436 static const char *const access_names[4] = {
Michael Karchera4448d92010-07-22 18:04:15 +00001437 "locked", "read-only", "write-only", "read-write"
1438 };
Mathias Krausea60faab2011-01-17 07:50:42 +00001439 static const char *const region_names[5] = {
Michael Karchera4448d92010-07-22 18:04:15 +00001440 "Flash Descriptor", "BIOS", "Management Engine",
1441 "Gigabit Ethernet", "Platform Data"
1442 };
1443 uint32_t base, limit;
1444 int rwperms = (((ICH_BRWA(frap) >> i) & 1) << 1) |
1445 (((ICH_BRRA(frap) >> i) & 1) << 0);
Stefan Tauner29c80832011-06-12 08:14:10 +00001446 int offset = ICH9_REG_FREG0 + i * 4;
Michael Karchera4448d92010-07-22 18:04:15 +00001447 uint32_t freg = mmio_readl(ich_spibar + offset);
1448
Michael Karchera4448d92010-07-22 18:04:15 +00001449 base = ICH_FREG_BASE(freg);
1450 limit = ICH_FREG_LIMIT(freg);
Stefan Taunere3adea02012-08-27 15:12:36 +00001451 if (base > limit || (freg == 0 && i > 0)) {
Michael Karchera4448d92010-07-22 18:04:15 +00001452 /* this FREG is disabled */
Stefan Tauner5210e722012-02-16 01:13:00 +00001453 msg_pdbg2("0x%02X: 0x%08x FREG%i: %s region is unused.\n",
1454 offset, freg, i, region_names[i]);
1455 return 0;
1456 }
1457 msg_pdbg("0x%02X: 0x%08x ", offset, freg);
1458 if (rwperms == 0x3) {
1459 msg_pdbg("FREG%i: %s region (0x%08x-0x%08x) is %s.\n", i,
1460 region_names[i], base, (limit | 0x0fff),
1461 access_names[rwperms]);
1462 return 0;
Michael Karchera4448d92010-07-22 18:04:15 +00001463 }
1464
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00001465 msg_pwarn("FREG%i: Warning: %s region (0x%08x-0x%08x) is %s.\n", i,
Stefan Tauner5210e722012-02-16 01:13:00 +00001466 region_names[i], base, (limit | 0x0fff),
1467 access_names[rwperms]);
1468 return 1;
Michael Karchera4448d92010-07-22 18:04:15 +00001469}
1470
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001471 /* In contrast to FRAP and the master section of the descriptor the bits
1472 * in the PR registers have an inverted meaning. The bits in FRAP
1473 * indicate read and write access _grant_. Here they indicate read
1474 * and write _protection_ respectively. If both bits are 0 the address
1475 * bits are ignored.
1476 */
1477#define ICH_PR_PERMS(pr) (((~((pr) >> PR_RP_OFF) & 1) << 0) | \
1478 ((~((pr) >> PR_WP_OFF) & 1) << 1))
1479
Stefan Tauner5210e722012-02-16 01:13:00 +00001480/* returns 0 if range is unused (i.e. r/w) */
1481static int ich9_handle_pr(int i)
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001482{
Stefan Tauner5210e722012-02-16 01:13:00 +00001483 static const char *const access_names[3] = {
1484 "locked", "read-only", "write-only"
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001485 };
1486 uint8_t off = ICH9_REG_PR0 + (i * 4);
1487 uint32_t pr = mmio_readl(ich_spibar + off);
Stefan Tauner5210e722012-02-16 01:13:00 +00001488 unsigned int rwperms = ICH_PR_PERMS(pr);
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001489
Stefan Tauner5210e722012-02-16 01:13:00 +00001490 if (rwperms == 0x3) {
1491 msg_pdbg2("0x%02X: 0x%08x (PR%u is unused)\n", off, pr, i);
1492 return 0;
1493 }
1494
1495 msg_pdbg("0x%02X: 0x%08x ", off, pr);
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00001496 msg_pwarn("PR%u: Warning: 0x%08x-0x%08x is %s.\n", i, ICH_FREG_BASE(pr),
Stefan Tauner5210e722012-02-16 01:13:00 +00001497 ICH_FREG_LIMIT(pr) | 0x0fff, access_names[rwperms]);
1498 return 1;
Stefan Taunerbf69aaa2011-09-17 21:21:48 +00001499}
1500
Stefan Tauner75da80c2011-09-17 22:21:55 +00001501/* Set/Clear the read and write protection enable bits of PR register @i
1502 * according to @read_prot and @write_prot. */
1503static void ich9_set_pr(int i, int read_prot, int write_prot)
1504{
1505 void *addr = ich_spibar + ICH9_REG_PR0 + (i * 4);
1506 uint32_t old = mmio_readl(addr);
1507 uint32_t new;
1508
1509 msg_gspew("PR%u is 0x%08x", i, old);
1510 new = old & ~((1 << PR_RP_OFF) | (1 << PR_WP_OFF));
1511 if (read_prot)
1512 new |= (1 << PR_RP_OFF);
1513 if (write_prot)
1514 new |= (1 << PR_WP_OFF);
1515 if (old == new) {
1516 msg_gspew(" already.\n");
1517 return;
1518 }
1519 msg_gspew(", trying to set it to 0x%08x ", new);
1520 rmmio_writel(new, addr);
1521 msg_gspew("resulted in 0x%08x.\n", mmio_readl(addr));
1522}
1523
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001524static const struct spi_master spi_master_ich7 = {
Michael Karcherb9dbe482011-05-11 17:07:07 +00001525 .type = SPI_CONTROLLER_ICH7,
1526 .max_data_read = 64,
1527 .max_data_write = 64,
1528 .command = ich_spi_send_command,
1529 .multicommand = ich_spi_send_multicommand,
1530 .read = default_spi_read,
1531 .write_256 = default_spi_write_256,
Nico Huber7bca1262012-06-15 22:28:12 +00001532 .write_aai = default_spi_write_aai,
Michael Karcherb9dbe482011-05-11 17:07:07 +00001533};
1534
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001535static const struct spi_master spi_master_ich9 = {
Michael Karcherb9dbe482011-05-11 17:07:07 +00001536 .type = SPI_CONTROLLER_ICH9,
1537 .max_data_read = 64,
1538 .max_data_write = 64,
1539 .command = ich_spi_send_command,
1540 .multicommand = ich_spi_send_multicommand,
1541 .read = default_spi_read,
1542 .write_256 = default_spi_write_256,
Nico Huber7bca1262012-06-15 22:28:12 +00001543 .write_aai = default_spi_write_aai,
Michael Karcherb9dbe482011-05-11 17:07:07 +00001544};
1545
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001546static const struct opaque_master opaque_master_ich_hwseq = {
Stefan Tauner50e7c602011-11-08 10:55:54 +00001547 .max_data_read = 64,
1548 .max_data_write = 64,
1549 .probe = ich_hwseq_probe,
1550 .read = ich_hwseq_read,
1551 .write = ich_hwseq_write,
1552 .erase = ich_hwseq_block_erase,
1553};
1554
Stefan Tauner92d6a862013-10-25 00:33:37 +00001555int ich_init_spi(struct pci_dev *dev, void *spibar, enum ich_chipset ich_gen)
Michael Karchera4448d92010-07-22 18:04:15 +00001556{
1557 int i;
Stefan Tauner92d6a862013-10-25 00:33:37 +00001558 uint16_t tmp2;
Michael Karchera4448d92010-07-22 18:04:15 +00001559 uint32_t tmp;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001560 char *arg;
Stefan Tauner5210e722012-02-16 01:13:00 +00001561 int ich_spi_force = 0;
1562 int ich_spi_rw_restricted = 0;
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001563 int desc_valid = 0;
Stefan Tauner50e7c602011-11-08 10:55:54 +00001564 struct ich_descriptors desc = {{ 0 }};
1565 enum ich_spi_mode {
1566 ich_auto,
1567 ich_hwseq,
1568 ich_swseq
1569 } ich_spi_mode = ich_auto;
Michael Karchera4448d92010-07-22 18:04:15 +00001570
Stefan Taunera8d838d2011-11-06 23:51:09 +00001571 ich_generation = ich_gen;
Stefan Tauner92d6a862013-10-25 00:33:37 +00001572 ich_spibar = spibar;
Michael Karchera4448d92010-07-22 18:04:15 +00001573
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001574 switch (ich_generation) {
Stefan Taunera8d838d2011-11-06 23:51:09 +00001575 case CHIPSET_ICH7:
Stefan Tauner92d6a862013-10-25 00:33:37 +00001576 case CHIPSET_TUNNEL_CREEK:
1577 case CHIPSET_CENTERTON:
Michael Karchera4448d92010-07-22 18:04:15 +00001578 msg_pdbg("0x00: 0x%04x (SPIS)\n",
1579 mmio_readw(ich_spibar + 0));
1580 msg_pdbg("0x02: 0x%04x (SPIC)\n",
1581 mmio_readw(ich_spibar + 2));
1582 msg_pdbg("0x04: 0x%08x (SPIA)\n",
1583 mmio_readl(ich_spibar + 4));
Michael Karchera4448d92010-07-22 18:04:15 +00001584 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
1585 msg_pdbg("0x50: 0x%08x (BBAR)\n",
1586 ichspi_bbar);
1587 msg_pdbg("0x54: 0x%04x (PREOP)\n",
1588 mmio_readw(ich_spibar + 0x54));
1589 msg_pdbg("0x56: 0x%04x (OPTYPE)\n",
1590 mmio_readw(ich_spibar + 0x56));
1591 msg_pdbg("0x58: 0x%08x (OPMENU)\n",
1592 mmio_readl(ich_spibar + 0x58));
1593 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n",
1594 mmio_readl(ich_spibar + 0x5c));
Stefan Tauner122dd122011-07-24 15:34:56 +00001595 for (i = 0; i < 3; i++) {
Michael Karchera4448d92010-07-22 18:04:15 +00001596 int offs;
1597 offs = 0x60 + (i * 4);
1598 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
1599 mmio_readl(ich_spibar + offs), i);
1600 }
Michael Karchera4448d92010-07-22 18:04:15 +00001601 if (mmio_readw(ich_spibar) & (1 << 15)) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00001602 msg_pwarn("WARNING: SPI Configuration Lockdown activated.\n");
Michael Karchera4448d92010-07-22 18:04:15 +00001603 ichspi_lock = 1;
1604 }
Stefan Tauner745f6bb2011-11-13 15:17:10 +00001605 ich_init_opcodes();
Stefan Taunera8d838d2011-11-06 23:51:09 +00001606 ich_set_bbar(0);
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001607 register_spi_master(&spi_master_ich7);
Michael Karchera4448d92010-07-22 18:04:15 +00001608 break;
Stefan Taunera8d838d2011-11-06 23:51:09 +00001609 case CHIPSET_ICH8:
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001610 default: /* Future version might behave the same */
Stefan Tauner50e7c602011-11-08 10:55:54 +00001611 arg = extract_programmer_param("ich_spi_mode");
1612 if (arg && !strcmp(arg, "hwseq")) {
1613 ich_spi_mode = ich_hwseq;
1614 msg_pspew("user selected hwseq\n");
1615 } else if (arg && !strcmp(arg, "swseq")) {
1616 ich_spi_mode = ich_swseq;
1617 msg_pspew("user selected swseq\n");
1618 } else if (arg && !strcmp(arg, "auto")) {
1619 msg_pspew("user selected auto\n");
1620 ich_spi_mode = ich_auto;
1621 } else if (arg && !strlen(arg)) {
1622 msg_perr("Missing argument for ich_spi_mode.\n");
1623 free(arg);
1624 return ERROR_FATAL;
1625 } else if (arg) {
1626 msg_perr("Unknown argument for ich_spi_mode: %s\n",
1627 arg);
1628 free(arg);
1629 return ERROR_FATAL;
1630 }
1631 free(arg);
1632
Stefan Tauner5210e722012-02-16 01:13:00 +00001633 arg = extract_programmer_param("ich_spi_force");
1634 if (arg && !strcmp(arg, "yes")) {
1635 ich_spi_force = 1;
1636 msg_pspew("ich_spi_force enabled.\n");
1637 } else if (arg && !strlen(arg)) {
1638 msg_perr("Missing argument for ich_spi_force.\n");
1639 free(arg);
1640 return ERROR_FATAL;
1641 } else if (arg) {
1642 msg_perr("Unknown argument for ich_spi_force: \"%s\" "
1643 "(not \"yes\").\n", arg);
1644 free(arg);
1645 return ERROR_FATAL;
1646 }
1647 free(arg);
1648
Stefan Tauner29c80832011-06-12 08:14:10 +00001649 tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFS);
Michael Karchera4448d92010-07-22 18:04:15 +00001650 msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2);
Stefan Tauner55206942011-06-11 09:53:22 +00001651 prettyprint_ich9_reg_hsfs(tmp2);
Stefan Tauner29c80832011-06-12 08:14:10 +00001652 if (tmp2 & HSFS_FLOCKDN) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00001653 msg_pwarn("Warning: SPI Configuration Lockdown activated.\n");
Stefan Tauner55206942011-06-11 09:53:22 +00001654 ichspi_lock = 1;
1655 }
Stefan Tauner1e146392011-09-15 23:52:55 +00001656 if (tmp2 & HSFS_FDV)
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001657 desc_valid = 1;
1658 if (!(tmp2 & HSFS_FDOPSS) && desc_valid)
Stefan Taunerd7d423b2012-10-20 09:13:16 +00001659 msg_pinfo("The Flash Descriptor Override Strap-Pin is set. Restrictions implied by\n"
1660 "the Master Section of the flash descriptor are NOT in effect. Please note\n"
1661 "that Protected Range (PR) restrictions still apply.\n");
Stefan Tauner745f6bb2011-11-13 15:17:10 +00001662 ich_init_opcodes();
Stefan Tauner55206942011-06-11 09:53:22 +00001663
Stefan Taunerf382e352011-11-08 11:55:24 +00001664 if (desc_valid) {
1665 tmp2 = mmio_readw(ich_spibar + ICH9_REG_HSFC);
1666 msg_pdbg("0x06: 0x%04x (HSFC)\n", tmp2);
1667 prettyprint_ich9_reg_hsfc(tmp2);
1668 }
Michael Karchera4448d92010-07-22 18:04:15 +00001669
Stefan Tauner5ffe65b2011-07-07 04:10:57 +00001670 tmp = mmio_readl(ich_spibar + ICH9_REG_FADDR);
Stefan Taunereb582572012-09-21 12:52:50 +00001671 msg_pdbg2("0x08: 0x%08x (FADDR)\n", tmp);
Michael Karchera4448d92010-07-22 18:04:15 +00001672
Stefan Taunerf382e352011-11-08 11:55:24 +00001673 if (desc_valid) {
1674 tmp = mmio_readl(ich_spibar + ICH9_REG_FRAP);
1675 msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp);
1676 msg_pdbg("BMWAG 0x%02x, ", ICH_BMWAG(tmp));
1677 msg_pdbg("BMRAG 0x%02x, ", ICH_BMRAG(tmp));
1678 msg_pdbg("BRWA 0x%02x, ", ICH_BRWA(tmp));
1679 msg_pdbg("BRRA 0x%02x\n", ICH_BRRA(tmp));
1680
Stefan Tauner5210e722012-02-16 01:13:00 +00001681 /* Handle FREGx and FRAP registers */
Stefan Taunerf382e352011-11-08 11:55:24 +00001682 for (i = 0; i < 5; i++)
Stefan Tauner5210e722012-02-16 01:13:00 +00001683 ich_spi_rw_restricted |= ich9_handle_frap(tmp, i);
Stefan Tauner27cb34b2013-06-01 00:06:12 +00001684 if (ich_spi_rw_restricted)
1685 msg_pwarn("Not all flash regions are freely accessible by flashrom. This is "
1686 "most likely\ndue to an active ME. Please see http://flashrom.org/ME "
1687 "for details.\n");
Stefan Taunerf382e352011-11-08 11:55:24 +00001688 }
Michael Karchera4448d92010-07-22 18:04:15 +00001689
Stefan Taunereb582572012-09-21 12:52:50 +00001690 /* Handle PR registers */
Stefan Tauner5210e722012-02-16 01:13:00 +00001691 for (i = 0; i < 5; i++) {
1692 /* if not locked down try to disable PR locks first */
1693 if (!ichspi_lock)
Stefan Tauner75da80c2011-09-17 22:21:55 +00001694 ich9_set_pr(i, 0, 0);
Stefan Tauner5210e722012-02-16 01:13:00 +00001695 ich_spi_rw_restricted |= ich9_handle_pr(i);
1696 }
1697
1698 if (ich_spi_rw_restricted) {
Stefan Tauner5210e722012-02-16 01:13:00 +00001699 if (!ich_spi_force)
1700 programmer_may_write = 0;
Stefan Taunerd7d423b2012-10-20 09:13:16 +00001701 msg_pinfo("Writes have been disabled for safety reasons. You can enforce write\n"
1702 "support with the ich_spi_force programmer option, but you will most likely\n"
1703 "harm your hardware! If you force flashrom you will get no support if\n"
1704 "something breaks. On a few mainboards it is possible to enable write\n"
1705 "access by setting a jumper (see its documentation or the board itself).\n");
Stefan Tauner5210e722012-02-16 01:13:00 +00001706 if (ich_spi_force)
Stefan Taunerd7d423b2012-10-20 09:13:16 +00001707 msg_pinfo("Continuing with write support because the user forced us to!\n");
Stefan Tauner5210e722012-02-16 01:13:00 +00001708 }
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001709
Stefan Tauner29c80832011-06-12 08:14:10 +00001710 tmp = mmio_readl(ich_spibar + ICH9_REG_SSFS);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001711 msg_pdbg("0x90: 0x%02x (SSFS)\n", tmp & 0xff);
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001712 prettyprint_ich9_reg_ssfs(tmp);
Stefan Tauner29c80832011-06-12 08:14:10 +00001713 if (tmp & SSFS_FCERR) {
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001714 msg_pdbg("Clearing SSFS.FCERR\n");
Stefan Tauner29c80832011-06-12 08:14:10 +00001715 mmio_writeb(SSFS_FCERR, ich_spibar + ICH9_REG_SSFS);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001716 }
Stefan Tauner2a8b2622011-06-11 09:53:16 +00001717 msg_pdbg("0x91: 0x%06x (SSFC)\n", tmp >> 8);
1718 prettyprint_ich9_reg_ssfc(tmp);
Carl-Daniel Hailfingereacbd162011-03-17 00:10:25 +00001719
Michael Karchera4448d92010-07-22 18:04:15 +00001720 msg_pdbg("0x94: 0x%04x (PREOP)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001721 mmio_readw(ich_spibar + ICH9_REG_PREOP));
Michael Karchera4448d92010-07-22 18:04:15 +00001722 msg_pdbg("0x96: 0x%04x (OPTYPE)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001723 mmio_readw(ich_spibar + ICH9_REG_OPTYPE));
Michael Karchera4448d92010-07-22 18:04:15 +00001724 msg_pdbg("0x98: 0x%08x (OPMENU)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001725 mmio_readl(ich_spibar + ICH9_REG_OPMENU));
Michael Karchera4448d92010-07-22 18:04:15 +00001726 msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n",
Stefan Tauner29c80832011-06-12 08:14:10 +00001727 mmio_readl(ich_spibar + ICH9_REG_OPMENU + 4));
Stefan Taunerf382e352011-11-08 11:55:24 +00001728 if (ich_generation == CHIPSET_ICH8 && desc_valid) {
Stefan Tauner1e146392011-09-15 23:52:55 +00001729 tmp = mmio_readl(ich_spibar + ICH8_REG_VSCC);
1730 msg_pdbg("0xC1: 0x%08x (VSCC)\n", tmp);
1731 msg_pdbg("VSCC: ");
1732 prettyprint_ich_reg_vscc(tmp, MSG_DEBUG);
1733 } else {
1734 ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR);
1735 msg_pdbg("0xA0: 0x%08x (BBAR)\n",
1736 ichspi_bbar);
Stefan Taunerbd649e42011-07-01 00:39:16 +00001737
Stefan Taunerf382e352011-11-08 11:55:24 +00001738 if (desc_valid) {
1739 tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC);
1740 msg_pdbg("0xC4: 0x%08x (LVSCC)\n", tmp);
1741 msg_pdbg("LVSCC: ");
1742 prettyprint_ich_reg_vscc(tmp, MSG_DEBUG);
Stefan Tauner1e146392011-09-15 23:52:55 +00001743
Stefan Taunerf382e352011-11-08 11:55:24 +00001744 tmp = mmio_readl(ich_spibar + ICH9_REG_UVSCC);
1745 msg_pdbg("0xC8: 0x%08x (UVSCC)\n", tmp);
1746 msg_pdbg("UVSCC: ");
1747 prettyprint_ich_reg_vscc(tmp, MSG_DEBUG);
Stefan Tauner1e146392011-09-15 23:52:55 +00001748
Stefan Taunerf382e352011-11-08 11:55:24 +00001749 tmp = mmio_readl(ich_spibar + ICH9_REG_FPB);
1750 msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp);
1751 }
Stefan Taunera8d838d2011-11-06 23:51:09 +00001752 ich_set_bbar(0);
Stefan Tauner1e146392011-09-15 23:52:55 +00001753 }
1754
1755 msg_pdbg("\n");
Stefan Taunerd0c5dc22011-10-20 12:57:14 +00001756 if (desc_valid) {
Stefan Tauner1e146392011-09-15 23:52:55 +00001757 if (read_ich_descriptors_via_fdo(ich_spibar, &desc) ==
1758 ICH_RET_OK)
1759 prettyprint_ich_descriptors(CHIPSET_ICH_UNKNOWN,
1760 &desc);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001761 /* If the descriptor is valid and indicates multiple
1762 * flash devices we need to use hwseq to be able to
1763 * access the second flash device.
1764 */
1765 if (ich_spi_mode == ich_auto && desc.content.NC != 0) {
1766 msg_pinfo("Enabling hardware sequencing due to "
1767 "multiple flash chips detected.\n");
1768 ich_spi_mode = ich_hwseq;
1769 }
Stefan Tauner1e146392011-09-15 23:52:55 +00001770 }
Stefan Tauner50e7c602011-11-08 10:55:54 +00001771
1772 if (ich_spi_mode == ich_auto && ichspi_lock &&
1773 ich_missing_opcodes()) {
1774 msg_pinfo("Enabling hardware sequencing because "
1775 "some important opcode is locked.\n");
1776 ich_spi_mode = ich_hwseq;
1777 }
1778
1779 if (ich_spi_mode == ich_hwseq) {
1780 if (!desc_valid) {
1781 msg_perr("Hardware sequencing was requested "
1782 "but the flash descriptor is not "
1783 "valid. Aborting.\n");
1784 return ERROR_FATAL;
1785 }
1786 hwseq_data.size_comp0 = getFCBA_component_density(&desc, 0);
1787 hwseq_data.size_comp1 = getFCBA_component_density(&desc, 1);
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001788 register_opaque_master(&opaque_master_ich_hwseq);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001789 } else {
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001790 register_spi_master(&spi_master_ich9);
Stefan Tauner50e7c602011-11-08 10:55:54 +00001791 }
Michael Karchera4448d92010-07-22 18:04:15 +00001792 break;
Michael Karchera4448d92010-07-22 18:04:15 +00001793 }
1794
Michael Karchera4448d92010-07-22 18:04:15 +00001795 return 0;
1796}
1797
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001798static const struct spi_master spi_master_via = {
Michael Karcherb9dbe482011-05-11 17:07:07 +00001799 .type = SPI_CONTROLLER_VIA,
1800 .max_data_read = 16,
1801 .max_data_write = 16,
1802 .command = ich_spi_send_command,
1803 .multicommand = ich_spi_send_multicommand,
1804 .read = default_spi_read,
1805 .write_256 = default_spi_write_256,
Nico Huber7bca1262012-06-15 22:28:12 +00001806 .write_aai = default_spi_write_aai,
Michael Karcherb9dbe482011-05-11 17:07:07 +00001807};
1808
Helge Wagnerdd73d832012-08-24 23:03:46 +00001809int via_init_spi(struct pci_dev *dev, uint32_t mmio_base)
Michael Karchera4448d92010-07-22 18:04:15 +00001810{
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00001811 int i;
Michael Karchera4448d92010-07-22 18:04:15 +00001812
Stefan Tauner7fb5aa02013-08-14 15:48:44 +00001813 ich_spibar = rphysmap("VIA SPI MMIO registers", mmio_base, 0x70);
1814 if (ich_spibar == ERROR_PTR)
1815 return ERROR_FATAL;
Helge Wagnerdd73d832012-08-24 23:03:46 +00001816 /* Do we really need no write enable? Like the LPC one at D17F0 0x40 */
Michael Karchera4448d92010-07-22 18:04:15 +00001817
Michael Karchera4448d92010-07-22 18:04:15 +00001818 /* Not sure if it speaks all these bus protocols. */
Carl-Daniel Hailfingereaacd2d2011-11-09 23:40:00 +00001819 internal_buses_supported = BUS_LPC | BUS_FWH;
Stefan Taunera8d838d2011-11-06 23:51:09 +00001820 ich_generation = CHIPSET_ICH7;
Carl-Daniel Hailfingera5bcbce2014-07-19 22:03:29 +00001821 register_spi_master(&spi_master_via);
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00001822
1823 msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0));
1824 msg_pdbg("0x02: 0x%04x (SPIC)\n", mmio_readw(ich_spibar + 2));
1825 msg_pdbg("0x04: 0x%08x (SPIA)\n", mmio_readl(ich_spibar + 4));
1826 for (i = 0; i < 2; i++) {
1827 int offs;
1828 offs = 8 + (i * 8);
1829 msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs,
1830 mmio_readl(ich_spibar + offs), i);
1831 msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
1832 mmio_readl(ich_spibar + offs + 4), i);
1833 }
1834 ichspi_bbar = mmio_readl(ich_spibar + 0x50);
1835 msg_pdbg("0x50: 0x%08x (BBAR)\n", ichspi_bbar);
1836 msg_pdbg("0x54: 0x%04x (PREOP)\n", mmio_readw(ich_spibar + 0x54));
1837 msg_pdbg("0x56: 0x%04x (OPTYPE)\n", mmio_readw(ich_spibar + 0x56));
1838 msg_pdbg("0x58: 0x%08x (OPMENU)\n", mmio_readl(ich_spibar + 0x58));
1839 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n", mmio_readl(ich_spibar + 0x5c));
1840 for (i = 0; i < 3; i++) {
1841 int offs;
1842 offs = 0x60 + (i * 4);
1843 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
1844 mmio_readl(ich_spibar + offs), i);
1845 }
1846 msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n",
1847 mmio_readw(ich_spibar + 0x6c));
1848 if (mmio_readw(ich_spibar) & (1 << 15)) {
Stefan Taunerc6fa32d2013-01-04 22:54:07 +00001849 msg_pwarn("Warning: SPI Configuration Lockdown activated.\n");
Carl-Daniel Hailfinger841d6312010-11-24 23:37:22 +00001850 ichspi_lock = 1;
1851 }
1852
Stefan Taunera8d838d2011-11-06 23:51:09 +00001853 ich_set_bbar(0);
Michael Karchera4448d92010-07-22 18:04:15 +00001854 ich_init_opcodes();
1855
1856 return 0;
1857}
1858
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001859#endif