blob: 21990f692aee8661d2a6fe2c12ed591a601d26b4 [file] [log] [blame]
Ollie Lho184a4042005-11-26 21:55:36 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ollie Lho184a4042005-11-26 21:55:36 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Stefan Reinauer8fa64812009-08-12 09:27:45 +00005 * Copyright (C) 2005-2009 coresystems GmbH
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00007 * Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger
Adam Jurkowskie4984102009-12-21 15:30:46 +00008 * Copyright (C) 2009 Kontron Modular Computers GmbH
Ollie Lho184a4042005-11-26 21:55:36 +00009 *
Uwe Hermannd1107642007-08-29 17:52:32 +000010 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
Ollie Lho184a4042005-11-26 21:55:36 +000013 *
Uwe Hermannd1107642007-08-29 17:52:32 +000014 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24/*
25 * Contains the chipset specific flash enables.
Ollie Lho184a4042005-11-26 21:55:36 +000026 */
27
Lane Brooksd54958a2007-11-13 16:45:22 +000028#define _LARGEFILE64_SOURCE
29
Ollie Lhocbbf1252004-03-17 22:22:08 +000030#include <stdlib.h>
Uwe Hermanne8ba5382009-05-22 11:37:27 +000031#include <string.h>
Carl-Daniel Hailfingerdcef67e2010-06-21 23:20:15 +000032#include <unistd.h>
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +000033#include <inttypes.h>
34#include <errno.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000035#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000036#include "programmer.h"
Stefan Reinauer86de2832006-03-31 11:26:55 +000037
Michael Karcher89bed6d2010-06-13 10:16:12 +000038#define NOT_DONE_YET 1
39
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +000040#if defined(__i386__) || defined(__x86_64__)
41
Uwe Hermann372eeb52007-12-04 21:49:06 +000042static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
Luc Verhaegen6b141752007-05-20 16:16:13 +000043{
44 uint8_t tmp;
45
Uwe Hermann372eeb52007-12-04 21:49:06 +000046 /*
47 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
48 * 0xFFFE0000-0xFFFFFFFF ROM select enable.
49 */
Luc Verhaegen6b141752007-05-20 16:16:13 +000050 tmp = pci_read_byte(dev, 0x47);
51 tmp |= 0x46;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000052 rpci_write_byte(dev, 0x47, tmp);
Luc Verhaegen6b141752007-05-20 16:16:13 +000053
54 return 0;
55}
56
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000057static int enable_flash_sis85c496(struct pci_dev *dev, const char *name)
58{
59 uint8_t tmp;
60
61 tmp = pci_read_byte(dev, 0xd0);
62 tmp |= 0xf8;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000063 rpci_write_byte(dev, 0xd0, tmp);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000064
65 return 0;
66}
67
68static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name)
69{
70 uint8_t new, newer;
71
72 /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
73 /* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
74 new = pci_read_byte(dev, 0x40);
75 new &= (~0x04); /* No idea why we clear bit 2. */
76 new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000077 rpci_write_byte(dev, 0x40, new);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000078 newer = pci_read_byte(dev, 0x40);
79 if (newer != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +000080 msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
81 msg_pinfo("Stuck at 0x%x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000082 return -1;
83 }
84 return 0;
85}
86
87static struct pci_dev *find_southbridge(uint16_t vendor, const char *name)
88{
89 struct pci_dev *sbdev;
90
91 sbdev = pci_dev_find_vendorclass(vendor, 0x0601);
92 if (!sbdev)
93 sbdev = pci_dev_find_vendorclass(vendor, 0x0680);
94 if (!sbdev)
95 sbdev = pci_dev_find_vendorclass(vendor, 0x0000);
96 if (!sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +000097 msg_perr("No southbridge found for %s!\n", name);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000098 if (sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +000099 msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n",
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000100 sbdev->vendor_id, sbdev->device_id,
101 sbdev->bus, sbdev->dev, sbdev->func);
102 return sbdev;
103}
104
105static int enable_flash_sis501(struct pci_dev *dev, const char *name)
106{
107 uint8_t tmp;
108 int ret = 0;
109 struct pci_dev *sbdev;
110
111 sbdev = find_southbridge(dev->vendor_id, name);
112 if (!sbdev)
113 return -1;
114
115 ret = enable_flash_sis_mapping(sbdev, name);
116
117 tmp = sio_read(0x22, 0x80);
118 tmp &= (~0x20);
119 tmp |= 0x4;
120 sio_write(0x22, 0x80, tmp);
121
122 tmp = sio_read(0x22, 0x70);
123 tmp &= (~0x20);
124 tmp |= 0x4;
125 sio_write(0x22, 0x70, tmp);
126
127 return ret;
128}
129
130static int enable_flash_sis5511(struct pci_dev *dev, const char *name)
131{
132 uint8_t tmp;
133 int ret = 0;
134 struct pci_dev *sbdev;
135
136 sbdev = find_southbridge(dev->vendor_id, name);
137 if (!sbdev)
138 return -1;
139
140 ret = enable_flash_sis_mapping(sbdev, name);
141
142 tmp = sio_read(0x22, 0x50);
143 tmp &= (~0x20);
144 tmp |= 0x4;
145 sio_write(0x22, 0x50, tmp);
146
147 return ret;
148}
149
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000150static int enable_flash_sis530(struct pci_dev *dev, const char *name)
151{
152 uint8_t new, newer;
153 int ret = 0;
154 struct pci_dev *sbdev;
155
156 sbdev = find_southbridge(dev->vendor_id, name);
157 if (!sbdev)
158 return -1;
159
160 ret = enable_flash_sis_mapping(sbdev, name);
161
162 new = pci_read_byte(sbdev, 0x45);
163 new &= (~0x20);
164 new |= 0x4;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000165 rpci_write_byte(sbdev, 0x45, new);
Luc Verhaegen9cce2f52010-01-10 15:01:08 +0000166 newer = pci_read_byte(sbdev, 0x45);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000167 if (newer != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000168 msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
169 msg_pinfo("Stuck at 0x%x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000170 ret = -1;
171 }
172
173 return ret;
174}
175
176static int enable_flash_sis540(struct pci_dev *dev, const char *name)
177{
178 uint8_t new, newer;
179 int ret = 0;
180 struct pci_dev *sbdev;
181
182 sbdev = find_southbridge(dev->vendor_id, name);
183 if (!sbdev)
184 return -1;
185
186 ret = enable_flash_sis_mapping(sbdev, name);
187
188 new = pci_read_byte(sbdev, 0x45);
189 new &= (~0x80);
190 new |= 0x40;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000191 rpci_write_byte(sbdev, 0x45, new);
Luc Verhaegen9cce2f52010-01-10 15:01:08 +0000192 newer = pci_read_byte(sbdev, 0x45);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000193 if (newer != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000194 msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
195 msg_pinfo("Stuck at 0x%x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000196 ret = -1;
197 }
198
199 return ret;
200}
201
Uwe Hermann987942d2006-11-07 11:16:21 +0000202/* Datasheet:
203 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
204 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
205 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
206 * - Order Number: 290562-001
207 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000208static int enable_flash_piix4(struct pci_dev *dev, const char *name)
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000209{
210 uint16_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000211 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000212
Maciej Pijankaa661e152009-12-08 17:26:24 +0000213 buses_supported = CHIP_BUSTYPE_PARALLEL;
214
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000215 old = pci_read_word(dev, xbcs);
216
217 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
Uwe Hermanna7e05482007-05-09 10:17:44 +0000218 * FFF00000-FFF7FFFF are forwarded to ISA).
Uwe Hermannc556d322008-10-28 11:50:05 +0000219 * Note: This bit is reserved on PIIX/PIIX3/MPIIX.
Uwe Hermanna7e05482007-05-09 10:17:44 +0000220 * Set bit 7: Extended BIOS Enable (PCI master accesses to
221 * FFF80000-FFFDFFFF are forwarded to ISA).
222 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
223 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
224 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
225 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
226 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
227 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
228 */
Uwe Hermannc556d322008-10-28 11:50:05 +0000229 if (dev->device_id == 0x122e || dev->device_id == 0x7000
230 || dev->device_id == 0x1234)
231 new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
Uwe Hermann87203452008-10-26 18:40:42 +0000232 else
233 new = old | 0x02c4;
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000234
235 if (new == old)
236 return 0;
237
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000238 rpci_write_word(dev, xbcs, new);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000239
240 if (pci_read_word(dev, xbcs) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000241 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000242 return -1;
243 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000244
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000245 return 0;
246}
247
Uwe Hermann372eeb52007-12-04 21:49:06 +0000248/*
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000249 * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet"
250 * http://download.intel.com/design/chipsets/datashts/30701303.pdf
Uwe Hermann372eeb52007-12-04 21:49:06 +0000251 */
252static int enable_flash_ich(struct pci_dev *dev, const char *name,
253 int bios_cntl)
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000254{
Ollie Lho184a4042005-11-26 21:55:36 +0000255 uint8_t old, new;
Stefan Reinauereb366472006-09-06 15:48:48 +0000256
Uwe Hermann372eeb52007-12-04 21:49:06 +0000257 /*
258 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
Uwe Hermanna7e05482007-05-09 10:17:44 +0000259 * just treating it as 8 bit wide seems to work fine in practice.
Stefan Reinauereb366472006-09-06 15:48:48 +0000260 */
Stefan Reinauer86de2832006-03-31 11:26:55 +0000261 old = pci_read_byte(dev, bios_cntl);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000262
Sean Nelson316a29f2010-05-07 20:09:04 +0000263 msg_pdbg("\nBIOS Lock Enable: %sabled, ",
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000264 (old & (1 << 1)) ? "en" : "dis");
Sean Nelson316a29f2010-05-07 20:09:04 +0000265 msg_pdbg("BIOS Write Enable: %sabled, ",
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000266 (old & (1 << 0)) ? "en" : "dis");
Sean Nelson316a29f2010-05-07 20:09:04 +0000267 msg_pdbg("BIOS_CNTL is 0x%x\n", old);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000268
Stefan Taunerf9a8da52011-06-11 18:16:50 +0000269 /*
270 * Quote from the 6 Series datasheet (Document Number: 324645-004):
271 * "Bit 5: SMM BIOS Write Protect Disable (SMM_BWP)
272 * 1 = BIOS region SMM protection is enabled.
273 * The BIOS Region is not writable unless all processors are in SMM."
274 * In earlier chipsets this bit is reserved. */
275 if (old & (1 << 5)) {
276 msg_pinfo("WARNING: BIOS region SMM protection is enabled!\n");
277 }
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000278
Stefan Taunerf9a8da52011-06-11 18:16:50 +0000279 new = old | 1;
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000280 if (new == old)
281 return 0;
282
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000283 rpci_write_byte(dev, bios_cntl, new);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000284
Stefan Reinauer86de2832006-03-31 11:26:55 +0000285 if (pci_read_byte(dev, bios_cntl) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000286 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000287 return -1;
288 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000289
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000290 return 0;
291}
292
Uwe Hermann372eeb52007-12-04 21:49:06 +0000293static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000294{
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000295 /*
296 * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and
297 * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and
298 * FB_DEC_EN2.
299 */
Carl-Daniel Hailfinger7f9922d2010-06-20 11:04:26 +0000300 buses_supported = CHIP_BUSTYPE_FWH;
Stefan Reinauereb366472006-09-06 15:48:48 +0000301 return enable_flash_ich(dev, name, 0x4e);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000302}
303
Uwe Hermann372eeb52007-12-04 21:49:06 +0000304static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000305{
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000306 uint32_t fwh_conf;
307 int i;
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000308 char *idsel = NULL;
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000309 int tmp;
310 int max_decode_fwh_idsel = 0;
311 int max_decode_fwh_decode = 0;
312 int contiguous = 1;
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000313
Carl-Daniel Hailfinger2b6dcb32010-07-08 10:13:37 +0000314 idsel = extract_programmer_param("fwh_idsel");
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000315 if (idsel && strlen(idsel)) {
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000316 uint64_t fwh_idsel_old;
317 uint64_t fwh_idsel;
318 errno = 0;
319 /* Base 16, nothing else makes sense. */
320 fwh_idsel = (uint64_t)strtoull(idsel, NULL, 16);
321 if (errno) {
322 msg_perr("Error: fwh_idsel= specified, but value could "
323 "not be converted.\n");
324 goto idsel_garbage_out;
325 }
326 if (fwh_idsel & 0xffff000000000000ULL) {
327 msg_perr("Error: fwh_idsel= specified, but value had "
328 "unusued bits set.\n");
329 goto idsel_garbage_out;
330 }
331 fwh_idsel_old = pci_read_long(dev, 0xd0);
332 fwh_idsel_old <<= 16;
333 fwh_idsel_old |= pci_read_word(dev, 0xd4);
334 msg_pdbg("\nSetting IDSEL from 0x%012" PRIx64 " to "
335 "0x%012" PRIx64 " for top 16 MB.", fwh_idsel_old,
336 fwh_idsel);
337 rpci_write_long(dev, 0xd0, (fwh_idsel >> 16) & 0xffffffff);
338 rpci_write_word(dev, 0xd4, fwh_idsel & 0xffff);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000339 /* FIXME: Decode settings are not changed. */
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000340 } else if (idsel) {
Carl-Daniel Hailfinger46fa0682011-07-25 22:44:09 +0000341 msg_perr("Error: fwh_idsel= specified, but no value given.\n");
342idsel_garbage_out:
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000343 free(idsel);
344 /* FIXME: Return failure here once internal_init() starts
345 * to care about the return value of the chipset enable.
346 */
347 exit(1);
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000348 }
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000349 free(idsel);
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000350
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000351 /* Ignore all legacy ranges below 1 MB.
352 * We currently only support flashing the chip which responds to
353 * IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations
354 * have to be adjusted.
355 */
356 /* FWH_SEL1 */
357 fwh_conf = pci_read_long(dev, 0xd0);
358 for (i = 7; i >= 0; i--) {
359 tmp = (fwh_conf >> (i * 4)) & 0xf;
Sean Nelson316a29f2010-05-07 20:09:04 +0000360 msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000361 (0x1ff8 + i) * 0x80000,
362 (0x1ff0 + i) * 0x80000,
363 tmp);
364 if ((tmp == 0) && contiguous) {
365 max_decode_fwh_idsel = (8 - i) * 0x80000;
366 } else {
367 contiguous = 0;
368 }
369 }
370 /* FWH_SEL2 */
371 fwh_conf = pci_read_word(dev, 0xd4);
372 for (i = 3; i >= 0; i--) {
373 tmp = (fwh_conf >> (i * 4)) & 0xf;
Sean Nelson316a29f2010-05-07 20:09:04 +0000374 msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000375 (0xff4 + i) * 0x100000,
376 (0xff0 + i) * 0x100000,
377 tmp);
378 if ((tmp == 0) && contiguous) {
379 max_decode_fwh_idsel = (8 - i) * 0x100000;
380 } else {
381 contiguous = 0;
382 }
383 }
384 contiguous = 1;
385 /* FWH_DEC_EN1 */
386 fwh_conf = pci_read_word(dev, 0xd8);
387 for (i = 7; i >= 0; i--) {
388 tmp = (fwh_conf >> (i + 0x8)) & 0x1;
Sean Nelson316a29f2010-05-07 20:09:04 +0000389 msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled",
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000390 (0x1ff8 + i) * 0x80000,
391 (0x1ff0 + i) * 0x80000,
392 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000393 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000394 max_decode_fwh_decode = (8 - i) * 0x80000;
395 } else {
396 contiguous = 0;
397 }
398 }
399 for (i = 3; i >= 0; i--) {
400 tmp = (fwh_conf >> i) & 0x1;
Sean Nelson316a29f2010-05-07 20:09:04 +0000401 msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled",
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000402 (0xff4 + i) * 0x100000,
403 (0xff0 + i) * 0x100000,
404 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000405 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000406 max_decode_fwh_decode = (8 - i) * 0x100000;
407 } else {
408 contiguous = 0;
409 }
410 }
411 max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode);
Sean Nelson316a29f2010-05-07 20:09:04 +0000412 msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000413
414 /* If we're called by enable_flash_ich_dc_spi, it will override
415 * buses_supported anyway.
416 */
417 buses_supported = CHIP_BUSTYPE_FWH;
Stefan Reinauereb366472006-09-06 15:48:48 +0000418 return enable_flash_ich(dev, name, 0xdc);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000419}
420
Adam Jurkowskie4984102009-12-21 15:30:46 +0000421static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
422{
423 uint16_t old, new;
424 int err;
425
426 if ((err = enable_flash_ich(dev, name, 0xd8)) != 0)
427 return err;
428
429 old = pci_read_byte(dev, 0xd9);
Sean Nelson316a29f2010-05-07 20:09:04 +0000430 msg_pdbg("BIOS Prefetch Enable: %sabled, ",
Adam Jurkowskie4984102009-12-21 15:30:46 +0000431 (old & 1) ? "en" : "dis");
432 new = old & ~1;
433
434 if (new != old)
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000435 rpci_write_byte(dev, 0xd9, new);
Adam Jurkowskie4984102009-12-21 15:30:46 +0000436
Carl-Daniel Hailfinger7f9922d2010-06-20 11:04:26 +0000437 buses_supported = CHIP_BUSTYPE_FWH;
Adam Jurkowskie4984102009-12-21 15:30:46 +0000438 return 0;
439}
440
441
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000442#define ICH_STRAP_RSVD 0x00
443#define ICH_STRAP_SPI 0x01
444#define ICH_STRAP_PCI 0x02
445#define ICH_STRAP_LPC 0x03
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000446
Uwe Hermann394131e2008-10-18 21:14:13 +0000447static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
448{
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000449 /* Do we really need no write enable? */
Michael Karchera4448d92010-07-22 18:04:15 +0000450 return via_init_spi(dev);
Joshua Roysf93b36a2010-07-01 17:45:54 +0000451}
452
Uwe Hermann394131e2008-10-18 21:14:13 +0000453static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
454 int ich_generation)
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000455{
Michael Karchera4448d92010-07-22 18:04:15 +0000456 int ret;
457 uint8_t bbs, buc;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000458 uint32_t tmp, gcs;
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000459 void *rcrb;
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000460 //TODO: These names are incorrect for EP80579. For that, the solution would look like the commented line
461 //static const char *straps_names[] = {"SPI", "reserved", "reserved", "LPC" };
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000462 static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" };
Uwe Hermann394131e2008-10-18 21:14:13 +0000463
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000464 /* Enable Flash Writes */
465 ret = enable_flash_ich_dc(dev, name);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000466
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000467 /* Get physical address of Root Complex Register Block */
468 tmp = pci_read_long(dev, 0xf0) & 0xffffc000;
Sean Nelson316a29f2010-05-07 20:09:04 +0000469 msg_pdbg("\nRoot Complex Register Block address = 0x%x\n", tmp);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000470
471 /* Map RCBA to virtual memory */
Stefan Reinauer0593f212009-01-26 01:10:48 +0000472 rcrb = physmap("ICH RCRB", tmp, 0x4000);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000473
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000474 gcs = mmio_readl(rcrb + 0x3410);
Sean Nelson316a29f2010-05-07 20:09:04 +0000475 msg_pdbg("GCS = 0x%x: ", gcs);
476 msg_pdbg("BIOS Interface Lock-Down: %sabled, ",
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000477 (gcs & 0x1) ? "en" : "dis");
478 bbs = (gcs >> 10) & 0x3;
Sean Nelson316a29f2010-05-07 20:09:04 +0000479 msg_pdbg("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000480
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000481 buc = mmio_readb(rcrb + 0x3414);
Sean Nelson316a29f2010-05-07 20:09:04 +0000482 msg_pdbg("Top Swap : %s\n",
Uwe Hermann394131e2008-10-18 21:14:13 +0000483 (buc & 1) ? "enabled (A16 inverted)" : "not enabled");
Stefan Reinauera9424d52008-06-27 16:28:34 +0000484
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000485 /* It seems the ICH7 does not support SPI and LPC chips at the same
486 * time. At least not with our current code. So we prevent searching
487 * on ICH7 when the southbridge is strapped to LPC
488 */
489
Michael Karchera4448d92010-07-22 18:04:15 +0000490 buses_supported = CHIP_BUSTYPE_FWH;
491 if (ich_generation == 7) {
492 if(bbs == ICH_STRAP_LPC) {
493 /* No further SPI initialization required */
494 return ret;
495 }
496 else
497 /* Disable LPC/FWH if strapped to PCI or SPI */
498 buses_supported = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000499 }
500
Michael Karchera4448d92010-07-22 18:04:15 +0000501 /* this adds CHIP_BUSTYPE_SPI */
502 if (ich_init_spi(dev, tmp, rcrb, ich_generation) != 0) {
503 if (!ret)
504 ret = ERROR_NONFATAL;
505 }
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000506
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000507 return ret;
508}
Stefan Reinauera9424d52008-06-27 16:28:34 +0000509
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000510static int enable_flash_ich7(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000511{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000512 return enable_flash_ich_dc_spi(dev, name, 7);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000513}
514
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000515static int enable_flash_ich8(struct pci_dev *dev, const char *name)
516{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000517 return enable_flash_ich_dc_spi(dev, name, 8);
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000518}
519
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000520static int enable_flash_ich9(struct pci_dev *dev, const char *name)
521{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000522 return enable_flash_ich_dc_spi(dev, name, 9);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000523}
524
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000525static int enable_flash_ich10(struct pci_dev *dev, const char *name)
526{
527 return enable_flash_ich_dc_spi(dev, name, 10);
528}
529
Michael Karcher89bed6d2010-06-13 10:16:12 +0000530static int via_no_byte_merge(struct pci_dev *dev, const char *name)
531{
532 uint8_t val;
533
534 val = pci_read_byte(dev, 0x71);
535 if (val & 0x40)
536 {
537 msg_pdbg("Disabling byte merging\n");
538 val &= ~0x40;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000539 rpci_write_byte(dev, 0x71, val);
Michael Karcher89bed6d2010-06-13 10:16:12 +0000540 }
541 return NOT_DONE_YET; /* need to find south bridge, too */
542}
543
Uwe Hermann372eeb52007-12-04 21:49:06 +0000544static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000545{
Ollie Lho184a4042005-11-26 21:55:36 +0000546 uint8_t val;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000547
Uwe Hermann394131e2008-10-18 21:14:13 +0000548 /* enable ROM decode range (1MB) FFC00000 - FFFFFFFF */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000549 rpci_write_byte(dev, 0x41, 0x7f);
Bari Ari9477c4e2008-04-29 13:46:38 +0000550
Uwe Hermannffec5f32007-08-23 16:08:21 +0000551 /* ROM write enable */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000552 val = pci_read_byte(dev, 0x40);
553 val |= 0x10;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000554 rpci_write_byte(dev, 0x40, val);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000555
556 if (pci_read_byte(dev, 0x40) != val) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000557 msg_pinfo("\nWARNING: Failed to enable flash write on \"%s\"\n",
Uwe Hermanna7e05482007-05-09 10:17:44 +0000558 name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000559 return -1;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000560 }
Luc Verhaegen6382b442007-03-02 22:16:38 +0000561
Luc Verhaegen73d21192009-12-23 00:54:26 +0000562 if (dev->device_id == 0x3227) { /* VT8237R */
563 /* All memory cycles, not just ROM ones, go to LPC. */
564 val = pci_read_byte(dev, 0x59);
565 val &= ~0x80;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000566 rpci_write_byte(dev, 0x59, val);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000567 }
568
Uwe Hermanna7e05482007-05-09 10:17:44 +0000569 return 0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000570}
571
Uwe Hermann372eeb52007-12-04 21:49:06 +0000572static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000573{
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000574 uint8_t reg8;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000575
Uwe Hermann394131e2008-10-18 21:14:13 +0000576#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
577#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000578#define CS5530_RESET_CONTROL_REG 0x44 /* F0 index 0x44 */
579#define CS5530_USB_SHADOW_REG 0x43 /* F0 index 0x43 */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000580
Uwe Hermann394131e2008-10-18 21:14:13 +0000581#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
582#define ROM_WRITE_ENABLE (1 << 1)
583#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
584#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000585#define CS5530_ISA_MASTER (1 << 7)
586#define CS5530_ENABLE_SA2320 (1 << 2)
587#define CS5530_ENABLE_SA20 (1 << 6)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000588
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000589 buses_supported = CHIP_BUSTYPE_PARALLEL;
Stefan Taunerc0aaf952011-05-19 02:58:17 +0000590 /* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and
591 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB.
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000592 * FIXME: Should we really touch the low mapping below 1 MB? Flashrom
593 * ignores that region completely.
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000594 * Make the configured ROM areas writable.
595 */
596 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
597 reg8 |= LOWER_ROM_ADDRESS_RANGE;
598 reg8 |= UPPER_ROM_ADDRESS_RANGE;
599 reg8 |= ROM_WRITE_ENABLE;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000600 rpci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000601
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000602 /* Set positive decode on ROM. */
603 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
604 reg8 |= BIOS_ROM_POSITIVE_DECODE;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000605 rpci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000606
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000607 reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG);
608 if (reg8 & CS5530_ISA_MASTER) {
609 /* We have A0-A23 available. */
610 max_rom_decode.parallel = 16 * 1024 * 1024;
611 } else {
612 reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG);
613 if (reg8 & CS5530_ENABLE_SA2320) {
614 /* We have A0-19, A20-A23 available. */
615 max_rom_decode.parallel = 16 * 1024 * 1024;
616 } else if (reg8 & CS5530_ENABLE_SA20) {
617 /* We have A0-19, A20 available. */
618 max_rom_decode.parallel = 2 * 1024 * 1024;
619 } else {
620 /* A20 and above are not active. */
621 max_rom_decode.parallel = 1024 * 1024;
622 }
623 }
624
Ollie Lhocbbf1252004-03-17 22:22:08 +0000625 return 0;
626}
627
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000628/*
Mart Raudseppe1344da2008-02-08 10:10:57 +0000629 * Geode systems write protect the BIOS via RCONFs (cache settings similar
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000630 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
Mart Raudseppe1344da2008-02-08 10:10:57 +0000631 *
632 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
633 * To enable write to NOR Boot flash for the benefit of systems that have such
634 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
Mart Raudseppe1344da2008-02-08 10:10:57 +0000635 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000636static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
Lane Brooksd54958a2007-11-13 16:45:22 +0000637{
Uwe Hermann394131e2008-10-18 21:14:13 +0000638#define MSR_RCONF_DEFAULT 0x1808
639#define MSR_NORF_CTL 0x51400018
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000640
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000641 msr_t msr;
Lane Brooksd54958a2007-11-13 16:45:22 +0000642
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000643 /* Geode only has a single core */
644 if (setup_cpu_msr(0))
Lane Brooksd54958a2007-11-13 16:45:22 +0000645 return -1;
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000646
647 msr = rdmsr(MSR_RCONF_DEFAULT);
648 if ((msr.hi >> 24) != 0x22) {
649 msr.hi &= 0xfbffffff;
650 wrmsr(MSR_RCONF_DEFAULT, msr);
Lane Brooksd54958a2007-11-13 16:45:22 +0000651 }
Mart Raudseppe1344da2008-02-08 10:10:57 +0000652
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000653 msr = rdmsr(MSR_NORF_CTL);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000654 /* Raise WE_CS3 bit. */
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000655 msr.lo |= 0x08;
656 wrmsr(MSR_NORF_CTL, msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000657
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000658 cleanup_cpu_msr();
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000659
Uwe Hermann394131e2008-10-18 21:14:13 +0000660#undef MSR_RCONF_DEFAULT
661#undef MSR_NORF_CTL
Lane Brooksd54958a2007-11-13 16:45:22 +0000662 return 0;
663}
664
Uwe Hermann372eeb52007-12-04 21:49:06 +0000665static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000666{
Ollie Lho184a4042005-11-26 21:55:36 +0000667 uint8_t new;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000668
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000669 rpci_write_byte(dev, 0x52, 0xee);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000670
671 new = pci_read_byte(dev, 0x52);
672
673 if (new != 0xee) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000674 msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000675 return -1;
676 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000677
Ollie Lhocbbf1252004-03-17 22:22:08 +0000678 return 0;
679}
680
Uwe Hermann190f8492008-10-25 18:03:50 +0000681/* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000682static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000683{
Ollie Lho184a4042005-11-26 21:55:36 +0000684 uint8_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000685
Uwe Hermann372eeb52007-12-04 21:49:06 +0000686 /* Enable decoding at 0xffb00000 to 0xffffffff. */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000687 old = pci_read_byte(dev, 0x43);
Ollie Lhod11f3612004-12-07 17:19:04 +0000688 new = old | 0xC0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000689 if (new != old) {
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000690 rpci_write_byte(dev, 0x43, new);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000691 if (pci_read_byte(dev, 0x43) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000692 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000693 }
694 }
695
Uwe Hermann190f8492008-10-25 18:03:50 +0000696 /* Enable 'ROM write' bit. */
Ollie Lho761bf1b2004-03-20 16:46:10 +0000697 old = pci_read_byte(dev, 0x40);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000698 new = old | 0x01;
699 if (new == old)
700 return 0;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000701 rpci_write_byte(dev, 0x40, new);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000702
703 if (pci_read_byte(dev, 0x40) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000704 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000705 return -1;
706 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000707
Ollie Lhocbbf1252004-03-17 22:22:08 +0000708 return 0;
709}
710
Marc Jones3af487d2008-10-15 17:50:29 +0000711static int enable_flash_sb600(struct pci_dev *dev, const char *name)
712{
Michael Karcherb05b9e12010-07-22 18:04:19 +0000713 uint32_t prot;
Marc Jones3af487d2008-10-15 17:50:29 +0000714 uint8_t reg;
Michael Karcherb05b9e12010-07-22 18:04:19 +0000715 int ret;
Marc Jones3af487d2008-10-15 17:50:29 +0000716
Jason Wanga3f04be2008-11-28 21:36:51 +0000717 /* Clear ROM protect 0-3. */
718 for (reg = 0x50; reg < 0x60; reg += 4) {
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000719 prot = pci_read_long(dev, reg);
720 /* No protection flags for this region?*/
721 if ((prot & 0x3) == 0)
722 continue;
Mathias Krause9fbdc032011-01-01 10:54:09 +0000723 msg_pinfo("SB600 %s%sprotected from 0x%08x to 0x%08x\n",
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000724 (prot & 0x1) ? "write " : "",
725 (prot & 0x2) ? "read " : "",
Mathias Krause9fbdc032011-01-01 10:54:09 +0000726 (prot & 0xfffff800),
727 (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000728 prot &= 0xfffffffc;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000729 rpci_write_byte(dev, reg, prot);
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000730 prot = pci_read_long(dev, reg);
Carl-Daniel Hailfinger9bb88ac2009-05-06 13:51:44 +0000731 if (prot & 0x3)
Mathias Krause9fbdc032011-01-01 10:54:09 +0000732 msg_perr("SB600 %s%sunprotect failed from 0x%08x to 0x%08x\n",
Carl-Daniel Hailfinger9bb88ac2009-05-06 13:51:44 +0000733 (prot & 0x1) ? "write " : "",
734 (prot & 0x2) ? "read " : "",
Mathias Krause9fbdc032011-01-01 10:54:09 +0000735 (prot & 0xfffff800),
736 (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
Jason Wanga3f04be2008-11-28 21:36:51 +0000737 }
738
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000739 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH;
Michael Karcherb05b9e12010-07-22 18:04:19 +0000740
741 ret = sb600_probe_spi(dev);
Jason Wanga3f04be2008-11-28 21:36:51 +0000742
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000743 /* Read ROM strap override register. */
744 OUTB(0x8f, 0xcd6);
745 reg = INB(0xcd7);
746 reg &= 0x0e;
Sean Nelson316a29f2010-05-07 20:09:04 +0000747 msg_pdbg("ROM strap override is %sactive", (reg & 0x02) ? "" : "not ");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000748 if (reg & 0x02) {
749 switch ((reg & 0x0c) >> 2) {
750 case 0x00:
Sean Nelson316a29f2010-05-07 20:09:04 +0000751 msg_pdbg(": LPC");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000752 break;
753 case 0x01:
Sean Nelson316a29f2010-05-07 20:09:04 +0000754 msg_pdbg(": PCI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000755 break;
756 case 0x02:
Sean Nelson316a29f2010-05-07 20:09:04 +0000757 msg_pdbg(": FWH");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000758 break;
759 case 0x03:
Sean Nelson316a29f2010-05-07 20:09:04 +0000760 msg_pdbg(": SPI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000761 break;
762 }
763 }
Sean Nelson316a29f2010-05-07 20:09:04 +0000764 msg_pdbg("\n");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000765
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000766 /* Force enable SPI ROM in SB600 PM register.
767 * If we enable SPI ROM here, we have to disable it after we leave.
Zheng Bao284a6002009-05-04 22:33:50 +0000768 * But how can we know which ROM we are going to handle? So we have
769 * to trade off. We only access LPC ROM if we boot via LPC ROM. And
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000770 * only SPI ROM if we boot via SPI ROM. If you want to access SPI on
771 * boards with LPC straps, you have to use the code below.
Zheng Bao284a6002009-05-04 22:33:50 +0000772 */
773 /*
Jason Wanga3f04be2008-11-28 21:36:51 +0000774 OUTB(0x8f, 0xcd6);
775 OUTB(0x0e, 0xcd7);
Zheng Bao284a6002009-05-04 22:33:50 +0000776 */
Marc Jones3af487d2008-10-15 17:50:29 +0000777
Michael Karcherb05b9e12010-07-22 18:04:19 +0000778 return ret;
Marc Jones3af487d2008-10-15 17:50:29 +0000779}
780
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000781static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name)
782{
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000783 uint8_t tmp;
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000784
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000785 rpci_write_byte(dev, 0x92, 0);
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000786
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000787 tmp = pci_read_byte(dev, 0x6d);
788 tmp |= 0x01;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000789 rpci_write_byte(dev, 0x6d, tmp);
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000790
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000791 return 0;
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000792}
793
Uwe Hermann372eeb52007-12-04 21:49:06 +0000794static int enable_flash_ck804(struct pci_dev *dev, const char *name)
Yinghai Lu952dfce2005-07-06 17:13:46 +0000795{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000796 uint8_t old, new;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000797
Uwe Hermanna7e05482007-05-09 10:17:44 +0000798 old = pci_read_byte(dev, 0x88);
799 new = old | 0xc0;
800 if (new != old) {
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000801 rpci_write_byte(dev, 0x88, new);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000802 if (pci_read_byte(dev, 0x88) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000803 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000804 }
805 }
Yinghai Lu952dfce2005-07-06 17:13:46 +0000806
Uwe Hermanna7e05482007-05-09 10:17:44 +0000807 old = pci_read_byte(dev, 0x6d);
808 new = old | 0x01;
809 if (new == old)
810 return 0;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000811 rpci_write_byte(dev, 0x6d, new);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000812
813 if (pci_read_byte(dev, 0x6d) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000814 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000815 return -1;
816 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000817
Uwe Hermanna7e05482007-05-09 10:17:44 +0000818 return 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000819}
820
Joshua Roys85835d82010-09-15 14:47:56 +0000821static int enable_flash_osb4(struct pci_dev *dev, const char *name)
822{
823 uint8_t tmp;
824
825 buses_supported = CHIP_BUSTYPE_PARALLEL;
826
827 tmp = INB(0xc06);
828 tmp |= 0x1;
829 OUTB(tmp, 0xc06);
830
831 tmp = INB(0xc6f);
832 tmp |= 0x40;
833 OUTB(tmp, 0xc6f);
834
835 return 0;
836}
837
Uwe Hermann372eeb52007-12-04 21:49:06 +0000838/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
839static int enable_flash_sb400(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000840{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000841 uint8_t tmp;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000842 struct pci_dev *smbusdev;
843
Uwe Hermann372eeb52007-12-04 21:49:06 +0000844 /* Look for the SMBus device. */
Carl-Daniel Hailfingerf6e3efb2009-05-06 00:35:31 +0000845 smbusdev = pci_dev_find(0x1002, 0x4372);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000846
Uwe Hermanna7e05482007-05-09 10:17:44 +0000847 if (!smbusdev) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000848 msg_perr("ERROR: SMBus device not found. Aborting.\n");
Stefan Reinauer86de2832006-03-31 11:26:55 +0000849 exit(1);
850 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000851
Uwe Hermann372eeb52007-12-04 21:49:06 +0000852 /* Enable some SMBus stuff. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000853 tmp = pci_read_byte(smbusdev, 0x79);
854 tmp |= 0x01;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000855 rpci_write_byte(smbusdev, 0x79, tmp);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000856
Uwe Hermann372eeb52007-12-04 21:49:06 +0000857 /* Change southbridge. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000858 tmp = pci_read_byte(dev, 0x48);
859 tmp |= 0x21;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000860 rpci_write_byte(dev, 0x48, tmp);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000861
Uwe Hermann372eeb52007-12-04 21:49:06 +0000862 /* Now become a bit silly. */
Andriy Gapon65c1b862008-05-22 13:22:45 +0000863 tmp = INB(0xc6f);
864 OUTB(tmp, 0xeb);
865 OUTB(tmp, 0xeb);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000866 tmp |= 0x40;
Andriy Gapon65c1b862008-05-22 13:22:45 +0000867 OUTB(tmp, 0xc6f);
868 OUTB(tmp, 0xeb);
869 OUTB(tmp, 0xeb);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000870
871 return 0;
872}
873
Uwe Hermann372eeb52007-12-04 21:49:06 +0000874static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
Yinghai Luca782972007-01-22 20:21:17 +0000875{
Michael Karcher4e2fb0e2010-01-12 23:29:26 +0000876 uint8_t old, new, val;
877 uint16_t wordval;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000878
Uwe Hermann372eeb52007-12-04 21:49:06 +0000879 /* Set the 0-16 MB enable bits. */
Michael Karcher4e2fb0e2010-01-12 23:29:26 +0000880 val = pci_read_byte(dev, 0x88);
881 val |= 0xff; /* 256K */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000882 rpci_write_byte(dev, 0x88, val);
Michael Karcher4e2fb0e2010-01-12 23:29:26 +0000883 val = pci_read_byte(dev, 0x8c);
884 val |= 0xff; /* 1M */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000885 rpci_write_byte(dev, 0x8c, val);
Michael Karcher4e2fb0e2010-01-12 23:29:26 +0000886 wordval = pci_read_word(dev, 0x90);
887 wordval |= 0x7fff; /* 16M */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000888 rpci_write_word(dev, 0x90, wordval);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000889
Uwe Hermanna7e05482007-05-09 10:17:44 +0000890 old = pci_read_byte(dev, 0x6d);
891 new = old | 0x01;
892 if (new == old)
893 return 0;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000894 rpci_write_byte(dev, 0x6d, new);
Yinghai Luca782972007-01-22 20:21:17 +0000895
Uwe Hermanna7e05482007-05-09 10:17:44 +0000896 if (pci_read_byte(dev, 0x6d) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000897 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000898 return -1;
899 }
Yinghai Luca782972007-01-22 20:21:17 +0000900
901 return 0;
Yinghai Luca782972007-01-22 20:21:17 +0000902}
903
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000904/*
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000905 * The MCP6x/MCP7x code is based on cleanroom reverse engineering.
906 * It is assumed that LPC chips need the MCP55 code and SPI chips need the
907 * code provided in enable_flash_mcp6x_7x_common.
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000908 */
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000909static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000910{
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000911 int ret = 0;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000912 int want_spi = 0;
Michael Karchercfa674f2010-02-25 11:38:23 +0000913 uint8_t val;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000914
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000915 msg_pinfo("This chipset is not really supported yet. Guesswork...\n");
916
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000917 /* dev is the ISA bridge. No idea what the stuff below does. */
Michael Karchercfa674f2010-02-25 11:38:23 +0000918 val = pci_read_byte(dev, 0x8a);
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000919 msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 "
Michael Karchercfa674f2010-02-25 11:38:23 +0000920 "is %i\n", val, (val >> 6) & 0x1, (val >> 5) & 0x1);
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000921
Michael Karchercfa674f2010-02-25 11:38:23 +0000922 switch ((val >> 5) & 0x3) {
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000923 case 0x0:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000924 ret = enable_flash_mcp55(dev, name);
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000925 buses_supported = CHIP_BUSTYPE_LPC;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000926 msg_pdbg("Flash bus type is LPC\n");
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000927 break;
928 case 0x2:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000929 want_spi = 1;
930 /* SPI is added in mcp6x_spi_init if it works.
931 * Do we really want to disable LPC in this case?
932 */
933 buses_supported = CHIP_BUSTYPE_NONE;
934 msg_pdbg("Flash bus type is SPI\n");
Stefan Tauner25b5a592011-07-13 20:48:54 +0000935 msg_pinfo("SPI on this chipset is WIP. Please report any "
936 "success or failure by mailing us the verbose "
937 "output to flashrom@flashrom.org, thanks!\n");
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000938 break;
939 default:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000940 /* Should not happen. */
941 buses_supported = CHIP_BUSTYPE_NONE;
942 msg_pdbg("Flash bus type is unknown (none)\n");
943 msg_pinfo("Something went wrong with bus type detection.\n");
944 goto out_msg;
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000945 break;
946 }
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000947
948 /* Force enable SPI and disable LPC? Not a good idea. */
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000949#if 0
Michael Karchercfa674f2010-02-25 11:38:23 +0000950 val |= (1 << 6);
951 val &= ~(1 << 5);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000952 rpci_write_byte(dev, 0x8a, val);
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000953#endif
954
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000955 if (mcp6x_spi_init(want_spi)) {
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000956 ret = 1;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000957 }
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000958out_msg:
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000959 msg_pinfo("Please send the output of \"flashrom -V\" to "
Paul Menzelab6328f2010-10-08 11:03:02 +0000960 "flashrom@flashrom.org with\n"
961 "your board name: flashrom -V as the subject to help us "
962 "finish support for your\n"
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000963 "chipset. Thanks.\n");
964
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000965 return ret;
966}
967
Uwe Hermann372eeb52007-12-04 21:49:06 +0000968static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000969{
Michael Karchercfa674f2010-02-25 11:38:23 +0000970 uint8_t val;
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000971
Uwe Hermanne823ee02007-06-05 15:02:18 +0000972 /* Set the 4MB enable bit. */
Michael Karchercfa674f2010-02-25 11:38:23 +0000973 val = pci_read_byte(dev, 0x41);
974 val |= 0x0e;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000975 rpci_write_byte(dev, 0x41, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000976
Michael Karchercfa674f2010-02-25 11:38:23 +0000977 val = pci_read_byte(dev, 0x43);
978 val |= (1 << 4);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000979 rpci_write_byte(dev, 0x43, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000980
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000981 return 0;
982}
983
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000984/*
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000985 * Usually on the x86 architectures (and on other PC-like platforms like some
986 * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
987 * Elan SC520 only a small piece of the system flash is mapped there, but the
988 * complete flash is mapped somewhere below 1G. The position can be determined
989 * by the BOOTCS PAR register.
990 */
991static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
992{
993 int i, bootcs_found = 0;
994 uint32_t parx = 0;
995 void *mmcr;
996
997 /* 1. Map MMCR */
Stefan Reinauer0593f212009-01-26 01:10:48 +0000998 mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000999
1000 /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for
1001 * BOOTCS region (PARx[31:29] = 100b)e
1002 */
1003 for (i = 0x88; i <= 0xc4; i += 4) {
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +00001004 parx = mmio_readl(mmcr + i);
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001005 if ((parx >> 29) == 4) {
1006 bootcs_found = 1;
1007 break; /* BOOTCS found */
1008 }
1009 }
1010
1011 /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0]
1012 * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0]
1013 */
1014 if (bootcs_found) {
1015 if (parx & (1 << 25)) {
1016 parx &= (1 << 14) - 1; /* Mask [13:0] */
1017 flashbase = parx << 16;
1018 } else {
1019 parx &= (1 << 18) - 1; /* Mask [17:0] */
1020 flashbase = parx << 12;
1021 }
1022 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +00001023 msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n");
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001024 }
1025
1026 /* 4. Clean up */
Carl-Daniel Hailfingerbe726812009-08-09 12:44:08 +00001027 physunmap(mmcr, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001028 return 0;
1029}
1030
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001031#endif
1032
Idwer Vollering326a0602011-06-18 18:45:41 +00001033/* Please keep this list numerically sorted by vendor/device ID. */
Uwe Hermann05fab752009-05-16 23:42:17 +00001034const struct penable chipset_enables[] = {
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001035#if defined(__i386__) || defined(__x86_64__)
Idwer Vollering326a0602011-06-18 18:45:41 +00001036 {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400},
Idwer Vollering570dcc72011-06-18 18:45:50 +00001037 {0x1002, 0x438d, OK, "AMD", "SB600", enable_flash_sb600},
Stefan Tauner77000512011-04-02 11:47:21 +00001038 {0x1002, 0x439d, OK, "AMD", "SB700/SB710/SB750/SB850", enable_flash_sb600},
Uwe Hermann4179d292009-05-08 17:50:51 +00001039 {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100},
Idwer Vollering326a0602011-06-18 18:45:41 +00001040 {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536},
1041 {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536},
1042 {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520},
1043 {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111},
1044 {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111},
1045 {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501},
1046 {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496},
1047 {0x1039, 0x0530, NT, "SiS", "530", enable_flash_sis530},
1048 {0x1039, 0x0540, NT, "SiS", "540", enable_flash_sis540},
1049 {0x1039, 0x0620, NT, "SiS", "620", enable_flash_sis530},
1050 {0x1039, 0x0630, NT, "SiS", "630", enable_flash_sis540},
1051 {0x1039, 0x0635, NT, "SiS", "635", enable_flash_sis540},
1052 {0x1039, 0x0640, NT, "SiS", "640", enable_flash_sis540},
1053 {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis540},
Stefan Tauner716e0982011-07-25 20:38:52 +00001054 {0x1039, 0x0646, OK, "SiS", "645DX", enable_flash_sis540},
Idwer Vollering326a0602011-06-18 18:45:41 +00001055 {0x1039, 0x0648, NT, "SiS", "648", enable_flash_sis540},
1056 {0x1039, 0x0650, NT, "SiS", "650", enable_flash_sis540},
Stefan Tauner716e0982011-07-25 20:38:52 +00001057 {0x1039, 0x0651, OK, "SiS", "651", enable_flash_sis540},
Idwer Vollering326a0602011-06-18 18:45:41 +00001058 {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis540},
1059 {0x1039, 0x0661, OK, "SiS", "661", enable_flash_sis540},
1060 {0x1039, 0x0730, NT, "SiS", "730", enable_flash_sis540},
1061 {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis540},
1062 {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis540},
1063 {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis540},
1064 {0x1039, 0x0741, OK, "SiS", "741", enable_flash_sis540},
1065 {0x1039, 0x0745, OK, "SiS", "745", enable_flash_sis540},
1066 {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540},
1067 {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540},
1068 {0x1039, 0x0755, NT, "SiS", "755", enable_flash_sis540},
1069 {0x1039, 0x5511, NT, "SiS", "5511", enable_flash_sis5511},
1070 {0x1039, 0x5571, NT, "SiS", "5571", enable_flash_sis530},
1071 {0x1039, 0x5591, NT, "SiS", "5591/5592", enable_flash_sis530},
1072 {0x1039, 0x5596, NT, "SiS", "5596", enable_flash_sis5511},
1073 {0x1039, 0x5597, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530},
1074 {0x1039, 0x5600, NT, "SiS", "600", enable_flash_sis530},
1075 {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530},
Idwer Vollering570dcc72011-06-18 18:45:50 +00001076 {0x10b9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533},
Stefan Taunerd06d9412011-06-12 19:47:55 +00001077 {0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2},
Uwe Hermannb0039912009-05-07 13:24:49 +00001078 {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */
1079 {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */
Stefan Taunerd06d9412011-06-12 19:47:55 +00001080 {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2},
1081 {0x10de, 0x00e0, OK, "NVIDIA", "NForce3", enable_flash_nvidia_nforce2},
Uwe Hermanneac10162008-03-13 18:52:51 +00001082 /* Slave, should not be here, to fix known bug for A01. */
Uwe Hermannb0039912009-05-07 13:24:49 +00001083 {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804},
1084 {0x10de, 0x0260, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1085 {0x10de, 0x0261, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1086 {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1087 {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1088 {0x10de, 0x0360, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/
Carl-Daniel Hailfinger33d7b6a2010-05-22 07:27:16 +00001089 /* 10de:0361 is present in Tyan S2915 OEM systems, but not connected to
1090 * the flash chip. Instead, 10de:0364 is connected to the flash chip.
1091 * Until we have PCI device class matching or some fallback mechanism,
1092 * this is needed to get flashrom working on Tyan S2915 and maybe other
1093 * dual-MCP55 boards.
1094 */
1095#if 0
1096 {0x10de, 0x0361, NT, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1097#endif
Uwe Hermannb0039912009-05-07 13:24:49 +00001098 {0x10de, 0x0362, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1099 {0x10de, 0x0363, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1100 {0x10de, 0x0364, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1101 {0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1102 {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1103 {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001104 {0x10de, 0x03e0, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1105 {0x10de, 0x03e1, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1106 {0x10de, 0x03e2, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1107 {0x10de, 0x03e3, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1108 {0x10de, 0x0440, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1109 {0x10de, 0x0441, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1110 {0x10de, 0x0442, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1111 {0x10de, 0x0443, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1112 {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp6x_7x},
1113 {0x10de, 0x075c, NT, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x},
1114 {0x10de, 0x075d, NT, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x},
1115 {0x10de, 0x07d7, NT, "NVIDIA", "MCP73", enable_flash_mcp6x_7x},
1116 {0x10de, 0x0aac, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1117 {0x10de, 0x0aad, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1118 {0x10de, 0x0aae, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1119 {0x10de, 0x0aaf, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
Michael Karcher89bed6d2010-06-13 10:16:12 +00001120 /* VIA northbridges */
1121 {0x1106, 0x0585, NT, "VIA", "VT82C585VPX", via_no_byte_merge},
1122 {0x1106, 0x0595, NT, "VIA", "VT82C595", via_no_byte_merge},
1123 {0x1106, 0x0597, NT, "VIA", "VT82C597", via_no_byte_merge},
Michael Karcher89bed6d2010-06-13 10:16:12 +00001124 {0x1106, 0x0601, NT, "VIA", "VT8601/VT8601A", via_no_byte_merge},
Idwer Vollering326a0602011-06-18 18:45:41 +00001125 {0x1106, 0x0691, NT, "VIA", "VT82C69x", via_no_byte_merge}, /* 691, 693a, 694t, 694x checked */
Michael Karcher89bed6d2010-06-13 10:16:12 +00001126 {0x1106, 0x8601, NT, "VIA", "VT8601T", via_no_byte_merge},
1127 /* VIA southbridges */
Idwer Vollering326a0602011-06-18 18:45:41 +00001128 {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111},
1129 {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111},
1130 {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111},
Mateusz Murawskie6abef02009-06-18 12:42:46 +00001131 {0x1106, 0x3074, NT, "VIA", "VT8233", enable_flash_vt823x},
Raúl Sorianocd8404d2009-12-23 21:29:18 +00001132 {0x1106, 0x3147, OK, "VIA", "VT8233A", enable_flash_vt823x},
Uwe Hermann4179d292009-05-08 17:50:51 +00001133 {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x},
1134 {0x1106, 0x3227, OK, "VIA", "VT8237", enable_flash_vt823x},
1135 {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x},
1136 {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi},
Idwer Vollering326a0602011-06-18 18:45:41 +00001137 {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x},
1138 {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x},
Idwer Vollering570dcc72011-06-18 18:45:50 +00001139 {0x1106, 0x8353, OK, "VIA", "VX800/VX820", enable_flash_vt8237s_spi},
1140 {0x1106, 0x8409, OK, "VIA", "VX855/VX875", enable_flash_vt823x},
Idwer Vollering326a0602011-06-18 18:45:41 +00001141 {0x1166, 0x0200, OK, "Broadcom", "OSB4", enable_flash_osb4},
1142 {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000},
1143 {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4},
1144 {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4},
Stefan Tauner2cf2da62011-06-18 18:45:56 +00001145 {0x8086, 0x1c44, NT, "Intel", "Z68", enable_flash_ich10},
1146 {0x8086, 0x1c46, NT, "Intel", "P67", enable_flash_ich10},
1147 {0x8086, 0x1c47, NT, "Intel", "UM67", enable_flash_ich10},
1148 {0x8086, 0x1c49, NT, "Intel", "HM65", enable_flash_ich10},
1149 {0x8086, 0x1c4a, NT, "Intel", "H67", enable_flash_ich10},
1150 {0x8086, 0x1c4b, NT, "Intel", "HM67", enable_flash_ich10},
1151 {0x8086, 0x1c4c, NT, "Intel", "Q65", enable_flash_ich10},
1152 {0x8086, 0x1c4d, NT, "Intel", "QS67", enable_flash_ich10},
1153 {0x8086, 0x1c4e, NT, "Intel", "Q67", enable_flash_ich10},
1154 {0x8086, 0x1c4f, NT, "Intel", "QM67", enable_flash_ich10},
1155 {0x8086, 0x1c50, NT, "Intel", "B65", enable_flash_ich10},
1156 {0x8086, 0x1c52, NT, "Intel", "C202", enable_flash_ich10},
1157 {0x8086, 0x1c54, NT, "Intel", "C204", enable_flash_ich10},
1158 {0x8086, 0x1c56, NT, "Intel", "C206", enable_flash_ich10},
1159 {0x8086, 0x1c5c, NT, "Intel", "H61", enable_flash_ich10},
Idwer Vollering326a0602011-06-18 18:45:41 +00001160 {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e},
1161 {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e},
1162 {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e},
1163 {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich_4e},
Idwer Vollering570dcc72011-06-18 18:45:50 +00001164 {0x8086, 0x2450, NT, "Intel", "C-ICH", enable_flash_ich_4e},
Idwer Vollering326a0602011-06-18 18:45:41 +00001165 {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich_4e},
1166 {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich_4e},
1167 {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich_4e},
1168 {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich_4e},
1169 {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich_4e},
1170 {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich_4e},
1171 {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich_dc},
1172 {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich_dc},
Idwer Vollering570dcc72011-06-18 18:45:50 +00001173 {0x8086, 0x2642, NT, "Intel", "ICH6W/ICH6RW", enable_flash_ich_dc},
Idwer Vollering326a0602011-06-18 18:45:41 +00001174 {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich_dc},
1175 {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7},
1176 {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7},
1177 {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7},
1178 {0x8086, 0x27bc, OK, "Intel", "NM10", enable_flash_ich7},
1179 {0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7},
1180 {0x8086, 0x2810, OK, "Intel", "ICH8/ICH8R", enable_flash_ich8},
1181 {0x8086, 0x2811, OK, "Intel", "ICH8M-E", enable_flash_ich8},
1182 {0x8086, 0x2812, OK, "Intel", "ICH8DH", enable_flash_ich8},
1183 {0x8086, 0x2814, OK, "Intel", "ICH8DO", enable_flash_ich8},
1184 {0x8086, 0x2815, OK, "Intel", "ICH8M", enable_flash_ich8},
1185 {0x8086, 0x2910, OK, "Intel", "ICH9 Engineering Sample", enable_flash_ich9},
1186 {0x8086, 0x2912, OK, "Intel", "ICH9DH", enable_flash_ich9},
1187 {0x8086, 0x2914, OK, "Intel", "ICH9DO", enable_flash_ich9},
1188 {0x8086, 0x2916, OK, "Intel", "ICH9R", enable_flash_ich9},
1189 {0x8086, 0x2917, OK, "Intel", "ICH9M-E", enable_flash_ich9},
1190 {0x8086, 0x2918, OK, "Intel", "ICH9", enable_flash_ich9},
1191 {0x8086, 0x2919, OK, "Intel", "ICH9M", enable_flash_ich9},
Idwer Vollering570dcc72011-06-18 18:45:50 +00001192 {0x8086, 0x3a10, NT, "Intel", "ICH10R Engineering Sample", enable_flash_ich10},
Idwer Vollering326a0602011-06-18 18:45:41 +00001193 {0x8086, 0x3a14, OK, "Intel", "ICH10DO", enable_flash_ich10},
1194 {0x8086, 0x3a16, OK, "Intel", "ICH10R", enable_flash_ich10},
1195 {0x8086, 0x3a18, OK, "Intel", "ICH10", enable_flash_ich10},
1196 {0x8086, 0x3a1a, OK, "Intel", "ICH10D", enable_flash_ich10},
Idwer Vollering570dcc72011-06-18 18:45:50 +00001197 {0x8086, 0x3a1e, NT, "Intel", "ICH10 Engineering Sample", enable_flash_ich10},
Idwer Vollering326a0602011-06-18 18:45:41 +00001198 {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_ich10},
1199 {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_ich10},
1200 {0x8086, 0x3b02, NT, "Intel", "P55", enable_flash_ich10},
1201 {0x8086, 0x3b03, NT, "Intel", "PM55", enable_flash_ich10},
1202 {0x8086, 0x3b06, NT, "Intel", "H55", enable_flash_ich10},
1203 {0x8086, 0x3b07, OK, "Intel", "QM57", enable_flash_ich10},
1204 {0x8086, 0x3b08, NT, "Intel", "H57", enable_flash_ich10},
1205 {0x8086, 0x3b09, NT, "Intel", "HM55", enable_flash_ich10},
1206 {0x8086, 0x3b0a, NT, "Intel", "Q57", enable_flash_ich10},
1207 {0x8086, 0x3b0b, NT, "Intel", "HM57", enable_flash_ich10},
1208 {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_ich10},
1209 {0x8086, 0x3b0e, NT, "Intel", "B55", enable_flash_ich10},
1210 {0x8086, 0x3b0f, OK, "Intel", "QS57", enable_flash_ich10},
1211 {0x8086, 0x3b12, NT, "Intel", "3400", enable_flash_ich10},
1212 {0x8086, 0x3b14, NT, "Intel", "3420", enable_flash_ich10},
1213 {0x8086, 0x3b16, NT, "Intel", "3450", enable_flash_ich10},
1214 {0x8086, 0x3b1e, NT, "Intel", "B55", enable_flash_ich10},
1215 {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7},
1216 {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4},
1217 {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4},
1218 {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4},
Idwer Vollering570dcc72011-06-18 18:45:50 +00001219 {0x8086, 0x8119, OK, "Intel", "SCH Poulsbo", enable_flash_poulsbo},
1220 {0x8086, 0x8186, NT, "Intel", "Atom E6xx(T)/Tunnel Creek", enable_flash_poulsbo},
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001221#endif
Uwe Hermann05fab752009-05-16 23:42:17 +00001222 {},
Ollie Lhocbbf1252004-03-17 22:22:08 +00001223};
Ollie Lho761bf1b2004-03-20 16:46:10 +00001224
Uwe Hermanna7e05482007-05-09 10:17:44 +00001225int chipset_flash_enable(void)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001226{
Peter Huewe73f8ec82011-01-24 19:15:51 +00001227 struct pci_dev *dev = NULL;
Uwe Hermann372eeb52007-12-04 21:49:06 +00001228 int ret = -2; /* Nothing! */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001229 int i;
Stefan Tauner00155492011-06-26 20:45:35 +00001230 char *s;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001231
Uwe Hermann372eeb52007-12-04 21:49:06 +00001232 /* Now let's try to find the chipset we have... */
Uwe Hermann05fab752009-05-16 23:42:17 +00001233 for (i = 0; chipset_enables[i].vendor_name != NULL; i++) {
1234 dev = pci_dev_find(chipset_enables[i].vendor_id,
1235 chipset_enables[i].device_id);
Michael Karcher89bed6d2010-06-13 10:16:12 +00001236 if (!dev)
1237 continue;
1238 if (ret != -2) {
1239 msg_pinfo("WARNING: unexpected second chipset match: "
Paul Menzelab6328f2010-10-08 11:03:02 +00001240 "\"%s %s\"\n"
1241 "ignoring, please report lspci and board URL "
1242 "to flashrom@flashrom.org\n"
Stefan Reinauerbf282b12011-03-29 21:41:41 +00001243 "with \'CHIPSET: your board name\' in the "
Paul Menzelab6328f2010-10-08 11:03:02 +00001244 "subject line.\n",
Michael Karcher89bed6d2010-06-13 10:16:12 +00001245 chipset_enables[i].vendor_name,
1246 chipset_enables[i].device_name);
1247 continue;
1248 }
Stefan Taunerec8c2482011-07-21 19:59:34 +00001249 msg_pinfo("Found chipset \"%s %s\"",
1250 chipset_enables[i].vendor_name,
1251 chipset_enables[i].device_name);
Stefan Tauner716e0982011-07-25 20:38:52 +00001252 msg_pdbg(" with PCI ID %04x:%04x",
Carl-Daniel Hailfingerf469c272010-05-22 07:31:50 +00001253 chipset_enables[i].vendor_id,
1254 chipset_enables[i].device_id);
Stefan Taunerec8c2482011-07-21 19:59:34 +00001255 msg_pinfo(". ");
Uwe Hermanna7e05482007-05-09 10:17:44 +00001256
Stefan Taunerec8c2482011-07-21 19:59:34 +00001257 if (chipset_enables[i].status == NT) {
1258 msg_pinfo("\nThis chipset is marked as untested. If "
1259 "you are using an up-to-date version\nof "
1260 "flashrom please email a report to "
1261 "flashrom@flashrom.org including a\nverbose "
1262 "(-V) log. Thank you!\n");
1263 }
1264 msg_pinfo("Enabling flash write... ");
Uwe Hermann05fab752009-05-16 23:42:17 +00001265 ret = chipset_enables[i].doit(dev,
1266 chipset_enables[i].device_name);
Michael Karcher89bed6d2010-06-13 10:16:12 +00001267 if (ret == NOT_DONE_YET) {
1268 ret = -2;
1269 msg_pinfo("OK - searching further chips.\n");
1270 } else if (ret < 0)
Sean Nelson316a29f2010-05-07 20:09:04 +00001271 msg_pinfo("FAILED!\n");
Michael Karcher89bed6d2010-06-13 10:16:12 +00001272 else if(ret == 0)
Sean Nelson316a29f2010-05-07 20:09:04 +00001273 msg_pinfo("OK.\n");
Michael Karchera4448d92010-07-22 18:04:15 +00001274 else if(ret == ERROR_NONFATAL)
1275 msg_pinfo("PROBLEMS, continuing anyway\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00001276 }
Michael Karcher89bed6d2010-06-13 10:16:12 +00001277
Stefan Tauner00155492011-06-26 20:45:35 +00001278 s = flashbuses_to_text(buses_supported);
1279 msg_pinfo("This chipset supports the following protocols: %s.\n", s);
1280 free(s);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001281
1282 return ret;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001283}