blob: 8b6b71c9d77d788ad85f68117dc36315391e4312 [file] [log] [blame]
Ollie Lho184a4042005-11-26 21:55:36 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ollie Lho184a4042005-11-26 21:55:36 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Stefan Reinauer8fa64812009-08-12 09:27:45 +00005 * Copyright (C) 2005-2009 coresystems GmbH
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00007 * Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger
Adam Jurkowskie4984102009-12-21 15:30:46 +00008 * Copyright (C) 2009 Kontron Modular Computers GmbH
Ollie Lho184a4042005-11-26 21:55:36 +00009 *
Uwe Hermannd1107642007-08-29 17:52:32 +000010 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
Ollie Lho184a4042005-11-26 21:55:36 +000013 *
Uwe Hermannd1107642007-08-29 17:52:32 +000014 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24/*
25 * Contains the chipset specific flash enables.
Ollie Lho184a4042005-11-26 21:55:36 +000026 */
27
Lane Brooksd54958a2007-11-13 16:45:22 +000028#define _LARGEFILE64_SOURCE
29
Ollie Lhocbbf1252004-03-17 22:22:08 +000030#include <stdlib.h>
Uwe Hermanne8ba5382009-05-22 11:37:27 +000031#include <string.h>
Carl-Daniel Hailfingerdcef67e2010-06-21 23:20:15 +000032#include <unistd.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000033#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000034#include "programmer.h"
Stefan Reinauer86de2832006-03-31 11:26:55 +000035
Michael Karcher89bed6d2010-06-13 10:16:12 +000036#define NOT_DONE_YET 1
37
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +000038#if defined(__i386__) || defined(__x86_64__)
39
Uwe Hermann372eeb52007-12-04 21:49:06 +000040static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
Luc Verhaegen6b141752007-05-20 16:16:13 +000041{
42 uint8_t tmp;
43
Uwe Hermann372eeb52007-12-04 21:49:06 +000044 /*
45 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
46 * 0xFFFE0000-0xFFFFFFFF ROM select enable.
47 */
Luc Verhaegen6b141752007-05-20 16:16:13 +000048 tmp = pci_read_byte(dev, 0x47);
49 tmp |= 0x46;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000050 rpci_write_byte(dev, 0x47, tmp);
Luc Verhaegen6b141752007-05-20 16:16:13 +000051
52 return 0;
53}
54
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000055static int enable_flash_sis85c496(struct pci_dev *dev, const char *name)
56{
57 uint8_t tmp;
58
59 tmp = pci_read_byte(dev, 0xd0);
60 tmp |= 0xf8;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000061 rpci_write_byte(dev, 0xd0, tmp);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000062
63 return 0;
64}
65
66static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name)
67{
68 uint8_t new, newer;
69
70 /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
71 /* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
72 new = pci_read_byte(dev, 0x40);
73 new &= (~0x04); /* No idea why we clear bit 2. */
74 new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +000075 rpci_write_byte(dev, 0x40, new);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000076 newer = pci_read_byte(dev, 0x40);
77 if (newer != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +000078 msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
79 msg_pinfo("Stuck at 0x%x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000080 return -1;
81 }
82 return 0;
83}
84
85static struct pci_dev *find_southbridge(uint16_t vendor, const char *name)
86{
87 struct pci_dev *sbdev;
88
89 sbdev = pci_dev_find_vendorclass(vendor, 0x0601);
90 if (!sbdev)
91 sbdev = pci_dev_find_vendorclass(vendor, 0x0680);
92 if (!sbdev)
93 sbdev = pci_dev_find_vendorclass(vendor, 0x0000);
94 if (!sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +000095 msg_perr("No southbridge found for %s!\n", name);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000096 if (sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +000097 msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n",
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000098 sbdev->vendor_id, sbdev->device_id,
99 sbdev->bus, sbdev->dev, sbdev->func);
100 return sbdev;
101}
102
103static int enable_flash_sis501(struct pci_dev *dev, const char *name)
104{
105 uint8_t tmp;
106 int ret = 0;
107 struct pci_dev *sbdev;
108
109 sbdev = find_southbridge(dev->vendor_id, name);
110 if (!sbdev)
111 return -1;
112
113 ret = enable_flash_sis_mapping(sbdev, name);
114
115 tmp = sio_read(0x22, 0x80);
116 tmp &= (~0x20);
117 tmp |= 0x4;
118 sio_write(0x22, 0x80, tmp);
119
120 tmp = sio_read(0x22, 0x70);
121 tmp &= (~0x20);
122 tmp |= 0x4;
123 sio_write(0x22, 0x70, tmp);
124
125 return ret;
126}
127
128static int enable_flash_sis5511(struct pci_dev *dev, const char *name)
129{
130 uint8_t tmp;
131 int ret = 0;
132 struct pci_dev *sbdev;
133
134 sbdev = find_southbridge(dev->vendor_id, name);
135 if (!sbdev)
136 return -1;
137
138 ret = enable_flash_sis_mapping(sbdev, name);
139
140 tmp = sio_read(0x22, 0x50);
141 tmp &= (~0x20);
142 tmp |= 0x4;
143 sio_write(0x22, 0x50, tmp);
144
145 return ret;
146}
147
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000148static int enable_flash_sis530(struct pci_dev *dev, const char *name)
149{
150 uint8_t new, newer;
151 int ret = 0;
152 struct pci_dev *sbdev;
153
154 sbdev = find_southbridge(dev->vendor_id, name);
155 if (!sbdev)
156 return -1;
157
158 ret = enable_flash_sis_mapping(sbdev, name);
159
160 new = pci_read_byte(sbdev, 0x45);
161 new &= (~0x20);
162 new |= 0x4;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000163 rpci_write_byte(sbdev, 0x45, new);
Luc Verhaegen9cce2f52010-01-10 15:01:08 +0000164 newer = pci_read_byte(sbdev, 0x45);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000165 if (newer != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000166 msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
167 msg_pinfo("Stuck at 0x%x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000168 ret = -1;
169 }
170
171 return ret;
172}
173
174static int enable_flash_sis540(struct pci_dev *dev, const char *name)
175{
176 uint8_t new, newer;
177 int ret = 0;
178 struct pci_dev *sbdev;
179
180 sbdev = find_southbridge(dev->vendor_id, name);
181 if (!sbdev)
182 return -1;
183
184 ret = enable_flash_sis_mapping(sbdev, name);
185
186 new = pci_read_byte(sbdev, 0x45);
187 new &= (~0x80);
188 new |= 0x40;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000189 rpci_write_byte(sbdev, 0x45, new);
Luc Verhaegen9cce2f52010-01-10 15:01:08 +0000190 newer = pci_read_byte(sbdev, 0x45);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000191 if (newer != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000192 msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
193 msg_pinfo("Stuck at 0x%x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000194 ret = -1;
195 }
196
197 return ret;
198}
199
Uwe Hermann987942d2006-11-07 11:16:21 +0000200/* Datasheet:
201 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
202 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
203 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
204 * - Order Number: 290562-001
205 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000206static int enable_flash_piix4(struct pci_dev *dev, const char *name)
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000207{
208 uint16_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000209 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000210
Maciej Pijankaa661e152009-12-08 17:26:24 +0000211 buses_supported = CHIP_BUSTYPE_PARALLEL;
212
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000213 old = pci_read_word(dev, xbcs);
214
215 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
Uwe Hermanna7e05482007-05-09 10:17:44 +0000216 * FFF00000-FFF7FFFF are forwarded to ISA).
Uwe Hermannc556d322008-10-28 11:50:05 +0000217 * Note: This bit is reserved on PIIX/PIIX3/MPIIX.
Uwe Hermanna7e05482007-05-09 10:17:44 +0000218 * Set bit 7: Extended BIOS Enable (PCI master accesses to
219 * FFF80000-FFFDFFFF are forwarded to ISA).
220 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
221 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
222 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
223 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
224 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
225 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
226 */
Uwe Hermannc556d322008-10-28 11:50:05 +0000227 if (dev->device_id == 0x122e || dev->device_id == 0x7000
228 || dev->device_id == 0x1234)
229 new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
Uwe Hermann87203452008-10-26 18:40:42 +0000230 else
231 new = old | 0x02c4;
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000232
233 if (new == old)
234 return 0;
235
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000236 rpci_write_word(dev, xbcs, new);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000237
238 if (pci_read_word(dev, xbcs) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000239 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000240 return -1;
241 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000242
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000243 return 0;
244}
245
Uwe Hermann372eeb52007-12-04 21:49:06 +0000246/*
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000247 * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet"
248 * http://download.intel.com/design/chipsets/datashts/30701303.pdf
Uwe Hermann372eeb52007-12-04 21:49:06 +0000249 */
250static int enable_flash_ich(struct pci_dev *dev, const char *name,
251 int bios_cntl)
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000252{
Ollie Lho184a4042005-11-26 21:55:36 +0000253 uint8_t old, new;
Stefan Reinauereb366472006-09-06 15:48:48 +0000254
Uwe Hermann372eeb52007-12-04 21:49:06 +0000255 /*
256 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
Uwe Hermanna7e05482007-05-09 10:17:44 +0000257 * just treating it as 8 bit wide seems to work fine in practice.
Stefan Reinauereb366472006-09-06 15:48:48 +0000258 */
Stefan Reinauer86de2832006-03-31 11:26:55 +0000259 old = pci_read_byte(dev, bios_cntl);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000260
Sean Nelson316a29f2010-05-07 20:09:04 +0000261 msg_pdbg("\nBIOS Lock Enable: %sabled, ",
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000262 (old & (1 << 1)) ? "en" : "dis");
Sean Nelson316a29f2010-05-07 20:09:04 +0000263 msg_pdbg("BIOS Write Enable: %sabled, ",
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000264 (old & (1 << 0)) ? "en" : "dis");
Sean Nelson316a29f2010-05-07 20:09:04 +0000265 msg_pdbg("BIOS_CNTL is 0x%x\n", old);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000266
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000267 new = old | 1;
268
269 if (new == old)
270 return 0;
271
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000272 rpci_write_byte(dev, bios_cntl, new);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000273
Stefan Reinauer86de2832006-03-31 11:26:55 +0000274 if (pci_read_byte(dev, bios_cntl) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000275 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000276 return -1;
277 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000278
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000279 return 0;
280}
281
Uwe Hermann372eeb52007-12-04 21:49:06 +0000282static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000283{
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000284 /*
285 * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and
286 * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and
287 * FB_DEC_EN2.
288 */
Carl-Daniel Hailfinger7f9922d2010-06-20 11:04:26 +0000289 buses_supported = CHIP_BUSTYPE_FWH;
Stefan Reinauereb366472006-09-06 15:48:48 +0000290 return enable_flash_ich(dev, name, 0x4e);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000291}
292
Uwe Hermann372eeb52007-12-04 21:49:06 +0000293static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000294{
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000295 uint32_t fwh_conf;
296 int i;
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000297 char *idsel = NULL;
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000298 int tmp;
299 int max_decode_fwh_idsel = 0;
300 int max_decode_fwh_decode = 0;
301 int contiguous = 1;
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000302
Carl-Daniel Hailfinger2b6dcb32010-07-08 10:13:37 +0000303 idsel = extract_programmer_param("fwh_idsel");
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000304 if (idsel && strlen(idsel)) {
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000305 fwh_conf = (uint32_t)strtoul(idsel, NULL, 0);
306
307 /* FIXME: Need to undo this on shutdown. */
Sean Nelson316a29f2010-05-07 20:09:04 +0000308 msg_pinfo("\nSetting IDSEL=0x%x for top 16 MB", fwh_conf);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000309 rpci_write_long(dev, 0xd0, fwh_conf);
310 rpci_write_word(dev, 0xd4, fwh_conf);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000311 /* FIXME: Decode settings are not changed. */
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000312 } else if (idsel) {
313 msg_perr("Error: idsel= specified, but no number given.\n");
314 free(idsel);
315 /* FIXME: Return failure here once internal_init() starts
316 * to care about the return value of the chipset enable.
317 */
318 exit(1);
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000319 }
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000320 free(idsel);
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000321
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000322 /* Ignore all legacy ranges below 1 MB.
323 * We currently only support flashing the chip which responds to
324 * IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations
325 * have to be adjusted.
326 */
327 /* FWH_SEL1 */
328 fwh_conf = pci_read_long(dev, 0xd0);
329 for (i = 7; i >= 0; i--) {
330 tmp = (fwh_conf >> (i * 4)) & 0xf;
Sean Nelson316a29f2010-05-07 20:09:04 +0000331 msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000332 (0x1ff8 + i) * 0x80000,
333 (0x1ff0 + i) * 0x80000,
334 tmp);
335 if ((tmp == 0) && contiguous) {
336 max_decode_fwh_idsel = (8 - i) * 0x80000;
337 } else {
338 contiguous = 0;
339 }
340 }
341 /* FWH_SEL2 */
342 fwh_conf = pci_read_word(dev, 0xd4);
343 for (i = 3; i >= 0; i--) {
344 tmp = (fwh_conf >> (i * 4)) & 0xf;
Sean Nelson316a29f2010-05-07 20:09:04 +0000345 msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000346 (0xff4 + i) * 0x100000,
347 (0xff0 + i) * 0x100000,
348 tmp);
349 if ((tmp == 0) && contiguous) {
350 max_decode_fwh_idsel = (8 - i) * 0x100000;
351 } else {
352 contiguous = 0;
353 }
354 }
355 contiguous = 1;
356 /* FWH_DEC_EN1 */
357 fwh_conf = pci_read_word(dev, 0xd8);
358 for (i = 7; i >= 0; i--) {
359 tmp = (fwh_conf >> (i + 0x8)) & 0x1;
Sean Nelson316a29f2010-05-07 20:09:04 +0000360 msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled",
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000361 (0x1ff8 + i) * 0x80000,
362 (0x1ff0 + i) * 0x80000,
363 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000364 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000365 max_decode_fwh_decode = (8 - i) * 0x80000;
366 } else {
367 contiguous = 0;
368 }
369 }
370 for (i = 3; i >= 0; i--) {
371 tmp = (fwh_conf >> i) & 0x1;
Sean Nelson316a29f2010-05-07 20:09:04 +0000372 msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled",
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000373 (0xff4 + i) * 0x100000,
374 (0xff0 + i) * 0x100000,
375 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000376 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000377 max_decode_fwh_decode = (8 - i) * 0x100000;
378 } else {
379 contiguous = 0;
380 }
381 }
382 max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode);
Sean Nelson316a29f2010-05-07 20:09:04 +0000383 msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000384
385 /* If we're called by enable_flash_ich_dc_spi, it will override
386 * buses_supported anyway.
387 */
388 buses_supported = CHIP_BUSTYPE_FWH;
Stefan Reinauereb366472006-09-06 15:48:48 +0000389 return enable_flash_ich(dev, name, 0xdc);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000390}
391
Adam Jurkowskie4984102009-12-21 15:30:46 +0000392static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
393{
394 uint16_t old, new;
395 int err;
396
397 if ((err = enable_flash_ich(dev, name, 0xd8)) != 0)
398 return err;
399
400 old = pci_read_byte(dev, 0xd9);
Sean Nelson316a29f2010-05-07 20:09:04 +0000401 msg_pdbg("BIOS Prefetch Enable: %sabled, ",
Adam Jurkowskie4984102009-12-21 15:30:46 +0000402 (old & 1) ? "en" : "dis");
403 new = old & ~1;
404
405 if (new != old)
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000406 rpci_write_byte(dev, 0xd9, new);
Adam Jurkowskie4984102009-12-21 15:30:46 +0000407
Carl-Daniel Hailfinger7f9922d2010-06-20 11:04:26 +0000408 buses_supported = CHIP_BUSTYPE_FWH;
Adam Jurkowskie4984102009-12-21 15:30:46 +0000409 return 0;
410}
411
412
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000413#define ICH_STRAP_RSVD 0x00
414#define ICH_STRAP_SPI 0x01
415#define ICH_STRAP_PCI 0x02
416#define ICH_STRAP_LPC 0x03
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000417
Uwe Hermann394131e2008-10-18 21:14:13 +0000418static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
419{
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000420 /* Do we really need no write enable? */
Michael Karchera4448d92010-07-22 18:04:15 +0000421 return via_init_spi(dev);
Joshua Roysf93b36a2010-07-01 17:45:54 +0000422}
423
Uwe Hermann394131e2008-10-18 21:14:13 +0000424static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
425 int ich_generation)
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000426{
Michael Karchera4448d92010-07-22 18:04:15 +0000427 int ret;
428 uint8_t bbs, buc;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000429 uint32_t tmp, gcs;
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000430 void *rcrb;
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000431 //TODO: These names are incorrect for EP80579. For that, the solution would look like the commented line
432 //static const char *straps_names[] = {"SPI", "reserved", "reserved", "LPC" };
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000433 static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" };
Uwe Hermann394131e2008-10-18 21:14:13 +0000434
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000435 /* Enable Flash Writes */
436 ret = enable_flash_ich_dc(dev, name);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000437
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000438 /* Get physical address of Root Complex Register Block */
439 tmp = pci_read_long(dev, 0xf0) & 0xffffc000;
Sean Nelson316a29f2010-05-07 20:09:04 +0000440 msg_pdbg("\nRoot Complex Register Block address = 0x%x\n", tmp);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000441
442 /* Map RCBA to virtual memory */
Stefan Reinauer0593f212009-01-26 01:10:48 +0000443 rcrb = physmap("ICH RCRB", tmp, 0x4000);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000444
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000445 gcs = mmio_readl(rcrb + 0x3410);
Sean Nelson316a29f2010-05-07 20:09:04 +0000446 msg_pdbg("GCS = 0x%x: ", gcs);
447 msg_pdbg("BIOS Interface Lock-Down: %sabled, ",
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000448 (gcs & 0x1) ? "en" : "dis");
449 bbs = (gcs >> 10) & 0x3;
Sean Nelson316a29f2010-05-07 20:09:04 +0000450 msg_pdbg("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000451
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000452 buc = mmio_readb(rcrb + 0x3414);
Sean Nelson316a29f2010-05-07 20:09:04 +0000453 msg_pdbg("Top Swap : %s\n",
Uwe Hermann394131e2008-10-18 21:14:13 +0000454 (buc & 1) ? "enabled (A16 inverted)" : "not enabled");
Stefan Reinauera9424d52008-06-27 16:28:34 +0000455
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000456 /* It seems the ICH7 does not support SPI and LPC chips at the same
457 * time. At least not with our current code. So we prevent searching
458 * on ICH7 when the southbridge is strapped to LPC
459 */
460
Michael Karchera4448d92010-07-22 18:04:15 +0000461 buses_supported = CHIP_BUSTYPE_FWH;
462 if (ich_generation == 7) {
463 if(bbs == ICH_STRAP_LPC) {
464 /* No further SPI initialization required */
465 return ret;
466 }
467 else
468 /* Disable LPC/FWH if strapped to PCI or SPI */
469 buses_supported = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000470 }
471
Michael Karchera4448d92010-07-22 18:04:15 +0000472 /* this adds CHIP_BUSTYPE_SPI */
473 if (ich_init_spi(dev, tmp, rcrb, ich_generation) != 0) {
474 if (!ret)
475 ret = ERROR_NONFATAL;
476 }
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000477
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000478 return ret;
479}
Stefan Reinauera9424d52008-06-27 16:28:34 +0000480
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000481static int enable_flash_ich7(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000482{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000483 return enable_flash_ich_dc_spi(dev, name, 7);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000484}
485
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000486static int enable_flash_ich8(struct pci_dev *dev, const char *name)
487{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000488 return enable_flash_ich_dc_spi(dev, name, 8);
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000489}
490
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000491static int enable_flash_ich9(struct pci_dev *dev, const char *name)
492{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000493 return enable_flash_ich_dc_spi(dev, name, 9);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000494}
495
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000496static int enable_flash_ich10(struct pci_dev *dev, const char *name)
497{
498 return enable_flash_ich_dc_spi(dev, name, 10);
499}
500
Michael Karcher89bed6d2010-06-13 10:16:12 +0000501static int via_no_byte_merge(struct pci_dev *dev, const char *name)
502{
503 uint8_t val;
504
505 val = pci_read_byte(dev, 0x71);
506 if (val & 0x40)
507 {
508 msg_pdbg("Disabling byte merging\n");
509 val &= ~0x40;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000510 rpci_write_byte(dev, 0x71, val);
Michael Karcher89bed6d2010-06-13 10:16:12 +0000511 }
512 return NOT_DONE_YET; /* need to find south bridge, too */
513}
514
Uwe Hermann372eeb52007-12-04 21:49:06 +0000515static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000516{
Ollie Lho184a4042005-11-26 21:55:36 +0000517 uint8_t val;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000518
Uwe Hermann394131e2008-10-18 21:14:13 +0000519 /* enable ROM decode range (1MB) FFC00000 - FFFFFFFF */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000520 rpci_write_byte(dev, 0x41, 0x7f);
Bari Ari9477c4e2008-04-29 13:46:38 +0000521
Uwe Hermannffec5f32007-08-23 16:08:21 +0000522 /* ROM write enable */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000523 val = pci_read_byte(dev, 0x40);
524 val |= 0x10;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000525 rpci_write_byte(dev, 0x40, val);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000526
527 if (pci_read_byte(dev, 0x40) != val) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000528 msg_pinfo("\nWARNING: Failed to enable flash write on \"%s\"\n",
Uwe Hermanna7e05482007-05-09 10:17:44 +0000529 name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000530 return -1;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000531 }
Luc Verhaegen6382b442007-03-02 22:16:38 +0000532
Luc Verhaegen73d21192009-12-23 00:54:26 +0000533 if (dev->device_id == 0x3227) { /* VT8237R */
534 /* All memory cycles, not just ROM ones, go to LPC. */
535 val = pci_read_byte(dev, 0x59);
536 val &= ~0x80;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000537 rpci_write_byte(dev, 0x59, val);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000538 }
539
Uwe Hermanna7e05482007-05-09 10:17:44 +0000540 return 0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000541}
542
Uwe Hermann372eeb52007-12-04 21:49:06 +0000543static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000544{
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000545 uint8_t reg8;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000546
Uwe Hermann394131e2008-10-18 21:14:13 +0000547#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
548#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000549#define CS5530_RESET_CONTROL_REG 0x44 /* F0 index 0x44 */
550#define CS5530_USB_SHADOW_REG 0x43 /* F0 index 0x43 */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000551
Uwe Hermann394131e2008-10-18 21:14:13 +0000552#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
553#define ROM_WRITE_ENABLE (1 << 1)
554#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
555#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000556#define CS5530_ISA_MASTER (1 << 7)
557#define CS5530_ENABLE_SA2320 (1 << 2)
558#define CS5530_ENABLE_SA20 (1 << 6)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000559
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000560 buses_supported = CHIP_BUSTYPE_PARALLEL;
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000561 /* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
562 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000563 * FIXME: Should we really touch the low mapping below 1 MB? Flashrom
564 * ignores that region completely.
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000565 * Make the configured ROM areas writable.
566 */
567 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
568 reg8 |= LOWER_ROM_ADDRESS_RANGE;
569 reg8 |= UPPER_ROM_ADDRESS_RANGE;
570 reg8 |= ROM_WRITE_ENABLE;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000571 rpci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000572
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000573 /* Set positive decode on ROM. */
574 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
575 reg8 |= BIOS_ROM_POSITIVE_DECODE;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000576 rpci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000577
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000578 reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG);
579 if (reg8 & CS5530_ISA_MASTER) {
580 /* We have A0-A23 available. */
581 max_rom_decode.parallel = 16 * 1024 * 1024;
582 } else {
583 reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG);
584 if (reg8 & CS5530_ENABLE_SA2320) {
585 /* We have A0-19, A20-A23 available. */
586 max_rom_decode.parallel = 16 * 1024 * 1024;
587 } else if (reg8 & CS5530_ENABLE_SA20) {
588 /* We have A0-19, A20 available. */
589 max_rom_decode.parallel = 2 * 1024 * 1024;
590 } else {
591 /* A20 and above are not active. */
592 max_rom_decode.parallel = 1024 * 1024;
593 }
594 }
595
Ollie Lhocbbf1252004-03-17 22:22:08 +0000596 return 0;
597}
598
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000599/*
Mart Raudseppe1344da2008-02-08 10:10:57 +0000600 * Geode systems write protect the BIOS via RCONFs (cache settings similar
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000601 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
Mart Raudseppe1344da2008-02-08 10:10:57 +0000602 *
603 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
604 * To enable write to NOR Boot flash for the benefit of systems that have such
605 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
Mart Raudseppe1344da2008-02-08 10:10:57 +0000606 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000607static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
Lane Brooksd54958a2007-11-13 16:45:22 +0000608{
Uwe Hermann394131e2008-10-18 21:14:13 +0000609#define MSR_RCONF_DEFAULT 0x1808
610#define MSR_NORF_CTL 0x51400018
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000611
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000612 msr_t msr;
Lane Brooksd54958a2007-11-13 16:45:22 +0000613
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000614 /* Geode only has a single core */
615 if (setup_cpu_msr(0))
Lane Brooksd54958a2007-11-13 16:45:22 +0000616 return -1;
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000617
618 msr = rdmsr(MSR_RCONF_DEFAULT);
619 if ((msr.hi >> 24) != 0x22) {
620 msr.hi &= 0xfbffffff;
621 wrmsr(MSR_RCONF_DEFAULT, msr);
Lane Brooksd54958a2007-11-13 16:45:22 +0000622 }
Mart Raudseppe1344da2008-02-08 10:10:57 +0000623
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000624 msr = rdmsr(MSR_NORF_CTL);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000625 /* Raise WE_CS3 bit. */
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000626 msr.lo |= 0x08;
627 wrmsr(MSR_NORF_CTL, msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000628
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000629 cleanup_cpu_msr();
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000630
Uwe Hermann394131e2008-10-18 21:14:13 +0000631#undef MSR_RCONF_DEFAULT
632#undef MSR_NORF_CTL
Lane Brooksd54958a2007-11-13 16:45:22 +0000633 return 0;
634}
635
Uwe Hermann372eeb52007-12-04 21:49:06 +0000636static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000637{
Ollie Lho184a4042005-11-26 21:55:36 +0000638 uint8_t new;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000639
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000640 rpci_write_byte(dev, 0x52, 0xee);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000641
642 new = pci_read_byte(dev, 0x52);
643
644 if (new != 0xee) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000645 msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000646 return -1;
647 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000648
Ollie Lhocbbf1252004-03-17 22:22:08 +0000649 return 0;
650}
651
Uwe Hermann190f8492008-10-25 18:03:50 +0000652/* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000653static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000654{
Ollie Lho184a4042005-11-26 21:55:36 +0000655 uint8_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000656
Uwe Hermann372eeb52007-12-04 21:49:06 +0000657 /* Enable decoding at 0xffb00000 to 0xffffffff. */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000658 old = pci_read_byte(dev, 0x43);
Ollie Lhod11f3612004-12-07 17:19:04 +0000659 new = old | 0xC0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000660 if (new != old) {
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000661 rpci_write_byte(dev, 0x43, new);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000662 if (pci_read_byte(dev, 0x43) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000663 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000664 }
665 }
666
Uwe Hermann190f8492008-10-25 18:03:50 +0000667 /* Enable 'ROM write' bit. */
Ollie Lho761bf1b2004-03-20 16:46:10 +0000668 old = pci_read_byte(dev, 0x40);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000669 new = old | 0x01;
670 if (new == old)
671 return 0;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000672 rpci_write_byte(dev, 0x40, new);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000673
674 if (pci_read_byte(dev, 0x40) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000675 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000676 return -1;
677 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000678
Ollie Lhocbbf1252004-03-17 22:22:08 +0000679 return 0;
680}
681
Marc Jones3af487d2008-10-15 17:50:29 +0000682static int enable_flash_sb600(struct pci_dev *dev, const char *name)
683{
Michael Karcherb05b9e12010-07-22 18:04:19 +0000684 uint32_t prot;
Marc Jones3af487d2008-10-15 17:50:29 +0000685 uint8_t reg;
Michael Karcherb05b9e12010-07-22 18:04:19 +0000686 int ret;
Marc Jones3af487d2008-10-15 17:50:29 +0000687
Jason Wanga3f04be2008-11-28 21:36:51 +0000688 /* Clear ROM protect 0-3. */
689 for (reg = 0x50; reg < 0x60; reg += 4) {
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000690 prot = pci_read_long(dev, reg);
691 /* No protection flags for this region?*/
692 if ((prot & 0x3) == 0)
693 continue;
Mathias Krause9fbdc032011-01-01 10:54:09 +0000694 msg_pinfo("SB600 %s%sprotected from 0x%08x to 0x%08x\n",
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000695 (prot & 0x1) ? "write " : "",
696 (prot & 0x2) ? "read " : "",
Mathias Krause9fbdc032011-01-01 10:54:09 +0000697 (prot & 0xfffff800),
698 (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000699 prot &= 0xfffffffc;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000700 rpci_write_byte(dev, reg, prot);
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000701 prot = pci_read_long(dev, reg);
Carl-Daniel Hailfinger9bb88ac2009-05-06 13:51:44 +0000702 if (prot & 0x3)
Mathias Krause9fbdc032011-01-01 10:54:09 +0000703 msg_perr("SB600 %s%sunprotect failed from 0x%08x to 0x%08x\n",
Carl-Daniel Hailfinger9bb88ac2009-05-06 13:51:44 +0000704 (prot & 0x1) ? "write " : "",
705 (prot & 0x2) ? "read " : "",
Mathias Krause9fbdc032011-01-01 10:54:09 +0000706 (prot & 0xfffff800),
707 (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
Jason Wanga3f04be2008-11-28 21:36:51 +0000708 }
709
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000710 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH;
Michael Karcherb05b9e12010-07-22 18:04:19 +0000711
712 ret = sb600_probe_spi(dev);
Jason Wanga3f04be2008-11-28 21:36:51 +0000713
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000714 /* Read ROM strap override register. */
715 OUTB(0x8f, 0xcd6);
716 reg = INB(0xcd7);
717 reg &= 0x0e;
Sean Nelson316a29f2010-05-07 20:09:04 +0000718 msg_pdbg("ROM strap override is %sactive", (reg & 0x02) ? "" : "not ");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000719 if (reg & 0x02) {
720 switch ((reg & 0x0c) >> 2) {
721 case 0x00:
Sean Nelson316a29f2010-05-07 20:09:04 +0000722 msg_pdbg(": LPC");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000723 break;
724 case 0x01:
Sean Nelson316a29f2010-05-07 20:09:04 +0000725 msg_pdbg(": PCI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000726 break;
727 case 0x02:
Sean Nelson316a29f2010-05-07 20:09:04 +0000728 msg_pdbg(": FWH");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000729 break;
730 case 0x03:
Sean Nelson316a29f2010-05-07 20:09:04 +0000731 msg_pdbg(": SPI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000732 break;
733 }
734 }
Sean Nelson316a29f2010-05-07 20:09:04 +0000735 msg_pdbg("\n");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000736
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000737 /* Force enable SPI ROM in SB600 PM register.
738 * If we enable SPI ROM here, we have to disable it after we leave.
Zheng Bao284a6002009-05-04 22:33:50 +0000739 * But how can we know which ROM we are going to handle? So we have
740 * to trade off. We only access LPC ROM if we boot via LPC ROM. And
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000741 * only SPI ROM if we boot via SPI ROM. If you want to access SPI on
742 * boards with LPC straps, you have to use the code below.
Zheng Bao284a6002009-05-04 22:33:50 +0000743 */
744 /*
Jason Wanga3f04be2008-11-28 21:36:51 +0000745 OUTB(0x8f, 0xcd6);
746 OUTB(0x0e, 0xcd7);
Zheng Bao284a6002009-05-04 22:33:50 +0000747 */
Marc Jones3af487d2008-10-15 17:50:29 +0000748
Michael Karcherb05b9e12010-07-22 18:04:19 +0000749 return ret;
Marc Jones3af487d2008-10-15 17:50:29 +0000750}
751
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000752static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name)
753{
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000754 uint8_t tmp;
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000755
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000756 rpci_write_byte(dev, 0x92, 0);
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000757
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000758 tmp = pci_read_byte(dev, 0x6d);
759 tmp |= 0x01;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000760 rpci_write_byte(dev, 0x6d, tmp);
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000761
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000762 return 0;
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000763}
764
Uwe Hermann372eeb52007-12-04 21:49:06 +0000765static int enable_flash_ck804(struct pci_dev *dev, const char *name)
Yinghai Lu952dfce2005-07-06 17:13:46 +0000766{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000767 uint8_t old, new;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000768
Uwe Hermanna7e05482007-05-09 10:17:44 +0000769 old = pci_read_byte(dev, 0x88);
770 new = old | 0xc0;
771 if (new != old) {
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000772 rpci_write_byte(dev, 0x88, new);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000773 if (pci_read_byte(dev, 0x88) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000774 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000775 }
776 }
Yinghai Lu952dfce2005-07-06 17:13:46 +0000777
Uwe Hermanna7e05482007-05-09 10:17:44 +0000778 old = pci_read_byte(dev, 0x6d);
779 new = old | 0x01;
780 if (new == old)
781 return 0;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000782 rpci_write_byte(dev, 0x6d, new);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000783
784 if (pci_read_byte(dev, 0x6d) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000785 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000786 return -1;
787 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000788
Uwe Hermanna7e05482007-05-09 10:17:44 +0000789 return 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000790}
791
Joshua Roys85835d82010-09-15 14:47:56 +0000792static int enable_flash_osb4(struct pci_dev *dev, const char *name)
793{
794 uint8_t tmp;
795
796 buses_supported = CHIP_BUSTYPE_PARALLEL;
797
798 tmp = INB(0xc06);
799 tmp |= 0x1;
800 OUTB(tmp, 0xc06);
801
802 tmp = INB(0xc6f);
803 tmp |= 0x40;
804 OUTB(tmp, 0xc6f);
805
806 return 0;
807}
808
Uwe Hermann372eeb52007-12-04 21:49:06 +0000809/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
810static int enable_flash_sb400(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000811{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000812 uint8_t tmp;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000813 struct pci_dev *smbusdev;
814
Uwe Hermann372eeb52007-12-04 21:49:06 +0000815 /* Look for the SMBus device. */
Carl-Daniel Hailfingerf6e3efb2009-05-06 00:35:31 +0000816 smbusdev = pci_dev_find(0x1002, 0x4372);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000817
Uwe Hermanna7e05482007-05-09 10:17:44 +0000818 if (!smbusdev) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000819 msg_perr("ERROR: SMBus device not found. Aborting.\n");
Stefan Reinauer86de2832006-03-31 11:26:55 +0000820 exit(1);
821 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000822
Uwe Hermann372eeb52007-12-04 21:49:06 +0000823 /* Enable some SMBus stuff. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000824 tmp = pci_read_byte(smbusdev, 0x79);
825 tmp |= 0x01;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000826 rpci_write_byte(smbusdev, 0x79, tmp);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000827
Uwe Hermann372eeb52007-12-04 21:49:06 +0000828 /* Change southbridge. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000829 tmp = pci_read_byte(dev, 0x48);
830 tmp |= 0x21;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000831 rpci_write_byte(dev, 0x48, tmp);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000832
Uwe Hermann372eeb52007-12-04 21:49:06 +0000833 /* Now become a bit silly. */
Andriy Gapon65c1b862008-05-22 13:22:45 +0000834 tmp = INB(0xc6f);
835 OUTB(tmp, 0xeb);
836 OUTB(tmp, 0xeb);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000837 tmp |= 0x40;
Andriy Gapon65c1b862008-05-22 13:22:45 +0000838 OUTB(tmp, 0xc6f);
839 OUTB(tmp, 0xeb);
840 OUTB(tmp, 0xeb);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000841
842 return 0;
843}
844
Uwe Hermann372eeb52007-12-04 21:49:06 +0000845static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
Yinghai Luca782972007-01-22 20:21:17 +0000846{
Michael Karcher4e2fb0e2010-01-12 23:29:26 +0000847 uint8_t old, new, val;
848 uint16_t wordval;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000849
Uwe Hermann372eeb52007-12-04 21:49:06 +0000850 /* Set the 0-16 MB enable bits. */
Michael Karcher4e2fb0e2010-01-12 23:29:26 +0000851 val = pci_read_byte(dev, 0x88);
852 val |= 0xff; /* 256K */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000853 rpci_write_byte(dev, 0x88, val);
Michael Karcher4e2fb0e2010-01-12 23:29:26 +0000854 val = pci_read_byte(dev, 0x8c);
855 val |= 0xff; /* 1M */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000856 rpci_write_byte(dev, 0x8c, val);
Michael Karcher4e2fb0e2010-01-12 23:29:26 +0000857 wordval = pci_read_word(dev, 0x90);
858 wordval |= 0x7fff; /* 16M */
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000859 rpci_write_word(dev, 0x90, wordval);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000860
Uwe Hermanna7e05482007-05-09 10:17:44 +0000861 old = pci_read_byte(dev, 0x6d);
862 new = old | 0x01;
863 if (new == old)
864 return 0;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000865 rpci_write_byte(dev, 0x6d, new);
Yinghai Luca782972007-01-22 20:21:17 +0000866
Uwe Hermanna7e05482007-05-09 10:17:44 +0000867 if (pci_read_byte(dev, 0x6d) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000868 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000869 return -1;
870 }
Yinghai Luca782972007-01-22 20:21:17 +0000871
872 return 0;
Yinghai Luca782972007-01-22 20:21:17 +0000873}
874
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000875/*
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000876 * The MCP6x/MCP7x code is based on cleanroom reverse engineering.
877 * It is assumed that LPC chips need the MCP55 code and SPI chips need the
878 * code provided in enable_flash_mcp6x_7x_common.
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000879 */
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000880static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000881{
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000882 int ret = 0;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000883 int want_spi = 0;
Michael Karchercfa674f2010-02-25 11:38:23 +0000884 uint8_t val;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000885
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000886 msg_pinfo("This chipset is not really supported yet. Guesswork...\n");
887
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000888 /* dev is the ISA bridge. No idea what the stuff below does. */
Michael Karchercfa674f2010-02-25 11:38:23 +0000889 val = pci_read_byte(dev, 0x8a);
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000890 msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 "
Michael Karchercfa674f2010-02-25 11:38:23 +0000891 "is %i\n", val, (val >> 6) & 0x1, (val >> 5) & 0x1);
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000892
Michael Karchercfa674f2010-02-25 11:38:23 +0000893 switch ((val >> 5) & 0x3) {
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000894 case 0x0:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000895 ret = enable_flash_mcp55(dev, name);
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000896 buses_supported = CHIP_BUSTYPE_LPC;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000897 msg_pdbg("Flash bus type is LPC\n");
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000898 break;
899 case 0x2:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000900 want_spi = 1;
901 /* SPI is added in mcp6x_spi_init if it works.
902 * Do we really want to disable LPC in this case?
903 */
904 buses_supported = CHIP_BUSTYPE_NONE;
905 msg_pdbg("Flash bus type is SPI\n");
906 msg_perr("SPI on this chipset is WIP. Write is unsupported!\n");
907 programmer_may_write = 0;
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000908 break;
909 default:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000910 /* Should not happen. */
911 buses_supported = CHIP_BUSTYPE_NONE;
912 msg_pdbg("Flash bus type is unknown (none)\n");
913 msg_pinfo("Something went wrong with bus type detection.\n");
914 goto out_msg;
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000915 break;
916 }
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000917
918 /* Force enable SPI and disable LPC? Not a good idea. */
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000919#if 0
Michael Karchercfa674f2010-02-25 11:38:23 +0000920 val |= (1 << 6);
921 val &= ~(1 << 5);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000922 rpci_write_byte(dev, 0x8a, val);
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000923#endif
924
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000925 if (mcp6x_spi_init(want_spi)) {
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000926 ret = 1;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000927 }
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000928out_msg:
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000929 msg_pinfo("Please send the output of \"flashrom -V\" to "
Paul Menzelab6328f2010-10-08 11:03:02 +0000930 "flashrom@flashrom.org with\n"
931 "your board name: flashrom -V as the subject to help us "
932 "finish support for your\n"
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000933 "chipset. Thanks.\n");
934
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000935 return ret;
936}
937
Uwe Hermann372eeb52007-12-04 21:49:06 +0000938static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000939{
Michael Karchercfa674f2010-02-25 11:38:23 +0000940 uint8_t val;
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000941
Uwe Hermanne823ee02007-06-05 15:02:18 +0000942 /* Set the 4MB enable bit. */
Michael Karchercfa674f2010-02-25 11:38:23 +0000943 val = pci_read_byte(dev, 0x41);
944 val |= 0x0e;
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000945 rpci_write_byte(dev, 0x41, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000946
Michael Karchercfa674f2010-02-25 11:38:23 +0000947 val = pci_read_byte(dev, 0x43);
948 val |= (1 << 4);
Carl-Daniel Hailfinger2bee8cf2010-11-10 15:25:18 +0000949 rpci_write_byte(dev, 0x43, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000950
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000951 return 0;
952}
953
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000954/*
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000955 * Usually on the x86 architectures (and on other PC-like platforms like some
956 * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
957 * Elan SC520 only a small piece of the system flash is mapped there, but the
958 * complete flash is mapped somewhere below 1G. The position can be determined
959 * by the BOOTCS PAR register.
960 */
961static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
962{
963 int i, bootcs_found = 0;
964 uint32_t parx = 0;
965 void *mmcr;
966
967 /* 1. Map MMCR */
Stefan Reinauer0593f212009-01-26 01:10:48 +0000968 mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000969
970 /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for
971 * BOOTCS region (PARx[31:29] = 100b)e
972 */
973 for (i = 0x88; i <= 0xc4; i += 4) {
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000974 parx = mmio_readl(mmcr + i);
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000975 if ((parx >> 29) == 4) {
976 bootcs_found = 1;
977 break; /* BOOTCS found */
978 }
979 }
980
981 /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0]
982 * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0]
983 */
984 if (bootcs_found) {
985 if (parx & (1 << 25)) {
986 parx &= (1 << 14) - 1; /* Mask [13:0] */
987 flashbase = parx << 16;
988 } else {
989 parx &= (1 << 18) - 1; /* Mask [17:0] */
990 flashbase = parx << 12;
991 }
992 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000993 msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n");
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000994 }
995
996 /* 4. Clean up */
Carl-Daniel Hailfingerbe726812009-08-09 12:44:08 +0000997 physunmap(mmcr, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000998 return 0;
999}
1000
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001001#endif
1002
Uwe Hermann4179d292009-05-08 17:50:51 +00001003/* Please keep this list alphabetically sorted by vendor/device. */
Uwe Hermann05fab752009-05-16 23:42:17 +00001004const struct penable chipset_enables[] = {
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001005#if defined(__i386__) || defined(__x86_64__)
Uwe Hermann4179d292009-05-08 17:50:51 +00001006 {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533},
1007 {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111},
1008 {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111},
1009 {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530},
1010 {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536},
Nils Jacobse715c7b2009-09-23 02:09:23 +00001011 {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536},
Uwe Hermann4179d292009-05-08 17:50:51 +00001012 {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520},
1013 {0x1002, 0x438D, OK, "AMD", "SB600", enable_flash_sb600},
Stefan Tauner77000512011-04-02 11:47:21 +00001014 {0x1002, 0x439d, OK, "AMD", "SB700/SB710/SB750/SB850", enable_flash_sb600},
Uwe Hermann4179d292009-05-08 17:50:51 +00001015 {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100},
1016 {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400},
Joshua Roys85835d82010-09-15 14:47:56 +00001017 {0x1166, 0x0200, OK, "Broadcom", "OSB4", enable_flash_osb4},
Uwe Hermann4179d292009-05-08 17:50:51 +00001018 {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000},
Carl-Daniel Hailfinger797a8342009-11-26 16:51:39 +00001019 {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_ich10},
1020 {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_ich10},
Helge Wagnera319be12010-08-11 21:06:10 +00001021 {0x8086, 0x3b02, NT, "Intel", "P55", enable_flash_ich10},
1022 {0x8086, 0x3b03, NT, "Intel", "PM55", enable_flash_ich10},
1023 {0x8086, 0x3b06, NT, "Intel", "H55", enable_flash_ich10},
1024 {0x8086, 0x3b07, OK, "Intel", "QM57", enable_flash_ich10},
1025 {0x8086, 0x3b08, NT, "Intel", "H57", enable_flash_ich10},
1026 {0x8086, 0x3b09, NT, "Intel", "HM55", enable_flash_ich10},
1027 {0x8086, 0x3b0a, NT, "Intel", "Q57", enable_flash_ich10},
1028 {0x8086, 0x3b0b, NT, "Intel", "HM57", enable_flash_ich10},
Carl-Daniel Hailfinger797a8342009-11-26 16:51:39 +00001029 {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_ich10},
Helge Wagnera319be12010-08-11 21:06:10 +00001030 {0x8086, 0x3b0e, NT, "Intel", "B55", enable_flash_ich10},
1031 {0x8086, 0x3b0f, NT, "Intel", "QS57", enable_flash_ich10},
1032 {0x8086, 0x3b12, NT, "Intel", "3400", enable_flash_ich10},
1033 {0x8086, 0x3b14, NT, "Intel", "3420", enable_flash_ich10},
1034 {0x8086, 0x3b16, NT, "Intel", "3450", enable_flash_ich10},
1035 {0x8086, 0x3b1e, NT, "Intel", "B55", enable_flash_ich10},
Uwe Hermannb0039912009-05-07 13:24:49 +00001036 {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4},
Uwe Hermann4179d292009-05-08 17:50:51 +00001037 {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich_4e},
1038 {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich_dc},
1039 {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7},
Uwe Hermannb0039912009-05-07 13:24:49 +00001040 {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e},
Uwe Hermann4179d292009-05-08 17:50:51 +00001041 {0x8086, 0x3a18, OK, "Intel", "ICH10", enable_flash_ich10},
1042 {0x8086, 0x3a1a, OK, "Intel", "ICH10D", enable_flash_ich10},
1043 {0x8086, 0x3a14, OK, "Intel", "ICH10DO", enable_flash_ich10},
1044 {0x8086, 0x3a16, OK, "Intel", "ICH10R", enable_flash_ich10},
Uwe Hermannb0039912009-05-07 13:24:49 +00001045 {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e},
1046 {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +00001047 {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich_4e},
Uwe Hermann4179d292009-05-08 17:50:51 +00001048 {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +00001049 {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich_4e},
1050 {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich_4e},
1051 {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +00001052 {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich_dc},
1053 {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich_dc},
Uwe Hermannb0039912009-05-07 13:24:49 +00001054 {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7},
1055 {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7},
1056 {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7},
1057 {0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7},
David Hendricksdb7c1532010-01-19 02:19:27 +00001058 {0x8086, 0x27bc, OK, "Intel", "NM10", enable_flash_ich7},
Uwe Hermann4179d292009-05-08 17:50:51 +00001059 {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +00001060 {0x8086, 0x2812, OK, "Intel", "ICH8DH", enable_flash_ich8},
1061 {0x8086, 0x2814, OK, "Intel", "ICH8DO", enable_flash_ich8},
Uwe Hermann4179d292009-05-08 17:50:51 +00001062 {0x8086, 0x2810, OK, "Intel", "ICH8/ICH8R", enable_flash_ich8},
Uwe Hermannb0039912009-05-07 13:24:49 +00001063 {0x8086, 0x2815, OK, "Intel", "ICH8M", enable_flash_ich8},
Uwe Hermann4179d292009-05-08 17:50:51 +00001064 {0x8086, 0x2811, OK, "Intel", "ICH8M-E", enable_flash_ich8},
1065 {0x8086, 0x2918, OK, "Intel", "ICH9", enable_flash_ich9},
Uwe Hermannb0039912009-05-07 13:24:49 +00001066 {0x8086, 0x2912, OK, "Intel", "ICH9DH", enable_flash_ich9},
1067 {0x8086, 0x2914, OK, "Intel", "ICH9DO", enable_flash_ich9},
Uwe Hermannb0039912009-05-07 13:24:49 +00001068 {0x8086, 0x2919, OK, "Intel", "ICH9M", enable_flash_ich9},
Uwe Hermann4179d292009-05-08 17:50:51 +00001069 {0x8086, 0x2917, OK, "Intel", "ICH9M-E", enable_flash_ich9},
1070 {0x8086, 0x2916, OK, "Intel", "ICH9R", enable_flash_ich9},
Carl-Daniel Hailfinger95baaad2009-08-21 17:26:13 +00001071 {0x8086, 0x2910, OK, "Intel", "ICH9 Engineering Sample", enable_flash_ich9},
Uwe Hermann4179d292009-05-08 17:50:51 +00001072 {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4},
1073 {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4},
1074 {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4},
1075 {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4},
Adam Jurkowskie4984102009-12-21 15:30:46 +00001076 {0x8086, 0x8119, OK, "Intel", "Poulsbo", enable_flash_poulsbo},
Luc Verhaegenaad7e672009-10-06 11:32:21 +00001077 {0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2},
Uwe Hermannb0039912009-05-07 13:24:49 +00001078 {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */
1079 {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */
Luc Verhaegen90e8e612009-05-26 09:48:28 +00001080 {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2},
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001081 {0x10de, 0x00e0, OK, "NVIDIA", "NForce3", enable_flash_nvidia_nforce2},
Uwe Hermanneac10162008-03-13 18:52:51 +00001082 /* Slave, should not be here, to fix known bug for A01. */
Uwe Hermannb0039912009-05-07 13:24:49 +00001083 {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804},
1084 {0x10de, 0x0260, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1085 {0x10de, 0x0261, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1086 {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1087 {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1088 {0x10de, 0x0360, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/
Carl-Daniel Hailfinger33d7b6a2010-05-22 07:27:16 +00001089 /* 10de:0361 is present in Tyan S2915 OEM systems, but not connected to
1090 * the flash chip. Instead, 10de:0364 is connected to the flash chip.
1091 * Until we have PCI device class matching or some fallback mechanism,
1092 * this is needed to get flashrom working on Tyan S2915 and maybe other
1093 * dual-MCP55 boards.
1094 */
1095#if 0
1096 {0x10de, 0x0361, NT, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1097#endif
Uwe Hermannb0039912009-05-07 13:24:49 +00001098 {0x10de, 0x0362, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1099 {0x10de, 0x0363, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1100 {0x10de, 0x0364, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1101 {0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1102 {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1103 {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001104 {0x10de, 0x03e0, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1105 {0x10de, 0x03e1, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1106 {0x10de, 0x03e2, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1107 {0x10de, 0x03e3, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1108 {0x10de, 0x0440, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1109 {0x10de, 0x0441, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1110 {0x10de, 0x0442, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1111 {0x10de, 0x0443, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1112 {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp6x_7x},
1113 {0x10de, 0x075c, NT, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x},
1114 {0x10de, 0x075d, NT, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x},
1115 {0x10de, 0x07d7, NT, "NVIDIA", "MCP73", enable_flash_mcp6x_7x},
1116 {0x10de, 0x0aac, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1117 {0x10de, 0x0aad, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1118 {0x10de, 0x0aae, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1119 {0x10de, 0x0aaf, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
Carl-Daniel Hailfinger6a0269e2009-11-15 17:20:21 +00001120 {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496},
1121 {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501},
1122 {0x1039, 0x5511, NT, "SiS", "5511", enable_flash_sis5511},
Luc Verhaegen9cce2f52010-01-10 15:01:08 +00001123 {0x1039, 0x5596, NT, "SiS", "5596", enable_flash_sis5511},
Carl-Daniel Hailfinger6a0269e2009-11-15 17:20:21 +00001124 {0x1039, 0x5571, NT, "SiS", "5571", enable_flash_sis530},
1125 {0x1039, 0x5591, NT, "SiS", "5591/5592", enable_flash_sis530},
1126 {0x1039, 0x5597, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530},
1127 {0x1039, 0x0530, NT, "SiS", "530", enable_flash_sis530},
1128 {0x1039, 0x5600, NT, "SiS", "600", enable_flash_sis530},
1129 {0x1039, 0x0620, NT, "SiS", "620", enable_flash_sis530},
1130 {0x1039, 0x0540, NT, "SiS", "540", enable_flash_sis540},
Luc Verhaegen9892ca62009-12-09 07:43:13 +00001131 {0x1039, 0x0630, NT, "SiS", "630", enable_flash_sis540},
1132 {0x1039, 0x0635, NT, "SiS", "635", enable_flash_sis540},
1133 {0x1039, 0x0640, NT, "SiS", "640", enable_flash_sis540},
1134 {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis540},
1135 {0x1039, 0x0646, NT, "SiS", "645DX", enable_flash_sis540},
1136 {0x1039, 0x0648, NT, "SiS", "648", enable_flash_sis540},
1137 {0x1039, 0x0650, NT, "SiS", "650", enable_flash_sis540},
1138 {0x1039, 0x0651, NT, "SiS", "651", enable_flash_sis540},
1139 {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis540},
David Borgf8ef5d92010-07-31 23:16:09 +00001140 {0x1039, 0x0661, OK, "SiS", "661", enable_flash_sis540},
Luc Verhaegen9892ca62009-12-09 07:43:13 +00001141 {0x1039, 0x0730, NT, "SiS", "730", enable_flash_sis540},
1142 {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis540},
1143 {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis540},
1144 {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis540},
Uwe Hermann17da61e2010-10-05 21:48:43 +00001145 {0x1039, 0x0741, OK, "SiS", "741", enable_flash_sis540},
Mattias Mattssone8388242010-09-11 15:25:48 +00001146 {0x1039, 0x0745, OK, "SiS", "745", enable_flash_sis540},
Luc Verhaegen9892ca62009-12-09 07:43:13 +00001147 {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540},
1148 {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540},
1149 {0x1039, 0x0755, NT, "SiS", "755", enable_flash_sis540},
Michael Karcher89bed6d2010-06-13 10:16:12 +00001150 /* VIA northbridges */
1151 {0x1106, 0x0585, NT, "VIA", "VT82C585VPX", via_no_byte_merge},
1152 {0x1106, 0x0595, NT, "VIA", "VT82C595", via_no_byte_merge},
1153 {0x1106, 0x0597, NT, "VIA", "VT82C597", via_no_byte_merge},
1154 {0x1106, 0x0691, NT, "VIA", "VT82C69x", via_no_byte_merge}, /* 691, 693a, 694t, 694x checked */
1155 {0x1106, 0x0601, NT, "VIA", "VT8601/VT8601A", via_no_byte_merge},
1156 {0x1106, 0x8601, NT, "VIA", "VT8601T", via_no_byte_merge},
1157 /* VIA southbridges */
Uwe Hermann4179d292009-05-08 17:50:51 +00001158 {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x},
1159 {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x},
Mateusz Murawskie6abef02009-06-18 12:42:46 +00001160 {0x1106, 0x3074, NT, "VIA", "VT8233", enable_flash_vt823x},
Raúl Sorianocd8404d2009-12-23 21:29:18 +00001161 {0x1106, 0x3147, OK, "VIA", "VT8233A", enable_flash_vt823x},
Uwe Hermann4179d292009-05-08 17:50:51 +00001162 {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x},
1163 {0x1106, 0x3227, OK, "VIA", "VT8237", enable_flash_vt823x},
1164 {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x},
1165 {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi},
Arjan Koers8dfea832009-06-15 00:03:37 +00001166 {0x1106, 0x8353, OK, "VIA", "VX800", enable_flash_vt8237s_spi},
John Schmergedec9cec2011-05-05 17:52:07 +00001167 {0x1106, 0x8409, OK, "VIA", "VX855", enable_flash_vt823x},
Uwe Hermann3e0774d2009-09-25 01:05:06 +00001168 {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111},
Uwe Hermann4179d292009-05-08 17:50:51 +00001169 {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111},
1170 {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111},
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001171#endif
Uwe Hermann05fab752009-05-16 23:42:17 +00001172 {},
Ollie Lhocbbf1252004-03-17 22:22:08 +00001173};
Ollie Lho761bf1b2004-03-20 16:46:10 +00001174
Uwe Hermanna7e05482007-05-09 10:17:44 +00001175int chipset_flash_enable(void)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001176{
Peter Huewe73f8ec82011-01-24 19:15:51 +00001177 struct pci_dev *dev = NULL;
Uwe Hermann372eeb52007-12-04 21:49:06 +00001178 int ret = -2; /* Nothing! */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001179 int i;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001180
Uwe Hermann372eeb52007-12-04 21:49:06 +00001181 /* Now let's try to find the chipset we have... */
Uwe Hermann05fab752009-05-16 23:42:17 +00001182 for (i = 0; chipset_enables[i].vendor_name != NULL; i++) {
1183 dev = pci_dev_find(chipset_enables[i].vendor_id,
1184 chipset_enables[i].device_id);
Michael Karcher89bed6d2010-06-13 10:16:12 +00001185 if (!dev)
1186 continue;
1187 if (ret != -2) {
1188 msg_pinfo("WARNING: unexpected second chipset match: "
Paul Menzelab6328f2010-10-08 11:03:02 +00001189 "\"%s %s\"\n"
1190 "ignoring, please report lspci and board URL "
1191 "to flashrom@flashrom.org\n"
Stefan Reinauerbf282b12011-03-29 21:41:41 +00001192 "with \'CHIPSET: your board name\' in the "
Paul Menzelab6328f2010-10-08 11:03:02 +00001193 "subject line.\n",
Michael Karcher89bed6d2010-06-13 10:16:12 +00001194 chipset_enables[i].vendor_name,
1195 chipset_enables[i].device_name);
1196 continue;
1197 }
Sean Nelson316a29f2010-05-07 20:09:04 +00001198 msg_pinfo("Found chipset \"%s %s\", enabling flash write... ",
Uwe Hermann05fab752009-05-16 23:42:17 +00001199 chipset_enables[i].vendor_name,
1200 chipset_enables[i].device_name);
Carl-Daniel Hailfingerf469c272010-05-22 07:31:50 +00001201 msg_pdbg("chipset PCI ID is %04x:%04x, ",
1202 chipset_enables[i].vendor_id,
1203 chipset_enables[i].device_id);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001204
Uwe Hermann05fab752009-05-16 23:42:17 +00001205 ret = chipset_enables[i].doit(dev,
1206 chipset_enables[i].device_name);
Michael Karcher89bed6d2010-06-13 10:16:12 +00001207 if (ret == NOT_DONE_YET) {
1208 ret = -2;
1209 msg_pinfo("OK - searching further chips.\n");
1210 } else if (ret < 0)
Sean Nelson316a29f2010-05-07 20:09:04 +00001211 msg_pinfo("FAILED!\n");
Michael Karcher89bed6d2010-06-13 10:16:12 +00001212 else if(ret == 0)
Sean Nelson316a29f2010-05-07 20:09:04 +00001213 msg_pinfo("OK.\n");
Michael Karchera4448d92010-07-22 18:04:15 +00001214 else if(ret == ERROR_NONFATAL)
1215 msg_pinfo("PROBLEMS, continuing anyway\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00001216 }
Michael Karcher89bed6d2010-06-13 10:16:12 +00001217
Sean Nelson316a29f2010-05-07 20:09:04 +00001218 msg_pinfo("This chipset supports the following protocols: %s.\n",
Uwe Hermann9899cad2009-06-28 21:47:57 +00001219 flashbuses_to_text(buses_supported));
Uwe Hermanna7e05482007-05-09 10:17:44 +00001220
1221 return ret;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001222}