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Ollie Lho184a4042005-11-26 21:55:36 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ollie Lho184a4042005-11-26 21:55:36 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Stefan Reinauer8fa64812009-08-12 09:27:45 +00005 * Copyright (C) 2005-2009 coresystems GmbH
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00007 * Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger
Adam Jurkowskie4984102009-12-21 15:30:46 +00008 * Copyright (C) 2009 Kontron Modular Computers GmbH
Ollie Lho184a4042005-11-26 21:55:36 +00009 *
Uwe Hermannd1107642007-08-29 17:52:32 +000010 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
Ollie Lho184a4042005-11-26 21:55:36 +000013 *
Uwe Hermannd1107642007-08-29 17:52:32 +000014 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24/*
25 * Contains the chipset specific flash enables.
Ollie Lho184a4042005-11-26 21:55:36 +000026 */
27
Lane Brooksd54958a2007-11-13 16:45:22 +000028#define _LARGEFILE64_SOURCE
29
Ollie Lhocbbf1252004-03-17 22:22:08 +000030#include <stdlib.h>
Uwe Hermanne8ba5382009-05-22 11:37:27 +000031#include <string.h>
Lane Brooksd54958a2007-11-13 16:45:22 +000032#include <sys/types.h>
33#include <sys/stat.h>
34#include <fcntl.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000035#include "flash.h"
Stefan Reinauer86de2832006-03-31 11:26:55 +000036
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000037#if defined(__i386__) || defined(__x86_64__)
38
Uwe Hermann372eeb52007-12-04 21:49:06 +000039static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
Luc Verhaegen6b141752007-05-20 16:16:13 +000040{
41 uint8_t tmp;
42
Uwe Hermann372eeb52007-12-04 21:49:06 +000043 /*
44 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
45 * 0xFFFE0000-0xFFFFFFFF ROM select enable.
46 */
Luc Verhaegen6b141752007-05-20 16:16:13 +000047 tmp = pci_read_byte(dev, 0x47);
48 tmp |= 0x46;
49 pci_write_byte(dev, 0x47, tmp);
50
51 return 0;
52}
53
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000054static int enable_flash_sis85c496(struct pci_dev *dev, const char *name)
55{
56 uint8_t tmp;
57
58 tmp = pci_read_byte(dev, 0xd0);
59 tmp |= 0xf8;
60 pci_write_byte(dev, 0xd0, tmp);
61
62 return 0;
63}
64
65static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name)
66{
67 uint8_t new, newer;
68
69 /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
70 /* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
71 new = pci_read_byte(dev, 0x40);
72 new &= (~0x04); /* No idea why we clear bit 2. */
73 new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */
74 pci_write_byte(dev, 0x40, new);
75 newer = pci_read_byte(dev, 0x40);
76 if (newer != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +000077 msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
78 msg_pinfo("Stuck at 0x%x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000079 return -1;
80 }
81 return 0;
82}
83
84static struct pci_dev *find_southbridge(uint16_t vendor, const char *name)
85{
86 struct pci_dev *sbdev;
87
88 sbdev = pci_dev_find_vendorclass(vendor, 0x0601);
89 if (!sbdev)
90 sbdev = pci_dev_find_vendorclass(vendor, 0x0680);
91 if (!sbdev)
92 sbdev = pci_dev_find_vendorclass(vendor, 0x0000);
93 if (!sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +000094 msg_perr("No southbridge found for %s!\n", name);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000095 if (sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +000096 msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n",
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000097 sbdev->vendor_id, sbdev->device_id,
98 sbdev->bus, sbdev->dev, sbdev->func);
99 return sbdev;
100}
101
102static int enable_flash_sis501(struct pci_dev *dev, const char *name)
103{
104 uint8_t tmp;
105 int ret = 0;
106 struct pci_dev *sbdev;
107
108 sbdev = find_southbridge(dev->vendor_id, name);
109 if (!sbdev)
110 return -1;
111
112 ret = enable_flash_sis_mapping(sbdev, name);
113
114 tmp = sio_read(0x22, 0x80);
115 tmp &= (~0x20);
116 tmp |= 0x4;
117 sio_write(0x22, 0x80, tmp);
118
119 tmp = sio_read(0x22, 0x70);
120 tmp &= (~0x20);
121 tmp |= 0x4;
122 sio_write(0x22, 0x70, tmp);
123
124 return ret;
125}
126
127static int enable_flash_sis5511(struct pci_dev *dev, const char *name)
128{
129 uint8_t tmp;
130 int ret = 0;
131 struct pci_dev *sbdev;
132
133 sbdev = find_southbridge(dev->vendor_id, name);
134 if (!sbdev)
135 return -1;
136
137 ret = enable_flash_sis_mapping(sbdev, name);
138
139 tmp = sio_read(0x22, 0x50);
140 tmp &= (~0x20);
141 tmp |= 0x4;
142 sio_write(0x22, 0x50, tmp);
143
144 return ret;
145}
146
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000147static int enable_flash_sis530(struct pci_dev *dev, const char *name)
148{
149 uint8_t new, newer;
150 int ret = 0;
151 struct pci_dev *sbdev;
152
153 sbdev = find_southbridge(dev->vendor_id, name);
154 if (!sbdev)
155 return -1;
156
157 ret = enable_flash_sis_mapping(sbdev, name);
158
159 new = pci_read_byte(sbdev, 0x45);
160 new &= (~0x20);
161 new |= 0x4;
162 pci_write_byte(sbdev, 0x45, new);
Luc Verhaegen9cce2f52010-01-10 15:01:08 +0000163 newer = pci_read_byte(sbdev, 0x45);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000164 if (newer != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000165 msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
166 msg_pinfo("Stuck at 0x%x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000167 ret = -1;
168 }
169
170 return ret;
171}
172
173static int enable_flash_sis540(struct pci_dev *dev, const char *name)
174{
175 uint8_t new, newer;
176 int ret = 0;
177 struct pci_dev *sbdev;
178
179 sbdev = find_southbridge(dev->vendor_id, name);
180 if (!sbdev)
181 return -1;
182
183 ret = enable_flash_sis_mapping(sbdev, name);
184
185 new = pci_read_byte(sbdev, 0x45);
186 new &= (~0x80);
187 new |= 0x40;
188 pci_write_byte(sbdev, 0x45, new);
Luc Verhaegen9cce2f52010-01-10 15:01:08 +0000189 newer = pci_read_byte(sbdev, 0x45);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000190 if (newer != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000191 msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
192 msg_pinfo("Stuck at 0x%x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000193 ret = -1;
194 }
195
196 return ret;
197}
198
Uwe Hermann987942d2006-11-07 11:16:21 +0000199/* Datasheet:
200 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
201 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
202 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
203 * - Order Number: 290562-001
204 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000205static int enable_flash_piix4(struct pci_dev *dev, const char *name)
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000206{
207 uint16_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000208 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000209
Maciej Pijankaa661e152009-12-08 17:26:24 +0000210 buses_supported = CHIP_BUSTYPE_PARALLEL;
211
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000212 old = pci_read_word(dev, xbcs);
213
214 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
Uwe Hermanna7e05482007-05-09 10:17:44 +0000215 * FFF00000-FFF7FFFF are forwarded to ISA).
Uwe Hermannc556d322008-10-28 11:50:05 +0000216 * Note: This bit is reserved on PIIX/PIIX3/MPIIX.
Uwe Hermanna7e05482007-05-09 10:17:44 +0000217 * Set bit 7: Extended BIOS Enable (PCI master accesses to
218 * FFF80000-FFFDFFFF are forwarded to ISA).
219 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
220 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
221 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
222 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
223 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
224 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
225 */
Uwe Hermannc556d322008-10-28 11:50:05 +0000226 if (dev->device_id == 0x122e || dev->device_id == 0x7000
227 || dev->device_id == 0x1234)
228 new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
Uwe Hermann87203452008-10-26 18:40:42 +0000229 else
230 new = old | 0x02c4;
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000231
232 if (new == old)
233 return 0;
234
235 pci_write_word(dev, xbcs, new);
236
237 if (pci_read_word(dev, xbcs) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000238 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000239 return -1;
240 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000241
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000242 return 0;
243}
244
Uwe Hermann372eeb52007-12-04 21:49:06 +0000245/*
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000246 * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet"
247 * http://download.intel.com/design/chipsets/datashts/30701303.pdf
Uwe Hermann372eeb52007-12-04 21:49:06 +0000248 */
249static int enable_flash_ich(struct pci_dev *dev, const char *name,
250 int bios_cntl)
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000251{
Ollie Lho184a4042005-11-26 21:55:36 +0000252 uint8_t old, new;
Stefan Reinauereb366472006-09-06 15:48:48 +0000253
Uwe Hermann372eeb52007-12-04 21:49:06 +0000254 /*
255 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
Uwe Hermanna7e05482007-05-09 10:17:44 +0000256 * just treating it as 8 bit wide seems to work fine in practice.
Stefan Reinauereb366472006-09-06 15:48:48 +0000257 */
Stefan Reinauer86de2832006-03-31 11:26:55 +0000258 old = pci_read_byte(dev, bios_cntl);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000259
Sean Nelson316a29f2010-05-07 20:09:04 +0000260 msg_pdbg("\nBIOS Lock Enable: %sabled, ",
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000261 (old & (1 << 1)) ? "en" : "dis");
Sean Nelson316a29f2010-05-07 20:09:04 +0000262 msg_pdbg("BIOS Write Enable: %sabled, ",
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000263 (old & (1 << 0)) ? "en" : "dis");
Sean Nelson316a29f2010-05-07 20:09:04 +0000264 msg_pdbg("BIOS_CNTL is 0x%x\n", old);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000265
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000266 new = old | 1;
267
268 if (new == old)
269 return 0;
270
Stefan Reinauer86de2832006-03-31 11:26:55 +0000271 pci_write_byte(dev, bios_cntl, new);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000272
Stefan Reinauer86de2832006-03-31 11:26:55 +0000273 if (pci_read_byte(dev, bios_cntl) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000274 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000275 return -1;
276 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000277
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000278 return 0;
279}
280
Uwe Hermann372eeb52007-12-04 21:49:06 +0000281static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000282{
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000283 /*
284 * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and
285 * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and
286 * FB_DEC_EN2.
287 */
Stefan Reinauereb366472006-09-06 15:48:48 +0000288 return enable_flash_ich(dev, name, 0x4e);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000289}
290
Uwe Hermann372eeb52007-12-04 21:49:06 +0000291static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000292{
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000293 uint32_t fwh_conf;
294 int i;
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000295 char *idsel = NULL;
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000296 int tmp;
297 int max_decode_fwh_idsel = 0;
298 int max_decode_fwh_decode = 0;
299 int contiguous = 1;
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000300
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000301 if (programmer_param)
302 idsel = strstr(programmer_param, "fwh_idsel=");
303
304 if (idsel) {
305 idsel += strlen("fwh_idsel=");
306 fwh_conf = (uint32_t)strtoul(idsel, NULL, 0);
307
308 /* FIXME: Need to undo this on shutdown. */
Sean Nelson316a29f2010-05-07 20:09:04 +0000309 msg_pinfo("\nSetting IDSEL=0x%x for top 16 MB", fwh_conf);
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000310 pci_write_long(dev, 0xd0, fwh_conf);
311 pci_write_word(dev, 0xd4, fwh_conf);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000312 /* FIXME: Decode settings are not changed. */
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000313 }
314
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000315 /* Ignore all legacy ranges below 1 MB.
316 * We currently only support flashing the chip which responds to
317 * IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations
318 * have to be adjusted.
319 */
320 /* FWH_SEL1 */
321 fwh_conf = pci_read_long(dev, 0xd0);
322 for (i = 7; i >= 0; i--) {
323 tmp = (fwh_conf >> (i * 4)) & 0xf;
Sean Nelson316a29f2010-05-07 20:09:04 +0000324 msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000325 (0x1ff8 + i) * 0x80000,
326 (0x1ff0 + i) * 0x80000,
327 tmp);
328 if ((tmp == 0) && contiguous) {
329 max_decode_fwh_idsel = (8 - i) * 0x80000;
330 } else {
331 contiguous = 0;
332 }
333 }
334 /* FWH_SEL2 */
335 fwh_conf = pci_read_word(dev, 0xd4);
336 for (i = 3; i >= 0; i--) {
337 tmp = (fwh_conf >> (i * 4)) & 0xf;
Sean Nelson316a29f2010-05-07 20:09:04 +0000338 msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000339 (0xff4 + i) * 0x100000,
340 (0xff0 + i) * 0x100000,
341 tmp);
342 if ((tmp == 0) && contiguous) {
343 max_decode_fwh_idsel = (8 - i) * 0x100000;
344 } else {
345 contiguous = 0;
346 }
347 }
348 contiguous = 1;
349 /* FWH_DEC_EN1 */
350 fwh_conf = pci_read_word(dev, 0xd8);
351 for (i = 7; i >= 0; i--) {
352 tmp = (fwh_conf >> (i + 0x8)) & 0x1;
Sean Nelson316a29f2010-05-07 20:09:04 +0000353 msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled",
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000354 (0x1ff8 + i) * 0x80000,
355 (0x1ff0 + i) * 0x80000,
356 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000357 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000358 max_decode_fwh_decode = (8 - i) * 0x80000;
359 } else {
360 contiguous = 0;
361 }
362 }
363 for (i = 3; i >= 0; i--) {
364 tmp = (fwh_conf >> i) & 0x1;
Sean Nelson316a29f2010-05-07 20:09:04 +0000365 msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled",
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000366 (0xff4 + i) * 0x100000,
367 (0xff0 + i) * 0x100000,
368 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000369 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000370 max_decode_fwh_decode = (8 - i) * 0x100000;
371 } else {
372 contiguous = 0;
373 }
374 }
375 max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode);
Sean Nelson316a29f2010-05-07 20:09:04 +0000376 msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000377
378 /* If we're called by enable_flash_ich_dc_spi, it will override
379 * buses_supported anyway.
380 */
381 buses_supported = CHIP_BUSTYPE_FWH;
Stefan Reinauereb366472006-09-06 15:48:48 +0000382 return enable_flash_ich(dev, name, 0xdc);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000383}
384
Adam Jurkowskie4984102009-12-21 15:30:46 +0000385static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
386{
387 uint16_t old, new;
388 int err;
389
390 if ((err = enable_flash_ich(dev, name, 0xd8)) != 0)
391 return err;
392
393 old = pci_read_byte(dev, 0xd9);
Sean Nelson316a29f2010-05-07 20:09:04 +0000394 msg_pdbg("BIOS Prefetch Enable: %sabled, ",
Adam Jurkowskie4984102009-12-21 15:30:46 +0000395 (old & 1) ? "en" : "dis");
396 new = old & ~1;
397
398 if (new != old)
399 pci_write_byte(dev, 0xd9, new);
400
401 return 0;
402}
403
404
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000405#define ICH_STRAP_RSVD 0x00
406#define ICH_STRAP_SPI 0x01
407#define ICH_STRAP_PCI 0x02
408#define ICH_STRAP_LPC 0x03
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000409
Uwe Hermann394131e2008-10-18 21:14:13 +0000410static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
411{
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000412 uint32_t mmio_base;
413
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000414 /* Do we really need no write enable? */
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000415 mmio_base = (pci_read_long(dev, 0xbc)) << 8;
Sean Nelson316a29f2010-05-07 20:09:04 +0000416 msg_pdbg("MMIO base at = 0x%x\n", mmio_base);
Stefan Reinauer0593f212009-01-26 01:10:48 +0000417 spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70);
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000418
Sean Nelson316a29f2010-05-07 20:09:04 +0000419 msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000420 mmio_readw(spibar + 0x6c));
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000421
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000422 /* Not sure if it speaks all these bus protocols. */
423 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000424 spi_controller = SPI_CONTROLLER_VIA;
Rudolf Marek0c2029f2009-02-01 18:40:50 +0000425 ich_init_opcodes();
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000426
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000427 return 0;
428}
429
Uwe Hermann394131e2008-10-18 21:14:13 +0000430static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
431 int ich_generation)
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000432{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000433 int ret, i;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000434 uint8_t old, new, bbs, buc;
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000435 uint16_t spibar_offset, tmp2;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000436 uint32_t tmp, gcs;
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000437 void *rcrb;
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000438 //TODO: These names are incorrect for EP80579. For that, the solution would look like the commented line
439 //static const char *straps_names[] = {"SPI", "reserved", "reserved", "LPC" };
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000440 static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" };
Uwe Hermann394131e2008-10-18 21:14:13 +0000441
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000442 /* Enable Flash Writes */
443 ret = enable_flash_ich_dc(dev, name);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000444
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000445 /* Get physical address of Root Complex Register Block */
446 tmp = pci_read_long(dev, 0xf0) & 0xffffc000;
Sean Nelson316a29f2010-05-07 20:09:04 +0000447 msg_pdbg("\nRoot Complex Register Block address = 0x%x\n", tmp);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000448
449 /* Map RCBA to virtual memory */
Stefan Reinauer0593f212009-01-26 01:10:48 +0000450 rcrb = physmap("ICH RCRB", tmp, 0x4000);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000451
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000452 gcs = mmio_readl(rcrb + 0x3410);
Sean Nelson316a29f2010-05-07 20:09:04 +0000453 msg_pdbg("GCS = 0x%x: ", gcs);
454 msg_pdbg("BIOS Interface Lock-Down: %sabled, ",
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000455 (gcs & 0x1) ? "en" : "dis");
456 bbs = (gcs >> 10) & 0x3;
Sean Nelson316a29f2010-05-07 20:09:04 +0000457 msg_pdbg("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000458
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000459 buc = mmio_readb(rcrb + 0x3414);
Sean Nelson316a29f2010-05-07 20:09:04 +0000460 msg_pdbg("Top Swap : %s\n",
Uwe Hermann394131e2008-10-18 21:14:13 +0000461 (buc & 1) ? "enabled (A16 inverted)" : "not enabled");
Stefan Reinauera9424d52008-06-27 16:28:34 +0000462
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000463 /* It seems the ICH7 does not support SPI and LPC chips at the same
464 * time. At least not with our current code. So we prevent searching
465 * on ICH7 when the southbridge is strapped to LPC
466 */
467
468 if (ich_generation == 7 && bbs == ICH_STRAP_LPC) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000469 buses_supported = CHIP_BUSTYPE_FWH;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000470 /* No further SPI initialization required */
471 return ret;
472 }
473
474 switch (ich_generation) {
475 case 7:
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000476 buses_supported = CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000477 spi_controller = SPI_CONTROLLER_ICH7;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000478 spibar_offset = 0x3020;
479 break;
480 case 8:
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000481 buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000482 spi_controller = SPI_CONTROLLER_ICH9;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000483 spibar_offset = 0x3020;
484 break;
485 case 9:
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000486 case 10:
Uwe Hermann394131e2008-10-18 21:14:13 +0000487 default: /* Future version might behave the same */
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000488 buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000489 spi_controller = SPI_CONTROLLER_ICH9;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000490 spibar_offset = 0x3800;
491 break;
492 }
493
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000494 /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
Sean Nelson316a29f2010-05-07 20:09:04 +0000495 msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000496
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000497 /* Assign Virtual Address */
Uwe Hermann394131e2008-10-18 21:14:13 +0000498 spibar = rcrb + spibar_offset;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000499
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000500 switch (spi_controller) {
501 case SPI_CONTROLLER_ICH7:
Sean Nelson316a29f2010-05-07 20:09:04 +0000502 msg_pdbg("0x00: 0x%04x (SPIS)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000503 mmio_readw(spibar + 0));
Sean Nelson316a29f2010-05-07 20:09:04 +0000504 msg_pdbg("0x02: 0x%04x (SPIC)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000505 mmio_readw(spibar + 2));
Sean Nelson316a29f2010-05-07 20:09:04 +0000506 msg_pdbg("0x04: 0x%08x (SPIA)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000507 mmio_readl(spibar + 4));
Uwe Hermann394131e2008-10-18 21:14:13 +0000508 for (i = 0; i < 8; i++) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000509 int offs;
510 offs = 8 + (i * 8);
Sean Nelson316a29f2010-05-07 20:09:04 +0000511 msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs,
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000512 mmio_readl(spibar + offs), i);
Sean Nelson316a29f2010-05-07 20:09:04 +0000513 msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000514 mmio_readl(spibar + offs + 4), i);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000515 }
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000516 ichspi_bbar = mmio_readl(spibar + 0x50);
Sean Nelson316a29f2010-05-07 20:09:04 +0000517 msg_pdbg("0x50: 0x%08x (BBAR)\n",
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000518 ichspi_bbar);
Sean Nelson316a29f2010-05-07 20:09:04 +0000519 msg_pdbg("0x54: 0x%04x (PREOP)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000520 mmio_readw(spibar + 0x54));
Sean Nelson316a29f2010-05-07 20:09:04 +0000521 msg_pdbg("0x56: 0x%04x (OPTYPE)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000522 mmio_readw(spibar + 0x56));
Sean Nelson316a29f2010-05-07 20:09:04 +0000523 msg_pdbg("0x58: 0x%08x (OPMENU)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000524 mmio_readl(spibar + 0x58));
Sean Nelson316a29f2010-05-07 20:09:04 +0000525 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000526 mmio_readl(spibar + 0x5c));
Uwe Hermann394131e2008-10-18 21:14:13 +0000527 for (i = 0; i < 4; i++) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000528 int offs;
529 offs = 0x60 + (i * 4);
Sean Nelson316a29f2010-05-07 20:09:04 +0000530 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000531 mmio_readl(spibar + offs), i);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000532 }
Sean Nelson316a29f2010-05-07 20:09:04 +0000533 msg_pdbg("\n");
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000534 if (mmio_readw(spibar) & (1 << 15)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000535 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000536 ichspi_lock = 1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000537 }
FENG yu ningf041e9b2008-12-15 02:32:11 +0000538 ich_init_opcodes();
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000539 break;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000540 case SPI_CONTROLLER_ICH9:
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000541 tmp2 = mmio_readw(spibar + 4);
Sean Nelson316a29f2010-05-07 20:09:04 +0000542 msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2);
543 msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1));
544 msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1);
545 msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1);
546 msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1);
547 msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3);
548 msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1);
549 msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1);
550 msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1);
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000551
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000552 tmp = mmio_readl(spibar + 0x50);
Sean Nelson316a29f2010-05-07 20:09:04 +0000553 msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp);
554 msg_pdbg("BMWAG %i, ", (tmp >> 24) & 0xff);
555 msg_pdbg("BMRAG %i, ", (tmp >> 16) & 0xff);
556 msg_pdbg("BRWA %i, ", (tmp >> 8) & 0xff);
557 msg_pdbg("BRRA %i\n", (tmp >> 0) & 0xff);
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000558
Sean Nelson316a29f2010-05-07 20:09:04 +0000559 msg_pdbg("0x54: 0x%08x (FREG0)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000560 mmio_readl(spibar + 0x54));
Sean Nelson316a29f2010-05-07 20:09:04 +0000561 msg_pdbg("0x58: 0x%08x (FREG1)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000562 mmio_readl(spibar + 0x58));
Sean Nelson316a29f2010-05-07 20:09:04 +0000563 msg_pdbg("0x5C: 0x%08x (FREG2)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000564 mmio_readl(spibar + 0x5C));
Sean Nelson316a29f2010-05-07 20:09:04 +0000565 msg_pdbg("0x60: 0x%08x (FREG3)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000566 mmio_readl(spibar + 0x60));
Sean Nelson316a29f2010-05-07 20:09:04 +0000567 msg_pdbg("0x64: 0x%08x (FREG4)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000568 mmio_readl(spibar + 0x64));
Sean Nelson316a29f2010-05-07 20:09:04 +0000569 msg_pdbg("0x74: 0x%08x (PR0)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000570 mmio_readl(spibar + 0x74));
Sean Nelson316a29f2010-05-07 20:09:04 +0000571 msg_pdbg("0x78: 0x%08x (PR1)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000572 mmio_readl(spibar + 0x78));
Sean Nelson316a29f2010-05-07 20:09:04 +0000573 msg_pdbg("0x7C: 0x%08x (PR2)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000574 mmio_readl(spibar + 0x7C));
Sean Nelson316a29f2010-05-07 20:09:04 +0000575 msg_pdbg("0x80: 0x%08x (PR3)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000576 mmio_readl(spibar + 0x80));
Sean Nelson316a29f2010-05-07 20:09:04 +0000577 msg_pdbg("0x84: 0x%08x (PR4)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000578 mmio_readl(spibar + 0x84));
Sean Nelson316a29f2010-05-07 20:09:04 +0000579 msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000580 mmio_readl(spibar + 0x90));
Sean Nelson316a29f2010-05-07 20:09:04 +0000581 msg_pdbg("0x94: 0x%04x (PREOP)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000582 mmio_readw(spibar + 0x94));
Sean Nelson316a29f2010-05-07 20:09:04 +0000583 msg_pdbg("0x96: 0x%04x (OPTYPE)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000584 mmio_readw(spibar + 0x96));
Sean Nelson316a29f2010-05-07 20:09:04 +0000585 msg_pdbg("0x98: 0x%08x (OPMENU)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000586 mmio_readl(spibar + 0x98));
Sean Nelson316a29f2010-05-07 20:09:04 +0000587 msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000588 mmio_readl(spibar + 0x9C));
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000589 ichspi_bbar = mmio_readl(spibar + 0xA0);
Sean Nelson316a29f2010-05-07 20:09:04 +0000590 msg_pdbg("0xA0: 0x%08x (BBAR)\n",
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000591 ichspi_bbar);
Sean Nelson316a29f2010-05-07 20:09:04 +0000592 msg_pdbg("0xB0: 0x%08x (FDOC)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000593 mmio_readl(spibar + 0xB0));
FENG yu ning37179b82009-01-18 06:39:32 +0000594 if (tmp2 & (1 << 15)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000595 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
FENG yu ning37179b82009-01-18 06:39:32 +0000596 ichspi_lock = 1;
597 }
Peter Stugee8a3e4c2008-12-22 14:12:08 +0000598 ich_init_opcodes();
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000599 break;
600 default:
601 /* Nothing */
602 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000603 }
604
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000605 old = pci_read_byte(dev, 0xdc);
Sean Nelson316a29f2010-05-07 20:09:04 +0000606 msg_pdbg("SPI Read Configuration: ");
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000607 new = (old >> 2) & 0x3;
608 switch (new) {
609 case 0:
610 case 1:
611 case 2:
Sean Nelson316a29f2010-05-07 20:09:04 +0000612 msg_pdbg("prefetching %sabled, caching %sabled, ",
Uwe Hermann394131e2008-10-18 21:14:13 +0000613 (new & 0x2) ? "en" : "dis",
614 (new & 0x1) ? "dis" : "en");
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000615 break;
616 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000617 msg_pdbg("invalid prefetching/caching settings, ");
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000618 break;
619 }
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000620
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000621 return ret;
622}
Stefan Reinauera9424d52008-06-27 16:28:34 +0000623
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000624static int enable_flash_ich7(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000625{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000626 return enable_flash_ich_dc_spi(dev, name, 7);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000627}
628
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000629static int enable_flash_ich8(struct pci_dev *dev, const char *name)
630{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000631 return enable_flash_ich_dc_spi(dev, name, 8);
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000632}
633
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000634static int enable_flash_ich9(struct pci_dev *dev, const char *name)
635{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000636 return enable_flash_ich_dc_spi(dev, name, 9);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000637}
638
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000639static int enable_flash_ich10(struct pci_dev *dev, const char *name)
640{
641 return enable_flash_ich_dc_spi(dev, name, 10);
642}
643
Uwe Hermann372eeb52007-12-04 21:49:06 +0000644static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000645{
Ollie Lho184a4042005-11-26 21:55:36 +0000646 uint8_t val;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000647
Uwe Hermann394131e2008-10-18 21:14:13 +0000648 /* enable ROM decode range (1MB) FFC00000 - FFFFFFFF */
Bari Ari9477c4e2008-04-29 13:46:38 +0000649 pci_write_byte(dev, 0x41, 0x7f);
650
Uwe Hermannffec5f32007-08-23 16:08:21 +0000651 /* ROM write enable */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000652 val = pci_read_byte(dev, 0x40);
653 val |= 0x10;
654 pci_write_byte(dev, 0x40, val);
655
656 if (pci_read_byte(dev, 0x40) != val) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000657 msg_pinfo("\nWARNING: Failed to enable flash write on \"%s\"\n",
Uwe Hermanna7e05482007-05-09 10:17:44 +0000658 name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000659 return -1;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000660 }
Luc Verhaegen6382b442007-03-02 22:16:38 +0000661
Luc Verhaegen73d21192009-12-23 00:54:26 +0000662 if (dev->device_id == 0x3227) { /* VT8237R */
663 /* All memory cycles, not just ROM ones, go to LPC. */
664 val = pci_read_byte(dev, 0x59);
665 val &= ~0x80;
666 pci_write_byte(dev, 0x59, val);
667 }
668
Uwe Hermanna7e05482007-05-09 10:17:44 +0000669 return 0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000670}
671
Uwe Hermann372eeb52007-12-04 21:49:06 +0000672static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000673{
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000674 uint8_t reg8;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000675
Uwe Hermann394131e2008-10-18 21:14:13 +0000676#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
677#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000678#define CS5530_RESET_CONTROL_REG 0x44 /* F0 index 0x44 */
679#define CS5530_USB_SHADOW_REG 0x43 /* F0 index 0x43 */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000680
Uwe Hermann394131e2008-10-18 21:14:13 +0000681#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
682#define ROM_WRITE_ENABLE (1 << 1)
683#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
684#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000685#define CS5530_ISA_MASTER (1 << 7)
686#define CS5530_ENABLE_SA2320 (1 << 2)
687#define CS5530_ENABLE_SA20 (1 << 6)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000688
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000689 buses_supported = CHIP_BUSTYPE_PARALLEL;
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000690 /* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
691 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000692 * FIXME: Should we really touch the low mapping below 1 MB? Flashrom
693 * ignores that region completely.
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000694 * Make the configured ROM areas writable.
695 */
696 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
697 reg8 |= LOWER_ROM_ADDRESS_RANGE;
698 reg8 |= UPPER_ROM_ADDRESS_RANGE;
699 reg8 |= ROM_WRITE_ENABLE;
700 pci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000701
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000702 /* Set positive decode on ROM. */
703 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
704 reg8 |= BIOS_ROM_POSITIVE_DECODE;
705 pci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000706
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000707 reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG);
708 if (reg8 & CS5530_ISA_MASTER) {
709 /* We have A0-A23 available. */
710 max_rom_decode.parallel = 16 * 1024 * 1024;
711 } else {
712 reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG);
713 if (reg8 & CS5530_ENABLE_SA2320) {
714 /* We have A0-19, A20-A23 available. */
715 max_rom_decode.parallel = 16 * 1024 * 1024;
716 } else if (reg8 & CS5530_ENABLE_SA20) {
717 /* We have A0-19, A20 available. */
718 max_rom_decode.parallel = 2 * 1024 * 1024;
719 } else {
720 /* A20 and above are not active. */
721 max_rom_decode.parallel = 1024 * 1024;
722 }
723 }
724
Ollie Lhocbbf1252004-03-17 22:22:08 +0000725 return 0;
726}
727
Mart Raudseppe1344da2008-02-08 10:10:57 +0000728/**
729 * Geode systems write protect the BIOS via RCONFs (cache settings similar
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000730 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
Mart Raudseppe1344da2008-02-08 10:10:57 +0000731 *
732 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
733 * To enable write to NOR Boot flash for the benefit of systems that have such
734 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
Mart Raudseppe1344da2008-02-08 10:10:57 +0000735 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000736static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
Lane Brooksd54958a2007-11-13 16:45:22 +0000737{
Uwe Hermann394131e2008-10-18 21:14:13 +0000738#define MSR_RCONF_DEFAULT 0x1808
739#define MSR_NORF_CTL 0x51400018
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000740
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000741 msr_t msr;
Lane Brooksd54958a2007-11-13 16:45:22 +0000742
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000743 /* Geode only has a single core */
744 if (setup_cpu_msr(0))
Lane Brooksd54958a2007-11-13 16:45:22 +0000745 return -1;
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000746
747 msr = rdmsr(MSR_RCONF_DEFAULT);
748 if ((msr.hi >> 24) != 0x22) {
749 msr.hi &= 0xfbffffff;
750 wrmsr(MSR_RCONF_DEFAULT, msr);
Lane Brooksd54958a2007-11-13 16:45:22 +0000751 }
Mart Raudseppe1344da2008-02-08 10:10:57 +0000752
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000753 msr = rdmsr(MSR_NORF_CTL);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000754 /* Raise WE_CS3 bit. */
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000755 msr.lo |= 0x08;
756 wrmsr(MSR_NORF_CTL, msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000757
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000758 cleanup_cpu_msr();
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000759
Uwe Hermann394131e2008-10-18 21:14:13 +0000760#undef MSR_RCONF_DEFAULT
761#undef MSR_NORF_CTL
Lane Brooksd54958a2007-11-13 16:45:22 +0000762 return 0;
763}
764
Uwe Hermann372eeb52007-12-04 21:49:06 +0000765static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000766{
Ollie Lho184a4042005-11-26 21:55:36 +0000767 uint8_t new;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000768
Ollie Lhocbbf1252004-03-17 22:22:08 +0000769 pci_write_byte(dev, 0x52, 0xee);
770
771 new = pci_read_byte(dev, 0x52);
772
773 if (new != 0xee) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000774 msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000775 return -1;
776 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000777
Ollie Lhocbbf1252004-03-17 22:22:08 +0000778 return 0;
779}
780
Uwe Hermann190f8492008-10-25 18:03:50 +0000781/* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000782static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000783{
Ollie Lho184a4042005-11-26 21:55:36 +0000784 uint8_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000785
Uwe Hermann372eeb52007-12-04 21:49:06 +0000786 /* Enable decoding at 0xffb00000 to 0xffffffff. */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000787 old = pci_read_byte(dev, 0x43);
Ollie Lhod11f3612004-12-07 17:19:04 +0000788 new = old | 0xC0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000789 if (new != old) {
790 pci_write_byte(dev, 0x43, new);
791 if (pci_read_byte(dev, 0x43) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000792 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000793 }
794 }
795
Uwe Hermann190f8492008-10-25 18:03:50 +0000796 /* Enable 'ROM write' bit. */
Ollie Lho761bf1b2004-03-20 16:46:10 +0000797 old = pci_read_byte(dev, 0x40);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000798 new = old | 0x01;
799 if (new == old)
800 return 0;
801 pci_write_byte(dev, 0x40, new);
802
803 if (pci_read_byte(dev, 0x40) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000804 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000805 return -1;
806 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000807
Ollie Lhocbbf1252004-03-17 22:22:08 +0000808 return 0;
809}
810
Marc Jones3af487d2008-10-15 17:50:29 +0000811static int enable_flash_sb600(struct pci_dev *dev, const char *name)
812{
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000813 uint32_t tmp, prot;
Marc Jones3af487d2008-10-15 17:50:29 +0000814 uint8_t reg;
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000815 struct pci_dev *smbus_dev;
816 int has_spi = 1;
Marc Jones3af487d2008-10-15 17:50:29 +0000817
Jason Wanga3f04be2008-11-28 21:36:51 +0000818 /* Clear ROM protect 0-3. */
819 for (reg = 0x50; reg < 0x60; reg += 4) {
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000820 prot = pci_read_long(dev, reg);
821 /* No protection flags for this region?*/
822 if ((prot & 0x3) == 0)
823 continue;
Sean Nelson316a29f2010-05-07 20:09:04 +0000824 msg_pinfo("SB600 %s%sprotected from %u to %u\n",
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000825 (prot & 0x1) ? "write " : "",
826 (prot & 0x2) ? "read " : "",
827 (prot & 0xfffffc00),
828 (prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
829 prot &= 0xfffffffc;
830 pci_write_byte(dev, reg, prot);
831 prot = pci_read_long(dev, reg);
Carl-Daniel Hailfinger9bb88ac2009-05-06 13:51:44 +0000832 if (prot & 0x3)
Sean Nelson316a29f2010-05-07 20:09:04 +0000833 msg_perr("SB600 %s%sunprotect failed from %u to %u\n",
Carl-Daniel Hailfinger9bb88ac2009-05-06 13:51:44 +0000834 (prot & 0x1) ? "write " : "",
835 (prot & 0x2) ? "read " : "",
836 (prot & 0xfffffc00),
837 (prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
Jason Wanga3f04be2008-11-28 21:36:51 +0000838 }
839
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000840 /* Read SPI_BaseAddr */
841 tmp = pci_read_long(dev, 0xa0);
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000842 tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */
Sean Nelson316a29f2010-05-07 20:09:04 +0000843 msg_pdbg("SPI base address is at 0x%x\n", tmp);
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000844
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000845 /* If the BAR has address 0, it is unlikely SPI is used. */
846 if (!tmp)
847 has_spi = 0;
848
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000849 if (has_spi) {
850 /* Physical memory has to be mapped at page (4k) boundaries. */
851 sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000,
852 0x1000);
853 /* The low bits of the SPI base address are used as offset into
854 * the mapped page.
855 */
856 sb600_spibar += tmp & 0xfff;
857
858 tmp = pci_read_long(dev, 0xa0);
Sean Nelson316a29f2010-05-07 20:09:04 +0000859 msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, "
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000860 "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1,
861 (tmp & 0x4) >> 2);
862 tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2;
Sean Nelson316a29f2010-05-07 20:09:04 +0000863 msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp);
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000864
865 tmp = pci_read_byte(dev, 0xbb);
Sean Nelson316a29f2010-05-07 20:09:04 +0000866 msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n",
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000867 tmp & 0x1, (tmp & 0x20) >> 5);
868 tmp = mmio_readl(sb600_spibar);
Sean Nelson316a29f2010-05-07 20:09:04 +0000869 msg_pdbg("SpiArbEnable=%i, SpiAccessMacRomEn=%i, "
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000870 "SpiHostAccessRomEn=%i, ArbWaitCount=%i, "
871 "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n",
872 (tmp >> 19) & 0x1, (tmp >> 22) & 0x1,
873 (tmp >> 23) & 0x1, (tmp >> 24) & 0x7,
874 (tmp >> 27) & 0x1, (tmp >> 28) & 0x1);
875 }
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000876
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000877 /* Look for the SMBus device. */
878 smbus_dev = pci_dev_find(0x1002, 0x4385);
879
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000880 if (has_spi && !smbus_dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000881 msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n");
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000882 has_spi = 0;
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000883 }
884 if (has_spi) {
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000885 /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */
886 /* GPIO11/SPI_DO and GPIO12/SPI_DI status */
887 reg = pci_read_byte(smbus_dev, 0xAB);
888 reg &= 0xC0;
Sean Nelson316a29f2010-05-07 20:09:04 +0000889 msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO");
890 msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI");
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000891 if (reg != 0x00)
892 has_spi = 0;
893 /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */
894 reg = pci_read_byte(smbus_dev, 0x83);
895 reg &= 0xC0;
Sean Nelson316a29f2010-05-07 20:09:04 +0000896 msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD");
897 msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000898 /* SPI_HOLD is not used on all boards, filter it out. */
899 if ((reg & 0x80) != 0x00)
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000900 has_spi = 0;
901 /* GPIO47/SPI_CLK status */
902 reg = pci_read_byte(smbus_dev, 0xA7);
903 reg &= 0x40;
Sean Nelson316a29f2010-05-07 20:09:04 +0000904 msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK");
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000905 if (reg != 0x00)
906 has_spi = 0;
907 }
908
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000909 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH;
910 if (has_spi) {
911 buses_supported |= CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000912 spi_controller = SPI_CONTROLLER_SB600;
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000913 }
Jason Wanga3f04be2008-11-28 21:36:51 +0000914
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000915 /* Read ROM strap override register. */
916 OUTB(0x8f, 0xcd6);
917 reg = INB(0xcd7);
918 reg &= 0x0e;
Sean Nelson316a29f2010-05-07 20:09:04 +0000919 msg_pdbg("ROM strap override is %sactive", (reg & 0x02) ? "" : "not ");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000920 if (reg & 0x02) {
921 switch ((reg & 0x0c) >> 2) {
922 case 0x00:
Sean Nelson316a29f2010-05-07 20:09:04 +0000923 msg_pdbg(": LPC");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000924 break;
925 case 0x01:
Sean Nelson316a29f2010-05-07 20:09:04 +0000926 msg_pdbg(": PCI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000927 break;
928 case 0x02:
Sean Nelson316a29f2010-05-07 20:09:04 +0000929 msg_pdbg(": FWH");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000930 break;
931 case 0x03:
Sean Nelson316a29f2010-05-07 20:09:04 +0000932 msg_pdbg(": SPI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000933 break;
934 }
935 }
Sean Nelson316a29f2010-05-07 20:09:04 +0000936 msg_pdbg("\n");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000937
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000938 /* Force enable SPI ROM in SB600 PM register.
939 * If we enable SPI ROM here, we have to disable it after we leave.
Zheng Bao284a6002009-05-04 22:33:50 +0000940 * But how can we know which ROM we are going to handle? So we have
941 * to trade off. We only access LPC ROM if we boot via LPC ROM. And
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000942 * only SPI ROM if we boot via SPI ROM. If you want to access SPI on
943 * boards with LPC straps, you have to use the code below.
Zheng Bao284a6002009-05-04 22:33:50 +0000944 */
945 /*
Jason Wanga3f04be2008-11-28 21:36:51 +0000946 OUTB(0x8f, 0xcd6);
947 OUTB(0x0e, 0xcd7);
Zheng Bao284a6002009-05-04 22:33:50 +0000948 */
Marc Jones3af487d2008-10-15 17:50:29 +0000949
950 return 0;
951}
952
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000953static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name)
954{
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000955 uint8_t tmp;
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000956
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000957 pci_write_byte(dev, 0x92, 0);
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000958
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000959 tmp = pci_read_byte(dev, 0x6d);
960 tmp |= 0x01;
961 pci_write_byte(dev, 0x6d, tmp);
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000962
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000963 return 0;
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000964}
965
Uwe Hermann372eeb52007-12-04 21:49:06 +0000966static int enable_flash_ck804(struct pci_dev *dev, const char *name)
Yinghai Lu952dfce2005-07-06 17:13:46 +0000967{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000968 uint8_t old, new;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000969
Uwe Hermanna7e05482007-05-09 10:17:44 +0000970 old = pci_read_byte(dev, 0x88);
971 new = old | 0xc0;
972 if (new != old) {
973 pci_write_byte(dev, 0x88, new);
974 if (pci_read_byte(dev, 0x88) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000975 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000976 }
977 }
Yinghai Lu952dfce2005-07-06 17:13:46 +0000978
Uwe Hermanna7e05482007-05-09 10:17:44 +0000979 old = pci_read_byte(dev, 0x6d);
980 new = old | 0x01;
981 if (new == old)
982 return 0;
983 pci_write_byte(dev, 0x6d, new);
984
985 if (pci_read_byte(dev, 0x6d) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000986 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000987 return -1;
988 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000989
Uwe Hermanna7e05482007-05-09 10:17:44 +0000990 return 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000991}
992
Uwe Hermann372eeb52007-12-04 21:49:06 +0000993/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
994static int enable_flash_sb400(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000995{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000996 uint8_t tmp;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000997 struct pci_dev *smbusdev;
998
Uwe Hermann372eeb52007-12-04 21:49:06 +0000999 /* Look for the SMBus device. */
Carl-Daniel Hailfingerf6e3efb2009-05-06 00:35:31 +00001000 smbusdev = pci_dev_find(0x1002, 0x4372);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001001
Uwe Hermanna7e05482007-05-09 10:17:44 +00001002 if (!smbusdev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001003 msg_perr("ERROR: SMBus device not found. Aborting.\n");
Stefan Reinauer86de2832006-03-31 11:26:55 +00001004 exit(1);
1005 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001006
Uwe Hermann372eeb52007-12-04 21:49:06 +00001007 /* Enable some SMBus stuff. */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001008 tmp = pci_read_byte(smbusdev, 0x79);
1009 tmp |= 0x01;
Stefan Reinauer86de2832006-03-31 11:26:55 +00001010 pci_write_byte(smbusdev, 0x79, tmp);
1011
Uwe Hermann372eeb52007-12-04 21:49:06 +00001012 /* Change southbridge. */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001013 tmp = pci_read_byte(dev, 0x48);
1014 tmp |= 0x21;
Stefan Reinauer86de2832006-03-31 11:26:55 +00001015 pci_write_byte(dev, 0x48, tmp);
1016
Uwe Hermann372eeb52007-12-04 21:49:06 +00001017 /* Now become a bit silly. */
Andriy Gapon65c1b862008-05-22 13:22:45 +00001018 tmp = INB(0xc6f);
1019 OUTB(tmp, 0xeb);
1020 OUTB(tmp, 0xeb);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001021 tmp |= 0x40;
Andriy Gapon65c1b862008-05-22 13:22:45 +00001022 OUTB(tmp, 0xc6f);
1023 OUTB(tmp, 0xeb);
1024 OUTB(tmp, 0xeb);
Stefan Reinauer86de2832006-03-31 11:26:55 +00001025
1026 return 0;
1027}
1028
Uwe Hermann372eeb52007-12-04 21:49:06 +00001029static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
Yinghai Luca782972007-01-22 20:21:17 +00001030{
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001031 uint8_t old, new, val;
1032 uint16_t wordval;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001033
Uwe Hermann372eeb52007-12-04 21:49:06 +00001034 /* Set the 0-16 MB enable bits. */
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001035 val = pci_read_byte(dev, 0x88);
1036 val |= 0xff; /* 256K */
1037 pci_write_byte(dev, 0x88, val);
1038 val = pci_read_byte(dev, 0x8c);
1039 val |= 0xff; /* 1M */
1040 pci_write_byte(dev, 0x8c, val);
1041 wordval = pci_read_word(dev, 0x90);
1042 wordval |= 0x7fff; /* 16M */
1043 pci_write_word(dev, 0x90, wordval);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001044
Uwe Hermanna7e05482007-05-09 10:17:44 +00001045 old = pci_read_byte(dev, 0x6d);
1046 new = old | 0x01;
1047 if (new == old)
1048 return 0;
1049 pci_write_byte(dev, 0x6d, new);
Yinghai Luca782972007-01-22 20:21:17 +00001050
Uwe Hermanna7e05482007-05-09 10:17:44 +00001051 if (pci_read_byte(dev, 0x6d) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001052 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001053 return -1;
1054 }
Yinghai Luca782972007-01-22 20:21:17 +00001055
1056 return 0;
Yinghai Luca782972007-01-22 20:21:17 +00001057}
1058
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001059/* This is a shot in the dark. Even if the code is totally bogus for some
1060 * chipsets, users will at least start to send in reports.
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001061 */
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001062static int enable_flash_mcp6x_7x_common(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001063{
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001064 int ret = 0;
Michael Karchercfa674f2010-02-25 11:38:23 +00001065 uint8_t val;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001066 uint16_t status;
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001067 char *busname;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001068 uint32_t mcp_spibaraddr;
1069 void *mcp_spibar;
1070 struct pci_dev *smbusdev;
1071
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001072 msg_pinfo("This chipset is not really supported yet. Guesswork...\n");
1073
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001074 /* dev is the ISA bridge. No idea what the stuff below does. */
Michael Karchercfa674f2010-02-25 11:38:23 +00001075 val = pci_read_byte(dev, 0x8a);
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001076 msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 "
Michael Karchercfa674f2010-02-25 11:38:23 +00001077 "is %i\n", val, (val >> 6) & 0x1, (val >> 5) & 0x1);
1078 switch ((val >> 5) & 0x3) {
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001079 case 0x0:
1080 buses_supported = CHIP_BUSTYPE_LPC;
1081 break;
1082 case 0x2:
1083 buses_supported = CHIP_BUSTYPE_SPI;
1084 break;
1085 default:
1086 buses_supported = CHIP_BUSTYPE_UNKNOWN;
1087 break;
1088 }
1089 busname = flashbuses_to_text(buses_supported);
1090 msg_pdbg("Guessed flash bus type is %s\n", busname);
1091 free(busname);
1092
1093 /* Force enable SPI and disable LPC? Not a good idea. */
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001094#if 0
Michael Karchercfa674f2010-02-25 11:38:23 +00001095 val |= (1 << 6);
1096 val &= ~(1 << 5);
1097 pci_write_byte(dev, 0x8a, val);
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001098#endif
1099
1100 /* Look for the SMBus device (SMBus PCI class) */
1101 smbusdev = pci_dev_find_vendorclass(0x10de, 0x0c05);
1102 if (!smbusdev) {
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001103 if (buses_supported & CHIP_BUSTYPE_SPI) {
1104 msg_perr("ERROR: SMBus device not found. Not enabling "
1105 "SPI.\n");
1106 buses_supported &= ~CHIP_BUSTYPE_SPI;
1107 ret = 1;
1108 } else {
1109 msg_pinfo("Odd. SMBus device not found.\n");
1110 }
1111 goto out_msg;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001112 }
1113 msg_pdbg("Found SMBus device %04x:%04x at %02x:%02x:%01x\n",
1114 smbusdev->vendor_id, smbusdev->device_id,
1115 smbusdev->bus, smbusdev->dev, smbusdev->func);
1116
1117 /* Locate the BAR where the SPI interface lives. */
1118 mcp_spibaraddr = pci_read_long(smbusdev, 0x74);
1119 msg_pdbg("SPI BAR is at 0x%08x, ", mcp_spibaraddr);
1120 /* We hope this has native alignment. We know the SPI interface (well,
1121 * a set of GPIOs that is connected to SPI flash) is at offset 0x530,
1122 * so we expect a size of at least 0x800. Clear the lower bits.
1123 * It is entirely possible that the BAR is 64k big and the low bits are
1124 * reserved for an entirely different purpose.
1125 */
1126 mcp_spibaraddr &= ~0x7ff;
1127 msg_pdbg("after clearing low bits BAR is at 0x%08x\n", mcp_spibaraddr);
1128
1129 /* Accessing a NULL pointer BAR is evil. Don't do it. */
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001130 if (mcp_spibaraddr && (buses_supported == CHIP_BUSTYPE_SPI)) {
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001131 /* Map the BAR. Bytewise/wordwise access at 0x530 and 0x540. */
1132 mcp_spibar = physmap("MCP67 SPI", mcp_spibaraddr, 0x544);
1133
1134/* Guessed. If this is correct, migrate to a separate MCP67 SPI driver. */
1135#define MCP67_SPI_CS (1 << 1)
1136#define MCP67_SPI_SCK (1 << 2)
1137#define MCP67_SPI_MOSI (1 << 3)
1138#define MCP67_SPI_MISO (1 << 4)
1139#define MCP67_SPI_ENABLE (1 << 0)
1140#define MCP67_SPI_IDLE (1 << 8)
1141
1142 status = mmio_readw(mcp_spibar + 0x530);
1143 msg_pdbg("SPI control is 0x%04x, enable=%i, idle=%i\n",
1144 status, status & 0x1, (status >> 8) & 0x1);
1145 /* FIXME: Remove the physunmap once the SPI driver exists. */
1146 physunmap(mcp_spibar, 0x544);
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001147 } else if (!mcp_spibaraddr && (buses_supported & CHIP_BUSTYPE_SPI)) {
1148 msg_pdbg("Strange. MCP SPI BAR is invalid.\n");
1149 buses_supported &= ~CHIP_BUSTYPE_SPI;
1150 ret = 1;
1151 } else if (mcp_spibaraddr && !(buses_supported & CHIP_BUSTYPE_SPI)) {
1152 msg_pdbg("Strange. MCP SPI BAR is valid, but chipset apparently"
1153 " doesn't have SPI enabled.\n");
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001154 } else {
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001155 msg_pdbg("MCP SPI is not used.\n");
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001156 }
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001157out_msg:
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001158 msg_pinfo("Please send the output of \"flashrom -V\" to "
1159 "flashrom@flashrom.org to help us finish support for your "
1160 "chipset. Thanks.\n");
1161
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001162 return ret;
1163}
1164
1165/**
1166 * The MCP61/MCP67 code is guesswork based on cleanroom reverse engineering.
1167 * Due to that, it only reads info and doesn't change any settings.
1168 * It is assumed that LPC chips need the MCP55 code and SPI chips need the
1169 * code provided in enable_flash_mcp6x_7x_common. Until we know for sure, call
1170 * enable_flash_mcp55 from this function only if enable_flash_mcp6x_7x_common
1171 * indicates the flash chip is LPC. Warning: enable_flash_mcp55
1172 * might make SPI flash inaccessible. The same caveat applies to SPI init
1173 * for LPC flash.
1174 */
1175static int enable_flash_mcp67(struct pci_dev *dev, const char *name)
1176{
1177 int result = 0;
1178
1179 result = enable_flash_mcp6x_7x_common(dev, name);
1180 if (result)
1181 return result;
1182
1183 /* Not sure if this is correct. No docs as usual. */
1184 switch (buses_supported) {
1185 case CHIP_BUSTYPE_LPC:
1186 result = enable_flash_mcp55(dev, name);
1187 break;
1188 case CHIP_BUSTYPE_SPI:
1189 msg_pinfo("SPI on this chipset is not supported yet.\n");
1190 buses_supported = CHIP_BUSTYPE_NONE;
1191 break;
1192 default:
1193 msg_pinfo("Something went wrong with bus type detection.\n");
1194 buses_supported = CHIP_BUSTYPE_NONE;
1195 break;
1196 }
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001197
1198 return result;
1199}
1200
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001201static int enable_flash_mcp7x(struct pci_dev *dev, const char *name)
1202{
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001203 int result = 0;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001204
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001205 result = enable_flash_mcp6x_7x_common(dev, name);
1206 if (result)
1207 return result;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001208
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001209 /* Not sure if this is correct. No docs as usual. */
1210 switch (buses_supported) {
1211 case CHIP_BUSTYPE_LPC:
1212 msg_pinfo("LPC on this chipset is not supported yet.\n");
1213 break;
1214 case CHIP_BUSTYPE_SPI:
1215 msg_pinfo("SPI on this chipset is not supported yet.\n");
1216 buses_supported = CHIP_BUSTYPE_NONE;
1217 break;
1218 default:
1219 msg_pinfo("Something went wrong with bus type detection.\n");
1220 buses_supported = CHIP_BUSTYPE_NONE;
1221 break;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001222 }
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001223
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001224 return result;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001225}
1226
Uwe Hermann372eeb52007-12-04 21:49:06 +00001227static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001228{
Michael Karchercfa674f2010-02-25 11:38:23 +00001229 uint8_t val;
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001230
Uwe Hermanne823ee02007-06-05 15:02:18 +00001231 /* Set the 4MB enable bit. */
Michael Karchercfa674f2010-02-25 11:38:23 +00001232 val = pci_read_byte(dev, 0x41);
1233 val |= 0x0e;
1234 pci_write_byte(dev, 0x41, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001235
Michael Karchercfa674f2010-02-25 11:38:23 +00001236 val = pci_read_byte(dev, 0x43);
1237 val |= (1 << 4);
1238 pci_write_byte(dev, 0x43, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001239
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001240 return 0;
1241}
1242
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001243/**
1244 * Usually on the x86 architectures (and on other PC-like platforms like some
1245 * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
1246 * Elan SC520 only a small piece of the system flash is mapped there, but the
1247 * complete flash is mapped somewhere below 1G. The position can be determined
1248 * by the BOOTCS PAR register.
1249 */
1250static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
1251{
1252 int i, bootcs_found = 0;
1253 uint32_t parx = 0;
1254 void *mmcr;
1255
1256 /* 1. Map MMCR */
Stefan Reinauer0593f212009-01-26 01:10:48 +00001257 mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001258
1259 /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for
1260 * BOOTCS region (PARx[31:29] = 100b)e
1261 */
1262 for (i = 0x88; i <= 0xc4; i += 4) {
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +00001263 parx = mmio_readl(mmcr + i);
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001264 if ((parx >> 29) == 4) {
1265 bootcs_found = 1;
1266 break; /* BOOTCS found */
1267 }
1268 }
1269
1270 /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0]
1271 * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0]
1272 */
1273 if (bootcs_found) {
1274 if (parx & (1 << 25)) {
1275 parx &= (1 << 14) - 1; /* Mask [13:0] */
1276 flashbase = parx << 16;
1277 } else {
1278 parx &= (1 << 18) - 1; /* Mask [17:0] */
1279 flashbase = parx << 12;
1280 }
1281 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +00001282 msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n");
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001283 }
1284
1285 /* 4. Clean up */
Carl-Daniel Hailfingerbe726812009-08-09 12:44:08 +00001286 physunmap(mmcr, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001287 return 0;
1288}
1289
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001290#endif
1291
Uwe Hermann4179d292009-05-08 17:50:51 +00001292/* Please keep this list alphabetically sorted by vendor/device. */
Uwe Hermann05fab752009-05-16 23:42:17 +00001293const struct penable chipset_enables[] = {
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001294#if defined(__i386__) || defined(__x86_64__)
Uwe Hermann4179d292009-05-08 17:50:51 +00001295 {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533},
1296 {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111},
1297 {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111},
1298 {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530},
1299 {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536},
Nils Jacobse715c7b2009-09-23 02:09:23 +00001300 {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536},
Uwe Hermann4179d292009-05-08 17:50:51 +00001301 {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520},
1302 {0x1002, 0x438D, OK, "AMD", "SB600", enable_flash_sb600},
Carl-Daniel Hailfinger174962d2009-09-01 22:13:42 +00001303 {0x1002, 0x439d, OK, "AMD", "SB700/SB710/SB750", enable_flash_sb600},
Uwe Hermann4179d292009-05-08 17:50:51 +00001304 {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100},
1305 {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400},
1306 {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000},
Carl-Daniel Hailfinger797a8342009-11-26 16:51:39 +00001307 {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_ich10},
1308 {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_ich10},
1309 {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_ich10},
Uwe Hermannb0039912009-05-07 13:24:49 +00001310 {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4},
Uwe Hermann4179d292009-05-08 17:50:51 +00001311 {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich_4e},
1312 {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich_dc},
1313 {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7},
Uwe Hermannb0039912009-05-07 13:24:49 +00001314 {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e},
Uwe Hermann4179d292009-05-08 17:50:51 +00001315 {0x8086, 0x3a18, OK, "Intel", "ICH10", enable_flash_ich10},
1316 {0x8086, 0x3a1a, OK, "Intel", "ICH10D", enable_flash_ich10},
1317 {0x8086, 0x3a14, OK, "Intel", "ICH10DO", enable_flash_ich10},
1318 {0x8086, 0x3a16, OK, "Intel", "ICH10R", enable_flash_ich10},
Uwe Hermannb0039912009-05-07 13:24:49 +00001319 {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e},
1320 {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +00001321 {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich_4e},
Uwe Hermann4179d292009-05-08 17:50:51 +00001322 {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +00001323 {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich_4e},
1324 {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich_4e},
1325 {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +00001326 {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich_dc},
1327 {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich_dc},
Uwe Hermannb0039912009-05-07 13:24:49 +00001328 {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7},
1329 {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7},
1330 {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7},
1331 {0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7},
David Hendricksdb7c1532010-01-19 02:19:27 +00001332 {0x8086, 0x27bc, OK, "Intel", "NM10", enable_flash_ich7},
Uwe Hermann4179d292009-05-08 17:50:51 +00001333 {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +00001334 {0x8086, 0x2812, OK, "Intel", "ICH8DH", enable_flash_ich8},
1335 {0x8086, 0x2814, OK, "Intel", "ICH8DO", enable_flash_ich8},
Uwe Hermann4179d292009-05-08 17:50:51 +00001336 {0x8086, 0x2810, OK, "Intel", "ICH8/ICH8R", enable_flash_ich8},
Uwe Hermannb0039912009-05-07 13:24:49 +00001337 {0x8086, 0x2815, OK, "Intel", "ICH8M", enable_flash_ich8},
Uwe Hermann4179d292009-05-08 17:50:51 +00001338 {0x8086, 0x2811, OK, "Intel", "ICH8M-E", enable_flash_ich8},
1339 {0x8086, 0x2918, OK, "Intel", "ICH9", enable_flash_ich9},
Uwe Hermannb0039912009-05-07 13:24:49 +00001340 {0x8086, 0x2912, OK, "Intel", "ICH9DH", enable_flash_ich9},
1341 {0x8086, 0x2914, OK, "Intel", "ICH9DO", enable_flash_ich9},
Uwe Hermannb0039912009-05-07 13:24:49 +00001342 {0x8086, 0x2919, OK, "Intel", "ICH9M", enable_flash_ich9},
Uwe Hermann4179d292009-05-08 17:50:51 +00001343 {0x8086, 0x2917, OK, "Intel", "ICH9M-E", enable_flash_ich9},
1344 {0x8086, 0x2916, OK, "Intel", "ICH9R", enable_flash_ich9},
Carl-Daniel Hailfinger95baaad2009-08-21 17:26:13 +00001345 {0x8086, 0x2910, OK, "Intel", "ICH9 Engineering Sample", enable_flash_ich9},
Uwe Hermann4179d292009-05-08 17:50:51 +00001346 {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4},
1347 {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4},
1348 {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4},
1349 {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4},
Adam Jurkowskie4984102009-12-21 15:30:46 +00001350 {0x8086, 0x8119, OK, "Intel", "Poulsbo", enable_flash_poulsbo},
Luc Verhaegenaad7e672009-10-06 11:32:21 +00001351 {0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2},
Uwe Hermannb0039912009-05-07 13:24:49 +00001352 {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */
1353 {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */
Luc Verhaegen90e8e612009-05-26 09:48:28 +00001354 {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2},
Uwe Hermanneac10162008-03-13 18:52:51 +00001355 /* Slave, should not be here, to fix known bug for A01. */
Uwe Hermannb0039912009-05-07 13:24:49 +00001356 {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804},
1357 {0x10de, 0x0260, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1358 {0x10de, 0x0261, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1359 {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1360 {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1361 {0x10de, 0x0360, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/
Carl-Daniel Hailfinger33d7b6a2010-05-22 07:27:16 +00001362 /* 10de:0361 is present in Tyan S2915 OEM systems, but not connected to
1363 * the flash chip. Instead, 10de:0364 is connected to the flash chip.
1364 * Until we have PCI device class matching or some fallback mechanism,
1365 * this is needed to get flashrom working on Tyan S2915 and maybe other
1366 * dual-MCP55 boards.
1367 */
1368#if 0
1369 {0x10de, 0x0361, NT, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1370#endif
Uwe Hermannb0039912009-05-07 13:24:49 +00001371 {0x10de, 0x0362, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1372 {0x10de, 0x0363, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1373 {0x10de, 0x0364, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1374 {0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1375 {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1376 {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001377 {0x10de, 0x03e0, NT, "NVIDIA", "MCP61", enable_flash_mcp67},
1378 {0x10de, 0x03e1, NT, "NVIDIA", "MCP61", enable_flash_mcp67},
1379 {0x10de, 0x03e2, NT, "NVIDIA", "MCP61", enable_flash_mcp67},
1380 {0x10de, 0x03e3, NT, "NVIDIA", "MCP61", enable_flash_mcp67},
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001381 {0x10de, 0x0440, NT, "NVIDIA", "MCP65", enable_flash_mcp7x},
1382 {0x10de, 0x0441, NT, "NVIDIA", "MCP65", enable_flash_mcp7x},
1383 {0x10de, 0x0442, NT, "NVIDIA", "MCP65", enable_flash_mcp7x},
1384 {0x10de, 0x0443, NT, "NVIDIA", "MCP65", enable_flash_mcp7x},
1385 {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp67},
1386 {0x10de, 0x075c, NT, "NVIDIA", "MCP78S", enable_flash_mcp7x},
1387 {0x10de, 0x075d, NT, "NVIDIA", "MCP78S", enable_flash_mcp7x},
1388 {0x10de, 0x07d7, NT, "NVIDIA", "MCP73", enable_flash_mcp7x},
1389 {0x10de, 0x0aac, NT, "NVIDIA", "MCP79", enable_flash_mcp7x},
1390 {0x10de, 0x0aad, NT, "NVIDIA", "MCP79", enable_flash_mcp7x},
1391 {0x10de, 0x0aae, NT, "NVIDIA", "MCP79", enable_flash_mcp7x},
1392 {0x10de, 0x0aaf, NT, "NVIDIA", "MCP79", enable_flash_mcp7x},
Carl-Daniel Hailfinger6a0269e2009-11-15 17:20:21 +00001393 {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496},
1394 {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501},
1395 {0x1039, 0x5511, NT, "SiS", "5511", enable_flash_sis5511},
Luc Verhaegen9cce2f52010-01-10 15:01:08 +00001396 {0x1039, 0x5596, NT, "SiS", "5596", enable_flash_sis5511},
Carl-Daniel Hailfinger6a0269e2009-11-15 17:20:21 +00001397 {0x1039, 0x5571, NT, "SiS", "5571", enable_flash_sis530},
1398 {0x1039, 0x5591, NT, "SiS", "5591/5592", enable_flash_sis530},
1399 {0x1039, 0x5597, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530},
1400 {0x1039, 0x0530, NT, "SiS", "530", enable_flash_sis530},
1401 {0x1039, 0x5600, NT, "SiS", "600", enable_flash_sis530},
1402 {0x1039, 0x0620, NT, "SiS", "620", enable_flash_sis530},
1403 {0x1039, 0x0540, NT, "SiS", "540", enable_flash_sis540},
Luc Verhaegen9892ca62009-12-09 07:43:13 +00001404 {0x1039, 0x0630, NT, "SiS", "630", enable_flash_sis540},
1405 {0x1039, 0x0635, NT, "SiS", "635", enable_flash_sis540},
1406 {0x1039, 0x0640, NT, "SiS", "640", enable_flash_sis540},
1407 {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis540},
1408 {0x1039, 0x0646, NT, "SiS", "645DX", enable_flash_sis540},
1409 {0x1039, 0x0648, NT, "SiS", "648", enable_flash_sis540},
1410 {0x1039, 0x0650, NT, "SiS", "650", enable_flash_sis540},
1411 {0x1039, 0x0651, NT, "SiS", "651", enable_flash_sis540},
1412 {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis540},
1413 {0x1039, 0x0730, NT, "SiS", "730", enable_flash_sis540},
1414 {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis540},
1415 {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis540},
1416 {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis540},
1417 {0x1039, 0x0745, NT, "SiS", "745", enable_flash_sis540},
1418 {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540},
1419 {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540},
1420 {0x1039, 0x0755, NT, "SiS", "755", enable_flash_sis540},
Uwe Hermann4179d292009-05-08 17:50:51 +00001421 {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x},
1422 {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x},
Mateusz Murawskie6abef02009-06-18 12:42:46 +00001423 {0x1106, 0x3074, NT, "VIA", "VT8233", enable_flash_vt823x},
Raúl Sorianocd8404d2009-12-23 21:29:18 +00001424 {0x1106, 0x3147, OK, "VIA", "VT8233A", enable_flash_vt823x},
Uwe Hermann4179d292009-05-08 17:50:51 +00001425 {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x},
1426 {0x1106, 0x3227, OK, "VIA", "VT8237", enable_flash_vt823x},
1427 {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x},
1428 {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi},
Arjan Koers8dfea832009-06-15 00:03:37 +00001429 {0x1106, 0x8353, OK, "VIA", "VX800", enable_flash_vt8237s_spi},
Uwe Hermann3e0774d2009-09-25 01:05:06 +00001430 {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111},
Uwe Hermann4179d292009-05-08 17:50:51 +00001431 {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111},
1432 {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111},
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001433#endif
Uwe Hermann05fab752009-05-16 23:42:17 +00001434 {},
Ollie Lhocbbf1252004-03-17 22:22:08 +00001435};
Ollie Lho761bf1b2004-03-20 16:46:10 +00001436
Uwe Hermanna7e05482007-05-09 10:17:44 +00001437int chipset_flash_enable(void)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001438{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001439 struct pci_dev *dev = 0;
Uwe Hermann372eeb52007-12-04 21:49:06 +00001440 int ret = -2; /* Nothing! */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001441 int i;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001442
Uwe Hermann372eeb52007-12-04 21:49:06 +00001443 /* Now let's try to find the chipset we have... */
Uwe Hermann05fab752009-05-16 23:42:17 +00001444 for (i = 0; chipset_enables[i].vendor_name != NULL; i++) {
1445 dev = pci_dev_find(chipset_enables[i].vendor_id,
1446 chipset_enables[i].device_id);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001447 if (dev)
1448 break;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001449 }
1450
Uwe Hermanna7e05482007-05-09 10:17:44 +00001451 if (dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001452 msg_pinfo("Found chipset \"%s %s\", enabling flash write... ",
Uwe Hermann05fab752009-05-16 23:42:17 +00001453 chipset_enables[i].vendor_name,
1454 chipset_enables[i].device_name);
Carl-Daniel Hailfingerf469c272010-05-22 07:31:50 +00001455 msg_pdbg("chipset PCI ID is %04x:%04x, ",
1456 chipset_enables[i].vendor_id,
1457 chipset_enables[i].device_id);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001458
Uwe Hermann05fab752009-05-16 23:42:17 +00001459 ret = chipset_enables[i].doit(dev,
1460 chipset_enables[i].device_name);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001461 if (ret)
Sean Nelson316a29f2010-05-07 20:09:04 +00001462 msg_pinfo("FAILED!\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00001463 else
Sean Nelson316a29f2010-05-07 20:09:04 +00001464 msg_pinfo("OK.\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00001465 }
Sean Nelson316a29f2010-05-07 20:09:04 +00001466 msg_pinfo("This chipset supports the following protocols: %s.\n",
Uwe Hermann9899cad2009-06-28 21:47:57 +00001467 flashbuses_to_text(buses_supported));
Uwe Hermanna7e05482007-05-09 10:17:44 +00001468
1469 return ret;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001470}