blob: d2ae21279a2867c685c4d8605ab522a2d304f3ed [file] [log] [blame]
Ollie Lho184a4042005-11-26 21:55:36 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ollie Lho184a4042005-11-26 21:55:36 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
6 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Ollie Lho184a4042005-11-26 21:55:36 +00007 *
Uwe Hermannd1107642007-08-29 17:52:32 +00008 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
Ollie Lho184a4042005-11-26 21:55:36 +000011 *
Uwe Hermannd1107642007-08-29 17:52:32 +000012 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22/*
23 * Contains the chipset specific flash enables.
Ollie Lho184a4042005-11-26 21:55:36 +000024 */
25
Lane Brooksd54958a2007-11-13 16:45:22 +000026#define _LARGEFILE64_SOURCE
27
Ollie Lhocbbf1252004-03-17 22:22:08 +000028#include <stdio.h>
29#include <pci/pci.h>
30#include <stdlib.h>
Lane Brooksd54958a2007-11-13 16:45:22 +000031#include <sys/types.h>
32#include <sys/stat.h>
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +000033#include <sys/mman.h>
Lane Brooksd54958a2007-11-13 16:45:22 +000034#include <fcntl.h>
35#include <unistd.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000036#include "flash.h"
Stefan Reinauer86de2832006-03-31 11:26:55 +000037
Stefan Reinauer9a6d1762008-12-03 21:24:40 +000038unsigned long flashbase = 0;
39
Stefan Reinauer2cb94e12008-06-30 23:45:22 +000040/**
41 * flashrom defaults to LPC flash devices. If a known SPI controller is found
42 * and the SPI strappings are set, this will be overwritten by the probing code.
43 *
44 * Eventually, this will become an array when multiple flash support works.
45 */
46
47flashbus_t flashbus = BUS_TYPE_LPC;
48void *spibar = NULL;
49
FENG yu ningc05a2952008-12-08 18:16:58 +000050extern int ichspi_lock;
51
Uwe Hermann372eeb52007-12-04 21:49:06 +000052static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
Luc Verhaegen6b141752007-05-20 16:16:13 +000053{
54 uint8_t tmp;
55
Uwe Hermann372eeb52007-12-04 21:49:06 +000056 /*
57 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
58 * 0xFFFE0000-0xFFFFFFFF ROM select enable.
59 */
Luc Verhaegen6b141752007-05-20 16:16:13 +000060 tmp = pci_read_byte(dev, 0x47);
61 tmp |= 0x46;
62 pci_write_byte(dev, 0x47, tmp);
63
64 return 0;
65}
66
Uwe Hermann372eeb52007-12-04 21:49:06 +000067static int enable_flash_sis630(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +000068{
Uwe Hermann372eeb52007-12-04 21:49:06 +000069 uint8_t b;
Ollie Lhocbbf1252004-03-17 22:22:08 +000070
Uwe Hermann372eeb52007-12-04 21:49:06 +000071 /* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
Alex Beregszaszic9fb5d92007-09-11 15:58:18 +000072 b = pci_read_byte(dev, 0x40);
73 pci_write_byte(dev, 0x40, b | 0xb);
Uwe Hermann372eeb52007-12-04 21:49:06 +000074
75 /* Flash write enable on SiS 540/630. */
Alex Beregszaszic9fb5d92007-09-11 15:58:18 +000076 b = pci_read_byte(dev, 0x45);
77 pci_write_byte(dev, 0x45, b | 0x40);
Ollie Lhocbbf1252004-03-17 22:22:08 +000078
Uwe Hermann372eeb52007-12-04 21:49:06 +000079 /* The same thing on SiS 950 Super I/O side... */
80
81 /* First probe for Super I/O on config port 0x2e. */
Andriy Gapon65c1b862008-05-22 13:22:45 +000082 OUTB(0x87, 0x2e);
83 OUTB(0x01, 0x2e);
84 OUTB(0x55, 0x2e);
85 OUTB(0x55, 0x2e);
Ollie Lhocbbf1252004-03-17 22:22:08 +000086
Andriy Gapon65c1b862008-05-22 13:22:45 +000087 if (INB(0x2f) != 0x87) {
Uwe Hermann372eeb52007-12-04 21:49:06 +000088 /* If that failed, try config port 0x4e. */
Andriy Gapon65c1b862008-05-22 13:22:45 +000089 OUTB(0x87, 0x4e);
90 OUTB(0x01, 0x4e);
91 OUTB(0x55, 0x4e);
92 OUTB(0xaa, 0x4e);
93 if (INB(0x4f) != 0x87) {
Ollie Lhocbbf1252004-03-17 22:22:08 +000094 printf("Can not access SiS 950\n");
95 return -1;
96 }
Andriy Gapon65c1b862008-05-22 13:22:45 +000097 OUTB(0x24, 0x4e);
98 b = INB(0x4f) | 0xfc;
99 OUTB(0x24, 0x4e);
100 OUTB(b, 0x4f);
101 OUTB(0x02, 0x4e);
102 OUTB(0x02, 0x4f);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000103 }
104
Andriy Gapon65c1b862008-05-22 13:22:45 +0000105 OUTB(0x24, 0x2e);
106 printf("2f is %#x\n", INB(0x2f));
107 b = INB(0x2f) | 0xfc;
108 OUTB(0x24, 0x2e);
109 OUTB(b, 0x2f);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000110
Andriy Gapon65c1b862008-05-22 13:22:45 +0000111 OUTB(0x02, 0x2e);
112 OUTB(0x02, 0x2f);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000113
114 return 0;
115}
116
Uwe Hermann987942d2006-11-07 11:16:21 +0000117/* Datasheet:
118 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
119 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
120 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
121 * - Order Number: 290562-001
122 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000123static int enable_flash_piix4(struct pci_dev *dev, const char *name)
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000124{
125 uint16_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000126 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000127
128 old = pci_read_word(dev, xbcs);
129
130 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
Uwe Hermanna7e05482007-05-09 10:17:44 +0000131 * FFF00000-FFF7FFFF are forwarded to ISA).
Uwe Hermannc556d322008-10-28 11:50:05 +0000132 * Note: This bit is reserved on PIIX/PIIX3/MPIIX.
Uwe Hermanna7e05482007-05-09 10:17:44 +0000133 * Set bit 7: Extended BIOS Enable (PCI master accesses to
134 * FFF80000-FFFDFFFF are forwarded to ISA).
135 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
136 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
137 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
138 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
139 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
140 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
141 */
Uwe Hermannc556d322008-10-28 11:50:05 +0000142 if (dev->device_id == 0x122e || dev->device_id == 0x7000
143 || dev->device_id == 0x1234)
144 new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
Uwe Hermann87203452008-10-26 18:40:42 +0000145 else
146 new = old | 0x02c4;
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000147
148 if (new == old)
149 return 0;
150
151 pci_write_word(dev, xbcs, new);
152
153 if (pci_read_word(dev, xbcs) != new) {
154 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name);
155 return -1;
156 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000157
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000158 return 0;
159}
160
Uwe Hermann372eeb52007-12-04 21:49:06 +0000161/*
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000162 * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet"
163 * http://download.intel.com/design/chipsets/datashts/30701303.pdf
Uwe Hermann372eeb52007-12-04 21:49:06 +0000164 */
165static int enable_flash_ich(struct pci_dev *dev, const char *name,
166 int bios_cntl)
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000167{
Ollie Lho184a4042005-11-26 21:55:36 +0000168 uint8_t old, new;
Stefan Reinauereb366472006-09-06 15:48:48 +0000169
Uwe Hermann372eeb52007-12-04 21:49:06 +0000170 /*
171 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
Uwe Hermanna7e05482007-05-09 10:17:44 +0000172 * just treating it as 8 bit wide seems to work fine in practice.
Stefan Reinauereb366472006-09-06 15:48:48 +0000173 */
Stefan Reinauer86de2832006-03-31 11:26:55 +0000174 old = pci_read_byte(dev, bios_cntl);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000175
Uwe Hermann793bdcd2008-05-22 22:47:04 +0000176 printf_debug("\nBIOS Lock Enable: %sabled, ",
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000177 (old & (1 << 1)) ? "en" : "dis");
178 printf_debug("BIOS Write Enable: %sabled, ",
179 (old & (1 << 0)) ? "en" : "dis");
180 printf_debug("BIOS_CNTL is 0x%x\n", old);
181
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000182 new = old | 1;
183
184 if (new == old)
185 return 0;
186
Stefan Reinauer86de2832006-03-31 11:26:55 +0000187 pci_write_byte(dev, bios_cntl, new);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000188
Stefan Reinauer86de2832006-03-31 11:26:55 +0000189 if (pci_read_byte(dev, bios_cntl) != new) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000190 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000191 return -1;
192 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000193
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000194 return 0;
195}
196
Uwe Hermann372eeb52007-12-04 21:49:06 +0000197static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000198{
Stefan Reinauereb366472006-09-06 15:48:48 +0000199 return enable_flash_ich(dev, name, 0x4e);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000200}
201
Uwe Hermann372eeb52007-12-04 21:49:06 +0000202static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000203{
Stefan Reinauereb366472006-09-06 15:48:48 +0000204 return enable_flash_ich(dev, name, 0xdc);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000205}
206
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000207#define ICH_STRAP_RSVD 0x00
208#define ICH_STRAP_SPI 0x01
209#define ICH_STRAP_PCI 0x02
210#define ICH_STRAP_LPC 0x03
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000211
Uwe Hermann394131e2008-10-18 21:14:13 +0000212static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
213{
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000214 uint32_t mmio_base;
215
216 mmio_base = (pci_read_long(dev, 0xbc)) << 8;
217 printf_debug("MMIO base at = 0x%x\n", mmio_base);
Uwe Hermann394131e2008-10-18 21:14:13 +0000218 spibar = mmap(NULL, 0x70, PROT_READ | PROT_WRITE, MAP_SHARED,
219 fd_mem, mmio_base);
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000220
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000221 if (spibar == MAP_FAILED) {
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000222 perror("Can't mmap memory using " MEM_DEV);
223 exit(1);
224 }
225
Uwe Hermann394131e2008-10-18 21:14:13 +0000226 printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n",
227 *(uint16_t *) (spibar + 0x6c));
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000228
229 flashbus = BUS_TYPE_VIA_SPI;
230
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000231 return 0;
232}
233
Uwe Hermann394131e2008-10-18 21:14:13 +0000234static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
235 int ich_generation)
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000236{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000237 int ret, i;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000238 uint8_t old, new, bbs, buc;
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000239 uint16_t spibar_offset, tmp2;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000240 uint32_t tmp, gcs;
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000241 void *rcrb;
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000242 //TODO: These names are incorrect for EP80579. For that, the solution would look like the commented line
243 //static const char *straps_names[] = {"SPI", "reserved", "reserved", "LPC" };
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000244 static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" };
Uwe Hermann394131e2008-10-18 21:14:13 +0000245
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000246 /* Enable Flash Writes */
247 ret = enable_flash_ich_dc(dev, name);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000248
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000249 /* Get physical address of Root Complex Register Block */
250 tmp = pci_read_long(dev, 0xf0) & 0xffffc000;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000251 printf_debug("\nRoot Complex Register Block address = 0x%x\n", tmp);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000252
253 /* Map RCBA to virtual memory */
Uwe Hermann394131e2008-10-18 21:14:13 +0000254 rcrb = mmap(0, 0x4000, PROT_READ | PROT_WRITE, MAP_SHARED, fd_mem,
255 (off_t) tmp);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000256 if (rcrb == MAP_FAILED) {
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000257 perror("Can't mmap memory using " MEM_DEV);
258 exit(1);
259 }
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000260
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000261 gcs = *(volatile uint32_t *)(rcrb + 0x3410);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000262 printf_debug("GCS = 0x%x: ", gcs);
263 printf_debug("BIOS Interface Lock-Down: %sabled, ",
264 (gcs & 0x1) ? "en" : "dis");
265 bbs = (gcs >> 10) & 0x3;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000266 printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000267
Stefan Reinauera9424d52008-06-27 16:28:34 +0000268 buc = *(volatile uint8_t *)(rcrb + 0x3414);
Uwe Hermann394131e2008-10-18 21:14:13 +0000269 printf_debug("Top Swap : %s\n",
270 (buc & 1) ? "enabled (A16 inverted)" : "not enabled");
Stefan Reinauera9424d52008-06-27 16:28:34 +0000271
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000272 /* It seems the ICH7 does not support SPI and LPC chips at the same
273 * time. At least not with our current code. So we prevent searching
274 * on ICH7 when the southbridge is strapped to LPC
275 */
276
277 if (ich_generation == 7 && bbs == ICH_STRAP_LPC) {
278 /* No further SPI initialization required */
279 return ret;
280 }
281
282 switch (ich_generation) {
283 case 7:
284 flashbus = BUS_TYPE_ICH7_SPI;
285 spibar_offset = 0x3020;
286 break;
287 case 8:
288 flashbus = BUS_TYPE_ICH9_SPI;
289 spibar_offset = 0x3020;
290 break;
291 case 9:
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000292 case 10:
Uwe Hermann394131e2008-10-18 21:14:13 +0000293 default: /* Future version might behave the same */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000294 flashbus = BUS_TYPE_ICH9_SPI;
295 spibar_offset = 0x3800;
296 break;
297 }
298
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000299 /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000300 printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000301
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000302 /* Assign Virtual Address */
Uwe Hermann394131e2008-10-18 21:14:13 +0000303 spibar = rcrb + spibar_offset;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000304
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000305 switch (flashbus) {
306 case BUS_TYPE_ICH7_SPI:
Uwe Hermann394131e2008-10-18 21:14:13 +0000307 printf_debug("0x00: 0x%04x (SPIS)\n",
308 *(uint16_t *) (spibar + 0));
309 printf_debug("0x02: 0x%04x (SPIC)\n",
310 *(uint16_t *) (spibar + 2));
311 printf_debug("0x04: 0x%08x (SPIA)\n",
312 *(uint32_t *) (spibar + 4));
313 for (i = 0; i < 8; i++) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000314 int offs;
315 offs = 8 + (i * 8);
Uwe Hermann394131e2008-10-18 21:14:13 +0000316 printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs,
317 *(uint32_t *) (spibar + offs), i);
318 printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
319 *(uint32_t *) (spibar + offs + 4), i);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000320 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000321 printf_debug("0x50: 0x%08x (BBAR)\n",
322 *(uint32_t *) (spibar + 0x50));
323 printf_debug("0x54: 0x%04x (PREOP)\n",
324 *(uint16_t *) (spibar + 0x54));
325 printf_debug("0x56: 0x%04x (OPTYPE)\n",
326 *(uint16_t *) (spibar + 0x56));
327 printf_debug("0x58: 0x%08x (OPMENU)\n",
328 *(uint32_t *) (spibar + 0x58));
329 printf_debug("0x5c: 0x%08x (OPMENU+4)\n",
330 *(uint32_t *) (spibar + 0x5c));
331 for (i = 0; i < 4; i++) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000332 int offs;
333 offs = 0x60 + (i * 4);
Uwe Hermann394131e2008-10-18 21:14:13 +0000334 printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs,
335 *(uint32_t *) (spibar + offs), i);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000336 }
337 printf_debug("\n");
Uwe Hermann394131e2008-10-18 21:14:13 +0000338 if ((*(uint16_t *) spibar) & (1 << 15)) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000339 printf("WARNING: SPI Configuration Lockdown activated.\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000340 ichspi_lock = 1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000341 }
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000342 break;
343 case BUS_TYPE_ICH9_SPI:
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000344 tmp2 = *(uint16_t *) (spibar + 0);
345 printf_debug("0x00: 0x%04x (HSFS)\n", tmp2);
346 printf_debug("FLOCKDN %i, ", (tmp >> 15 & 1));
347 printf_debug("FDV %i, ", (tmp >> 14) & 1);
348 printf_debug("FDOPSS %i, ", (tmp >> 13) & 1);
349 printf_debug("SCIP %i, ", (tmp >> 5) & 1);
350 printf_debug("BERASE %i, ", (tmp >> 3) & 3);
351 printf_debug("AEL %i, ", (tmp >> 2) & 1);
352 printf_debug("FCERR %i, ", (tmp >> 1) & 1);
353 printf_debug("FDONE %i\n", (tmp >> 0) & 1);
354
355 tmp = *(uint32_t *) (spibar + 0x50);
356 printf_debug("0x50: 0x%08x (FRAP)\n", tmp);
357 printf_debug("BMWAG %i, ", (tmp >> 24) & 0xff);
358 printf_debug("BMRAG %i, ", (tmp >> 16) & 0xff);
359 printf_debug("BRWA %i, ", (tmp >> 8) & 0xff);
360 printf_debug("BRRA %i\n", (tmp >> 0) & 0xff);
361
362 printf_debug("0x54: 0x%08x (FREG0)\n",
363 *(uint32_t *) (spibar + 0x54));
364 printf_debug("0x58: 0x%08x (FREG1)\n",
365 *(uint32_t *) (spibar + 0x58));
366 printf_debug("0x5C: 0x%08x (FREG2)\n",
367 *(uint32_t *) (spibar + 0x5C));
368 printf_debug("0x60: 0x%08x (FREG3)\n",
369 *(uint32_t *) (spibar + 0x60));
370 printf_debug("0x64: 0x%08x (FREG4)\n",
371 *(uint32_t *) (spibar + 0x64));
372 printf_debug("0x74: 0x%08x (PR0)\n",
373 *(uint32_t *) (spibar + 0x74));
374 printf_debug("0x78: 0x%08x (PR1)\n",
375 *(uint32_t *) (spibar + 0x78));
376 printf_debug("0x7C: 0x%08x (PR2)\n",
377 *(uint32_t *) (spibar + 0x7C));
378 printf_debug("0x80: 0x%08x (PR3)\n",
379 *(uint32_t *) (spibar + 0x80));
380 printf_debug("0x84: 0x%08x (PR4)\n",
381 *(uint32_t *) (spibar + 0x84));
382 /* printf_debug("0xA0: 0x%08x (BBAR)\n",
383 *(uint32_t *) (spibar + 0xA0)); ICH10 only? */
384 printf_debug("0xB0: 0x%08x (FDOC)\n",
385 *(uint32_t *) (spibar + 0xB0));
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000386 break;
387 default:
388 /* Nothing */
389 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000390 }
391
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000392 old = pci_read_byte(dev, 0xdc);
393 printf_debug("SPI Read Configuration: ");
394 new = (old >> 2) & 0x3;
395 switch (new) {
396 case 0:
397 case 1:
398 case 2:
399 printf_debug("prefetching %sabled, caching %sabled, ",
Uwe Hermann394131e2008-10-18 21:14:13 +0000400 (new & 0x2) ? "en" : "dis",
401 (new & 0x1) ? "dis" : "en");
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000402 break;
403 default:
404 printf_debug("invalid prefetching/caching settings, ");
405 break;
406 }
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000407
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000408 return ret;
409}
Stefan Reinauera9424d52008-06-27 16:28:34 +0000410
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000411static int enable_flash_ich7(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000412{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000413 return enable_flash_ich_dc_spi(dev, name, 7);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000414}
415
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000416static int enable_flash_ich8(struct pci_dev *dev, const char *name)
417{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000418 return enable_flash_ich_dc_spi(dev, name, 8);
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000419}
420
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000421static int enable_flash_ich9(struct pci_dev *dev, const char *name)
422{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000423 return enable_flash_ich_dc_spi(dev, name, 9);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000424}
425
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000426static int enable_flash_ich10(struct pci_dev *dev, const char *name)
427{
428 return enable_flash_ich_dc_spi(dev, name, 10);
429}
430
Uwe Hermann372eeb52007-12-04 21:49:06 +0000431static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000432{
Ollie Lho184a4042005-11-26 21:55:36 +0000433 uint8_t val;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000434
Uwe Hermann394131e2008-10-18 21:14:13 +0000435 /* enable ROM decode range (1MB) FFC00000 - FFFFFFFF */
Bari Ari9477c4e2008-04-29 13:46:38 +0000436 pci_write_byte(dev, 0x41, 0x7f);
437
Uwe Hermannffec5f32007-08-23 16:08:21 +0000438 /* ROM write enable */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000439 val = pci_read_byte(dev, 0x40);
440 val |= 0x10;
441 pci_write_byte(dev, 0x40, val);
442
443 if (pci_read_byte(dev, 0x40) != val) {
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000444 printf("\nWARNING: Failed to enable ROM Write on \"%s\"\n",
Uwe Hermanna7e05482007-05-09 10:17:44 +0000445 name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000446 return -1;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000447 }
Luc Verhaegen6382b442007-03-02 22:16:38 +0000448
Uwe Hermanna7e05482007-05-09 10:17:44 +0000449 return 0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000450}
451
Uwe Hermann372eeb52007-12-04 21:49:06 +0000452static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000453{
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000454 uint8_t reg8;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000455
Uwe Hermann394131e2008-10-18 21:14:13 +0000456#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
457#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000458
Uwe Hermann394131e2008-10-18 21:14:13 +0000459#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
460#define ROM_WRITE_ENABLE (1 << 1)
461#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
462#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000463
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000464 /* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
465 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
466 * Make the configured ROM areas writable.
467 */
468 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
469 reg8 |= LOWER_ROM_ADDRESS_RANGE;
470 reg8 |= UPPER_ROM_ADDRESS_RANGE;
471 reg8 |= ROM_WRITE_ENABLE;
472 pci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000473
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000474 /* Set positive decode on ROM. */
475 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
476 reg8 |= BIOS_ROM_POSITIVE_DECODE;
477 pci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000478
Ollie Lhocbbf1252004-03-17 22:22:08 +0000479 return 0;
480}
481
Mart Raudseppe1344da2008-02-08 10:10:57 +0000482/**
483 * Geode systems write protect the BIOS via RCONFs (cache settings similar
484 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22. Reading and
485 * writing to MSRs, however requires instructions rdmsr/wrmsr, which are
486 * ring0 privileged instructions so only the kernel can do the read/write.
487 * This function, therefore, requires that the msr kernel module be loaded
488 * to access these instructions from user space using device /dev/cpu/0/msr.
489 *
490 * This hard-coded location could have potential problems on SMP machines
491 * since it assumes cpu0, but it is safe on the Geode which is not SMP.
492 *
493 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
494 * To enable write to NOR Boot flash for the benefit of systems that have such
495 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
496 *
497 * This is probably not portable beyond Linux.
498 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000499static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
Lane Brooksd54958a2007-11-13 16:45:22 +0000500{
Uwe Hermann394131e2008-10-18 21:14:13 +0000501#define MSR_RCONF_DEFAULT 0x1808
502#define MSR_NORF_CTL 0x51400018
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000503
Lane Brooksd54958a2007-11-13 16:45:22 +0000504 int fd_msr;
505 unsigned char buf[8];
Lane Brooksd54958a2007-11-13 16:45:22 +0000506
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000507 fd_msr = open("/dev/cpu/0/msr", O_RDWR);
Lane Brooksd54958a2007-11-13 16:45:22 +0000508 if (!fd_msr) {
509 perror("open msr");
510 return -1;
511 }
Mart Raudseppe1344da2008-02-08 10:10:57 +0000512
513 if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) {
514 perror("lseek64");
Mart Raudsepp3697ac72008-02-11 14:32:45 +0000515 printf("Cannot operate on MSR. Did you run 'modprobe msr'?\n");
Mart Raudseppe1344da2008-02-08 10:10:57 +0000516 close(fd_msr);
517 return -1;
518 }
519
520 if (read(fd_msr, buf, 8) != 8) {
Mart Raudsepp3697ac72008-02-11 14:32:45 +0000521 perror("read msr");
Mart Raudseppe1344da2008-02-08 10:10:57 +0000522 close(fd_msr);
523 return -1;
524 }
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000525
Lane Brooksd54958a2007-11-13 16:45:22 +0000526 if (buf[7] != 0x22) {
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000527 buf[7] &= 0xfb;
Uwe Hermann394131e2008-10-18 21:14:13 +0000528 if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT,
529 SEEK_SET) == -1) {
Mart Raudseppe1344da2008-02-08 10:10:57 +0000530 perror("lseek64");
531 close(fd_msr);
532 return -1;
533 }
534
Lane Brooksd54958a2007-11-13 16:45:22 +0000535 if (write(fd_msr, buf, 8) < 0) {
536 perror("msr write");
Mart Raudseppe1344da2008-02-08 10:10:57 +0000537 close(fd_msr);
Lane Brooksd54958a2007-11-13 16:45:22 +0000538 return -1;
539 }
Lane Brooksd54958a2007-11-13 16:45:22 +0000540 }
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000541
Mart Raudseppe1344da2008-02-08 10:10:57 +0000542 if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) {
543 perror("lseek64");
544 close(fd_msr);
545 return -1;
546 }
547
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000548 if (read(fd_msr, buf, 8) != 8) {
549 perror("read msr");
Mart Raudseppe1344da2008-02-08 10:10:57 +0000550 close(fd_msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000551 return -1;
552 }
553
554 /* Raise WE_CS3 bit. */
555 buf[0] |= 0x08;
556
Mart Raudseppe1344da2008-02-08 10:10:57 +0000557 if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) {
558 perror("lseek64");
559 close(fd_msr);
560 return -1;
561 }
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000562 if (write(fd_msr, buf, 8) < 0) {
563 perror("msr write");
Mart Raudseppe1344da2008-02-08 10:10:57 +0000564 close(fd_msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000565 return -1;
566 }
567
568 close(fd_msr);
569
Uwe Hermann394131e2008-10-18 21:14:13 +0000570#undef MSR_RCONF_DEFAULT
571#undef MSR_NORF_CTL
Lane Brooksd54958a2007-11-13 16:45:22 +0000572 return 0;
573}
574
Uwe Hermann372eeb52007-12-04 21:49:06 +0000575static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000576{
Ollie Lho184a4042005-11-26 21:55:36 +0000577 uint8_t new;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000578
Ollie Lhocbbf1252004-03-17 22:22:08 +0000579 pci_write_byte(dev, 0x52, 0xee);
580
581 new = pci_read_byte(dev, 0x52);
582
583 if (new != 0xee) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000584 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000585 return -1;
586 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000587
Ollie Lhocbbf1252004-03-17 22:22:08 +0000588 return 0;
589}
590
Uwe Hermann372eeb52007-12-04 21:49:06 +0000591static int enable_flash_sis5595(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000592{
Ollie Lho184a4042005-11-26 21:55:36 +0000593 uint8_t new, newer;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000594
Ollie Lhocbbf1252004-03-17 22:22:08 +0000595 new = pci_read_byte(dev, 0x45);
596
Uwe Hermann372eeb52007-12-04 21:49:06 +0000597 new &= (~0x20); /* Clear bit 5. */
598 new |= 0x4; /* Set bit 2. */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000599
600 pci_write_byte(dev, 0x45, new);
601
602 newer = pci_read_byte(dev, 0x45);
603 if (newer != new) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000604 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000605 printf("Stuck at 0x%x\n", newer);
606 return -1;
607 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000608
Urja Rannikkoa88daa72008-10-18 13:54:30 +0000609 /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
Uwe Hermann394131e2008-10-18 21:14:13 +0000610 new = pci_read_byte(dev, 0x40);
Urja Rannikkoa88daa72008-10-18 13:54:30 +0000611 new &= 0xFB;
612 new |= 0x3;
Uwe Hermann394131e2008-10-18 21:14:13 +0000613 pci_write_byte(dev, 0x40, new);
614 newer = pci_read_byte(dev, 0x40);
Urja Rannikkoa88daa72008-10-18 13:54:30 +0000615 if (newer != new) {
616 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
617 printf("Stuck at 0x%x\n", newer);
618 return -1;
619 }
Ollie Lhocbbf1252004-03-17 22:22:08 +0000620 return 0;
621}
622
Uwe Hermann190f8492008-10-25 18:03:50 +0000623/* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000624static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000625{
Ollie Lho184a4042005-11-26 21:55:36 +0000626 uint8_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000627
Uwe Hermann372eeb52007-12-04 21:49:06 +0000628 /* Enable decoding at 0xffb00000 to 0xffffffff. */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000629 old = pci_read_byte(dev, 0x43);
Ollie Lhod11f3612004-12-07 17:19:04 +0000630 new = old | 0xC0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000631 if (new != old) {
632 pci_write_byte(dev, 0x43, new);
633 if (pci_read_byte(dev, 0x43) != new) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000634 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000635 }
636 }
637
Uwe Hermann190f8492008-10-25 18:03:50 +0000638 /* Enable 'ROM write' bit. */
Ollie Lho761bf1b2004-03-20 16:46:10 +0000639 old = pci_read_byte(dev, 0x40);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000640 new = old | 0x01;
641 if (new == old)
642 return 0;
643 pci_write_byte(dev, 0x40, new);
644
645 if (pci_read_byte(dev, 0x40) != new) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000646 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000647 return -1;
648 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000649
Ollie Lhocbbf1252004-03-17 22:22:08 +0000650 return 0;
651}
652
Marc Jones3af487d2008-10-15 17:50:29 +0000653static int enable_flash_sb600(struct pci_dev *dev, const char *name)
654{
Jason Wanga3f04be2008-11-28 21:36:51 +0000655 uint32_t tmp, low_bits, num;
Marc Jones3af487d2008-10-15 17:50:29 +0000656 uint8_t reg;
657
Jason Wanga3f04be2008-11-28 21:36:51 +0000658 low_bits = tmp = pci_read_long(dev, 0xa0);
659 low_bits &= ~0xffffc000; /* for mmap aligning requirements */
660 low_bits &= 0xfffffff0; /* remove low 4 bits */
661 tmp &= 0xffffc000;
662 printf_debug("SPI base address is at 0x%x\n", tmp + low_bits);
663
664 sb600_spibar = mmap(0, 0x4000, PROT_READ | PROT_WRITE, MAP_SHARED,
665 fd_mem, (off_t)tmp);
666 if (sb600_spibar == MAP_FAILED) {
667 perror("Can't mmap memory using " MEM_DEV);
668 exit(1);
Marc Jones3af487d2008-10-15 17:50:29 +0000669 }
Jason Wanga3f04be2008-11-28 21:36:51 +0000670 sb600_spibar += low_bits;
671
672 /* Clear ROM protect 0-3. */
673 for (reg = 0x50; reg < 0x60; reg += 4) {
674 num = pci_read_long(dev, reg);
675 num &= 0xfffffffc;
676 pci_write_byte(dev, reg, num);
677 }
678
679 flashbus = BUS_TYPE_SB600_SPI;
680
681 /* Enable SPI ROM in SB600 PM register. */
682 OUTB(0x8f, 0xcd6);
683 OUTB(0x0e, 0xcd7);
Marc Jones3af487d2008-10-15 17:50:29 +0000684
685 return 0;
686}
687
Uwe Hermann372eeb52007-12-04 21:49:06 +0000688static int enable_flash_ck804(struct pci_dev *dev, const char *name)
Yinghai Lu952dfce2005-07-06 17:13:46 +0000689{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000690 uint8_t old, new;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000691
Uwe Hermanna7e05482007-05-09 10:17:44 +0000692 old = pci_read_byte(dev, 0x88);
693 new = old | 0xc0;
694 if (new != old) {
695 pci_write_byte(dev, 0x88, new);
696 if (pci_read_byte(dev, 0x88) != new) {
697 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name);
698 }
699 }
Yinghai Lu952dfce2005-07-06 17:13:46 +0000700
Uwe Hermanna7e05482007-05-09 10:17:44 +0000701 old = pci_read_byte(dev, 0x6d);
702 new = old | 0x01;
703 if (new == old)
704 return 0;
705 pci_write_byte(dev, 0x6d, new);
706
707 if (pci_read_byte(dev, 0x6d) != new) {
708 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
709 return -1;
710 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000711
Uwe Hermanna7e05482007-05-09 10:17:44 +0000712 return 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000713}
714
Uwe Hermann372eeb52007-12-04 21:49:06 +0000715/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
716static int enable_flash_sb400(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000717{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000718 uint8_t tmp;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000719 struct pci_filter f;
720 struct pci_dev *smbusdev;
721
Uwe Hermann372eeb52007-12-04 21:49:06 +0000722 /* Look for the SMBus device. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000723 pci_filter_init((struct pci_access *)0, &f);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000724 f.vendor = 0x1002;
725 f.device = 0x4372;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000726
Stefan Reinauer86de2832006-03-31 11:26:55 +0000727 for (smbusdev = pacc->devices; smbusdev; smbusdev = smbusdev->next) {
Uwe Hermann394131e2008-10-18 21:14:13 +0000728 if (pci_filter_match(&f, smbusdev))
Stefan Reinauer86de2832006-03-31 11:26:55 +0000729 break;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000730 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000731
Uwe Hermanna7e05482007-05-09 10:17:44 +0000732 if (!smbusdev) {
Uwe Hermann372eeb52007-12-04 21:49:06 +0000733 fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n");
Stefan Reinauer86de2832006-03-31 11:26:55 +0000734 exit(1);
735 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000736
Uwe Hermann372eeb52007-12-04 21:49:06 +0000737 /* Enable some SMBus stuff. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000738 tmp = pci_read_byte(smbusdev, 0x79);
739 tmp |= 0x01;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000740 pci_write_byte(smbusdev, 0x79, tmp);
741
Uwe Hermann372eeb52007-12-04 21:49:06 +0000742 /* Change southbridge. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000743 tmp = pci_read_byte(dev, 0x48);
744 tmp |= 0x21;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000745 pci_write_byte(dev, 0x48, tmp);
746
Uwe Hermann372eeb52007-12-04 21:49:06 +0000747 /* Now become a bit silly. */
Andriy Gapon65c1b862008-05-22 13:22:45 +0000748 tmp = INB(0xc6f);
749 OUTB(tmp, 0xeb);
750 OUTB(tmp, 0xeb);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000751 tmp |= 0x40;
Andriy Gapon65c1b862008-05-22 13:22:45 +0000752 OUTB(tmp, 0xc6f);
753 OUTB(tmp, 0xeb);
754 OUTB(tmp, 0xeb);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000755
756 return 0;
757}
758
Uwe Hermann372eeb52007-12-04 21:49:06 +0000759static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
Yinghai Luca782972007-01-22 20:21:17 +0000760{
Uwe Hermann372eeb52007-12-04 21:49:06 +0000761 uint8_t old, new, byte;
762 uint16_t word;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000763
Uwe Hermann372eeb52007-12-04 21:49:06 +0000764 /* Set the 0-16 MB enable bits. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000765 byte = pci_read_byte(dev, 0x88);
766 byte |= 0xff; /* 256K */
767 pci_write_byte(dev, 0x88, byte);
768 byte = pci_read_byte(dev, 0x8c);
769 byte |= 0xff; /* 1M */
770 pci_write_byte(dev, 0x8c, byte);
771 word = pci_read_word(dev, 0x90);
Carl-Daniel Hailfingerdca0ab12007-10-17 22:30:07 +0000772 word |= 0x7fff; /* 16M */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000773 pci_write_word(dev, 0x90, word);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000774
Uwe Hermanna7e05482007-05-09 10:17:44 +0000775 old = pci_read_byte(dev, 0x6d);
776 new = old | 0x01;
777 if (new == old)
778 return 0;
779 pci_write_byte(dev, 0x6d, new);
Yinghai Luca782972007-01-22 20:21:17 +0000780
Uwe Hermanna7e05482007-05-09 10:17:44 +0000781 if (pci_read_byte(dev, 0x6d) != new) {
Uwe Hermann394131e2008-10-18 21:14:13 +0000782 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000783 return -1;
784 }
Yinghai Luca782972007-01-22 20:21:17 +0000785
786 return 0;
Yinghai Luca782972007-01-22 20:21:17 +0000787}
788
Uwe Hermann372eeb52007-12-04 21:49:06 +0000789static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000790{
Uwe Hermanne823ee02007-06-05 15:02:18 +0000791 uint8_t byte;
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000792
Uwe Hermanne823ee02007-06-05 15:02:18 +0000793 /* Set the 4MB enable bit. */
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000794 byte = pci_read_byte(dev, 0x41);
795 byte |= 0x0e;
796 pci_write_byte(dev, 0x41, byte);
797
798 byte = pci_read_byte(dev, 0x43);
Uwe Hermannffec5f32007-08-23 16:08:21 +0000799 byte |= (1 << 4);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000800 pci_write_byte(dev, 0x43, byte);
801
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000802 return 0;
803}
804
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000805/**
806 * Usually on the x86 architectures (and on other PC-like platforms like some
807 * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
808 * Elan SC520 only a small piece of the system flash is mapped there, but the
809 * complete flash is mapped somewhere below 1G. The position can be determined
810 * by the BOOTCS PAR register.
811 */
812static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
813{
814 int i, bootcs_found = 0;
815 uint32_t parx = 0;
816 void *mmcr;
817
818 /* 1. Map MMCR */
819 mmcr = mmap(0, getpagesize(), PROT_WRITE | PROT_READ,
820 MAP_SHARED, fd_mem, (off_t)0xFFFEF000);
821
822 if (mmcr == MAP_FAILED) {
823 perror("Can't mmap Elan SC520 specific registers using " MEM_DEV);
824 exit(1);
825 }
826
827 /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for
828 * BOOTCS region (PARx[31:29] = 100b)e
829 */
830 for (i = 0x88; i <= 0xc4; i += 4) {
831 parx = *(volatile uint32_t *)(mmcr + i);
832 if ((parx >> 29) == 4) {
833 bootcs_found = 1;
834 break; /* BOOTCS found */
835 }
836 }
837
838 /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0]
839 * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0]
840 */
841 if (bootcs_found) {
842 if (parx & (1 << 25)) {
843 parx &= (1 << 14) - 1; /* Mask [13:0] */
844 flashbase = parx << 16;
845 } else {
846 parx &= (1 << 18) - 1; /* Mask [17:0] */
847 flashbase = parx << 12;
848 }
849 } else {
850 printf("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n");
851 }
852
853 /* 4. Clean up */
854 munmap (mmcr, getpagesize());
855 return 0;
856}
857
Ollie Lhocbbf1252004-03-17 22:22:08 +0000858typedef struct penable {
Uwe Hermann372eeb52007-12-04 21:49:06 +0000859 uint16_t vendor, device;
860 const char *name;
861 int (*doit) (struct pci_dev *dev, const char *name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000862} FLASH_ENABLE;
863
Uwe Hermann372eeb52007-12-04 21:49:06 +0000864static const FLASH_ENABLE enables[] = {
Uwe Hermanneac10162008-03-13 18:52:51 +0000865 {0x1039, 0x0630, "SiS630", enable_flash_sis630},
Uwe Hermann87203452008-10-26 18:40:42 +0000866 {0x8086, 0x122e, "Intel PIIX", enable_flash_piix4},
Uwe Hermannc556d322008-10-28 11:50:05 +0000867 {0x8086, 0x1234, "Intel MPIIX", enable_flash_piix4},
Uwe Hermann87203452008-10-26 18:40:42 +0000868 {0x8086, 0x7000, "Intel PIIX3", enable_flash_piix4},
Uwe Hermanneac10162008-03-13 18:52:51 +0000869 {0x8086, 0x7110, "Intel PIIX4/4E/4M", enable_flash_piix4},
870 {0x8086, 0x7198, "Intel 440MX", enable_flash_piix4},
871 {0x8086, 0x2410, "Intel ICH", enable_flash_ich_4e},
872 {0x8086, 0x2420, "Intel ICH0", enable_flash_ich_4e},
873 {0x8086, 0x2440, "Intel ICH2", enable_flash_ich_4e},
874 {0x8086, 0x244c, "Intel ICH2-M", enable_flash_ich_4e},
875 {0x8086, 0x2480, "Intel ICH3-S", enable_flash_ich_4e},
876 {0x8086, 0x248c, "Intel ICH3-M", enable_flash_ich_4e},
877 {0x8086, 0x24c0, "Intel ICH4/ICH4-L", enable_flash_ich_4e},
878 {0x8086, 0x24cc, "Intel ICH4-M", enable_flash_ich_4e},
879 {0x8086, 0x24d0, "Intel ICH5/ICH5R", enable_flash_ich_4e},
Claus Gindharta00e2a02008-05-14 12:22:38 +0000880 {0x8086, 0x25a1, "Intel 6300ESB", enable_flash_ich_4e},
Uwe Hermanneac10162008-03-13 18:52:51 +0000881 {0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc},
882 {0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc},
Ed Swierkb759db22008-10-29 14:54:36 +0000883 {0x8086, 0x5031, "Intel EP80579", enable_flash_ich7},
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000884 {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich7},
885 {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich7},
886 {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich7},
887 {0x8086, 0x27bd, "Intel ICH7MDH", enable_flash_ich7},
888 {0x8086, 0x2810, "Intel ICH8/ICH8R", enable_flash_ich8},
889 {0x8086, 0x2811, "Intel ICH8M-E", enable_flash_ich8},
890 {0x8086, 0x2812, "Intel ICH8DH", enable_flash_ich8},
891 {0x8086, 0x2814, "Intel ICH8DO", enable_flash_ich8},
892 {0x8086, 0x2815, "Intel ICH8M", enable_flash_ich8},
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000893 {0x8086, 0x2912, "Intel ICH9DH", enable_flash_ich9},
894 {0x8086, 0x2914, "Intel ICH9DO", enable_flash_ich9},
895 {0x8086, 0x2916, "Intel ICH9R", enable_flash_ich9},
896 {0x8086, 0x2917, "Intel ICH9M-E", enable_flash_ich9},
897 {0x8086, 0x2918, "Intel ICH9", enable_flash_ich9},
898 {0x8086, 0x2919, "Intel ICH9M", enable_flash_ich9},
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000899 {0x8086, 0x3a14, "Intel ICH10DO", enable_flash_ich10},
900 {0x8086, 0x3a16, "Intel ICH10R", enable_flash_ich10},
901 {0x8086, 0x3a18, "Intel ICH10", enable_flash_ich10},
902 {0x8086, 0x3a1a, "Intel ICH10D", enable_flash_ich10},
Uwe Hermanneac10162008-03-13 18:52:51 +0000903 {0x1106, 0x8231, "VIA VT8231", enable_flash_vt823x},
904 {0x1106, 0x3177, "VIA VT8235", enable_flash_vt823x},
905 {0x1106, 0x3227, "VIA VT8237", enable_flash_vt823x},
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000906 {0x1106, 0x3372, "VIA VT8237S", enable_flash_vt8237s_spi},
Uwe Hermanneac10162008-03-13 18:52:51 +0000907 {0x1106, 0x8324, "VIA CX700", enable_flash_vt823x},
Uwe Hermann190f8492008-10-25 18:03:50 +0000908 {0x1106, 0x0586, "VIA VT82C586A/B", enable_flash_amd8111},
909 {0x1106, 0x0686, "VIA VT82C686A/B", enable_flash_amd8111},
Uwe Hermanneac10162008-03-13 18:52:51 +0000910 {0x1078, 0x0100, "AMD CS5530(A)", enable_flash_cs5530},
911 {0x100b, 0x0510, "AMD SC1100", enable_flash_sc1100},
912 {0x1039, 0x0008, "SiS5595", enable_flash_sis5595},
913 {0x1022, 0x2080, "AMD CS5536", enable_flash_cs5536},
914 {0x1022, 0x7468, "AMD8111", enable_flash_amd8111},
Marc Jones3af487d2008-10-15 17:50:29 +0000915 {0x1002, 0x438D, "ATI(AMD) SB600", enable_flash_sb600},
Niels Ole Salscheiderf63c0dc2008-12-05 11:58:43 +0000916 {0x1002, 0x439d, "ATI(AMD) SB700", enable_flash_sb600},
Uwe Hermanneac10162008-03-13 18:52:51 +0000917 {0x10B9, 0x1533, "ALi M1533", enable_flash_ali_m1533},
918 {0x10de, 0x0050, "NVIDIA CK804", enable_flash_ck804}, /* LPC */
919 {0x10de, 0x0051, "NVIDIA CK804", enable_flash_ck804}, /* Pro */
920 /* Slave, should not be here, to fix known bug for A01. */
921 {0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804},
922 {0x10de, 0x0260, "NVIDIA MCP51", enable_flash_ck804},
923 {0x10de, 0x0261, "NVIDIA MCP51", enable_flash_ck804},
924 {0x10de, 0x0262, "NVIDIA MCP51", enable_flash_ck804},
925 {0x10de, 0x0263, "NVIDIA MCP51", enable_flash_ck804},
926 {0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, /* M57SLI*/
927 {0x10de, 0x0361, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
928 {0x10de, 0x0362, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
929 {0x10de, 0x0363, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
930 {0x10de, 0x0364, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
931 {0x10de, 0x0365, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
932 {0x10de, 0x0366, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
933 {0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, /* Pro */
Stefan Reinauer7f274642008-07-05 09:48:30 +0000934 {0x10de, 0x0548, "NVIDIA MCP67", enable_flash_mcp55},
Uwe Hermanneac10162008-03-13 18:52:51 +0000935 {0x1002, 0x4377, "ATI SB400", enable_flash_sb400},
936 {0x1166, 0x0205, "Broadcom HT-1000", enable_flash_ht1000},
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000937 {0x1022, 0x3000, "AMD Elan SC520", get_flashbase_sc520},
Ollie Lhocbbf1252004-03-17 22:22:08 +0000938};
Ollie Lho761bf1b2004-03-20 16:46:10 +0000939
Uwe Hermanne5ac1642008-03-12 11:54:51 +0000940void print_supported_chipsets(void)
941{
942 int i;
943
944 printf("\nSupported chipsets:\n\n");
945
946 for (i = 0; i < ARRAY_SIZE(enables); i++)
947 printf("%s (%04x:%04x)\n", enables[i].name,
948 enables[i].vendor, enables[i].device);
949}
950
Uwe Hermanna7e05482007-05-09 10:17:44 +0000951int chipset_flash_enable(void)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000952{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000953 struct pci_dev *dev = 0;
Uwe Hermann372eeb52007-12-04 21:49:06 +0000954 int ret = -2; /* Nothing! */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000955 int i;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000956
Uwe Hermann372eeb52007-12-04 21:49:06 +0000957 /* Now let's try to find the chipset we have... */
Uwe Hermanne5ac1642008-03-12 11:54:51 +0000958 for (i = 0; i < ARRAY_SIZE(enables); i++) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000959 dev = pci_dev_find(enables[i].vendor, enables[i].device);
960 if (dev)
961 break;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000962 }
963
Uwe Hermanna7e05482007-05-09 10:17:44 +0000964 if (dev) {
Uwe Hermanna502dce2007-10-17 23:55:15 +0000965 printf("Found chipset \"%s\", enabling flash write... ",
Uwe Hermanna7e05482007-05-09 10:17:44 +0000966 enables[i].name);
967
968 ret = enables[i].doit(dev, enables[i].name);
969 if (ret)
Uwe Hermanna502dce2007-10-17 23:55:15 +0000970 printf("FAILED!\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +0000971 else
Uwe Hermannac309342007-10-10 17:42:20 +0000972 printf("OK.\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +0000973 }
974
975 return ret;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000976}