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Ollie Lho184a4042005-11-26 21:55:36 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ollie Lho184a4042005-11-26 21:55:36 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Stefan Reinauer8fa64812009-08-12 09:27:45 +00005 * Copyright (C) 2005-2009 coresystems GmbH
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00007 * Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger
Adam Jurkowskie4984102009-12-21 15:30:46 +00008 * Copyright (C) 2009 Kontron Modular Computers GmbH
Ollie Lho184a4042005-11-26 21:55:36 +00009 *
Uwe Hermannd1107642007-08-29 17:52:32 +000010 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
Ollie Lho184a4042005-11-26 21:55:36 +000013 *
Uwe Hermannd1107642007-08-29 17:52:32 +000014 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24/*
25 * Contains the chipset specific flash enables.
Ollie Lho184a4042005-11-26 21:55:36 +000026 */
27
Lane Brooksd54958a2007-11-13 16:45:22 +000028#define _LARGEFILE64_SOURCE
29
Carl-Daniel Hailfinger831e8f42010-05-30 22:24:40 +000030#include <unistd.h>
Ollie Lhocbbf1252004-03-17 22:22:08 +000031#include <stdlib.h>
Uwe Hermanne8ba5382009-05-22 11:37:27 +000032#include <string.h>
Lane Brooksd54958a2007-11-13 16:45:22 +000033#include <sys/types.h>
34#include <sys/stat.h>
35#include <fcntl.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000036#include "flash.h"
Stefan Reinauer86de2832006-03-31 11:26:55 +000037
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +000038#if defined(__i386__) || defined(__x86_64__)
39
Michael Karcher89bed6d2010-06-13 10:16:12 +000040#define NOT_DONE_YET 1
41
Uwe Hermann372eeb52007-12-04 21:49:06 +000042static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
Luc Verhaegen6b141752007-05-20 16:16:13 +000043{
44 uint8_t tmp;
45
Uwe Hermann372eeb52007-12-04 21:49:06 +000046 /*
47 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
48 * 0xFFFE0000-0xFFFFFFFF ROM select enable.
49 */
Luc Verhaegen6b141752007-05-20 16:16:13 +000050 tmp = pci_read_byte(dev, 0x47);
51 tmp |= 0x46;
52 pci_write_byte(dev, 0x47, tmp);
53
54 return 0;
55}
56
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000057static int enable_flash_sis85c496(struct pci_dev *dev, const char *name)
58{
59 uint8_t tmp;
60
61 tmp = pci_read_byte(dev, 0xd0);
62 tmp |= 0xf8;
63 pci_write_byte(dev, 0xd0, tmp);
64
65 return 0;
66}
67
68static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name)
69{
70 uint8_t new, newer;
71
72 /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
73 /* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
74 new = pci_read_byte(dev, 0x40);
75 new &= (~0x04); /* No idea why we clear bit 2. */
76 new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */
77 pci_write_byte(dev, 0x40, new);
78 newer = pci_read_byte(dev, 0x40);
79 if (newer != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +000080 msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
81 msg_pinfo("Stuck at 0x%x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000082 return -1;
83 }
84 return 0;
85}
86
87static struct pci_dev *find_southbridge(uint16_t vendor, const char *name)
88{
89 struct pci_dev *sbdev;
90
91 sbdev = pci_dev_find_vendorclass(vendor, 0x0601);
92 if (!sbdev)
93 sbdev = pci_dev_find_vendorclass(vendor, 0x0680);
94 if (!sbdev)
95 sbdev = pci_dev_find_vendorclass(vendor, 0x0000);
96 if (!sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +000097 msg_perr("No southbridge found for %s!\n", name);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000098 if (sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +000099 msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n",
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000100 sbdev->vendor_id, sbdev->device_id,
101 sbdev->bus, sbdev->dev, sbdev->func);
102 return sbdev;
103}
104
105static int enable_flash_sis501(struct pci_dev *dev, const char *name)
106{
107 uint8_t tmp;
108 int ret = 0;
109 struct pci_dev *sbdev;
110
111 sbdev = find_southbridge(dev->vendor_id, name);
112 if (!sbdev)
113 return -1;
114
115 ret = enable_flash_sis_mapping(sbdev, name);
116
117 tmp = sio_read(0x22, 0x80);
118 tmp &= (~0x20);
119 tmp |= 0x4;
120 sio_write(0x22, 0x80, tmp);
121
122 tmp = sio_read(0x22, 0x70);
123 tmp &= (~0x20);
124 tmp |= 0x4;
125 sio_write(0x22, 0x70, tmp);
126
127 return ret;
128}
129
130static int enable_flash_sis5511(struct pci_dev *dev, const char *name)
131{
132 uint8_t tmp;
133 int ret = 0;
134 struct pci_dev *sbdev;
135
136 sbdev = find_southbridge(dev->vendor_id, name);
137 if (!sbdev)
138 return -1;
139
140 ret = enable_flash_sis_mapping(sbdev, name);
141
142 tmp = sio_read(0x22, 0x50);
143 tmp &= (~0x20);
144 tmp |= 0x4;
145 sio_write(0x22, 0x50, tmp);
146
147 return ret;
148}
149
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000150static int enable_flash_sis530(struct pci_dev *dev, const char *name)
151{
152 uint8_t new, newer;
153 int ret = 0;
154 struct pci_dev *sbdev;
155
156 sbdev = find_southbridge(dev->vendor_id, name);
157 if (!sbdev)
158 return -1;
159
160 ret = enable_flash_sis_mapping(sbdev, name);
161
162 new = pci_read_byte(sbdev, 0x45);
163 new &= (~0x20);
164 new |= 0x4;
165 pci_write_byte(sbdev, 0x45, new);
Luc Verhaegen9cce2f52010-01-10 15:01:08 +0000166 newer = pci_read_byte(sbdev, 0x45);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000167 if (newer != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000168 msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
169 msg_pinfo("Stuck at 0x%x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000170 ret = -1;
171 }
172
173 return ret;
174}
175
176static int enable_flash_sis540(struct pci_dev *dev, const char *name)
177{
178 uint8_t new, newer;
179 int ret = 0;
180 struct pci_dev *sbdev;
181
182 sbdev = find_southbridge(dev->vendor_id, name);
183 if (!sbdev)
184 return -1;
185
186 ret = enable_flash_sis_mapping(sbdev, name);
187
188 new = pci_read_byte(sbdev, 0x45);
189 new &= (~0x80);
190 new |= 0x40;
191 pci_write_byte(sbdev, 0x45, new);
Luc Verhaegen9cce2f52010-01-10 15:01:08 +0000192 newer = pci_read_byte(sbdev, 0x45);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000193 if (newer != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000194 msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
195 msg_pinfo("Stuck at 0x%x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000196 ret = -1;
197 }
198
199 return ret;
200}
201
Uwe Hermann987942d2006-11-07 11:16:21 +0000202/* Datasheet:
203 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
204 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
205 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
206 * - Order Number: 290562-001
207 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000208static int enable_flash_piix4(struct pci_dev *dev, const char *name)
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000209{
210 uint16_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000211 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000212
Maciej Pijankaa661e152009-12-08 17:26:24 +0000213 buses_supported = CHIP_BUSTYPE_PARALLEL;
214
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000215 old = pci_read_word(dev, xbcs);
216
217 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
Uwe Hermanna7e05482007-05-09 10:17:44 +0000218 * FFF00000-FFF7FFFF are forwarded to ISA).
Uwe Hermannc556d322008-10-28 11:50:05 +0000219 * Note: This bit is reserved on PIIX/PIIX3/MPIIX.
Uwe Hermanna7e05482007-05-09 10:17:44 +0000220 * Set bit 7: Extended BIOS Enable (PCI master accesses to
221 * FFF80000-FFFDFFFF are forwarded to ISA).
222 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
223 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
224 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
225 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
226 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
227 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
228 */
Uwe Hermannc556d322008-10-28 11:50:05 +0000229 if (dev->device_id == 0x122e || dev->device_id == 0x7000
230 || dev->device_id == 0x1234)
231 new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
Uwe Hermann87203452008-10-26 18:40:42 +0000232 else
233 new = old | 0x02c4;
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000234
235 if (new == old)
236 return 0;
237
238 pci_write_word(dev, xbcs, new);
239
240 if (pci_read_word(dev, xbcs) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000241 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000242 return -1;
243 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000244
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000245 return 0;
246}
247
Uwe Hermann372eeb52007-12-04 21:49:06 +0000248/*
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000249 * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet"
250 * http://download.intel.com/design/chipsets/datashts/30701303.pdf
Uwe Hermann372eeb52007-12-04 21:49:06 +0000251 */
252static int enable_flash_ich(struct pci_dev *dev, const char *name,
253 int bios_cntl)
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000254{
Ollie Lho184a4042005-11-26 21:55:36 +0000255 uint8_t old, new;
Stefan Reinauereb366472006-09-06 15:48:48 +0000256
Uwe Hermann372eeb52007-12-04 21:49:06 +0000257 /*
258 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
Uwe Hermanna7e05482007-05-09 10:17:44 +0000259 * just treating it as 8 bit wide seems to work fine in practice.
Stefan Reinauereb366472006-09-06 15:48:48 +0000260 */
Stefan Reinauer86de2832006-03-31 11:26:55 +0000261 old = pci_read_byte(dev, bios_cntl);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000262
Sean Nelson316a29f2010-05-07 20:09:04 +0000263 msg_pdbg("\nBIOS Lock Enable: %sabled, ",
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000264 (old & (1 << 1)) ? "en" : "dis");
Sean Nelson316a29f2010-05-07 20:09:04 +0000265 msg_pdbg("BIOS Write Enable: %sabled, ",
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000266 (old & (1 << 0)) ? "en" : "dis");
Sean Nelson316a29f2010-05-07 20:09:04 +0000267 msg_pdbg("BIOS_CNTL is 0x%x\n", old);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000268
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000269 new = old | 1;
270
271 if (new == old)
272 return 0;
273
Stefan Reinauer86de2832006-03-31 11:26:55 +0000274 pci_write_byte(dev, bios_cntl, new);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000275
Stefan Reinauer86de2832006-03-31 11:26:55 +0000276 if (pci_read_byte(dev, bios_cntl) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000277 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000278 return -1;
279 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000280
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000281 return 0;
282}
283
Uwe Hermann372eeb52007-12-04 21:49:06 +0000284static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000285{
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000286 /*
287 * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and
288 * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and
289 * FB_DEC_EN2.
290 */
Stefan Reinauereb366472006-09-06 15:48:48 +0000291 return enable_flash_ich(dev, name, 0x4e);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000292}
293
Uwe Hermann372eeb52007-12-04 21:49:06 +0000294static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000295{
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000296 uint32_t fwh_conf;
297 int i;
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000298 char *idsel = NULL;
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000299 int tmp;
300 int max_decode_fwh_idsel = 0;
301 int max_decode_fwh_decode = 0;
302 int contiguous = 1;
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000303
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000304 if (programmer_param)
305 idsel = strstr(programmer_param, "fwh_idsel=");
306
307 if (idsel) {
308 idsel += strlen("fwh_idsel=");
309 fwh_conf = (uint32_t)strtoul(idsel, NULL, 0);
310
311 /* FIXME: Need to undo this on shutdown. */
Sean Nelson316a29f2010-05-07 20:09:04 +0000312 msg_pinfo("\nSetting IDSEL=0x%x for top 16 MB", fwh_conf);
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000313 pci_write_long(dev, 0xd0, fwh_conf);
314 pci_write_word(dev, 0xd4, fwh_conf);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000315 /* FIXME: Decode settings are not changed. */
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000316 }
317
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000318 /* Ignore all legacy ranges below 1 MB.
319 * We currently only support flashing the chip which responds to
320 * IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations
321 * have to be adjusted.
322 */
323 /* FWH_SEL1 */
324 fwh_conf = pci_read_long(dev, 0xd0);
325 for (i = 7; i >= 0; i--) {
326 tmp = (fwh_conf >> (i * 4)) & 0xf;
Sean Nelson316a29f2010-05-07 20:09:04 +0000327 msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000328 (0x1ff8 + i) * 0x80000,
329 (0x1ff0 + i) * 0x80000,
330 tmp);
331 if ((tmp == 0) && contiguous) {
332 max_decode_fwh_idsel = (8 - i) * 0x80000;
333 } else {
334 contiguous = 0;
335 }
336 }
337 /* FWH_SEL2 */
338 fwh_conf = pci_read_word(dev, 0xd4);
339 for (i = 3; i >= 0; i--) {
340 tmp = (fwh_conf >> (i * 4)) & 0xf;
Sean Nelson316a29f2010-05-07 20:09:04 +0000341 msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000342 (0xff4 + i) * 0x100000,
343 (0xff0 + i) * 0x100000,
344 tmp);
345 if ((tmp == 0) && contiguous) {
346 max_decode_fwh_idsel = (8 - i) * 0x100000;
347 } else {
348 contiguous = 0;
349 }
350 }
351 contiguous = 1;
352 /* FWH_DEC_EN1 */
353 fwh_conf = pci_read_word(dev, 0xd8);
354 for (i = 7; i >= 0; i--) {
355 tmp = (fwh_conf >> (i + 0x8)) & 0x1;
Sean Nelson316a29f2010-05-07 20:09:04 +0000356 msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled",
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000357 (0x1ff8 + i) * 0x80000,
358 (0x1ff0 + i) * 0x80000,
359 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000360 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000361 max_decode_fwh_decode = (8 - i) * 0x80000;
362 } else {
363 contiguous = 0;
364 }
365 }
366 for (i = 3; i >= 0; i--) {
367 tmp = (fwh_conf >> i) & 0x1;
Sean Nelson316a29f2010-05-07 20:09:04 +0000368 msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled",
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000369 (0xff4 + i) * 0x100000,
370 (0xff0 + i) * 0x100000,
371 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000372 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000373 max_decode_fwh_decode = (8 - i) * 0x100000;
374 } else {
375 contiguous = 0;
376 }
377 }
378 max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode);
Sean Nelson316a29f2010-05-07 20:09:04 +0000379 msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000380
381 /* If we're called by enable_flash_ich_dc_spi, it will override
382 * buses_supported anyway.
383 */
384 buses_supported = CHIP_BUSTYPE_FWH;
Stefan Reinauereb366472006-09-06 15:48:48 +0000385 return enable_flash_ich(dev, name, 0xdc);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000386}
387
Adam Jurkowskie4984102009-12-21 15:30:46 +0000388static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
389{
390 uint16_t old, new;
391 int err;
392
393 if ((err = enable_flash_ich(dev, name, 0xd8)) != 0)
394 return err;
395
396 old = pci_read_byte(dev, 0xd9);
Sean Nelson316a29f2010-05-07 20:09:04 +0000397 msg_pdbg("BIOS Prefetch Enable: %sabled, ",
Adam Jurkowskie4984102009-12-21 15:30:46 +0000398 (old & 1) ? "en" : "dis");
399 new = old & ~1;
400
401 if (new != old)
402 pci_write_byte(dev, 0xd9, new);
403
404 return 0;
405}
406
407
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000408#define ICH_STRAP_RSVD 0x00
409#define ICH_STRAP_SPI 0x01
410#define ICH_STRAP_PCI 0x02
411#define ICH_STRAP_LPC 0x03
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000412
Uwe Hermann394131e2008-10-18 21:14:13 +0000413static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
414{
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000415 uint32_t mmio_base;
416
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000417 /* Do we really need no write enable? */
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000418 mmio_base = (pci_read_long(dev, 0xbc)) << 8;
Sean Nelson316a29f2010-05-07 20:09:04 +0000419 msg_pdbg("MMIO base at = 0x%x\n", mmio_base);
Stefan Reinauer0593f212009-01-26 01:10:48 +0000420 spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70);
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000421
Sean Nelson316a29f2010-05-07 20:09:04 +0000422 msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000423 mmio_readw(spibar + 0x6c));
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000424
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000425 /* Not sure if it speaks all these bus protocols. */
426 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000427 spi_controller = SPI_CONTROLLER_VIA;
Rudolf Marek0c2029f2009-02-01 18:40:50 +0000428 ich_init_opcodes();
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000429
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000430 return 0;
431}
432
Uwe Hermann394131e2008-10-18 21:14:13 +0000433static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
434 int ich_generation)
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000435{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000436 int ret, i;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000437 uint8_t old, new, bbs, buc;
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000438 uint16_t spibar_offset, tmp2;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000439 uint32_t tmp, gcs;
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000440 void *rcrb;
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000441 //TODO: These names are incorrect for EP80579. For that, the solution would look like the commented line
442 //static const char *straps_names[] = {"SPI", "reserved", "reserved", "LPC" };
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000443 static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" };
Uwe Hermann394131e2008-10-18 21:14:13 +0000444
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000445 /* Enable Flash Writes */
446 ret = enable_flash_ich_dc(dev, name);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000447
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000448 /* Get physical address of Root Complex Register Block */
449 tmp = pci_read_long(dev, 0xf0) & 0xffffc000;
Sean Nelson316a29f2010-05-07 20:09:04 +0000450 msg_pdbg("\nRoot Complex Register Block address = 0x%x\n", tmp);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000451
452 /* Map RCBA to virtual memory */
Stefan Reinauer0593f212009-01-26 01:10:48 +0000453 rcrb = physmap("ICH RCRB", tmp, 0x4000);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000454
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000455 gcs = mmio_readl(rcrb + 0x3410);
Sean Nelson316a29f2010-05-07 20:09:04 +0000456 msg_pdbg("GCS = 0x%x: ", gcs);
457 msg_pdbg("BIOS Interface Lock-Down: %sabled, ",
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000458 (gcs & 0x1) ? "en" : "dis");
459 bbs = (gcs >> 10) & 0x3;
Sean Nelson316a29f2010-05-07 20:09:04 +0000460 msg_pdbg("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000461
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000462 buc = mmio_readb(rcrb + 0x3414);
Sean Nelson316a29f2010-05-07 20:09:04 +0000463 msg_pdbg("Top Swap : %s\n",
Uwe Hermann394131e2008-10-18 21:14:13 +0000464 (buc & 1) ? "enabled (A16 inverted)" : "not enabled");
Stefan Reinauera9424d52008-06-27 16:28:34 +0000465
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000466 /* It seems the ICH7 does not support SPI and LPC chips at the same
467 * time. At least not with our current code. So we prevent searching
468 * on ICH7 when the southbridge is strapped to LPC
469 */
470
471 if (ich_generation == 7 && bbs == ICH_STRAP_LPC) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000472 buses_supported = CHIP_BUSTYPE_FWH;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000473 /* No further SPI initialization required */
474 return ret;
475 }
476
477 switch (ich_generation) {
478 case 7:
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000479 buses_supported = CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000480 spi_controller = SPI_CONTROLLER_ICH7;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000481 spibar_offset = 0x3020;
482 break;
483 case 8:
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000484 buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000485 spi_controller = SPI_CONTROLLER_ICH9;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000486 spibar_offset = 0x3020;
487 break;
488 case 9:
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000489 case 10:
Uwe Hermann394131e2008-10-18 21:14:13 +0000490 default: /* Future version might behave the same */
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000491 buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000492 spi_controller = SPI_CONTROLLER_ICH9;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000493 spibar_offset = 0x3800;
494 break;
495 }
496
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000497 /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
Sean Nelson316a29f2010-05-07 20:09:04 +0000498 msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000499
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000500 /* Assign Virtual Address */
Uwe Hermann394131e2008-10-18 21:14:13 +0000501 spibar = rcrb + spibar_offset;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000502
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000503 switch (spi_controller) {
504 case SPI_CONTROLLER_ICH7:
Sean Nelson316a29f2010-05-07 20:09:04 +0000505 msg_pdbg("0x00: 0x%04x (SPIS)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000506 mmio_readw(spibar + 0));
Sean Nelson316a29f2010-05-07 20:09:04 +0000507 msg_pdbg("0x02: 0x%04x (SPIC)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000508 mmio_readw(spibar + 2));
Sean Nelson316a29f2010-05-07 20:09:04 +0000509 msg_pdbg("0x04: 0x%08x (SPIA)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000510 mmio_readl(spibar + 4));
Uwe Hermann394131e2008-10-18 21:14:13 +0000511 for (i = 0; i < 8; i++) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000512 int offs;
513 offs = 8 + (i * 8);
Sean Nelson316a29f2010-05-07 20:09:04 +0000514 msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs,
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000515 mmio_readl(spibar + offs), i);
Sean Nelson316a29f2010-05-07 20:09:04 +0000516 msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000517 mmio_readl(spibar + offs + 4), i);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000518 }
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000519 ichspi_bbar = mmio_readl(spibar + 0x50);
Sean Nelson316a29f2010-05-07 20:09:04 +0000520 msg_pdbg("0x50: 0x%08x (BBAR)\n",
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000521 ichspi_bbar);
Sean Nelson316a29f2010-05-07 20:09:04 +0000522 msg_pdbg("0x54: 0x%04x (PREOP)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000523 mmio_readw(spibar + 0x54));
Sean Nelson316a29f2010-05-07 20:09:04 +0000524 msg_pdbg("0x56: 0x%04x (OPTYPE)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000525 mmio_readw(spibar + 0x56));
Sean Nelson316a29f2010-05-07 20:09:04 +0000526 msg_pdbg("0x58: 0x%08x (OPMENU)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000527 mmio_readl(spibar + 0x58));
Sean Nelson316a29f2010-05-07 20:09:04 +0000528 msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000529 mmio_readl(spibar + 0x5c));
Uwe Hermann394131e2008-10-18 21:14:13 +0000530 for (i = 0; i < 4; i++) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000531 int offs;
532 offs = 0x60 + (i * 4);
Sean Nelson316a29f2010-05-07 20:09:04 +0000533 msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000534 mmio_readl(spibar + offs), i);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000535 }
Sean Nelson316a29f2010-05-07 20:09:04 +0000536 msg_pdbg("\n");
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000537 if (mmio_readw(spibar) & (1 << 15)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000538 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000539 ichspi_lock = 1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000540 }
FENG yu ningf041e9b2008-12-15 02:32:11 +0000541 ich_init_opcodes();
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000542 break;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000543 case SPI_CONTROLLER_ICH9:
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000544 tmp2 = mmio_readw(spibar + 4);
Sean Nelson316a29f2010-05-07 20:09:04 +0000545 msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2);
546 msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1));
547 msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1);
548 msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1);
549 msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1);
550 msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3);
551 msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1);
552 msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1);
553 msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1);
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000554
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000555 tmp = mmio_readl(spibar + 0x50);
Sean Nelson316a29f2010-05-07 20:09:04 +0000556 msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp);
557 msg_pdbg("BMWAG %i, ", (tmp >> 24) & 0xff);
558 msg_pdbg("BMRAG %i, ", (tmp >> 16) & 0xff);
559 msg_pdbg("BRWA %i, ", (tmp >> 8) & 0xff);
560 msg_pdbg("BRRA %i\n", (tmp >> 0) & 0xff);
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000561
Sean Nelson316a29f2010-05-07 20:09:04 +0000562 msg_pdbg("0x54: 0x%08x (FREG0)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000563 mmio_readl(spibar + 0x54));
Sean Nelson316a29f2010-05-07 20:09:04 +0000564 msg_pdbg("0x58: 0x%08x (FREG1)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000565 mmio_readl(spibar + 0x58));
Sean Nelson316a29f2010-05-07 20:09:04 +0000566 msg_pdbg("0x5C: 0x%08x (FREG2)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000567 mmio_readl(spibar + 0x5C));
Sean Nelson316a29f2010-05-07 20:09:04 +0000568 msg_pdbg("0x60: 0x%08x (FREG3)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000569 mmio_readl(spibar + 0x60));
Sean Nelson316a29f2010-05-07 20:09:04 +0000570 msg_pdbg("0x64: 0x%08x (FREG4)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000571 mmio_readl(spibar + 0x64));
Sean Nelson316a29f2010-05-07 20:09:04 +0000572 msg_pdbg("0x74: 0x%08x (PR0)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000573 mmio_readl(spibar + 0x74));
Sean Nelson316a29f2010-05-07 20:09:04 +0000574 msg_pdbg("0x78: 0x%08x (PR1)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000575 mmio_readl(spibar + 0x78));
Sean Nelson316a29f2010-05-07 20:09:04 +0000576 msg_pdbg("0x7C: 0x%08x (PR2)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000577 mmio_readl(spibar + 0x7C));
Sean Nelson316a29f2010-05-07 20:09:04 +0000578 msg_pdbg("0x80: 0x%08x (PR3)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000579 mmio_readl(spibar + 0x80));
Sean Nelson316a29f2010-05-07 20:09:04 +0000580 msg_pdbg("0x84: 0x%08x (PR4)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000581 mmio_readl(spibar + 0x84));
Sean Nelson316a29f2010-05-07 20:09:04 +0000582 msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000583 mmio_readl(spibar + 0x90));
Sean Nelson316a29f2010-05-07 20:09:04 +0000584 msg_pdbg("0x94: 0x%04x (PREOP)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000585 mmio_readw(spibar + 0x94));
Sean Nelson316a29f2010-05-07 20:09:04 +0000586 msg_pdbg("0x96: 0x%04x (OPTYPE)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000587 mmio_readw(spibar + 0x96));
Sean Nelson316a29f2010-05-07 20:09:04 +0000588 msg_pdbg("0x98: 0x%08x (OPMENU)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000589 mmio_readl(spibar + 0x98));
Sean Nelson316a29f2010-05-07 20:09:04 +0000590 msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000591 mmio_readl(spibar + 0x9C));
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000592 ichspi_bbar = mmio_readl(spibar + 0xA0);
Sean Nelson316a29f2010-05-07 20:09:04 +0000593 msg_pdbg("0xA0: 0x%08x (BBAR)\n",
Carl-Daniel Hailfinger80f3d052010-05-28 15:53:08 +0000594 ichspi_bbar);
Sean Nelson316a29f2010-05-07 20:09:04 +0000595 msg_pdbg("0xB0: 0x%08x (FDOC)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000596 mmio_readl(spibar + 0xB0));
FENG yu ning37179b82009-01-18 06:39:32 +0000597 if (tmp2 & (1 << 15)) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000598 msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
FENG yu ning37179b82009-01-18 06:39:32 +0000599 ichspi_lock = 1;
600 }
Peter Stugee8a3e4c2008-12-22 14:12:08 +0000601 ich_init_opcodes();
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000602 break;
603 default:
604 /* Nothing */
605 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000606 }
607
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000608 old = pci_read_byte(dev, 0xdc);
Sean Nelson316a29f2010-05-07 20:09:04 +0000609 msg_pdbg("SPI Read Configuration: ");
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000610 new = (old >> 2) & 0x3;
611 switch (new) {
612 case 0:
613 case 1:
614 case 2:
Sean Nelson316a29f2010-05-07 20:09:04 +0000615 msg_pdbg("prefetching %sabled, caching %sabled, ",
Uwe Hermann394131e2008-10-18 21:14:13 +0000616 (new & 0x2) ? "en" : "dis",
617 (new & 0x1) ? "dis" : "en");
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000618 break;
619 default:
Sean Nelson316a29f2010-05-07 20:09:04 +0000620 msg_pdbg("invalid prefetching/caching settings, ");
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000621 break;
622 }
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000623
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000624 return ret;
625}
Stefan Reinauera9424d52008-06-27 16:28:34 +0000626
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000627static int enable_flash_ich7(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000628{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000629 return enable_flash_ich_dc_spi(dev, name, 7);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000630}
631
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000632static int enable_flash_ich8(struct pci_dev *dev, const char *name)
633{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000634 return enable_flash_ich_dc_spi(dev, name, 8);
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000635}
636
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000637static int enable_flash_ich9(struct pci_dev *dev, const char *name)
638{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000639 return enable_flash_ich_dc_spi(dev, name, 9);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000640}
641
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000642static int enable_flash_ich10(struct pci_dev *dev, const char *name)
643{
644 return enable_flash_ich_dc_spi(dev, name, 10);
645}
646
Michael Karcher89bed6d2010-06-13 10:16:12 +0000647static void via_do_byte_merge(void * arg)
648{
649 struct pci_dev * dev = arg;
650 uint8_t val;
651
652 msg_pdbg("Re-enabling byte merging\n");
653 val = pci_read_byte(dev, 0x71);
654 val |= 0x40;
655 pci_write_byte(dev, 0x71, val);
656}
657
658static int via_no_byte_merge(struct pci_dev *dev, const char *name)
659{
660 uint8_t val;
661
662 val = pci_read_byte(dev, 0x71);
663 if (val & 0x40)
664 {
665 msg_pdbg("Disabling byte merging\n");
666 val &= ~0x40;
667 pci_write_byte(dev, 0x71, val);
668 register_shutdown(via_do_byte_merge, dev);
669 }
670 return NOT_DONE_YET; /* need to find south bridge, too */
671}
672
Uwe Hermann372eeb52007-12-04 21:49:06 +0000673static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000674{
Ollie Lho184a4042005-11-26 21:55:36 +0000675 uint8_t val;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000676
Uwe Hermann394131e2008-10-18 21:14:13 +0000677 /* enable ROM decode range (1MB) FFC00000 - FFFFFFFF */
Bari Ari9477c4e2008-04-29 13:46:38 +0000678 pci_write_byte(dev, 0x41, 0x7f);
679
Uwe Hermannffec5f32007-08-23 16:08:21 +0000680 /* ROM write enable */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000681 val = pci_read_byte(dev, 0x40);
682 val |= 0x10;
683 pci_write_byte(dev, 0x40, val);
684
685 if (pci_read_byte(dev, 0x40) != val) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000686 msg_pinfo("\nWARNING: Failed to enable flash write on \"%s\"\n",
Uwe Hermanna7e05482007-05-09 10:17:44 +0000687 name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000688 return -1;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000689 }
Luc Verhaegen6382b442007-03-02 22:16:38 +0000690
Luc Verhaegen73d21192009-12-23 00:54:26 +0000691 if (dev->device_id == 0x3227) { /* VT8237R */
692 /* All memory cycles, not just ROM ones, go to LPC. */
693 val = pci_read_byte(dev, 0x59);
694 val &= ~0x80;
695 pci_write_byte(dev, 0x59, val);
696 }
697
Uwe Hermanna7e05482007-05-09 10:17:44 +0000698 return 0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000699}
700
Uwe Hermann372eeb52007-12-04 21:49:06 +0000701static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000702{
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000703 uint8_t reg8;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000704
Uwe Hermann394131e2008-10-18 21:14:13 +0000705#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
706#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000707#define CS5530_RESET_CONTROL_REG 0x44 /* F0 index 0x44 */
708#define CS5530_USB_SHADOW_REG 0x43 /* F0 index 0x43 */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000709
Uwe Hermann394131e2008-10-18 21:14:13 +0000710#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
711#define ROM_WRITE_ENABLE (1 << 1)
712#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
713#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000714#define CS5530_ISA_MASTER (1 << 7)
715#define CS5530_ENABLE_SA2320 (1 << 2)
716#define CS5530_ENABLE_SA20 (1 << 6)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000717
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000718 buses_supported = CHIP_BUSTYPE_PARALLEL;
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000719 /* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
720 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000721 * FIXME: Should we really touch the low mapping below 1 MB? Flashrom
722 * ignores that region completely.
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000723 * Make the configured ROM areas writable.
724 */
725 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
726 reg8 |= LOWER_ROM_ADDRESS_RANGE;
727 reg8 |= UPPER_ROM_ADDRESS_RANGE;
728 reg8 |= ROM_WRITE_ENABLE;
729 pci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000730
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000731 /* Set positive decode on ROM. */
732 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
733 reg8 |= BIOS_ROM_POSITIVE_DECODE;
734 pci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000735
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000736 reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG);
737 if (reg8 & CS5530_ISA_MASTER) {
738 /* We have A0-A23 available. */
739 max_rom_decode.parallel = 16 * 1024 * 1024;
740 } else {
741 reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG);
742 if (reg8 & CS5530_ENABLE_SA2320) {
743 /* We have A0-19, A20-A23 available. */
744 max_rom_decode.parallel = 16 * 1024 * 1024;
745 } else if (reg8 & CS5530_ENABLE_SA20) {
746 /* We have A0-19, A20 available. */
747 max_rom_decode.parallel = 2 * 1024 * 1024;
748 } else {
749 /* A20 and above are not active. */
750 max_rom_decode.parallel = 1024 * 1024;
751 }
752 }
753
Ollie Lhocbbf1252004-03-17 22:22:08 +0000754 return 0;
755}
756
Mart Raudseppe1344da2008-02-08 10:10:57 +0000757/**
758 * Geode systems write protect the BIOS via RCONFs (cache settings similar
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000759 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
Mart Raudseppe1344da2008-02-08 10:10:57 +0000760 *
761 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
762 * To enable write to NOR Boot flash for the benefit of systems that have such
763 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
Mart Raudseppe1344da2008-02-08 10:10:57 +0000764 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000765static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
Lane Brooksd54958a2007-11-13 16:45:22 +0000766{
Uwe Hermann394131e2008-10-18 21:14:13 +0000767#define MSR_RCONF_DEFAULT 0x1808
768#define MSR_NORF_CTL 0x51400018
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000769
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000770 msr_t msr;
Lane Brooksd54958a2007-11-13 16:45:22 +0000771
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000772 /* Geode only has a single core */
773 if (setup_cpu_msr(0))
Lane Brooksd54958a2007-11-13 16:45:22 +0000774 return -1;
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000775
776 msr = rdmsr(MSR_RCONF_DEFAULT);
777 if ((msr.hi >> 24) != 0x22) {
778 msr.hi &= 0xfbffffff;
779 wrmsr(MSR_RCONF_DEFAULT, msr);
Lane Brooksd54958a2007-11-13 16:45:22 +0000780 }
Mart Raudseppe1344da2008-02-08 10:10:57 +0000781
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000782 msr = rdmsr(MSR_NORF_CTL);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000783 /* Raise WE_CS3 bit. */
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000784 msr.lo |= 0x08;
785 wrmsr(MSR_NORF_CTL, msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000786
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000787 cleanup_cpu_msr();
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000788
Uwe Hermann394131e2008-10-18 21:14:13 +0000789#undef MSR_RCONF_DEFAULT
790#undef MSR_NORF_CTL
Lane Brooksd54958a2007-11-13 16:45:22 +0000791 return 0;
792}
793
Uwe Hermann372eeb52007-12-04 21:49:06 +0000794static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000795{
Ollie Lho184a4042005-11-26 21:55:36 +0000796 uint8_t new;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000797
Ollie Lhocbbf1252004-03-17 22:22:08 +0000798 pci_write_byte(dev, 0x52, 0xee);
799
800 new = pci_read_byte(dev, 0x52);
801
802 if (new != 0xee) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000803 msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000804 return -1;
805 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000806
Ollie Lhocbbf1252004-03-17 22:22:08 +0000807 return 0;
808}
809
Uwe Hermann190f8492008-10-25 18:03:50 +0000810/* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000811static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000812{
Ollie Lho184a4042005-11-26 21:55:36 +0000813 uint8_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000814
Uwe Hermann372eeb52007-12-04 21:49:06 +0000815 /* Enable decoding at 0xffb00000 to 0xffffffff. */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000816 old = pci_read_byte(dev, 0x43);
Ollie Lhod11f3612004-12-07 17:19:04 +0000817 new = old | 0xC0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000818 if (new != old) {
819 pci_write_byte(dev, 0x43, new);
820 if (pci_read_byte(dev, 0x43) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000821 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000822 }
823 }
824
Uwe Hermann190f8492008-10-25 18:03:50 +0000825 /* Enable 'ROM write' bit. */
Ollie Lho761bf1b2004-03-20 16:46:10 +0000826 old = pci_read_byte(dev, 0x40);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000827 new = old | 0x01;
828 if (new == old)
829 return 0;
830 pci_write_byte(dev, 0x40, new);
831
832 if (pci_read_byte(dev, 0x40) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000833 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000834 return -1;
835 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000836
Ollie Lhocbbf1252004-03-17 22:22:08 +0000837 return 0;
838}
839
Marc Jones3af487d2008-10-15 17:50:29 +0000840static int enable_flash_sb600(struct pci_dev *dev, const char *name)
841{
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000842 uint32_t tmp, prot;
Marc Jones3af487d2008-10-15 17:50:29 +0000843 uint8_t reg;
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000844 struct pci_dev *smbus_dev;
845 int has_spi = 1;
Marc Jones3af487d2008-10-15 17:50:29 +0000846
Jason Wanga3f04be2008-11-28 21:36:51 +0000847 /* Clear ROM protect 0-3. */
848 for (reg = 0x50; reg < 0x60; reg += 4) {
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000849 prot = pci_read_long(dev, reg);
850 /* No protection flags for this region?*/
851 if ((prot & 0x3) == 0)
852 continue;
Sean Nelson316a29f2010-05-07 20:09:04 +0000853 msg_pinfo("SB600 %s%sprotected from %u to %u\n",
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000854 (prot & 0x1) ? "write " : "",
855 (prot & 0x2) ? "read " : "",
856 (prot & 0xfffffc00),
857 (prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
858 prot &= 0xfffffffc;
859 pci_write_byte(dev, reg, prot);
860 prot = pci_read_long(dev, reg);
Carl-Daniel Hailfinger9bb88ac2009-05-06 13:51:44 +0000861 if (prot & 0x3)
Sean Nelson316a29f2010-05-07 20:09:04 +0000862 msg_perr("SB600 %s%sunprotect failed from %u to %u\n",
Carl-Daniel Hailfinger9bb88ac2009-05-06 13:51:44 +0000863 (prot & 0x1) ? "write " : "",
864 (prot & 0x2) ? "read " : "",
865 (prot & 0xfffffc00),
866 (prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
Jason Wanga3f04be2008-11-28 21:36:51 +0000867 }
868
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000869 /* Read SPI_BaseAddr */
870 tmp = pci_read_long(dev, 0xa0);
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000871 tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */
Sean Nelson316a29f2010-05-07 20:09:04 +0000872 msg_pdbg("SPI base address is at 0x%x\n", tmp);
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000873
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000874 /* If the BAR has address 0, it is unlikely SPI is used. */
875 if (!tmp)
876 has_spi = 0;
877
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000878 if (has_spi) {
879 /* Physical memory has to be mapped at page (4k) boundaries. */
880 sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000,
881 0x1000);
882 /* The low bits of the SPI base address are used as offset into
883 * the mapped page.
884 */
885 sb600_spibar += tmp & 0xfff;
886
887 tmp = pci_read_long(dev, 0xa0);
Sean Nelson316a29f2010-05-07 20:09:04 +0000888 msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, "
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000889 "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1,
890 (tmp & 0x4) >> 2);
891 tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2;
Sean Nelson316a29f2010-05-07 20:09:04 +0000892 msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp);
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000893
894 tmp = pci_read_byte(dev, 0xbb);
Sean Nelson316a29f2010-05-07 20:09:04 +0000895 msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n",
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000896 tmp & 0x1, (tmp & 0x20) >> 5);
897 tmp = mmio_readl(sb600_spibar);
Sean Nelson316a29f2010-05-07 20:09:04 +0000898 msg_pdbg("SpiArbEnable=%i, SpiAccessMacRomEn=%i, "
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000899 "SpiHostAccessRomEn=%i, ArbWaitCount=%i, "
900 "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n",
901 (tmp >> 19) & 0x1, (tmp >> 22) & 0x1,
902 (tmp >> 23) & 0x1, (tmp >> 24) & 0x7,
903 (tmp >> 27) & 0x1, (tmp >> 28) & 0x1);
904 }
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000905
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000906 /* Look for the SMBus device. */
907 smbus_dev = pci_dev_find(0x1002, 0x4385);
908
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000909 if (has_spi && !smbus_dev) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000910 msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n");
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000911 has_spi = 0;
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000912 }
913 if (has_spi) {
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000914 /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */
915 /* GPIO11/SPI_DO and GPIO12/SPI_DI status */
916 reg = pci_read_byte(smbus_dev, 0xAB);
917 reg &= 0xC0;
Sean Nelson316a29f2010-05-07 20:09:04 +0000918 msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO");
919 msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI");
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000920 if (reg != 0x00)
921 has_spi = 0;
922 /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */
923 reg = pci_read_byte(smbus_dev, 0x83);
924 reg &= 0xC0;
Sean Nelson316a29f2010-05-07 20:09:04 +0000925 msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD");
926 msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000927 /* SPI_HOLD is not used on all boards, filter it out. */
928 if ((reg & 0x80) != 0x00)
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000929 has_spi = 0;
930 /* GPIO47/SPI_CLK status */
931 reg = pci_read_byte(smbus_dev, 0xA7);
932 reg &= 0x40;
Sean Nelson316a29f2010-05-07 20:09:04 +0000933 msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK");
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000934 if (reg != 0x00)
935 has_spi = 0;
936 }
937
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000938 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH;
939 if (has_spi) {
940 buses_supported |= CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000941 spi_controller = SPI_CONTROLLER_SB600;
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000942 }
Jason Wanga3f04be2008-11-28 21:36:51 +0000943
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000944 /* Read ROM strap override register. */
945 OUTB(0x8f, 0xcd6);
946 reg = INB(0xcd7);
947 reg &= 0x0e;
Sean Nelson316a29f2010-05-07 20:09:04 +0000948 msg_pdbg("ROM strap override is %sactive", (reg & 0x02) ? "" : "not ");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000949 if (reg & 0x02) {
950 switch ((reg & 0x0c) >> 2) {
951 case 0x00:
Sean Nelson316a29f2010-05-07 20:09:04 +0000952 msg_pdbg(": LPC");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000953 break;
954 case 0x01:
Sean Nelson316a29f2010-05-07 20:09:04 +0000955 msg_pdbg(": PCI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000956 break;
957 case 0x02:
Sean Nelson316a29f2010-05-07 20:09:04 +0000958 msg_pdbg(": FWH");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000959 break;
960 case 0x03:
Sean Nelson316a29f2010-05-07 20:09:04 +0000961 msg_pdbg(": SPI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000962 break;
963 }
964 }
Sean Nelson316a29f2010-05-07 20:09:04 +0000965 msg_pdbg("\n");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000966
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000967 /* Force enable SPI ROM in SB600 PM register.
968 * If we enable SPI ROM here, we have to disable it after we leave.
Zheng Bao284a6002009-05-04 22:33:50 +0000969 * But how can we know which ROM we are going to handle? So we have
970 * to trade off. We only access LPC ROM if we boot via LPC ROM. And
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000971 * only SPI ROM if we boot via SPI ROM. If you want to access SPI on
972 * boards with LPC straps, you have to use the code below.
Zheng Bao284a6002009-05-04 22:33:50 +0000973 */
974 /*
Jason Wanga3f04be2008-11-28 21:36:51 +0000975 OUTB(0x8f, 0xcd6);
976 OUTB(0x0e, 0xcd7);
Zheng Bao284a6002009-05-04 22:33:50 +0000977 */
Marc Jones3af487d2008-10-15 17:50:29 +0000978
979 return 0;
980}
981
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000982static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name)
983{
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000984 uint8_t tmp;
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000985
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000986 pci_write_byte(dev, 0x92, 0);
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000987
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000988 tmp = pci_read_byte(dev, 0x6d);
989 tmp |= 0x01;
990 pci_write_byte(dev, 0x6d, tmp);
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000991
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000992 return 0;
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000993}
994
Uwe Hermann372eeb52007-12-04 21:49:06 +0000995static int enable_flash_ck804(struct pci_dev *dev, const char *name)
Yinghai Lu952dfce2005-07-06 17:13:46 +0000996{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000997 uint8_t old, new;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000998
Uwe Hermanna7e05482007-05-09 10:17:44 +0000999 old = pci_read_byte(dev, 0x88);
1000 new = old | 0xc0;
1001 if (new != old) {
1002 pci_write_byte(dev, 0x88, new);
1003 if (pci_read_byte(dev, 0x88) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001004 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001005 }
1006 }
Yinghai Lu952dfce2005-07-06 17:13:46 +00001007
Uwe Hermanna7e05482007-05-09 10:17:44 +00001008 old = pci_read_byte(dev, 0x6d);
1009 new = old | 0x01;
1010 if (new == old)
1011 return 0;
1012 pci_write_byte(dev, 0x6d, new);
1013
1014 if (pci_read_byte(dev, 0x6d) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001015 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001016 return -1;
1017 }
Uwe Hermannffec5f32007-08-23 16:08:21 +00001018
Uwe Hermanna7e05482007-05-09 10:17:44 +00001019 return 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +00001020}
1021
Uwe Hermann372eeb52007-12-04 21:49:06 +00001022/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
1023static int enable_flash_sb400(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +00001024{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001025 uint8_t tmp;
Stefan Reinauer86de2832006-03-31 11:26:55 +00001026 struct pci_dev *smbusdev;
1027
Uwe Hermann372eeb52007-12-04 21:49:06 +00001028 /* Look for the SMBus device. */
Carl-Daniel Hailfingerf6e3efb2009-05-06 00:35:31 +00001029 smbusdev = pci_dev_find(0x1002, 0x4372);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001030
Uwe Hermanna7e05482007-05-09 10:17:44 +00001031 if (!smbusdev) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001032 msg_perr("ERROR: SMBus device not found. Aborting.\n");
Stefan Reinauer86de2832006-03-31 11:26:55 +00001033 exit(1);
1034 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001035
Uwe Hermann372eeb52007-12-04 21:49:06 +00001036 /* Enable some SMBus stuff. */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001037 tmp = pci_read_byte(smbusdev, 0x79);
1038 tmp |= 0x01;
Stefan Reinauer86de2832006-03-31 11:26:55 +00001039 pci_write_byte(smbusdev, 0x79, tmp);
1040
Uwe Hermann372eeb52007-12-04 21:49:06 +00001041 /* Change southbridge. */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001042 tmp = pci_read_byte(dev, 0x48);
1043 tmp |= 0x21;
Stefan Reinauer86de2832006-03-31 11:26:55 +00001044 pci_write_byte(dev, 0x48, tmp);
1045
Uwe Hermann372eeb52007-12-04 21:49:06 +00001046 /* Now become a bit silly. */
Andriy Gapon65c1b862008-05-22 13:22:45 +00001047 tmp = INB(0xc6f);
1048 OUTB(tmp, 0xeb);
1049 OUTB(tmp, 0xeb);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001050 tmp |= 0x40;
Andriy Gapon65c1b862008-05-22 13:22:45 +00001051 OUTB(tmp, 0xc6f);
1052 OUTB(tmp, 0xeb);
1053 OUTB(tmp, 0xeb);
Stefan Reinauer86de2832006-03-31 11:26:55 +00001054
1055 return 0;
1056}
1057
Uwe Hermann372eeb52007-12-04 21:49:06 +00001058static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
Yinghai Luca782972007-01-22 20:21:17 +00001059{
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001060 uint8_t old, new, val;
1061 uint16_t wordval;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001062
Uwe Hermann372eeb52007-12-04 21:49:06 +00001063 /* Set the 0-16 MB enable bits. */
Michael Karcher4e2fb0e2010-01-12 23:29:26 +00001064 val = pci_read_byte(dev, 0x88);
1065 val |= 0xff; /* 256K */
1066 pci_write_byte(dev, 0x88, val);
1067 val = pci_read_byte(dev, 0x8c);
1068 val |= 0xff; /* 1M */
1069 pci_write_byte(dev, 0x8c, val);
1070 wordval = pci_read_word(dev, 0x90);
1071 wordval |= 0x7fff; /* 16M */
1072 pci_write_word(dev, 0x90, wordval);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001073
Uwe Hermanna7e05482007-05-09 10:17:44 +00001074 old = pci_read_byte(dev, 0x6d);
1075 new = old | 0x01;
1076 if (new == old)
1077 return 0;
1078 pci_write_byte(dev, 0x6d, new);
Yinghai Luca782972007-01-22 20:21:17 +00001079
Uwe Hermanna7e05482007-05-09 10:17:44 +00001080 if (pci_read_byte(dev, 0x6d) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +00001081 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001082 return -1;
1083 }
Yinghai Luca782972007-01-22 20:21:17 +00001084
1085 return 0;
Yinghai Luca782972007-01-22 20:21:17 +00001086}
1087
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001088/* This is a shot in the dark. Even if the code is totally bogus for some
1089 * chipsets, users will at least start to send in reports.
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001090 */
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001091static int enable_flash_mcp6x_7x_common(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001092{
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001093 int ret = 0;
Michael Karchercfa674f2010-02-25 11:38:23 +00001094 uint8_t val;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001095 uint16_t status;
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001096 char *busname;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001097 uint32_t mcp_spibaraddr;
1098 void *mcp_spibar;
1099 struct pci_dev *smbusdev;
1100
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001101 msg_pinfo("This chipset is not really supported yet. Guesswork...\n");
1102
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001103 /* dev is the ISA bridge. No idea what the stuff below does. */
Michael Karchercfa674f2010-02-25 11:38:23 +00001104 val = pci_read_byte(dev, 0x8a);
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001105 msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 "
Michael Karchercfa674f2010-02-25 11:38:23 +00001106 "is %i\n", val, (val >> 6) & 0x1, (val >> 5) & 0x1);
1107 switch ((val >> 5) & 0x3) {
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001108 case 0x0:
1109 buses_supported = CHIP_BUSTYPE_LPC;
1110 break;
1111 case 0x2:
1112 buses_supported = CHIP_BUSTYPE_SPI;
1113 break;
1114 default:
1115 buses_supported = CHIP_BUSTYPE_UNKNOWN;
1116 break;
1117 }
1118 busname = flashbuses_to_text(buses_supported);
1119 msg_pdbg("Guessed flash bus type is %s\n", busname);
1120 free(busname);
1121
1122 /* Force enable SPI and disable LPC? Not a good idea. */
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001123#if 0
Michael Karchercfa674f2010-02-25 11:38:23 +00001124 val |= (1 << 6);
1125 val &= ~(1 << 5);
1126 pci_write_byte(dev, 0x8a, val);
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001127#endif
1128
1129 /* Look for the SMBus device (SMBus PCI class) */
1130 smbusdev = pci_dev_find_vendorclass(0x10de, 0x0c05);
1131 if (!smbusdev) {
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001132 if (buses_supported & CHIP_BUSTYPE_SPI) {
1133 msg_perr("ERROR: SMBus device not found. Not enabling "
1134 "SPI.\n");
1135 buses_supported &= ~CHIP_BUSTYPE_SPI;
1136 ret = 1;
1137 } else {
1138 msg_pinfo("Odd. SMBus device not found.\n");
1139 }
1140 goto out_msg;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001141 }
1142 msg_pdbg("Found SMBus device %04x:%04x at %02x:%02x:%01x\n",
1143 smbusdev->vendor_id, smbusdev->device_id,
1144 smbusdev->bus, smbusdev->dev, smbusdev->func);
1145
1146 /* Locate the BAR where the SPI interface lives. */
1147 mcp_spibaraddr = pci_read_long(smbusdev, 0x74);
1148 msg_pdbg("SPI BAR is at 0x%08x, ", mcp_spibaraddr);
1149 /* We hope this has native alignment. We know the SPI interface (well,
1150 * a set of GPIOs that is connected to SPI flash) is at offset 0x530,
1151 * so we expect a size of at least 0x800. Clear the lower bits.
1152 * It is entirely possible that the BAR is 64k big and the low bits are
1153 * reserved for an entirely different purpose.
1154 */
1155 mcp_spibaraddr &= ~0x7ff;
1156 msg_pdbg("after clearing low bits BAR is at 0x%08x\n", mcp_spibaraddr);
1157
1158 /* Accessing a NULL pointer BAR is evil. Don't do it. */
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001159 if (mcp_spibaraddr && (buses_supported == CHIP_BUSTYPE_SPI)) {
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001160 /* Map the BAR. Bytewise/wordwise access at 0x530 and 0x540. */
1161 mcp_spibar = physmap("MCP67 SPI", mcp_spibaraddr, 0x544);
1162
1163/* Guessed. If this is correct, migrate to a separate MCP67 SPI driver. */
1164#define MCP67_SPI_CS (1 << 1)
1165#define MCP67_SPI_SCK (1 << 2)
1166#define MCP67_SPI_MOSI (1 << 3)
1167#define MCP67_SPI_MISO (1 << 4)
1168#define MCP67_SPI_ENABLE (1 << 0)
1169#define MCP67_SPI_IDLE (1 << 8)
1170
1171 status = mmio_readw(mcp_spibar + 0x530);
1172 msg_pdbg("SPI control is 0x%04x, enable=%i, idle=%i\n",
1173 status, status & 0x1, (status >> 8) & 0x1);
1174 /* FIXME: Remove the physunmap once the SPI driver exists. */
1175 physunmap(mcp_spibar, 0x544);
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001176 } else if (!mcp_spibaraddr && (buses_supported & CHIP_BUSTYPE_SPI)) {
1177 msg_pdbg("Strange. MCP SPI BAR is invalid.\n");
1178 buses_supported &= ~CHIP_BUSTYPE_SPI;
1179 ret = 1;
1180 } else if (mcp_spibaraddr && !(buses_supported & CHIP_BUSTYPE_SPI)) {
1181 msg_pdbg("Strange. MCP SPI BAR is valid, but chipset apparently"
1182 " doesn't have SPI enabled.\n");
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001183 } else {
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001184 msg_pdbg("MCP SPI is not used.\n");
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001185 }
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001186out_msg:
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001187 msg_pinfo("Please send the output of \"flashrom -V\" to "
1188 "flashrom@flashrom.org to help us finish support for your "
1189 "chipset. Thanks.\n");
1190
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001191 return ret;
1192}
1193
1194/**
1195 * The MCP61/MCP67 code is guesswork based on cleanroom reverse engineering.
1196 * Due to that, it only reads info and doesn't change any settings.
1197 * It is assumed that LPC chips need the MCP55 code and SPI chips need the
1198 * code provided in enable_flash_mcp6x_7x_common. Until we know for sure, call
1199 * enable_flash_mcp55 from this function only if enable_flash_mcp6x_7x_common
1200 * indicates the flash chip is LPC. Warning: enable_flash_mcp55
1201 * might make SPI flash inaccessible. The same caveat applies to SPI init
1202 * for LPC flash.
1203 */
1204static int enable_flash_mcp67(struct pci_dev *dev, const char *name)
1205{
1206 int result = 0;
1207
1208 result = enable_flash_mcp6x_7x_common(dev, name);
1209 if (result)
1210 return result;
1211
1212 /* Not sure if this is correct. No docs as usual. */
1213 switch (buses_supported) {
1214 case CHIP_BUSTYPE_LPC:
1215 result = enable_flash_mcp55(dev, name);
1216 break;
1217 case CHIP_BUSTYPE_SPI:
1218 msg_pinfo("SPI on this chipset is not supported yet.\n");
1219 buses_supported = CHIP_BUSTYPE_NONE;
1220 break;
1221 default:
1222 msg_pinfo("Something went wrong with bus type detection.\n");
1223 buses_supported = CHIP_BUSTYPE_NONE;
1224 break;
1225 }
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001226
1227 return result;
1228}
1229
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001230static int enable_flash_mcp7x(struct pci_dev *dev, const char *name)
1231{
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001232 int result = 0;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001233
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001234 result = enable_flash_mcp6x_7x_common(dev, name);
1235 if (result)
1236 return result;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001237
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001238 /* Not sure if this is correct. No docs as usual. */
1239 switch (buses_supported) {
1240 case CHIP_BUSTYPE_LPC:
1241 msg_pinfo("LPC on this chipset is not supported yet.\n");
1242 break;
1243 case CHIP_BUSTYPE_SPI:
1244 msg_pinfo("SPI on this chipset is not supported yet.\n");
1245 buses_supported = CHIP_BUSTYPE_NONE;
1246 break;
1247 default:
1248 msg_pinfo("Something went wrong with bus type detection.\n");
1249 buses_supported = CHIP_BUSTYPE_NONE;
1250 break;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001251 }
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001252
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001253 return result;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001254}
1255
Uwe Hermann372eeb52007-12-04 21:49:06 +00001256static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001257{
Michael Karchercfa674f2010-02-25 11:38:23 +00001258 uint8_t val;
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001259
Uwe Hermanne823ee02007-06-05 15:02:18 +00001260 /* Set the 4MB enable bit. */
Michael Karchercfa674f2010-02-25 11:38:23 +00001261 val = pci_read_byte(dev, 0x41);
1262 val |= 0x0e;
1263 pci_write_byte(dev, 0x41, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001264
Michael Karchercfa674f2010-02-25 11:38:23 +00001265 val = pci_read_byte(dev, 0x43);
1266 val |= (1 << 4);
1267 pci_write_byte(dev, 0x43, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001268
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001269 return 0;
1270}
1271
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001272/**
1273 * Usually on the x86 architectures (and on other PC-like platforms like some
1274 * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
1275 * Elan SC520 only a small piece of the system flash is mapped there, but the
1276 * complete flash is mapped somewhere below 1G. The position can be determined
1277 * by the BOOTCS PAR register.
1278 */
1279static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
1280{
1281 int i, bootcs_found = 0;
1282 uint32_t parx = 0;
1283 void *mmcr;
1284
1285 /* 1. Map MMCR */
Stefan Reinauer0593f212009-01-26 01:10:48 +00001286 mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001287
1288 /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for
1289 * BOOTCS region (PARx[31:29] = 100b)e
1290 */
1291 for (i = 0x88; i <= 0xc4; i += 4) {
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +00001292 parx = mmio_readl(mmcr + i);
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001293 if ((parx >> 29) == 4) {
1294 bootcs_found = 1;
1295 break; /* BOOTCS found */
1296 }
1297 }
1298
1299 /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0]
1300 * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0]
1301 */
1302 if (bootcs_found) {
1303 if (parx & (1 << 25)) {
1304 parx &= (1 << 14) - 1; /* Mask [13:0] */
1305 flashbase = parx << 16;
1306 } else {
1307 parx &= (1 << 18) - 1; /* Mask [17:0] */
1308 flashbase = parx << 12;
1309 }
1310 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +00001311 msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n");
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001312 }
1313
1314 /* 4. Clean up */
Carl-Daniel Hailfingerbe726812009-08-09 12:44:08 +00001315 physunmap(mmcr, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001316 return 0;
1317}
1318
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001319#endif
1320
Uwe Hermann4179d292009-05-08 17:50:51 +00001321/* Please keep this list alphabetically sorted by vendor/device. */
Uwe Hermann05fab752009-05-16 23:42:17 +00001322const struct penable chipset_enables[] = {
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001323#if defined(__i386__) || defined(__x86_64__)
Uwe Hermann4179d292009-05-08 17:50:51 +00001324 {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533},
1325 {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111},
1326 {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111},
1327 {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530},
1328 {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536},
Nils Jacobse715c7b2009-09-23 02:09:23 +00001329 {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536},
Uwe Hermann4179d292009-05-08 17:50:51 +00001330 {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520},
1331 {0x1002, 0x438D, OK, "AMD", "SB600", enable_flash_sb600},
Carl-Daniel Hailfinger174962d2009-09-01 22:13:42 +00001332 {0x1002, 0x439d, OK, "AMD", "SB700/SB710/SB750", enable_flash_sb600},
Uwe Hermann4179d292009-05-08 17:50:51 +00001333 {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100},
1334 {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400},
1335 {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000},
Carl-Daniel Hailfinger797a8342009-11-26 16:51:39 +00001336 {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_ich10},
1337 {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_ich10},
1338 {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_ich10},
Uwe Hermannb0039912009-05-07 13:24:49 +00001339 {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4},
Uwe Hermann4179d292009-05-08 17:50:51 +00001340 {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich_4e},
1341 {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich_dc},
1342 {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7},
Uwe Hermannb0039912009-05-07 13:24:49 +00001343 {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e},
Uwe Hermann4179d292009-05-08 17:50:51 +00001344 {0x8086, 0x3a18, OK, "Intel", "ICH10", enable_flash_ich10},
1345 {0x8086, 0x3a1a, OK, "Intel", "ICH10D", enable_flash_ich10},
1346 {0x8086, 0x3a14, OK, "Intel", "ICH10DO", enable_flash_ich10},
1347 {0x8086, 0x3a16, OK, "Intel", "ICH10R", enable_flash_ich10},
Uwe Hermannb0039912009-05-07 13:24:49 +00001348 {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e},
1349 {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +00001350 {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich_4e},
Uwe Hermann4179d292009-05-08 17:50:51 +00001351 {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +00001352 {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich_4e},
1353 {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich_4e},
1354 {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +00001355 {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich_dc},
1356 {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich_dc},
Uwe Hermannb0039912009-05-07 13:24:49 +00001357 {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7},
1358 {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7},
1359 {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7},
1360 {0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7},
David Hendricksdb7c1532010-01-19 02:19:27 +00001361 {0x8086, 0x27bc, OK, "Intel", "NM10", enable_flash_ich7},
Uwe Hermann4179d292009-05-08 17:50:51 +00001362 {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +00001363 {0x8086, 0x2812, OK, "Intel", "ICH8DH", enable_flash_ich8},
1364 {0x8086, 0x2814, OK, "Intel", "ICH8DO", enable_flash_ich8},
Uwe Hermann4179d292009-05-08 17:50:51 +00001365 {0x8086, 0x2810, OK, "Intel", "ICH8/ICH8R", enable_flash_ich8},
Uwe Hermannb0039912009-05-07 13:24:49 +00001366 {0x8086, 0x2815, OK, "Intel", "ICH8M", enable_flash_ich8},
Uwe Hermann4179d292009-05-08 17:50:51 +00001367 {0x8086, 0x2811, OK, "Intel", "ICH8M-E", enable_flash_ich8},
1368 {0x8086, 0x2918, OK, "Intel", "ICH9", enable_flash_ich9},
Uwe Hermannb0039912009-05-07 13:24:49 +00001369 {0x8086, 0x2912, OK, "Intel", "ICH9DH", enable_flash_ich9},
1370 {0x8086, 0x2914, OK, "Intel", "ICH9DO", enable_flash_ich9},
Uwe Hermannb0039912009-05-07 13:24:49 +00001371 {0x8086, 0x2919, OK, "Intel", "ICH9M", enable_flash_ich9},
Uwe Hermann4179d292009-05-08 17:50:51 +00001372 {0x8086, 0x2917, OK, "Intel", "ICH9M-E", enable_flash_ich9},
1373 {0x8086, 0x2916, OK, "Intel", "ICH9R", enable_flash_ich9},
Carl-Daniel Hailfinger95baaad2009-08-21 17:26:13 +00001374 {0x8086, 0x2910, OK, "Intel", "ICH9 Engineering Sample", enable_flash_ich9},
Uwe Hermann4179d292009-05-08 17:50:51 +00001375 {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4},
1376 {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4},
1377 {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4},
1378 {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4},
Adam Jurkowskie4984102009-12-21 15:30:46 +00001379 {0x8086, 0x8119, OK, "Intel", "Poulsbo", enable_flash_poulsbo},
Luc Verhaegenaad7e672009-10-06 11:32:21 +00001380 {0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2},
Uwe Hermannb0039912009-05-07 13:24:49 +00001381 {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */
1382 {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */
Luc Verhaegen90e8e612009-05-26 09:48:28 +00001383 {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2},
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001384 {0x10de, 0x00e0, OK, "NVIDIA", "NForce3", enable_flash_nvidia_nforce2},
Uwe Hermanneac10162008-03-13 18:52:51 +00001385 /* Slave, should not be here, to fix known bug for A01. */
Uwe Hermannb0039912009-05-07 13:24:49 +00001386 {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804},
1387 {0x10de, 0x0260, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1388 {0x10de, 0x0261, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1389 {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1390 {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1391 {0x10de, 0x0360, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/
Carl-Daniel Hailfinger33d7b6a2010-05-22 07:27:16 +00001392 /* 10de:0361 is present in Tyan S2915 OEM systems, but not connected to
1393 * the flash chip. Instead, 10de:0364 is connected to the flash chip.
1394 * Until we have PCI device class matching or some fallback mechanism,
1395 * this is needed to get flashrom working on Tyan S2915 and maybe other
1396 * dual-MCP55 boards.
1397 */
1398#if 0
1399 {0x10de, 0x0361, NT, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1400#endif
Uwe Hermannb0039912009-05-07 13:24:49 +00001401 {0x10de, 0x0362, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1402 {0x10de, 0x0363, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1403 {0x10de, 0x0364, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1404 {0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1405 {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1406 {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +00001407 {0x10de, 0x03e0, NT, "NVIDIA", "MCP61", enable_flash_mcp67},
1408 {0x10de, 0x03e1, NT, "NVIDIA", "MCP61", enable_flash_mcp67},
1409 {0x10de, 0x03e2, NT, "NVIDIA", "MCP61", enable_flash_mcp67},
1410 {0x10de, 0x03e3, NT, "NVIDIA", "MCP61", enable_flash_mcp67},
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +00001411 {0x10de, 0x0440, NT, "NVIDIA", "MCP65", enable_flash_mcp7x},
1412 {0x10de, 0x0441, NT, "NVIDIA", "MCP65", enable_flash_mcp7x},
1413 {0x10de, 0x0442, NT, "NVIDIA", "MCP65", enable_flash_mcp7x},
1414 {0x10de, 0x0443, NT, "NVIDIA", "MCP65", enable_flash_mcp7x},
1415 {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp67},
1416 {0x10de, 0x075c, NT, "NVIDIA", "MCP78S", enable_flash_mcp7x},
1417 {0x10de, 0x075d, NT, "NVIDIA", "MCP78S", enable_flash_mcp7x},
1418 {0x10de, 0x07d7, NT, "NVIDIA", "MCP73", enable_flash_mcp7x},
1419 {0x10de, 0x0aac, NT, "NVIDIA", "MCP79", enable_flash_mcp7x},
1420 {0x10de, 0x0aad, NT, "NVIDIA", "MCP79", enable_flash_mcp7x},
1421 {0x10de, 0x0aae, NT, "NVIDIA", "MCP79", enable_flash_mcp7x},
1422 {0x10de, 0x0aaf, NT, "NVIDIA", "MCP79", enable_flash_mcp7x},
Carl-Daniel Hailfinger6a0269e2009-11-15 17:20:21 +00001423 {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496},
1424 {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501},
1425 {0x1039, 0x5511, NT, "SiS", "5511", enable_flash_sis5511},
Luc Verhaegen9cce2f52010-01-10 15:01:08 +00001426 {0x1039, 0x5596, NT, "SiS", "5596", enable_flash_sis5511},
Carl-Daniel Hailfinger6a0269e2009-11-15 17:20:21 +00001427 {0x1039, 0x5571, NT, "SiS", "5571", enable_flash_sis530},
1428 {0x1039, 0x5591, NT, "SiS", "5591/5592", enable_flash_sis530},
1429 {0x1039, 0x5597, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530},
1430 {0x1039, 0x0530, NT, "SiS", "530", enable_flash_sis530},
1431 {0x1039, 0x5600, NT, "SiS", "600", enable_flash_sis530},
1432 {0x1039, 0x0620, NT, "SiS", "620", enable_flash_sis530},
1433 {0x1039, 0x0540, NT, "SiS", "540", enable_flash_sis540},
Luc Verhaegen9892ca62009-12-09 07:43:13 +00001434 {0x1039, 0x0630, NT, "SiS", "630", enable_flash_sis540},
1435 {0x1039, 0x0635, NT, "SiS", "635", enable_flash_sis540},
1436 {0x1039, 0x0640, NT, "SiS", "640", enable_flash_sis540},
1437 {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis540},
1438 {0x1039, 0x0646, NT, "SiS", "645DX", enable_flash_sis540},
1439 {0x1039, 0x0648, NT, "SiS", "648", enable_flash_sis540},
1440 {0x1039, 0x0650, NT, "SiS", "650", enable_flash_sis540},
1441 {0x1039, 0x0651, NT, "SiS", "651", enable_flash_sis540},
1442 {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis540},
1443 {0x1039, 0x0730, NT, "SiS", "730", enable_flash_sis540},
1444 {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis540},
1445 {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis540},
1446 {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis540},
1447 {0x1039, 0x0745, NT, "SiS", "745", enable_flash_sis540},
1448 {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540},
1449 {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540},
1450 {0x1039, 0x0755, NT, "SiS", "755", enable_flash_sis540},
Michael Karcher89bed6d2010-06-13 10:16:12 +00001451 /* VIA northbridges */
1452 {0x1106, 0x0585, NT, "VIA", "VT82C585VPX", via_no_byte_merge},
1453 {0x1106, 0x0595, NT, "VIA", "VT82C595", via_no_byte_merge},
1454 {0x1106, 0x0597, NT, "VIA", "VT82C597", via_no_byte_merge},
1455 {0x1106, 0x0691, NT, "VIA", "VT82C69x", via_no_byte_merge}, /* 691, 693a, 694t, 694x checked */
1456 {0x1106, 0x0601, NT, "VIA", "VT8601/VT8601A", via_no_byte_merge},
1457 {0x1106, 0x8601, NT, "VIA", "VT8601T", via_no_byte_merge},
1458 /* VIA southbridges */
Uwe Hermann4179d292009-05-08 17:50:51 +00001459 {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x},
1460 {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x},
Mateusz Murawskie6abef02009-06-18 12:42:46 +00001461 {0x1106, 0x3074, NT, "VIA", "VT8233", enable_flash_vt823x},
Raúl Sorianocd8404d2009-12-23 21:29:18 +00001462 {0x1106, 0x3147, OK, "VIA", "VT8233A", enable_flash_vt823x},
Uwe Hermann4179d292009-05-08 17:50:51 +00001463 {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x},
1464 {0x1106, 0x3227, OK, "VIA", "VT8237", enable_flash_vt823x},
1465 {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x},
1466 {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi},
Arjan Koers8dfea832009-06-15 00:03:37 +00001467 {0x1106, 0x8353, OK, "VIA", "VX800", enable_flash_vt8237s_spi},
Uwe Hermann3e0774d2009-09-25 01:05:06 +00001468 {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111},
Uwe Hermann4179d292009-05-08 17:50:51 +00001469 {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111},
1470 {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111},
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001471#endif
Uwe Hermann05fab752009-05-16 23:42:17 +00001472 {},
Ollie Lhocbbf1252004-03-17 22:22:08 +00001473};
Ollie Lho761bf1b2004-03-20 16:46:10 +00001474
Uwe Hermanna7e05482007-05-09 10:17:44 +00001475int chipset_flash_enable(void)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001476{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001477 struct pci_dev *dev = 0;
Uwe Hermann372eeb52007-12-04 21:49:06 +00001478 int ret = -2; /* Nothing! */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001479 int i;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001480
Uwe Hermann372eeb52007-12-04 21:49:06 +00001481 /* Now let's try to find the chipset we have... */
Uwe Hermann05fab752009-05-16 23:42:17 +00001482 for (i = 0; chipset_enables[i].vendor_name != NULL; i++) {
1483 dev = pci_dev_find(chipset_enables[i].vendor_id,
1484 chipset_enables[i].device_id);
Michael Karcher89bed6d2010-06-13 10:16:12 +00001485 if (!dev)
1486 continue;
1487 if (ret != -2) {
1488 msg_pinfo("WARNING: unexpected second chipset match: "
1489 "\"%s %s\"\nignoring, please report lspci and "
1490 "board URL to flashrom@flashrom.org!\n",
1491 chipset_enables[i].vendor_name,
1492 chipset_enables[i].device_name);
1493 continue;
1494 }
Sean Nelson316a29f2010-05-07 20:09:04 +00001495 msg_pinfo("Found chipset \"%s %s\", enabling flash write... ",
Uwe Hermann05fab752009-05-16 23:42:17 +00001496 chipset_enables[i].vendor_name,
1497 chipset_enables[i].device_name);
Carl-Daniel Hailfingerf469c272010-05-22 07:31:50 +00001498 msg_pdbg("chipset PCI ID is %04x:%04x, ",
1499 chipset_enables[i].vendor_id,
1500 chipset_enables[i].device_id);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001501
Uwe Hermann05fab752009-05-16 23:42:17 +00001502 ret = chipset_enables[i].doit(dev,
1503 chipset_enables[i].device_name);
Michael Karcher89bed6d2010-06-13 10:16:12 +00001504 if (ret == NOT_DONE_YET) {
1505 ret = -2;
1506 msg_pinfo("OK - searching further chips.\n");
1507 } else if (ret < 0)
Sean Nelson316a29f2010-05-07 20:09:04 +00001508 msg_pinfo("FAILED!\n");
Michael Karcher89bed6d2010-06-13 10:16:12 +00001509 else if(ret == 0)
Sean Nelson316a29f2010-05-07 20:09:04 +00001510 msg_pinfo("OK.\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00001511 }
Michael Karcher89bed6d2010-06-13 10:16:12 +00001512
Sean Nelson316a29f2010-05-07 20:09:04 +00001513 msg_pinfo("This chipset supports the following protocols: %s.\n",
Uwe Hermann9899cad2009-06-28 21:47:57 +00001514 flashbuses_to_text(buses_supported));
Uwe Hermanna7e05482007-05-09 10:17:44 +00001515
1516 return ret;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001517}