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Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +00006 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
Carl-Daniel Hailfinger92242622007-09-27 14:29:57 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000021 */
22
23/*
24 * Contains the board specific flash enables.
25 */
26
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000027#include <string.h>
Mart Raudseppfaa62fb2008-02-20 11:11:18 +000028#include <fcntl.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000029#include "flash.h"
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000030
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000031/*
Uwe Hermannffec5f32007-08-23 16:08:21 +000032 * Helper functions for many Winbond Super I/Os of the W836xx range.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000033 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000034/* Enter extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000035void w836xx_ext_enter(uint16_t port)
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000036{
Andriy Gapon65c1b862008-05-22 13:22:45 +000037 OUTB(0x87, port);
38 OUTB(0x87, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000039}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000040
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000041/* Leave extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000042void w836xx_ext_leave(uint16_t port)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000043{
Andriy Gapon65c1b862008-05-22 13:22:45 +000044 OUTB(0xAA, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000045}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000046
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000047/* Generic Super I/O helper functions */
48uint8_t sio_read(uint16_t port, uint8_t reg)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000049{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000050 OUTB(reg, port);
51 return INB(port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000052}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000053
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000054void sio_write(uint16_t port, uint8_t reg, uint8_t data)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000055{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000056 OUTB(reg, port);
57 OUTB(data, port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000058}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000059
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000060void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000061{
Ronald G. Minnichfa496922007-10-12 21:22:40 +000062 uint8_t tmp;
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000063
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000064 OUTB(reg, port);
65 tmp = INB(port + 1) & ~mask;
66 OUTB(tmp | (data & mask), port + 1);
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000067}
68
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000069/* Not used yet. */
70#if 0
71static int enable_flash_decode_superio(void)
72{
73 int ret;
74 uint8_t tmp;
75
76 switch (superio.vendor) {
77 case SUPERIO_VENDOR_NONE:
78 ret = -1;
79 break;
80 case SUPERIO_VENDOR_ITE:
81 enter_conf_mode_ite(superio.port);
Uwe Hermann43959702010-03-13 17:28:29 +000082 /* Enable flash mapping. Works for most old ITE style Super I/O. */
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000083 tmp = sio_read(superio.port, 0x24);
84 tmp |= 0xfc;
85 sio_write(superio.port, 0x24, tmp);
86 exit_conf_mode_ite(superio.port);
87 ret = 0;
88 break;
89 default:
Uwe Hermann43959702010-03-13 17:28:29 +000090 printf_debug("Unhandled Super I/O type!\n");
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000091 ret = -1;
92 break;
93 }
94 return ret;
95}
96#endif
97
Uwe Hermannffec5f32007-08-23 16:08:21 +000098/**
99 * Winbond W83627HF: Raise GPIO24.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000100 *
101 * Suited for:
Uwe Hermannffec5f32007-08-23 16:08:21 +0000102 * - Agami Aruma
103 * - IWILL DK8-HTX
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000104 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000105static int w83627hf_gpio24_raise(uint16_t port, const char *name)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000106{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000107 w836xx_ext_enter(port);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000108
Uwe Hermann372eeb52007-12-04 21:49:06 +0000109 /* Is this the W83627HF? */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000110 if (sio_read(port, 0x20) != 0x52) { /* Super I/O device ID reg. */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000111 fprintf(stderr, "\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n",
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000112 name, sio_read(port, 0x20));
113 w836xx_ext_leave(port);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000114 return -1;
115 }
116
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000117 /* PIN89S: WDTO/GP24 multiplex -> GPIO24 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000118 sio_mask(port, 0x2B, 0x10, 0x10);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000119
Uwe Hermann372eeb52007-12-04 21:49:06 +0000120 /* Select logical device 8: GPIO port 2 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000121 sio_write(port, 0x07, 0x08);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000122
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000123 sio_mask(port, 0x30, 0x01, 0x01); /* Activate logical device. */
124 sio_mask(port, 0xF0, 0x00, 0x10); /* GPIO24 -> output */
125 sio_mask(port, 0xF2, 0x00, 0x10); /* Clear GPIO24 inversion */
126 sio_mask(port, 0xF1, 0x10, 0x10); /* Raise GPIO24 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000127
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000128 w836xx_ext_leave(port);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000129
130 return 0;
131}
132
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000133static int w83627hf_gpio24_raise_2e(const char *name)
134{
Mondrian nuessle197d6cd2009-04-09 14:28:36 +0000135 return w83627hf_gpio24_raise(0x2e, name);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000136}
137
138/**
139 * Winbond W83627THF: GPIO 4, bit 4
140 *
141 * Suited for:
Peter Stugecce26822008-07-21 17:48:40 +0000142 * - MSI K8T Neo2-F
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000143 * - MSI K8N-NEO3
144 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000145static int w83627thf_gpio4_4_raise(uint16_t port, const char *name)
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000146{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000147 w836xx_ext_enter(port);
Uwe Hermann372eeb52007-12-04 21:49:06 +0000148
149 /* Is this the W83627THF? */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000150 if (sio_read(port, 0x20) != 0x82) { /* Super I/O device ID reg. */
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000151 fprintf(stderr, "\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n",
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000152 name, sio_read(port, 0x20));
153 w836xx_ext_leave(port);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000154 return -1;
155 }
156
157 /* PINxxxxS: GPIO4/bit 4 multiplex -> GPIOXXX */
158
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000159 sio_write(port, 0x07, 0x09); /* Select LDN 9: GPIO port 4 */
160 sio_mask(port, 0x30, 0x02, 0x02); /* Activate logical device. */
161 sio_mask(port, 0xF4, 0x00, 0x10); /* GPIO4 bit 4 -> output */
162 sio_mask(port, 0xF6, 0x00, 0x10); /* Clear GPIO4 bit 4 inversion */
163 sio_mask(port, 0xF5, 0x10, 0x10); /* Raise GPIO4 bit 4 */
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000164
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000165 w836xx_ext_leave(port);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000166
167 return 0;
168}
169
Peter Stugecce26822008-07-21 17:48:40 +0000170static int w83627thf_gpio4_4_raise_2e(const char *name)
171{
172 return w83627thf_gpio4_4_raise(0x2e, name);
173}
174
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000175static int w83627thf_gpio4_4_raise_4e(const char *name)
176{
Uwe Hermann372eeb52007-12-04 21:49:06 +0000177 return w83627thf_gpio4_4_raise(0x4e, name);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000178}
Uwe Hermann372eeb52007-12-04 21:49:06 +0000179
Uwe Hermannffec5f32007-08-23 16:08:21 +0000180/**
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000181 * w83627: Enable MEMW# and set ROM size to max.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000182 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000183static void w836xx_memw_enable(uint16_t port)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000184{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000185 w836xx_ext_enter(port);
186 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000187 /* Enable MEMW# and set ROM size select to max. (4M). */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000188 sio_mask(port, 0x24, 0x28, 0x28);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000189 }
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000190 w836xx_ext_leave(port);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000191}
192
193/**
Luc Verhaegen73d21192009-12-23 00:54:26 +0000194 * Suited for:
195 * - EPoX EP-8K5A2: VIA KT333 + VT8235.
196 * - Albatron PM266A Pro: VIA P4M266A + VT8235.
197 * - Shuttle AK31 (all versions): VIA KT266 + VT8233.
198 * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
199 * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000200 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000201static int w836xx_memw_enable_2e(const char *name)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000202{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000203 w836xx_memw_enable(0x2E);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000204
Luc Verhaegen73d21192009-12-23 00:54:26 +0000205 return 0;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000206}
207
Luc Verhaegen21f54962010-01-20 14:45:07 +0000208/**
Daniel Brandt4ad4c742010-03-21 13:36:20 +0000209 * Suited for:
210 * - Termtek TK-3370 (rev. 2.5b)
211 */
212static int w836xx_memw_enable_4e(const char *name)
213{
214 w836xx_memw_enable(0x4E);
215
216 return 0;
217}
218
219/**
Luc Verhaegen21f54962010-01-20 14:45:07 +0000220 *
221 */
222static int it8705f_write_enable(uint8_t port, const char *name)
223{
224 enter_conf_mode_ite(port);
225 sio_mask(port, 0x24, 0x04, 0x04); /* Flash ROM I/F Writes Enable */
226 exit_conf_mode_ite(port);
227
228 return 0;
229}
230
231/**
232 * Suited for:
233 * - AOpen vKM400Am-S: VIA KM400 + VT8237 + IT8705F.
234 * - Biostar P4M80-M4: VIA P4M800 + VT8237 + IT8705AF
235 * - Elitegroup K7S6A: SiS745 + ITE IT8705F
236 * - Elitegroup K7VTA3: VIA Apollo KT266/A/333 + VIA VT8235 + ITE IT8705F
237 * - GIGABYTE GA-7VT600: VIA KT600 + VT8237 + IT8705
238 * - Shuttle AK38N: VIA KT333CF + VIA VT8235 + ITE IT8705F
239 *
Uwe Hermann43959702010-03-13 17:28:29 +0000240 * The SIS950 Super I/O probably requires the same flash write enable.
Luc Verhaegen21f54962010-01-20 14:45:07 +0000241 */
242static int it8705f_write_enable_2e(const char *name)
243{
244 return it8705f_write_enable(0x2e, name);
245}
Luc Verhaegen73d21192009-12-23 00:54:26 +0000246
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000247static int pc87360_gpio_set(uint8_t gpio, int raise)
248{
249 static const int bankbase[] = {0, 4, 8, 10, 12};
250 int gpio_bank = gpio / 8;
251 int gpio_pin = gpio % 8;
252 uint16_t baseport;
Uwe Hermann43959702010-03-13 17:28:29 +0000253 uint8_t id, val;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000254
Uwe Hermann43959702010-03-13 17:28:29 +0000255 if (gpio_bank > 4) {
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000256 fprintf(stderr, "PC87360: Invalid GPIO %d\n", gpio);
257 return -1;
258 }
259
260 id = sio_read(0x2E, 0x20);
Uwe Hermann43959702010-03-13 17:28:29 +0000261 if (id != 0xE1) {
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000262 fprintf(stderr, "PC87360: unexpected ID %02x\n", id);
263 return -1;
264 }
265
Uwe Hermann43959702010-03-13 17:28:29 +0000266 sio_write(0x2E, 0x07, 0x07); /* Select GPIO device */
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000267 baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
Uwe Hermann43959702010-03-13 17:28:29 +0000268 if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) {
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000269 fprintf (stderr, "PC87360: invalid GPIO base address %04x\n",
270 baseport);
271 return -1;
272 }
273 sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device */
Uwe Hermann43959702010-03-13 17:28:29 +0000274 sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin);
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000275 sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output */
276
277 val = INB(baseport + bankbase[gpio_bank]);
Uwe Hermann43959702010-03-13 17:28:29 +0000278 if (raise)
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000279 val |= 1 << gpio_pin;
280 else
281 val &= ~(1 << gpio_pin);
282 OUTB(val, baseport + bankbase[gpio_bank]);
283
284 return 0;
285}
286
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000287/**
288 * VT823x: Set one of the GPIO pins.
289 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000290static int via_vt823x_gpio_set(uint8_t gpio, int raise)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000291{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000292 struct pci_dev *dev;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000293 uint16_t base;
David Bartleyf58d3642009-12-09 07:53:01 +0000294 uint8_t val, bit, offset;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000295
Luc Verhaegen73d21192009-12-23 00:54:26 +0000296 dev = pci_dev_find_vendorclass(0x1106, 0x0601);
297 switch (dev->device_id) {
298 case 0x3177: /* VT8235 */
299 case 0x3227: /* VT8237R */
300 case 0x3337: /* VT8237A */
301 break;
302 default:
303 fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n");
304 return -1;
305 }
306
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000307 if ((gpio >= 12) && (gpio <= 15)) {
308 /* GPIO12-15 -> output */
309 val = pci_read_byte(dev, 0xE4);
310 val |= 0x10;
311 pci_write_byte(dev, 0xE4, val);
312 } else if (gpio == 9) {
313 /* GPIO9 -> Output */
314 val = pci_read_byte(dev, 0xE4);
315 val |= 0x20;
316 pci_write_byte(dev, 0xE4, val);
David Bartleyf58d3642009-12-09 07:53:01 +0000317 } else if (gpio == 5) {
318 val = pci_read_byte(dev, 0xE4);
319 val |= 0x01;
320 pci_write_byte(dev, 0xE4, val);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000321 } else {
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000322 fprintf(stderr, "\nERROR: "
323 "VT823x GPIO%02d is not implemented.\n", gpio);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000324 return -1;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000325 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000326
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000327 /* We need the I/O Base Address for this board's flash enable. */
328 base = pci_read_word(dev, 0x88) & 0xff80;
329
David Bartleyf58d3642009-12-09 07:53:01 +0000330 offset = 0x4C + gpio / 8;
331 bit = 0x01 << (gpio % 8);
332
333 val = INB(base + offset);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000334 if (raise)
335 val |= bit;
336 else
337 val &= ~bit;
David Bartleyf58d3642009-12-09 07:53:01 +0000338 OUTB(val, base + offset);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000339
Uwe Hermanna7e05482007-05-09 10:17:44 +0000340 return 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000341}
342
Uwe Hermannffec5f32007-08-23 16:08:21 +0000343/**
Luc Verhaegen73d21192009-12-23 00:54:26 +0000344 * Suited for Asus M2V-MX: VIA K8M890 + VT8237A + IT8716F
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000345 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000346static int via_vt823x_gpio5_raise(const char *name)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000347{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000348 /* On M2V-MX: GPO5 is connected to WP# and TBL#. */
349 return via_vt823x_gpio_set(5, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000350}
351
352/**
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000353 * Suited for VIAs EPIA N & NL.
354 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000355static int via_vt823x_gpio9_raise(const char *name)
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000356{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000357 return via_vt823x_gpio_set(9, 1);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000358}
359
360/**
Luc Verhaegen73d21192009-12-23 00:54:26 +0000361 * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs.
362 *
363 * We don't need to do this for EPIA M when using coreboot, GPIO15 is never
364 * lowered there.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000365 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000366static int via_vt823x_gpio15_raise(const char *name)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000367{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000368 return via_vt823x_gpio_set(15, 1);
369}
370
371/**
372 * Winbond W83697HF Super I/O + VIA VT8235 southbridge
373 *
374 * Suited for:
375 * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
376 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
377 */
378static int board_msi_kt4v(const char *name)
379{
380 int ret;
381
382 ret = via_vt823x_gpio_set(12, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000383 w836xx_memw_enable(0x2E);
Luc Verhaegen97866082008-02-09 02:03:06 +0000384
Luc Verhaegen73d21192009-12-23 00:54:26 +0000385 return ret;
Luc Verhaegen97866082008-02-09 02:03:06 +0000386}
387
388/**
Luc Verhaegen6b141752007-05-20 16:16:13 +0000389 * Suited for ASUS P5A.
390 *
391 * This is rather nasty code, but there's no way to do this cleanly.
392 * We're basically talking to some unknown device on SMBus, my guess
393 * is that it is the Winbond W83781D that lives near the DIP BIOS.
394 */
Luc Verhaegen6b141752007-05-20 16:16:13 +0000395static int board_asus_p5a(const char *name)
396{
397 uint8_t tmp;
398 int i;
399
400#define ASUSP5A_LOOP 5000
401
Andriy Gapon65c1b862008-05-22 13:22:45 +0000402 OUTB(0x00, 0xE807);
403 OUTB(0xEF, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000404
Andriy Gapon65c1b862008-05-22 13:22:45 +0000405 OUTB(0xFF, 0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000406
407 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000408 OUTB(0xE1, 0xFF);
409 if (INB(0xE800) & 0x04)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000410 break;
411 }
412
413 if (i == ASUSP5A_LOOP) {
414 printf("%s: Unable to contact device.\n", name);
415 return -1;
416 }
417
Andriy Gapon65c1b862008-05-22 13:22:45 +0000418 OUTB(0x20, 0xE801);
419 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000420
Andriy Gapon65c1b862008-05-22 13:22:45 +0000421 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000422
423 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000424 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000425 if (tmp & 0x70)
426 break;
427 }
428
429 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
430 printf("%s: failed to read device.\n", name);
431 return -1;
432 }
433
Andriy Gapon65c1b862008-05-22 13:22:45 +0000434 tmp = INB(0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000435 tmp &= ~0x02;
436
Andriy Gapon65c1b862008-05-22 13:22:45 +0000437 OUTB(0x00, 0xE807);
438 OUTB(0xEE, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000439
Andriy Gapon65c1b862008-05-22 13:22:45 +0000440 OUTB(tmp, 0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000441
Andriy Gapon65c1b862008-05-22 13:22:45 +0000442 OUTB(0xFF, 0xE800);
443 OUTB(0xE1, 0xFF);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000444
Andriy Gapon65c1b862008-05-22 13:22:45 +0000445 OUTB(0x20, 0xE801);
446 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000447
Andriy Gapon65c1b862008-05-22 13:22:45 +0000448 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000449
450 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000451 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000452 if (tmp & 0x70)
453 break;
454 }
455
456 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
457 printf("%s: failed to write to device.\n", name);
458 return -1;
459 }
460
461 return 0;
462}
463
Luc Verhaegena7e30502009-12-09 11:39:02 +0000464/*
465 * Set GPIO lines in the Broadcom HT-1000 southbridge.
466 *
467 * It's not a Super I/O but it uses the same index/data port method.
468 */
469static int board_hp_dl145_g3_enable(const char *name)
470{
471 /* GPIO 0 reg from PM regs */
472 /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
473 sio_mask(0xcd6, 0x44, 0x24, 0x24);
474
475 return 0;
476}
477
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000478static int board_ibm_x3455(const char *name)
479{
Luc Verhaegena7e30502009-12-09 11:39:02 +0000480 /* raise gpio13 */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +0000481 sio_mask(0xcd6, 0x45, 0x20, 0x20);
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000482
483 return 0;
484}
485
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000486/**
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000487 * Suited for Shuttle FN25 (SN25P): AMD S939 + Nvidia CK804 (nForce4).
488 */
489static int board_shuttle_fn25(const char *name)
490{
491 struct pci_dev *dev;
492
493 dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA Bridge. */
494 if (!dev) {
495 fprintf(stderr,
496 "\nERROR: NVIDIA nForce4 ISA bridge not found.\n");
497 return -1;
498 }
499
500 /* one of those bits seems to be connected to TBL#, but -ENOINFO. */
501 pci_write_byte(dev, 0x92, 0);
502
503 return 0;
504}
505
506/**
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000507 * Very similar to AMD 8111 IO Hub.
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000508 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000509static int nvidia_mcp_gpio_set(int gpio, int raise)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000510{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000511 struct pci_dev *dev;
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000512 uint16_t base;
513 uint8_t tmp;
514
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000515 if ((gpio < 0) || (gpio >= 0x40)) {
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000516 fprintf(stderr, "\nERROR: unsupported GPIO: %d.\n", gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000517 return -1;
518 }
519
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000520 /* First, check the ISA Bridge */
521 dev = pci_dev_find_vendorclass(0x10DE, 0x0601);
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000522 switch (dev->device_id) {
523 case 0x0030: /* CK804 */
524 case 0x0050: /* MCP04 */
525 case 0x0060: /* MCP2 */
526 break;
527 default:
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000528 /* Newer MCPs use the SMBus Controller */
529 dev = pci_dev_find_vendorclass(0x10DE, 0x0C05);
530 switch (dev->device_id) {
531 case 0x0264: /* MCP51 */
532 break;
533 default:
534 fprintf(stderr,
535 "\nERROR: no nVidia LPC/SMBus controller found.\n");
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000536 return -1;
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000537 }
538 break;
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000539 }
540
541 base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
542 base += 0xC0;
543
544 tmp = INB(base + gpio);
545 tmp &= ~0x0F; /* null lower nibble */
546 tmp |= 0x04; /* gpio -> output. */
547 if (raise)
548 tmp |= 0x01;
549 OUTB(tmp, base + gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000550
551 return 0;
552}
553
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000554/**
Sean Nelson392e05a2010-03-19 22:58:15 +0000555 * Suited for ASUS A8N-LA: nVidia MCP51.
Michael Karcherb2184c12010-03-07 16:42:55 +0000556 * Suited for ASUS M2NBP-VM CSM: nVidia MCP51.
557 */
558static int nvidia_mcp_gpio0_raise(const char *name)
559{
560 return nvidia_mcp_gpio_set(0x00, 1);
561}
562
563/**
Sean Nelson92bc6bd2010-03-19 22:37:29 +0000564 * Suited for Abit KN8 Ultra: nVidia CK804.
565 */
566static int nvidia_mcp_gpio2_lower(const char *name)
567{
568 return nvidia_mcp_gpio_set(0x02, 0);
569}
570
571/**
Luc Verhaegen6c5f7332009-12-23 03:01:36 +0000572 * Suited for MSI K8N Neo4: nVidia CK804.
Michael Karcher5fdf2702010-03-07 16:52:59 +0000573 * Suited for MSI K8N GM2-L: nVidia MCP51.
Luc Verhaegen6c5f7332009-12-23 03:01:36 +0000574 */
575static int nvidia_mcp_gpio2_raise(const char *name)
576{
577 return nvidia_mcp_gpio_set(0x02, 1);
578}
579
580/**
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000581 * Suited for ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04.
582 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000583static int nvidia_mcp_gpio10_raise(const char *name)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000584{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000585 return nvidia_mcp_gpio_set(0x10, 1);
586}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000587
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000588/**
589 * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge.
590 */
591static int nvidia_mcp_gpio21_raise(const char *name)
592{
593 return nvidia_mcp_gpio_set(0x21, 0x01);
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000594}
595
Luc Verhaegen2c04fab2009-10-05 18:46:35 +0000596/**
597 * Suited for EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2.
598 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000599static int nvidia_mcp_gpio31_raise(const char *name)
Luc Verhaegen2c04fab2009-10-05 18:46:35 +0000600{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000601 return nvidia_mcp_gpio_set(0x31, 0x01);
Luc Verhaegen2c04fab2009-10-05 18:46:35 +0000602}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000603
Luc Verhaegenfdd0c582007-08-11 16:59:11 +0000604/**
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000605 * Suited for Artec Group DBE61 and DBE62.
606 */
607static int board_artecgroup_dbe6x(const char *name)
608{
609#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
610#define DBE6x_PRI_BOOT_LOC_SHIFT (2)
611#define DBE6x_BOOT_OP_LATCHED_SHIFT (8)
612#define DBE6x_SEC_BOOT_LOC_SHIFT (10)
613#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
614#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
615#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
616#define DBE6x_BOOT_LOC_FLASH (2)
617#define DBE6x_BOOT_LOC_FWHUB (3)
618
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000619 msr_t msr;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000620 unsigned long boot_loc;
621
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000622 /* Geode only has a single core */
623 if (setup_cpu_msr(0))
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000624 return -1;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000625
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000626 msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000627
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000628 if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) ==
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000629 (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
630 boot_loc = DBE6x_BOOT_LOC_FWHUB;
631 else
632 boot_loc = DBE6x_BOOT_LOC_FLASH;
633
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000634 msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
635 msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
Uwe Hermann394131e2008-10-18 21:14:13 +0000636 (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000637
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000638 wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000639
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000640 cleanup_cpu_msr();
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000641
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000642 return 0;
643}
644
Uwe Hermann93f66db2008-05-22 21:19:38 +0000645/**
Luc Verhaegenf5226912009-12-14 10:41:58 +0000646 * Helper function to raise/drop a given gpo line on intel PIIX4{,E,M}
647 */
648static int intel_piix4_gpo_set(unsigned int gpo, int raise)
649{
Michael Karcher01f6d7d2010-02-24 00:00:21 +0000650 unsigned int gpo_byte, gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +0000651 struct pci_dev *dev;
652 uint32_t tmp, base;
653
654 dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */
655 if (!dev) {
656 fprintf(stderr, "\nERROR: Intel PIIX4 ISA bridge not found.\n");
657 return -1;
658 }
659
660 /* sanity check */
661 if (gpo > 30) {
662 fprintf(stderr, "\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);
663 return -1;
664 }
665
666 /* these are dual function pins which are most likely in use already */
667 if (((gpo >= 1) && (gpo <= 7)) ||
668 ((gpo >= 9) && (gpo <= 21)) || (gpo == 29)) {
669 fprintf(stderr, "\nERROR: Unsupported PIIX4 GPO%d.\n", gpo);
670 return -1;
671 }
672
673 /* dual function that need special enable. */
674 if ((gpo >= 22) && (gpo <= 26)) {
675 tmp = pci_read_long(dev, 0xB0); /* GENCFG */
676 switch (gpo) {
677 case 22: /* XBUS: XDIR#/GPO22 */
678 case 23: /* XBUS: XOE#/GPO23 */
679 tmp |= 1 << 28;
680 break;
681 case 24: /* RTCSS#/GPO24 */
682 tmp |= 1 << 29;
683 break;
684 case 25: /* RTCALE/GPO25 */
685 tmp |= 1 << 30;
686 break;
687 case 26: /* KBCSS#/GPO26 */
688 tmp |= 1 << 31;
689 break;
690 }
691 pci_write_long(dev, 0xB0, tmp);
692 }
693
694 /* GPO {0,8,27,28,30} are always available. */
695
696 dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */
697 if (!dev) {
698 fprintf(stderr, "\nERROR: Intel PIIX4 PM not found.\n");
699 return -1;
700 }
701
702 /* PM IO base */
703 base = pci_read_long(dev, 0x40) & 0x0000FFC0;
704
Michael Karcher01f6d7d2010-02-24 00:00:21 +0000705 gpo_byte = gpo >> 3;
706 gpo_bit = gpo & 7;
707 tmp = INB(base + 0x34 + gpo_byte); /* GPO register */
Luc Verhaegenf5226912009-12-14 10:41:58 +0000708 if (raise)
Michael Karcher01f6d7d2010-02-24 00:00:21 +0000709 tmp |= 0x01 << gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +0000710 else
Michael Karcher01f6d7d2010-02-24 00:00:21 +0000711 tmp &= ~(0x01 << gpo_bit);
712 OUTB(tmp, base + 0x34 + gpo_byte);
Luc Verhaegenf5226912009-12-14 10:41:58 +0000713
714 return 0;
715}
716
717/**
718 * Suited for EPoX EP-BX3, and maybe some other Intel 440BX based boards.
719 */
720static int board_epox_ep_bx3(const char *name)
721{
722 return intel_piix4_gpo_set(22, 1);
723}
724
725/**
Michael Karcher51cd0c92010-03-19 22:35:21 +0000726 * Suited for Intel SE440BX-2
727 */
728static int intel_piix4_gpo27_lower(const char *name)
729{
730 return intel_piix4_gpo_set(27, 0);
731}
732
733/**
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000734 * Set a GPIO line on a given intel ICH LPC controller.
Uwe Hermann93f66db2008-05-22 21:19:38 +0000735 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000736static int intel_ich_gpio_set(int gpio, int raise)
Uwe Hermann93f66db2008-05-22 21:19:38 +0000737{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000738 /* table mapping the different intel ICH LPC chipsets. */
739 static struct {
740 uint16_t id;
741 uint8_t base_reg;
742 uint32_t bank0;
743 uint32_t bank1;
744 uint32_t bank2;
745 } intel_ich_gpio_table[] = {
746 {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */
747 {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */
748 {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */
749 {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */
750 {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */
751 {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */
752 {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */
753 {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */
754 {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */
755 {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */
756 {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */
757 {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */
758 {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */
759 {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */
760 {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */
761 {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */
762 {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */
763 {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */
764 {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */
765 {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */
766 {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */
767 {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */
768 {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */
769 {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */
770 {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */
771 {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */
772 {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */
773 {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */
774 {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */
775 {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */
776 {0, 0, 0, 0, 0} /* end marker */
777 };
Uwe Hermann93f66db2008-05-22 21:19:38 +0000778
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000779 struct pci_dev *dev;
780 uint16_t base;
781 uint32_t tmp;
782 int i, allowed;
783
784 /* First, look for a known LPC bridge */
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +0000785 for (dev = pacc->devices; dev; dev = dev->next) {
786 pci_fill_info(dev, PCI_FILL_CLASS);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000787 if ((dev->vendor_id == 0x8086) &&
788 (dev->device_class == 0x0601)) { /* ISA Bridge */
789 /* Is this device in our list? */
790 for (i = 0; intel_ich_gpio_table[i].id; i++)
791 if (dev->device_id == intel_ich_gpio_table[i].id)
792 break;
793
794 if (intel_ich_gpio_table[i].id)
795 break;
796 }
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +0000797 }
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000798
Uwe Hermann93f66db2008-05-22 21:19:38 +0000799 if (!dev) {
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000800 fprintf(stderr, "\nERROR: No Known Intel LPC Bridge found.\n");
Uwe Hermann93f66db2008-05-22 21:19:38 +0000801 return -1;
802 }
803
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000804 /* According to the datasheets, all intel ICHs have the gpio bar 5:1
805 strapped to zero. From some mobile ich9 version on, this becomes
806 6:1. The mask below catches all. */
807 base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
Uwe Hermann93f66db2008-05-22 21:19:38 +0000808
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000809 /* check whether the line is allowed */
810 if (gpio < 32)
811 allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01;
812 else if (gpio < 64)
813 allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01;
814 else
815 allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;
816
817 if (!allowed) {
818 fprintf(stderr, "\nERROR: This Intel LPC Bridge does not allow"
819 " setting GPIO%02d\n", gpio);
820 return -1;
821 }
822
823 printf("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n",
824 raise ? "Rais" : "Dropp", gpio);
825
826 if (gpio < 32) {
827 /* Set line to GPIO */
828 tmp = INL(base);
829 /* ICH/ICH0 multiplexes 27/28 on the line set. */
830 if ((gpio == 28) &&
831 ((dev->device_id == 0x2410) || (dev->device_id == 0x2420)))
832 tmp |= 1 << 27;
833 else
834 tmp |= 1 << gpio;
835 OUTL(tmp, base);
836
837 /* As soon as we are talking to ICH8 and above, this register
838 decides whether we can set the gpio or not. */
839 if (dev->device_id > 0x2800) {
840 tmp = INL(base);
841 if (!(tmp & (1 << gpio))) {
842 fprintf(stderr, "\nERROR: This Intel LPC Bridge"
843 " does not allow setting GPIO%02d\n",
844 gpio);
845 return -1;
846 }
847 }
848
849 /* Set GPIO to OUTPUT */
850 tmp = INL(base + 0x04);
851 tmp &= ~(1 << gpio);
852 OUTL(tmp, base + 0x04);
853
854 /* Raise GPIO line */
855 tmp = INL(base + 0x0C);
856 if (raise)
857 tmp |= 1 << gpio;
858 else
859 tmp &= ~(1 << gpio);
860 OUTL(tmp, base + 0x0C);
861 } else if (gpio < 64) {
862 gpio -= 32;
863
864 /* Set line to GPIO */
865 tmp = INL(base + 0x30);
866 tmp |= 1 << gpio;
867 OUTL(tmp, base + 0x30);
868
869 /* As soon as we are talking to ICH8 and above, this register
870 decides whether we can set the gpio or not. */
871 if (dev->device_id > 0x2800) {
872 tmp = INL(base + 30);
873 if (!(tmp & (1 << gpio))) {
874 fprintf(stderr, "\nERROR: This Intel LPC Bridge"
875 " does not allow setting GPIO%02d\n",
876 gpio + 32);
877 return -1;
878 }
879 }
880
881 /* Set GPIO to OUTPUT */
882 tmp = INL(base + 0x34);
883 tmp &= ~(1 << gpio);
884 OUTL(tmp, base + 0x34);
885
886 /* Raise GPIO line */
887 tmp = INL(base + 0x38);
888 if (raise)
889 tmp |= 1 << gpio;
890 else
891 tmp &= ~(1 << gpio);
892 OUTL(tmp, base + 0x38);
893 } else {
894 gpio -= 64;
895
896 /* Set line to GPIO */
897 tmp = INL(base + 0x40);
898 tmp |= 1 << gpio;
899 OUTL(tmp, base + 0x40);
900
901 tmp = INL(base + 40);
902 if (!(tmp & (1 << gpio))) {
903 fprintf(stderr, "\nERROR: This Intel LPC Bridge does "
904 "not allow setting GPIO%02d\n", gpio + 64);
905 return -1;
906 }
907
908 /* Set GPIO to OUTPUT */
909 tmp = INL(base + 0x44);
910 tmp &= ~(1 << gpio);
911 OUTL(tmp, base + 0x44);
912
913 /* Raise GPIO line */
914 tmp = INL(base + 0x48);
915 if (raise)
916 tmp |= 1 << gpio;
917 else
918 tmp &= ~(1 << gpio);
919 OUTL(tmp, base + 0x48);
920 }
Uwe Hermann93f66db2008-05-22 21:19:38 +0000921
922 return 0;
923}
924
925/**
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000926 * Suited for Abit IP35: Intel P35 + ICH9R.
Michael Karcherb4a3d1c2010-03-03 16:15:12 +0000927 * Suited for Abit IP35 Pro: Intel P35 + ICH9R.
Uwe Hermann93f66db2008-05-22 21:19:38 +0000928 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000929static int intel_ich_gpio16_raise(const char *name)
Uwe Hermann93f66db2008-05-22 21:19:38 +0000930{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000931 return intel_ich_gpio_set(16, 1);
Uwe Hermann93f66db2008-05-22 21:19:38 +0000932}
933
Peter Stuge09c13332009-02-02 22:55:26 +0000934/**
James Lancaster998c9dc2010-03-19 22:39:24 +0000935 * Suited for ASUS A8JM: Intel 945 + ICH7
936 */
937static int intel_ich_gpio34_raise(const char *name)
938{
939 return intel_ich_gpio_set(34, 1);
940}
941
942/**
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000943 * Suited for MSI MS-7046: LGA775 + 915P + ICH6.
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +0000944 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000945static int intel_ich_gpio19_raise(const char *name)
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +0000946{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000947 return intel_ich_gpio_set(19, 1);
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +0000948}
949
950/**
Luc Verhaegen6c5d4cc2009-11-28 18:26:21 +0000951 * Suited for:
952 * - Asus P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2.
Michael Karcher6499d5a2010-03-17 06:19:23 +0000953 * - Asus P4C800-E Deluxe: socket478 + 875P + ICH5.
Luc Verhaegen6c5d4cc2009-11-28 18:26:21 +0000954 * - Asus P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R.
Peter Stuge09c13332009-02-02 22:55:26 +0000955 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000956static int intel_ich_gpio21_raise(const char *name)
Peter Stuge09c13332009-02-02 22:55:26 +0000957{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000958 return intel_ich_gpio_set(21, 1);
Peter Stuge09c13332009-02-02 22:55:26 +0000959}
960
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000961/**
Michael Karcher03b80e92010-03-07 16:32:32 +0000962 * Suited for:
963 * - Asus P4B266: socket478 + intel 845D + ICH2.
Michael Karcher255a9e02010-03-19 22:52:00 +0000964 * - Asus P4B533-E: socket478 + 845E + ICH4
Michael Karcher03b80e92010-03-07 16:32:32 +0000965 * - Asus P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000966 */
967static int intel_ich_gpio22_raise(const char *name)
968{
969 return intel_ich_gpio_set(22, 1);
970}
971
972/**
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000973 * Suited for HP Vectra VL400: 815 + ICH + PC87360.
974 */
975
976static int board_hp_vl400(const char *name)
977{
978 int ret;
979 ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */
980 if (!ret)
981 ret = pc87360_gpio_set(0x09, 1); /* #WP ? */
982 if (!ret)
983 ret = pc87360_gpio_set(0x27, 1); /* #TBL */
984 return ret;
985}
986
987/**
Luc Verhaegen1265d8d2009-11-28 18:16:31 +0000988 * Suited for:
989 * - Dell Poweredge 1850: Intel PPGA604 + E7520 + ICH5R.
990 * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R.
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000991 */
992static int intel_ich_gpio23_raise(const char *name)
993{
994 return intel_ich_gpio_set(23, 1);
995}
996
997/**
Luc Verhaegenf63c4362010-03-19 23:01:34 +0000998 * Suited for IBase MB899: i945GM + ICH7.
999 */
1000static int intel_ich_gpio26_raise(const char *name)
1001{
1002 return intel_ich_gpio_set(26, 1);
1003}
1004
1005/**
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001006 * Suited for Acorp 6A815EPD: socket 370 + intel 815 + ICH2.
1007 */
1008static int board_acorp_6a815epd(const char *name)
1009{
1010 int ret;
1011
1012 /* Lower Blocks Lock -- pin 7 of PLCC32 */
1013 ret = intel_ich_gpio_set(22, 1);
1014 if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */
1015 ret = intel_ich_gpio_set(23, 1);
1016
1017 return ret;
1018}
1019
1020/**
1021 * Suited for Kontron 986LCD-M: socket478 + 915GM + ICH7R.
1022 */
Stefan Reinauerac378972008-03-17 22:59:40 +00001023static int board_kontron_986lcd_m(const char *name)
1024{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001025 int ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001026
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001027 ret = intel_ich_gpio_set(34, 1); /* #TBL */
1028 if (!ret)
1029 ret = intel_ich_gpio_set(35, 1); /* #WP */
Stefan Reinauerac378972008-03-17 22:59:40 +00001030
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +00001031 return ret;
Stefan Reinauerac378972008-03-17 22:59:40 +00001032}
1033
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001034/**
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001035 * Suited for Soyo SY-7VCA: Pro133A + VT82C686.
1036 */
Michael Karcher06477332010-03-19 22:49:09 +00001037static int via_apollo_gpo_set(int gpio, int raise)
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001038{
Michael Karcher06477332010-03-19 22:49:09 +00001039 struct pci_dev *dev;
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001040 uint32_t base;
Michael Karcher06477332010-03-19 22:49:09 +00001041 uint32_t tmp;
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001042
1043 /* VT82C686 Power management */
1044 dev = pci_dev_find(0x1106, 0x3057);
1045 if (!dev) {
1046 fprintf(stderr, "\nERROR: VT82C686 PM device not found.\n");
1047 return -1;
1048 }
1049
Michael Karcher06477332010-03-19 22:49:09 +00001050 printf("\nVIA Apollo ACPI: %sing GPIO%02d.\n",
1051 raise ? "Rais" : "Dropp", gpio);
1052
1053 /* select GPO function on multiplexed pins */
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001054 tmp = pci_read_byte(dev, 0x54);
Michael Karcher06477332010-03-19 22:49:09 +00001055 switch(gpio)
1056 {
1057 case 0:
1058 tmp &= ~0x03;
1059 break;
1060 case 1:
1061 tmp |= 0x04;
1062 break;
1063 case 2:
1064 tmp |= 0x08;
1065 break;
1066 case 3:
1067 tmp |= 0x10;
1068 break;
1069 }
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001070 pci_write_byte(dev, 0x54, tmp);
1071
1072 /* PM IO base */
1073 base = pci_read_long(dev, 0x48) & 0x0000FF00;
1074
1075 /* Drop GPO0 */
Michael Karcher06477332010-03-19 22:49:09 +00001076 tmp = INL(base + 0x4C);
1077 if (raise)
1078 tmp |= 1U << gpio;
1079 else
1080 tmp &= ~(1U << gpio);
1081 OUTL(tmp, base + 0x4C);
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001082
1083 return 0;
1084}
1085
Michael Karcher9f9e6132010-01-09 17:36:06 +00001086/**
Michael Karcher98eff462010-03-24 22:55:56 +00001087 * Suited for Abit VT6X4: Pro133x + VT82C686A
Michael Karcher187a46a2010-03-19 22:30:49 +00001088 */
1089static int via_apollo_gpo4_lower(const char *name)
1090{
1091 return via_apollo_gpo_set(4, 0);
1092}
1093
1094/**
Michael Karcher06477332010-03-19 22:49:09 +00001095 * Suited for Soyo SY-7VCA: Pro133A + VT82C686.
1096 */
1097static int via_apollo_gpo0_lower(const char *name)
1098{
1099 return via_apollo_gpo_set(0, 0);
1100}
1101
1102/**
Michael Karcher9f9e6132010-01-09 17:36:06 +00001103 * Enable some GPIO pin on SiS southbridge.
1104 * Suited for MSI 651M-L: SiS651 / SiS962
1105 */
1106static int board_msi_651ml(const char *name)
1107{
1108 struct pci_dev *dev;
Uwe Hermann43959702010-03-13 17:28:29 +00001109 uint16_t base, temp;
Michael Karcher9f9e6132010-01-09 17:36:06 +00001110
1111 dev = pci_dev_find(0x1039, 0x0962);
1112 if (!dev) {
1113 fprintf(stderr, "Expected south bridge not found\n");
1114 return 1;
1115 }
1116
1117 /* Registers 68 and 64 seem like bitmaps */
1118 base = pci_read_word(dev, 0x74);
1119 temp = INW(base + 0x68);
1120 temp &= ~(1 << 0); /* Make pin output? */
Michael Karcher0435dfd2010-01-09 23:31:13 +00001121 OUTW(temp, base + 0x68);
Michael Karcher9f9e6132010-01-09 17:36:06 +00001122
1123 temp = INW(base + 0x64);
1124 temp |= (1 << 0); /* Raise output? */
1125 OUTW(temp, base + 0x64);
1126
1127 w836xx_memw_enable(0x2E);
1128
1129 return 0;
1130}
1131
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001132/**
Michael Gold6d52e472009-06-19 13:00:24 +00001133 * Find the runtime registers of an SMSC Super I/O, after verifying its
1134 * chip ID.
1135 *
1136 * Returns the base port of the runtime register block, or 0 on error.
1137 */
1138static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
1139 uint8_t logical_device)
1140{
1141 uint16_t rt_port = 0;
1142
1143 /* Verify the chip ID. */
Uwe Hermann1432a602009-06-28 23:26:37 +00001144 OUTB(0x55, sio_port); /* Enable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00001145 if (sio_read(sio_port, 0x20) != chip_id) {
Uwe Hermann1432a602009-06-28 23:26:37 +00001146 fprintf(stderr, "\nERROR: SMSC Super I/O not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00001147 goto out;
1148 }
1149
1150 /* If the runtime block is active, get its address. */
1151 sio_write(sio_port, 0x07, logical_device);
1152 if (sio_read(sio_port, 0x30) & 1) {
1153 rt_port = (sio_read(sio_port, 0x60) << 8)
1154 | sio_read(sio_port, 0x61);
1155 }
1156
1157 if (rt_port == 0) {
1158 fprintf(stderr, "\nERROR: "
1159 "Super I/O runtime interface not available.\n");
1160 }
1161out:
Uwe Hermann1432a602009-06-28 23:26:37 +00001162 OUTB(0xaa, sio_port); /* Disable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00001163 return rt_port;
1164}
1165
1166/**
1167 * Disable write protection on the Mitac 6513WU. WP# on the FWH is
1168 * connected to GP30 on the Super I/O, and TBL# is always high.
1169 */
1170static int board_mitac_6513wu(const char *name)
1171{
1172 struct pci_dev *dev;
1173 uint16_t rt_port;
1174 uint8_t val;
1175
1176 dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */
1177 if (!dev) {
1178 fprintf(stderr, "\nERROR: Intel 82801AA ISA bridge not found.\n");
1179 return -1;
1180 }
1181
Uwe Hermann1432a602009-06-28 23:26:37 +00001182 rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa);
Michael Gold6d52e472009-06-19 13:00:24 +00001183 if (rt_port == 0)
1184 return -1;
1185
1186 /* Configure the GPIO pin. */
1187 val = INB(rt_port + 0x33); /* GP30 config */
Uwe Hermann1432a602009-06-28 23:26:37 +00001188 val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */
Michael Gold6d52e472009-06-19 13:00:24 +00001189 OUTB(val, rt_port + 0x33);
1190
1191 /* Disable write protection. */
1192 val = INB(rt_port + 0x4d); /* GP3 values */
Uwe Hermann1432a602009-06-28 23:26:37 +00001193 val |= 0x01; /* Set GP30 high. */
Michael Gold6d52e472009-06-19 13:00:24 +00001194 OUTB(val, rt_port + 0x4d);
1195
1196 return 0;
1197}
1198
1199/**
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001200 * Suited for Asus A7V8X: VIA KT400 + VT8235 + IT8703F-A
1201 */
1202static int board_asus_a7v8x(const char *name)
1203{
1204 uint16_t id, base;
1205 uint8_t tmp;
1206
1207 /* find the IT8703F */
1208 w836xx_ext_enter(0x2E);
1209 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
1210 w836xx_ext_leave(0x2E);
1211
1212 if (id != 0x8701) {
Uwe Hermann43959702010-03-13 17:28:29 +00001213 fprintf(stderr, "\nERROR: IT8703F Super I/O not found.\n");
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001214 return -1;
1215 }
1216
1217 /* Get the GP567 IO base */
1218 w836xx_ext_enter(0x2E);
1219 sio_write(0x2E, 0x07, 0x0C);
1220 base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
1221 w836xx_ext_leave(0x2E);
1222
1223 if (!base) {
Uwe Hermann43959702010-03-13 17:28:29 +00001224 fprintf(stderr, "\nERROR: Failed to read IT8703F Super I/O GPIO"
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001225 " Base.\n");
1226 return -1;
1227 }
1228
1229 /* Raise GP51. */
1230 tmp = INB(base);
1231 tmp |= 0x02;
1232 OUTB(tmp, base);
1233
1234 return 0;
1235}
1236
Luc Verhaegen72272912009-09-01 21:22:23 +00001237/*
1238 * General routine for raising/dropping GPIO lines on the ITE IT8712F.
1239 * There is only some limited checking on the port numbers.
1240 */
Uwe Hermann43959702010-03-13 17:28:29 +00001241static int it8712f_gpio_set(unsigned int line, int raise)
Luc Verhaegen72272912009-09-01 21:22:23 +00001242{
1243 unsigned int port;
1244 uint16_t id, base;
1245 uint8_t tmp;
1246
1247 port = line / 10;
1248 port--;
1249 line %= 10;
1250
1251 /* Check line */
1252 if ((port > 4) || /* also catches unsigned -1 */
1253 ((port < 4) && (line > 7)) || ((port == 4) && (line > 5))) {
1254 fprintf(stderr,
1255 "\nERROR: Unsupported IT8712F GPIO Line %02d.\n", line);
1256 return -1;
1257 }
1258
1259 /* find the IT8712F */
1260 enter_conf_mode_ite(0x2E);
1261 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
1262 exit_conf_mode_ite(0x2E);
1263
1264 if (id != 0x8712) {
Uwe Hermann43959702010-03-13 17:28:29 +00001265 fprintf(stderr, "\nERROR: IT8712F Super I/O not found.\n");
Luc Verhaegen72272912009-09-01 21:22:23 +00001266 return -1;
1267 }
1268
1269 /* Get the GPIO base */
1270 enter_conf_mode_ite(0x2E);
1271 sio_write(0x2E, 0x07, 0x07);
1272 base = (sio_read(0x2E, 0x62) << 8) | sio_read(0x2E, 0x63);
1273 exit_conf_mode_ite(0x2E);
1274
1275 if (!base) {
Uwe Hermann43959702010-03-13 17:28:29 +00001276 fprintf(stderr, "\nERROR: Failed to read IT8712F Super I/O GPIO"
Luc Verhaegen72272912009-09-01 21:22:23 +00001277 " Base.\n");
1278 return -1;
1279 }
1280
1281 /* set GPIO. */
1282 tmp = INB(base + port);
1283 if (raise)
1284 tmp |= 1 << line;
1285 else
1286 tmp &= ~(1 << line);
1287 OUTB(tmp, base + port);
1288
1289 return 0;
1290}
1291
1292/**
Russ Dillbd622d12010-03-09 16:57:06 +00001293 * Suited for:
1294 * - Asus A7V600-X: VIA KT600 + VT8237 + IT8712F
1295 * - Asus A7V8X-X: VIA KT400 + VT8235 + IT8712F
Luc Verhaegen72272912009-09-01 21:22:23 +00001296 */
Russ Dillbd622d12010-03-09 16:57:06 +00001297static int it8712f_gpio3_1_raise(const char *name)
Luc Verhaegen72272912009-09-01 21:22:23 +00001298{
1299 return it8712f_gpio_set(32, 1);
1300}
1301
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001302/**
Uwe Hermannd0e347d2009-10-06 13:00:00 +00001303 * Below is the list of boards which need a special "board enable" code in
1304 * flashrom before their ROM chip can be accessed/written to.
1305 *
1306 * NOTE: Please add boards that _don't_ need such enables or don't work yet
1307 * to the respective tables in print.c. Thanks!
1308 *
Uwe Hermannffec5f32007-08-23 16:08:21 +00001309 * We use 2 sets of IDs here, you're free to choose which is which. This
1310 * is to provide a very high degree of certainty when matching a board on
1311 * the basis of subsystem/card IDs. As not every vendor handles
1312 * subsystem/card IDs in a sane manner.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001313 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00001314 * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00001315 * NULLed if they don't identify the board fully and if you can't use DMI.
1316 * But please take care to provide an as complete set of pci ids as possible;
1317 * autodetection is the preferred behaviour and we would like to make sure that
1318 * matches are unique.
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001319 *
Michael Karcher6701ee82010-01-20 14:14:11 +00001320 * If PCI IDs are not sufficient for board matching, the match can be further
1321 * constrained by a string that has to be present in the DMI database for
1322 * the baseboard or the system entry. The pattern is matched by case sensitve
1323 * substring match, unless it is anchored to the beginning (with a ^ in front)
1324 * or the end (with a $ at the end). Both anchors may be specified at the
1325 * same time to match the full field.
1326 *
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00001327 * When a board is matched through DMI, the first and second main PCI IDs
1328 * and the first subsystem PCI ID have to match as well. If you specify the
1329 * first subsystem ID as 0x0:0x0, the DMI matching code expects that the
1330 * subsystem ID of that device is indeed zero.
1331 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00001332 * The coreboot ids are used two fold. When running with a coreboot firmware,
1333 * the ids uniquely matches the coreboot board identification string. When a
1334 * legacy bios is installed and when autodetection is not possible, these ids
1335 * can be used to identify the board through the -m command line argument.
1336 *
1337 * When a board is identified through its coreboot ids (in both cases), the
1338 * main pci ids are still required to match, as a safeguard.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001339 */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001340
Uwe Hermanndeeebe22009-05-08 16:23:34 +00001341/* Please keep this list alphabetically ordered by vendor/board name. */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001342struct board_pciid_enable board_pciid_enables[] = {
Uwe Hermann5ab88892009-06-21 20:50:22 +00001343
Michael Karcher0bdc0922010-02-28 01:33:48 +00001344 /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */
Sean Nelsonc94746d2010-03-19 23:00:07 +00001345 {0x10DE, 0x0547, 0x147B, 0x1C2F, 0x10DE, 0x0548, 0x147B, 0x1C2F, NULL, NULL, NULL, "Abit", "AN-M2", 0, NT, nvidia_mcp_gpio2_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001346 {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise},
Michael Karcherb4a3d1c2010-03-03 16:15:12 +00001347 {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise},
Sean Nelson92bc6bd2010-03-19 22:37:29 +00001348 {0x10de, 0x0050, 0x147b, 0x1c1a, 0, 0, 0, 0, NULL, NULL, NULL, "Abit", "KN8 Ultra", 0, NT, nvidia_mcp_gpio2_lower},
Michael Karcher98eff462010-03-24 22:55:56 +00001349 {0x1106, 0x0691, 0, 0, 0x1106, 0x3057, 0, 0, NULL, "abit", "vt6x4", "Abit", "VT6X4", 0, OK, via_apollo_gpo4_lower},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001350 {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd},
1351 {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise},
1352 {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e},
1353 {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A", 0, OK, w836xx_memw_enable_2e},
1354 {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, NULL, "AOpen", "vKM400Am-S", 0, OK, it8705f_write_enable_2e},
1355 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x},
1356 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x},
Russ Dillbd622d12010-03-09 16:57:06 +00001357 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001358 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, board_asus_a7v8x},
Russ Dillbd622d12010-03-09 16:57:06 +00001359 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001360 {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e},
James Lancaster998c9dc2010-03-19 22:39:24 +00001361 {0x8086, 0x27A0, 0x1043, 0x1287, 0x8086, 0x27DF, 0x1043, 0x1287, "^A8J", NULL, NULL, "ASUS", "A8JM", 0, NT, intel_ich_gpio34_raise},
Luc Verhaegen49146c12010-03-19 22:26:44 +00001362 {0x10DE, 0x005E, 0x1043, 0x815A, 0x10DE, 0x0054, 0x1043, 0x815A, NULL, NULL, NULL, "ASUS", "A8N", 0, NT, board_shuttle_fn25},
Sean Nelson392e05a2010-03-19 22:58:15 +00001363 {0x10DE, 0x0260, 0x103c, 0x2a3e, 0x10DE, 0x0264, 0x103c, 0x2a3e, "NAGAMI", NULL, NULL, "ASUS", "A8N-LA", 0, NT, nvidia_mcp_gpio0_raise},
Michael Karcherb2184c12010-03-07 16:42:55 +00001364 {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001365 {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise},
1366 {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise},
1367 {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise},
Michael Karcher255a9e02010-03-19 22:52:00 +00001368 {0x8086, 0x1A30, 0x1043, 0x8088, 0x8086, 0x24C3, 0x1043, 0x8089, NULL, NULL, NULL, "ASUS", "P4B533-E", 0, NT, intel_ich_gpio22_raise},
Michael Karcher6499d5a2010-03-17 06:19:23 +00001369 {0x8086, 0x24D3, 0x1043, 0x80A6, 0x8086, 0x2578, 0x1043, 0x80F6, NULL, NULL, NULL, "ASUS", "P4C800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001370 {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
1371 {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a},
1372 {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise},
1373 {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, NULL, "Biostar", "P4M80-M4", 0, OK, it8705f_write_enable_2e},
1374 {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise},
1375 {0x1039, 0x5513, 0x1019, 0x0A41, 0x1039, 0x0018, 0, 0, NULL, NULL, NULL, "Elitegroup", "K7S6A", 0, OK, it8705f_write_enable_2e},
1376 {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, it8705f_write_enable_2e},
1377 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e},
1378 {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise},
1379 {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", "EPoX", "EP-BX3", 0, OK, board_epox_ep_bx3},
1380 {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL},
1381 {0x1039, 0x0761, 0, 0, 0x10EC, 0x8168, 0, 0, NULL, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", 0, OK, it87xx_probe_spi_flash},
1382 {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, NULL, "GIGABYTE", "GA-7VT600", 0, OK, it8705f_write_enable_2e},
1383 {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise},
1384 {0x10DE, 0x0360, 0x1458, 0x0C11, 0x10DE, 0x0369, 0x1458, 0x5001, NULL, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", 0, OK, it87xx_probe_spi_flash},
1385 {0x10de, 0x03e0, 0, 0, 0x10DE, 0x03D0, 0, 0, NULL, NULL, NULL, "GIGABYTE", "GA-M61P-S3", 0, OK, it87xx_probe_spi_flash},
Raúl Soriano8111e7f2010-03-14 00:00:14 +00001386 {0x1002, 0x7910, 0x1458, 0x5000, 0x1002, 0x438D, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-MA69VM-S2", 0, OK, it87xx_probe_spi_flash},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001387 {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, NULL, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", 0, OK, it87xx_probe_spi_flash},
Peter Lemenkov064f1662010-03-19 22:55:48 +00001388 {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb002, "^GA-MA78GM-S2H$", NULL, NULL, "GIGABYTE", "GA-MA78GM-S2H", 0, OK, it87xx_probe_spi_flash},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001389 {0x1002, 0x438d, 0x1458, 0x5001, 0x1002, 0x5956, 0x1002, 0x5956, NULL, NULL, NULL, "GIGABYTE", "GA-MA790FX-DQ6", 0, OK, it87xx_probe_spi_flash},
1390 {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable},
1391 {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400},
Michael Karcher03b80e92010-03-07 16:32:32 +00001392 {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise},
Luc Verhaegenf63c4362010-03-19 23:01:34 +00001393 {0x8086, 0x27A0, 0, 0, 0x8086, 0x27B9, 0, 0, NULL, "ibase", "mb899", "iBASE", "MB899", 0, NT, intel_ich_gpio26_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001394 {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455},
1395 {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi},
Michael Karcher51cd0c92010-03-19 22:35:21 +00001396 {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001397 {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e},
James Lancaster998c9dc2010-03-19 22:39:24 +00001398 {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001399 {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, "Mitac", "6513WU", 0, OK, board_mitac_6513wu},
1400 {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v},
1401 {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio4_4_raise_2e},
1402 {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v},
1403 {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml},
1404 {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise},
1405 {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio4_4_raise_4e},
Michael Karcher5fdf2702010-03-07 16:52:59 +00001406 {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001407 {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise},
1408 {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e},
1409 {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, it8705f_write_enable_2e},
1410 {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25},
Michael Karcher06477332010-03-19 22:49:09 +00001411 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, OK, via_apollo_gpo0_lower},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001412 {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e},
1413 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, OK, NULL},
Daniel Brandt4ad4c742010-03-21 13:36:20 +00001414 {0x1106, 0x3123, 0x1106, 0x3123, 0x1106, 0x3059, 0x1106, 0x4161, NULL, NULL, NULL, "Termtek", "TK-3370 (Rev:2.5B)", 0, OK, w836xx_memw_enable_4e},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001415 {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise},
1416 {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise},
1417 {0x1106, 0x5337, 0x1458, 0xb003, 0x1106, 0x287e, 0x1106, 0x337e, NULL, NULL, NULL, "VIA", "PC3500G", 0, OK, it87xx_probe_spi_flash},
Luc Verhaegen93938c32010-01-20 14:45:03 +00001418
Michael Karcher0bdc0922010-02-28 01:33:48 +00001419 { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001420};
1421
Uwe Hermannffec5f32007-08-23 16:08:21 +00001422/**
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00001423 * Match boards on coreboot table gathered vendor and part name.
Uwe Hermannffec5f32007-08-23 16:08:21 +00001424 * Require main PCI IDs to match too as extra safety.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001425 */
Uwe Hermann394131e2008-10-18 21:14:13 +00001426static struct board_pciid_enable *board_match_coreboot_name(const char *vendor,
1427 const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001428{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001429 struct board_pciid_enable *board = board_pciid_enables;
Peter Stuge6b53fed2008-01-27 16:21:21 +00001430 struct board_pciid_enable *partmatch = NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001431
Uwe Hermanna93045c2009-05-09 00:47:04 +00001432 for (; board->vendor_name; board++) {
Uwe Hermann394131e2008-10-18 21:14:13 +00001433 if (vendor && (!board->lb_vendor
1434 || strcasecmp(board->lb_vendor, vendor)))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001435 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001436
Peter Stuge0b9c5f32008-07-02 00:47:30 +00001437 if (!board->lb_part || strcasecmp(board->lb_part, part))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001438 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001439
Uwe Hermanna7e05482007-05-09 10:17:44 +00001440 if (!pci_dev_find(board->first_vendor, board->first_device))
1441 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001442
Uwe Hermanna7e05482007-05-09 10:17:44 +00001443 if (board->second_vendor &&
Uwe Hermann394131e2008-10-18 21:14:13 +00001444 !pci_dev_find(board->second_vendor, board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001445 continue;
Peter Stuge6b53fed2008-01-27 16:21:21 +00001446
1447 if (vendor)
1448 return board;
1449
1450 if (partmatch) {
1451 /* a second entry has a matching part name */
1452 printf("AMBIGUOUS BOARD NAME: %s\n", part);
1453 printf("At least vendors '%s' and '%s' match.\n",
Uwe Hermann394131e2008-10-18 21:14:13 +00001454 partmatch->lb_vendor, board->lb_vendor);
Peter Stuge6b53fed2008-01-27 16:21:21 +00001455 printf("Please use the full -m vendor:part syntax.\n");
1456 return NULL;
1457 }
1458 partmatch = board;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001459 }
Uwe Hermann372eeb52007-12-04 21:49:06 +00001460
Peter Stuge6b53fed2008-01-27 16:21:21 +00001461 if (partmatch)
1462 return partmatch;
1463
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00001464 if (!partvendor_from_cbtable) {
1465 /* Only warn if the mainboard type was not gathered from the
1466 * coreboot table. If it was, the coreboot implementor is
1467 * expected to fix flashrom, too.
1468 */
1469 printf("\nUnknown vendor:board from -m option: %s:%s\n\n",
1470 vendor, part);
1471 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00001472 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001473}
1474
Uwe Hermannffec5f32007-08-23 16:08:21 +00001475/**
1476 * Match boards on PCI IDs and subsystem IDs.
1477 * Second set of IDs can be main only or missing completely.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001478 */
1479static struct board_pciid_enable *board_match_pci_card_ids(void)
1480{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001481 struct board_pciid_enable *board = board_pciid_enables;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001482
Uwe Hermanna93045c2009-05-09 00:47:04 +00001483 for (; board->vendor_name; board++) {
Michael Karcher2eab70d2010-02-04 10:58:50 +00001484 if ((!board->first_card_vendor || !board->first_card_device) &&
1485 !board->dmi_pattern)
Uwe Hermanna7e05482007-05-09 10:17:44 +00001486 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001487
Uwe Hermanna7e05482007-05-09 10:17:44 +00001488 if (!pci_card_find(board->first_vendor, board->first_device,
Uwe Hermann394131e2008-10-18 21:14:13 +00001489 board->first_card_vendor,
1490 board->first_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001491 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001492
Uwe Hermanna7e05482007-05-09 10:17:44 +00001493 if (board->second_vendor) {
1494 if (board->second_card_vendor) {
1495 if (!pci_card_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00001496 board->second_device,
1497 board->second_card_vendor,
1498 board->second_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001499 continue;
1500 } else {
1501 if (!pci_dev_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00001502 board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001503 continue;
1504 }
1505 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001506
Michael Karcher6701ee82010-01-20 14:14:11 +00001507 if (board->dmi_pattern) {
1508 if (!has_dmi_support) {
1509 fprintf(stderr, "WARNING: Can't autodetect %s %s,"
1510 " DMI info unavailable.\n",
1511 board->vendor_name, board->board_name);
1512 continue;
1513 } else {
1514 if (!dmi_match(board->dmi_pattern))
1515 continue;
1516 }
1517 }
1518
Uwe Hermanna7e05482007-05-09 10:17:44 +00001519 return board;
1520 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001521
Uwe Hermanna7e05482007-05-09 10:17:44 +00001522 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001523}
1524
Uwe Hermann372eeb52007-12-04 21:49:06 +00001525int board_flash_enable(const char *vendor, const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001526{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001527 struct board_pciid_enable *board = NULL;
1528 int ret = 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001529
Peter Stuge6b53fed2008-01-27 16:21:21 +00001530 if (part)
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00001531 board = board_match_coreboot_name(vendor, part);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001532
Uwe Hermanna7e05482007-05-09 10:17:44 +00001533 if (!board)
1534 board = board_match_pci_card_ids();
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001535
Michael Karcher0b9e2a72010-03-11 23:04:16 +00001536 if (board && board->status == NT) {
Uwe Hermann43959702010-03-13 17:28:29 +00001537 if (!force_boardenable) {
Michael Karcher7f0c3ec2010-03-07 22:29:28 +00001538 printf("WARNING: Your mainboard is %s %s, but the mainboard-specific\n"
1539 "code has not been tested, and thus will not not be executed by default.\n"
1540 "Depending on your hardware environment, erasing, writing or even probing\n"
1541 "can fail without running the board specific code.\n\n"
1542 "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n"
Uwe Hermann43959702010-03-13 17:28:29 +00001543 "\"internal programmer\") for details.\n",
Michael Karcher7f0c3ec2010-03-07 22:29:28 +00001544 board->vendor_name, board->board_name);
1545 board = NULL;
Uwe Hermann43959702010-03-13 17:28:29 +00001546 } else {
Michael Karcher7f0c3ec2010-03-07 22:29:28 +00001547 printf("NOTE: Running an untested board enable procedure.\n"
Uwe Hermann43959702010-03-13 17:28:29 +00001548 "Please report success/failure to flashrom@flashrom.org.\n");
1549 }
Michael Karcher7f0c3ec2010-03-07 22:29:28 +00001550 }
1551
Uwe Hermanna7e05482007-05-09 10:17:44 +00001552 if (board) {
Luc Verhaegen93938c32010-01-20 14:45:03 +00001553 if (board->max_rom_decode_parallel)
1554 max_rom_decode.parallel =
1555 board->max_rom_decode_parallel * 1024;
1556
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00001557 if (board->enable != NULL) {
1558 printf("Disabling flash write protection for "
1559 "board \"%s %s\"... ", board->vendor_name,
1560 board->board_name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001561
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00001562 ret = board->enable(board->vendor_name);
1563 if (ret)
1564 printf("FAILED!\n");
1565 else
1566 printf("OK.\n");
1567 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00001568 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001569
Uwe Hermanna7e05482007-05-09 10:17:44 +00001570 return ret;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001571}