blob: 05d8e09466faed3a7f02b9de535b68db796790ee [file] [log] [blame]
Ollie Lho184a4042005-11-26 21:55:36 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ollie Lho184a4042005-11-26 21:55:36 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Stefan Reinauer8fa64812009-08-12 09:27:45 +00005 * Copyright (C) 2005-2009 coresystems GmbH
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +00007 * Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger
Adam Jurkowskie4984102009-12-21 15:30:46 +00008 * Copyright (C) 2009 Kontron Modular Computers GmbH
Ollie Lho184a4042005-11-26 21:55:36 +00009 *
Uwe Hermannd1107642007-08-29 17:52:32 +000010 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
Ollie Lho184a4042005-11-26 21:55:36 +000013 *
Uwe Hermannd1107642007-08-29 17:52:32 +000014 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 */
23
24/*
25 * Contains the chipset specific flash enables.
Ollie Lho184a4042005-11-26 21:55:36 +000026 */
27
Lane Brooksd54958a2007-11-13 16:45:22 +000028#define _LARGEFILE64_SOURCE
29
Ollie Lhocbbf1252004-03-17 22:22:08 +000030#include <stdlib.h>
Uwe Hermanne8ba5382009-05-22 11:37:27 +000031#include <string.h>
Lane Brooksd54958a2007-11-13 16:45:22 +000032#include <sys/types.h>
Carl-Daniel Hailfingerdcef67e2010-06-21 23:20:15 +000033#include <unistd.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000034#include "flash.h"
Carl-Daniel Hailfinger5b997c32010-07-27 22:41:39 +000035#include "programmer.h"
Stefan Reinauer86de2832006-03-31 11:26:55 +000036
Michael Karcher89bed6d2010-06-13 10:16:12 +000037#define NOT_DONE_YET 1
38
Carl-Daniel Hailfinger1d3a2fe2010-07-27 22:03:46 +000039#if defined(__i386__) || defined(__x86_64__)
40
Uwe Hermann372eeb52007-12-04 21:49:06 +000041static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
Luc Verhaegen6b141752007-05-20 16:16:13 +000042{
43 uint8_t tmp;
44
Uwe Hermann372eeb52007-12-04 21:49:06 +000045 /*
46 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
47 * 0xFFFE0000-0xFFFFFFFF ROM select enable.
48 */
Luc Verhaegen6b141752007-05-20 16:16:13 +000049 tmp = pci_read_byte(dev, 0x47);
50 tmp |= 0x46;
51 pci_write_byte(dev, 0x47, tmp);
52
53 return 0;
54}
55
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000056static int enable_flash_sis85c496(struct pci_dev *dev, const char *name)
57{
58 uint8_t tmp;
59
60 tmp = pci_read_byte(dev, 0xd0);
61 tmp |= 0xf8;
62 pci_write_byte(dev, 0xd0, tmp);
63
64 return 0;
65}
66
67static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name)
68{
69 uint8_t new, newer;
70
71 /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
72 /* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
73 new = pci_read_byte(dev, 0x40);
74 new &= (~0x04); /* No idea why we clear bit 2. */
75 new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */
76 pci_write_byte(dev, 0x40, new);
77 newer = pci_read_byte(dev, 0x40);
78 if (newer != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +000079 msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
80 msg_pinfo("Stuck at 0x%x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000081 return -1;
82 }
83 return 0;
84}
85
86static struct pci_dev *find_southbridge(uint16_t vendor, const char *name)
87{
88 struct pci_dev *sbdev;
89
90 sbdev = pci_dev_find_vendorclass(vendor, 0x0601);
91 if (!sbdev)
92 sbdev = pci_dev_find_vendorclass(vendor, 0x0680);
93 if (!sbdev)
94 sbdev = pci_dev_find_vendorclass(vendor, 0x0000);
95 if (!sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +000096 msg_perr("No southbridge found for %s!\n", name);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000097 if (sbdev)
Sean Nelson316a29f2010-05-07 20:09:04 +000098 msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n",
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000099 sbdev->vendor_id, sbdev->device_id,
100 sbdev->bus, sbdev->dev, sbdev->func);
101 return sbdev;
102}
103
104static int enable_flash_sis501(struct pci_dev *dev, const char *name)
105{
106 uint8_t tmp;
107 int ret = 0;
108 struct pci_dev *sbdev;
109
110 sbdev = find_southbridge(dev->vendor_id, name);
111 if (!sbdev)
112 return -1;
113
114 ret = enable_flash_sis_mapping(sbdev, name);
115
116 tmp = sio_read(0x22, 0x80);
117 tmp &= (~0x20);
118 tmp |= 0x4;
119 sio_write(0x22, 0x80, tmp);
120
121 tmp = sio_read(0x22, 0x70);
122 tmp &= (~0x20);
123 tmp |= 0x4;
124 sio_write(0x22, 0x70, tmp);
125
126 return ret;
127}
128
129static int enable_flash_sis5511(struct pci_dev *dev, const char *name)
130{
131 uint8_t tmp;
132 int ret = 0;
133 struct pci_dev *sbdev;
134
135 sbdev = find_southbridge(dev->vendor_id, name);
136 if (!sbdev)
137 return -1;
138
139 ret = enable_flash_sis_mapping(sbdev, name);
140
141 tmp = sio_read(0x22, 0x50);
142 tmp &= (~0x20);
143 tmp |= 0x4;
144 sio_write(0x22, 0x50, tmp);
145
146 return ret;
147}
148
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000149static int enable_flash_sis530(struct pci_dev *dev, const char *name)
150{
151 uint8_t new, newer;
152 int ret = 0;
153 struct pci_dev *sbdev;
154
155 sbdev = find_southbridge(dev->vendor_id, name);
156 if (!sbdev)
157 return -1;
158
159 ret = enable_flash_sis_mapping(sbdev, name);
160
161 new = pci_read_byte(sbdev, 0x45);
162 new &= (~0x20);
163 new |= 0x4;
164 pci_write_byte(sbdev, 0x45, new);
Luc Verhaegen9cce2f52010-01-10 15:01:08 +0000165 newer = pci_read_byte(sbdev, 0x45);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000166 if (newer != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000167 msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
168 msg_pinfo("Stuck at 0x%x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000169 ret = -1;
170 }
171
172 return ret;
173}
174
175static int enable_flash_sis540(struct pci_dev *dev, const char *name)
176{
177 uint8_t new, newer;
178 int ret = 0;
179 struct pci_dev *sbdev;
180
181 sbdev = find_southbridge(dev->vendor_id, name);
182 if (!sbdev)
183 return -1;
184
185 ret = enable_flash_sis_mapping(sbdev, name);
186
187 new = pci_read_byte(sbdev, 0x45);
188 new &= (~0x80);
189 new |= 0x40;
190 pci_write_byte(sbdev, 0x45, new);
Luc Verhaegen9cce2f52010-01-10 15:01:08 +0000191 newer = pci_read_byte(sbdev, 0x45);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000192 if (newer != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000193 msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
194 msg_pinfo("Stuck at 0x%x\n", newer);
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000195 ret = -1;
196 }
197
198 return ret;
199}
200
Uwe Hermann987942d2006-11-07 11:16:21 +0000201/* Datasheet:
202 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
203 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
204 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
205 * - Order Number: 290562-001
206 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000207static int enable_flash_piix4(struct pci_dev *dev, const char *name)
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000208{
209 uint16_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000210 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000211
Maciej Pijankaa661e152009-12-08 17:26:24 +0000212 buses_supported = CHIP_BUSTYPE_PARALLEL;
213
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000214 old = pci_read_word(dev, xbcs);
215
216 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
Uwe Hermanna7e05482007-05-09 10:17:44 +0000217 * FFF00000-FFF7FFFF are forwarded to ISA).
Uwe Hermannc556d322008-10-28 11:50:05 +0000218 * Note: This bit is reserved on PIIX/PIIX3/MPIIX.
Uwe Hermanna7e05482007-05-09 10:17:44 +0000219 * Set bit 7: Extended BIOS Enable (PCI master accesses to
220 * FFF80000-FFFDFFFF are forwarded to ISA).
221 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
222 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
223 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
224 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
225 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
226 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
227 */
Uwe Hermannc556d322008-10-28 11:50:05 +0000228 if (dev->device_id == 0x122e || dev->device_id == 0x7000
229 || dev->device_id == 0x1234)
230 new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
Uwe Hermann87203452008-10-26 18:40:42 +0000231 else
232 new = old | 0x02c4;
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000233
234 if (new == old)
235 return 0;
236
237 pci_write_word(dev, xbcs, new);
238
239 if (pci_read_word(dev, xbcs) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000240 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000241 return -1;
242 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000243
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000244 return 0;
245}
246
Uwe Hermann372eeb52007-12-04 21:49:06 +0000247/*
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000248 * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet"
249 * http://download.intel.com/design/chipsets/datashts/30701303.pdf
Uwe Hermann372eeb52007-12-04 21:49:06 +0000250 */
251static int enable_flash_ich(struct pci_dev *dev, const char *name,
252 int bios_cntl)
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000253{
Ollie Lho184a4042005-11-26 21:55:36 +0000254 uint8_t old, new;
Stefan Reinauereb366472006-09-06 15:48:48 +0000255
Uwe Hermann372eeb52007-12-04 21:49:06 +0000256 /*
257 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
Uwe Hermanna7e05482007-05-09 10:17:44 +0000258 * just treating it as 8 bit wide seems to work fine in practice.
Stefan Reinauereb366472006-09-06 15:48:48 +0000259 */
Stefan Reinauer86de2832006-03-31 11:26:55 +0000260 old = pci_read_byte(dev, bios_cntl);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000261
Sean Nelson316a29f2010-05-07 20:09:04 +0000262 msg_pdbg("\nBIOS Lock Enable: %sabled, ",
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000263 (old & (1 << 1)) ? "en" : "dis");
Sean Nelson316a29f2010-05-07 20:09:04 +0000264 msg_pdbg("BIOS Write Enable: %sabled, ",
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000265 (old & (1 << 0)) ? "en" : "dis");
Sean Nelson316a29f2010-05-07 20:09:04 +0000266 msg_pdbg("BIOS_CNTL is 0x%x\n", old);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000267
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000268 new = old | 1;
269
270 if (new == old)
271 return 0;
272
Stefan Reinauer86de2832006-03-31 11:26:55 +0000273 pci_write_byte(dev, bios_cntl, new);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000274
Stefan Reinauer86de2832006-03-31 11:26:55 +0000275 if (pci_read_byte(dev, bios_cntl) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000276 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000277 return -1;
278 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000279
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000280 return 0;
281}
282
Uwe Hermann372eeb52007-12-04 21:49:06 +0000283static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000284{
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000285 /*
286 * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and
287 * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and
288 * FB_DEC_EN2.
289 */
Carl-Daniel Hailfinger7f9922d2010-06-20 11:04:26 +0000290 buses_supported = CHIP_BUSTYPE_FWH;
Stefan Reinauereb366472006-09-06 15:48:48 +0000291 return enable_flash_ich(dev, name, 0x4e);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000292}
293
Uwe Hermann372eeb52007-12-04 21:49:06 +0000294static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000295{
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000296 uint32_t fwh_conf;
297 int i;
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000298 char *idsel = NULL;
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000299 int tmp;
300 int max_decode_fwh_idsel = 0;
301 int max_decode_fwh_decode = 0;
302 int contiguous = 1;
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000303
Carl-Daniel Hailfinger2b6dcb32010-07-08 10:13:37 +0000304 idsel = extract_programmer_param("fwh_idsel");
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000305 if (idsel && strlen(idsel)) {
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000306 fwh_conf = (uint32_t)strtoul(idsel, NULL, 0);
307
308 /* FIXME: Need to undo this on shutdown. */
Sean Nelson316a29f2010-05-07 20:09:04 +0000309 msg_pinfo("\nSetting IDSEL=0x%x for top 16 MB", fwh_conf);
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000310 pci_write_long(dev, 0xd0, fwh_conf);
311 pci_write_word(dev, 0xd4, fwh_conf);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000312 /* FIXME: Decode settings are not changed. */
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000313 } else if (idsel) {
314 msg_perr("Error: idsel= specified, but no number given.\n");
315 free(idsel);
316 /* FIXME: Return failure here once internal_init() starts
317 * to care about the return value of the chipset enable.
318 */
319 exit(1);
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000320 }
Carl-Daniel Hailfinger744132a2010-07-06 09:55:48 +0000321 free(idsel);
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000322
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000323 /* Ignore all legacy ranges below 1 MB.
324 * We currently only support flashing the chip which responds to
325 * IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations
326 * have to be adjusted.
327 */
328 /* FWH_SEL1 */
329 fwh_conf = pci_read_long(dev, 0xd0);
330 for (i = 7; i >= 0; i--) {
331 tmp = (fwh_conf >> (i * 4)) & 0xf;
Sean Nelson316a29f2010-05-07 20:09:04 +0000332 msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000333 (0x1ff8 + i) * 0x80000,
334 (0x1ff0 + i) * 0x80000,
335 tmp);
336 if ((tmp == 0) && contiguous) {
337 max_decode_fwh_idsel = (8 - i) * 0x80000;
338 } else {
339 contiguous = 0;
340 }
341 }
342 /* FWH_SEL2 */
343 fwh_conf = pci_read_word(dev, 0xd4);
344 for (i = 3; i >= 0; i--) {
345 tmp = (fwh_conf >> (i * 4)) & 0xf;
Sean Nelson316a29f2010-05-07 20:09:04 +0000346 msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000347 (0xff4 + i) * 0x100000,
348 (0xff0 + i) * 0x100000,
349 tmp);
350 if ((tmp == 0) && contiguous) {
351 max_decode_fwh_idsel = (8 - i) * 0x100000;
352 } else {
353 contiguous = 0;
354 }
355 }
356 contiguous = 1;
357 /* FWH_DEC_EN1 */
358 fwh_conf = pci_read_word(dev, 0xd8);
359 for (i = 7; i >= 0; i--) {
360 tmp = (fwh_conf >> (i + 0x8)) & 0x1;
Sean Nelson316a29f2010-05-07 20:09:04 +0000361 msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled",
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000362 (0x1ff8 + i) * 0x80000,
363 (0x1ff0 + i) * 0x80000,
364 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000365 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000366 max_decode_fwh_decode = (8 - i) * 0x80000;
367 } else {
368 contiguous = 0;
369 }
370 }
371 for (i = 3; i >= 0; i--) {
372 tmp = (fwh_conf >> i) & 0x1;
Sean Nelson316a29f2010-05-07 20:09:04 +0000373 msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled",
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000374 (0xff4 + i) * 0x100000,
375 (0xff0 + i) * 0x100000,
376 tmp ? "en" : "dis");
Michael Karcher96785392010-01-03 15:09:17 +0000377 if ((tmp == 1) && contiguous) {
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000378 max_decode_fwh_decode = (8 - i) * 0x100000;
379 } else {
380 contiguous = 0;
381 }
382 }
383 max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode);
Sean Nelson316a29f2010-05-07 20:09:04 +0000384 msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh);
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000385
386 /* If we're called by enable_flash_ich_dc_spi, it will override
387 * buses_supported anyway.
388 */
389 buses_supported = CHIP_BUSTYPE_FWH;
Stefan Reinauereb366472006-09-06 15:48:48 +0000390 return enable_flash_ich(dev, name, 0xdc);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000391}
392
Adam Jurkowskie4984102009-12-21 15:30:46 +0000393static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
394{
395 uint16_t old, new;
396 int err;
397
398 if ((err = enable_flash_ich(dev, name, 0xd8)) != 0)
399 return err;
400
401 old = pci_read_byte(dev, 0xd9);
Sean Nelson316a29f2010-05-07 20:09:04 +0000402 msg_pdbg("BIOS Prefetch Enable: %sabled, ",
Adam Jurkowskie4984102009-12-21 15:30:46 +0000403 (old & 1) ? "en" : "dis");
404 new = old & ~1;
405
406 if (new != old)
407 pci_write_byte(dev, 0xd9, new);
408
Carl-Daniel Hailfinger7f9922d2010-06-20 11:04:26 +0000409 buses_supported = CHIP_BUSTYPE_FWH;
Adam Jurkowskie4984102009-12-21 15:30:46 +0000410 return 0;
411}
412
413
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000414#define ICH_STRAP_RSVD 0x00
415#define ICH_STRAP_SPI 0x01
416#define ICH_STRAP_PCI 0x02
417#define ICH_STRAP_LPC 0x03
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000418
Uwe Hermann394131e2008-10-18 21:14:13 +0000419static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
420{
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000421 /* Do we really need no write enable? */
Michael Karchera4448d92010-07-22 18:04:15 +0000422 return via_init_spi(dev);
Joshua Roysf93b36a2010-07-01 17:45:54 +0000423}
424
Uwe Hermann394131e2008-10-18 21:14:13 +0000425static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
426 int ich_generation)
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000427{
Michael Karchera4448d92010-07-22 18:04:15 +0000428 int ret;
429 uint8_t bbs, buc;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000430 uint32_t tmp, gcs;
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000431 void *rcrb;
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000432 //TODO: These names are incorrect for EP80579. For that, the solution would look like the commented line
433 //static const char *straps_names[] = {"SPI", "reserved", "reserved", "LPC" };
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000434 static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" };
Uwe Hermann394131e2008-10-18 21:14:13 +0000435
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000436 /* Enable Flash Writes */
437 ret = enable_flash_ich_dc(dev, name);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000438
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000439 /* Get physical address of Root Complex Register Block */
440 tmp = pci_read_long(dev, 0xf0) & 0xffffc000;
Sean Nelson316a29f2010-05-07 20:09:04 +0000441 msg_pdbg("\nRoot Complex Register Block address = 0x%x\n", tmp);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000442
443 /* Map RCBA to virtual memory */
Stefan Reinauer0593f212009-01-26 01:10:48 +0000444 rcrb = physmap("ICH RCRB", tmp, 0x4000);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000445
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000446 gcs = mmio_readl(rcrb + 0x3410);
Sean Nelson316a29f2010-05-07 20:09:04 +0000447 msg_pdbg("GCS = 0x%x: ", gcs);
448 msg_pdbg("BIOS Interface Lock-Down: %sabled, ",
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000449 (gcs & 0x1) ? "en" : "dis");
450 bbs = (gcs >> 10) & 0x3;
Sean Nelson316a29f2010-05-07 20:09:04 +0000451 msg_pdbg("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000452
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000453 buc = mmio_readb(rcrb + 0x3414);
Sean Nelson316a29f2010-05-07 20:09:04 +0000454 msg_pdbg("Top Swap : %s\n",
Uwe Hermann394131e2008-10-18 21:14:13 +0000455 (buc & 1) ? "enabled (A16 inverted)" : "not enabled");
Stefan Reinauera9424d52008-06-27 16:28:34 +0000456
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000457 /* It seems the ICH7 does not support SPI and LPC chips at the same
458 * time. At least not with our current code. So we prevent searching
459 * on ICH7 when the southbridge is strapped to LPC
460 */
461
Michael Karchera4448d92010-07-22 18:04:15 +0000462 buses_supported = CHIP_BUSTYPE_FWH;
463 if (ich_generation == 7) {
464 if(bbs == ICH_STRAP_LPC) {
465 /* No further SPI initialization required */
466 return ret;
467 }
468 else
469 /* Disable LPC/FWH if strapped to PCI or SPI */
470 buses_supported = 0;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000471 }
472
Michael Karchera4448d92010-07-22 18:04:15 +0000473 /* this adds CHIP_BUSTYPE_SPI */
474 if (ich_init_spi(dev, tmp, rcrb, ich_generation) != 0) {
475 if (!ret)
476 ret = ERROR_NONFATAL;
477 }
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000478
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000479 return ret;
480}
Stefan Reinauera9424d52008-06-27 16:28:34 +0000481
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000482static int enable_flash_ich7(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000483{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000484 return enable_flash_ich_dc_spi(dev, name, 7);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000485}
486
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000487static int enable_flash_ich8(struct pci_dev *dev, const char *name)
488{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000489 return enable_flash_ich_dc_spi(dev, name, 8);
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000490}
491
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000492static int enable_flash_ich9(struct pci_dev *dev, const char *name)
493{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000494 return enable_flash_ich_dc_spi(dev, name, 9);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000495}
496
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000497static int enable_flash_ich10(struct pci_dev *dev, const char *name)
498{
499 return enable_flash_ich_dc_spi(dev, name, 10);
500}
501
Michael Karcher89bed6d2010-06-13 10:16:12 +0000502static void via_do_byte_merge(void * arg)
503{
504 struct pci_dev * dev = arg;
505 uint8_t val;
506
507 msg_pdbg("Re-enabling byte merging\n");
508 val = pci_read_byte(dev, 0x71);
509 val |= 0x40;
510 pci_write_byte(dev, 0x71, val);
511}
512
513static int via_no_byte_merge(struct pci_dev *dev, const char *name)
514{
515 uint8_t val;
516
517 val = pci_read_byte(dev, 0x71);
518 if (val & 0x40)
519 {
520 msg_pdbg("Disabling byte merging\n");
521 val &= ~0x40;
522 pci_write_byte(dev, 0x71, val);
523 register_shutdown(via_do_byte_merge, dev);
524 }
525 return NOT_DONE_YET; /* need to find south bridge, too */
526}
527
Uwe Hermann372eeb52007-12-04 21:49:06 +0000528static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000529{
Ollie Lho184a4042005-11-26 21:55:36 +0000530 uint8_t val;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000531
Uwe Hermann394131e2008-10-18 21:14:13 +0000532 /* enable ROM decode range (1MB) FFC00000 - FFFFFFFF */
Bari Ari9477c4e2008-04-29 13:46:38 +0000533 pci_write_byte(dev, 0x41, 0x7f);
534
Uwe Hermannffec5f32007-08-23 16:08:21 +0000535 /* ROM write enable */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000536 val = pci_read_byte(dev, 0x40);
537 val |= 0x10;
538 pci_write_byte(dev, 0x40, val);
539
540 if (pci_read_byte(dev, 0x40) != val) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000541 msg_pinfo("\nWARNING: Failed to enable flash write on \"%s\"\n",
Uwe Hermanna7e05482007-05-09 10:17:44 +0000542 name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000543 return -1;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000544 }
Luc Verhaegen6382b442007-03-02 22:16:38 +0000545
Luc Verhaegen73d21192009-12-23 00:54:26 +0000546 if (dev->device_id == 0x3227) { /* VT8237R */
547 /* All memory cycles, not just ROM ones, go to LPC. */
548 val = pci_read_byte(dev, 0x59);
549 val &= ~0x80;
550 pci_write_byte(dev, 0x59, val);
551 }
552
Uwe Hermanna7e05482007-05-09 10:17:44 +0000553 return 0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000554}
555
Uwe Hermann372eeb52007-12-04 21:49:06 +0000556static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000557{
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000558 uint8_t reg8;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000559
Uwe Hermann394131e2008-10-18 21:14:13 +0000560#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
561#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000562#define CS5530_RESET_CONTROL_REG 0x44 /* F0 index 0x44 */
563#define CS5530_USB_SHADOW_REG 0x43 /* F0 index 0x43 */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000564
Uwe Hermann394131e2008-10-18 21:14:13 +0000565#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
566#define ROM_WRITE_ENABLE (1 << 1)
567#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
568#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000569#define CS5530_ISA_MASTER (1 << 7)
570#define CS5530_ENABLE_SA2320 (1 << 2)
571#define CS5530_ENABLE_SA20 (1 << 6)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000572
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000573 buses_supported = CHIP_BUSTYPE_PARALLEL;
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000574 /* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
575 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000576 * FIXME: Should we really touch the low mapping below 1 MB? Flashrom
577 * ignores that region completely.
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000578 * Make the configured ROM areas writable.
579 */
580 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
581 reg8 |= LOWER_ROM_ADDRESS_RANGE;
582 reg8 |= UPPER_ROM_ADDRESS_RANGE;
583 reg8 |= ROM_WRITE_ENABLE;
584 pci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000585
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000586 /* Set positive decode on ROM. */
587 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
588 reg8 |= BIOS_ROM_POSITIVE_DECODE;
589 pci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000590
Carl-Daniel Hailfinger2a9e2452009-12-17 15:20:01 +0000591 reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG);
592 if (reg8 & CS5530_ISA_MASTER) {
593 /* We have A0-A23 available. */
594 max_rom_decode.parallel = 16 * 1024 * 1024;
595 } else {
596 reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG);
597 if (reg8 & CS5530_ENABLE_SA2320) {
598 /* We have A0-19, A20-A23 available. */
599 max_rom_decode.parallel = 16 * 1024 * 1024;
600 } else if (reg8 & CS5530_ENABLE_SA20) {
601 /* We have A0-19, A20 available. */
602 max_rom_decode.parallel = 2 * 1024 * 1024;
603 } else {
604 /* A20 and above are not active. */
605 max_rom_decode.parallel = 1024 * 1024;
606 }
607 }
608
Ollie Lhocbbf1252004-03-17 22:22:08 +0000609 return 0;
610}
611
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000612/*
Mart Raudseppe1344da2008-02-08 10:10:57 +0000613 * Geode systems write protect the BIOS via RCONFs (cache settings similar
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000614 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
Mart Raudseppe1344da2008-02-08 10:10:57 +0000615 *
616 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
617 * To enable write to NOR Boot flash for the benefit of systems that have such
618 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
Mart Raudseppe1344da2008-02-08 10:10:57 +0000619 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000620static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
Lane Brooksd54958a2007-11-13 16:45:22 +0000621{
Uwe Hermann394131e2008-10-18 21:14:13 +0000622#define MSR_RCONF_DEFAULT 0x1808
623#define MSR_NORF_CTL 0x51400018
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000624
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000625 msr_t msr;
Lane Brooksd54958a2007-11-13 16:45:22 +0000626
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000627 /* Geode only has a single core */
628 if (setup_cpu_msr(0))
Lane Brooksd54958a2007-11-13 16:45:22 +0000629 return -1;
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000630
631 msr = rdmsr(MSR_RCONF_DEFAULT);
632 if ((msr.hi >> 24) != 0x22) {
633 msr.hi &= 0xfbffffff;
634 wrmsr(MSR_RCONF_DEFAULT, msr);
Lane Brooksd54958a2007-11-13 16:45:22 +0000635 }
Mart Raudseppe1344da2008-02-08 10:10:57 +0000636
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000637 msr = rdmsr(MSR_NORF_CTL);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000638 /* Raise WE_CS3 bit. */
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000639 msr.lo |= 0x08;
640 wrmsr(MSR_NORF_CTL, msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000641
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000642 cleanup_cpu_msr();
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000643
Uwe Hermann394131e2008-10-18 21:14:13 +0000644#undef MSR_RCONF_DEFAULT
645#undef MSR_NORF_CTL
Lane Brooksd54958a2007-11-13 16:45:22 +0000646 return 0;
647}
648
Uwe Hermann372eeb52007-12-04 21:49:06 +0000649static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000650{
Ollie Lho184a4042005-11-26 21:55:36 +0000651 uint8_t new;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000652
Ollie Lhocbbf1252004-03-17 22:22:08 +0000653 pci_write_byte(dev, 0x52, 0xee);
654
655 new = pci_read_byte(dev, 0x52);
656
657 if (new != 0xee) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000658 msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000659 return -1;
660 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000661
Ollie Lhocbbf1252004-03-17 22:22:08 +0000662 return 0;
663}
664
Uwe Hermann190f8492008-10-25 18:03:50 +0000665/* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000666static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000667{
Ollie Lho184a4042005-11-26 21:55:36 +0000668 uint8_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000669
Uwe Hermann372eeb52007-12-04 21:49:06 +0000670 /* Enable decoding at 0xffb00000 to 0xffffffff. */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000671 old = pci_read_byte(dev, 0x43);
Ollie Lhod11f3612004-12-07 17:19:04 +0000672 new = old | 0xC0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000673 if (new != old) {
674 pci_write_byte(dev, 0x43, new);
675 if (pci_read_byte(dev, 0x43) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000676 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000677 }
678 }
679
Uwe Hermann190f8492008-10-25 18:03:50 +0000680 /* Enable 'ROM write' bit. */
Ollie Lho761bf1b2004-03-20 16:46:10 +0000681 old = pci_read_byte(dev, 0x40);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000682 new = old | 0x01;
683 if (new == old)
684 return 0;
685 pci_write_byte(dev, 0x40, new);
686
687 if (pci_read_byte(dev, 0x40) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000688 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000689 return -1;
690 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000691
Ollie Lhocbbf1252004-03-17 22:22:08 +0000692 return 0;
693}
694
Marc Jones3af487d2008-10-15 17:50:29 +0000695static int enable_flash_sb600(struct pci_dev *dev, const char *name)
696{
Michael Karcherb05b9e12010-07-22 18:04:19 +0000697 uint32_t prot;
Marc Jones3af487d2008-10-15 17:50:29 +0000698 uint8_t reg;
Michael Karcherb05b9e12010-07-22 18:04:19 +0000699 int ret;
Marc Jones3af487d2008-10-15 17:50:29 +0000700
Jason Wanga3f04be2008-11-28 21:36:51 +0000701 /* Clear ROM protect 0-3. */
702 for (reg = 0x50; reg < 0x60; reg += 4) {
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000703 prot = pci_read_long(dev, reg);
704 /* No protection flags for this region?*/
705 if ((prot & 0x3) == 0)
706 continue;
Sean Nelson316a29f2010-05-07 20:09:04 +0000707 msg_pinfo("SB600 %s%sprotected from %u to %u\n",
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000708 (prot & 0x1) ? "write " : "",
709 (prot & 0x2) ? "read " : "",
710 (prot & 0xfffffc00),
711 (prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
712 prot &= 0xfffffffc;
713 pci_write_byte(dev, reg, prot);
714 prot = pci_read_long(dev, reg);
Carl-Daniel Hailfinger9bb88ac2009-05-06 13:51:44 +0000715 if (prot & 0x3)
Sean Nelson316a29f2010-05-07 20:09:04 +0000716 msg_perr("SB600 %s%sunprotect failed from %u to %u\n",
Carl-Daniel Hailfinger9bb88ac2009-05-06 13:51:44 +0000717 (prot & 0x1) ? "write " : "",
718 (prot & 0x2) ? "read " : "",
719 (prot & 0xfffffc00),
720 (prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
Jason Wanga3f04be2008-11-28 21:36:51 +0000721 }
722
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000723 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH;
Michael Karcherb05b9e12010-07-22 18:04:19 +0000724
725 ret = sb600_probe_spi(dev);
Jason Wanga3f04be2008-11-28 21:36:51 +0000726
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000727 /* Read ROM strap override register. */
728 OUTB(0x8f, 0xcd6);
729 reg = INB(0xcd7);
730 reg &= 0x0e;
Sean Nelson316a29f2010-05-07 20:09:04 +0000731 msg_pdbg("ROM strap override is %sactive", (reg & 0x02) ? "" : "not ");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000732 if (reg & 0x02) {
733 switch ((reg & 0x0c) >> 2) {
734 case 0x00:
Sean Nelson316a29f2010-05-07 20:09:04 +0000735 msg_pdbg(": LPC");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000736 break;
737 case 0x01:
Sean Nelson316a29f2010-05-07 20:09:04 +0000738 msg_pdbg(": PCI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000739 break;
740 case 0x02:
Sean Nelson316a29f2010-05-07 20:09:04 +0000741 msg_pdbg(": FWH");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000742 break;
743 case 0x03:
Sean Nelson316a29f2010-05-07 20:09:04 +0000744 msg_pdbg(": SPI");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000745 break;
746 }
747 }
Sean Nelson316a29f2010-05-07 20:09:04 +0000748 msg_pdbg("\n");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000749
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000750 /* Force enable SPI ROM in SB600 PM register.
751 * If we enable SPI ROM here, we have to disable it after we leave.
Zheng Bao284a6002009-05-04 22:33:50 +0000752 * But how can we know which ROM we are going to handle? So we have
753 * to trade off. We only access LPC ROM if we boot via LPC ROM. And
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000754 * only SPI ROM if we boot via SPI ROM. If you want to access SPI on
755 * boards with LPC straps, you have to use the code below.
Zheng Bao284a6002009-05-04 22:33:50 +0000756 */
757 /*
Jason Wanga3f04be2008-11-28 21:36:51 +0000758 OUTB(0x8f, 0xcd6);
759 OUTB(0x0e, 0xcd7);
Zheng Bao284a6002009-05-04 22:33:50 +0000760 */
Marc Jones3af487d2008-10-15 17:50:29 +0000761
Michael Karcherb05b9e12010-07-22 18:04:19 +0000762 return ret;
Marc Jones3af487d2008-10-15 17:50:29 +0000763}
764
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000765static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name)
766{
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000767 uint8_t tmp;
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000768
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000769 pci_write_byte(dev, 0x92, 0);
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000770
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000771 tmp = pci_read_byte(dev, 0x6d);
772 tmp |= 0x01;
773 pci_write_byte(dev, 0x6d, tmp);
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000774
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000775 return 0;
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000776}
777
Uwe Hermann372eeb52007-12-04 21:49:06 +0000778static int enable_flash_ck804(struct pci_dev *dev, const char *name)
Yinghai Lu952dfce2005-07-06 17:13:46 +0000779{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000780 uint8_t old, new;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000781
Uwe Hermanna7e05482007-05-09 10:17:44 +0000782 old = pci_read_byte(dev, 0x88);
783 new = old | 0xc0;
784 if (new != old) {
785 pci_write_byte(dev, 0x88, new);
786 if (pci_read_byte(dev, 0x88) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000787 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000788 }
789 }
Yinghai Lu952dfce2005-07-06 17:13:46 +0000790
Uwe Hermanna7e05482007-05-09 10:17:44 +0000791 old = pci_read_byte(dev, 0x6d);
792 new = old | 0x01;
793 if (new == old)
794 return 0;
795 pci_write_byte(dev, 0x6d, new);
796
797 if (pci_read_byte(dev, 0x6d) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000798 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000799 return -1;
800 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000801
Uwe Hermanna7e05482007-05-09 10:17:44 +0000802 return 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000803}
804
Uwe Hermann372eeb52007-12-04 21:49:06 +0000805/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
806static int enable_flash_sb400(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000807{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000808 uint8_t tmp;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000809 struct pci_dev *smbusdev;
810
Uwe Hermann372eeb52007-12-04 21:49:06 +0000811 /* Look for the SMBus device. */
Carl-Daniel Hailfingerf6e3efb2009-05-06 00:35:31 +0000812 smbusdev = pci_dev_find(0x1002, 0x4372);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000813
Uwe Hermanna7e05482007-05-09 10:17:44 +0000814 if (!smbusdev) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000815 msg_perr("ERROR: SMBus device not found. Aborting.\n");
Stefan Reinauer86de2832006-03-31 11:26:55 +0000816 exit(1);
817 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000818
Uwe Hermann372eeb52007-12-04 21:49:06 +0000819 /* Enable some SMBus stuff. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000820 tmp = pci_read_byte(smbusdev, 0x79);
821 tmp |= 0x01;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000822 pci_write_byte(smbusdev, 0x79, tmp);
823
Uwe Hermann372eeb52007-12-04 21:49:06 +0000824 /* Change southbridge. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000825 tmp = pci_read_byte(dev, 0x48);
826 tmp |= 0x21;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000827 pci_write_byte(dev, 0x48, tmp);
828
Uwe Hermann372eeb52007-12-04 21:49:06 +0000829 /* Now become a bit silly. */
Andriy Gapon65c1b862008-05-22 13:22:45 +0000830 tmp = INB(0xc6f);
831 OUTB(tmp, 0xeb);
832 OUTB(tmp, 0xeb);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000833 tmp |= 0x40;
Andriy Gapon65c1b862008-05-22 13:22:45 +0000834 OUTB(tmp, 0xc6f);
835 OUTB(tmp, 0xeb);
836 OUTB(tmp, 0xeb);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000837
838 return 0;
839}
840
Uwe Hermann372eeb52007-12-04 21:49:06 +0000841static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
Yinghai Luca782972007-01-22 20:21:17 +0000842{
Michael Karcher4e2fb0e2010-01-12 23:29:26 +0000843 uint8_t old, new, val;
844 uint16_t wordval;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000845
Uwe Hermann372eeb52007-12-04 21:49:06 +0000846 /* Set the 0-16 MB enable bits. */
Michael Karcher4e2fb0e2010-01-12 23:29:26 +0000847 val = pci_read_byte(dev, 0x88);
848 val |= 0xff; /* 256K */
849 pci_write_byte(dev, 0x88, val);
850 val = pci_read_byte(dev, 0x8c);
851 val |= 0xff; /* 1M */
852 pci_write_byte(dev, 0x8c, val);
853 wordval = pci_read_word(dev, 0x90);
854 wordval |= 0x7fff; /* 16M */
855 pci_write_word(dev, 0x90, wordval);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000856
Uwe Hermanna7e05482007-05-09 10:17:44 +0000857 old = pci_read_byte(dev, 0x6d);
858 new = old | 0x01;
859 if (new == old)
860 return 0;
861 pci_write_byte(dev, 0x6d, new);
Yinghai Luca782972007-01-22 20:21:17 +0000862
Uwe Hermanna7e05482007-05-09 10:17:44 +0000863 if (pci_read_byte(dev, 0x6d) != new) {
Sean Nelson316a29f2010-05-07 20:09:04 +0000864 msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000865 return -1;
866 }
Yinghai Luca782972007-01-22 20:21:17 +0000867
868 return 0;
Yinghai Luca782972007-01-22 20:21:17 +0000869}
870
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000871/*
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000872 * The MCP6x/MCP7x code is based on cleanroom reverse engineering.
873 * It is assumed that LPC chips need the MCP55 code and SPI chips need the
874 * code provided in enable_flash_mcp6x_7x_common.
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000875 */
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000876static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000877{
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000878 int ret = 0;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000879 int want_spi = 0;
Michael Karchercfa674f2010-02-25 11:38:23 +0000880 uint8_t val;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000881
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000882 msg_pinfo("This chipset is not really supported yet. Guesswork...\n");
883
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000884 /* dev is the ISA bridge. No idea what the stuff below does. */
Michael Karchercfa674f2010-02-25 11:38:23 +0000885 val = pci_read_byte(dev, 0x8a);
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000886 msg_pdbg("ISA/LPC bridge reg 0x8a contents: 0x%02x, bit 6 is %i, bit 5 "
Michael Karchercfa674f2010-02-25 11:38:23 +0000887 "is %i\n", val, (val >> 6) & 0x1, (val >> 5) & 0x1);
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000888
Michael Karchercfa674f2010-02-25 11:38:23 +0000889 switch ((val >> 5) & 0x3) {
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000890 case 0x0:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000891 ret = enable_flash_mcp55(dev, name);
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000892 buses_supported = CHIP_BUSTYPE_LPC;
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000893 msg_pdbg("Flash bus type is LPC\n");
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000894 break;
895 case 0x2:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000896 want_spi = 1;
897 /* SPI is added in mcp6x_spi_init if it works.
898 * Do we really want to disable LPC in this case?
899 */
900 buses_supported = CHIP_BUSTYPE_NONE;
901 msg_pdbg("Flash bus type is SPI\n");
902 msg_perr("SPI on this chipset is WIP. Write is unsupported!\n");
903 programmer_may_write = 0;
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000904 break;
905 default:
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000906 /* Should not happen. */
907 buses_supported = CHIP_BUSTYPE_NONE;
908 msg_pdbg("Flash bus type is unknown (none)\n");
909 msg_pinfo("Something went wrong with bus type detection.\n");
910 goto out_msg;
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000911 break;
912 }
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000913
914 /* Force enable SPI and disable LPC? Not a good idea. */
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000915#if 0
Michael Karchercfa674f2010-02-25 11:38:23 +0000916 val |= (1 << 6);
917 val &= ~(1 << 5);
918 pci_write_byte(dev, 0x8a, val);
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000919#endif
920
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +0000921 if (mcp6x_spi_init(want_spi)) {
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000922 ret = 1;
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000923 }
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000924out_msg:
Carl-Daniel Hailfingerea3b1b42010-02-13 23:41:01 +0000925 msg_pinfo("Please send the output of \"flashrom -V\" to "
926 "flashrom@flashrom.org to help us finish support for your "
927 "chipset. Thanks.\n");
928
Carl-Daniel Hailfingerce5fad02010-02-18 12:24:38 +0000929 return ret;
930}
931
Uwe Hermann372eeb52007-12-04 21:49:06 +0000932static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000933{
Michael Karchercfa674f2010-02-25 11:38:23 +0000934 uint8_t val;
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000935
Uwe Hermanne823ee02007-06-05 15:02:18 +0000936 /* Set the 4MB enable bit. */
Michael Karchercfa674f2010-02-25 11:38:23 +0000937 val = pci_read_byte(dev, 0x41);
938 val |= 0x0e;
939 pci_write_byte(dev, 0x41, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000940
Michael Karchercfa674f2010-02-25 11:38:23 +0000941 val = pci_read_byte(dev, 0x43);
942 val |= (1 << 4);
943 pci_write_byte(dev, 0x43, val);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000944
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000945 return 0;
946}
947
Uwe Hermann48ec1b12010-08-08 17:01:18 +0000948/*
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000949 * Usually on the x86 architectures (and on other PC-like platforms like some
950 * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
951 * Elan SC520 only a small piece of the system flash is mapped there, but the
952 * complete flash is mapped somewhere below 1G. The position can be determined
953 * by the BOOTCS PAR register.
954 */
955static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
956{
957 int i, bootcs_found = 0;
958 uint32_t parx = 0;
959 void *mmcr;
960
961 /* 1. Map MMCR */
Stefan Reinauer0593f212009-01-26 01:10:48 +0000962 mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000963
964 /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for
965 * BOOTCS region (PARx[31:29] = 100b)e
966 */
967 for (i = 0x88; i <= 0xc4; i += 4) {
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000968 parx = mmio_readl(mmcr + i);
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000969 if ((parx >> 29) == 4) {
970 bootcs_found = 1;
971 break; /* BOOTCS found */
972 }
973 }
974
975 /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0]
976 * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0]
977 */
978 if (bootcs_found) {
979 if (parx & (1 << 25)) {
980 parx &= (1 << 14) - 1; /* Mask [13:0] */
981 flashbase = parx << 16;
982 } else {
983 parx &= (1 << 18) - 1; /* Mask [17:0] */
984 flashbase = parx << 12;
985 }
986 } else {
Sean Nelson316a29f2010-05-07 20:09:04 +0000987 msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n");
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000988 }
989
990 /* 4. Clean up */
Carl-Daniel Hailfingerbe726812009-08-09 12:44:08 +0000991 physunmap(mmcr, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000992 return 0;
993}
994
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000995#endif
996
Uwe Hermann4179d292009-05-08 17:50:51 +0000997/* Please keep this list alphabetically sorted by vendor/device. */
Uwe Hermann05fab752009-05-16 23:42:17 +0000998const struct penable chipset_enables[] = {
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +0000999#if defined(__i386__) || defined(__x86_64__)
Uwe Hermann4179d292009-05-08 17:50:51 +00001000 {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533},
1001 {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111},
1002 {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111},
1003 {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530},
1004 {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536},
Nils Jacobse715c7b2009-09-23 02:09:23 +00001005 {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536},
Uwe Hermann4179d292009-05-08 17:50:51 +00001006 {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520},
1007 {0x1002, 0x438D, OK, "AMD", "SB600", enable_flash_sb600},
Carl-Daniel Hailfinger174962d2009-09-01 22:13:42 +00001008 {0x1002, 0x439d, OK, "AMD", "SB700/SB710/SB750", enable_flash_sb600},
Uwe Hermann4179d292009-05-08 17:50:51 +00001009 {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100},
1010 {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400},
1011 {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000},
Carl-Daniel Hailfinger797a8342009-11-26 16:51:39 +00001012 {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_ich10},
1013 {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_ich10},
1014 {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_ich10},
Uwe Hermannb0039912009-05-07 13:24:49 +00001015 {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4},
Uwe Hermann4179d292009-05-08 17:50:51 +00001016 {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich_4e},
1017 {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich_dc},
1018 {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7},
Uwe Hermannb0039912009-05-07 13:24:49 +00001019 {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e},
Uwe Hermann4179d292009-05-08 17:50:51 +00001020 {0x8086, 0x3a18, OK, "Intel", "ICH10", enable_flash_ich10},
1021 {0x8086, 0x3a1a, OK, "Intel", "ICH10D", enable_flash_ich10},
1022 {0x8086, 0x3a14, OK, "Intel", "ICH10DO", enable_flash_ich10},
1023 {0x8086, 0x3a16, OK, "Intel", "ICH10R", enable_flash_ich10},
Uwe Hermannb0039912009-05-07 13:24:49 +00001024 {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e},
1025 {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +00001026 {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich_4e},
Uwe Hermann4179d292009-05-08 17:50:51 +00001027 {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +00001028 {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich_4e},
1029 {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich_4e},
1030 {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +00001031 {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich_dc},
1032 {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich_dc},
Uwe Hermannb0039912009-05-07 13:24:49 +00001033 {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7},
1034 {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7},
1035 {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7},
1036 {0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7},
David Hendricksdb7c1532010-01-19 02:19:27 +00001037 {0x8086, 0x27bc, OK, "Intel", "NM10", enable_flash_ich7},
Uwe Hermann4179d292009-05-08 17:50:51 +00001038 {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +00001039 {0x8086, 0x2812, OK, "Intel", "ICH8DH", enable_flash_ich8},
1040 {0x8086, 0x2814, OK, "Intel", "ICH8DO", enable_flash_ich8},
Uwe Hermann4179d292009-05-08 17:50:51 +00001041 {0x8086, 0x2810, OK, "Intel", "ICH8/ICH8R", enable_flash_ich8},
Uwe Hermannb0039912009-05-07 13:24:49 +00001042 {0x8086, 0x2815, OK, "Intel", "ICH8M", enable_flash_ich8},
Uwe Hermann4179d292009-05-08 17:50:51 +00001043 {0x8086, 0x2811, OK, "Intel", "ICH8M-E", enable_flash_ich8},
1044 {0x8086, 0x2918, OK, "Intel", "ICH9", enable_flash_ich9},
Uwe Hermannb0039912009-05-07 13:24:49 +00001045 {0x8086, 0x2912, OK, "Intel", "ICH9DH", enable_flash_ich9},
1046 {0x8086, 0x2914, OK, "Intel", "ICH9DO", enable_flash_ich9},
Uwe Hermannb0039912009-05-07 13:24:49 +00001047 {0x8086, 0x2919, OK, "Intel", "ICH9M", enable_flash_ich9},
Uwe Hermann4179d292009-05-08 17:50:51 +00001048 {0x8086, 0x2917, OK, "Intel", "ICH9M-E", enable_flash_ich9},
1049 {0x8086, 0x2916, OK, "Intel", "ICH9R", enable_flash_ich9},
Carl-Daniel Hailfinger95baaad2009-08-21 17:26:13 +00001050 {0x8086, 0x2910, OK, "Intel", "ICH9 Engineering Sample", enable_flash_ich9},
Uwe Hermann4179d292009-05-08 17:50:51 +00001051 {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4},
1052 {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4},
1053 {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4},
1054 {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4},
Adam Jurkowskie4984102009-12-21 15:30:46 +00001055 {0x8086, 0x8119, OK, "Intel", "Poulsbo", enable_flash_poulsbo},
Luc Verhaegenaad7e672009-10-06 11:32:21 +00001056 {0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2},
Uwe Hermannb0039912009-05-07 13:24:49 +00001057 {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */
1058 {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */
Luc Verhaegen90e8e612009-05-26 09:48:28 +00001059 {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2},
Michael Karcher5f31ebe2010-06-12 23:07:26 +00001060 {0x10de, 0x00e0, OK, "NVIDIA", "NForce3", enable_flash_nvidia_nforce2},
Uwe Hermanneac10162008-03-13 18:52:51 +00001061 /* Slave, should not be here, to fix known bug for A01. */
Uwe Hermannb0039912009-05-07 13:24:49 +00001062 {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804},
1063 {0x10de, 0x0260, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1064 {0x10de, 0x0261, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1065 {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1066 {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1067 {0x10de, 0x0360, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/
Carl-Daniel Hailfinger33d7b6a2010-05-22 07:27:16 +00001068 /* 10de:0361 is present in Tyan S2915 OEM systems, but not connected to
1069 * the flash chip. Instead, 10de:0364 is connected to the flash chip.
1070 * Until we have PCI device class matching or some fallback mechanism,
1071 * this is needed to get flashrom working on Tyan S2915 and maybe other
1072 * dual-MCP55 boards.
1073 */
1074#if 0
1075 {0x10de, 0x0361, NT, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1076#endif
Uwe Hermannb0039912009-05-07 13:24:49 +00001077 {0x10de, 0x0362, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1078 {0x10de, 0x0363, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1079 {0x10de, 0x0364, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1080 {0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1081 {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1082 {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */
Carl-Daniel Hailfinger2f436162010-07-28 15:08:35 +00001083 {0x10de, 0x03e0, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1084 {0x10de, 0x03e1, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1085 {0x10de, 0x03e2, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1086 {0x10de, 0x03e3, NT, "NVIDIA", "MCP61", enable_flash_mcp6x_7x},
1087 {0x10de, 0x0440, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1088 {0x10de, 0x0441, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1089 {0x10de, 0x0442, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1090 {0x10de, 0x0443, NT, "NVIDIA", "MCP65", enable_flash_mcp6x_7x},
1091 {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp6x_7x},
1092 {0x10de, 0x075c, NT, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x},
1093 {0x10de, 0x075d, NT, "NVIDIA", "MCP78S", enable_flash_mcp6x_7x},
1094 {0x10de, 0x07d7, NT, "NVIDIA", "MCP73", enable_flash_mcp6x_7x},
1095 {0x10de, 0x0aac, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1096 {0x10de, 0x0aad, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1097 {0x10de, 0x0aae, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
1098 {0x10de, 0x0aaf, NT, "NVIDIA", "MCP79", enable_flash_mcp6x_7x},
Carl-Daniel Hailfinger6a0269e2009-11-15 17:20:21 +00001099 {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496},
1100 {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501},
1101 {0x1039, 0x5511, NT, "SiS", "5511", enable_flash_sis5511},
Luc Verhaegen9cce2f52010-01-10 15:01:08 +00001102 {0x1039, 0x5596, NT, "SiS", "5596", enable_flash_sis5511},
Carl-Daniel Hailfinger6a0269e2009-11-15 17:20:21 +00001103 {0x1039, 0x5571, NT, "SiS", "5571", enable_flash_sis530},
1104 {0x1039, 0x5591, NT, "SiS", "5591/5592", enable_flash_sis530},
1105 {0x1039, 0x5597, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530},
1106 {0x1039, 0x0530, NT, "SiS", "530", enable_flash_sis530},
1107 {0x1039, 0x5600, NT, "SiS", "600", enable_flash_sis530},
1108 {0x1039, 0x0620, NT, "SiS", "620", enable_flash_sis530},
1109 {0x1039, 0x0540, NT, "SiS", "540", enable_flash_sis540},
Luc Verhaegen9892ca62009-12-09 07:43:13 +00001110 {0x1039, 0x0630, NT, "SiS", "630", enable_flash_sis540},
1111 {0x1039, 0x0635, NT, "SiS", "635", enable_flash_sis540},
1112 {0x1039, 0x0640, NT, "SiS", "640", enable_flash_sis540},
1113 {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis540},
1114 {0x1039, 0x0646, NT, "SiS", "645DX", enable_flash_sis540},
1115 {0x1039, 0x0648, NT, "SiS", "648", enable_flash_sis540},
1116 {0x1039, 0x0650, NT, "SiS", "650", enable_flash_sis540},
1117 {0x1039, 0x0651, NT, "SiS", "651", enable_flash_sis540},
1118 {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis540},
David Borgf8ef5d92010-07-31 23:16:09 +00001119 {0x1039, 0x0661, OK, "SiS", "661", enable_flash_sis540},
Luc Verhaegen9892ca62009-12-09 07:43:13 +00001120 {0x1039, 0x0730, NT, "SiS", "730", enable_flash_sis540},
1121 {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis540},
1122 {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis540},
1123 {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis540},
1124 {0x1039, 0x0745, NT, "SiS", "745", enable_flash_sis540},
1125 {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis540},
1126 {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis540},
1127 {0x1039, 0x0755, NT, "SiS", "755", enable_flash_sis540},
Michael Karcher89bed6d2010-06-13 10:16:12 +00001128 /* VIA northbridges */
1129 {0x1106, 0x0585, NT, "VIA", "VT82C585VPX", via_no_byte_merge},
1130 {0x1106, 0x0595, NT, "VIA", "VT82C595", via_no_byte_merge},
1131 {0x1106, 0x0597, NT, "VIA", "VT82C597", via_no_byte_merge},
1132 {0x1106, 0x0691, NT, "VIA", "VT82C69x", via_no_byte_merge}, /* 691, 693a, 694t, 694x checked */
1133 {0x1106, 0x0601, NT, "VIA", "VT8601/VT8601A", via_no_byte_merge},
1134 {0x1106, 0x8601, NT, "VIA", "VT8601T", via_no_byte_merge},
1135 /* VIA southbridges */
Uwe Hermann4179d292009-05-08 17:50:51 +00001136 {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x},
1137 {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x},
Mateusz Murawskie6abef02009-06-18 12:42:46 +00001138 {0x1106, 0x3074, NT, "VIA", "VT8233", enable_flash_vt823x},
Raúl Sorianocd8404d2009-12-23 21:29:18 +00001139 {0x1106, 0x3147, OK, "VIA", "VT8233A", enable_flash_vt823x},
Uwe Hermann4179d292009-05-08 17:50:51 +00001140 {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x},
1141 {0x1106, 0x3227, OK, "VIA", "VT8237", enable_flash_vt823x},
1142 {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x},
1143 {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi},
Arjan Koers8dfea832009-06-15 00:03:37 +00001144 {0x1106, 0x8353, OK, "VIA", "VX800", enable_flash_vt8237s_spi},
Uwe Hermann3e0774d2009-09-25 01:05:06 +00001145 {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111},
Uwe Hermann4179d292009-05-08 17:50:51 +00001146 {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111},
1147 {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111},
Carl-Daniel Hailfingercceafa22010-05-26 01:45:41 +00001148#endif
Uwe Hermann05fab752009-05-16 23:42:17 +00001149 {},
Ollie Lhocbbf1252004-03-17 22:22:08 +00001150};
Ollie Lho761bf1b2004-03-20 16:46:10 +00001151
Uwe Hermanna7e05482007-05-09 10:17:44 +00001152int chipset_flash_enable(void)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001153{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001154 struct pci_dev *dev = 0;
Uwe Hermann372eeb52007-12-04 21:49:06 +00001155 int ret = -2; /* Nothing! */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001156 int i;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001157
Uwe Hermann372eeb52007-12-04 21:49:06 +00001158 /* Now let's try to find the chipset we have... */
Uwe Hermann05fab752009-05-16 23:42:17 +00001159 for (i = 0; chipset_enables[i].vendor_name != NULL; i++) {
1160 dev = pci_dev_find(chipset_enables[i].vendor_id,
1161 chipset_enables[i].device_id);
Michael Karcher89bed6d2010-06-13 10:16:12 +00001162 if (!dev)
1163 continue;
1164 if (ret != -2) {
1165 msg_pinfo("WARNING: unexpected second chipset match: "
1166 "\"%s %s\"\nignoring, please report lspci and "
1167 "board URL to flashrom@flashrom.org!\n",
1168 chipset_enables[i].vendor_name,
1169 chipset_enables[i].device_name);
1170 continue;
1171 }
Sean Nelson316a29f2010-05-07 20:09:04 +00001172 msg_pinfo("Found chipset \"%s %s\", enabling flash write... ",
Uwe Hermann05fab752009-05-16 23:42:17 +00001173 chipset_enables[i].vendor_name,
1174 chipset_enables[i].device_name);
Carl-Daniel Hailfingerf469c272010-05-22 07:31:50 +00001175 msg_pdbg("chipset PCI ID is %04x:%04x, ",
1176 chipset_enables[i].vendor_id,
1177 chipset_enables[i].device_id);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001178
Uwe Hermann05fab752009-05-16 23:42:17 +00001179 ret = chipset_enables[i].doit(dev,
1180 chipset_enables[i].device_name);
Michael Karcher89bed6d2010-06-13 10:16:12 +00001181 if (ret == NOT_DONE_YET) {
1182 ret = -2;
1183 msg_pinfo("OK - searching further chips.\n");
1184 } else if (ret < 0)
Sean Nelson316a29f2010-05-07 20:09:04 +00001185 msg_pinfo("FAILED!\n");
Michael Karcher89bed6d2010-06-13 10:16:12 +00001186 else if(ret == 0)
Sean Nelson316a29f2010-05-07 20:09:04 +00001187 msg_pinfo("OK.\n");
Michael Karchera4448d92010-07-22 18:04:15 +00001188 else if(ret == ERROR_NONFATAL)
1189 msg_pinfo("PROBLEMS, continuing anyway\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00001190 }
Michael Karcher89bed6d2010-06-13 10:16:12 +00001191
Sean Nelson316a29f2010-05-07 20:09:04 +00001192 msg_pinfo("This chipset supports the following protocols: %s.\n",
Uwe Hermann9899cad2009-06-28 21:47:57 +00001193 flashbuses_to_text(buses_supported));
Uwe Hermanna7e05482007-05-09 10:17:44 +00001194
1195 return ret;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001196}