blob: 6ac829b7c14cc830e9858ae291c06df6728a3df7 [file] [log] [blame]
Ollie Lho184a4042005-11-26 21:55:36 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ollie Lho184a4042005-11-26 21:55:36 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Stefan Reinauer8fa64812009-08-12 09:27:45 +00005 * Copyright (C) 2005-2009 coresystems GmbH
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Ollie Lho184a4042005-11-26 21:55:36 +00007 *
Uwe Hermannd1107642007-08-29 17:52:32 +00008 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
Ollie Lho184a4042005-11-26 21:55:36 +000011 *
Uwe Hermannd1107642007-08-29 17:52:32 +000012 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22/*
23 * Contains the chipset specific flash enables.
Ollie Lho184a4042005-11-26 21:55:36 +000024 */
25
Lane Brooksd54958a2007-11-13 16:45:22 +000026#define _LARGEFILE64_SOURCE
27
Ollie Lhocbbf1252004-03-17 22:22:08 +000028#include <stdlib.h>
Uwe Hermanne8ba5382009-05-22 11:37:27 +000029#include <string.h>
Lane Brooksd54958a2007-11-13 16:45:22 +000030#include <sys/types.h>
31#include <sys/stat.h>
32#include <fcntl.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000033#include "flash.h"
Stefan Reinauer86de2832006-03-31 11:26:55 +000034
Stefan Reinauer9a6d1762008-12-03 21:24:40 +000035unsigned long flashbase = 0;
36
Stefan Reinauer2cb94e12008-06-30 23:45:22 +000037/**
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +000038 * flashrom defaults to Parallel/LPC/FWH flash devices. If a known host
39 * controller is found, the init routine sets the buses_supported bitfield to
40 * contain the supported buses for that controller.
Stefan Reinauer2cb94e12008-06-30 23:45:22 +000041 */
42
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +000043enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +000044
FENG yu ningc05a2952008-12-08 18:16:58 +000045extern int ichspi_lock;
46
Uwe Hermann372eeb52007-12-04 21:49:06 +000047static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
Luc Verhaegen6b141752007-05-20 16:16:13 +000048{
49 uint8_t tmp;
50
Uwe Hermann372eeb52007-12-04 21:49:06 +000051 /*
52 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
53 * 0xFFFE0000-0xFFFFFFFF ROM select enable.
54 */
Luc Verhaegen6b141752007-05-20 16:16:13 +000055 tmp = pci_read_byte(dev, 0x47);
56 tmp |= 0x46;
57 pci_write_byte(dev, 0x47, tmp);
58
59 return 0;
60}
61
Uwe Hermann372eeb52007-12-04 21:49:06 +000062static int enable_flash_sis630(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +000063{
Uwe Hermann372eeb52007-12-04 21:49:06 +000064 uint8_t b;
Ollie Lhocbbf1252004-03-17 22:22:08 +000065
Uwe Hermann372eeb52007-12-04 21:49:06 +000066 /* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
Alex Beregszaszic9fb5d92007-09-11 15:58:18 +000067 b = pci_read_byte(dev, 0x40);
68 pci_write_byte(dev, 0x40, b | 0xb);
Uwe Hermann372eeb52007-12-04 21:49:06 +000069
70 /* Flash write enable on SiS 540/630. */
Alex Beregszaszic9fb5d92007-09-11 15:58:18 +000071 b = pci_read_byte(dev, 0x45);
72 pci_write_byte(dev, 0x45, b | 0x40);
Ollie Lhocbbf1252004-03-17 22:22:08 +000073
Uwe Hermann372eeb52007-12-04 21:49:06 +000074 /* The same thing on SiS 950 Super I/O side... */
75
76 /* First probe for Super I/O on config port 0x2e. */
Andriy Gapon65c1b862008-05-22 13:22:45 +000077 OUTB(0x87, 0x2e);
78 OUTB(0x01, 0x2e);
79 OUTB(0x55, 0x2e);
80 OUTB(0x55, 0x2e);
Ollie Lhocbbf1252004-03-17 22:22:08 +000081
Andriy Gapon65c1b862008-05-22 13:22:45 +000082 if (INB(0x2f) != 0x87) {
Uwe Hermann372eeb52007-12-04 21:49:06 +000083 /* If that failed, try config port 0x4e. */
Andriy Gapon65c1b862008-05-22 13:22:45 +000084 OUTB(0x87, 0x4e);
85 OUTB(0x01, 0x4e);
86 OUTB(0x55, 0x4e);
87 OUTB(0xaa, 0x4e);
88 if (INB(0x4f) != 0x87) {
Ollie Lhocbbf1252004-03-17 22:22:08 +000089 printf("Can not access SiS 950\n");
90 return -1;
91 }
Andriy Gapon65c1b862008-05-22 13:22:45 +000092 OUTB(0x24, 0x4e);
93 b = INB(0x4f) | 0xfc;
94 OUTB(0x24, 0x4e);
95 OUTB(b, 0x4f);
96 OUTB(0x02, 0x4e);
97 OUTB(0x02, 0x4f);
Ollie Lhocbbf1252004-03-17 22:22:08 +000098 }
99
Andriy Gapon65c1b862008-05-22 13:22:45 +0000100 OUTB(0x24, 0x2e);
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000101 printf_debug("2f is %#x\n", INB(0x2f));
Andriy Gapon65c1b862008-05-22 13:22:45 +0000102 b = INB(0x2f) | 0xfc;
103 OUTB(0x24, 0x2e);
104 OUTB(b, 0x2f);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000105
Andriy Gapon65c1b862008-05-22 13:22:45 +0000106 OUTB(0x02, 0x2e);
107 OUTB(0x02, 0x2f);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000108
109 return 0;
110}
111
Uwe Hermann987942d2006-11-07 11:16:21 +0000112/* Datasheet:
113 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
114 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
115 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
116 * - Order Number: 290562-001
117 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000118static int enable_flash_piix4(struct pci_dev *dev, const char *name)
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000119{
120 uint16_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000121 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000122
123 old = pci_read_word(dev, xbcs);
124
125 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
Uwe Hermanna7e05482007-05-09 10:17:44 +0000126 * FFF00000-FFF7FFFF are forwarded to ISA).
Uwe Hermannc556d322008-10-28 11:50:05 +0000127 * Note: This bit is reserved on PIIX/PIIX3/MPIIX.
Uwe Hermanna7e05482007-05-09 10:17:44 +0000128 * Set bit 7: Extended BIOS Enable (PCI master accesses to
129 * FFF80000-FFFDFFFF are forwarded to ISA).
130 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
131 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
132 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
133 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
134 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
135 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
136 */
Uwe Hermannc556d322008-10-28 11:50:05 +0000137 if (dev->device_id == 0x122e || dev->device_id == 0x7000
138 || dev->device_id == 0x1234)
139 new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
Uwe Hermann87203452008-10-26 18:40:42 +0000140 else
141 new = old | 0x02c4;
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000142
143 if (new == old)
144 return 0;
145
146 pci_write_word(dev, xbcs, new);
147
148 if (pci_read_word(dev, xbcs) != new) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000149 printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000150 return -1;
151 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000152
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000153 return 0;
154}
155
Uwe Hermann372eeb52007-12-04 21:49:06 +0000156/*
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000157 * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet"
158 * http://download.intel.com/design/chipsets/datashts/30701303.pdf
Uwe Hermann372eeb52007-12-04 21:49:06 +0000159 */
160static int enable_flash_ich(struct pci_dev *dev, const char *name,
161 int bios_cntl)
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000162{
Ollie Lho184a4042005-11-26 21:55:36 +0000163 uint8_t old, new;
Stefan Reinauereb366472006-09-06 15:48:48 +0000164
Uwe Hermann372eeb52007-12-04 21:49:06 +0000165 /*
166 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
Uwe Hermanna7e05482007-05-09 10:17:44 +0000167 * just treating it as 8 bit wide seems to work fine in practice.
Stefan Reinauereb366472006-09-06 15:48:48 +0000168 */
Stefan Reinauer86de2832006-03-31 11:26:55 +0000169 old = pci_read_byte(dev, bios_cntl);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000170
Uwe Hermann793bdcd2008-05-22 22:47:04 +0000171 printf_debug("\nBIOS Lock Enable: %sabled, ",
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000172 (old & (1 << 1)) ? "en" : "dis");
173 printf_debug("BIOS Write Enable: %sabled, ",
174 (old & (1 << 0)) ? "en" : "dis");
175 printf_debug("BIOS_CNTL is 0x%x\n", old);
176
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000177 new = old | 1;
178
179 if (new == old)
180 return 0;
181
Stefan Reinauer86de2832006-03-31 11:26:55 +0000182 pci_write_byte(dev, bios_cntl, new);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000183
Stefan Reinauer86de2832006-03-31 11:26:55 +0000184 if (pci_read_byte(dev, bios_cntl) != new) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000185 printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000186 return -1;
187 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000188
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000189 return 0;
190}
191
Uwe Hermann372eeb52007-12-04 21:49:06 +0000192static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000193{
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000194 /*
195 * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and
196 * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and
197 * FB_DEC_EN2.
198 */
Stefan Reinauereb366472006-09-06 15:48:48 +0000199 return enable_flash_ich(dev, name, 0x4e);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000200}
201
Uwe Hermann372eeb52007-12-04 21:49:06 +0000202static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000203{
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000204 uint32_t fwh_conf;
205 int i;
206
207 /* Ignore all legacy ranges below 1 MB. */
208 /* FWH_SEL1 */
209 fwh_conf = pci_read_long(dev, 0xd0);
210 for (i = 7; i >= 0; i--)
211 printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
212 (0x1ff8 + i) * 0x80000,
213 (0x1ff0 + i) * 0x80000,
214 (fwh_conf >> (i * 4)) & 0xf);
215 /* FWH_SEL2 */
216 fwh_conf = pci_read_word(dev, 0xd4);
217 for (i = 3; i >= 0; i--)
218 printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
219 (0xff4 + i) * 0x100000,
220 (0xff0 + i) * 0x100000,
221 (fwh_conf >> (i * 4)) & 0xf);
222 /* FWH_DEC_EN1 */
223 fwh_conf = pci_read_word(dev, 0xd8);
224 for (i = 7; i >= 0; i--)
225 printf_debug("\n0x%08x/0x%08x FWH decode %sabled",
226 (0x1ff8 + i) * 0x80000,
227 (0x1ff0 + i) * 0x80000,
228 (fwh_conf >> (i + 0x8)) & 0x1 ? "en" : "dis");
229 for (i = 3; i >= 0; i--)
230 printf_debug("\n0x%08x/0x%08x FWH decode %sabled",
231 (0xff4 + i) * 0x100000,
232 (0xff0 + i) * 0x100000,
233 (fwh_conf >> i) & 0x1 ? "en" : "dis");
234
Stefan Reinauereb366472006-09-06 15:48:48 +0000235 return enable_flash_ich(dev, name, 0xdc);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000236}
237
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000238#define ICH_STRAP_RSVD 0x00
239#define ICH_STRAP_SPI 0x01
240#define ICH_STRAP_PCI 0x02
241#define ICH_STRAP_LPC 0x03
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000242
Uwe Hermann394131e2008-10-18 21:14:13 +0000243static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
244{
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000245 uint32_t mmio_base;
246
247 mmio_base = (pci_read_long(dev, 0xbc)) << 8;
248 printf_debug("MMIO base at = 0x%x\n", mmio_base);
Stefan Reinauer0593f212009-01-26 01:10:48 +0000249 spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70);
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000250
Uwe Hermann394131e2008-10-18 21:14:13 +0000251 printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000252 mmio_readw(spibar + 0x6c));
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000253
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000254 /* Not sure if it speaks all these bus protocols. */
255 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000256 spi_controller = SPI_CONTROLLER_VIA;
Rudolf Marek0c2029f2009-02-01 18:40:50 +0000257 ich_init_opcodes();
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000258
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000259 return 0;
260}
261
Uwe Hermann394131e2008-10-18 21:14:13 +0000262static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
263 int ich_generation)
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000264{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000265 int ret, i;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000266 uint8_t old, new, bbs, buc;
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000267 uint16_t spibar_offset, tmp2;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000268 uint32_t tmp, gcs;
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000269 void *rcrb;
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000270 //TODO: These names are incorrect for EP80579. For that, the solution would look like the commented line
271 //static const char *straps_names[] = {"SPI", "reserved", "reserved", "LPC" };
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000272 static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" };
Uwe Hermann394131e2008-10-18 21:14:13 +0000273
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000274 /* Enable Flash Writes */
275 ret = enable_flash_ich_dc(dev, name);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000276
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000277 /* Get physical address of Root Complex Register Block */
278 tmp = pci_read_long(dev, 0xf0) & 0xffffc000;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000279 printf_debug("\nRoot Complex Register Block address = 0x%x\n", tmp);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000280
281 /* Map RCBA to virtual memory */
Stefan Reinauer0593f212009-01-26 01:10:48 +0000282 rcrb = physmap("ICH RCRB", tmp, 0x4000);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000283
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000284 gcs = mmio_readl(rcrb + 0x3410);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000285 printf_debug("GCS = 0x%x: ", gcs);
286 printf_debug("BIOS Interface Lock-Down: %sabled, ",
287 (gcs & 0x1) ? "en" : "dis");
288 bbs = (gcs >> 10) & 0x3;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000289 printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000290
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000291 buc = mmio_readb(rcrb + 0x3414);
Uwe Hermann394131e2008-10-18 21:14:13 +0000292 printf_debug("Top Swap : %s\n",
293 (buc & 1) ? "enabled (A16 inverted)" : "not enabled");
Stefan Reinauera9424d52008-06-27 16:28:34 +0000294
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000295 /* It seems the ICH7 does not support SPI and LPC chips at the same
296 * time. At least not with our current code. So we prevent searching
297 * on ICH7 when the southbridge is strapped to LPC
298 */
299
300 if (ich_generation == 7 && bbs == ICH_STRAP_LPC) {
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000301 /* Not sure if it speaks LPC as well. */
302 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000303 /* No further SPI initialization required */
304 return ret;
305 }
306
307 switch (ich_generation) {
308 case 7:
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000309 buses_supported = CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000310 spi_controller = SPI_CONTROLLER_ICH7;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000311 spibar_offset = 0x3020;
312 break;
313 case 8:
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000314 /* Not sure if it speaks LPC as well. */
315 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000316 spi_controller = SPI_CONTROLLER_ICH9;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000317 spibar_offset = 0x3020;
318 break;
319 case 9:
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000320 case 10:
Uwe Hermann394131e2008-10-18 21:14:13 +0000321 default: /* Future version might behave the same */
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000322 /* Not sure if it speaks LPC as well. */
323 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000324 spi_controller = SPI_CONTROLLER_ICH9;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000325 spibar_offset = 0x3800;
326 break;
327 }
328
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000329 /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000330 printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000331
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000332 /* Assign Virtual Address */
Uwe Hermann394131e2008-10-18 21:14:13 +0000333 spibar = rcrb + spibar_offset;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000334
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000335 switch (spi_controller) {
336 case SPI_CONTROLLER_ICH7:
Uwe Hermann394131e2008-10-18 21:14:13 +0000337 printf_debug("0x00: 0x%04x (SPIS)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000338 mmio_readw(spibar + 0));
Uwe Hermann394131e2008-10-18 21:14:13 +0000339 printf_debug("0x02: 0x%04x (SPIC)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000340 mmio_readw(spibar + 2));
Uwe Hermann394131e2008-10-18 21:14:13 +0000341 printf_debug("0x04: 0x%08x (SPIA)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000342 mmio_readl(spibar + 4));
Uwe Hermann394131e2008-10-18 21:14:13 +0000343 for (i = 0; i < 8; i++) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000344 int offs;
345 offs = 8 + (i * 8);
Uwe Hermann394131e2008-10-18 21:14:13 +0000346 printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs,
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000347 mmio_readl(spibar + offs), i);
Uwe Hermann394131e2008-10-18 21:14:13 +0000348 printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000349 mmio_readl(spibar + offs + 4), i);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000350 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000351 printf_debug("0x50: 0x%08x (BBAR)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000352 mmio_readl(spibar + 0x50));
Uwe Hermann394131e2008-10-18 21:14:13 +0000353 printf_debug("0x54: 0x%04x (PREOP)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000354 mmio_readw(spibar + 0x54));
Uwe Hermann394131e2008-10-18 21:14:13 +0000355 printf_debug("0x56: 0x%04x (OPTYPE)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000356 mmio_readw(spibar + 0x56));
Uwe Hermann394131e2008-10-18 21:14:13 +0000357 printf_debug("0x58: 0x%08x (OPMENU)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000358 mmio_readl(spibar + 0x58));
Uwe Hermann394131e2008-10-18 21:14:13 +0000359 printf_debug("0x5c: 0x%08x (OPMENU+4)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000360 mmio_readl(spibar + 0x5c));
Uwe Hermann394131e2008-10-18 21:14:13 +0000361 for (i = 0; i < 4; i++) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000362 int offs;
363 offs = 0x60 + (i * 4);
Uwe Hermann394131e2008-10-18 21:14:13 +0000364 printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs,
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000365 mmio_readl(spibar + offs), i);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000366 }
367 printf_debug("\n");
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000368 if (mmio_readw(spibar) & (1 << 15)) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000369 printf("WARNING: SPI Configuration Lockdown activated.\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000370 ichspi_lock = 1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000371 }
FENG yu ningf041e9b2008-12-15 02:32:11 +0000372 ich_init_opcodes();
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000373 break;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000374 case SPI_CONTROLLER_ICH9:
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000375 tmp2 = mmio_readw(spibar + 4);
FENG yu ning37179b82009-01-18 06:39:32 +0000376 printf_debug("0x04: 0x%04x (HSFS)\n", tmp2);
377 printf_debug("FLOCKDN %i, ", (tmp2 >> 15 & 1));
378 printf_debug("FDV %i, ", (tmp2 >> 14) & 1);
379 printf_debug("FDOPSS %i, ", (tmp2 >> 13) & 1);
380 printf_debug("SCIP %i, ", (tmp2 >> 5) & 1);
381 printf_debug("BERASE %i, ", (tmp2 >> 3) & 3);
382 printf_debug("AEL %i, ", (tmp2 >> 2) & 1);
383 printf_debug("FCERR %i, ", (tmp2 >> 1) & 1);
384 printf_debug("FDONE %i\n", (tmp2 >> 0) & 1);
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000385
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000386 tmp = mmio_readl(spibar + 0x50);
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000387 printf_debug("0x50: 0x%08x (FRAP)\n", tmp);
388 printf_debug("BMWAG %i, ", (tmp >> 24) & 0xff);
389 printf_debug("BMRAG %i, ", (tmp >> 16) & 0xff);
390 printf_debug("BRWA %i, ", (tmp >> 8) & 0xff);
391 printf_debug("BRRA %i\n", (tmp >> 0) & 0xff);
392
393 printf_debug("0x54: 0x%08x (FREG0)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000394 mmio_readl(spibar + 0x54));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000395 printf_debug("0x58: 0x%08x (FREG1)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000396 mmio_readl(spibar + 0x58));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000397 printf_debug("0x5C: 0x%08x (FREG2)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000398 mmio_readl(spibar + 0x5C));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000399 printf_debug("0x60: 0x%08x (FREG3)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000400 mmio_readl(spibar + 0x60));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000401 printf_debug("0x64: 0x%08x (FREG4)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000402 mmio_readl(spibar + 0x64));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000403 printf_debug("0x74: 0x%08x (PR0)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000404 mmio_readl(spibar + 0x74));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000405 printf_debug("0x78: 0x%08x (PR1)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000406 mmio_readl(spibar + 0x78));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000407 printf_debug("0x7C: 0x%08x (PR2)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000408 mmio_readl(spibar + 0x7C));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000409 printf_debug("0x80: 0x%08x (PR3)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000410 mmio_readl(spibar + 0x80));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000411 printf_debug("0x84: 0x%08x (PR4)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000412 mmio_readl(spibar + 0x84));
FENG yu ning37179b82009-01-18 06:39:32 +0000413 printf_debug("0x90: 0x%08x (SSFS, SSFC)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000414 mmio_readl(spibar + 0x90));
FENG yu ning37179b82009-01-18 06:39:32 +0000415 printf_debug("0x94: 0x%04x (PREOP)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000416 mmio_readw(spibar + 0x94));
FENG yu ning37179b82009-01-18 06:39:32 +0000417 printf_debug("0x96: 0x%04x (OPTYPE)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000418 mmio_readw(spibar + 0x96));
FENG yu ning37179b82009-01-18 06:39:32 +0000419 printf_debug("0x98: 0x%08x (OPMENU)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000420 mmio_readl(spibar + 0x98));
FENG yu ning37179b82009-01-18 06:39:32 +0000421 printf_debug("0x9C: 0x%08x (OPMENU+4)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000422 mmio_readl(spibar + 0x9C));
FENG yu ning37179b82009-01-18 06:39:32 +0000423 printf_debug("0xA0: 0x%08x (BBAR)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000424 mmio_readl(spibar + 0xA0));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000425 printf_debug("0xB0: 0x%08x (FDOC)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000426 mmio_readl(spibar + 0xB0));
FENG yu ning37179b82009-01-18 06:39:32 +0000427 if (tmp2 & (1 << 15)) {
428 printf("WARNING: SPI Configuration Lockdown activated.\n");
429 ichspi_lock = 1;
430 }
Peter Stugee8a3e4c2008-12-22 14:12:08 +0000431 ich_init_opcodes();
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000432 break;
433 default:
434 /* Nothing */
435 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000436 }
437
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000438 old = pci_read_byte(dev, 0xdc);
439 printf_debug("SPI Read Configuration: ");
440 new = (old >> 2) & 0x3;
441 switch (new) {
442 case 0:
443 case 1:
444 case 2:
445 printf_debug("prefetching %sabled, caching %sabled, ",
Uwe Hermann394131e2008-10-18 21:14:13 +0000446 (new & 0x2) ? "en" : "dis",
447 (new & 0x1) ? "dis" : "en");
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000448 break;
449 default:
450 printf_debug("invalid prefetching/caching settings, ");
451 break;
452 }
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000453
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000454 return ret;
455}
Stefan Reinauera9424d52008-06-27 16:28:34 +0000456
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000457static int enable_flash_ich7(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000458{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000459 return enable_flash_ich_dc_spi(dev, name, 7);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000460}
461
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000462static int enable_flash_ich8(struct pci_dev *dev, const char *name)
463{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000464 return enable_flash_ich_dc_spi(dev, name, 8);
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000465}
466
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000467static int enable_flash_ich9(struct pci_dev *dev, const char *name)
468{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000469 return enable_flash_ich_dc_spi(dev, name, 9);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000470}
471
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000472static int enable_flash_ich10(struct pci_dev *dev, const char *name)
473{
474 return enable_flash_ich_dc_spi(dev, name, 10);
475}
476
Uwe Hermann372eeb52007-12-04 21:49:06 +0000477static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000478{
Ollie Lho184a4042005-11-26 21:55:36 +0000479 uint8_t val;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000480
Uwe Hermann394131e2008-10-18 21:14:13 +0000481 /* enable ROM decode range (1MB) FFC00000 - FFFFFFFF */
Bari Ari9477c4e2008-04-29 13:46:38 +0000482 pci_write_byte(dev, 0x41, 0x7f);
483
Uwe Hermannffec5f32007-08-23 16:08:21 +0000484 /* ROM write enable */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000485 val = pci_read_byte(dev, 0x40);
486 val |= 0x10;
487 pci_write_byte(dev, 0x40, val);
488
489 if (pci_read_byte(dev, 0x40) != val) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000490 printf("\nWARNING: Failed to enable flash write on \"%s\"\n",
Uwe Hermanna7e05482007-05-09 10:17:44 +0000491 name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000492 return -1;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000493 }
Luc Verhaegen6382b442007-03-02 22:16:38 +0000494
Uwe Hermanna7e05482007-05-09 10:17:44 +0000495 return 0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000496}
497
Uwe Hermann372eeb52007-12-04 21:49:06 +0000498static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000499{
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000500 uint8_t reg8;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000501
Uwe Hermann394131e2008-10-18 21:14:13 +0000502#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
503#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000504
Uwe Hermann394131e2008-10-18 21:14:13 +0000505#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
506#define ROM_WRITE_ENABLE (1 << 1)
507#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
508#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000509
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000510 /* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
511 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
512 * Make the configured ROM areas writable.
513 */
514 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
515 reg8 |= LOWER_ROM_ADDRESS_RANGE;
516 reg8 |= UPPER_ROM_ADDRESS_RANGE;
517 reg8 |= ROM_WRITE_ENABLE;
518 pci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000519
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000520 /* Set positive decode on ROM. */
521 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
522 reg8 |= BIOS_ROM_POSITIVE_DECODE;
523 pci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000524
Ollie Lhocbbf1252004-03-17 22:22:08 +0000525 return 0;
526}
527
Mart Raudseppe1344da2008-02-08 10:10:57 +0000528/**
529 * Geode systems write protect the BIOS via RCONFs (cache settings similar
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000530 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
Mart Raudseppe1344da2008-02-08 10:10:57 +0000531 *
532 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
533 * To enable write to NOR Boot flash for the benefit of systems that have such
534 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
Mart Raudseppe1344da2008-02-08 10:10:57 +0000535 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000536static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
Lane Brooksd54958a2007-11-13 16:45:22 +0000537{
Uwe Hermann394131e2008-10-18 21:14:13 +0000538#define MSR_RCONF_DEFAULT 0x1808
539#define MSR_NORF_CTL 0x51400018
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000540
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000541 msr_t msr;
Lane Brooksd54958a2007-11-13 16:45:22 +0000542
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000543 /* Geode only has a single core */
544 if (setup_cpu_msr(0))
Lane Brooksd54958a2007-11-13 16:45:22 +0000545 return -1;
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000546
547 msr = rdmsr(MSR_RCONF_DEFAULT);
548 if ((msr.hi >> 24) != 0x22) {
549 msr.hi &= 0xfbffffff;
550 wrmsr(MSR_RCONF_DEFAULT, msr);
Lane Brooksd54958a2007-11-13 16:45:22 +0000551 }
Mart Raudseppe1344da2008-02-08 10:10:57 +0000552
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000553 msr = rdmsr(MSR_NORF_CTL);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000554 /* Raise WE_CS3 bit. */
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000555 msr.lo |= 0x08;
556 wrmsr(MSR_NORF_CTL, msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000557
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000558 cleanup_cpu_msr();
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000559
Uwe Hermann394131e2008-10-18 21:14:13 +0000560#undef MSR_RCONF_DEFAULT
561#undef MSR_NORF_CTL
Lane Brooksd54958a2007-11-13 16:45:22 +0000562 return 0;
563}
564
Uwe Hermann372eeb52007-12-04 21:49:06 +0000565static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000566{
Ollie Lho184a4042005-11-26 21:55:36 +0000567 uint8_t new;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000568
Ollie Lhocbbf1252004-03-17 22:22:08 +0000569 pci_write_byte(dev, 0x52, 0xee);
570
571 new = pci_read_byte(dev, 0x52);
572
573 if (new != 0xee) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000574 printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000575 return -1;
576 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000577
Ollie Lhocbbf1252004-03-17 22:22:08 +0000578 return 0;
579}
580
Uwe Hermann372eeb52007-12-04 21:49:06 +0000581static int enable_flash_sis5595(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000582{
Ollie Lho184a4042005-11-26 21:55:36 +0000583 uint8_t new, newer;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000584
Ollie Lhocbbf1252004-03-17 22:22:08 +0000585 new = pci_read_byte(dev, 0x45);
586
Uwe Hermann372eeb52007-12-04 21:49:06 +0000587 new &= (~0x20); /* Clear bit 5. */
588 new |= 0x4; /* Set bit 2. */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000589
590 pci_write_byte(dev, 0x45, new);
591
592 newer = pci_read_byte(dev, 0x45);
593 if (newer != new) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000594 printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
595 printf_debug("Stuck at 0x%x\n", newer);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000596 return -1;
597 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000598
Urja Rannikkoa88daa72008-10-18 13:54:30 +0000599 /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
Uwe Hermann394131e2008-10-18 21:14:13 +0000600 new = pci_read_byte(dev, 0x40);
Urja Rannikkoa88daa72008-10-18 13:54:30 +0000601 new &= 0xFB;
602 new |= 0x3;
Uwe Hermann394131e2008-10-18 21:14:13 +0000603 pci_write_byte(dev, 0x40, new);
604 newer = pci_read_byte(dev, 0x40);
Urja Rannikkoa88daa72008-10-18 13:54:30 +0000605 if (newer != new) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000606 printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
607 printf_debug("Stuck at 0x%x\n", newer);
Urja Rannikkoa88daa72008-10-18 13:54:30 +0000608 return -1;
609 }
Ollie Lhocbbf1252004-03-17 22:22:08 +0000610 return 0;
611}
612
Uwe Hermann190f8492008-10-25 18:03:50 +0000613/* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000614static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000615{
Ollie Lho184a4042005-11-26 21:55:36 +0000616 uint8_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000617
Uwe Hermann372eeb52007-12-04 21:49:06 +0000618 /* Enable decoding at 0xffb00000 to 0xffffffff. */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000619 old = pci_read_byte(dev, 0x43);
Ollie Lhod11f3612004-12-07 17:19:04 +0000620 new = old | 0xC0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000621 if (new != old) {
622 pci_write_byte(dev, 0x43, new);
623 if (pci_read_byte(dev, 0x43) != new) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000624 printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000625 }
626 }
627
Uwe Hermann190f8492008-10-25 18:03:50 +0000628 /* Enable 'ROM write' bit. */
Ollie Lho761bf1b2004-03-20 16:46:10 +0000629 old = pci_read_byte(dev, 0x40);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000630 new = old | 0x01;
631 if (new == old)
632 return 0;
633 pci_write_byte(dev, 0x40, new);
634
635 if (pci_read_byte(dev, 0x40) != new) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000636 printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000637 return -1;
638 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000639
Ollie Lhocbbf1252004-03-17 22:22:08 +0000640 return 0;
641}
642
Marc Jones3af487d2008-10-15 17:50:29 +0000643static int enable_flash_sb600(struct pci_dev *dev, const char *name)
644{
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000645 uint32_t tmp, prot;
Marc Jones3af487d2008-10-15 17:50:29 +0000646 uint8_t reg;
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000647 struct pci_dev *smbus_dev;
648 int has_spi = 1;
Marc Jones3af487d2008-10-15 17:50:29 +0000649
Jason Wanga3f04be2008-11-28 21:36:51 +0000650 /* Clear ROM protect 0-3. */
651 for (reg = 0x50; reg < 0x60; reg += 4) {
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000652 prot = pci_read_long(dev, reg);
653 /* No protection flags for this region?*/
654 if ((prot & 0x3) == 0)
655 continue;
656 printf_debug("SB600 %s%sprotected from %u to %u\n",
657 (prot & 0x1) ? "write " : "",
658 (prot & 0x2) ? "read " : "",
659 (prot & 0xfffffc00),
660 (prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
661 prot &= 0xfffffffc;
662 pci_write_byte(dev, reg, prot);
663 prot = pci_read_long(dev, reg);
Carl-Daniel Hailfinger9bb88ac2009-05-06 13:51:44 +0000664 if (prot & 0x3)
Peter Stuge19997ae2009-05-06 15:05:39 +0000665 printf("SB600 %s%sunprotect failed from %u to %u\n",
Carl-Daniel Hailfinger9bb88ac2009-05-06 13:51:44 +0000666 (prot & 0x1) ? "write " : "",
667 (prot & 0x2) ? "read " : "",
668 (prot & 0xfffffc00),
669 (prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
Jason Wanga3f04be2008-11-28 21:36:51 +0000670 }
671
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000672 /* Read SPI_BaseAddr */
673 tmp = pci_read_long(dev, 0xa0);
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000674 tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000675 printf_debug("SPI base address is at 0x%x\n", tmp);
676
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000677 /* If the BAR has address 0, it is unlikely SPI is used. */
678 if (!tmp)
679 has_spi = 0;
680
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000681 if (has_spi) {
682 /* Physical memory has to be mapped at page (4k) boundaries. */
683 sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000,
684 0x1000);
685 /* The low bits of the SPI base address are used as offset into
686 * the mapped page.
687 */
688 sb600_spibar += tmp & 0xfff;
689
690 tmp = pci_read_long(dev, 0xa0);
691 printf_debug("AltSpiCSEnable=%i, SpiRomEnable=%i, "
692 "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1,
693 (tmp & 0x4) >> 2);
694 tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2;
695 printf_debug("PrefetchEnSPIFromIMC=%i, ", tmp);
696
697 tmp = pci_read_byte(dev, 0xbb);
698 printf_debug("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n",
699 tmp & 0x1, (tmp & 0x20) >> 5);
700 tmp = mmio_readl(sb600_spibar);
701 printf_debug("SpiArbEnable=%i, SpiAccessMacRomEn=%i, "
702 "SpiHostAccessRomEn=%i, ArbWaitCount=%i, "
703 "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n",
704 (tmp >> 19) & 0x1, (tmp >> 22) & 0x1,
705 (tmp >> 23) & 0x1, (tmp >> 24) & 0x7,
706 (tmp >> 27) & 0x1, (tmp >> 28) & 0x1);
707 }
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000708
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000709 /* Look for the SMBus device. */
710 smbus_dev = pci_dev_find(0x1002, 0x4385);
711
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000712 if (has_spi && !smbus_dev) {
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000713 fprintf(stderr, "ERROR: SMBus device not found. Not enabling SPI.\n");
714 has_spi = 0;
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000715 }
716 if (has_spi) {
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000717 /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */
718 /* GPIO11/SPI_DO and GPIO12/SPI_DI status */
719 reg = pci_read_byte(smbus_dev, 0xAB);
720 reg &= 0xC0;
721 printf_debug("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO");
722 printf_debug("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI");
723 if (reg != 0x00)
724 has_spi = 0;
725 /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */
726 reg = pci_read_byte(smbus_dev, 0x83);
727 reg &= 0xC0;
728 printf_debug("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD");
729 printf_debug("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000730 /* SPI_HOLD is not used on all boards, filter it out. */
731 if ((reg & 0x80) != 0x00)
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000732 has_spi = 0;
733 /* GPIO47/SPI_CLK status */
734 reg = pci_read_byte(smbus_dev, 0xA7);
735 reg &= 0x40;
736 printf_debug("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK");
737 if (reg != 0x00)
738 has_spi = 0;
739 }
740
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000741 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH;
742 if (has_spi) {
743 buses_supported |= CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000744 spi_controller = SPI_CONTROLLER_SB600;
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000745 }
Jason Wanga3f04be2008-11-28 21:36:51 +0000746
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000747 /* Read ROM strap override register. */
748 OUTB(0x8f, 0xcd6);
749 reg = INB(0xcd7);
750 reg &= 0x0e;
751 printf_debug("ROM strap override is %sactive", (reg & 0x02) ? "" : "not ");
752 if (reg & 0x02) {
753 switch ((reg & 0x0c) >> 2) {
754 case 0x00:
755 printf_debug(": LPC");
756 break;
757 case 0x01:
758 printf_debug(": PCI");
759 break;
760 case 0x02:
761 printf_debug(": FWH");
762 break;
763 case 0x03:
764 printf_debug(": SPI");
765 break;
766 }
767 }
768 printf_debug("\n");
769
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000770 /* Force enable SPI ROM in SB600 PM register.
771 * If we enable SPI ROM here, we have to disable it after we leave.
Zheng Bao284a6002009-05-04 22:33:50 +0000772 * But how can we know which ROM we are going to handle? So we have
773 * to trade off. We only access LPC ROM if we boot via LPC ROM. And
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000774 * only SPI ROM if we boot via SPI ROM. If you want to access SPI on
775 * boards with LPC straps, you have to use the code below.
Zheng Bao284a6002009-05-04 22:33:50 +0000776 */
777 /*
Jason Wanga3f04be2008-11-28 21:36:51 +0000778 OUTB(0x8f, 0xcd6);
779 OUTB(0x0e, 0xcd7);
Zheng Bao284a6002009-05-04 22:33:50 +0000780 */
Marc Jones3af487d2008-10-15 17:50:29 +0000781
782 return 0;
783}
784
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000785static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name)
786{
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000787 uint8_t tmp;
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000788
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000789 pci_write_byte(dev, 0x92, 0);
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000790
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000791 tmp = pci_read_byte(dev, 0x6d);
792 tmp |= 0x01;
793 pci_write_byte(dev, 0x6d, tmp);
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000794
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000795 return 0;
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000796}
797
Uwe Hermann372eeb52007-12-04 21:49:06 +0000798static int enable_flash_ck804(struct pci_dev *dev, const char *name)
Yinghai Lu952dfce2005-07-06 17:13:46 +0000799{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000800 uint8_t old, new;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000801
Uwe Hermanna7e05482007-05-09 10:17:44 +0000802 old = pci_read_byte(dev, 0x88);
803 new = old | 0xc0;
804 if (new != old) {
805 pci_write_byte(dev, 0x88, new);
806 if (pci_read_byte(dev, 0x88) != new) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000807 printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000808 }
809 }
Yinghai Lu952dfce2005-07-06 17:13:46 +0000810
Uwe Hermanna7e05482007-05-09 10:17:44 +0000811 old = pci_read_byte(dev, 0x6d);
812 new = old | 0x01;
813 if (new == old)
814 return 0;
815 pci_write_byte(dev, 0x6d, new);
816
817 if (pci_read_byte(dev, 0x6d) != new) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000818 printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000819 return -1;
820 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000821
Uwe Hermanna7e05482007-05-09 10:17:44 +0000822 return 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000823}
824
Uwe Hermann372eeb52007-12-04 21:49:06 +0000825/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
826static int enable_flash_sb400(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000827{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000828 uint8_t tmp;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000829 struct pci_dev *smbusdev;
830
Uwe Hermann372eeb52007-12-04 21:49:06 +0000831 /* Look for the SMBus device. */
Carl-Daniel Hailfingerf6e3efb2009-05-06 00:35:31 +0000832 smbusdev = pci_dev_find(0x1002, 0x4372);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000833
Uwe Hermanna7e05482007-05-09 10:17:44 +0000834 if (!smbusdev) {
Uwe Hermann372eeb52007-12-04 21:49:06 +0000835 fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n");
Stefan Reinauer86de2832006-03-31 11:26:55 +0000836 exit(1);
837 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000838
Uwe Hermann372eeb52007-12-04 21:49:06 +0000839 /* Enable some SMBus stuff. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000840 tmp = pci_read_byte(smbusdev, 0x79);
841 tmp |= 0x01;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000842 pci_write_byte(smbusdev, 0x79, tmp);
843
Uwe Hermann372eeb52007-12-04 21:49:06 +0000844 /* Change southbridge. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000845 tmp = pci_read_byte(dev, 0x48);
846 tmp |= 0x21;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000847 pci_write_byte(dev, 0x48, tmp);
848
Uwe Hermann372eeb52007-12-04 21:49:06 +0000849 /* Now become a bit silly. */
Andriy Gapon65c1b862008-05-22 13:22:45 +0000850 tmp = INB(0xc6f);
851 OUTB(tmp, 0xeb);
852 OUTB(tmp, 0xeb);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000853 tmp |= 0x40;
Andriy Gapon65c1b862008-05-22 13:22:45 +0000854 OUTB(tmp, 0xc6f);
855 OUTB(tmp, 0xeb);
856 OUTB(tmp, 0xeb);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000857
858 return 0;
859}
860
Uwe Hermann372eeb52007-12-04 21:49:06 +0000861static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
Yinghai Luca782972007-01-22 20:21:17 +0000862{
Uwe Hermann372eeb52007-12-04 21:49:06 +0000863 uint8_t old, new, byte;
864 uint16_t word;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000865
Uwe Hermann372eeb52007-12-04 21:49:06 +0000866 /* Set the 0-16 MB enable bits. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000867 byte = pci_read_byte(dev, 0x88);
868 byte |= 0xff; /* 256K */
869 pci_write_byte(dev, 0x88, byte);
870 byte = pci_read_byte(dev, 0x8c);
871 byte |= 0xff; /* 1M */
872 pci_write_byte(dev, 0x8c, byte);
873 word = pci_read_word(dev, 0x90);
Carl-Daniel Hailfingerdca0ab12007-10-17 22:30:07 +0000874 word |= 0x7fff; /* 16M */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000875 pci_write_word(dev, 0x90, word);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000876
Uwe Hermanna7e05482007-05-09 10:17:44 +0000877 old = pci_read_byte(dev, 0x6d);
878 new = old | 0x01;
879 if (new == old)
880 return 0;
881 pci_write_byte(dev, 0x6d, new);
Yinghai Luca782972007-01-22 20:21:17 +0000882
Uwe Hermanna7e05482007-05-09 10:17:44 +0000883 if (pci_read_byte(dev, 0x6d) != new) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000884 printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000885 return -1;
886 }
Yinghai Luca782972007-01-22 20:21:17 +0000887
888 return 0;
Yinghai Luca782972007-01-22 20:21:17 +0000889}
890
Uwe Hermann372eeb52007-12-04 21:49:06 +0000891static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000892{
Uwe Hermanne823ee02007-06-05 15:02:18 +0000893 uint8_t byte;
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000894
Uwe Hermanne823ee02007-06-05 15:02:18 +0000895 /* Set the 4MB enable bit. */
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000896 byte = pci_read_byte(dev, 0x41);
897 byte |= 0x0e;
898 pci_write_byte(dev, 0x41, byte);
899
900 byte = pci_read_byte(dev, 0x43);
Uwe Hermannffec5f32007-08-23 16:08:21 +0000901 byte |= (1 << 4);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000902 pci_write_byte(dev, 0x43, byte);
903
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000904 return 0;
905}
906
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000907/**
908 * Usually on the x86 architectures (and on other PC-like platforms like some
909 * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
910 * Elan SC520 only a small piece of the system flash is mapped there, but the
911 * complete flash is mapped somewhere below 1G. The position can be determined
912 * by the BOOTCS PAR register.
913 */
914static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
915{
916 int i, bootcs_found = 0;
917 uint32_t parx = 0;
918 void *mmcr;
919
920 /* 1. Map MMCR */
Stefan Reinauer0593f212009-01-26 01:10:48 +0000921 mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000922
923 /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for
924 * BOOTCS region (PARx[31:29] = 100b)e
925 */
926 for (i = 0x88; i <= 0xc4; i += 4) {
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000927 parx = mmio_readl(mmcr + i);
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000928 if ((parx >> 29) == 4) {
929 bootcs_found = 1;
930 break; /* BOOTCS found */
931 }
932 }
933
934 /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0]
935 * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0]
936 */
937 if (bootcs_found) {
938 if (parx & (1 << 25)) {
939 parx &= (1 << 14) - 1; /* Mask [13:0] */
940 flashbase = parx << 16;
941 } else {
942 parx &= (1 << 18) - 1; /* Mask [17:0] */
943 flashbase = parx << 12;
944 }
945 } else {
946 printf("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n");
947 }
948
949 /* 4. Clean up */
Carl-Daniel Hailfingerbe726812009-08-09 12:44:08 +0000950 physunmap(mmcr, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000951 return 0;
952}
953
Uwe Hermann4179d292009-05-08 17:50:51 +0000954/* Please keep this list alphabetically sorted by vendor/device. */
Uwe Hermann05fab752009-05-16 23:42:17 +0000955const struct penable chipset_enables[] = {
Uwe Hermann4179d292009-05-08 17:50:51 +0000956 {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533},
957 {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111},
958 {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111},
959 {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530},
960 {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536},
961 {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520},
962 {0x1002, 0x438D, OK, "AMD", "SB600", enable_flash_sb600},
963 {0x1002, 0x439d, OK, "AMD", "SB700", enable_flash_sb600},
964 {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100},
965 {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400},
966 {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000},
Uwe Hermannb0039912009-05-07 13:24:49 +0000967 {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4},
Uwe Hermann4179d292009-05-08 17:50:51 +0000968 {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich_4e},
969 {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich_dc},
970 {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7},
Uwe Hermannb0039912009-05-07 13:24:49 +0000971 {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e},
Uwe Hermann4179d292009-05-08 17:50:51 +0000972 {0x8086, 0x3a18, OK, "Intel", "ICH10", enable_flash_ich10},
973 {0x8086, 0x3a1a, OK, "Intel", "ICH10D", enable_flash_ich10},
974 {0x8086, 0x3a14, OK, "Intel", "ICH10DO", enable_flash_ich10},
975 {0x8086, 0x3a16, OK, "Intel", "ICH10R", enable_flash_ich10},
Uwe Hermannb0039912009-05-07 13:24:49 +0000976 {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e},
977 {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +0000978 {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich_4e},
Uwe Hermann4179d292009-05-08 17:50:51 +0000979 {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +0000980 {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich_4e},
981 {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich_4e},
982 {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +0000983 {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich_dc},
984 {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich_dc},
Uwe Hermannb0039912009-05-07 13:24:49 +0000985 {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7},
986 {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7},
987 {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7},
988 {0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7},
Uwe Hermann4179d292009-05-08 17:50:51 +0000989 {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +0000990 {0x8086, 0x2812, OK, "Intel", "ICH8DH", enable_flash_ich8},
991 {0x8086, 0x2814, OK, "Intel", "ICH8DO", enable_flash_ich8},
Uwe Hermann4179d292009-05-08 17:50:51 +0000992 {0x8086, 0x2810, OK, "Intel", "ICH8/ICH8R", enable_flash_ich8},
Uwe Hermannb0039912009-05-07 13:24:49 +0000993 {0x8086, 0x2815, OK, "Intel", "ICH8M", enable_flash_ich8},
Uwe Hermann4179d292009-05-08 17:50:51 +0000994 {0x8086, 0x2811, OK, "Intel", "ICH8M-E", enable_flash_ich8},
995 {0x8086, 0x2918, OK, "Intel", "ICH9", enable_flash_ich9},
Uwe Hermannb0039912009-05-07 13:24:49 +0000996 {0x8086, 0x2912, OK, "Intel", "ICH9DH", enable_flash_ich9},
997 {0x8086, 0x2914, OK, "Intel", "ICH9DO", enable_flash_ich9},
Uwe Hermannb0039912009-05-07 13:24:49 +0000998 {0x8086, 0x2919, OK, "Intel", "ICH9M", enable_flash_ich9},
Uwe Hermann4179d292009-05-08 17:50:51 +0000999 {0x8086, 0x2917, OK, "Intel", "ICH9M-E", enable_flash_ich9},
1000 {0x8086, 0x2916, OK, "Intel", "ICH9R", enable_flash_ich9},
1001 {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4},
1002 {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4},
1003 {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4},
1004 {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4},
Uwe Hermannb0039912009-05-07 13:24:49 +00001005 {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */
1006 {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */
Luc Verhaegen90e8e612009-05-26 09:48:28 +00001007 {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2},
Uwe Hermanneac10162008-03-13 18:52:51 +00001008 /* Slave, should not be here, to fix known bug for A01. */
Uwe Hermannb0039912009-05-07 13:24:49 +00001009 {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804},
1010 {0x10de, 0x0260, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1011 {0x10de, 0x0261, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1012 {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1013 {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1014 {0x10de, 0x0360, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/
1015 {0x10de, 0x0361, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1016 {0x10de, 0x0362, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1017 {0x10de, 0x0363, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1018 {0x10de, 0x0364, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1019 {0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1020 {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1021 {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */
1022 {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp55},
Uwe Hermann4179d292009-05-08 17:50:51 +00001023 {0x1039, 0x0008, OK, "SiS", "SiS5595", enable_flash_sis5595},
1024 {0x1039, 0x0630, NT, "SiS", "SiS630", enable_flash_sis630},
1025 {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x},
1026 {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x},
Mateusz Murawskie6abef02009-06-18 12:42:46 +00001027 {0x1106, 0x3074, NT, "VIA", "VT8233", enable_flash_vt823x},
Uwe Hermann4179d292009-05-08 17:50:51 +00001028 {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x},
1029 {0x1106, 0x3227, OK, "VIA", "VT8237", enable_flash_vt823x},
1030 {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x},
1031 {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi},
Arjan Koers8dfea832009-06-15 00:03:37 +00001032 {0x1106, 0x8353, OK, "VIA", "VX800", enable_flash_vt8237s_spi},
Uwe Hermann4179d292009-05-08 17:50:51 +00001033 {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111},
1034 {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111},
Uwe Hermann05fab752009-05-16 23:42:17 +00001035
1036 {},
Ollie Lhocbbf1252004-03-17 22:22:08 +00001037};
Ollie Lho761bf1b2004-03-20 16:46:10 +00001038
Uwe Hermanna7e05482007-05-09 10:17:44 +00001039int chipset_flash_enable(void)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001040{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001041 struct pci_dev *dev = 0;
Uwe Hermann372eeb52007-12-04 21:49:06 +00001042 int ret = -2; /* Nothing! */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001043 int i;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001044
Uwe Hermann372eeb52007-12-04 21:49:06 +00001045 /* Now let's try to find the chipset we have... */
Uwe Hermann05fab752009-05-16 23:42:17 +00001046 for (i = 0; chipset_enables[i].vendor_name != NULL; i++) {
1047 dev = pci_dev_find(chipset_enables[i].vendor_id,
1048 chipset_enables[i].device_id);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001049 if (dev)
1050 break;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001051 }
1052
Uwe Hermanna7e05482007-05-09 10:17:44 +00001053 if (dev) {
Uwe Hermannb0039912009-05-07 13:24:49 +00001054 printf("Found chipset \"%s %s\", enabling flash write... ",
Uwe Hermann05fab752009-05-16 23:42:17 +00001055 chipset_enables[i].vendor_name,
1056 chipset_enables[i].device_name);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001057
Uwe Hermann05fab752009-05-16 23:42:17 +00001058 ret = chipset_enables[i].doit(dev,
1059 chipset_enables[i].device_name);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001060 if (ret)
Uwe Hermanna502dce2007-10-17 23:55:15 +00001061 printf("FAILED!\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00001062 else
Uwe Hermannac309342007-10-10 17:42:20 +00001063 printf("OK.\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00001064 }
Uwe Hermann1432a602009-06-28 23:26:37 +00001065 printf("This chipset supports the following protocols: %s.\n",
Uwe Hermann9899cad2009-06-28 21:47:57 +00001066 flashbuses_to_text(buses_supported));
Uwe Hermanna7e05482007-05-09 10:17:44 +00001067
1068 return ret;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001069}