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review.sourcearcade.org / libgfxinit / 247adf39f6172aace09aef819c245d92263a86f4 / . / common / hw-gfx-gma-registers.ads
blob: 70c27ccf2d308e1546223516b1fb9673daefc49c [file] [log] [blame]
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1--
2-- Copyright (C) 2015-2016 secunet Security Networks AG
3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +0200[diff] [blame]6-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]8--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
15with System;
16with HW.GFX.GMA;
17with HW.GFX.GMA.Config;
18
19private package HW.GFX.GMA.Registers
20with
21 Abstract_State =>
22 ((Address_State with Part_Of => GMA.State),
23 (Register_State with External, Part_Of => GMA.Device_State),
24 (GTT_State with External, Part_Of => GMA.Device_State)),
25 Initializes => Address_State
26is
27 type Registers_Invalid_Index is
28 (Invalid_Register, -- Allow a placeholder when access is not acceptable
29
30 RCS_RING_BUFFER_TAIL,
31 RCS_RING_BUFFER_HEAD,
32 RCS_RING_BUFFER_STRT,
33 RCS_RING_BUFFER_CTL,
34 QUIRK_02084,
35 QUIRK_02090,
36 HWSTAM,
37 MI_MODE,
38 INSTPM,
39 GT_MODE,
40 CACHE_MODE_0,
41 CTX_SIZE,
42 PP_DCLV_HIGH,
43 PP_DCLV_LOW,
44 GFX_MODE,
45 ARB_MODE,
46 HWS_PGA,
47 GAM_ECOCHK,
48 MBCTL,
49 UCGCTL1,
50 UCGCTL2,
51 VCS_RING_BUFFER_TAIL,
52 VCS_RING_BUFFER_HEAD,
53 VCS_RING_BUFFER_STRT,
54 VCS_RING_BUFFER_CTL,
55 SLEEP_PSMI_CONTROL,
56 VCS_HWSTAM,
57 VCS_PP_DCLV_HIGH,
58 VCS_PP_DCLV_LOW,
59 GAC_ECO_BITS,
60 BCS_RING_BUFFER_TAIL,
61 BCS_RING_BUFFER_HEAD,
62 BCS_RING_BUFFER_STRT,
63 BCS_RING_BUFFER_CTL,
64 BCS_HWSTAM,
65 BCS_PP_DCLV_HIGH,
66 BCS_PP_DCLV_LOW,
67 GAB_CTL_REG,
68 VGACNTRL,
69 FUSE_STATUS,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]70 ILK_DISPLAY_CHICKEN2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]71 DSPCLK_GATE_D,
72 FBA_CFB_BASE,
73 FBC_CTL,
74 IPS_CTL,
75 DEISR,
76 DEIMR,
77 DEIIR,
78 DEIER,
79 GTISR,
80 GTIMR,
81 GTIIR,
82 GTIER,
83 IIR,
84 HOTPLUG_CTL,
85 ARB_CTL,
86 DBUF_CTL,
87 WM_PIPE_A,
88 WM_PIPE_B,
89 WM1_LP_ILK,
90 WM2_LP_ILK,
91 WM3_LP_ILK,
92 WM_PIPE_C,
93 WM_LINETIME_A,
94 WM_LINETIME_B,
95 WM_LINETIME_C,
96 PWR_WELL_CTL_BIOS,
97 PWR_WELL_CTL_DRIVER,
98 PWR_WELL_CTL_KVMR,
99 PWR_WELL_CTL_DEBUG,
100 PWR_WELL_CTL5,
101 PWR_WELL_CTL6,
102 CDCLK_CTL,
103 LCPLL1_CTL,
104 LCPLL2_CTL,
105 SPLL_CTL,
106 WRPLL_CTL_1,
107 WRPLL_CTL_2,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]108 BXT_DE_PLL_ENABLE,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]109 BXT_PORT_PLL_ENABLE_A,
110 BXT_PORT_PLL_ENABLE_B,
111 BXT_PORT_PLL_ENABLE_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]112 PORT_CLK_SEL_DDIA,
113 PORT_CLK_SEL_DDIB,
114 PORT_CLK_SEL_DDIC,
115 PORT_CLK_SEL_DDID,
116 PORT_CLK_SEL_DDIE,
117 TRANSA_CLK_SEL,
118 TRANSB_CLK_SEL,
119 TRANSC_CLK_SEL,
120 NDE_RSTWRN_OPT,
121 BLC_PWM_CPU_CTL2,
122 BLC_PWM_CPU_CTL,
123 HTOTAL_A,
124 HBLANK_A,
125 HSYNC_A,
126 VTOTAL_A,
127 VBLANK_A,
128 VSYNC_A,
129 PIPEASRC,
130 PIPE_VSYNCSHIFT_A,
131 PIPEA_DATA_M1,
132 PIPEA_DATA_N1,
133 PIPEA_LINK_M1,
134 PIPEA_LINK_N1,
135 FDI_TX_CTL_A,
136 PIPEA_DDI_FUNC_CTL,
137 PIPEA_MSA_MISC,
138 SRD_CTL_A,
139 SRD_STATUS_A,
140 HTOTAL_B,
141 HBLANK_B,
142 HSYNC_B,
143 VTOTAL_B,
144 VBLANK_B,
145 VSYNC_B,
146 PIPEBSRC,
147 PIPE_VSYNCSHIFT_B,
148 PIPEB_DATA_M1,
149 PIPEB_DATA_N1,
150 PIPEB_LINK_M1,
151 PIPEB_LINK_N1,
152 FDI_TX_CTL_B,
153 PIPEB_DDI_FUNC_CTL,
154 PIPEB_MSA_MISC,
155 SRD_CTL_B,
156 SRD_STATUS_B,
157 HTOTAL_C,
158 HBLANK_C,
159 HSYNC_C,
160 VTOTAL_C,
161 VBLANK_C,
162 VSYNC_C,
163 PIPECSRC,
164 PIPE_VSYNCSHIFT_C,
165 PIPEC_DATA_M1,
166 PIPEC_DATA_N1,
167 PIPEC_LINK_M1,
168 PIPEC_LINK_N1,
169 FDI_TX_CTL_C,
170 PIPEC_DDI_FUNC_CTL,
171 PIPEC_MSA_MISC,
172 SRD_CTL_C,
173 SRD_STATUS_C,
174 DDI_BUF_CTL_A,
175 DDI_AUX_CTL_A,
176 DDI_AUX_DATA_A_1,
177 DDI_AUX_DATA_A_2,
178 DDI_AUX_DATA_A_3,
179 DDI_AUX_DATA_A_4,
180 DDI_AUX_DATA_A_5,
181 DDI_AUX_MUTEX_A,
182 DP_TP_CTL_A,
183 DDI_BUF_CTL_B,
184 DDI_AUX_CTL_B,
185 DDI_AUX_DATA_B_1,
186 DDI_AUX_DATA_B_2,
187 DDI_AUX_DATA_B_3,
188 DDI_AUX_DATA_B_4,
189 DDI_AUX_DATA_B_5,
190 DDI_AUX_MUTEX_B,
191 DP_TP_CTL_B,
192 DP_TP_STATUS_B,
193 DDI_BUF_CTL_C,
194 DDI_AUX_CTL_C,
195 DDI_AUX_DATA_C_1,
196 DDI_AUX_DATA_C_2,
197 DDI_AUX_DATA_C_3,
198 DDI_AUX_DATA_C_4,
199 DDI_AUX_DATA_C_5,
200 DDI_AUX_MUTEX_C,
201 DP_TP_CTL_C,
202 DP_TP_STATUS_C,
203 DDI_BUF_CTL_D,
204 DDI_AUX_CTL_D,
205 DDI_AUX_DATA_D_1,
206 DDI_AUX_DATA_D_2,
207 DDI_AUX_DATA_D_3,
208 DDI_AUX_DATA_D_4,
209 DDI_AUX_DATA_D_5,
210 DDI_AUX_MUTEX_D,
211 DP_TP_CTL_D,
212 DP_TP_STATUS_D,
213 DDI_BUF_CTL_E,
214 DP_TP_CTL_E,
215 DP_TP_STATUS_E,
216 SRD_CTL,
217 SRD_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]218 BXT_PHY_CTL_A,
219 BXT_PHY_CTL_B,
220 BXT_PHY_CTL_C,
221 BXT_PHY_CTL_FAM_EDP,
222 BXT_PHY_CTL_FAM_DDI,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]223 AUD_VID_DID,
224 PFA_WIN_POS,
225 PFA_WIN_SZ,
226 PFA_CTL_1,
227 PS_WIN_POS_1_A,
228 PS_WIN_SZ_1_A,
229 PS_CTRL_1_A,
230 PS_WIN_POS_2_A,
231 PS_WIN_SZ_2_A,
232 PS_CTRL_2_A,
233 PFB_WIN_POS,
234 PFB_WIN_SZ,
235 PFB_CTL_1,
236 PS_WIN_POS_1_B,
237 PS_WIN_SZ_1_B,
238 PS_CTRL_1_B,
239 PS_WIN_POS_2_B,
240 PS_WIN_SZ_2_B,
241 PS_CTRL_2_B,
242 PFC_WIN_POS,
243 PFC_WIN_SZ,
244 PFC_CTL_1,
245 PS_WIN_POS_1_C,
246 PS_WIN_SZ_1_C,
247 PS_CTRL_1_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]248 BXT_PORT_CL1CM_DW0_BC,
249 BXT_PORT_CL1CM_DW9_BC,
250 BXT_PORT_CL1CM_DW10_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]251 BXT_PORT_PLL_EBB_0_B,
252 BXT_PORT_PLL_EBB_4_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]253 DPLL1_CFGR1,
254 DPLL1_CFGR2,
255 DPLL2_CFGR1,
256 DPLL2_CFGR2,
257 DPLL3_CFGR1,
258 DPLL3_CFGR2,
259 DPLL_CTRL1,
260 DPLL_CTRL2,
261 DPLL_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]262 BXT_PORT_CL1CM_DW28_BC,
263 BXT_PORT_CL1CM_DW30_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]264 BXT_PORT_PLL_0_B,
265 BXT_PORT_PLL_1_B,
266 BXT_PORT_PLL_2_B,
267 BXT_PORT_PLL_3_B,
268 BXT_PORT_PLL_6_B,
269 BXT_PORT_PLL_8_B,
270 BXT_PORT_PLL_9_B,
271 BXT_PORT_PLL_10_B,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]272 BXT_PORT_REF_DW3_BC,
273 BXT_PORT_REF_DW6_BC,
274 BXT_PORT_REF_DW8_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]275 BXT_PORT_PLL_EBB_0_C,
276 BXT_PORT_PLL_EBB_4_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]277 BXT_PORT_CL2CM_DW6_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]278 BXT_PORT_PLL_0_C,
279 BXT_PORT_PLL_1_C,
280 BXT_PORT_PLL_2_C,
281 BXT_PORT_PLL_3_C,
282 BXT_PORT_PLL_6_C,
283 BXT_PORT_PLL_8_C,
284 BXT_PORT_PLL_9_C,
285 BXT_PORT_PLL_10_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]286 BXT_PORT_PCS_DW10_01_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]287 BXT_PORT_PCS_DW12_01_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]288 BXT_PORT_TX_DW2_LN0_B,
289 BXT_PORT_TX_DW3_LN0_B,
290 BXT_PORT_TX_DW4_LN0_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]291 BXT_PORT_TX_DW14_LN0_B,
292 BXT_PORT_TX_DW14_LN1_B,
293 BXT_PORT_TX_DW14_LN2_B,
294 BXT_PORT_TX_DW14_LN3_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]295 BXT_PORT_PCS_DW10_01_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]296 BXT_PORT_PCS_DW12_01_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]297 BXT_PORT_TX_DW2_LN0_C,
298 BXT_PORT_TX_DW3_LN0_C,
299 BXT_PORT_TX_DW4_LN0_C,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]300 BXT_PORT_TX_DW14_LN0_C,
301 BXT_PORT_TX_DW14_LN1_C,
302 BXT_PORT_TX_DW14_LN2_C,
303 BXT_PORT_TX_DW14_LN3_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]304 BXT_PORT_PCS_DW10_GRP_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]305 BXT_PORT_PCS_DW12_GRP_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]306 BXT_PORT_TX_DW2_GRP_B,
307 BXT_PORT_TX_DW3_GRP_B,
308 BXT_PORT_TX_DW4_GRP_B,
309 BXT_PORT_PCS_DW10_GRP_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]310 BXT_PORT_PCS_DW12_GRP_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]311 BXT_PORT_TX_DW2_GRP_C,
312 BXT_PORT_TX_DW3_GRP_C,
313 BXT_PORT_TX_DW4_GRP_C,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]314 BXT_DE_PLL_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]315 HTOTAL_EDP,
316 HBLANK_EDP,
317 HSYNC_EDP,
318 VTOTAL_EDP,
319 VBLANK_EDP,
320 VSYNC_EDP,
321 PIPE_EDP_DATA_M1,
322 PIPE_EDP_DATA_N1,
323 PIPE_EDP_LINK_M1,
324 PIPE_EDP_LINK_N1,
325 PIPE_EDP_DDI_FUNC_CTL,
326 PIPE_EDP_MSA_MISC,
327 SRD_CTL_EDP,
328 SRD_STATUS_EDP,
329 PIPE_SCANLINE_A,
330 PIPEACONF,
331 PIPEAMISC,
332 PIPE_FRMCNT_A,
333 DSPACNTR,
334 DSPALINOFF,
335 DSPASTRIDE,
336 PLANE_POS_1_A,
337 PLANE_SIZE_1_A,
338 DSPASURF,
339 DSPATILEOFF,
340 PLANE_WM_1_A_0,
341 PLANE_WM_1_A_1,
342 PLANE_WM_1_A_2,
343 PLANE_WM_1_A_3,
344 PLANE_WM_1_A_4,
345 PLANE_WM_1_A_5,
346 PLANE_WM_1_A_6,
347 PLANE_WM_1_A_7,
348 PLANE_BUF_CFG_1_A,
349 SPACNTR,
350 PIPE_SCANLINE_B,
351 PIPEBCONF,
352 PIPEBMISC,
353 PIPE_FRMCNT_B,
354 DSPBCNTR,
355 DSPBLINOFF,
356 DSPBSTRIDE,
357 PLANE_POS_1_B,
358 PLANE_SIZE_1_B,
359 DSPBSURF,
360 DSPBTILEOFF,
361 PLANE_WM_1_B_0,
362 PLANE_WM_1_B_1,
363 PLANE_WM_1_B_2,
364 PLANE_WM_1_B_3,
365 PLANE_WM_1_B_4,
366 PLANE_WM_1_B_5,
367 PLANE_WM_1_B_6,
368 PLANE_WM_1_B_7,
369 PLANE_BUF_CFG_1_B,
370 SPBCNTR,
371 PIPE_SCANLINE_C,
372 PIPECCONF,
373 PIPECMISC,
374 PIPE_FRMCNT_C,
375 DSPCCNTR,
376 DSPCLINOFF,
377 DSPCSTRIDE,
378 PLANE_POS_1_C,
379 PLANE_SIZE_1_C,
380 DSPCSURF,
381 DSPCTILEOFF,
382 PLANE_WM_1_C_0,
383 PLANE_WM_1_C_1,
384 PLANE_WM_1_C_2,
385 PLANE_WM_1_C_3,
386 PLANE_WM_1_C_4,
387 PLANE_WM_1_C_5,
388 PLANE_WM_1_C_6,
389 PLANE_WM_1_C_7,
390 PLANE_BUF_CFG_1_C,
391 SPCCNTR,
392 PIPE_EDP_CONF,
393 PCH_FDI_CHICKEN_B_C,
394 QUIRK_C2004,
395 SFUSE_STRAP,
396 PCH_DSPCLK_GATE_D,
397 SDEISR,
398 SDEIMR,
399 SDEIIR,
400 SDEIER,
401 SHOTPLUG_CTL,
402 PCH_GMBUS0,
403 PCH_GMBUS1,
404 PCH_GMBUS2,
405 PCH_GMBUS3,
406 PCH_GMBUS4,
407 PCH_GMBUS5,
408 SBI_ADDR,
409 SBI_DATA,
410 SBI_CTL_STAT,
411 PCH_DPLL_A,
412 PCH_DPLL_B,
413 PCH_PIXCLK_GATE,
414 PCH_FPA0,
415 PCH_FPA1,
416 PCH_FPB0,
417 PCH_FPB1,
418 PCH_DREF_CONTROL,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]419 PCH_RAWCLK_FREQ,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]420 PCH_DPLL_SEL,
421 PCH_PP_STATUS,
422 PCH_PP_CONTROL,
423 PCH_PP_ON_DELAYS,
424 PCH_PP_OFF_DELAYS,
425 PCH_PP_DIVISOR,
426 BLC_PWM_PCH_CTL1,
427 BLC_PWM_PCH_CTL2,
428 TRANS_HTOTAL_A,
429 TRANS_HBLANK_A,
430 TRANS_HSYNC_A,
431 TRANS_VTOTAL_A,
432 TRANS_VBLANK_A,
433 TRANS_VSYNC_A,
434 TRANS_VSYNCSHIFT_A,
435 TRANSA_DATA_M1,
436 TRANSA_DATA_N1,
437 TRANSA_DP_LINK_M1,
438 TRANSA_DP_LINK_N1,
439 TRANS_DP_CTL_A,
440 TRANS_HTOTAL_B,
441 TRANS_HBLANK_B,
442 TRANS_HSYNC_B,
443 TRANS_VTOTAL_B,
444 TRANS_VBLANK_B,
445 TRANS_VSYNC_B,
446 TRANS_VSYNCSHIFT_B,
447 TRANSB_DATA_M1,
448 TRANSB_DATA_N1,
449 TRANSB_DP_LINK_M1,
450 TRANSB_DP_LINK_N1,
451 PCH_ADPA,
452 PCH_HDMIB,
453 PCH_HDMIC,
454 PCH_HDMID,
455 PCH_LVDS,
456 TRANS_DP_CTL_B,
457 TRANS_HTOTAL_C,
458 TRANS_HBLANK_C,
459 TRANS_HSYNC_C,
460 TRANS_VTOTAL_C,
461 TRANS_VBLANK_C,
462 TRANS_VSYNC_C,
463 TRANS_VSYNCSHIFT_C,
464 TRANSC_DATA_M1,
465 TRANSC_DATA_N1,
466 TRANSC_DP_LINK_M1,
467 TRANSC_DP_LINK_N1,
468 TRANS_DP_CTL_C,
469 PCH_DP_B,
470 PCH_DP_AUX_CTL_B,
471 PCH_DP_AUX_DATA_B_1,
472 PCH_DP_AUX_DATA_B_2,
473 PCH_DP_AUX_DATA_B_3,
474 PCH_DP_AUX_DATA_B_4,
475 PCH_DP_AUX_DATA_B_5,
476 PCH_DP_C,
477 PCH_DP_AUX_CTL_C,
478 PCH_DP_AUX_DATA_C_1,
479 PCH_DP_AUX_DATA_C_2,
480 PCH_DP_AUX_DATA_C_3,
481 PCH_DP_AUX_DATA_C_4,
482 PCH_DP_AUX_DATA_C_5,
483 PCH_DP_D,
484 PCH_DP_AUX_CTL_D,
485 PCH_DP_AUX_DATA_D_1,
486 PCH_DP_AUX_DATA_D_2,
487 PCH_DP_AUX_DATA_D_3,
488 PCH_DP_AUX_DATA_D_4,
489 PCH_DP_AUX_DATA_D_5,
490 AUD_CONFIG_A,
491 PCH_AUD_VID_DID,
492 AUD_HDMIW_HDMIEDID_A,
493 AUD_CNTL_ST_A,
494 AUD_CNTRL_ST2,
495 AUD_CONFIG_B,
496 AUD_HDMIW_HDMIEDID_B,
497 AUD_CNTL_ST_B,
498 AUD_CONFIG_C,
499 AUD_HDMIW_HDMIEDID_C,
500 AUD_CNTL_ST_C,
501 TRANSACONF,
502 FDI_RXA_CTL,
503 FDI_RX_MISC_A,
504 FDI_RXA_IIR,
505 FDI_RXA_IMR,
506 FDI_RXA_TUSIZE1,
507 QUIRK_F0060,
508 TRANSA_CHICKEN2,
509 TRANSBCONF,
510 FDI_RXB_CTL,
511 FDI_RX_MISC_B,
512 FDI_RXB_IIR,
513 FDI_RXB_IMR,
514 FDI_RXB_TUSIZE1,
515 QUIRK_F1060,
516 TRANSB_CHICKEN2,
517 TRANSCCONF,
518 FDI_RXC_CTL,
519 FDI_RX_MISC_C,
520 FDI_RXC_IIR,
521 FDI_RXC_IMR,
522 FDI_RXC_TUSIZE1,
523 QUIRK_F2060,
524 TRANSC_CHICKEN2,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]525 BXT_P_CR_GT_DISP_PWRON,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]526 GT_MAILBOX,
527 GT_MAILBOX_DATA,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]528 GT_MAILBOX_DATA_1,
529 BXT_PORT_CL1CM_DW0_A,
530 BXT_PORT_CL1CM_DW9_A,
531 BXT_PORT_CL1CM_DW10_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]532 BXT_PORT_PLL_EBB_0_A,
533 BXT_PORT_PLL_EBB_4_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]534 BXT_PORT_CL1CM_DW28_A,
535 BXT_PORT_CL1CM_DW30_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]536 BXT_PORT_PLL_0_A,
537 BXT_PORT_PLL_1_A,
538 BXT_PORT_PLL_2_A,
539 BXT_PORT_PLL_3_A,
540 BXT_PORT_PLL_6_A,
541 BXT_PORT_PLL_8_A,
542 BXT_PORT_PLL_9_A,
543 BXT_PORT_PLL_10_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]544 BXT_PORT_REF_DW3_A,
545 BXT_PORT_REF_DW6_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]546 BXT_PORT_REF_DW8_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]547 BXT_PORT_PCS_DW10_01_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]548 BXT_PORT_PCS_DW12_01_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]549 BXT_PORT_TX_DW2_LN0_A,
550 BXT_PORT_TX_DW3_LN0_A,
551 BXT_PORT_TX_DW4_LN0_A,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]552 BXT_PORT_TX_DW14_LN0_A,
553 BXT_PORT_TX_DW14_LN1_A,
554 BXT_PORT_TX_DW14_LN2_A,
555 BXT_PORT_TX_DW14_LN3_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]556 BXT_PORT_PCS_DW10_GRP_A,
557 BXT_PORT_PCS_DW12_GRP_A,
558 BXT_PORT_TX_DW2_GRP_A,
559 BXT_PORT_TX_DW3_GRP_A,
560 BXT_PORT_TX_DW4_GRP_A);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]561
562 pragma Warnings
563 (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)",
564 Reason => "TODO: Should it matter?");
565 pragma Keep_Names (Registers_Invalid_Index);
566 pragma Warnings
567 (GNATprove, On, "pragma ""KEEP_NAMES"" ignored *(not yet supported)");
568
569 Register_Width : constant := 4;
570
571 for Registers_Invalid_Index use
572 (Invalid_Register => 0,
573
574 ---------------------------------------------------------------------------
575 -- Pipe A registers
576 ---------------------------------------------------------------------------
577
578 -- pipe timing registers
579
580 HTOTAL_A => 16#06_0000# / Register_Width,
581 HBLANK_A => 16#06_0004# / Register_Width,
582 HSYNC_A => 16#06_0008# / Register_Width,
583 VTOTAL_A => 16#06_000c# / Register_Width,
584 VBLANK_A => 16#06_0010# / Register_Width,
585 VSYNC_A => 16#06_0014# / Register_Width,
586 PIPEASRC => 16#06_001c# / Register_Width,
587 PIPEACONF => 16#07_0008# / Register_Width,
588 PIPEAMISC => 16#07_0030# / Register_Width,
589 TRANS_HTOTAL_A => 16#0e_0000# / Register_Width,
590 TRANS_HBLANK_A => 16#0e_0004# / Register_Width,
591 TRANS_HSYNC_A => 16#0e_0008# / Register_Width,
592 TRANS_VTOTAL_A => 16#0e_000c# / Register_Width,
593 TRANS_VBLANK_A => 16#0e_0010# / Register_Width,
594 TRANS_VSYNC_A => 16#0e_0014# / Register_Width,
595 TRANSA_DATA_M1 => 16#0e_0030# / Register_Width,
596 TRANSA_DATA_N1 => 16#0e_0034# / Register_Width,
597 TRANSA_DP_LINK_M1 => 16#0e_0040# / Register_Width,
598 TRANSA_DP_LINK_N1 => 16#0e_0044# / Register_Width,
599 PIPEA_DATA_M1 => 16#06_0030# / Register_Width,
600 PIPEA_DATA_N1 => 16#06_0034# / Register_Width,
601 PIPEA_LINK_M1 => 16#06_0040# / Register_Width,
602 PIPEA_LINK_N1 => 16#06_0044# / Register_Width,
603 PIPEA_DDI_FUNC_CTL => 16#06_0400# / Register_Width,
604 PIPEA_MSA_MISC => 16#06_0410# / Register_Width,
605
606 -- PCH sideband interface registers
607 SBI_ADDR => 16#0c_6000# / Register_Width,
608 SBI_DATA => 16#0c_6004# / Register_Width,
609 SBI_CTL_STAT => 16#0c_6008# / Register_Width,
610
611 -- clock registers
612 PCH_DPLL_A => 16#0c_6014# / Register_Width,
613 PCH_PIXCLK_GATE => 16#0c_6020# / Register_Width,
614 PCH_FPA0 => 16#0c_6040# / Register_Width,
615 PCH_FPA1 => 16#0c_6044# / Register_Width,
616
617 -- panel fitter
618 PFA_CTL_1 => 16#06_8080# / Register_Width,
619 PFA_WIN_POS => 16#06_8070# / Register_Width,
620 PFA_WIN_SZ => 16#06_8074# / Register_Width,
621 PS_WIN_POS_1_A => 16#06_8170# / Register_Width,
622 PS_WIN_SZ_1_A => 16#06_8174# / Register_Width,
623 PS_CTRL_1_A => 16#06_8180# / Register_Width,
624 PS_WIN_POS_2_A => 16#06_8270# / Register_Width,
625 PS_WIN_SZ_2_A => 16#06_8274# / Register_Width,
626 PS_CTRL_2_A => 16#06_8280# / Register_Width,
627
628 -- display control
629 DSPACNTR => 16#07_0180# / Register_Width,
630 DSPALINOFF => 16#07_0184# / Register_Width,
631 DSPASTRIDE => 16#07_0188# / Register_Width,
632 PLANE_POS_1_A => 16#07_018c# / Register_Width,
633 PLANE_SIZE_1_A => 16#07_0190# / Register_Width,
634 DSPASURF => 16#07_019c# / Register_Width,
635 DSPATILEOFF => 16#07_01a4# / Register_Width,
636
637 -- sprite control
638 SPACNTR => 16#07_0280# / Register_Width,
639
640 -- FDI and PCH transcoder control
641 FDI_TX_CTL_A => 16#06_0100# / Register_Width,
642 FDI_RXA_CTL => 16#0f_000c# / Register_Width,
643 FDI_RX_MISC_A => 16#0f_0010# / Register_Width,
644 FDI_RXA_IIR => 16#0f_0014# / Register_Width,
645 FDI_RXA_IMR => 16#0f_0018# / Register_Width,
646 FDI_RXA_TUSIZE1 => 16#0f_0030# / Register_Width,
647 TRANSACONF => 16#0f_0008# / Register_Width,
648 TRANSA_CHICKEN2 => 16#0f_0064# / Register_Width,
649
650 -- watermark registers
651 WM_LINETIME_A => 16#04_5270# / Register_Width,
652 PLANE_WM_1_A_0 => 16#07_0240# / Register_Width,
653 PLANE_WM_1_A_1 => 16#07_0244# / Register_Width,
654 PLANE_WM_1_A_2 => 16#07_0248# / Register_Width,
655 PLANE_WM_1_A_3 => 16#07_024c# / Register_Width,
656 PLANE_WM_1_A_4 => 16#07_0250# / Register_Width,
657 PLANE_WM_1_A_5 => 16#07_0254# / Register_Width,
658 PLANE_WM_1_A_6 => 16#07_0258# / Register_Width,
659 PLANE_WM_1_A_7 => 16#07_025c# / Register_Width,
660 PLANE_BUF_CFG_1_A => 16#07_027c# / Register_Width,
661
662 -- CPU transcoder clock select
663 TRANSA_CLK_SEL => 16#04_6140# / Register_Width,
664
665 ---------------------------------------------------------------------------
666 -- Pipe B registers
667 ---------------------------------------------------------------------------
668
669 -- pipe timing registers
670
671 HTOTAL_B => 16#06_1000# / Register_Width,
672 HBLANK_B => 16#06_1004# / Register_Width,
673 HSYNC_B => 16#06_1008# / Register_Width,
674 VTOTAL_B => 16#06_100c# / Register_Width,
675 VBLANK_B => 16#06_1010# / Register_Width,
676 VSYNC_B => 16#06_1014# / Register_Width,
677 PIPEBSRC => 16#06_101c# / Register_Width,
678 PIPEBCONF => 16#07_1008# / Register_Width,
679 PIPEBMISC => 16#07_1030# / Register_Width,
680 TRANS_HTOTAL_B => 16#0e_1000# / Register_Width,
681 TRANS_HBLANK_B => 16#0e_1004# / Register_Width,
682 TRANS_HSYNC_B => 16#0e_1008# / Register_Width,
683 TRANS_VTOTAL_B => 16#0e_100c# / Register_Width,
684 TRANS_VBLANK_B => 16#0e_1010# / Register_Width,
685 TRANS_VSYNC_B => 16#0e_1014# / Register_Width,
686 TRANSB_DATA_M1 => 16#0e_1030# / Register_Width,
687 TRANSB_DATA_N1 => 16#0e_1034# / Register_Width,
688 TRANSB_DP_LINK_M1 => 16#0e_1040# / Register_Width,
689 TRANSB_DP_LINK_N1 => 16#0e_1044# / Register_Width,
690 PIPEB_DATA_M1 => 16#06_1030# / Register_Width,
691 PIPEB_DATA_N1 => 16#06_1034# / Register_Width,
692 PIPEB_LINK_M1 => 16#06_1040# / Register_Width,
693 PIPEB_LINK_N1 => 16#06_1044# / Register_Width,
694 PIPEB_DDI_FUNC_CTL => 16#06_1400# / Register_Width,
695 PIPEB_MSA_MISC => 16#06_1410# / Register_Width,
696
697 -- clock registers
698 PCH_DPLL_B => 16#0c_6018# / Register_Width,
699 PCH_FPB0 => 16#0c_6048# / Register_Width,
700 PCH_FPB1 => 16#0c_604c# / Register_Width,
701
702 -- panel fitter
703 PFB_CTL_1 => 16#06_8880# / Register_Width,
704 PFB_WIN_POS => 16#06_8870# / Register_Width,
705 PFB_WIN_SZ => 16#06_8874# / Register_Width,
706 PS_WIN_POS_1_B => 16#06_8970# / Register_Width,
707 PS_WIN_SZ_1_B => 16#06_8974# / Register_Width,
708 PS_CTRL_1_B => 16#06_8980# / Register_Width,
709 PS_WIN_POS_2_B => 16#06_8a70# / Register_Width,
710 PS_WIN_SZ_2_B => 16#06_8a74# / Register_Width,
711 PS_CTRL_2_B => 16#06_8a80# / Register_Width,
712
713 -- display control
714 DSPBCNTR => 16#07_1180# / Register_Width,
715 DSPBLINOFF => 16#07_1184# / Register_Width,
716 DSPBSTRIDE => 16#07_1188# / Register_Width,
717 PLANE_POS_1_B => 16#07_118c# / Register_Width,
718 PLANE_SIZE_1_B => 16#07_1190# / Register_Width,
719 DSPBSURF => 16#07_119c# / Register_Width,
720 DSPBTILEOFF => 16#07_11a4# / Register_Width,
721
722 -- sprite control
723 SPBCNTR => 16#07_1280# / Register_Width,
724
725 -- FDI and PCH transcoder control
726 FDI_TX_CTL_B => 16#06_1100# / Register_Width,
727 FDI_RXB_CTL => 16#0f_100c# / Register_Width,
728 FDI_RX_MISC_B => 16#0f_1010# / Register_Width,
729 FDI_RXB_IIR => 16#0f_1014# / Register_Width,
730 FDI_RXB_IMR => 16#0f_1018# / Register_Width,
731 FDI_RXB_TUSIZE1 => 16#0f_1030# / Register_Width,
732 TRANSBCONF => 16#0f_1008# / Register_Width,
733 TRANSB_CHICKEN2 => 16#0f_1064# / Register_Width,
734
735 -- watermark registers
736 WM_LINETIME_B => 16#04_5274# / Register_Width,
737 PLANE_WM_1_B_0 => 16#07_1240# / Register_Width,
738 PLANE_WM_1_B_1 => 16#07_1244# / Register_Width,
739 PLANE_WM_1_B_2 => 16#07_1248# / Register_Width,
740 PLANE_WM_1_B_3 => 16#07_124c# / Register_Width,
741 PLANE_WM_1_B_4 => 16#07_1250# / Register_Width,
742 PLANE_WM_1_B_5 => 16#07_1254# / Register_Width,
743 PLANE_WM_1_B_6 => 16#07_1258# / Register_Width,
744 PLANE_WM_1_B_7 => 16#07_125c# / Register_Width,
745 PLANE_BUF_CFG_1_B => 16#07_127c# / Register_Width,
746
747 -- CPU transcoder clock select
748 TRANSB_CLK_SEL => 16#04_6144# / Register_Width,
749
750 ---------------------------------------------------------------------------
751 -- Pipe C registers
752 ---------------------------------------------------------------------------
753
754 -- pipe timing registers
755
756 HTOTAL_C => 16#06_2000# / Register_Width,
757 HBLANK_C => 16#06_2004# / Register_Width,
758 HSYNC_C => 16#06_2008# / Register_Width,
759 VTOTAL_C => 16#06_200c# / Register_Width,
760 VBLANK_C => 16#06_2010# / Register_Width,
761 VSYNC_C => 16#06_2014# / Register_Width,
762 PIPECSRC => 16#06_201c# / Register_Width,
763 PIPECCONF => 16#07_2008# / Register_Width,
764 PIPECMISC => 16#07_2030# / Register_Width,
765 TRANS_HTOTAL_C => 16#0e_2000# / Register_Width,
766 TRANS_HBLANK_C => 16#0e_2004# / Register_Width,
767 TRANS_HSYNC_C => 16#0e_2008# / Register_Width,
768 TRANS_VTOTAL_C => 16#0e_200c# / Register_Width,
769 TRANS_VBLANK_C => 16#0e_2010# / Register_Width,
770 TRANS_VSYNC_C => 16#0e_2014# / Register_Width,
771 TRANSC_DATA_M1 => 16#0e_2030# / Register_Width,
772 TRANSC_DATA_N1 => 16#0e_2034# / Register_Width,
773 TRANSC_DP_LINK_M1 => 16#0e_2040# / Register_Width,
774 TRANSC_DP_LINK_N1 => 16#0e_2044# / Register_Width,
775 PIPEC_DATA_M1 => 16#06_2030# / Register_Width,
776 PIPEC_DATA_N1 => 16#06_2034# / Register_Width,
777 PIPEC_LINK_M1 => 16#06_2040# / Register_Width,
778 PIPEC_LINK_N1 => 16#06_2044# / Register_Width,
779 PIPEC_DDI_FUNC_CTL => 16#06_2400# / Register_Width,
780 PIPEC_MSA_MISC => 16#06_2410# / Register_Width,
781
782 -- panel fitter
783 PFC_CTL_1 => 16#06_9080# / Register_Width,
784 PFC_WIN_POS => 16#06_9070# / Register_Width,
785 PFC_WIN_SZ => 16#06_9074# / Register_Width,
786 PS_WIN_POS_1_C => 16#06_9170# / Register_Width,
787 PS_WIN_SZ_1_C => 16#06_9174# / Register_Width,
788 PS_CTRL_1_C => 16#06_9180# / Register_Width,
789
790 -- display control
791 DSPCCNTR => 16#07_2180# / Register_Width,
792 DSPCLINOFF => 16#07_2184# / Register_Width,
793 DSPCSTRIDE => 16#07_2188# / Register_Width,
794 PLANE_POS_1_C => 16#07_218c# / Register_Width,
795 PLANE_SIZE_1_C => 16#07_2190# / Register_Width,
796 DSPCSURF => 16#07_219c# / Register_Width,
797 DSPCTILEOFF => 16#07_21a4# / Register_Width,
798
799 -- sprite control
800 SPCCNTR => 16#07_2280# / Register_Width,
801
802 -- PCH transcoder control
803 FDI_TX_CTL_C => 16#06_2100# / Register_Width,
804 FDI_RXC_CTL => 16#0f_200c# / Register_Width,
805 FDI_RX_MISC_C => 16#0f_2010# / Register_Width,
806 FDI_RXC_IIR => 16#0f_2014# / Register_Width,
807 FDI_RXC_IMR => 16#0f_2018# / Register_Width,
808 FDI_RXC_TUSIZE1 => 16#0f_2030# / Register_Width,
809 TRANSCCONF => 16#0f_2008# / Register_Width,
810 TRANSC_CHICKEN2 => 16#0f_2064# / Register_Width,
811
812 -- watermark registers
813 WM_LINETIME_C => 16#04_5278# / Register_Width,
814 PLANE_WM_1_C_0 => 16#07_2240# / Register_Width,
815 PLANE_WM_1_C_1 => 16#07_2244# / Register_Width,
816 PLANE_WM_1_C_2 => 16#07_2248# / Register_Width,
817 PLANE_WM_1_C_3 => 16#07_224c# / Register_Width,
818 PLANE_WM_1_C_4 => 16#07_2250# / Register_Width,
819 PLANE_WM_1_C_5 => 16#07_2254# / Register_Width,
820 PLANE_WM_1_C_6 => 16#07_2258# / Register_Width,
821 PLANE_WM_1_C_7 => 16#07_225c# / Register_Width,
822 PLANE_BUF_CFG_1_C => 16#07_227c# / Register_Width,
823
824 -- CPU transcoder clock select
825 TRANSC_CLK_SEL => 16#04_6148# / Register_Width,
826
827 ---------------------------------------------------------------------------
828 -- Pipe EDP registers
829 ---------------------------------------------------------------------------
830
831 -- pipe timing registers
832
833 HTOTAL_EDP => 16#06_f000# / Register_Width,
834 HBLANK_EDP => 16#06_f004# / Register_Width,
835 HSYNC_EDP => 16#06_f008# / Register_Width,
836 VTOTAL_EDP => 16#06_f00c# / Register_Width,
837 VBLANK_EDP => 16#06_f010# / Register_Width,
838 VSYNC_EDP => 16#06_f014# / Register_Width,
839 PIPE_EDP_CONF => 16#07_f008# / Register_Width,
840 PIPE_EDP_DATA_M1 => 16#06_f030# / Register_Width,
841 PIPE_EDP_DATA_N1 => 16#06_f034# / Register_Width,
842 PIPE_EDP_LINK_M1 => 16#06_f040# / Register_Width,
843 PIPE_EDP_LINK_N1 => 16#06_f044# / Register_Width,
844 PIPE_EDP_DDI_FUNC_CTL => 16#06_f400# / Register_Width,
845 PIPE_EDP_MSA_MISC => 16#06_f410# / Register_Width,
846
847 -- PSR registers
848 SRD_CTL => 16#06_4800# / Register_Width,
849 SRD_CTL_A => 16#06_0800# / Register_Width,
850 SRD_CTL_B => 16#06_1800# / Register_Width,
851 SRD_CTL_C => 16#06_2800# / Register_Width,
852 SRD_CTL_EDP => 16#06_f800# / Register_Width,
853 SRD_STATUS => 16#06_4840# / Register_Width,
854 SRD_STATUS_A => 16#06_0840# / Register_Width,
855 SRD_STATUS_B => 16#06_1840# / Register_Width,
856 SRD_STATUS_C => 16#06_2840# / Register_Width,
857 SRD_STATUS_EDP => 16#06_f840# / Register_Width,
858
859 -- DDI registers
860 DDI_BUF_CTL_A => 16#06_4000# / Register_Width, -- aliased by DP_CTL_A
861 DDI_AUX_CTL_A => 16#06_4010# / Register_Width, -- aliased by DP_AUX_CTL_A
862 DDI_AUX_DATA_A_1 => 16#06_4014# / Register_Width, -- aliased by DP_AUX_DATA_A_1
863 DDI_AUX_DATA_A_2 => 16#06_4018# / Register_Width, -- aliased by DP_AUX_DATA_A_2
864 DDI_AUX_DATA_A_3 => 16#06_401c# / Register_Width, -- aliased by DP_AUX_DATA_A_3
865 DDI_AUX_DATA_A_4 => 16#06_4020# / Register_Width, -- aliased by DP_AUX_DATA_A_4
866 DDI_AUX_DATA_A_5 => 16#06_4024# / Register_Width, -- aliased by DP_AUX_DATA_A_5
867 DDI_AUX_MUTEX_A => 16#06_402c# / Register_Width,
868 DDI_BUF_CTL_B => 16#06_4100# / Register_Width,
869 DDI_AUX_CTL_B => 16#06_4110# / Register_Width,
870 DDI_AUX_DATA_B_1 => 16#06_4114# / Register_Width,
871 DDI_AUX_DATA_B_2 => 16#06_4118# / Register_Width,
872 DDI_AUX_DATA_B_3 => 16#06_411c# / Register_Width,
873 DDI_AUX_DATA_B_4 => 16#06_4120# / Register_Width,
874 DDI_AUX_DATA_B_5 => 16#06_4124# / Register_Width,
875 DDI_AUX_MUTEX_B => 16#06_412c# / Register_Width,
876 DDI_BUF_CTL_C => 16#06_4200# / Register_Width,
877 DDI_AUX_CTL_C => 16#06_4210# / Register_Width,
878 DDI_AUX_DATA_C_1 => 16#06_4214# / Register_Width,
879 DDI_AUX_DATA_C_2 => 16#06_4218# / Register_Width,
880 DDI_AUX_DATA_C_3 => 16#06_421c# / Register_Width,
881 DDI_AUX_DATA_C_4 => 16#06_4220# / Register_Width,
882 DDI_AUX_DATA_C_5 => 16#06_4224# / Register_Width,
883 DDI_AUX_MUTEX_C => 16#06_422c# / Register_Width,
884 DDI_BUF_CTL_D => 16#06_4300# / Register_Width,
885 DDI_AUX_CTL_D => 16#06_4310# / Register_Width,
886 DDI_AUX_DATA_D_1 => 16#06_4314# / Register_Width,
887 DDI_AUX_DATA_D_2 => 16#06_4318# / Register_Width,
888 DDI_AUX_DATA_D_3 => 16#06_431c# / Register_Width,
889 DDI_AUX_DATA_D_4 => 16#06_4320# / Register_Width,
890 DDI_AUX_DATA_D_5 => 16#06_4324# / Register_Width,
891 DDI_AUX_MUTEX_D => 16#06_432c# / Register_Width,
892 DDI_BUF_CTL_E => 16#06_4400# / Register_Width,
893 DP_TP_CTL_A => 16#06_4040# / Register_Width,
894 DP_TP_CTL_B => 16#06_4140# / Register_Width,
895 DP_TP_CTL_C => 16#06_4240# / Register_Width,
896 DP_TP_CTL_D => 16#06_4340# / Register_Width,
897 DP_TP_CTL_E => 16#06_4440# / Register_Width,
898 DP_TP_STATUS_B => 16#06_4144# / Register_Width,
899 DP_TP_STATUS_C => 16#06_4244# / Register_Width,
900 DP_TP_STATUS_D => 16#06_4344# / Register_Width,
901 DP_TP_STATUS_E => 16#06_4444# / Register_Width,
902 PORT_CLK_SEL_DDIA => 16#04_6100# / Register_Width,
903 PORT_CLK_SEL_DDIB => 16#04_6104# / Register_Width,
904 PORT_CLK_SEL_DDIC => 16#04_6108# / Register_Width,
905 PORT_CLK_SEL_DDID => 16#04_610c# / Register_Width,
906 PORT_CLK_SEL_DDIE => 16#04_6110# / Register_Width,
907
908 -- Skylake DPLL registers
909 DPLL1_CFGR1 => 16#06_c040# / Register_Width,
910 DPLL1_CFGR2 => 16#06_c044# / Register_Width,
911 DPLL2_CFGR1 => 16#06_c048# / Register_Width,
912 DPLL2_CFGR2 => 16#06_c04c# / Register_Width,
913 DPLL3_CFGR1 => 16#06_c050# / Register_Width,
914 DPLL3_CFGR2 => 16#06_c054# / Register_Width,
915 DPLL_CTRL1 => 16#06_c058# / Register_Width,
916 DPLL_CTRL2 => 16#06_c05c# / Register_Width,
917 DPLL_STATUS => 16#06_c060# / Register_Width,
918
919 -- CD CLK register
920 CDCLK_CTL => 16#04_6000# / Register_Width,
921
922 -- Skylake LCPLL registers
923 LCPLL1_CTL => 16#04_6010# / Register_Width,
924 LCPLL2_CTL => 16#04_6014# / Register_Width,
925
926 -- SPLL register
927 SPLL_CTL => 16#04_6020# / Register_Width,
928
929 -- WRPLL registers
930 WRPLL_CTL_1 => 16#04_6040# / Register_Width,
931 WRPLL_CTL_2 => 16#04_6060# / Register_Width,
932
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]933 -- Broxton Display Engine PLL registers
934 BXT_DE_PLL_CTL => 16#06_d000# / Register_Width,
935 BXT_DE_PLL_ENABLE => 16#04_6070# / Register_Width,
936
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]937 -- Broxton DDI PHY PLL registers
938 BXT_PORT_PLL_ENABLE_A => 16#04_6074# / Register_Width,
939 BXT_PORT_PLL_ENABLE_B => 16#04_6078# / Register_Width,
940 BXT_PORT_PLL_ENABLE_C => 16#04_607c# / Register_Width,
941 BXT_PORT_PLL_EBB_0_A => 16#16_2034# / Register_Width,
942 BXT_PORT_PLL_EBB_4_A => 16#16_2038# / Register_Width,
943 BXT_PORT_PLL_0_A => 16#16_2100# / Register_Width,
944 BXT_PORT_PLL_1_A => 16#16_2104# / Register_Width,
945 BXT_PORT_PLL_2_A => 16#16_2108# / Register_Width,
946 BXT_PORT_PLL_3_A => 16#16_210c# / Register_Width,
947 BXT_PORT_PLL_6_A => 16#16_2118# / Register_Width,
948 BXT_PORT_PLL_8_A => 16#16_2120# / Register_Width,
949 BXT_PORT_PLL_9_A => 16#16_2124# / Register_Width,
950 BXT_PORT_PLL_10_A => 16#16_2128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]951 BXT_PORT_PLL_EBB_0_B => 16#06_c034# / Register_Width,
952 BXT_PORT_PLL_EBB_4_B => 16#06_c038# / Register_Width,
953 BXT_PORT_PLL_0_B => 16#06_c100# / Register_Width,
954 BXT_PORT_PLL_1_B => 16#06_c104# / Register_Width,
955 BXT_PORT_PLL_2_B => 16#06_c108# / Register_Width,
956 BXT_PORT_PLL_3_B => 16#06_c10c# / Register_Width,
957 BXT_PORT_PLL_6_B => 16#06_c118# / Register_Width,
958 BXT_PORT_PLL_8_B => 16#06_c120# / Register_Width,
959 BXT_PORT_PLL_9_B => 16#06_c124# / Register_Width,
960 BXT_PORT_PLL_10_B => 16#06_c128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]961 BXT_PORT_PLL_EBB_0_C => 16#06_c340# / Register_Width,
962 BXT_PORT_PLL_EBB_4_C => 16#06_c344# / Register_Width,
963 BXT_PORT_PLL_0_C => 16#06_c380# / Register_Width,
964 BXT_PORT_PLL_1_C => 16#06_c384# / Register_Width,
965 BXT_PORT_PLL_2_C => 16#06_c388# / Register_Width,
966 BXT_PORT_PLL_3_C => 16#06_c38c# / Register_Width,
967 BXT_PORT_PLL_6_C => 16#06_c398# / Register_Width,
968 BXT_PORT_PLL_8_C => 16#06_c3a0# / Register_Width,
969 BXT_PORT_PLL_9_C => 16#06_c3a4# / Register_Width,
970 BXT_PORT_PLL_10_C => 16#06_c3a8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]971
972 -- Broxton DDI PHY PCS? registers
973 BXT_PORT_PCS_DW10_01_A => 16#16_2428# / Register_Width,
974 BXT_PORT_PCS_DW12_01_A => 16#16_2430# / Register_Width,
975 BXT_PORT_PCS_DW10_GRP_A => 16#16_2c28# / Register_Width,
976 BXT_PORT_PCS_DW12_GRP_A => 16#16_2c30# / Register_Width,
977 BXT_PORT_PCS_DW10_01_B => 16#06_c428# / Register_Width,
978 BXT_PORT_PCS_DW12_01_B => 16#06_c430# / Register_Width,
979 BXT_PORT_PCS_DW10_01_C => 16#06_c828# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]980 BXT_PORT_PCS_DW12_01_C => 16#06_c830# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]981 BXT_PORT_PCS_DW10_GRP_B => 16#06_cc28# / Register_Width,
982 BXT_PORT_PCS_DW12_GRP_B => 16#06_cc30# / Register_Width,
983 BXT_PORT_PCS_DW10_GRP_C => 16#06_ce28# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]984 BXT_PORT_PCS_DW12_GRP_C => 16#06_ce30# / Register_Width,
985
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]986 -- Broxton DDI PHY registers
987 BXT_P_CR_GT_DISP_PWRON => 16#13_8090# / Register_Width,
988 BXT_PHY_CTL_A => 16#06_4c00# / Register_Width,
989 BXT_PHY_CTL_B => 16#06_4c10# / Register_Width,
990 BXT_PHY_CTL_C => 16#06_4c20# / Register_Width,
991 BXT_PHY_CTL_FAM_EDP => 16#06_4c80# / Register_Width,
992 BXT_PHY_CTL_FAM_DDI => 16#06_4c90# / Register_Width,
993
994 -- Broxton DDI PHY common lane registers
995 BXT_PORT_CL1CM_DW0_A => 16#16_2000# / Register_Width,
996 BXT_PORT_CL1CM_DW0_BC => 16#06_c000# / Register_Width,
997 BXT_PORT_CL1CM_DW9_A => 16#16_2024# / Register_Width,
998 BXT_PORT_CL1CM_DW9_BC => 16#06_c024# / Register_Width,
999 BXT_PORT_CL1CM_DW10_A => 16#16_2028# / Register_Width,
1000 BXT_PORT_CL1CM_DW10_BC => 16#06_c028# / Register_Width,
1001 BXT_PORT_CL1CM_DW28_A => 16#16_2070# / Register_Width,
1002 BXT_PORT_CL1CM_DW28_BC => 16#06_c070# / Register_Width,
1003 BXT_PORT_CL1CM_DW30_A => 16#16_2078# / Register_Width,
1004 BXT_PORT_CL1CM_DW30_BC => 16#06_c078# / Register_Width,
1005 BXT_PORT_CL2CM_DW6_BC => 16#06_c358# / Register_Width,
1006
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1007 -- Broxton DDI PHY TX lane registers
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1008 BXT_PORT_TX_DW2_LN0_A => 16#16_2508# / Register_Width,
1009 BXT_PORT_TX_DW3_LN0_A => 16#16_250c# / Register_Width,
1010 BXT_PORT_TX_DW4_LN0_A => 16#16_2510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1011 BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width,
1012 BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width,
1013 BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width,
1014 BXT_PORT_TX_DW14_LN3_A => 16#16_27b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1015 BXT_PORT_TX_DW2_GRP_A => 16#16_2d08# / Register_Width,
1016 BXT_PORT_TX_DW3_GRP_A => 16#16_2d0c# / Register_Width,
1017 BXT_PORT_TX_DW4_GRP_A => 16#16_2d10# / Register_Width,
1018 BXT_PORT_TX_DW2_LN0_B => 16#06_c508# / Register_Width,
1019 BXT_PORT_TX_DW3_LN0_B => 16#06_c50c# / Register_Width,
1020 BXT_PORT_TX_DW4_LN0_B => 16#06_c510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1021 BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width,
1022 BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width,
1023 BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width,
1024 BXT_PORT_TX_DW14_LN3_B => 16#06_c7b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1025 BXT_PORT_TX_DW2_GRP_B => 16#06_cd08# / Register_Width,
1026 BXT_PORT_TX_DW3_GRP_B => 16#06_cd0c# / Register_Width,
1027 BXT_PORT_TX_DW4_GRP_B => 16#06_cd10# / Register_Width,
1028 BXT_PORT_TX_DW2_LN0_C => 16#06_c908# / Register_Width,
1029 BXT_PORT_TX_DW3_LN0_C => 16#06_c90c# / Register_Width,
1030 BXT_PORT_TX_DW4_LN0_C => 16#06_c910# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1031 BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width,
1032 BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width,
1033 BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width,
1034 BXT_PORT_TX_DW14_LN3_C => 16#06_cbb8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1035 BXT_PORT_TX_DW2_GRP_C => 16#06_cf08# / Register_Width,
1036 BXT_PORT_TX_DW3_GRP_C => 16#06_cf0c# / Register_Width,
1037 BXT_PORT_TX_DW4_GRP_C => 16#06_cf10# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1038
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1039 -- Broxton DDI PHY ref registers
1040 BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width,
1041 BXT_PORT_REF_DW3_BC => 16#06_c18c# / Register_Width,
1042 BXT_PORT_REF_DW6_A => 16#16_2198# / Register_Width,
1043 BXT_PORT_REF_DW6_BC => 16#06_c198# / Register_Width,
1044 BXT_PORT_REF_DW8_A => 16#16_21a0# / Register_Width,
1045 BXT_PORT_REF_DW8_BC => 16#06_c1a0# / Register_Width,
1046
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1047 -- Power Down Well registers
1048 PWR_WELL_CTL_BIOS => 16#04_5400# / Register_Width,
1049 PWR_WELL_CTL_DRIVER => 16#04_5404# / Register_Width,
1050 PWR_WELL_CTL_KVMR => 16#04_5408# / Register_Width,
1051 PWR_WELL_CTL_DEBUG => 16#04_540c# / Register_Width,
1052 PWR_WELL_CTL5 => 16#04_5410# / Register_Width,
1053 PWR_WELL_CTL6 => 16#04_5414# / Register_Width,
1054
1055 -- class Panel registers
1056 PCH_PP_STATUS => 16#0c_7200# / Register_Width,
1057 PCH_PP_CONTROL => 16#0c_7204# / Register_Width,
1058 PCH_PP_ON_DELAYS => 16#0c_7208# / Register_Width,
1059 PCH_PP_OFF_DELAYS => 16#0c_720c# / Register_Width,
1060 PCH_PP_DIVISOR => 16#0c_7210# / Register_Width,
1061 BLC_PWM_CPU_CTL => 16#04_8254# / Register_Width,
1062 BLC_PWM_PCH_CTL2 => 16#0c_8254# / Register_Width,
1063
1064 -- PCH LVDS Connector Registers
1065 PCH_LVDS => 16#0e_1180# / Register_Width,
1066
1067 -- PCH ADPA Connector Registers
1068 PCH_ADPA => 16#0e_1100# / Register_Width,
1069
1070 -- PCH HDMIB Connector Registers
1071 PCH_HDMIB => 16#0e_1140# / Register_Width,
1072
1073 -- PCH HDMIC Connector Registers
1074 PCH_HDMIC => 16#0e_1150# / Register_Width,
1075
1076 -- PCH HDMID Connector Registers
1077 PCH_HDMID => 16#0e_1160# / Register_Width,
1078
1079 -- Intel Registers
1080 VGACNTRL => 16#04_1000# / Register_Width,
1081 FUSE_STATUS => 16#04_2000# / Register_Width,
1082 FBA_CFB_BASE => 16#04_3200# / Register_Width,
1083 IPS_CTL => 16#04_3408# / Register_Width,
1084 ARB_CTL => 16#04_5000# / Register_Width,
1085 DBUF_CTL => 16#04_5008# / Register_Width,
1086 NDE_RSTWRN_OPT => 16#04_6408# / Register_Width,
1087 PCH_DREF_CONTROL => 16#0c_6200# / Register_Width,
1088 BLC_PWM_PCH_CTL1 => 16#0c_8250# / Register_Width,
1089 BLC_PWM_CPU_CTL2 => 16#04_8250# / Register_Width,
1090 PCH_DPLL_SEL => 16#0c_7000# / Register_Width,
1091 GT_MAILBOX => 16#13_8124# / Register_Width,
1092 GT_MAILBOX_DATA => 16#13_8128# / Register_Width,
1093 GT_MAILBOX_DATA_1 => 16#13_812c# / Register_Width,
1094
1095 PCH_DP_B => 16#0e_4100# / Register_Width,
1096 PCH_DP_AUX_CTL_B => 16#0e_4110# / Register_Width,
1097 PCH_DP_AUX_DATA_B_1 => 16#0e_4114# / Register_Width,
1098 PCH_DP_AUX_DATA_B_2 => 16#0e_4118# / Register_Width,
1099 PCH_DP_AUX_DATA_B_3 => 16#0e_411c# / Register_Width,
1100 PCH_DP_AUX_DATA_B_4 => 16#0e_4120# / Register_Width,
1101 PCH_DP_AUX_DATA_B_5 => 16#0e_4124# / Register_Width,
1102 PCH_DP_C => 16#0e_4200# / Register_Width,
1103 PCH_DP_AUX_CTL_C => 16#0e_4210# / Register_Width,
1104 PCH_DP_AUX_DATA_C_1 => 16#0e_4214# / Register_Width,
1105 PCH_DP_AUX_DATA_C_2 => 16#0e_4218# / Register_Width,
1106 PCH_DP_AUX_DATA_C_3 => 16#0e_421c# / Register_Width,
1107 PCH_DP_AUX_DATA_C_4 => 16#0e_4220# / Register_Width,
1108 PCH_DP_AUX_DATA_C_5 => 16#0e_4224# / Register_Width,
1109 PCH_DP_D => 16#0e_4300# / Register_Width,
1110 PCH_DP_AUX_CTL_D => 16#0e_4310# / Register_Width,
1111 PCH_DP_AUX_DATA_D_1 => 16#0e_4314# / Register_Width,
1112 PCH_DP_AUX_DATA_D_2 => 16#0e_4318# / Register_Width,
1113 PCH_DP_AUX_DATA_D_3 => 16#0e_431c# / Register_Width,
1114 PCH_DP_AUX_DATA_D_4 => 16#0e_4320# / Register_Width,
1115 PCH_DP_AUX_DATA_D_5 => 16#0e_4324# / Register_Width,
1116
1117 -- watermark registers
1118 WM1_LP_ILK => 16#04_5108# / Register_Width,
1119 WM2_LP_ILK => 16#04_510c# / Register_Width,
1120 WM3_LP_ILK => 16#04_5110# / Register_Width,
1121
1122 -- audio VID/DID
1123 AUD_VID_DID => 16#06_5020# / Register_Width,
1124 PCH_AUD_VID_DID => 16#0e_5020# / Register_Width,
1125
1126 -- interrupt registers
1127 DEISR => 16#04_4000# / Register_Width,
1128 DEIMR => 16#04_4004# / Register_Width,
1129 DEIIR => 16#04_4008# / Register_Width,
1130 DEIER => 16#04_400c# / Register_Width,
1131 GTISR => 16#04_4010# / Register_Width,
1132 GTIMR => 16#04_4014# / Register_Width,
1133 GTIIR => 16#04_4018# / Register_Width,
1134 GTIER => 16#04_401c# / Register_Width,
1135 SDEISR => 16#0c_4000# / Register_Width,
1136 SDEIMR => 16#0c_4004# / Register_Width,
1137 SDEIIR => 16#0c_4008# / Register_Width,
1138 SDEIER => 16#0c_400c# / Register_Width,
1139
1140 -- I2C stuff
1141 PCH_GMBUS0 => 16#0c_5100# / Register_Width,
1142 PCH_GMBUS1 => 16#0c_5104# / Register_Width,
1143 PCH_GMBUS2 => 16#0c_5108# / Register_Width,
1144 PCH_GMBUS3 => 16#0c_510c# / Register_Width,
1145 PCH_GMBUS4 => 16#0c_5110# / Register_Width,
1146 PCH_GMBUS5 => 16#0c_5120# / Register_Width,
1147
1148 -- clock gating -- maybe have to touch this
1149 DSPCLK_GATE_D => 16#04_2020# / Register_Width,
1150 PCH_FDI_CHICKEN_B_C => 16#0c_2000# / Register_Width,
1151 PCH_DSPCLK_GATE_D => 16#0c_2020# / Register_Width,
1152
1153 -- hotplug and initial detection
1154 HOTPLUG_CTL => 16#04_4030# / Register_Width,
1155 SHOTPLUG_CTL => 16#0c_4030# / Register_Width,
1156 SFUSE_STRAP => 16#0c_2014# / Register_Width,
1157
1158 -- Render Engine Command Streamer
1159 ARB_MODE => 16#00_4030# / Register_Width,
1160 HWS_PGA => 16#00_4080# / Register_Width,
1161 RCS_RING_BUFFER_TAIL => 16#00_2030# / Register_Width,
1162 VCS_RING_BUFFER_TAIL => 16#01_2030# / Register_Width,
1163 BCS_RING_BUFFER_TAIL => 16#02_2030# / Register_Width,
1164 RCS_RING_BUFFER_HEAD => 16#00_2034# / Register_Width,
1165 VCS_RING_BUFFER_HEAD => 16#01_2034# / Register_Width,
1166 BCS_RING_BUFFER_HEAD => 16#02_2034# / Register_Width,
1167 RCS_RING_BUFFER_STRT => 16#00_2038# / Register_Width,
1168 VCS_RING_BUFFER_STRT => 16#01_2038# / Register_Width,
1169 BCS_RING_BUFFER_STRT => 16#02_2038# / Register_Width,
1170 RCS_RING_BUFFER_CTL => 16#00_203c# / Register_Width,
1171 VCS_RING_BUFFER_CTL => 16#01_203c# / Register_Width,
1172 BCS_RING_BUFFER_CTL => 16#02_203c# / Register_Width,
1173 MI_MODE => 16#00_209c# / Register_Width,
1174 INSTPM => 16#00_20c0# / Register_Width,
1175 GAB_CTL_REG => 16#02_4000# / Register_Width,
1176 PP_DCLV_HIGH => 16#00_2220# / Register_Width,
1177 PP_DCLV_LOW => 16#00_2228# / Register_Width,
1178 VCS_PP_DCLV_HIGH => 16#01_2220# / Register_Width,
1179 VCS_PP_DCLV_LOW => 16#01_2228# / Register_Width,
1180 BCS_PP_DCLV_HIGH => 16#02_2220# / Register_Width,
1181 BCS_PP_DCLV_LOW => 16#02_2228# / Register_Width,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1182 ILK_DISPLAY_CHICKEN2 => 16#04_2004# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1183 UCGCTL1 => 16#00_9400# / Register_Width,
1184 UCGCTL2 => 16#00_9404# / Register_Width,
1185 MBCTL => 16#00_907c# / Register_Width,
1186 HWSTAM => 16#00_2098# / Register_Width,
1187 VCS_HWSTAM => 16#01_2098# / Register_Width,
1188 BCS_HWSTAM => 16#02_2098# / Register_Width,
1189 IIR => 16#04_4028# / Register_Width,
1190 PIPE_FRMCNT_A => 16#07_0040# / Register_Width,
1191 PIPE_FRMCNT_B => 16#07_1040# / Register_Width,
1192 PIPE_FRMCNT_C => 16#07_2040# / Register_Width,
1193 FBC_CTL => 16#04_3208# / Register_Width,
1194 PIPE_VSYNCSHIFT_A => 16#06_0028# / Register_Width,
1195 PIPE_VSYNCSHIFT_B => 16#06_1028# / Register_Width,
1196 PIPE_VSYNCSHIFT_C => 16#06_2028# / Register_Width,
1197 WM_PIPE_A => 16#04_5100# / Register_Width,
1198 WM_PIPE_B => 16#04_5104# / Register_Width,
1199 WM_PIPE_C => 16#04_5200# / Register_Width,
1200 PIPE_SCANLINE_A => 16#07_0000# / Register_Width,
1201 PIPE_SCANLINE_B => 16#07_1000# / Register_Width,
1202 PIPE_SCANLINE_C => 16#07_2000# / Register_Width,
1203 GFX_MODE => 16#00_2520# / Register_Width,
1204 CACHE_MODE_0 => 16#00_2120# / Register_Width,
1205 SLEEP_PSMI_CONTROL => 16#01_2050# / Register_Width,
1206 CTX_SIZE => 16#00_21a0# / Register_Width,
1207 GAC_ECO_BITS => 16#01_4090# / Register_Width,
1208 GAM_ECOCHK => 16#00_4090# / Register_Width,
1209 QUIRK_02084 => 16#00_2084# / Register_Width,
1210 QUIRK_02090 => 16#00_2090# / Register_Width,
1211 GT_MODE => 16#00_20d0# / Register_Width,
1212 QUIRK_F0060 => 16#0f_0060# / Register_Width,
1213 QUIRK_F1060 => 16#0f_1060# / Register_Width,
1214 QUIRK_F2060 => 16#0f_2060# / Register_Width,
1215 AUD_CNTRL_ST2 => 16#0e_50c0# / Register_Width,
1216 AUD_CNTL_ST_A => 16#0e_50b4# / Register_Width,
1217 AUD_CNTL_ST_B => 16#0e_51b4# / Register_Width,
1218 AUD_CNTL_ST_C => 16#0e_52b4# / Register_Width,
1219 AUD_HDMIW_HDMIEDID_A => 16#0e_5050# / Register_Width,
1220 AUD_HDMIW_HDMIEDID_B => 16#0e_5150# / Register_Width,
1221 AUD_HDMIW_HDMIEDID_C => 16#0e_5250# / Register_Width,
1222 AUD_CONFIG_A => 16#0e_5000# / Register_Width,
1223 AUD_CONFIG_B => 16#0e_5100# / Register_Width,
1224 AUD_CONFIG_C => 16#0e_5200# / Register_Width,
1225 TRANS_DP_CTL_A => 16#0e_0300# / Register_Width,
1226 TRANS_DP_CTL_B => 16#0e_1300# / Register_Width,
1227 TRANS_DP_CTL_C => 16#0e_2300# / Register_Width,
1228 TRANS_VSYNCSHIFT_A => 16#0e_0028# / Register_Width,
1229 TRANS_VSYNCSHIFT_B => 16#0e_1028# / Register_Width,
1230 TRANS_VSYNCSHIFT_C => 16#0e_2028# / Register_Width,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]1231 PCH_RAWCLK_FREQ => 16#0c_6204# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1232 QUIRK_C2004 => 16#0c_2004# / Register_Width);
1233
1234 subtype Registers_Index is Registers_Invalid_Index range
1235 Registers_Invalid_Index'Succ (Invalid_Register) ..
1236 Registers_Invalid_Index'Last;
1237
1238 -- aliased registers
1239 DP_CTL_A : constant Registers_Index := DDI_BUF_CTL_A;
1240 DP_AUX_CTL_A : constant Registers_Index := DDI_AUX_CTL_A;
1241 DP_AUX_DATA_A_1 : constant Registers_Index := DDI_AUX_DATA_A_1;
1242 DP_AUX_DATA_A_2 : constant Registers_Index := DDI_AUX_DATA_A_2;
1243 DP_AUX_DATA_A_3 : constant Registers_Index := DDI_AUX_DATA_A_3;
1244 DP_AUX_DATA_A_4 : constant Registers_Index := DDI_AUX_DATA_A_4;
1245 DP_AUX_DATA_A_5 : constant Registers_Index := DDI_AUX_DATA_A_5;
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1246 ILK_DISPLAY_CHICKEN1 : constant Registers_Index := FUSE_STATUS;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1247
1248 ---------------------------------------------------------------------------
1249
1250 Default_Timeout_MS : constant := 10;
1251
1252 ---------------------------------------------------------------------------
1253
1254 procedure Posting_Read
1255 (Register : in Registers_Index)
1256 with
1257 Global => (In_Out => Register_State),
1258 Depends => (Register_State =>+ (Register)),
1259 Pre => True,
1260 Post => True;
1261
1262 pragma Warnings (GNATprove, Off, "unused variable ""Verbose""",
1263 Reason => "Only used on debugging path");
1264 procedure Read
1265 (Register : in Registers_Index;
1266 Value : out Word32;
1267 Verbose : in Boolean := True)
1268 with
1269 Global => (In_Out => Register_State),
1270 Depends => ((Value, Register_State) => (Register, Register_State),
1271 null => Verbose),
1272 Pre => True,
1273 Post => True;
1274 pragma Warnings (GNATprove, On, "unused variable ""Verbose""");
1275
1276 procedure Write
1277 (Register : Registers_Index;
1278 Value : Word32)
1279 with
1280 Global => (In_Out => Register_State),
1281 Depends => (Register_State => (Register, Register_State, Value)),
1282 Pre => True,
1283 Post => True;
1284
1285 procedure Is_Set_Mask
1286 (Register : in Registers_Index;
1287 Mask : in Word32;
1288 Result : out Boolean);
1289
1290 pragma Warnings (GNATprove, Off, "unused initial value of ""Verbose""",
1291 Reason => "Only used on debugging path");
Nico Huberbcb2c472017-02-02 16:39:26 +0100[diff] [blame]1292 procedure Wait
1293 (Register : Registers_Index;
1294 Mask : Word32;
1295 Value : Word32;
1296 TOut_MS : Natural := Default_Timeout_MS;
1297 Verbose : Boolean := False);
1298
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1299 procedure Wait_Set_Mask
1300 (Register : Registers_Index;
1301 Mask : Word32;
1302 TOut_MS : Natural := Default_Timeout_MS;
1303 Verbose : Boolean := False);
1304
1305 procedure Wait_Unset_Mask
1306 (Register : Registers_Index;
1307 Mask : Word32;
1308 TOut_MS : Natural := Default_Timeout_MS;
1309 Verbose : Boolean := False);
1310 pragma Warnings (GNATprove, On, "unused initial value of ""Verbose""");
1311
1312 procedure Set_Mask
1313 (Register : Registers_Index;
1314 Mask : Word32);
1315
1316 procedure Unset_Mask
1317 (Register : Registers_Index;
1318 Mask : Word32);
1319
1320 procedure Unset_And_Set_Mask
1321 (Register : Registers_Index;
1322 Mask_Unset : Word32;
1323 Mask_Set : Word32);
1324
1325 pragma Warnings (Off, "declaration of ""Write_GTT"" hides one at *");
1326 procedure Write_GTT
1327 (GTT_Page : GTT_Range;
1328 Device_Address : GTT_Address_Type;
1329 Valid : Boolean)
1330 with
1331 Global => (In_Out => GTT_State),
1332 Depends => (GTT_State =>+ (GTT_Page, Device_Address, Valid)),
1333 Pre => True,
1334 Post => True;
1335 pragma Warnings (On, "declaration of ""Write_GTT"" hides one at *");
1336
1337 procedure Set_Register_Base (Base : Word64)
1338 with
1339 Global => (Output => Address_State),
1340 Depends => (Address_State => Base),
1341 Pre => True,
1342 Post => True;
1343
1344end HW.GFX.GMA.Registers;