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Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
5 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +00006 * Copyright (C) 2007-2009 Luc Verhaegen <libv@skynet.be>
Carl-Daniel Hailfinger92242622007-09-27 14:29:57 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00008 *
Uwe Hermannd1107642007-08-29 17:52:32 +00009 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000021 */
22
23/*
24 * Contains the board specific flash enables.
25 */
26
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000027#include <string.h>
Mart Raudseppfaa62fb2008-02-20 11:11:18 +000028#include <fcntl.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000029#include "flash.h"
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000030
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000031/*
Uwe Hermannffec5f32007-08-23 16:08:21 +000032 * Helper functions for many Winbond Super I/Os of the W836xx range.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000033 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000034/* Enter extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000035void w836xx_ext_enter(uint16_t port)
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000036{
Andriy Gapon65c1b862008-05-22 13:22:45 +000037 OUTB(0x87, port);
38 OUTB(0x87, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000039}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000040
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000041/* Leave extended functions */
Peter Stuge9d9399c2009-01-26 02:34:51 +000042void w836xx_ext_leave(uint16_t port)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000043{
Andriy Gapon65c1b862008-05-22 13:22:45 +000044 OUTB(0xAA, port);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000045}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000046
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000047/* Generic Super I/O helper functions */
48uint8_t sio_read(uint16_t port, uint8_t reg)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000049{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000050 OUTB(reg, port);
51 return INB(port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000052}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000053
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000054void sio_write(uint16_t port, uint8_t reg, uint8_t data)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000055{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000056 OUTB(reg, port);
57 OUTB(data, port + 1);
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000058}
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000059
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000060void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask)
Luc Verhaegen7977f4e2007-05-04 04:47:04 +000061{
Ronald G. Minnichfa496922007-10-12 21:22:40 +000062 uint8_t tmp;
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000063
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +000064 OUTB(reg, port);
65 tmp = INB(port + 1) & ~mask;
66 OUTB(tmp | (data & mask), port + 1);
Mondrian Nuessleaef1c7c2007-05-03 10:09:23 +000067}
68
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000069/* Not used yet. */
70#if 0
71static int enable_flash_decode_superio(void)
72{
73 int ret;
74 uint8_t tmp;
75
76 switch (superio.vendor) {
77 case SUPERIO_VENDOR_NONE:
78 ret = -1;
79 break;
80 case SUPERIO_VENDOR_ITE:
81 enter_conf_mode_ite(superio.port);
Uwe Hermann43959702010-03-13 17:28:29 +000082 /* Enable flash mapping. Works for most old ITE style Super I/O. */
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000083 tmp = sio_read(superio.port, 0x24);
84 tmp |= 0xfc;
85 sio_write(superio.port, 0x24, tmp);
86 exit_conf_mode_ite(superio.port);
87 ret = 0;
88 break;
89 default:
Uwe Hermann43959702010-03-13 17:28:29 +000090 printf_debug("Unhandled Super I/O type!\n");
Carl-Daniel Hailfinger14e100c2009-12-22 23:42:04 +000091 ret = -1;
92 break;
93 }
94 return ret;
95}
96#endif
97
Uwe Hermannffec5f32007-08-23 16:08:21 +000098/**
99 * Winbond W83627HF: Raise GPIO24.
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000100 *
101 * Suited for:
Uwe Hermannffec5f32007-08-23 16:08:21 +0000102 * - Agami Aruma
103 * - IWILL DK8-HTX
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000104 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000105static int w83627hf_gpio24_raise(uint16_t port, const char *name)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000106{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000107 w836xx_ext_enter(port);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000108
Uwe Hermann372eeb52007-12-04 21:49:06 +0000109 /* Is this the W83627HF? */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000110 if (sio_read(port, 0x20) != 0x52) { /* Super I/O device ID reg. */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000111 fprintf(stderr, "\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n",
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000112 name, sio_read(port, 0x20));
113 w836xx_ext_leave(port);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000114 return -1;
115 }
116
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000117 /* PIN89S: WDTO/GP24 multiplex -> GPIO24 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000118 sio_mask(port, 0x2B, 0x10, 0x10);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000119
Uwe Hermann372eeb52007-12-04 21:49:06 +0000120 /* Select logical device 8: GPIO port 2 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000121 sio_write(port, 0x07, 0x08);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000122
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000123 sio_mask(port, 0x30, 0x01, 0x01); /* Activate logical device. */
124 sio_mask(port, 0xF0, 0x00, 0x10); /* GPIO24 -> output */
125 sio_mask(port, 0xF2, 0x00, 0x10); /* Clear GPIO24 inversion */
126 sio_mask(port, 0xF1, 0x10, 0x10); /* Raise GPIO24 */
Luc Verhaegen7977f4e2007-05-04 04:47:04 +0000127
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000128 w836xx_ext_leave(port);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000129
130 return 0;
131}
132
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000133static int w83627hf_gpio24_raise_2e(const char *name)
134{
Mondrian nuessle197d6cd2009-04-09 14:28:36 +0000135 return w83627hf_gpio24_raise(0x2e, name);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000136}
137
138/**
139 * Winbond W83627THF: GPIO 4, bit 4
140 *
141 * Suited for:
Peter Stugecce26822008-07-21 17:48:40 +0000142 * - MSI K8T Neo2-F
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000143 * - MSI K8N-NEO3
144 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000145static int w83627thf_gpio4_4_raise(uint16_t port, const char *name)
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000146{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000147 w836xx_ext_enter(port);
Uwe Hermann372eeb52007-12-04 21:49:06 +0000148
149 /* Is this the W83627THF? */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000150 if (sio_read(port, 0x20) != 0x82) { /* Super I/O device ID reg. */
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000151 fprintf(stderr, "\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n",
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000152 name, sio_read(port, 0x20));
153 w836xx_ext_leave(port);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000154 return -1;
155 }
156
157 /* PINxxxxS: GPIO4/bit 4 multiplex -> GPIOXXX */
158
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000159 sio_write(port, 0x07, 0x09); /* Select LDN 9: GPIO port 4 */
160 sio_mask(port, 0x30, 0x02, 0x02); /* Activate logical device. */
161 sio_mask(port, 0xF4, 0x00, 0x10); /* GPIO4 bit 4 -> output */
162 sio_mask(port, 0xF6, 0x00, 0x10); /* Clear GPIO4 bit 4 inversion */
163 sio_mask(port, 0xF5, 0x10, 0x10); /* Raise GPIO4 bit 4 */
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000164
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000165 w836xx_ext_leave(port);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000166
167 return 0;
168}
169
Peter Stugecce26822008-07-21 17:48:40 +0000170static int w83627thf_gpio4_4_raise_2e(const char *name)
171{
172 return w83627thf_gpio4_4_raise(0x2e, name);
173}
174
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000175static int w83627thf_gpio4_4_raise_4e(const char *name)
176{
Uwe Hermann372eeb52007-12-04 21:49:06 +0000177 return w83627thf_gpio4_4_raise(0x4e, name);
Ronald G. Minnichfa496922007-10-12 21:22:40 +0000178}
Uwe Hermann372eeb52007-12-04 21:49:06 +0000179
Uwe Hermannffec5f32007-08-23 16:08:21 +0000180/**
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000181 * w83627: Enable MEMW# and set ROM size to max.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000182 */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000183static void w836xx_memw_enable(uint16_t port)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000184{
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000185 w836xx_ext_enter(port);
186 if (!(sio_read(port, 0x24) & 0x02)) { /* Flash ROM enabled? */
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000187 /* Enable MEMW# and set ROM size select to max. (4M). */
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000188 sio_mask(port, 0x24, 0x28, 0x28);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000189 }
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000190 w836xx_ext_leave(port);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000191}
192
193/**
Luc Verhaegen73d21192009-12-23 00:54:26 +0000194 * Suited for:
195 * - EPoX EP-8K5A2: VIA KT333 + VT8235.
196 * - Albatron PM266A Pro: VIA P4M266A + VT8235.
197 * - Shuttle AK31 (all versions): VIA KT266 + VT8233.
198 * - ASUS A7V8X-MX SE and A7V400-MX: AMD K7 + VIA KM400A + VT8235
199 * - Tyan S2498 (Tomcat K7M): AMD Geode NX + VIA KM400 + VT8237.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000200 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000201static int w836xx_memw_enable_2e(const char *name)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000202{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000203 w836xx_memw_enable(0x2E);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000204
Luc Verhaegen73d21192009-12-23 00:54:26 +0000205 return 0;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000206}
207
Luc Verhaegen21f54962010-01-20 14:45:07 +0000208/**
209 *
210 */
211static int it8705f_write_enable(uint8_t port, const char *name)
212{
213 enter_conf_mode_ite(port);
214 sio_mask(port, 0x24, 0x04, 0x04); /* Flash ROM I/F Writes Enable */
215 exit_conf_mode_ite(port);
216
217 return 0;
218}
219
220/**
221 * Suited for:
222 * - AOpen vKM400Am-S: VIA KM400 + VT8237 + IT8705F.
223 * - Biostar P4M80-M4: VIA P4M800 + VT8237 + IT8705AF
224 * - Elitegroup K7S6A: SiS745 + ITE IT8705F
225 * - Elitegroup K7VTA3: VIA Apollo KT266/A/333 + VIA VT8235 + ITE IT8705F
226 * - GIGABYTE GA-7VT600: VIA KT600 + VT8237 + IT8705
227 * - Shuttle AK38N: VIA KT333CF + VIA VT8235 + ITE IT8705F
228 *
Uwe Hermann43959702010-03-13 17:28:29 +0000229 * The SIS950 Super I/O probably requires the same flash write enable.
Luc Verhaegen21f54962010-01-20 14:45:07 +0000230 */
231static int it8705f_write_enable_2e(const char *name)
232{
233 return it8705f_write_enable(0x2e, name);
234}
Luc Verhaegen73d21192009-12-23 00:54:26 +0000235
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000236static int pc87360_gpio_set(uint8_t gpio, int raise)
237{
238 static const int bankbase[] = {0, 4, 8, 10, 12};
239 int gpio_bank = gpio / 8;
240 int gpio_pin = gpio % 8;
241 uint16_t baseport;
Uwe Hermann43959702010-03-13 17:28:29 +0000242 uint8_t id, val;
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000243
Uwe Hermann43959702010-03-13 17:28:29 +0000244 if (gpio_bank > 4) {
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000245 fprintf(stderr, "PC87360: Invalid GPIO %d\n", gpio);
246 return -1;
247 }
248
249 id = sio_read(0x2E, 0x20);
Uwe Hermann43959702010-03-13 17:28:29 +0000250 if (id != 0xE1) {
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000251 fprintf(stderr, "PC87360: unexpected ID %02x\n", id);
252 return -1;
253 }
254
Uwe Hermann43959702010-03-13 17:28:29 +0000255 sio_write(0x2E, 0x07, 0x07); /* Select GPIO device */
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000256 baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
Uwe Hermann43959702010-03-13 17:28:29 +0000257 if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) {
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000258 fprintf (stderr, "PC87360: invalid GPIO base address %04x\n",
259 baseport);
260 return -1;
261 }
262 sio_mask (0x2E, 0x30, 0x01, 0x01); /* Enable logical device */
Uwe Hermann43959702010-03-13 17:28:29 +0000263 sio_write(0x2E, 0xF0, gpio_bank * 16 + gpio_pin);
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000264 sio_mask (0x2E, 0xF1, 0x01, 0x01); /* Make pin output */
265
266 val = INB(baseport + bankbase[gpio_bank]);
Uwe Hermann43959702010-03-13 17:28:29 +0000267 if (raise)
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000268 val |= 1 << gpio_pin;
269 else
270 val &= ~(1 << gpio_pin);
271 OUTB(val, baseport + bankbase[gpio_bank]);
272
273 return 0;
274}
275
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000276/**
277 * VT823x: Set one of the GPIO pins.
278 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000279static int via_vt823x_gpio_set(uint8_t gpio, int raise)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000280{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000281 struct pci_dev *dev;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000282 uint16_t base;
David Bartleyf58d3642009-12-09 07:53:01 +0000283 uint8_t val, bit, offset;
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000284
Luc Verhaegen73d21192009-12-23 00:54:26 +0000285 dev = pci_dev_find_vendorclass(0x1106, 0x0601);
286 switch (dev->device_id) {
287 case 0x3177: /* VT8235 */
288 case 0x3227: /* VT8237R */
289 case 0x3337: /* VT8237A */
290 break;
291 default:
292 fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n");
293 return -1;
294 }
295
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000296 if ((gpio >= 12) && (gpio <= 15)) {
297 /* GPIO12-15 -> output */
298 val = pci_read_byte(dev, 0xE4);
299 val |= 0x10;
300 pci_write_byte(dev, 0xE4, val);
301 } else if (gpio == 9) {
302 /* GPIO9 -> Output */
303 val = pci_read_byte(dev, 0xE4);
304 val |= 0x20;
305 pci_write_byte(dev, 0xE4, val);
David Bartleyf58d3642009-12-09 07:53:01 +0000306 } else if (gpio == 5) {
307 val = pci_read_byte(dev, 0xE4);
308 val |= 0x01;
309 pci_write_byte(dev, 0xE4, val);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000310 } else {
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000311 fprintf(stderr, "\nERROR: "
312 "VT823x GPIO%02d is not implemented.\n", gpio);
Luc Verhaegen73d21192009-12-23 00:54:26 +0000313 return -1;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000314 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000315
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000316 /* We need the I/O Base Address for this board's flash enable. */
317 base = pci_read_word(dev, 0x88) & 0xff80;
318
David Bartleyf58d3642009-12-09 07:53:01 +0000319 offset = 0x4C + gpio / 8;
320 bit = 0x01 << (gpio % 8);
321
322 val = INB(base + offset);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000323 if (raise)
324 val |= bit;
325 else
326 val &= ~bit;
David Bartleyf58d3642009-12-09 07:53:01 +0000327 OUTB(val, base + offset);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000328
Uwe Hermanna7e05482007-05-09 10:17:44 +0000329 return 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000330}
331
Uwe Hermannffec5f32007-08-23 16:08:21 +0000332/**
Luc Verhaegen73d21192009-12-23 00:54:26 +0000333 * Suited for Asus M2V-MX: VIA K8M890 + VT8237A + IT8716F
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000334 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000335static int via_vt823x_gpio5_raise(const char *name)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000336{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000337 /* On M2V-MX: GPO5 is connected to WP# and TBL#. */
338 return via_vt823x_gpio_set(5, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000339}
340
341/**
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000342 * Suited for VIAs EPIA N & NL.
343 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000344static int via_vt823x_gpio9_raise(const char *name)
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000345{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000346 return via_vt823x_gpio_set(9, 1);
Jon Harrison2eeff4e2009-06-19 13:53:59 +0000347}
348
349/**
Luc Verhaegen73d21192009-12-23 00:54:26 +0000350 * Suited for VIAs EPIA M and MII, and maybe other CLE266 based EPIAs.
351 *
352 * We don't need to do this for EPIA M when using coreboot, GPIO15 is never
353 * lowered there.
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000354 */
Luc Verhaegen73d21192009-12-23 00:54:26 +0000355static int via_vt823x_gpio15_raise(const char *name)
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000356{
Luc Verhaegen73d21192009-12-23 00:54:26 +0000357 return via_vt823x_gpio_set(15, 1);
358}
359
360/**
361 * Winbond W83697HF Super I/O + VIA VT8235 southbridge
362 *
363 * Suited for:
364 * - MSI KT4V and KT4V-L: AMD K7 + VIA KT400 + VT8235
365 * - MSI KT4 Ultra: AMD K7 + VIA KT400 + VT8235
366 */
367static int board_msi_kt4v(const char *name)
368{
369 int ret;
370
371 ret = via_vt823x_gpio_set(12, 1);
Luc Verhaegenadd6d9b2009-05-09 14:26:04 +0000372 w836xx_memw_enable(0x2E);
Luc Verhaegen97866082008-02-09 02:03:06 +0000373
Luc Verhaegen73d21192009-12-23 00:54:26 +0000374 return ret;
Luc Verhaegen97866082008-02-09 02:03:06 +0000375}
376
377/**
Luc Verhaegen6b141752007-05-20 16:16:13 +0000378 * Suited for ASUS P5A.
379 *
380 * This is rather nasty code, but there's no way to do this cleanly.
381 * We're basically talking to some unknown device on SMBus, my guess
382 * is that it is the Winbond W83781D that lives near the DIP BIOS.
383 */
Luc Verhaegen6b141752007-05-20 16:16:13 +0000384static int board_asus_p5a(const char *name)
385{
386 uint8_t tmp;
387 int i;
388
389#define ASUSP5A_LOOP 5000
390
Andriy Gapon65c1b862008-05-22 13:22:45 +0000391 OUTB(0x00, 0xE807);
392 OUTB(0xEF, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000393
Andriy Gapon65c1b862008-05-22 13:22:45 +0000394 OUTB(0xFF, 0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000395
396 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000397 OUTB(0xE1, 0xFF);
398 if (INB(0xE800) & 0x04)
Luc Verhaegen6b141752007-05-20 16:16:13 +0000399 break;
400 }
401
402 if (i == ASUSP5A_LOOP) {
403 printf("%s: Unable to contact device.\n", name);
404 return -1;
405 }
406
Andriy Gapon65c1b862008-05-22 13:22:45 +0000407 OUTB(0x20, 0xE801);
408 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000409
Andriy Gapon65c1b862008-05-22 13:22:45 +0000410 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000411
412 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000413 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000414 if (tmp & 0x70)
415 break;
416 }
417
418 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
419 printf("%s: failed to read device.\n", name);
420 return -1;
421 }
422
Andriy Gapon65c1b862008-05-22 13:22:45 +0000423 tmp = INB(0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000424 tmp &= ~0x02;
425
Andriy Gapon65c1b862008-05-22 13:22:45 +0000426 OUTB(0x00, 0xE807);
427 OUTB(0xEE, 0xE803);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000428
Andriy Gapon65c1b862008-05-22 13:22:45 +0000429 OUTB(tmp, 0xE804);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000430
Andriy Gapon65c1b862008-05-22 13:22:45 +0000431 OUTB(0xFF, 0xE800);
432 OUTB(0xE1, 0xFF);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000433
Andriy Gapon65c1b862008-05-22 13:22:45 +0000434 OUTB(0x20, 0xE801);
435 OUTB(0x20, 0xE1);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000436
Andriy Gapon65c1b862008-05-22 13:22:45 +0000437 OUTB(0xFF, 0xE802);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000438
439 for (i = 0; i < ASUSP5A_LOOP; i++) {
Andriy Gapon65c1b862008-05-22 13:22:45 +0000440 tmp = INB(0xE800);
Luc Verhaegen6b141752007-05-20 16:16:13 +0000441 if (tmp & 0x70)
442 break;
443 }
444
445 if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
446 printf("%s: failed to write to device.\n", name);
447 return -1;
448 }
449
450 return 0;
451}
452
Luc Verhaegena7e30502009-12-09 11:39:02 +0000453/*
454 * Set GPIO lines in the Broadcom HT-1000 southbridge.
455 *
456 * It's not a Super I/O but it uses the same index/data port method.
457 */
458static int board_hp_dl145_g3_enable(const char *name)
459{
460 /* GPIO 0 reg from PM regs */
461 /* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
462 sio_mask(0xcd6, 0x44, 0x24, 0x24);
463
464 return 0;
465}
466
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000467static int board_ibm_x3455(const char *name)
468{
Luc Verhaegena7e30502009-12-09 11:39:02 +0000469 /* raise gpio13 */
Carl-Daniel Hailfinger500b4232009-06-01 21:30:42 +0000470 sio_mask(0xcd6, 0x45, 0x20, 0x20);
Stefan Reinauer1c283f42007-06-05 12:51:52 +0000471
472 return 0;
473}
474
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000475/**
Luc Verhaegen20fdce12009-10-21 12:05:50 +0000476 * Suited for Shuttle FN25 (SN25P): AMD S939 + Nvidia CK804 (nForce4).
477 */
478static int board_shuttle_fn25(const char *name)
479{
480 struct pci_dev *dev;
481
482 dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA Bridge. */
483 if (!dev) {
484 fprintf(stderr,
485 "\nERROR: NVIDIA nForce4 ISA bridge not found.\n");
486 return -1;
487 }
488
489 /* one of those bits seems to be connected to TBL#, but -ENOINFO. */
490 pci_write_byte(dev, 0x92, 0);
491
492 return 0;
493}
494
495/**
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000496 * Very similar to AMD 8111 IO Hub.
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000497 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000498static int nvidia_mcp_gpio_set(int gpio, int raise)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000499{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000500 struct pci_dev *dev;
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000501 uint16_t base;
502 uint8_t tmp;
503
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000504 if ((gpio < 0) || (gpio >= 0x40)) {
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000505 fprintf(stderr, "\nERROR: unsupported GPIO: %d.\n", gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000506 return -1;
507 }
508
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000509 /* First, check the ISA Bridge */
510 dev = pci_dev_find_vendorclass(0x10DE, 0x0601);
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000511 switch (dev->device_id) {
512 case 0x0030: /* CK804 */
513 case 0x0050: /* MCP04 */
514 case 0x0060: /* MCP2 */
515 break;
516 default:
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000517 /* Newer MCPs use the SMBus Controller */
518 dev = pci_dev_find_vendorclass(0x10DE, 0x0C05);
519 switch (dev->device_id) {
520 case 0x0264: /* MCP51 */
521 break;
522 default:
523 fprintf(stderr,
524 "\nERROR: no nVidia LPC/SMBus controller found.\n");
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000525 return -1;
Luc Verhaegen23ebd752009-12-22 13:04:13 +0000526 }
527 break;
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000528 }
529
530 base = pci_read_long(dev, 0x64) & 0x0000FF00; /* System control area */
531 base += 0xC0;
532
533 tmp = INB(base + gpio);
534 tmp &= ~0x0F; /* null lower nibble */
535 tmp |= 0x04; /* gpio -> output. */
536 if (raise)
537 tmp |= 0x01;
538 OUTB(tmp, base + gpio);
Luc Verhaegen48f34c62009-06-03 07:50:39 +0000539
540 return 0;
541}
542
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000543/**
Michael Karcherb2184c12010-03-07 16:42:55 +0000544 * Suited for ASUS M2NBP-VM CSM: nVidia MCP51.
545 */
546static int nvidia_mcp_gpio0_raise(const char *name)
547{
548 return nvidia_mcp_gpio_set(0x00, 1);
549}
550
551/**
Luc Verhaegen6c5f7332009-12-23 03:01:36 +0000552 * Suited for MSI K8N Neo4: nVidia CK804.
Michael Karcher5fdf2702010-03-07 16:52:59 +0000553 * Suited for MSI K8N GM2-L: nVidia MCP51.
Luc Verhaegen6c5f7332009-12-23 03:01:36 +0000554 */
555static int nvidia_mcp_gpio2_raise(const char *name)
556{
557 return nvidia_mcp_gpio_set(0x02, 1);
558}
559
560/**
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000561 * Suited for ASUS P5ND2-SLI Deluxe: LGA775 + nForce4 SLI + MCP04.
562 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000563static int nvidia_mcp_gpio10_raise(const char *name)
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000564{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000565 return nvidia_mcp_gpio_set(0x10, 1);
566}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000567
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000568/**
569 * Suited for the Gigabyte GA-K8N-SLI: CK804 southbridge.
570 */
571static int nvidia_mcp_gpio21_raise(const char *name)
572{
573 return nvidia_mcp_gpio_set(0x21, 0x01);
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000574}
575
Luc Verhaegen2c04fab2009-10-05 18:46:35 +0000576/**
577 * Suited for EPoX EP-8RDA3+: Socket A + nForce2 Ultra 400 + MCP2.
578 */
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000579static int nvidia_mcp_gpio31_raise(const char *name)
Luc Verhaegen2c04fab2009-10-05 18:46:35 +0000580{
Luc Verhaegen96f88fb2009-12-03 12:25:34 +0000581 return nvidia_mcp_gpio_set(0x31, 0x01);
Luc Verhaegen2c04fab2009-10-05 18:46:35 +0000582}
Luc Verhaegen8ff741e2009-10-05 16:07:00 +0000583
Luc Verhaegenfdd0c582007-08-11 16:59:11 +0000584/**
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000585 * Suited for Artec Group DBE61 and DBE62.
586 */
587static int board_artecgroup_dbe6x(const char *name)
588{
589#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
590#define DBE6x_PRI_BOOT_LOC_SHIFT (2)
591#define DBE6x_BOOT_OP_LATCHED_SHIFT (8)
592#define DBE6x_SEC_BOOT_LOC_SHIFT (10)
593#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
594#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
595#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
596#define DBE6x_BOOT_LOC_FLASH (2)
597#define DBE6x_BOOT_LOC_FWHUB (3)
598
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000599 msr_t msr;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000600 unsigned long boot_loc;
601
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000602 /* Geode only has a single core */
603 if (setup_cpu_msr(0))
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000604 return -1;
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000605
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000606 msr = rdmsr(DBE6x_MSR_DIVIL_BALL_OPTS);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000607
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000608 if ((msr.lo & (DBE6x_BOOT_OP_LATCHED)) ==
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000609 (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
610 boot_loc = DBE6x_BOOT_LOC_FWHUB;
611 else
612 boot_loc = DBE6x_BOOT_LOC_FLASH;
613
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000614 msr.lo &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
615 msr.lo |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
Uwe Hermann394131e2008-10-18 21:14:13 +0000616 (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000617
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000618 wrmsr(DBE6x_MSR_DIVIL_BALL_OPTS, msr);
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000619
Stefan Reinauerb4fe6642009-08-12 18:25:24 +0000620 cleanup_cpu_msr();
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000621
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000622 return 0;
623}
624
Uwe Hermann93f66db2008-05-22 21:19:38 +0000625/**
Luc Verhaegenf5226912009-12-14 10:41:58 +0000626 * Helper function to raise/drop a given gpo line on intel PIIX4{,E,M}
627 */
628static int intel_piix4_gpo_set(unsigned int gpo, int raise)
629{
Michael Karcher01f6d7d2010-02-24 00:00:21 +0000630 unsigned int gpo_byte, gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +0000631 struct pci_dev *dev;
632 uint32_t tmp, base;
633
634 dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */
635 if (!dev) {
636 fprintf(stderr, "\nERROR: Intel PIIX4 ISA bridge not found.\n");
637 return -1;
638 }
639
640 /* sanity check */
641 if (gpo > 30) {
642 fprintf(stderr, "\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);
643 return -1;
644 }
645
646 /* these are dual function pins which are most likely in use already */
647 if (((gpo >= 1) && (gpo <= 7)) ||
648 ((gpo >= 9) && (gpo <= 21)) || (gpo == 29)) {
649 fprintf(stderr, "\nERROR: Unsupported PIIX4 GPO%d.\n", gpo);
650 return -1;
651 }
652
653 /* dual function that need special enable. */
654 if ((gpo >= 22) && (gpo <= 26)) {
655 tmp = pci_read_long(dev, 0xB0); /* GENCFG */
656 switch (gpo) {
657 case 22: /* XBUS: XDIR#/GPO22 */
658 case 23: /* XBUS: XOE#/GPO23 */
659 tmp |= 1 << 28;
660 break;
661 case 24: /* RTCSS#/GPO24 */
662 tmp |= 1 << 29;
663 break;
664 case 25: /* RTCALE/GPO25 */
665 tmp |= 1 << 30;
666 break;
667 case 26: /* KBCSS#/GPO26 */
668 tmp |= 1 << 31;
669 break;
670 }
671 pci_write_long(dev, 0xB0, tmp);
672 }
673
674 /* GPO {0,8,27,28,30} are always available. */
675
676 dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */
677 if (!dev) {
678 fprintf(stderr, "\nERROR: Intel PIIX4 PM not found.\n");
679 return -1;
680 }
681
682 /* PM IO base */
683 base = pci_read_long(dev, 0x40) & 0x0000FFC0;
684
Michael Karcher01f6d7d2010-02-24 00:00:21 +0000685 gpo_byte = gpo >> 3;
686 gpo_bit = gpo & 7;
687 tmp = INB(base + 0x34 + gpo_byte); /* GPO register */
Luc Verhaegenf5226912009-12-14 10:41:58 +0000688 if (raise)
Michael Karcher01f6d7d2010-02-24 00:00:21 +0000689 tmp |= 0x01 << gpo_bit;
Luc Verhaegenf5226912009-12-14 10:41:58 +0000690 else
Michael Karcher01f6d7d2010-02-24 00:00:21 +0000691 tmp &= ~(0x01 << gpo_bit);
692 OUTB(tmp, base + 0x34 + gpo_byte);
Luc Verhaegenf5226912009-12-14 10:41:58 +0000693
694 return 0;
695}
696
697/**
698 * Suited for EPoX EP-BX3, and maybe some other Intel 440BX based boards.
699 */
700static int board_epox_ep_bx3(const char *name)
701{
702 return intel_piix4_gpo_set(22, 1);
703}
704
705/**
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000706 * Set a GPIO line on a given intel ICH LPC controller.
Uwe Hermann93f66db2008-05-22 21:19:38 +0000707 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000708static int intel_ich_gpio_set(int gpio, int raise)
Uwe Hermann93f66db2008-05-22 21:19:38 +0000709{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000710 /* table mapping the different intel ICH LPC chipsets. */
711 static struct {
712 uint16_t id;
713 uint8_t base_reg;
714 uint32_t bank0;
715 uint32_t bank1;
716 uint32_t bank2;
717 } intel_ich_gpio_table[] = {
718 {0x2410, 0x58, 0x0FE30000, 0, 0}, /* 82801AA (ICH) */
719 {0x2420, 0x58, 0x0FE30000, 0, 0}, /* 82801AB (ICH0) */
720 {0x2440, 0x58, 0x1BFF391B, 0, 0}, /* 82801BA (ICH2) */
721 {0x244C, 0x58, 0x1A23399B, 0, 0}, /* 82801BAM (ICH2M) */
722 {0x2450, 0x58, 0x1BFF0000, 0, 0}, /* 82801E (C-ICH) */
723 {0x2480, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801CA (ICH3-S) */
724 {0x248C, 0x58, 0x1A230000, 0x00000FFF, 0}, /* 82801CAM (ICH3-M) */
725 {0x24C0, 0x58, 0x1BFF0000, 0x00000FFF, 0}, /* 82801DB/DBL (ICH4/ICH4-L) */
726 {0x24CC, 0x58, 0x1A030000, 0x00000FFF, 0}, /* 82801DBM (ICH4-M) */
727 {0x24D0, 0x58, 0x1BFF0000, 0x00030305, 0}, /* 82801EB/ER (ICH5/ICH5R) */
728 {0x2640, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FB/FR (ICH6/ICH6R) */
729 {0x2641, 0x48, 0x1BFF0000, 0x00030307, 0}, /* 82801FBM (ICH6M) */
730 {0x27B8, 0x48, 0xFFFFFFFF, 0x000300FF, 0}, /* 82801GB/GR (ICH7 Family) */
731 {0x27B9, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GBM (ICH7-M) */
732 {0x27BD, 0x48, 0xFFEBFFFE, 0x000300FE, 0}, /* 82801GHM (ICH7-M DH) */
733 {0x2810, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HB/HR (ICH8/R) */
734 {0x2811, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HBM (ICH8M-E) */
735 {0x2812, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HH (ICH8DH) */
736 {0x2814, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HO (ICH8DO) */
737 {0x2815, 0x48, 0xFFFFFFFF, 0x00FF0FFF, 0}, /* 82801HEM (ICH8M) */
738 {0x2912, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IH (ICH9DH) */
739 {0x2914, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IO (ICH9DO) */
740 {0x2916, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IR (ICH9R) */
741 {0x2917, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IEM (ICH9M-E) */
742 {0x2918, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IB (ICH9) */
743 {0x2919, 0x48, 0xFFFFFFFF, 0x00FFFFFF, 0}, /* 82801IBM (ICH9M) */
744 {0x3A14, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JDO (ICH10DO) */
745 {0x3A16, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIR (ICH10R) */
746 {0x3A18, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JIB (ICH10) */
747 {0x3A1A, 0x48, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000100}, /* 82801JD (ICH10D) */
748 {0, 0, 0, 0, 0} /* end marker */
749 };
Uwe Hermann93f66db2008-05-22 21:19:38 +0000750
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000751 struct pci_dev *dev;
752 uint16_t base;
753 uint32_t tmp;
754 int i, allowed;
755
756 /* First, look for a known LPC bridge */
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +0000757 for (dev = pacc->devices; dev; dev = dev->next) {
758 pci_fill_info(dev, PCI_FILL_CLASS);
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000759 if ((dev->vendor_id == 0x8086) &&
760 (dev->device_class == 0x0601)) { /* ISA Bridge */
761 /* Is this device in our list? */
762 for (i = 0; intel_ich_gpio_table[i].id; i++)
763 if (dev->device_id == intel_ich_gpio_table[i].id)
764 break;
765
766 if (intel_ich_gpio_table[i].id)
767 break;
768 }
Jonathan A. Kollaschb87f23b2009-12-14 04:24:42 +0000769 }
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000770
Uwe Hermann93f66db2008-05-22 21:19:38 +0000771 if (!dev) {
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000772 fprintf(stderr, "\nERROR: No Known Intel LPC Bridge found.\n");
Uwe Hermann93f66db2008-05-22 21:19:38 +0000773 return -1;
774 }
775
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000776 /* According to the datasheets, all intel ICHs have the gpio bar 5:1
777 strapped to zero. From some mobile ich9 version on, this becomes
778 6:1. The mask below catches all. */
779 base = pci_read_word(dev, intel_ich_gpio_table[i].base_reg) & 0xFFC0;
Uwe Hermann93f66db2008-05-22 21:19:38 +0000780
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000781 /* check whether the line is allowed */
782 if (gpio < 32)
783 allowed = (intel_ich_gpio_table[i].bank0 >> gpio) & 0x01;
784 else if (gpio < 64)
785 allowed = (intel_ich_gpio_table[i].bank1 >> (gpio - 32)) & 0x01;
786 else
787 allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;
788
789 if (!allowed) {
790 fprintf(stderr, "\nERROR: This Intel LPC Bridge does not allow"
791 " setting GPIO%02d\n", gpio);
792 return -1;
793 }
794
795 printf("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n",
796 raise ? "Rais" : "Dropp", gpio);
797
798 if (gpio < 32) {
799 /* Set line to GPIO */
800 tmp = INL(base);
801 /* ICH/ICH0 multiplexes 27/28 on the line set. */
802 if ((gpio == 28) &&
803 ((dev->device_id == 0x2410) || (dev->device_id == 0x2420)))
804 tmp |= 1 << 27;
805 else
806 tmp |= 1 << gpio;
807 OUTL(tmp, base);
808
809 /* As soon as we are talking to ICH8 and above, this register
810 decides whether we can set the gpio or not. */
811 if (dev->device_id > 0x2800) {
812 tmp = INL(base);
813 if (!(tmp & (1 << gpio))) {
814 fprintf(stderr, "\nERROR: This Intel LPC Bridge"
815 " does not allow setting GPIO%02d\n",
816 gpio);
817 return -1;
818 }
819 }
820
821 /* Set GPIO to OUTPUT */
822 tmp = INL(base + 0x04);
823 tmp &= ~(1 << gpio);
824 OUTL(tmp, base + 0x04);
825
826 /* Raise GPIO line */
827 tmp = INL(base + 0x0C);
828 if (raise)
829 tmp |= 1 << gpio;
830 else
831 tmp &= ~(1 << gpio);
832 OUTL(tmp, base + 0x0C);
833 } else if (gpio < 64) {
834 gpio -= 32;
835
836 /* Set line to GPIO */
837 tmp = INL(base + 0x30);
838 tmp |= 1 << gpio;
839 OUTL(tmp, base + 0x30);
840
841 /* As soon as we are talking to ICH8 and above, this register
842 decides whether we can set the gpio or not. */
843 if (dev->device_id > 0x2800) {
844 tmp = INL(base + 30);
845 if (!(tmp & (1 << gpio))) {
846 fprintf(stderr, "\nERROR: This Intel LPC Bridge"
847 " does not allow setting GPIO%02d\n",
848 gpio + 32);
849 return -1;
850 }
851 }
852
853 /* Set GPIO to OUTPUT */
854 tmp = INL(base + 0x34);
855 tmp &= ~(1 << gpio);
856 OUTL(tmp, base + 0x34);
857
858 /* Raise GPIO line */
859 tmp = INL(base + 0x38);
860 if (raise)
861 tmp |= 1 << gpio;
862 else
863 tmp &= ~(1 << gpio);
864 OUTL(tmp, base + 0x38);
865 } else {
866 gpio -= 64;
867
868 /* Set line to GPIO */
869 tmp = INL(base + 0x40);
870 tmp |= 1 << gpio;
871 OUTL(tmp, base + 0x40);
872
873 tmp = INL(base + 40);
874 if (!(tmp & (1 << gpio))) {
875 fprintf(stderr, "\nERROR: This Intel LPC Bridge does "
876 "not allow setting GPIO%02d\n", gpio + 64);
877 return -1;
878 }
879
880 /* Set GPIO to OUTPUT */
881 tmp = INL(base + 0x44);
882 tmp &= ~(1 << gpio);
883 OUTL(tmp, base + 0x44);
884
885 /* Raise GPIO line */
886 tmp = INL(base + 0x48);
887 if (raise)
888 tmp |= 1 << gpio;
889 else
890 tmp &= ~(1 << gpio);
891 OUTL(tmp, base + 0x48);
892 }
Uwe Hermann93f66db2008-05-22 21:19:38 +0000893
894 return 0;
895}
896
897/**
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000898 * Suited for Abit IP35: Intel P35 + ICH9R.
Michael Karcherb4a3d1c2010-03-03 16:15:12 +0000899 * Suited for Abit IP35 Pro: Intel P35 + ICH9R.
Uwe Hermann93f66db2008-05-22 21:19:38 +0000900 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000901static int intel_ich_gpio16_raise(const char *name)
Uwe Hermann93f66db2008-05-22 21:19:38 +0000902{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000903 return intel_ich_gpio_set(16, 1);
Uwe Hermann93f66db2008-05-22 21:19:38 +0000904}
905
Peter Stuge09c13332009-02-02 22:55:26 +0000906/**
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000907 * Suited for MSI MS-7046: LGA775 + 915P + ICH6.
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +0000908 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000909static int intel_ich_gpio19_raise(const char *name)
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +0000910{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000911 return intel_ich_gpio_set(19, 1);
Carl-Daniel Hailfinger29124262009-09-23 02:05:12 +0000912}
913
914/**
Luc Verhaegen6c5d4cc2009-11-28 18:26:21 +0000915 * Suited for:
916 * - Asus P4B266LM (Sony Vaio PCV-RX650): socket478 + 845D + ICH2.
917 * - Asus P4P800-E Deluxe: Intel socket478 + 865PE + ICH5R.
Peter Stuge09c13332009-02-02 22:55:26 +0000918 */
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000919static int intel_ich_gpio21_raise(const char *name)
Peter Stuge09c13332009-02-02 22:55:26 +0000920{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000921 return intel_ich_gpio_set(21, 1);
Peter Stuge09c13332009-02-02 22:55:26 +0000922}
923
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000924/**
Michael Karcher03b80e92010-03-07 16:32:32 +0000925 * Suited for:
926 * - Asus P4B266: socket478 + intel 845D + ICH2.
927 * - Asus P4B-MX variant in HP Vectra VL420 SFF: socket478 + 845D + ICH2
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000928 */
929static int intel_ich_gpio22_raise(const char *name)
930{
931 return intel_ich_gpio_set(22, 1);
932}
933
934/**
Michael Karcher5fbd18d2010-02-27 18:35:54 +0000935 * Suited for HP Vectra VL400: 815 + ICH + PC87360.
936 */
937
938static int board_hp_vl400(const char *name)
939{
940 int ret;
941 ret = intel_ich_gpio_set(25, 1); /* Master write enable ? */
942 if (!ret)
943 ret = pc87360_gpio_set(0x09, 1); /* #WP ? */
944 if (!ret)
945 ret = pc87360_gpio_set(0x27, 1); /* #TBL */
946 return ret;
947}
948
949/**
Luc Verhaegen1265d8d2009-11-28 18:16:31 +0000950 * Suited for:
951 * - Dell Poweredge 1850: Intel PPGA604 + E7520 + ICH5R.
952 * - ASRock P4i65GV: Intel Socket478 + 865GV + ICH5R.
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000953 */
954static int intel_ich_gpio23_raise(const char *name)
955{
956 return intel_ich_gpio_set(23, 1);
957}
958
959/**
960 * Suited for Acorp 6A815EPD: socket 370 + intel 815 + ICH2.
961 */
962static int board_acorp_6a815epd(const char *name)
963{
964 int ret;
965
966 /* Lower Blocks Lock -- pin 7 of PLCC32 */
967 ret = intel_ich_gpio_set(22, 1);
968 if (!ret) /* Top Block Lock -- pin 8 of PLCC32 */
969 ret = intel_ich_gpio_set(23, 1);
970
971 return ret;
972}
973
974/**
975 * Suited for Kontron 986LCD-M: socket478 + 915GM + ICH7R.
976 */
Stefan Reinauerac378972008-03-17 22:59:40 +0000977static int board_kontron_986lcd_m(const char *name)
978{
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000979 int ret;
Stefan Reinauerac378972008-03-17 22:59:40 +0000980
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000981 ret = intel_ich_gpio_set(34, 1); /* #TBL */
982 if (!ret)
983 ret = intel_ich_gpio_set(35, 1); /* #WP */
Stefan Reinauerac378972008-03-17 22:59:40 +0000984
Luc Verhaegen60ea7dc2009-11-28 18:07:51 +0000985 return ret;
Stefan Reinauerac378972008-03-17 22:59:40 +0000986}
987
Mart Raudseppfaa62fb2008-02-20 11:11:18 +0000988/**
Luc Verhaegen3920eda2009-06-17 14:43:24 +0000989 * Suited for Soyo SY-7VCA: Pro133A + VT82C686.
990 */
991static int board_soyo_sy_7vca(const char *name)
992{
993 struct pci_dev *dev;
994 uint32_t base;
995 uint8_t tmp;
996
997 /* VT82C686 Power management */
998 dev = pci_dev_find(0x1106, 0x3057);
999 if (!dev) {
1000 fprintf(stderr, "\nERROR: VT82C686 PM device not found.\n");
1001 return -1;
1002 }
1003
1004 /* GPO0 output from PM IO base + 0x4C */
1005 tmp = pci_read_byte(dev, 0x54);
1006 tmp &= ~0x03;
1007 pci_write_byte(dev, 0x54, tmp);
1008
1009 /* PM IO base */
1010 base = pci_read_long(dev, 0x48) & 0x0000FF00;
1011
1012 /* Drop GPO0 */
1013 tmp = INB(base + 0x4C);
1014 tmp &= ~0x01;
1015 OUTB(tmp, base + 0x4C);
1016
1017 return 0;
1018}
1019
Michael Karcher9f9e6132010-01-09 17:36:06 +00001020/**
1021 * Enable some GPIO pin on SiS southbridge.
1022 * Suited for MSI 651M-L: SiS651 / SiS962
1023 */
1024static int board_msi_651ml(const char *name)
1025{
1026 struct pci_dev *dev;
Uwe Hermann43959702010-03-13 17:28:29 +00001027 uint16_t base, temp;
Michael Karcher9f9e6132010-01-09 17:36:06 +00001028
1029 dev = pci_dev_find(0x1039, 0x0962);
1030 if (!dev) {
1031 fprintf(stderr, "Expected south bridge not found\n");
1032 return 1;
1033 }
1034
1035 /* Registers 68 and 64 seem like bitmaps */
1036 base = pci_read_word(dev, 0x74);
1037 temp = INW(base + 0x68);
1038 temp &= ~(1 << 0); /* Make pin output? */
Michael Karcher0435dfd2010-01-09 23:31:13 +00001039 OUTW(temp, base + 0x68);
Michael Karcher9f9e6132010-01-09 17:36:06 +00001040
1041 temp = INW(base + 0x64);
1042 temp |= (1 << 0); /* Raise output? */
1043 OUTW(temp, base + 0x64);
1044
1045 w836xx_memw_enable(0x2E);
1046
1047 return 0;
1048}
1049
Luc Verhaegen3920eda2009-06-17 14:43:24 +00001050/**
Michael Gold6d52e472009-06-19 13:00:24 +00001051 * Find the runtime registers of an SMSC Super I/O, after verifying its
1052 * chip ID.
1053 *
1054 * Returns the base port of the runtime register block, or 0 on error.
1055 */
1056static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
1057 uint8_t logical_device)
1058{
1059 uint16_t rt_port = 0;
1060
1061 /* Verify the chip ID. */
Uwe Hermann1432a602009-06-28 23:26:37 +00001062 OUTB(0x55, sio_port); /* Enable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00001063 if (sio_read(sio_port, 0x20) != chip_id) {
Uwe Hermann1432a602009-06-28 23:26:37 +00001064 fprintf(stderr, "\nERROR: SMSC Super I/O not found.\n");
Michael Gold6d52e472009-06-19 13:00:24 +00001065 goto out;
1066 }
1067
1068 /* If the runtime block is active, get its address. */
1069 sio_write(sio_port, 0x07, logical_device);
1070 if (sio_read(sio_port, 0x30) & 1) {
1071 rt_port = (sio_read(sio_port, 0x60) << 8)
1072 | sio_read(sio_port, 0x61);
1073 }
1074
1075 if (rt_port == 0) {
1076 fprintf(stderr, "\nERROR: "
1077 "Super I/O runtime interface not available.\n");
1078 }
1079out:
Uwe Hermann1432a602009-06-28 23:26:37 +00001080 OUTB(0xaa, sio_port); /* Disable configuration. */
Michael Gold6d52e472009-06-19 13:00:24 +00001081 return rt_port;
1082}
1083
1084/**
1085 * Disable write protection on the Mitac 6513WU. WP# on the FWH is
1086 * connected to GP30 on the Super I/O, and TBL# is always high.
1087 */
1088static int board_mitac_6513wu(const char *name)
1089{
1090 struct pci_dev *dev;
1091 uint16_t rt_port;
1092 uint8_t val;
1093
1094 dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */
1095 if (!dev) {
1096 fprintf(stderr, "\nERROR: Intel 82801AA ISA bridge not found.\n");
1097 return -1;
1098 }
1099
Uwe Hermann1432a602009-06-28 23:26:37 +00001100 rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa);
Michael Gold6d52e472009-06-19 13:00:24 +00001101 if (rt_port == 0)
1102 return -1;
1103
1104 /* Configure the GPIO pin. */
1105 val = INB(rt_port + 0x33); /* GP30 config */
Uwe Hermann1432a602009-06-28 23:26:37 +00001106 val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */
Michael Gold6d52e472009-06-19 13:00:24 +00001107 OUTB(val, rt_port + 0x33);
1108
1109 /* Disable write protection. */
1110 val = INB(rt_port + 0x4d); /* GP3 values */
Uwe Hermann1432a602009-06-28 23:26:37 +00001111 val |= 0x01; /* Set GP30 high. */
Michael Gold6d52e472009-06-19 13:00:24 +00001112 OUTB(val, rt_port + 0x4d);
1113
1114 return 0;
1115}
1116
1117/**
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001118 * Suited for Asus A7V8X: VIA KT400 + VT8235 + IT8703F-A
1119 */
1120static int board_asus_a7v8x(const char *name)
1121{
1122 uint16_t id, base;
1123 uint8_t tmp;
1124
1125 /* find the IT8703F */
1126 w836xx_ext_enter(0x2E);
1127 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
1128 w836xx_ext_leave(0x2E);
1129
1130 if (id != 0x8701) {
Uwe Hermann43959702010-03-13 17:28:29 +00001131 fprintf(stderr, "\nERROR: IT8703F Super I/O not found.\n");
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001132 return -1;
1133 }
1134
1135 /* Get the GP567 IO base */
1136 w836xx_ext_enter(0x2E);
1137 sio_write(0x2E, 0x07, 0x0C);
1138 base = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
1139 w836xx_ext_leave(0x2E);
1140
1141 if (!base) {
Uwe Hermann43959702010-03-13 17:28:29 +00001142 fprintf(stderr, "\nERROR: Failed to read IT8703F Super I/O GPIO"
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001143 " Base.\n");
1144 return -1;
1145 }
1146
1147 /* Raise GP51. */
1148 tmp = INB(base);
1149 tmp |= 0x02;
1150 OUTB(tmp, base);
1151
1152 return 0;
1153}
1154
Luc Verhaegen72272912009-09-01 21:22:23 +00001155/*
1156 * General routine for raising/dropping GPIO lines on the ITE IT8712F.
1157 * There is only some limited checking on the port numbers.
1158 */
Uwe Hermann43959702010-03-13 17:28:29 +00001159static int it8712f_gpio_set(unsigned int line, int raise)
Luc Verhaegen72272912009-09-01 21:22:23 +00001160{
1161 unsigned int port;
1162 uint16_t id, base;
1163 uint8_t tmp;
1164
1165 port = line / 10;
1166 port--;
1167 line %= 10;
1168
1169 /* Check line */
1170 if ((port > 4) || /* also catches unsigned -1 */
1171 ((port < 4) && (line > 7)) || ((port == 4) && (line > 5))) {
1172 fprintf(stderr,
1173 "\nERROR: Unsupported IT8712F GPIO Line %02d.\n", line);
1174 return -1;
1175 }
1176
1177 /* find the IT8712F */
1178 enter_conf_mode_ite(0x2E);
1179 id = (sio_read(0x2E, 0x20) << 8) | sio_read(0x2E, 0x21);
1180 exit_conf_mode_ite(0x2E);
1181
1182 if (id != 0x8712) {
Uwe Hermann43959702010-03-13 17:28:29 +00001183 fprintf(stderr, "\nERROR: IT8712F Super I/O not found.\n");
Luc Verhaegen72272912009-09-01 21:22:23 +00001184 return -1;
1185 }
1186
1187 /* Get the GPIO base */
1188 enter_conf_mode_ite(0x2E);
1189 sio_write(0x2E, 0x07, 0x07);
1190 base = (sio_read(0x2E, 0x62) << 8) | sio_read(0x2E, 0x63);
1191 exit_conf_mode_ite(0x2E);
1192
1193 if (!base) {
Uwe Hermann43959702010-03-13 17:28:29 +00001194 fprintf(stderr, "\nERROR: Failed to read IT8712F Super I/O GPIO"
Luc Verhaegen72272912009-09-01 21:22:23 +00001195 " Base.\n");
1196 return -1;
1197 }
1198
1199 /* set GPIO. */
1200 tmp = INB(base + port);
1201 if (raise)
1202 tmp |= 1 << line;
1203 else
1204 tmp &= ~(1 << line);
1205 OUTB(tmp, base + port);
1206
1207 return 0;
1208}
1209
1210/**
Russ Dillbd622d12010-03-09 16:57:06 +00001211 * Suited for:
1212 * - Asus A7V600-X: VIA KT600 + VT8237 + IT8712F
1213 * - Asus A7V8X-X: VIA KT400 + VT8235 + IT8712F
Luc Verhaegen72272912009-09-01 21:22:23 +00001214 */
Russ Dillbd622d12010-03-09 16:57:06 +00001215static int it8712f_gpio3_1_raise(const char *name)
Luc Verhaegen72272912009-09-01 21:22:23 +00001216{
1217 return it8712f_gpio_set(32, 1);
1218}
1219
Luc Verhaegen78e4e122009-07-13 12:40:17 +00001220/**
Uwe Hermannd0e347d2009-10-06 13:00:00 +00001221 * Below is the list of boards which need a special "board enable" code in
1222 * flashrom before their ROM chip can be accessed/written to.
1223 *
1224 * NOTE: Please add boards that _don't_ need such enables or don't work yet
1225 * to the respective tables in print.c. Thanks!
1226 *
Uwe Hermannffec5f32007-08-23 16:08:21 +00001227 * We use 2 sets of IDs here, you're free to choose which is which. This
1228 * is to provide a very high degree of certainty when matching a board on
1229 * the basis of subsystem/card IDs. As not every vendor handles
1230 * subsystem/card IDs in a sane manner.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001231 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00001232 * Keep the second set NULLed if it should be ignored. Keep the subsystem IDs
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00001233 * NULLed if they don't identify the board fully and if you can't use DMI.
1234 * But please take care to provide an as complete set of pci ids as possible;
1235 * autodetection is the preferred behaviour and we would like to make sure that
1236 * matches are unique.
Mart Raudseppfaa62fb2008-02-20 11:11:18 +00001237 *
Michael Karcher6701ee82010-01-20 14:14:11 +00001238 * If PCI IDs are not sufficient for board matching, the match can be further
1239 * constrained by a string that has to be present in the DMI database for
1240 * the baseboard or the system entry. The pattern is matched by case sensitve
1241 * substring match, unless it is anchored to the beginning (with a ^ in front)
1242 * or the end (with a $ at the end). Both anchors may be specified at the
1243 * same time to match the full field.
1244 *
Carl-Daniel Hailfinger7a788f52010-02-04 11:12:04 +00001245 * When a board is matched through DMI, the first and second main PCI IDs
1246 * and the first subsystem PCI ID have to match as well. If you specify the
1247 * first subsystem ID as 0x0:0x0, the DMI matching code expects that the
1248 * subsystem ID of that device is indeed zero.
1249 *
Luc Verhaegenc5210162009-04-20 12:38:17 +00001250 * The coreboot ids are used two fold. When running with a coreboot firmware,
1251 * the ids uniquely matches the coreboot board identification string. When a
1252 * legacy bios is installed and when autodetection is not possible, these ids
1253 * can be used to identify the board through the -m command line argument.
1254 *
1255 * When a board is identified through its coreboot ids (in both cases), the
1256 * main pci ids are still required to match, as a safeguard.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001257 */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001258
Uwe Hermanndeeebe22009-05-08 16:23:34 +00001259/* Please keep this list alphabetically ordered by vendor/board name. */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001260struct board_pciid_enable board_pciid_enables[] = {
Uwe Hermann5ab88892009-06-21 20:50:22 +00001261
Michael Karcher0bdc0922010-02-28 01:33:48 +00001262 /* first pci-id set [4], second pci-id set [4], dmi identifier coreboot id [2], vendor name board name max_rom_... OK? flash enable */
1263 {0x8086, 0x2926, 0x147b, 0x1084, 0x11ab, 0x4364, 0x147b, 0x1084, NULL, NULL, NULL, "Abit", "IP35", 0, OK, intel_ich_gpio16_raise},
Michael Karcherb4a3d1c2010-03-03 16:15:12 +00001264 {0x8086, 0x2930, 0x147b, 0x1083, 0x10ec, 0x8167, 0x147b, 0x1083, NULL, NULL, NULL, "Abit", "IP35 Pro", 0, OK, intel_ich_gpio16_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001265 {0x105a, 0x0d30, 0x105a, 0x4d33, 0x8086, 0x1130, 0x8086, 0, NULL, NULL, NULL, "Acorp", "6A815EPD", 0, OK, board_acorp_6a815epd},
1266 {0x8086, 0x24D4, 0x1849, 0x24D0, 0x8086, 0x24D5, 0x1849, 0x9739, NULL, NULL, NULL, "ASRock", "P4i65GV", 0, OK, intel_ich_gpio23_raise},
1267 {0x1022, 0x746B, 0, 0, 0, 0, 0, 0, NULL, "AGAMI", "ARUMA", "agami", "Aruma", 0, OK, w83627hf_gpio24_raise_2e},
1268 {0x1106, 0x3177, 0x17F2, 0x3177, 0x1106, 0x3148, 0x17F2, 0x3148, NULL, NULL, NULL, "Albatron", "PM266A", 0, OK, w836xx_memw_enable_2e},
1269 {0x1106, 0x3205, 0x1106, 0x3205, 0x10EC, 0x8139, 0xA0A0, 0x0477, NULL, NULL, NULL, "AOpen", "vKM400Am-S", 0, OK, it8705f_write_enable_2e},
1270 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe61", "Artec Group", "DBE61", 0, OK, board_artecgroup_dbe6x},
1271 {0x1022, 0x2090, 0, 0, 0x1022, 0x2080, 0, 0, NULL, "artecgroup", "dbe62", "Artec Group", "DBE62", 0, OK, board_artecgroup_dbe6x},
Russ Dillbd622d12010-03-09 16:57:06 +00001272 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3065, 0x1043, 0x80ED, NULL, NULL, NULL, "ASUS", "A7V600-X", 0, OK, it8712f_gpio3_1_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001273 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x808C, NULL, NULL, NULL, "ASUS", "A7V8X", 0, OK, board_asus_a7v8x},
Russ Dillbd622d12010-03-09 16:57:06 +00001274 {0x1106, 0x3189, 0x1043, 0x807F, 0x1106, 0x3177, 0x1043, 0x80A1, NULL, NULL, NULL, "ASUS", "A7V8X-X", 0, OK, it8712f_gpio3_1_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001275 {0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118, NULL, NULL, NULL, "ASUS", "A7V8X-MX SE", 0, OK, w836xx_memw_enable_2e},
Michael Karcherb2184c12010-03-07 16:42:55 +00001276 {0x10DE, 0x0264, 0x1043, 0x81C0, 0x10DE, 0x0260, 0x1043, 0x81C0, NULL, NULL, NULL, "ASUS", "M2NBP-VM CSM", 0, OK, nvidia_mcp_gpio0_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001277 {0x1106, 0x1336, 0x1043, 0x80ed, 0x1106, 0x3288, 0x1043, 0x8249, NULL, NULL, NULL, "ASUS", "M2V-MX", 0, OK, via_vt823x_gpio5_raise},
1278 {0x8086, 0x1a30, 0x1043, 0x8070, 0x8086, 0x244b, 0x1043, 0x8028, NULL, NULL, NULL, "ASUS", "P4B266", 0, OK, intel_ich_gpio22_raise},
1279 {0x8086, 0x1A30, 0x1043, 0x8025, 0x8086, 0x244B, 0x104D, 0x80F0, NULL, NULL, NULL, "ASUS", "P4B266-LM", 0, OK, intel_ich_gpio21_raise},
1280 {0x8086, 0x2570, 0x1043, 0x80F2, 0x105A, 0x3373, 0x1043, 0x80F5, NULL, NULL, NULL, "ASUS", "P4P800-E Deluxe", 0, OK, intel_ich_gpio21_raise},
1281 {0x10B9, 0x1541, 0, 0, 0x10B9, 0x1533, 0, 0, "^P5A$", "asus", "p5a", "ASUS", "P5A", 0, OK, board_asus_p5a},
1282 {0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", 0, OK, nvidia_mcp_gpio10_raise},
1283 {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, NULL, "Biostar", "P4M80-M4", 0, OK, it8705f_write_enable_2e},
1284 {0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, NULL, "Dell", "PowerEdge 1850", 0, OK, intel_ich_gpio23_raise},
1285 {0x1039, 0x5513, 0x1019, 0x0A41, 0x1039, 0x0018, 0, 0, NULL, NULL, NULL, "Elitegroup", "K7S6A", 0, OK, it8705f_write_enable_2e},
1286 {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, NULL, "Elitegroup", "K7VTA3", 256, OK, it8705f_write_enable_2e},
1287 {0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, NULL, "EPoX", "EP-8K5A2", 0, OK, w836xx_memw_enable_2e},
1288 {0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, NULL, "EPoX", "EP-8RDA3+", 0, OK, nvidia_mcp_gpio31_raise},
1289 {0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, NULL, "epox", "ep-bx3", "EPoX", "EP-BX3", 0, OK, board_epox_ep_bx3},
1290 {0x1106, 0x0686, 0x1106, 0x0686, 0x1106, 0x3058, 0x1458, 0xa000, NULL, NULL, NULL, "GIGABYTE", "GA-7ZM", 512, OK, NULL},
1291 {0x1039, 0x0761, 0, 0, 0x10EC, 0x8168, 0, 0, NULL, "gigabyte", "2761gxdk", "GIGABYTE", "GA-2761GXDK", 0, OK, it87xx_probe_spi_flash},
1292 {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000, NULL, NULL, NULL, "GIGABYTE", "GA-7VT600", 0, OK, it8705f_write_enable_2e},
1293 {0x10DE, 0x0050, 0x1458, 0x0C11, 0x10DE, 0x005e, 0x1458, 0x5000, NULL, NULL, NULL, "GIGABYTE", "GA-K8N-SLI", 0, OK, nvidia_mcp_gpio21_raise},
1294 {0x10DE, 0x0360, 0x1458, 0x0C11, 0x10DE, 0x0369, 0x1458, 0x5001, NULL, "gigabyte", "m57sli", "GIGABYTE", "GA-M57SLI-S4", 0, OK, it87xx_probe_spi_flash},
1295 {0x10de, 0x03e0, 0, 0, 0x10DE, 0x03D0, 0, 0, NULL, NULL, NULL, "GIGABYTE", "GA-M61P-S3", 0, OK, it87xx_probe_spi_flash},
Raúl Soriano8111e7f2010-03-14 00:00:14 +00001296 {0x1002, 0x7910, 0x1458, 0x5000, 0x1002, 0x438D, 0x1458, 0x5001, NULL, NULL, NULL, "GIGABYTE", "GA-MA69VM-S2", 0, OK, it87xx_probe_spi_flash},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001297 {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb000, NULL, NULL, NULL, "GIGABYTE", "GA-MA78G-DS3H", 0, OK, it87xx_probe_spi_flash},
1298 {0x1002, 0x4398, 0x1458, 0x5004, 0x1002, 0x4391, 0x1458, 0xb002, NULL, NULL, NULL, "GIGABYTE", "GA-MA78GM-S2H", 0, OK, it87xx_probe_spi_flash},
1299 {0x1002, 0x438d, 0x1458, 0x5001, 0x1002, 0x5956, 0x1002, 0x5956, NULL, NULL, NULL, "GIGABYTE", "GA-MA790FX-DQ6", 0, OK, it87xx_probe_spi_flash},
1300 {0x1166, 0x0223, 0x103c, 0x320d, 0x102b, 0x0522, 0x103c, 0x31fa, NULL, "hp", "dl145_g3", "HP", "DL145 G3", 0, OK, board_hp_dl145_g3_enable},
1301 {0x8086, 0x2415, 0x103c, 0x1249, 0x10b7, 0x9200, 0x103c, 0x1246, NULL, NULL, NULL, "HP", "Vectra VL400", 0, OK, board_hp_vl400},
Michael Karcher03b80e92010-03-07 16:32:32 +00001302 {0x8086, 0x1a30, 0x103c, 0x1a30, 0x8086, 0x2443, 0x103c, 0x2440, "^VL420$", NULL, NULL, "HP", "VL420 SFF", 0, OK, intel_ich_gpio22_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001303 {0x1166, 0x0205, 0x1014, 0x0347, 0x1002, 0x515E, 0x1014, 0x0325, NULL, NULL, NULL, "IBM", "x3455", 0, OK, board_ibm_x3455},
1304 {0x1039, 0x5513, 0x8086, 0xd61f, 0x1039, 0x6330, 0x8086, 0xd61f, NULL, NULL, NULL, "Intel", "D201GLY", 0, OK, wbsio_check_for_spi},
1305 {0x1022, 0x7468, 0, 0, 0, 0, 0, 0, NULL, "iwill", "dk8_htx", "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e},
1306 {0x8086, 0x27A0, 0, 0, 0x8086, 0x27b8, 0, 0, NULL, "kontron", "986lcd-m", "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m},
1307 {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, "Mitac", "6513WU", 0, OK, board_mitac_6513wu},
1308 {0x13f6, 0x0111, 0x1462, 0x5900, 0x1106, 0x3177, 0x1106, 0, NULL, NULL, NULL, "MSI", "MS-6590 (KT4 Ultra)", 0, OK, board_msi_kt4v},
1309 {0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c, NULL, NULL, NULL, "MSI", "MS-6702E (K8T Neo2-F)", 0, OK, w83627thf_gpio4_4_raise_2e},
1310 {0x1106, 0x0571, 0x1462, 0x7120, 0x1106, 0x3065, 0x1462, 0x7120, NULL, NULL, NULL, "MSI", "MS-6712 (KT4V)", 0, OK, board_msi_kt4v},
1311 {0x1039, 0x7012, 0x1462, 0x0050, 0x1039, 0x6325, 0x1462, 0x0058, NULL, NULL, NULL, "MSI", "MS-7005 (651M-L)", 0, OK, board_msi_651ml},
1312 {0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, NULL, "MSI", "MS-7046", 0, OK, intel_ich_gpio19_raise},
1313 {0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, NULL, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", 0, OK, w83627thf_gpio4_4_raise_4e},
Michael Karcher5fdf2702010-03-07 16:52:59 +00001314 {0x10DE, 0x0270, 0x1462, 0x7207, 0x10DE, 0x0264, 0x1462, 0x7207, NULL, NULL, NULL, "MSI", "MS-7207 (K8N GM2-L)", 0, NT, nvidia_mcp_gpio2_raise},
Michael Karcher0bdc0922010-02-28 01:33:48 +00001315 {0x10DE, 0x005E, 0x1462, 0x7125, 0x10DE, 0x0052, 0x1462, 0x7125, NULL, NULL, NULL, "MSI", "K8N Neo4-F", 0, OK, nvidia_mcp_gpio2_raise},
1316 {0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, NULL, "shuttle", "ak31", "Shuttle", "AK31", 0, OK, w836xx_memw_enable_2e},
1317 {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, NULL, "Shuttle", "AK38N", 256, OK, it8705f_write_enable_2e},
1318 {0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, NULL, "Shuttle", "FN25", 0, OK, board_shuttle_fn25},
1319 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, NULL, "Soyo", "SY-7VCA", 0, OK, board_soyo_sy_7vca},
1320 {0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", 0, OK, w836xx_memw_enable_2e},
1321 {0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x0596, 0x1106, 0, NULL, NULL, NULL, "Tekram", "P6Pro-A5", 256, OK, NULL},
1322 {0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01, NULL, NULL, NULL, "VIA", "EPIA M/MII/...", 0, OK, via_vt823x_gpio15_raise},
1323 {0x1106, 0x0259, 0x1106, 0x3227, 0x1106, 0x3065, 0x1106, 0x3149, NULL, NULL, NULL, "VIA", "EPIA-N/NL", 0, OK, via_vt823x_gpio9_raise},
1324 {0x1106, 0x5337, 0x1458, 0xb003, 0x1106, 0x287e, 0x1106, 0x337e, NULL, NULL, NULL, "VIA", "PC3500G", 0, OK, it87xx_probe_spi_flash},
Luc Verhaegen93938c32010-01-20 14:45:03 +00001325
Michael Karcher0bdc0922010-02-28 01:33:48 +00001326 { 0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, 0, NT, NULL}, /* end marker */
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001327};
1328
Uwe Hermannffec5f32007-08-23 16:08:21 +00001329/**
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00001330 * Match boards on coreboot table gathered vendor and part name.
Uwe Hermannffec5f32007-08-23 16:08:21 +00001331 * Require main PCI IDs to match too as extra safety.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001332 */
Uwe Hermann394131e2008-10-18 21:14:13 +00001333static struct board_pciid_enable *board_match_coreboot_name(const char *vendor,
1334 const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001335{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001336 struct board_pciid_enable *board = board_pciid_enables;
Peter Stuge6b53fed2008-01-27 16:21:21 +00001337 struct board_pciid_enable *partmatch = NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001338
Uwe Hermanna93045c2009-05-09 00:47:04 +00001339 for (; board->vendor_name; board++) {
Uwe Hermann394131e2008-10-18 21:14:13 +00001340 if (vendor && (!board->lb_vendor
1341 || strcasecmp(board->lb_vendor, vendor)))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001342 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001343
Peter Stuge0b9c5f32008-07-02 00:47:30 +00001344 if (!board->lb_part || strcasecmp(board->lb_part, part))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001345 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001346
Uwe Hermanna7e05482007-05-09 10:17:44 +00001347 if (!pci_dev_find(board->first_vendor, board->first_device))
1348 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001349
Uwe Hermanna7e05482007-05-09 10:17:44 +00001350 if (board->second_vendor &&
Uwe Hermann394131e2008-10-18 21:14:13 +00001351 !pci_dev_find(board->second_vendor, board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001352 continue;
Peter Stuge6b53fed2008-01-27 16:21:21 +00001353
1354 if (vendor)
1355 return board;
1356
1357 if (partmatch) {
1358 /* a second entry has a matching part name */
1359 printf("AMBIGUOUS BOARD NAME: %s\n", part);
1360 printf("At least vendors '%s' and '%s' match.\n",
Uwe Hermann394131e2008-10-18 21:14:13 +00001361 partmatch->lb_vendor, board->lb_vendor);
Peter Stuge6b53fed2008-01-27 16:21:21 +00001362 printf("Please use the full -m vendor:part syntax.\n");
1363 return NULL;
1364 }
1365 partmatch = board;
Uwe Hermanna7e05482007-05-09 10:17:44 +00001366 }
Uwe Hermann372eeb52007-12-04 21:49:06 +00001367
Peter Stuge6b53fed2008-01-27 16:21:21 +00001368 if (partmatch)
1369 return partmatch;
1370
Carl-Daniel Hailfingerbc25f942009-07-30 13:30:17 +00001371 if (!partvendor_from_cbtable) {
1372 /* Only warn if the mainboard type was not gathered from the
1373 * coreboot table. If it was, the coreboot implementor is
1374 * expected to fix flashrom, too.
1375 */
1376 printf("\nUnknown vendor:board from -m option: %s:%s\n\n",
1377 vendor, part);
1378 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00001379 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001380}
1381
Uwe Hermannffec5f32007-08-23 16:08:21 +00001382/**
1383 * Match boards on PCI IDs and subsystem IDs.
1384 * Second set of IDs can be main only or missing completely.
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001385 */
1386static struct board_pciid_enable *board_match_pci_card_ids(void)
1387{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001388 struct board_pciid_enable *board = board_pciid_enables;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001389
Uwe Hermanna93045c2009-05-09 00:47:04 +00001390 for (; board->vendor_name; board++) {
Michael Karcher2eab70d2010-02-04 10:58:50 +00001391 if ((!board->first_card_vendor || !board->first_card_device) &&
1392 !board->dmi_pattern)
Uwe Hermanna7e05482007-05-09 10:17:44 +00001393 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001394
Uwe Hermanna7e05482007-05-09 10:17:44 +00001395 if (!pci_card_find(board->first_vendor, board->first_device,
Uwe Hermann394131e2008-10-18 21:14:13 +00001396 board->first_card_vendor,
1397 board->first_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001398 continue;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001399
Uwe Hermanna7e05482007-05-09 10:17:44 +00001400 if (board->second_vendor) {
1401 if (board->second_card_vendor) {
1402 if (!pci_card_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00001403 board->second_device,
1404 board->second_card_vendor,
1405 board->second_card_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001406 continue;
1407 } else {
1408 if (!pci_dev_find(board->second_vendor,
Uwe Hermann394131e2008-10-18 21:14:13 +00001409 board->second_device))
Uwe Hermanna7e05482007-05-09 10:17:44 +00001410 continue;
1411 }
1412 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001413
Michael Karcher6701ee82010-01-20 14:14:11 +00001414 if (board->dmi_pattern) {
1415 if (!has_dmi_support) {
1416 fprintf(stderr, "WARNING: Can't autodetect %s %s,"
1417 " DMI info unavailable.\n",
1418 board->vendor_name, board->board_name);
1419 continue;
1420 } else {
1421 if (!dmi_match(board->dmi_pattern))
1422 continue;
1423 }
1424 }
1425
Uwe Hermanna7e05482007-05-09 10:17:44 +00001426 return board;
1427 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001428
Uwe Hermanna7e05482007-05-09 10:17:44 +00001429 return NULL;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001430}
1431
Uwe Hermann372eeb52007-12-04 21:49:06 +00001432int board_flash_enable(const char *vendor, const char *part)
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001433{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001434 struct board_pciid_enable *board = NULL;
1435 int ret = 0;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001436
Peter Stuge6b53fed2008-01-27 16:21:21 +00001437 if (part)
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +00001438 board = board_match_coreboot_name(vendor, part);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001439
Uwe Hermanna7e05482007-05-09 10:17:44 +00001440 if (!board)
1441 board = board_match_pci_card_ids();
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001442
Michael Karcher0b9e2a72010-03-11 23:04:16 +00001443 if (board && board->status == NT) {
Uwe Hermann43959702010-03-13 17:28:29 +00001444 if (!force_boardenable) {
Michael Karcher7f0c3ec2010-03-07 22:29:28 +00001445 printf("WARNING: Your mainboard is %s %s, but the mainboard-specific\n"
1446 "code has not been tested, and thus will not not be executed by default.\n"
1447 "Depending on your hardware environment, erasing, writing or even probing\n"
1448 "can fail without running the board specific code.\n\n"
1449 "Please see the man page (section PROGRAMMER SPECIFIC INFO, subsection\n"
Uwe Hermann43959702010-03-13 17:28:29 +00001450 "\"internal programmer\") for details.\n",
Michael Karcher7f0c3ec2010-03-07 22:29:28 +00001451 board->vendor_name, board->board_name);
1452 board = NULL;
Uwe Hermann43959702010-03-13 17:28:29 +00001453 } else {
Michael Karcher7f0c3ec2010-03-07 22:29:28 +00001454 printf("NOTE: Running an untested board enable procedure.\n"
Uwe Hermann43959702010-03-13 17:28:29 +00001455 "Please report success/failure to flashrom@flashrom.org.\n");
1456 }
Michael Karcher7f0c3ec2010-03-07 22:29:28 +00001457 }
1458
Uwe Hermanna7e05482007-05-09 10:17:44 +00001459 if (board) {
Luc Verhaegen93938c32010-01-20 14:45:03 +00001460 if (board->max_rom_decode_parallel)
1461 max_rom_decode.parallel =
1462 board->max_rom_decode_parallel * 1024;
1463
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00001464 if (board->enable != NULL) {
1465 printf("Disabling flash write protection for "
1466 "board \"%s %s\"... ", board->vendor_name,
1467 board->board_name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001468
Uwe Hermannb1bd3e82010-01-28 19:02:36 +00001469 ret = board->enable(board->vendor_name);
1470 if (ret)
1471 printf("FAILED!\n");
1472 else
1473 printf("OK.\n");
1474 }
Uwe Hermanna7e05482007-05-09 10:17:44 +00001475 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001476
Uwe Hermanna7e05482007-05-09 10:17:44 +00001477 return ret;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001478}