Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 1 | /* |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 2 | * This file is part of the flashrom project. |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 3 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 4 | * Copyright (C) 2000 Silicon Integrated System Corporation |
| 5 | * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de> |
| 6 | * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de> |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 7 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 11 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | /* |
| 23 | * Contains the chipset specific flash enables. |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 24 | */ |
| 25 | |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 26 | #define _LARGEFILE64_SOURCE |
| 27 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 28 | #include <stdlib.h> |
Uwe Hermann | e8ba538 | 2009-05-22 11:37:27 +0000 | [diff] [blame] | 29 | #include <string.h> |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 30 | #include <sys/types.h> |
| 31 | #include <sys/stat.h> |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 32 | #include <sys/mman.h> |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 33 | #include <fcntl.h> |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 34 | #include "flash.h" |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 35 | |
Stefan Reinauer | 9a6d176 | 2008-12-03 21:24:40 +0000 | [diff] [blame] | 36 | unsigned long flashbase = 0; |
| 37 | |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 38 | /** |
Carl-Daniel Hailfinger | b22918c | 2009-06-01 02:08:58 +0000 | [diff] [blame] | 39 | * flashrom defaults to Parallel/LPC/FWH flash devices. If a known host |
| 40 | * controller is found, the init routine sets the buses_supported bitfield to |
| 41 | * contain the supported buses for that controller. |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 42 | */ |
| 43 | |
Carl-Daniel Hailfinger | b22918c | 2009-06-01 02:08:58 +0000 | [diff] [blame] | 44 | enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI; |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 45 | |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 46 | extern int ichspi_lock; |
| 47 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 48 | static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name) |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 49 | { |
| 50 | uint8_t tmp; |
| 51 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 52 | /* |
| 53 | * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and |
| 54 | * 0xFFFE0000-0xFFFFFFFF ROM select enable. |
| 55 | */ |
Luc Verhaegen | 6b14175 | 2007-05-20 16:16:13 +0000 | [diff] [blame] | 56 | tmp = pci_read_byte(dev, 0x47); |
| 57 | tmp |= 0x46; |
| 58 | pci_write_byte(dev, 0x47, tmp); |
| 59 | |
| 60 | return 0; |
| 61 | } |
| 62 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 63 | static int enable_flash_sis630(struct pci_dev *dev, const char *name) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 64 | { |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 65 | uint8_t b; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 66 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 67 | /* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */ |
Alex Beregszaszi | c9fb5d9 | 2007-09-11 15:58:18 +0000 | [diff] [blame] | 68 | b = pci_read_byte(dev, 0x40); |
| 69 | pci_write_byte(dev, 0x40, b | 0xb); |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 70 | |
| 71 | /* Flash write enable on SiS 540/630. */ |
Alex Beregszaszi | c9fb5d9 | 2007-09-11 15:58:18 +0000 | [diff] [blame] | 72 | b = pci_read_byte(dev, 0x45); |
| 73 | pci_write_byte(dev, 0x45, b | 0x40); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 74 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 75 | /* The same thing on SiS 950 Super I/O side... */ |
| 76 | |
| 77 | /* First probe for Super I/O on config port 0x2e. */ |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 78 | OUTB(0x87, 0x2e); |
| 79 | OUTB(0x01, 0x2e); |
| 80 | OUTB(0x55, 0x2e); |
| 81 | OUTB(0x55, 0x2e); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 82 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 83 | if (INB(0x2f) != 0x87) { |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 84 | /* If that failed, try config port 0x4e. */ |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 85 | OUTB(0x87, 0x4e); |
| 86 | OUTB(0x01, 0x4e); |
| 87 | OUTB(0x55, 0x4e); |
| 88 | OUTB(0xaa, 0x4e); |
| 89 | if (INB(0x4f) != 0x87) { |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 90 | printf("Can not access SiS 950\n"); |
| 91 | return -1; |
| 92 | } |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 93 | OUTB(0x24, 0x4e); |
| 94 | b = INB(0x4f) | 0xfc; |
| 95 | OUTB(0x24, 0x4e); |
| 96 | OUTB(b, 0x4f); |
| 97 | OUTB(0x02, 0x4e); |
| 98 | OUTB(0x02, 0x4f); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 99 | } |
| 100 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 101 | OUTB(0x24, 0x2e); |
| 102 | printf("2f is %#x\n", INB(0x2f)); |
| 103 | b = INB(0x2f) | 0xfc; |
| 104 | OUTB(0x24, 0x2e); |
| 105 | OUTB(b, 0x2f); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 106 | |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 107 | OUTB(0x02, 0x2e); |
| 108 | OUTB(0x02, 0x2f); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 109 | |
| 110 | return 0; |
| 111 | } |
| 112 | |
Uwe Hermann | 987942d | 2006-11-07 11:16:21 +0000 | [diff] [blame] | 113 | /* Datasheet: |
| 114 | * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4) |
| 115 | * - URL: http://www.intel.com/design/intarch/datashts/290562.htm |
| 116 | * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf |
| 117 | * - Order Number: 290562-001 |
| 118 | */ |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 119 | static int enable_flash_piix4(struct pci_dev *dev, const char *name) |
Uwe Hermann | ea2c66d | 2006-11-05 18:26:08 +0000 | [diff] [blame] | 120 | { |
| 121 | uint16_t old, new; |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 122 | uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */ |
Uwe Hermann | ea2c66d | 2006-11-05 18:26:08 +0000 | [diff] [blame] | 123 | |
| 124 | old = pci_read_word(dev, xbcs); |
| 125 | |
| 126 | /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 127 | * FFF00000-FFF7FFFF are forwarded to ISA). |
Uwe Hermann | c556d32 | 2008-10-28 11:50:05 +0000 | [diff] [blame] | 128 | * Note: This bit is reserved on PIIX/PIIX3/MPIIX. |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 129 | * Set bit 7: Extended BIOS Enable (PCI master accesses to |
| 130 | * FFF80000-FFFDFFFF are forwarded to ISA). |
| 131 | * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to |
| 132 | * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top |
| 133 | * of 1 Mbyte, or the aliases at the top of 4 Gbyte |
| 134 | * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#. |
| 135 | * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA. |
| 136 | * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable). |
| 137 | */ |
Uwe Hermann | c556d32 | 2008-10-28 11:50:05 +0000 | [diff] [blame] | 138 | if (dev->device_id == 0x122e || dev->device_id == 0x7000 |
| 139 | || dev->device_id == 0x1234) |
| 140 | new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */ |
Uwe Hermann | 8720345 | 2008-10-26 18:40:42 +0000 | [diff] [blame] | 141 | else |
| 142 | new = old | 0x02c4; |
Uwe Hermann | ea2c66d | 2006-11-05 18:26:08 +0000 | [diff] [blame] | 143 | |
| 144 | if (new == old) |
| 145 | return 0; |
| 146 | |
| 147 | pci_write_word(dev, xbcs, new); |
| 148 | |
| 149 | if (pci_read_word(dev, xbcs) != new) { |
| 150 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name); |
| 151 | return -1; |
| 152 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 153 | |
Uwe Hermann | ea2c66d | 2006-11-05 18:26:08 +0000 | [diff] [blame] | 154 | return 0; |
| 155 | } |
| 156 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 157 | /* |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 158 | * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet" |
| 159 | * http://download.intel.com/design/chipsets/datashts/30701303.pdf |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 160 | */ |
| 161 | static int enable_flash_ich(struct pci_dev *dev, const char *name, |
| 162 | int bios_cntl) |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 163 | { |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 164 | uint8_t old, new; |
Stefan Reinauer | eb36647 | 2006-09-06 15:48:48 +0000 | [diff] [blame] | 165 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 166 | /* |
| 167 | * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 168 | * just treating it as 8 bit wide seems to work fine in practice. |
Stefan Reinauer | eb36647 | 2006-09-06 15:48:48 +0000 | [diff] [blame] | 169 | */ |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 170 | old = pci_read_byte(dev, bios_cntl); |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 171 | |
Uwe Hermann | 793bdcd | 2008-05-22 22:47:04 +0000 | [diff] [blame] | 172 | printf_debug("\nBIOS Lock Enable: %sabled, ", |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 173 | (old & (1 << 1)) ? "en" : "dis"); |
| 174 | printf_debug("BIOS Write Enable: %sabled, ", |
| 175 | (old & (1 << 0)) ? "en" : "dis"); |
| 176 | printf_debug("BIOS_CNTL is 0x%x\n", old); |
| 177 | |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 178 | new = old | 1; |
| 179 | |
| 180 | if (new == old) |
| 181 | return 0; |
| 182 | |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 183 | pci_write_byte(dev, bios_cntl, new); |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 184 | |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 185 | if (pci_read_byte(dev, bios_cntl) != new) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 186 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name); |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 187 | return -1; |
| 188 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 189 | |
Ronald G. Minnich | 6a96741 | 2004-09-28 20:09:06 +0000 | [diff] [blame] | 190 | return 0; |
| 191 | } |
| 192 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 193 | static int enable_flash_ich_4e(struct pci_dev *dev, const char *name) |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 194 | { |
Stefan Reinauer | eb36647 | 2006-09-06 15:48:48 +0000 | [diff] [blame] | 195 | return enable_flash_ich(dev, name, 0x4e); |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 196 | } |
| 197 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 198 | static int enable_flash_ich_dc(struct pci_dev *dev, const char *name) |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 199 | { |
Stefan Reinauer | eb36647 | 2006-09-06 15:48:48 +0000 | [diff] [blame] | 200 | return enable_flash_ich(dev, name, 0xdc); |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 201 | } |
| 202 | |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 203 | #define ICH_STRAP_RSVD 0x00 |
| 204 | #define ICH_STRAP_SPI 0x01 |
| 205 | #define ICH_STRAP_PCI 0x02 |
| 206 | #define ICH_STRAP_LPC 0x03 |
Carl-Daniel Hailfinger | 6dc1d3b | 2008-05-14 14:51:22 +0000 | [diff] [blame] | 207 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 208 | static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) |
| 209 | { |
Rudolf Marek | 3fdbccf | 2008-06-30 21:38:30 +0000 | [diff] [blame] | 210 | uint32_t mmio_base; |
| 211 | |
| 212 | mmio_base = (pci_read_long(dev, 0xbc)) << 8; |
| 213 | printf_debug("MMIO base at = 0x%x\n", mmio_base); |
Stefan Reinauer | 0593f21 | 2009-01-26 01:10:48 +0000 | [diff] [blame] | 214 | spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); |
Rudolf Marek | 3fdbccf | 2008-06-30 21:38:30 +0000 | [diff] [blame] | 215 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 216 | printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 217 | mmio_readw(spibar + 0x6c)); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 218 | |
Carl-Daniel Hailfinger | b22918c | 2009-06-01 02:08:58 +0000 | [diff] [blame] | 219 | /* Not sure if it speaks all these bus protocols. */ |
| 220 | buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 221 | spi_controller = SPI_CONTROLLER_VIA; |
Rudolf Marek | 0c2029f | 2009-02-01 18:40:50 +0000 | [diff] [blame] | 222 | ich_init_opcodes(); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 223 | |
Rudolf Marek | 3fdbccf | 2008-06-30 21:38:30 +0000 | [diff] [blame] | 224 | return 0; |
| 225 | } |
| 226 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 227 | static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, |
| 228 | int ich_generation) |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 229 | { |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 230 | int ret, i; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 231 | uint8_t old, new, bbs, buc; |
Carl-Daniel Hailfinger | d3b0e39 | 2008-11-03 00:20:22 +0000 | [diff] [blame] | 232 | uint16_t spibar_offset, tmp2; |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 233 | uint32_t tmp, gcs; |
Carl-Daniel Hailfinger | 6dc1d3b | 2008-05-14 14:51:22 +0000 | [diff] [blame] | 234 | void *rcrb; |
Carl-Daniel Hailfinger | d3b0e39 | 2008-11-03 00:20:22 +0000 | [diff] [blame] | 235 | //TODO: These names are incorrect for EP80579. For that, the solution would look like the commented line |
| 236 | //static const char *straps_names[] = {"SPI", "reserved", "reserved", "LPC" }; |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 237 | static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" }; |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 238 | |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 239 | /* Enable Flash Writes */ |
| 240 | ret = enable_flash_ich_dc(dev, name); |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 241 | |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 242 | /* Get physical address of Root Complex Register Block */ |
| 243 | tmp = pci_read_long(dev, 0xf0) & 0xffffc000; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 244 | printf_debug("\nRoot Complex Register Block address = 0x%x\n", tmp); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 245 | |
| 246 | /* Map RCBA to virtual memory */ |
Stefan Reinauer | 0593f21 | 2009-01-26 01:10:48 +0000 | [diff] [blame] | 247 | rcrb = physmap("ICH RCRB", tmp, 0x4000); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 248 | |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 249 | gcs = mmio_readl(rcrb + 0x3410); |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 250 | printf_debug("GCS = 0x%x: ", gcs); |
| 251 | printf_debug("BIOS Interface Lock-Down: %sabled, ", |
| 252 | (gcs & 0x1) ? "en" : "dis"); |
| 253 | bbs = (gcs >> 10) & 0x3; |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 254 | printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]); |
Carl-Daniel Hailfinger | 6dc1d3b | 2008-05-14 14:51:22 +0000 | [diff] [blame] | 255 | |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 256 | buc = mmio_readb(rcrb + 0x3414); |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 257 | printf_debug("Top Swap : %s\n", |
| 258 | (buc & 1) ? "enabled (A16 inverted)" : "not enabled"); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 259 | |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 260 | /* It seems the ICH7 does not support SPI and LPC chips at the same |
| 261 | * time. At least not with our current code. So we prevent searching |
| 262 | * on ICH7 when the southbridge is strapped to LPC |
| 263 | */ |
| 264 | |
| 265 | if (ich_generation == 7 && bbs == ICH_STRAP_LPC) { |
Carl-Daniel Hailfinger | b22918c | 2009-06-01 02:08:58 +0000 | [diff] [blame] | 266 | /* Not sure if it speaks LPC as well. */ |
| 267 | buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 268 | /* No further SPI initialization required */ |
| 269 | return ret; |
| 270 | } |
| 271 | |
| 272 | switch (ich_generation) { |
| 273 | case 7: |
Carl-Daniel Hailfinger | b22918c | 2009-06-01 02:08:58 +0000 | [diff] [blame] | 274 | buses_supported = CHIP_BUSTYPE_SPI; |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 275 | spi_controller = SPI_CONTROLLER_ICH7; |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 276 | spibar_offset = 0x3020; |
| 277 | break; |
| 278 | case 8: |
Carl-Daniel Hailfinger | b22918c | 2009-06-01 02:08:58 +0000 | [diff] [blame] | 279 | /* Not sure if it speaks LPC as well. */ |
| 280 | buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 281 | spi_controller = SPI_CONTROLLER_ICH9; |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 282 | spibar_offset = 0x3020; |
| 283 | break; |
| 284 | case 9: |
Carl-Daniel Hailfinger | 28ec74b | 2008-10-10 20:54:41 +0000 | [diff] [blame] | 285 | case 10: |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 286 | default: /* Future version might behave the same */ |
Carl-Daniel Hailfinger | b22918c | 2009-06-01 02:08:58 +0000 | [diff] [blame] | 287 | /* Not sure if it speaks LPC as well. */ |
| 288 | buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI; |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 289 | spi_controller = SPI_CONTROLLER_ICH9; |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 290 | spibar_offset = 0x3800; |
| 291 | break; |
| 292 | } |
| 293 | |
Carl-Daniel Hailfinger | 6dc1d3b | 2008-05-14 14:51:22 +0000 | [diff] [blame] | 294 | /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */ |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 295 | printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 296 | |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 297 | /* Assign Virtual Address */ |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 298 | spibar = rcrb + spibar_offset; |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 299 | |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 300 | switch (spi_controller) { |
| 301 | case SPI_CONTROLLER_ICH7: |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 302 | printf_debug("0x00: 0x%04x (SPIS)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 303 | mmio_readw(spibar + 0)); |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 304 | printf_debug("0x02: 0x%04x (SPIC)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 305 | mmio_readw(spibar + 2)); |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 306 | printf_debug("0x04: 0x%08x (SPIA)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 307 | mmio_readl(spibar + 4)); |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 308 | for (i = 0; i < 8; i++) { |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 309 | int offs; |
| 310 | offs = 8 + (i * 8); |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 311 | printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs, |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 312 | mmio_readl(spibar + offs), i); |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 313 | printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4, |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 314 | mmio_readl(spibar + offs + 4), i); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 315 | } |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 316 | printf_debug("0x50: 0x%08x (BBAR)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 317 | mmio_readl(spibar + 0x50)); |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 318 | printf_debug("0x54: 0x%04x (PREOP)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 319 | mmio_readw(spibar + 0x54)); |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 320 | printf_debug("0x56: 0x%04x (OPTYPE)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 321 | mmio_readw(spibar + 0x56)); |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 322 | printf_debug("0x58: 0x%08x (OPMENU)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 323 | mmio_readl(spibar + 0x58)); |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 324 | printf_debug("0x5c: 0x%08x (OPMENU+4)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 325 | mmio_readl(spibar + 0x5c)); |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 326 | for (i = 0; i < 4; i++) { |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 327 | int offs; |
| 328 | offs = 0x60 + (i * 4); |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 329 | printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs, |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 330 | mmio_readl(spibar + offs), i); |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 331 | } |
| 332 | printf_debug("\n"); |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 333 | if (mmio_readw(spibar) & (1 << 15)) { |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 334 | printf("WARNING: SPI Configuration Lockdown activated.\n"); |
FENG yu ning | c05a295 | 2008-12-08 18:16:58 +0000 | [diff] [blame] | 335 | ichspi_lock = 1; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 336 | } |
FENG yu ning | f041e9b | 2008-12-15 02:32:11 +0000 | [diff] [blame] | 337 | ich_init_opcodes(); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 338 | break; |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 339 | case SPI_CONTROLLER_ICH9: |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 340 | tmp2 = mmio_readw(spibar + 4); |
FENG yu ning | 37179b8 | 2009-01-18 06:39:32 +0000 | [diff] [blame] | 341 | printf_debug("0x04: 0x%04x (HSFS)\n", tmp2); |
| 342 | printf_debug("FLOCKDN %i, ", (tmp2 >> 15 & 1)); |
| 343 | printf_debug("FDV %i, ", (tmp2 >> 14) & 1); |
| 344 | printf_debug("FDOPSS %i, ", (tmp2 >> 13) & 1); |
| 345 | printf_debug("SCIP %i, ", (tmp2 >> 5) & 1); |
| 346 | printf_debug("BERASE %i, ", (tmp2 >> 3) & 3); |
| 347 | printf_debug("AEL %i, ", (tmp2 >> 2) & 1); |
| 348 | printf_debug("FCERR %i, ", (tmp2 >> 1) & 1); |
| 349 | printf_debug("FDONE %i\n", (tmp2 >> 0) & 1); |
Carl-Daniel Hailfinger | d3b0e39 | 2008-11-03 00:20:22 +0000 | [diff] [blame] | 350 | |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 351 | tmp = mmio_readl(spibar + 0x50); |
Carl-Daniel Hailfinger | d3b0e39 | 2008-11-03 00:20:22 +0000 | [diff] [blame] | 352 | printf_debug("0x50: 0x%08x (FRAP)\n", tmp); |
| 353 | printf_debug("BMWAG %i, ", (tmp >> 24) & 0xff); |
| 354 | printf_debug("BMRAG %i, ", (tmp >> 16) & 0xff); |
| 355 | printf_debug("BRWA %i, ", (tmp >> 8) & 0xff); |
| 356 | printf_debug("BRRA %i\n", (tmp >> 0) & 0xff); |
| 357 | |
| 358 | printf_debug("0x54: 0x%08x (FREG0)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 359 | mmio_readl(spibar + 0x54)); |
Carl-Daniel Hailfinger | d3b0e39 | 2008-11-03 00:20:22 +0000 | [diff] [blame] | 360 | printf_debug("0x58: 0x%08x (FREG1)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 361 | mmio_readl(spibar + 0x58)); |
Carl-Daniel Hailfinger | d3b0e39 | 2008-11-03 00:20:22 +0000 | [diff] [blame] | 362 | printf_debug("0x5C: 0x%08x (FREG2)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 363 | mmio_readl(spibar + 0x5C)); |
Carl-Daniel Hailfinger | d3b0e39 | 2008-11-03 00:20:22 +0000 | [diff] [blame] | 364 | printf_debug("0x60: 0x%08x (FREG3)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 365 | mmio_readl(spibar + 0x60)); |
Carl-Daniel Hailfinger | d3b0e39 | 2008-11-03 00:20:22 +0000 | [diff] [blame] | 366 | printf_debug("0x64: 0x%08x (FREG4)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 367 | mmio_readl(spibar + 0x64)); |
Carl-Daniel Hailfinger | d3b0e39 | 2008-11-03 00:20:22 +0000 | [diff] [blame] | 368 | printf_debug("0x74: 0x%08x (PR0)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 369 | mmio_readl(spibar + 0x74)); |
Carl-Daniel Hailfinger | d3b0e39 | 2008-11-03 00:20:22 +0000 | [diff] [blame] | 370 | printf_debug("0x78: 0x%08x (PR1)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 371 | mmio_readl(spibar + 0x78)); |
Carl-Daniel Hailfinger | d3b0e39 | 2008-11-03 00:20:22 +0000 | [diff] [blame] | 372 | printf_debug("0x7C: 0x%08x (PR2)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 373 | mmio_readl(spibar + 0x7C)); |
Carl-Daniel Hailfinger | d3b0e39 | 2008-11-03 00:20:22 +0000 | [diff] [blame] | 374 | printf_debug("0x80: 0x%08x (PR3)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 375 | mmio_readl(spibar + 0x80)); |
Carl-Daniel Hailfinger | d3b0e39 | 2008-11-03 00:20:22 +0000 | [diff] [blame] | 376 | printf_debug("0x84: 0x%08x (PR4)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 377 | mmio_readl(spibar + 0x84)); |
FENG yu ning | 37179b8 | 2009-01-18 06:39:32 +0000 | [diff] [blame] | 378 | printf_debug("0x90: 0x%08x (SSFS, SSFC)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 379 | mmio_readl(spibar + 0x90)); |
FENG yu ning | 37179b8 | 2009-01-18 06:39:32 +0000 | [diff] [blame] | 380 | printf_debug("0x94: 0x%04x (PREOP)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 381 | mmio_readw(spibar + 0x94)); |
FENG yu ning | 37179b8 | 2009-01-18 06:39:32 +0000 | [diff] [blame] | 382 | printf_debug("0x96: 0x%04x (OPTYPE)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 383 | mmio_readw(spibar + 0x96)); |
FENG yu ning | 37179b8 | 2009-01-18 06:39:32 +0000 | [diff] [blame] | 384 | printf_debug("0x98: 0x%08x (OPMENU)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 385 | mmio_readl(spibar + 0x98)); |
FENG yu ning | 37179b8 | 2009-01-18 06:39:32 +0000 | [diff] [blame] | 386 | printf_debug("0x9C: 0x%08x (OPMENU+4)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 387 | mmio_readl(spibar + 0x9C)); |
FENG yu ning | 37179b8 | 2009-01-18 06:39:32 +0000 | [diff] [blame] | 388 | printf_debug("0xA0: 0x%08x (BBAR)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 389 | mmio_readl(spibar + 0xA0)); |
Carl-Daniel Hailfinger | d3b0e39 | 2008-11-03 00:20:22 +0000 | [diff] [blame] | 390 | printf_debug("0xB0: 0x%08x (FDOC)\n", |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 391 | mmio_readl(spibar + 0xB0)); |
FENG yu ning | 37179b8 | 2009-01-18 06:39:32 +0000 | [diff] [blame] | 392 | if (tmp2 & (1 << 15)) { |
| 393 | printf("WARNING: SPI Configuration Lockdown activated.\n"); |
| 394 | ichspi_lock = 1; |
| 395 | } |
Peter Stuge | e8a3e4c | 2008-12-22 14:12:08 +0000 | [diff] [blame] | 396 | ich_init_opcodes(); |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 397 | break; |
| 398 | default: |
| 399 | /* Nothing */ |
| 400 | break; |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 401 | } |
| 402 | |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 403 | old = pci_read_byte(dev, 0xdc); |
| 404 | printf_debug("SPI Read Configuration: "); |
| 405 | new = (old >> 2) & 0x3; |
| 406 | switch (new) { |
| 407 | case 0: |
| 408 | case 1: |
| 409 | case 2: |
| 410 | printf_debug("prefetching %sabled, caching %sabled, ", |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 411 | (new & 0x2) ? "en" : "dis", |
| 412 | (new & 0x1) ? "dis" : "en"); |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 413 | break; |
| 414 | default: |
| 415 | printf_debug("invalid prefetching/caching settings, "); |
| 416 | break; |
| 417 | } |
Carl-Daniel Hailfinger | 67f9ea3 | 2008-03-14 17:20:59 +0000 | [diff] [blame] | 418 | |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 419 | return ret; |
| 420 | } |
Stefan Reinauer | a9424d5 | 2008-06-27 16:28:34 +0000 | [diff] [blame] | 421 | |
Carl-Daniel Hailfinger | 1b18b3c | 2008-05-16 14:39:39 +0000 | [diff] [blame] | 422 | static int enable_flash_ich7(struct pci_dev *dev, const char *name) |
Carl-Daniel Hailfinger | 6dc1d3b | 2008-05-14 14:51:22 +0000 | [diff] [blame] | 423 | { |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 424 | return enable_flash_ich_dc_spi(dev, name, 7); |
Carl-Daniel Hailfinger | 6dc1d3b | 2008-05-14 14:51:22 +0000 | [diff] [blame] | 425 | } |
| 426 | |
Carl-Daniel Hailfinger | 1b18b3c | 2008-05-16 14:39:39 +0000 | [diff] [blame] | 427 | static int enable_flash_ich8(struct pci_dev *dev, const char *name) |
| 428 | { |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 429 | return enable_flash_ich_dc_spi(dev, name, 8); |
Carl-Daniel Hailfinger | 1b18b3c | 2008-05-16 14:39:39 +0000 | [diff] [blame] | 430 | } |
| 431 | |
Carl-Daniel Hailfinger | 6dc1d3b | 2008-05-14 14:51:22 +0000 | [diff] [blame] | 432 | static int enable_flash_ich9(struct pci_dev *dev, const char *name) |
| 433 | { |
Stefan Reinauer | 2cb94e1 | 2008-06-30 23:45:22 +0000 | [diff] [blame] | 434 | return enable_flash_ich_dc_spi(dev, name, 9); |
Carl-Daniel Hailfinger | 6dc1d3b | 2008-05-14 14:51:22 +0000 | [diff] [blame] | 435 | } |
| 436 | |
Carl-Daniel Hailfinger | 28ec74b | 2008-10-10 20:54:41 +0000 | [diff] [blame] | 437 | static int enable_flash_ich10(struct pci_dev *dev, const char *name) |
| 438 | { |
| 439 | return enable_flash_ich_dc_spi(dev, name, 10); |
| 440 | } |
| 441 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 442 | static int enable_flash_vt823x(struct pci_dev *dev, const char *name) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 443 | { |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 444 | uint8_t val; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 445 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 446 | /* enable ROM decode range (1MB) FFC00000 - FFFFFFFF */ |
Bari Ari | 9477c4e | 2008-04-29 13:46:38 +0000 | [diff] [blame] | 447 | pci_write_byte(dev, 0x41, 0x7f); |
| 448 | |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 449 | /* ROM write enable */ |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 450 | val = pci_read_byte(dev, 0x40); |
| 451 | val |= 0x10; |
| 452 | pci_write_byte(dev, 0x40, val); |
| 453 | |
| 454 | if (pci_read_byte(dev, 0x40) != val) { |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 455 | printf("\nWARNING: Failed to enable ROM Write on \"%s\"\n", |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 456 | name); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 457 | return -1; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 458 | } |
Luc Verhaegen | 6382b44 | 2007-03-02 22:16:38 +0000 | [diff] [blame] | 459 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 460 | return 0; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 461 | } |
| 462 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 463 | static int enable_flash_cs5530(struct pci_dev *dev, const char *name) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 464 | { |
Uwe Hermann | f4a673b | 2007-06-06 21:35:45 +0000 | [diff] [blame] | 465 | uint8_t reg8; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 466 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 467 | #define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */ |
| 468 | #define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */ |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 469 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 470 | #define LOWER_ROM_ADDRESS_RANGE (1 << 0) |
| 471 | #define ROM_WRITE_ENABLE (1 << 1) |
| 472 | #define UPPER_ROM_ADDRESS_RANGE (1 << 2) |
| 473 | #define BIOS_ROM_POSITIVE_DECODE (1 << 5) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 474 | |
Uwe Hermann | f4a673b | 2007-06-06 21:35:45 +0000 | [diff] [blame] | 475 | /* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and |
| 476 | * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB. |
| 477 | * Make the configured ROM areas writable. |
| 478 | */ |
| 479 | reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG); |
| 480 | reg8 |= LOWER_ROM_ADDRESS_RANGE; |
| 481 | reg8 |= UPPER_ROM_ADDRESS_RANGE; |
| 482 | reg8 |= ROM_WRITE_ENABLE; |
| 483 | pci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 484 | |
Uwe Hermann | f4a673b | 2007-06-06 21:35:45 +0000 | [diff] [blame] | 485 | /* Set positive decode on ROM. */ |
| 486 | reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2); |
| 487 | reg8 |= BIOS_ROM_POSITIVE_DECODE; |
| 488 | pci_write_byte(dev, DECODE_CONTROL_REG2, reg8); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 489 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 490 | return 0; |
| 491 | } |
| 492 | |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 493 | /** |
| 494 | * Geode systems write protect the BIOS via RCONFs (cache settings similar |
| 495 | * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22. Reading and |
| 496 | * writing to MSRs, however requires instructions rdmsr/wrmsr, which are |
| 497 | * ring0 privileged instructions so only the kernel can do the read/write. |
| 498 | * This function, therefore, requires that the msr kernel module be loaded |
| 499 | * to access these instructions from user space using device /dev/cpu/0/msr. |
| 500 | * |
| 501 | * This hard-coded location could have potential problems on SMP machines |
| 502 | * since it assumes cpu0, but it is safe on the Geode which is not SMP. |
| 503 | * |
| 504 | * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL. |
| 505 | * To enable write to NOR Boot flash for the benefit of systems that have such |
| 506 | * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select). |
| 507 | * |
| 508 | * This is probably not portable beyond Linux. |
| 509 | */ |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 510 | static int enable_flash_cs5536(struct pci_dev *dev, const char *name) |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 511 | { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 512 | #define MSR_RCONF_DEFAULT 0x1808 |
| 513 | #define MSR_NORF_CTL 0x51400018 |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 514 | |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 515 | int fd_msr; |
| 516 | unsigned char buf[8]; |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 517 | |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 518 | fd_msr = open("/dev/cpu/0/msr", O_RDWR); |
Bertrand Jacquin | b452a91 | 2009-05-05 21:08:36 +0000 | [diff] [blame] | 519 | if (fd_msr == -1) { |
Peter Stuge | 7725fa8 | 2009-05-06 13:38:55 +0000 | [diff] [blame] | 520 | perror("open(/dev/cpu/0/msr)"); |
| 521 | printf("Cannot operate on MSR. Did you run 'modprobe msr'?\n"); |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 522 | return -1; |
| 523 | } |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 524 | |
| 525 | if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) { |
| 526 | perror("lseek64"); |
| 527 | close(fd_msr); |
| 528 | return -1; |
| 529 | } |
| 530 | |
| 531 | if (read(fd_msr, buf, 8) != 8) { |
Mart Raudsepp | 3697ac7 | 2008-02-11 14:32:45 +0000 | [diff] [blame] | 532 | perror("read msr"); |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 533 | close(fd_msr); |
| 534 | return -1; |
| 535 | } |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 536 | |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 537 | if (buf[7] != 0x22) { |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 538 | buf[7] &= 0xfb; |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 539 | if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, |
| 540 | SEEK_SET) == -1) { |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 541 | perror("lseek64"); |
| 542 | close(fd_msr); |
| 543 | return -1; |
| 544 | } |
| 545 | |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 546 | if (write(fd_msr, buf, 8) < 0) { |
| 547 | perror("msr write"); |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 548 | close(fd_msr); |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 549 | return -1; |
| 550 | } |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 551 | } |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 552 | |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 553 | if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) { |
| 554 | perror("lseek64"); |
| 555 | close(fd_msr); |
| 556 | return -1; |
| 557 | } |
| 558 | |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 559 | if (read(fd_msr, buf, 8) != 8) { |
| 560 | perror("read msr"); |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 561 | close(fd_msr); |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 562 | return -1; |
| 563 | } |
| 564 | |
| 565 | /* Raise WE_CS3 bit. */ |
| 566 | buf[0] |= 0x08; |
| 567 | |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 568 | if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) { |
| 569 | perror("lseek64"); |
| 570 | close(fd_msr); |
| 571 | return -1; |
| 572 | } |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 573 | if (write(fd_msr, buf, 8) < 0) { |
| 574 | perror("msr write"); |
Mart Raudsepp | e1344da | 2008-02-08 10:10:57 +0000 | [diff] [blame] | 575 | close(fd_msr); |
Mart Raudsepp | 0514a5f | 2008-02-08 09:59:58 +0000 | [diff] [blame] | 576 | return -1; |
| 577 | } |
| 578 | |
| 579 | close(fd_msr); |
| 580 | |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 581 | #undef MSR_RCONF_DEFAULT |
| 582 | #undef MSR_NORF_CTL |
Lane Brooks | d54958a | 2007-11-13 16:45:22 +0000 | [diff] [blame] | 583 | return 0; |
| 584 | } |
| 585 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 586 | static int enable_flash_sc1100(struct pci_dev *dev, const char *name) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 587 | { |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 588 | uint8_t new; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 589 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 590 | pci_write_byte(dev, 0x52, 0xee); |
| 591 | |
| 592 | new = pci_read_byte(dev, 0x52); |
| 593 | |
| 594 | if (new != 0xee) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 595 | printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 596 | return -1; |
| 597 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 598 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 599 | return 0; |
| 600 | } |
| 601 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 602 | static int enable_flash_sis5595(struct pci_dev *dev, const char *name) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 603 | { |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 604 | uint8_t new, newer; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 605 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 606 | new = pci_read_byte(dev, 0x45); |
| 607 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 608 | new &= (~0x20); /* Clear bit 5. */ |
| 609 | new |= 0x4; /* Set bit 2. */ |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 610 | |
| 611 | pci_write_byte(dev, 0x45, new); |
| 612 | |
| 613 | newer = pci_read_byte(dev, 0x45); |
| 614 | if (newer != new) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 615 | printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 616 | printf("Stuck at 0x%x\n", newer); |
| 617 | return -1; |
| 618 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 619 | |
Urja Rannikko | a88daa7 | 2008-10-18 13:54:30 +0000 | [diff] [blame] | 620 | /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */ |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 621 | new = pci_read_byte(dev, 0x40); |
Urja Rannikko | a88daa7 | 2008-10-18 13:54:30 +0000 | [diff] [blame] | 622 | new &= 0xFB; |
| 623 | new |= 0x3; |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 624 | pci_write_byte(dev, 0x40, new); |
| 625 | newer = pci_read_byte(dev, 0x40); |
Urja Rannikko | a88daa7 | 2008-10-18 13:54:30 +0000 | [diff] [blame] | 626 | if (newer != new) { |
| 627 | printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); |
| 628 | printf("Stuck at 0x%x\n", newer); |
| 629 | return -1; |
| 630 | } |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 631 | return 0; |
| 632 | } |
| 633 | |
Uwe Hermann | 190f849 | 2008-10-25 18:03:50 +0000 | [diff] [blame] | 634 | /* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */ |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 635 | static int enable_flash_amd8111(struct pci_dev *dev, const char *name) |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 636 | { |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 637 | uint8_t old, new; |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 638 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 639 | /* Enable decoding at 0xffb00000 to 0xffffffff. */ |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 640 | old = pci_read_byte(dev, 0x43); |
Ollie Lho | d11f361 | 2004-12-07 17:19:04 +0000 | [diff] [blame] | 641 | new = old | 0xC0; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 642 | if (new != old) { |
| 643 | pci_write_byte(dev, 0x43, new); |
| 644 | if (pci_read_byte(dev, 0x43) != new) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 645 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 646 | } |
| 647 | } |
| 648 | |
Uwe Hermann | 190f849 | 2008-10-25 18:03:50 +0000 | [diff] [blame] | 649 | /* Enable 'ROM write' bit. */ |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 650 | old = pci_read_byte(dev, 0x40); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 651 | new = old | 0x01; |
| 652 | if (new == old) |
| 653 | return 0; |
| 654 | pci_write_byte(dev, 0x40, new); |
| 655 | |
| 656 | if (pci_read_byte(dev, 0x40) != new) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 657 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name); |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 658 | return -1; |
| 659 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 660 | |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 661 | return 0; |
| 662 | } |
| 663 | |
Marc Jones | 3af487d | 2008-10-15 17:50:29 +0000 | [diff] [blame] | 664 | static int enable_flash_sb600(struct pci_dev *dev, const char *name) |
| 665 | { |
Carl-Daniel Hailfinger | 41d6bd9 | 2009-05-05 22:50:07 +0000 | [diff] [blame] | 666 | uint32_t tmp, prot; |
Marc Jones | 3af487d | 2008-10-15 17:50:29 +0000 | [diff] [blame] | 667 | uint8_t reg; |
Carl-Daniel Hailfinger | dbfa029 | 2009-05-10 14:11:07 +0000 | [diff] [blame] | 668 | struct pci_dev *smbus_dev; |
| 669 | int has_spi = 1; |
Marc Jones | 3af487d | 2008-10-15 17:50:29 +0000 | [diff] [blame] | 670 | |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 671 | /* Clear ROM protect 0-3. */ |
| 672 | for (reg = 0x50; reg < 0x60; reg += 4) { |
Carl-Daniel Hailfinger | 41d6bd9 | 2009-05-05 22:50:07 +0000 | [diff] [blame] | 673 | prot = pci_read_long(dev, reg); |
| 674 | /* No protection flags for this region?*/ |
| 675 | if ((prot & 0x3) == 0) |
| 676 | continue; |
| 677 | printf_debug("SB600 %s%sprotected from %u to %u\n", |
| 678 | (prot & 0x1) ? "write " : "", |
| 679 | (prot & 0x2) ? "read " : "", |
| 680 | (prot & 0xfffffc00), |
| 681 | (prot & 0xfffffc00) + ((prot & 0x3ff) << 8)); |
| 682 | prot &= 0xfffffffc; |
| 683 | pci_write_byte(dev, reg, prot); |
| 684 | prot = pci_read_long(dev, reg); |
Carl-Daniel Hailfinger | 9bb88ac | 2009-05-06 13:51:44 +0000 | [diff] [blame] | 685 | if (prot & 0x3) |
Peter Stuge | 19997ae | 2009-05-06 15:05:39 +0000 | [diff] [blame] | 686 | printf("SB600 %s%sunprotect failed from %u to %u\n", |
Carl-Daniel Hailfinger | 9bb88ac | 2009-05-06 13:51:44 +0000 | [diff] [blame] | 687 | (prot & 0x1) ? "write " : "", |
| 688 | (prot & 0x2) ? "read " : "", |
| 689 | (prot & 0xfffffc00), |
| 690 | (prot & 0xfffffc00) + ((prot & 0x3ff) << 8)); |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 691 | } |
| 692 | |
Carl-Daniel Hailfinger | 41d6bd9 | 2009-05-05 22:50:07 +0000 | [diff] [blame] | 693 | /* Read SPI_BaseAddr */ |
| 694 | tmp = pci_read_long(dev, 0xa0); |
| 695 | tmp &= 0xfffffff0; /* remove low 4 bits (reserved) */ |
| 696 | printf_debug("SPI base address is at 0x%x\n", tmp); |
| 697 | |
Carl-Daniel Hailfinger | dbfa029 | 2009-05-10 14:11:07 +0000 | [diff] [blame] | 698 | /* If the BAR has address 0, it is unlikely SPI is used. */ |
| 699 | if (!tmp) |
| 700 | has_spi = 0; |
| 701 | |
Carl-Daniel Hailfinger | 41d6bd9 | 2009-05-05 22:50:07 +0000 | [diff] [blame] | 702 | /* Physical memory can only be mapped at page (4k) boundaries */ |
| 703 | sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000, 0x1000); |
| 704 | /* The low bits of the SPI base address are used as offset into the mapped page */ |
| 705 | sb600_spibar += tmp & 0xfff; |
| 706 | |
Carl-Daniel Hailfinger | dbfa029 | 2009-05-10 14:11:07 +0000 | [diff] [blame] | 707 | /* Look for the SMBus device. */ |
| 708 | smbus_dev = pci_dev_find(0x1002, 0x4385); |
| 709 | |
| 710 | if (!smbus_dev) { |
| 711 | fprintf(stderr, "ERROR: SMBus device not found. Not enabling SPI.\n"); |
| 712 | has_spi = 0; |
| 713 | } else { |
| 714 | /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */ |
| 715 | /* GPIO11/SPI_DO and GPIO12/SPI_DI status */ |
| 716 | reg = pci_read_byte(smbus_dev, 0xAB); |
| 717 | reg &= 0xC0; |
| 718 | printf_debug("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO"); |
| 719 | printf_debug("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI"); |
| 720 | if (reg != 0x00) |
| 721 | has_spi = 0; |
| 722 | /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */ |
| 723 | reg = pci_read_byte(smbus_dev, 0x83); |
| 724 | reg &= 0xC0; |
| 725 | printf_debug("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD"); |
| 726 | printf_debug("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS"); |
Carl-Daniel Hailfinger | 9862251 | 2009-05-15 23:36:23 +0000 | [diff] [blame] | 727 | /* SPI_HOLD is not used on all boards, filter it out. */ |
| 728 | if ((reg & 0x80) != 0x00) |
Carl-Daniel Hailfinger | dbfa029 | 2009-05-10 14:11:07 +0000 | [diff] [blame] | 729 | has_spi = 0; |
| 730 | /* GPIO47/SPI_CLK status */ |
| 731 | reg = pci_read_byte(smbus_dev, 0xA7); |
| 732 | reg &= 0x40; |
| 733 | printf_debug("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK"); |
| 734 | if (reg != 0x00) |
| 735 | has_spi = 0; |
| 736 | } |
| 737 | |
Carl-Daniel Hailfinger | b22918c | 2009-06-01 02:08:58 +0000 | [diff] [blame] | 738 | buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; |
| 739 | if (has_spi) { |
| 740 | buses_supported |= CHIP_BUSTYPE_SPI; |
Carl-Daniel Hailfinger | 1dfe0ff | 2009-05-31 17:57:34 +0000 | [diff] [blame] | 741 | spi_controller = SPI_CONTROLLER_SB600; |
Carl-Daniel Hailfinger | b22918c | 2009-06-01 02:08:58 +0000 | [diff] [blame] | 742 | } |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 743 | |
Carl-Daniel Hailfinger | 9862251 | 2009-05-15 23:36:23 +0000 | [diff] [blame] | 744 | /* Read ROM strap override register. */ |
| 745 | OUTB(0x8f, 0xcd6); |
| 746 | reg = INB(0xcd7); |
| 747 | reg &= 0x0e; |
| 748 | printf_debug("ROM strap override is %sactive", (reg & 0x02) ? "" : "not "); |
| 749 | if (reg & 0x02) { |
| 750 | switch ((reg & 0x0c) >> 2) { |
| 751 | case 0x00: |
| 752 | printf_debug(": LPC"); |
| 753 | break; |
| 754 | case 0x01: |
| 755 | printf_debug(": PCI"); |
| 756 | break; |
| 757 | case 0x02: |
| 758 | printf_debug(": FWH"); |
| 759 | break; |
| 760 | case 0x03: |
| 761 | printf_debug(": SPI"); |
| 762 | break; |
| 763 | } |
| 764 | } |
| 765 | printf_debug("\n"); |
| 766 | |
Carl-Daniel Hailfinger | 41d6bd9 | 2009-05-05 22:50:07 +0000 | [diff] [blame] | 767 | /* Force enable SPI ROM in SB600 PM register. |
| 768 | * If we enable SPI ROM here, we have to disable it after we leave. |
Zheng Bao | 284a600 | 2009-05-04 22:33:50 +0000 | [diff] [blame] | 769 | * But how can we know which ROM we are going to handle? So we have |
| 770 | * to trade off. We only access LPC ROM if we boot via LPC ROM. And |
Carl-Daniel Hailfinger | 41d6bd9 | 2009-05-05 22:50:07 +0000 | [diff] [blame] | 771 | * only SPI ROM if we boot via SPI ROM. If you want to access SPI on |
| 772 | * boards with LPC straps, you have to use the code below. |
Zheng Bao | 284a600 | 2009-05-04 22:33:50 +0000 | [diff] [blame] | 773 | */ |
| 774 | /* |
Jason Wang | a3f04be | 2008-11-28 21:36:51 +0000 | [diff] [blame] | 775 | OUTB(0x8f, 0xcd6); |
| 776 | OUTB(0x0e, 0xcd7); |
Zheng Bao | 284a600 | 2009-05-04 22:33:50 +0000 | [diff] [blame] | 777 | */ |
Marc Jones | 3af487d | 2008-10-15 17:50:29 +0000 | [diff] [blame] | 778 | |
| 779 | return 0; |
| 780 | } |
| 781 | |
Luc Verhaegen | 90e8e61 | 2009-05-26 09:48:28 +0000 | [diff] [blame] | 782 | static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name) |
| 783 | { |
Uwe Hermann | e9d04d4 | 2009-06-02 19:54:22 +0000 | [diff] [blame] | 784 | uint8_t tmp; |
Luc Verhaegen | 90e8e61 | 2009-05-26 09:48:28 +0000 | [diff] [blame] | 785 | |
Uwe Hermann | e9d04d4 | 2009-06-02 19:54:22 +0000 | [diff] [blame] | 786 | pci_write_byte(dev, 0x92, 0); |
Luc Verhaegen | 90e8e61 | 2009-05-26 09:48:28 +0000 | [diff] [blame] | 787 | |
Uwe Hermann | e9d04d4 | 2009-06-02 19:54:22 +0000 | [diff] [blame] | 788 | tmp = pci_read_byte(dev, 0x6d); |
| 789 | tmp |= 0x01; |
| 790 | pci_write_byte(dev, 0x6d, tmp); |
Luc Verhaegen | 90e8e61 | 2009-05-26 09:48:28 +0000 | [diff] [blame] | 791 | |
Uwe Hermann | e9d04d4 | 2009-06-02 19:54:22 +0000 | [diff] [blame] | 792 | return 0; |
Luc Verhaegen | 90e8e61 | 2009-05-26 09:48:28 +0000 | [diff] [blame] | 793 | } |
| 794 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 795 | static int enable_flash_ck804(struct pci_dev *dev, const char *name) |
Yinghai Lu | 952dfce | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 796 | { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 797 | uint8_t old, new; |
Yinghai Lu | 952dfce | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 798 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 799 | old = pci_read_byte(dev, 0x88); |
| 800 | new = old | 0xc0; |
| 801 | if (new != old) { |
| 802 | pci_write_byte(dev, 0x88, new); |
| 803 | if (pci_read_byte(dev, 0x88) != new) { |
| 804 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name); |
| 805 | } |
| 806 | } |
Yinghai Lu | 952dfce | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 807 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 808 | old = pci_read_byte(dev, 0x6d); |
| 809 | new = old | 0x01; |
| 810 | if (new == old) |
| 811 | return 0; |
| 812 | pci_write_byte(dev, 0x6d, new); |
| 813 | |
| 814 | if (pci_read_byte(dev, 0x6d) != new) { |
| 815 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); |
| 816 | return -1; |
| 817 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 818 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 819 | return 0; |
Yinghai Lu | 952dfce | 2005-07-06 17:13:46 +0000 | [diff] [blame] | 820 | } |
| 821 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 822 | /* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */ |
| 823 | static int enable_flash_sb400(struct pci_dev *dev, const char *name) |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 824 | { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 825 | uint8_t tmp; |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 826 | struct pci_dev *smbusdev; |
| 827 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 828 | /* Look for the SMBus device. */ |
Carl-Daniel Hailfinger | f6e3efb | 2009-05-06 00:35:31 +0000 | [diff] [blame] | 829 | smbusdev = pci_dev_find(0x1002, 0x4372); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 830 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 831 | if (!smbusdev) { |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 832 | fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n"); |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 833 | exit(1); |
| 834 | } |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 835 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 836 | /* Enable some SMBus stuff. */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 837 | tmp = pci_read_byte(smbusdev, 0x79); |
| 838 | tmp |= 0x01; |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 839 | pci_write_byte(smbusdev, 0x79, tmp); |
| 840 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 841 | /* Change southbridge. */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 842 | tmp = pci_read_byte(dev, 0x48); |
| 843 | tmp |= 0x21; |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 844 | pci_write_byte(dev, 0x48, tmp); |
| 845 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 846 | /* Now become a bit silly. */ |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 847 | tmp = INB(0xc6f); |
| 848 | OUTB(tmp, 0xeb); |
| 849 | OUTB(tmp, 0xeb); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 850 | tmp |= 0x40; |
Andriy Gapon | 65c1b86 | 2008-05-22 13:22:45 +0000 | [diff] [blame] | 851 | OUTB(tmp, 0xc6f); |
| 852 | OUTB(tmp, 0xeb); |
| 853 | OUTB(tmp, 0xeb); |
Stefan Reinauer | 86de283 | 2006-03-31 11:26:55 +0000 | [diff] [blame] | 854 | |
| 855 | return 0; |
| 856 | } |
| 857 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 858 | static int enable_flash_mcp55(struct pci_dev *dev, const char *name) |
Yinghai Lu | ca78297 | 2007-01-22 20:21:17 +0000 | [diff] [blame] | 859 | { |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 860 | uint8_t old, new, byte; |
| 861 | uint16_t word; |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 862 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 863 | /* Set the 0-16 MB enable bits. */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 864 | byte = pci_read_byte(dev, 0x88); |
| 865 | byte |= 0xff; /* 256K */ |
| 866 | pci_write_byte(dev, 0x88, byte); |
| 867 | byte = pci_read_byte(dev, 0x8c); |
| 868 | byte |= 0xff; /* 1M */ |
| 869 | pci_write_byte(dev, 0x8c, byte); |
| 870 | word = pci_read_word(dev, 0x90); |
Carl-Daniel Hailfinger | dca0ab1 | 2007-10-17 22:30:07 +0000 | [diff] [blame] | 871 | word |= 0x7fff; /* 16M */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 872 | pci_write_word(dev, 0x90, word); |
Luc Verhaegen | 8e3a600 | 2007-04-04 22:45:58 +0000 | [diff] [blame] | 873 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 874 | old = pci_read_byte(dev, 0x6d); |
| 875 | new = old | 0x01; |
| 876 | if (new == old) |
| 877 | return 0; |
| 878 | pci_write_byte(dev, 0x6d, new); |
Yinghai Lu | ca78297 | 2007-01-22 20:21:17 +0000 | [diff] [blame] | 879 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 880 | if (pci_read_byte(dev, 0x6d) != new) { |
Uwe Hermann | 394131e | 2008-10-18 21:14:13 +0000 | [diff] [blame] | 881 | printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 882 | return -1; |
| 883 | } |
Yinghai Lu | ca78297 | 2007-01-22 20:21:17 +0000 | [diff] [blame] | 884 | |
| 885 | return 0; |
Yinghai Lu | ca78297 | 2007-01-22 20:21:17 +0000 | [diff] [blame] | 886 | } |
| 887 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 888 | static int enable_flash_ht1000(struct pci_dev *dev, const char *name) |
Stefan Reinauer | c868b9e | 2007-06-05 10:28:39 +0000 | [diff] [blame] | 889 | { |
Uwe Hermann | e823ee0 | 2007-06-05 15:02:18 +0000 | [diff] [blame] | 890 | uint8_t byte; |
Stefan Reinauer | c868b9e | 2007-06-05 10:28:39 +0000 | [diff] [blame] | 891 | |
Uwe Hermann | e823ee0 | 2007-06-05 15:02:18 +0000 | [diff] [blame] | 892 | /* Set the 4MB enable bit. */ |
Stefan Reinauer | c868b9e | 2007-06-05 10:28:39 +0000 | [diff] [blame] | 893 | byte = pci_read_byte(dev, 0x41); |
| 894 | byte |= 0x0e; |
| 895 | pci_write_byte(dev, 0x41, byte); |
| 896 | |
| 897 | byte = pci_read_byte(dev, 0x43); |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 898 | byte |= (1 << 4); |
Stefan Reinauer | c868b9e | 2007-06-05 10:28:39 +0000 | [diff] [blame] | 899 | pci_write_byte(dev, 0x43, byte); |
| 900 | |
Stefan Reinauer | c868b9e | 2007-06-05 10:28:39 +0000 | [diff] [blame] | 901 | return 0; |
| 902 | } |
| 903 | |
Stefan Reinauer | 9a6d176 | 2008-12-03 21:24:40 +0000 | [diff] [blame] | 904 | /** |
| 905 | * Usually on the x86 architectures (and on other PC-like platforms like some |
| 906 | * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD |
| 907 | * Elan SC520 only a small piece of the system flash is mapped there, but the |
| 908 | * complete flash is mapped somewhere below 1G. The position can be determined |
| 909 | * by the BOOTCS PAR register. |
| 910 | */ |
| 911 | static int get_flashbase_sc520(struct pci_dev *dev, const char *name) |
| 912 | { |
| 913 | int i, bootcs_found = 0; |
| 914 | uint32_t parx = 0; |
| 915 | void *mmcr; |
| 916 | |
| 917 | /* 1. Map MMCR */ |
Stefan Reinauer | 0593f21 | 2009-01-26 01:10:48 +0000 | [diff] [blame] | 918 | mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize()); |
Stefan Reinauer | 9a6d176 | 2008-12-03 21:24:40 +0000 | [diff] [blame] | 919 | |
| 920 | /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for |
| 921 | * BOOTCS region (PARx[31:29] = 100b)e |
| 922 | */ |
| 923 | for (i = 0x88; i <= 0xc4; i += 4) { |
Carl-Daniel Hailfinger | 78185dc | 2009-05-17 15:49:24 +0000 | [diff] [blame] | 924 | parx = mmio_readl(mmcr + i); |
Stefan Reinauer | 9a6d176 | 2008-12-03 21:24:40 +0000 | [diff] [blame] | 925 | if ((parx >> 29) == 4) { |
| 926 | bootcs_found = 1; |
| 927 | break; /* BOOTCS found */ |
| 928 | } |
| 929 | } |
| 930 | |
| 931 | /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0] |
| 932 | * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0] |
| 933 | */ |
| 934 | if (bootcs_found) { |
| 935 | if (parx & (1 << 25)) { |
| 936 | parx &= (1 << 14) - 1; /* Mask [13:0] */ |
| 937 | flashbase = parx << 16; |
| 938 | } else { |
| 939 | parx &= (1 << 18) - 1; /* Mask [17:0] */ |
| 940 | flashbase = parx << 12; |
| 941 | } |
| 942 | } else { |
| 943 | printf("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n"); |
| 944 | } |
| 945 | |
| 946 | /* 4. Clean up */ |
Uwe Hermann | 7b2969b | 2009-04-15 10:52:49 +0000 | [diff] [blame] | 947 | munmap(mmcr, getpagesize()); |
Stefan Reinauer | 9a6d176 | 2008-12-03 21:24:40 +0000 | [diff] [blame] | 948 | return 0; |
| 949 | } |
| 950 | |
Uwe Hermann | 4179d29 | 2009-05-08 17:50:51 +0000 | [diff] [blame] | 951 | /* Please keep this list alphabetically sorted by vendor/device. */ |
Uwe Hermann | 05fab75 | 2009-05-16 23:42:17 +0000 | [diff] [blame] | 952 | const struct penable chipset_enables[] = { |
Uwe Hermann | 4179d29 | 2009-05-08 17:50:51 +0000 | [diff] [blame] | 953 | {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533}, |
| 954 | {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111}, |
| 955 | {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111}, |
| 956 | {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530}, |
| 957 | {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536}, |
| 958 | {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520}, |
| 959 | {0x1002, 0x438D, OK, "AMD", "SB600", enable_flash_sb600}, |
| 960 | {0x1002, 0x439d, OK, "AMD", "SB700", enable_flash_sb600}, |
| 961 | {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100}, |
| 962 | {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400}, |
| 963 | {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000}, |
Uwe Hermann | b003991 | 2009-05-07 13:24:49 +0000 | [diff] [blame] | 964 | {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4}, |
Uwe Hermann | 4179d29 | 2009-05-08 17:50:51 +0000 | [diff] [blame] | 965 | {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich_4e}, |
| 966 | {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich_dc}, |
| 967 | {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7}, |
Uwe Hermann | b003991 | 2009-05-07 13:24:49 +0000 | [diff] [blame] | 968 | {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e}, |
Uwe Hermann | 4179d29 | 2009-05-08 17:50:51 +0000 | [diff] [blame] | 969 | {0x8086, 0x3a18, OK, "Intel", "ICH10", enable_flash_ich10}, |
| 970 | {0x8086, 0x3a1a, OK, "Intel", "ICH10D", enable_flash_ich10}, |
| 971 | {0x8086, 0x3a14, OK, "Intel", "ICH10DO", enable_flash_ich10}, |
| 972 | {0x8086, 0x3a16, OK, "Intel", "ICH10R", enable_flash_ich10}, |
Uwe Hermann | b003991 | 2009-05-07 13:24:49 +0000 | [diff] [blame] | 973 | {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e}, |
| 974 | {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich_4e}, |
Uwe Hermann | b003991 | 2009-05-07 13:24:49 +0000 | [diff] [blame] | 975 | {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich_4e}, |
Uwe Hermann | 4179d29 | 2009-05-08 17:50:51 +0000 | [diff] [blame] | 976 | {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich_4e}, |
Uwe Hermann | b003991 | 2009-05-07 13:24:49 +0000 | [diff] [blame] | 977 | {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich_4e}, |
| 978 | {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich_4e}, |
| 979 | {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich_4e}, |
Uwe Hermann | b003991 | 2009-05-07 13:24:49 +0000 | [diff] [blame] | 980 | {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich_dc}, |
| 981 | {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich_dc}, |
Uwe Hermann | b003991 | 2009-05-07 13:24:49 +0000 | [diff] [blame] | 982 | {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7}, |
| 983 | {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7}, |
| 984 | {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7}, |
| 985 | {0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7}, |
Uwe Hermann | 4179d29 | 2009-05-08 17:50:51 +0000 | [diff] [blame] | 986 | {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e}, |
Uwe Hermann | b003991 | 2009-05-07 13:24:49 +0000 | [diff] [blame] | 987 | {0x8086, 0x2812, OK, "Intel", "ICH8DH", enable_flash_ich8}, |
| 988 | {0x8086, 0x2814, OK, "Intel", "ICH8DO", enable_flash_ich8}, |
Uwe Hermann | 4179d29 | 2009-05-08 17:50:51 +0000 | [diff] [blame] | 989 | {0x8086, 0x2810, OK, "Intel", "ICH8/ICH8R", enable_flash_ich8}, |
Uwe Hermann | b003991 | 2009-05-07 13:24:49 +0000 | [diff] [blame] | 990 | {0x8086, 0x2815, OK, "Intel", "ICH8M", enable_flash_ich8}, |
Uwe Hermann | 4179d29 | 2009-05-08 17:50:51 +0000 | [diff] [blame] | 991 | {0x8086, 0x2811, OK, "Intel", "ICH8M-E", enable_flash_ich8}, |
| 992 | {0x8086, 0x2918, OK, "Intel", "ICH9", enable_flash_ich9}, |
Uwe Hermann | b003991 | 2009-05-07 13:24:49 +0000 | [diff] [blame] | 993 | {0x8086, 0x2912, OK, "Intel", "ICH9DH", enable_flash_ich9}, |
| 994 | {0x8086, 0x2914, OK, "Intel", "ICH9DO", enable_flash_ich9}, |
Uwe Hermann | b003991 | 2009-05-07 13:24:49 +0000 | [diff] [blame] | 995 | {0x8086, 0x2919, OK, "Intel", "ICH9M", enable_flash_ich9}, |
Uwe Hermann | 4179d29 | 2009-05-08 17:50:51 +0000 | [diff] [blame] | 996 | {0x8086, 0x2917, OK, "Intel", "ICH9M-E", enable_flash_ich9}, |
| 997 | {0x8086, 0x2916, OK, "Intel", "ICH9R", enable_flash_ich9}, |
| 998 | {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4}, |
| 999 | {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4}, |
| 1000 | {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4}, |
| 1001 | {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4}, |
Uwe Hermann | b003991 | 2009-05-07 13:24:49 +0000 | [diff] [blame] | 1002 | {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */ |
| 1003 | {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */ |
Luc Verhaegen | 90e8e61 | 2009-05-26 09:48:28 +0000 | [diff] [blame] | 1004 | {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2}, |
Uwe Hermann | eac1016 | 2008-03-13 18:52:51 +0000 | [diff] [blame] | 1005 | /* Slave, should not be here, to fix known bug for A01. */ |
Uwe Hermann | b003991 | 2009-05-07 13:24:49 +0000 | [diff] [blame] | 1006 | {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804}, |
| 1007 | {0x10de, 0x0260, NT, "NVIDIA", "MCP51", enable_flash_ck804}, |
| 1008 | {0x10de, 0x0261, NT, "NVIDIA", "MCP51", enable_flash_ck804}, |
| 1009 | {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804}, |
| 1010 | {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804}, |
| 1011 | {0x10de, 0x0360, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/ |
| 1012 | {0x10de, 0x0361, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ |
| 1013 | {0x10de, 0x0362, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ |
| 1014 | {0x10de, 0x0363, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ |
| 1015 | {0x10de, 0x0364, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ |
| 1016 | {0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ |
| 1017 | {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */ |
| 1018 | {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */ |
| 1019 | {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp55}, |
Uwe Hermann | 4179d29 | 2009-05-08 17:50:51 +0000 | [diff] [blame] | 1020 | {0x1039, 0x0008, OK, "SiS", "SiS5595", enable_flash_sis5595}, |
| 1021 | {0x1039, 0x0630, NT, "SiS", "SiS630", enable_flash_sis630}, |
| 1022 | {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x}, |
| 1023 | {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x}, |
| 1024 | {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x}, |
| 1025 | {0x1106, 0x3227, OK, "VIA", "VT8237", enable_flash_vt823x}, |
| 1026 | {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x}, |
| 1027 | {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi}, |
Arjan Koers | 8dfea83 | 2009-06-15 00:03:37 +0000 | [diff] [blame] | 1028 | {0x1106, 0x8353, OK, "VIA", "VX800", enable_flash_vt8237s_spi}, |
Uwe Hermann | 4179d29 | 2009-05-08 17:50:51 +0000 | [diff] [blame] | 1029 | {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111}, |
| 1030 | {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111}, |
Uwe Hermann | 05fab75 | 2009-05-16 23:42:17 +0000 | [diff] [blame] | 1031 | |
| 1032 | {}, |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 1033 | }; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 1034 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1035 | int chipset_flash_enable(void) |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 1036 | { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1037 | struct pci_dev *dev = 0; |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 1038 | int ret = -2; /* Nothing! */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1039 | int i; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 1040 | |
Uwe Hermann | 372eeb5 | 2007-12-04 21:49:06 +0000 | [diff] [blame] | 1041 | /* Now let's try to find the chipset we have... */ |
Uwe Hermann | 05fab75 | 2009-05-16 23:42:17 +0000 | [diff] [blame] | 1042 | for (i = 0; chipset_enables[i].vendor_name != NULL; i++) { |
| 1043 | dev = pci_dev_find(chipset_enables[i].vendor_id, |
| 1044 | chipset_enables[i].device_id); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1045 | if (dev) |
| 1046 | break; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 1047 | } |
| 1048 | |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1049 | if (dev) { |
Uwe Hermann | b003991 | 2009-05-07 13:24:49 +0000 | [diff] [blame] | 1050 | printf("Found chipset \"%s %s\", enabling flash write... ", |
Uwe Hermann | 05fab75 | 2009-05-16 23:42:17 +0000 | [diff] [blame] | 1051 | chipset_enables[i].vendor_name, |
| 1052 | chipset_enables[i].device_name); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1053 | |
Uwe Hermann | 05fab75 | 2009-05-16 23:42:17 +0000 | [diff] [blame] | 1054 | ret = chipset_enables[i].doit(dev, |
| 1055 | chipset_enables[i].device_name); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1056 | if (ret) |
Uwe Hermann | a502dce | 2007-10-17 23:55:15 +0000 | [diff] [blame] | 1057 | printf("FAILED!\n"); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1058 | else |
Uwe Hermann | ac30934 | 2007-10-10 17:42:20 +0000 | [diff] [blame] | 1059 | printf("OK.\n"); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 1060 | } |
| 1061 | |
| 1062 | return ret; |
Ollie Lho | cbbf125 | 2004-03-17 22:22:08 +0000 | [diff] [blame] | 1063 | } |