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Adam Kaufman064b1f22007-02-06 19:47:50 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Adam Kaufman064b1f22007-02-06 19:47:50 +00003 *
Uwe Hermannd22a1d42007-09-09 20:21:05 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2000 Ronald G. Minnich <rminnich@gmail.com>
6 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
Adam Kaufman064b1f22007-02-06 19:47:50 +00007 *
Uwe Hermannd1107642007-08-29 17:52:32 +00008 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
Adam Kaufman064b1f22007-02-06 19:47:50 +000012 *
Uwe Hermannd1107642007-08-29 17:52:32 +000013 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
Adam Kaufman064b1f22007-02-06 19:47:50 +000017 *
Uwe Hermannd1107642007-08-29 17:52:32 +000018 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Adam Kaufman064b1f22007-02-06 19:47:50 +000021 */
22
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +000023#ifndef __FLASH_H__
24#define __FLASH_H__ 1
25
Adam Kaufman064b1f22007-02-06 19:47:50 +000026#if defined(__GLIBC__)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000027#include <sys/io.h>
Adam Kaufman064b1f22007-02-06 19:47:50 +000028#endif
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000029#include <unistd.h>
Ollie Lho184a4042005-11-26 21:55:36 +000030#include <stdint.h>
Uwe Hermann0846f892007-08-23 13:34:59 +000031#include <stdio.h>
Christian Ruppert0cdb0312009-05-14 18:57:26 +000032#include <pci/pci.h>
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000033
Carl-Daniel Hailfinger9abf5292009-05-01 16:34:32 +000034/* for iopl and outb under Solaris */
35#if defined (__sun) && (defined(__i386) || defined(__amd64))
36#include <strings.h>
37#include <sys/sysi86.h>
38#include <sys/psw.h>
39#include <asm/sunddi.h>
40#endif
41
Stefan Reinauerf79edb92009-01-26 01:23:31 +000042#if (defined(__MACH__) && defined(__APPLE__))
43#define __DARWIN__
44#endif
45
Patrick Georgi60622e22009-04-28 12:56:04 +000046#if defined(__FreeBSD__) || defined(__DragonFly__)
Andriy Gapon65c1b862008-05-22 13:22:45 +000047 #include <machine/cpufunc.h>
48 #define off64_t off_t
49 #define lseek64 lseek
50 #define OUTB(x, y) do { u_int tmp = (y); outb(tmp, (x)); } while (0)
51 #define OUTW(x, y) do { u_int tmp = (y); outw(tmp, (x)); } while (0)
52 #define OUTL(x, y) do { u_int tmp = (y); outl(tmp, (x)); } while (0)
53 #define INB(x) __extension__ ({ u_int tmp = (x); inb(tmp); })
54 #define INW(x) __extension__ ({ u_int tmp = (x); inw(tmp); })
55 #define INL(x) __extension__ ({ u_int tmp = (x); inl(tmp); })
56#else
Stefan Reinauerf79edb92009-01-26 01:23:31 +000057#if defined(__DARWIN__)
58 #include <DirectIO/darwinio.h>
59 #define off64_t off_t
60 #define lseek64 lseek
61#endif
Carl-Daniel Hailfinger9abf5292009-05-01 16:34:32 +000062#if defined (__sun) && (defined(__i386) || defined(__amd64))
63 /* Note different order for outb */
64 #define OUTB(x,y) outb(y, x)
65 #define OUTW(x,y) outw(y, x)
66 #define OUTL(x,y) outl(y, x)
67 #define INB inb
68 #define INW inw
69 #define INL inl
70#else
Andriy Gapon65c1b862008-05-22 13:22:45 +000071 #define OUTB outb
72 #define OUTW outw
73 #define OUTL outl
74 #define INB inb
75 #define INW inw
76 #define INL inl
77#endif
Carl-Daniel Hailfinger9abf5292009-05-01 16:34:32 +000078#endif
Andriy Gapon65c1b862008-05-22 13:22:45 +000079
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000080typedef unsigned long chipaddr;
81
Carl-Daniel Hailfinger702218d2009-05-08 17:43:22 +000082extern int programmer;
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +000083#define PROGRAMMER_INTERNAL 0x00
84#define PROGRAMMER_DUMMY 0x01
Uwe Hermannb4dcb712009-05-13 11:36:06 +000085#define PROGRAMMER_NIC3COM 0x02
Rudolf Marek68720c72009-05-17 19:39:27 +000086#define PROGRAMMER_SATASII 0x03
Carl-Daniel Hailfingerb8afecd2009-05-31 18:00:57 +000087#define PROGRAMMER_IT87SPI 0x04
Carl-Daniel Hailfinger702218d2009-05-08 17:43:22 +000088
89struct programmer_entry {
90 const char *vendor;
91 const char *name;
92
93 int (*init) (void);
94 int (*shutdown) (void);
95
Uwe Hermannd1129ac2009-05-28 15:07:42 +000096 void * (*map_flash_region) (const char *descr, unsigned long phys_addr,
97 size_t len);
Carl-Daniel Hailfinger1455b2b2009-05-11 14:13:25 +000098 void (*unmap_flash_region) (void *virt_addr, size_t len);
99
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000100 void (*chip_writeb) (uint8_t val, chipaddr addr);
101 void (*chip_writew) (uint16_t val, chipaddr addr);
102 void (*chip_writel) (uint32_t val, chipaddr addr);
Carl-Daniel Hailfinger0bd2a2b2009-06-05 18:32:07 +0000103 void (*chip_writen) (uint8_t *buf, chipaddr addr, size_t len);
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000104 uint8_t (*chip_readb) (const chipaddr addr);
105 uint16_t (*chip_readw) (const chipaddr addr);
106 uint32_t (*chip_readl) (const chipaddr addr);
Carl-Daniel Hailfinger0bd2a2b2009-06-05 18:32:07 +0000107 void (*chip_readn) (uint8_t *buf, const chipaddr addr, size_t len);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000108 void (*delay) (int usecs);
Carl-Daniel Hailfinger702218d2009-05-08 17:43:22 +0000109};
110
111extern const struct programmer_entry programmer_table[];
112
Uwe Hermann09e04f72009-05-16 22:36:00 +0000113int programmer_init(void);
114int programmer_shutdown(void);
115void *programmer_map_flash_region(const char *descr, unsigned long phys_addr,
116 size_t len);
117void programmer_unmap_flash_region(void *virt_addr, size_t len);
118void chip_writeb(uint8_t val, chipaddr addr);
119void chip_writew(uint16_t val, chipaddr addr);
120void chip_writel(uint32_t val, chipaddr addr);
Carl-Daniel Hailfinger0bd2a2b2009-06-05 18:32:07 +0000121void chip_writen(uint8_t *buf, chipaddr addr, size_t len);
Uwe Hermann09e04f72009-05-16 22:36:00 +0000122uint8_t chip_readb(const chipaddr addr);
123uint16_t chip_readw(const chipaddr addr);
124uint32_t chip_readl(const chipaddr addr);
Carl-Daniel Hailfinger0bd2a2b2009-06-05 18:32:07 +0000125void chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000126void programmer_delay(int usecs);
Carl-Daniel Hailfinger61a8bd22009-03-05 19:24:22 +0000127
Uwe Hermanne5ac1642008-03-12 11:54:51 +0000128#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
129
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000130enum chipbustype {
Carl-Daniel Hailfinger3504b532009-06-01 00:02:11 +0000131 CHIP_BUSTYPE_NONE = 0,
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000132 CHIP_BUSTYPE_PARALLEL = 1 << 0,
133 CHIP_BUSTYPE_LPC = 1 << 1,
134 CHIP_BUSTYPE_FWH = 1 << 2,
135 CHIP_BUSTYPE_SPI = 1 << 3,
136 CHIP_BUSTYPE_NONSPI = CHIP_BUSTYPE_PARALLEL | CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH,
137 CHIP_BUSTYPE_UNKNOWN = CHIP_BUSTYPE_PARALLEL | CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI,
138};
139
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000140struct flashchip {
Uwe Hermann76158682008-03-14 23:55:58 +0000141 const char *vendor;
Uwe Hermann372eeb52007-12-04 21:49:06 +0000142 const char *name;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000143
144 enum chipbustype bustype;
145
Uwe Hermann394131e2008-10-18 21:14:13 +0000146 /*
147 * With 32bit manufacture_id and model_id we can cover IDs up to
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000148 * (including) the 4th bank of JEDEC JEP106W Standard Manufacturer's
149 * Identification code.
150 */
151 uint32_t manufacture_id;
152 uint32_t model_id;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000153
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000154 int total_size;
155 int page_size;
156
Uwe Hermann394131e2008-10-18 21:14:13 +0000157 /*
158 * Indicate if flashrom has been tested with this flash chip and if
Peter Stuge1159d582008-05-03 04:34:37 +0000159 * everything worked correctly.
160 */
161 uint32_t tested;
162
Uwe Hermann0b7afe62007-04-01 19:44:21 +0000163 int (*probe) (struct flashchip *flash);
Maciej Pijankac6e11112009-06-03 14:46:22 +0000164
165 /* Delay after "enter/exit ID mode" commands in microseconds. */
166 int probe_timing;
Uwe Hermann0b7afe62007-04-01 19:44:21 +0000167 int (*erase) (struct flashchip *flash);
168 int (*write) (struct flashchip *flash, uint8_t *buf);
169 int (*read) (struct flashchip *flash, uint8_t *buf);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000170
Uwe Hermann372eeb52007-12-04 21:49:06 +0000171 /* Some flash devices have an additional register space. */
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000172 chipaddr virtual_memory;
173 chipaddr virtual_registers;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000174};
175
Peter Stuge1159d582008-05-03 04:34:37 +0000176#define TEST_UNTESTED 0
177
Uwe Hermannd1129ac2009-05-28 15:07:42 +0000178#define TEST_OK_PROBE (1 << 0)
179#define TEST_OK_READ (1 << 1)
180#define TEST_OK_ERASE (1 << 2)
181#define TEST_OK_WRITE (1 << 3)
182#define TEST_OK_PR (TEST_OK_PROBE | TEST_OK_READ)
183#define TEST_OK_PRE (TEST_OK_PROBE | TEST_OK_READ | TEST_OK_ERASE)
184#define TEST_OK_PREW (TEST_OK_PROBE | TEST_OK_READ | TEST_OK_ERASE | TEST_OK_WRITE)
Peter Stuge1159d582008-05-03 04:34:37 +0000185#define TEST_OK_MASK 0x0f
186
Uwe Hermannd1129ac2009-05-28 15:07:42 +0000187#define TEST_BAD_PROBE (1 << 4)
188#define TEST_BAD_READ (1 << 5)
189#define TEST_BAD_ERASE (1 << 6)
190#define TEST_BAD_WRITE (1 << 7)
191#define TEST_BAD_PREW (TEST_BAD_PROBE | TEST_BAD_READ | TEST_BAD_ERASE | TEST_BAD_WRITE)
Peter Stuge1159d582008-05-03 04:34:37 +0000192#define TEST_BAD_MASK 0xf0
193
Maciej Pijankac6e11112009-06-03 14:46:22 +0000194/* Timing used in probe routines. ZERO is -2 to differentiate between an unset
195 * field and zero delay.
196 *
197 * SPI devices will always have zero delay and ignore this field.
198 */
199#define TIMING_FIXME -1
200/* this is intentionally same value as fixme */
201#define TIMING_IGNORED -1
202#define TIMING_ZERO -2
203
Ollie Lho184a4042005-11-26 21:55:36 +0000204extern struct flashchip flashchips[];
205
Uwe Hermann05fab752009-05-16 23:42:17 +0000206struct penable {
207 uint16_t vendor_id;
208 uint16_t device_id;
209 int status;
210 const char *vendor_name;
211 const char *device_name;
212 int (*doit) (struct pci_dev *dev, const char *name);
213};
214
215extern const struct penable chipset_enables[];
216
217struct board_pciid_enable {
218 /* Any device, but make it sensible, like the ISA bridge. */
219 uint16_t first_vendor;
220 uint16_t first_device;
221 uint16_t first_card_vendor;
222 uint16_t first_card_device;
223
224 /* Any device, but make it sensible, like
225 * the host bridge. May be NULL.
226 */
227 uint16_t second_vendor;
228 uint16_t second_device;
229 uint16_t second_card_vendor;
230 uint16_t second_card_device;
231
232 /* The vendor / part name from the coreboot table. */
233 const char *lb_vendor;
234 const char *lb_part;
235
236 const char *vendor_name;
237 const char *board_name;
238
239 int (*enable) (const char *name);
240};
241
242extern struct board_pciid_enable board_pciid_enables[];
243
244struct board_info {
245 const char *vendor;
246 const char *name;
247};
248
249extern const struct board_info boards_ok[];
250extern const struct board_info boards_bad[];
251
Uwe Hermann372eeb52007-12-04 21:49:06 +0000252/*
253 * Please keep this list sorted alphabetically by manufacturer. The first
Uwe Hermannaf2b52d2007-04-01 20:00:32 +0000254 * entry of each section should be the manufacturer ID, followed by the
255 * list of devices from that manufacturer (sorted by device IDs).
Uwe Hermann372eeb52007-12-04 21:49:06 +0000256 *
Carl-Daniel Hailfingere973b052008-01-04 16:22:09 +0000257 * All LPC/FWH parts (parallel flash) have 8-bit device IDs if there is no
258 * continuation code.
Carl-Daniel Hailfinger6a0a25c2008-11-28 23:45:27 +0000259 * SPI parts have 16-bit device IDs if they support RDID.
Uwe Hermannaf2b52d2007-04-01 20:00:32 +0000260 */
261
Carl-Daniel Hailfingere973b052008-01-04 16:22:09 +0000262#define GENERIC_DEVICE_ID 0xffff /* Only match the vendor ID */
263
Carl-Daniel Hailfingerc2a18452007-12-31 01:18:26 +0000264#define ALLIANCE_ID 0x52 /* Alliance Semiconductor */
Peter Lemenkov539478d2007-10-22 20:36:16 +0000265
Uwe Hermannaf2b52d2007-04-01 20:00:32 +0000266#define AMD_ID 0x01 /* AMD */
Mats Erik Anderssoncbfed282008-10-07 12:21:12 +0000267#define AM_29F002BT 0xB0
268#define AM_29F002BB 0x34
Uwe Hermann0b7afe62007-04-01 19:44:21 +0000269#define AM_29F040B 0xA4
Mateusz Murawski5bae4382009-06-02 00:38:14 +0000270#define AM_29F080B 0xD5
Peter Lemenkov220e26b2007-10-25 04:11:11 +0000271#define AM_29LV040B 0x4F
Mateusz Murawski5bae4382009-06-02 00:38:14 +0000272#define AM_29LV081B 0x38
Uwe Hermann0b7afe62007-04-01 19:44:21 +0000273#define AM_29F016D 0xAD
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000274
Carl-Daniel Hailfingerc2a18452007-12-31 01:18:26 +0000275#define AMIC_ID 0x7F37 /* AMIC */
Carl-Daniel Hailfinger78c6dfe2008-05-12 14:25:31 +0000276#define AMIC_ID_NOPREFIX 0x37 /* AMIC */
Rudolf Marekdcf46532008-05-22 13:42:23 +0000277#define AMIC_A25L40P 0x2013
Carl-Daniel Hailfinger8b114392008-07-06 23:04:01 +0000278#define AMIC_A29002B 0x0d
279#define AMIC_A29002T 0x8c
280#define AMIC_A29040B 0x86
Jens Kuehnelb9f61742008-06-18 13:36:34 +0000281#define AMIC_A49LF040A 0x9d
Peter Lemenkov539478d2007-10-22 20:36:16 +0000282
Carl-Daniel Hailfingercbdd4f02009-05-06 21:54:22 +0000283/* This chip vendor/device ID is probably a misinterpreted LHA header. */
Carl-Daniel Hailfingerc2a18452007-12-31 01:18:26 +0000284#define ASD_ID 0x25 /* ASD, not listed in JEP106W */
Uwe Hermann0b7afe62007-04-01 19:44:21 +0000285#define ASD_AE49F2008 0x52
Stefan Reinaueref54aba2006-11-21 23:51:08 +0000286
Uwe Hermannaf2b52d2007-04-01 20:00:32 +0000287#define ATMEL_ID 0x1F /* Atmel */
Carl-Daniel Hailfinger4e84dfb2008-05-14 04:27:02 +0000288#define AT_25DF021 0x4300
289#define AT_25DF041A 0x4401
290#define AT_25DF081 0x4502
291#define AT_25DF161 0x4602
292#define AT_25DF321 0x4700 /* also 26DF321 */
293#define AT_25DF321A 0x4701
294#define AT_25DF641 0x4800
Carl-Daniel Hailfingerd54ef6e2008-11-15 13:55:43 +0000295#define AT_25F512A 0x65 /* Needs special RDID. AT25F512A_RDID 15 1d */
296#define AT_25F512B 0x6500
297#define AT_25FS010 0x6601
298#define AT_25FS040 0x6604
Carl-Daniel Hailfinger4e84dfb2008-05-14 04:27:02 +0000299#define AT_26DF041 0x4400
300#define AT_26DF081 0x4500 /* guessed, no datasheet available */
301#define AT_26DF081A 0x4501
302#define AT_26DF161 0x4600
303#define AT_26DF161A 0x4601
Carl-Daniel Hailfingerd54ef6e2008-11-15 13:55:43 +0000304#define AT_26DF321 0x4700 /* also 25DF321 */
305#define AT_26F004 0x0400
Uwe Hermannaf2b52d2007-04-01 20:00:32 +0000306#define AT_29C040A 0xA4
Uwe Hermann8403ccb2009-05-16 21:39:19 +0000307#define AT_29C010A 0xD5
Uwe Hermannd7f48062007-04-28 02:22:59 +0000308#define AT_29C020 0xDA
Maciej Pijankabc2bbd22009-06-02 16:45:59 +0000309#define AT_29C512 0x5D
Carl-Daniel Hailfingerd54ef6e2008-11-15 13:55:43 +0000310#define AT_45BR3214B /* No ID available */
311#define AT_45CS1282 0x2920
312#define AT_45D011 /* No ID available */
313#define AT_45D021A /* No ID available */
314#define AT_45D041A /* No ID available */
315#define AT_45D081A /* No ID available */
316#define AT_45D161 /* No ID available */
317#define AT_45DB011 /* No ID available */
318#define AT_45DB011B /* No ID available */
319#define AT_45DB011D 0x2200
320#define AT_45DB021A /* No ID available */
321#define AT_45DB021B /* No ID available */
322#define AT_45DB021D 0x2300
323#define AT_45DB041A /* No ID available */
324#define AT_45DB041D 0x2400
325#define AT_45DB081A /* No ID available */
326#define AT_45DB081D 0x2500
327#define AT_45DB161 /* No ID available */
328#define AT_45DB161B /* No ID available */
329#define AT_45DB161D 0x2600
330#define AT_45DB321 /* No ID available */
331#define AT_45DB321B /* No ID available */
332#define AT_45DB321C 0x2700
333#define AT_45DB321D 0x2701 /* Buggy data sheet */
334#define AT_45DB642 /* No ID available */
335#define AT_45DB642D 0x2800
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000336#define AT_49BV512 0x03
Frederico Silva4bcf1752007-12-10 16:57:59 +0000337#define AT_49F002N 0x07 /* for AT49F002(N) */
338#define AT_49F002NT 0x08 /* for AT49F002(N)T */
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000339
Peter Lemenkov539478d2007-10-22 20:36:16 +0000340#define CATALYST_ID 0x31 /* Catalyst */
341
Uwe Hermann394131e2008-10-18 21:14:13 +0000342#define EMST_ID 0x8C /* EMST / EFST Elite Flash Storage */
Peter Lemenkov539478d2007-10-22 20:36:16 +0000343#define EMST_F49B002UA 0x00
344
Uwe Hermann372eeb52007-12-04 21:49:06 +0000345/*
346 * EN25 chips are SPI, first byte of device ID is memory type,
347 * second byte of device ID is log(bitsize)-9.
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000348 * Vendor and device ID of EN29 series are both prefixed with 0x7F, which
349 * is the continuation code for IDs in bank 2.
350 * Vendor ID of EN25 series is NOT prefixed with 0x7F, this results in
351 * a collision with Mitsubishi. Mitsubishi once manufactured flash chips.
352 * Let's hope they are not manufacturing SPI flash chips as well.
Uwe Hermann372eeb52007-12-04 21:49:06 +0000353 */
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000354#define EON_ID 0x7F1C /* EON Silicon Devices */
355#define EON_ID_NOPREFIX 0x1C /* EON, missing 0x7F prefix */
Carl-Daniel Hailfingere1514992007-10-02 15:49:25 +0000356#define EN_25B05 0x2010 /* 2^19 kbit or 2^16 kByte */
357#define EN_25B10 0x2011
358#define EN_25B20 0x2012
359#define EN_25B40 0x2013
360#define EN_25B80 0x2014
361#define EN_25B16 0x2015
362#define EN_25B32 0x2016
Carl-Daniel Hailfinger80243c92009-06-05 20:53:07 +0000363#define EN_25B64 0x2017
364#define EN_25F40 0x3113
365#define EN_25F80 0x3114
366#define EN_25F16 0x3115
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000367#define EN_29F512 0x7F21
368#define EN_29F010 0x7F20
369#define EN_29F040A 0x7F04
370#define EN_29LV010 0x7F6E
371#define EN_29LV040A 0x7F4F /* EN_29LV040(A) */
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000372#define EN_29F002T 0x7F92 /* Also EN29F002A */
373#define EN_29F002B 0x7F97 /* Also EN29F002AN */
Carl-Daniel Hailfingere1514992007-10-02 15:49:25 +0000374
Peter Lemenkov539478d2007-10-22 20:36:16 +0000375#define FUJITSU_ID 0x04 /* Fujitsu */
Carl-Daniel Hailfinger1c2ec282008-11-04 12:11:12 +0000376#define MBM29F400BC 0xAB
377#define MBM29F400TC 0x23
378#define MBM29F004BC 0x7B
379#define MBM29F004TC 0x77
Peter Lemenkov539478d2007-10-22 20:36:16 +0000380
381#define HYUNDAI_ID 0xAD /* Hyundai */
382
Carl-Daniel Hailfingerc2a18452007-12-31 01:18:26 +0000383#define IMT_ID 0x7F1F /* Integrated Memory Technologies */
384#define IM_29F004B 0xAE
385#define IM_29F004T 0xAF
Peter Lemenkov539478d2007-10-22 20:36:16 +0000386
387#define INTEL_ID 0x89 /* Intel */
Mateusz Murawskie33890d2009-06-12 11:45:10 +0000388#define I_82802AB 0xAD
389#define I_82802AC 0xAC
Urja Rannikkoebd7b832009-05-29 12:55:31 +0000390#define P28F001BXT 0x94 /* 28F001BX-T */
391#define P28F001BXB 0x95 /* 28F001BX-B */
Peter Lemenkov539478d2007-10-22 20:36:16 +0000392
Carl-Daniel Hailfingerc2a18452007-12-31 01:18:26 +0000393#define ISSI_ID 0xD5 /* ISSI Integrated Silicon Solutions */
Peter Lemenkov539478d2007-10-22 20:36:16 +0000394
Uwe Hermann372eeb52007-12-04 21:49:06 +0000395/*
396 * MX25 chips are SPI, first byte of device ID is memory type,
397 * second byte of device ID is log(bitsize)-9.
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000398 * Generalplus SPI chips seem to be compatible with Macronix
399 * and use the same set of IDs.
Uwe Hermann372eeb52007-12-04 21:49:06 +0000400 */
Uwe Hermannaf2b52d2007-04-01 20:00:32 +0000401#define MX_ID 0xC2 /* Macronix (MX) */
Carl-Daniel Hailfingere1514992007-10-02 15:49:25 +0000402#define MX_25L512 0x2010 /* 2^19 kbit or 2^16 kByte */
403#define MX_25L1005 0x2011
404#define MX_25L2005 0x2012
405#define MX_25L4005 0x2013 /* MX25L4005{,A} */
406#define MX_25L8005 0x2014
407#define MX_25L1605 0x2015 /* MX25L1605{,A,D} */
408#define MX_25L3205 0x2016 /* MX25L3205{,A} */
409#define MX_25L6405 0x2017 /* MX25L3205{,D} */
Stephan Guilloux2f132fe2009-04-21 01:47:16 +0000410#define MX_25L12805 0x2018 /* MX25L12805 */
Carl-Daniel Hailfingere1514992007-10-02 15:49:25 +0000411#define MX_25L1635D 0x2415
Stephan Guilloux70ea9a32009-04-23 22:51:56 +0000412#define MX_25L3235D 0x5E16 /* MX25L3225D/MX25L3235D/MX25L3237D */
Carl-Daniel Hailfinger1c2ec282008-11-04 12:11:12 +0000413#define MX_29F002B 0x34
414#define MX_29F002T 0xB0
Carl-Daniel Hailfinger7de86392008-12-10 10:32:05 +0000415#define MX_29LV002CB 0x5A
416#define MX_29LV002CT 0x59
417#define MX_29LV004CB 0xB6
418#define MX_29LV004CT 0xB5
419#define MX_29LV008CB 0x37
420#define MX_29LV008CT 0x3E
421#define MX_29F040C 0xA4
422#define MX_29F200CB 0x57
423#define MX_29F200CT 0x51
424#define MX_29F400CB 0xAB
425#define MX_29F400CT 0x23
426#define MX_29LV040C 0x4F
427#define MX_29LV128DB 0x7A
428#define MX_29LV128DT 0x7E
429#define MX_29LV160DB 0x49 /* Same as MX29LV161DB/MX29LV160CB */
430#define MX_29LV160DT 0xC4 /* Same as MX29LV161DT/MX29LV160CT */
431#define MX_29LV320DB 0xA8 /* Same as MX29LV321DB */
432#define MX_29LV320DT 0xA7 /* Same as MX29LV321DT */
433#define MX_29LV400CB 0xBA
434#define MX_29LV400CT 0xB9
435#define MX_29LV800CB 0x5B
436#define MX_29LV800CT 0xDA
437#define MX_29LV640DB 0xCB /* Same as MX29LV640EB */
438#define MX_29LV640DT 0xC9 /* Same as MX29LV640ET */
439#define MX_29SL402CB 0xF1
440#define MX_29SL402CT 0x70
441#define MX_29SL800CB 0x6B /* Same as MX29SL802CB */
442#define MX_29SL800CT 0xEA /* Same as MX29SL802CT */
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000443
Uwe Hermann394131e2008-10-18 21:14:13 +0000444/*
445 * Programmable Micro Corp is listed in JEP106W in bank 2, so it should
446 * have a 0x7F continuation code prefix.
Carl-Daniel Hailfingerc2a18452007-12-31 01:18:26 +0000447 */
Carl-Daniel Hailfinger1263d2a2008-02-06 22:07:58 +0000448#define PMC_ID 0x7F9D /* PMC */
449#define PMC_ID_NOPREFIX 0x9D /* PMC, missing 0x7F prefix */
450#define PMC_25LV512 0x7B
451#define PMC_25LV010 0x7C
452#define PMC_25LV020 0x7D
453#define PMC_25LV040 0x7E
454#define PMC_25LV080B 0x13
455#define PMC_25LV016B 0x14
Uwe Hermannf983d9f2009-06-14 21:53:26 +0000456#define PMC_29F002T 0x1D
457#define PMC_29F002B 0x2D
Carl-Daniel Hailfinger1263d2a2008-02-06 22:07:58 +0000458#define PMC_39LV512 0x1B
459#define PMC_39F010 0x1C /* also Pm39LV010 */
460#define PMC_39LV020 0x3D
461#define PMC_39LV040 0x3E
462#define PMC_39F020 0x4D
463#define PMC_39F040 0x4E
Peter Lemenkov539478d2007-10-22 20:36:16 +0000464#define PMC_49FL002 0x6D
465#define PMC_49FL004 0x6E
466
Uwe Hermannaf2b52d2007-04-01 20:00:32 +0000467#define SHARP_ID 0xB0 /* Sharp */
Uwe Hermann0b7afe62007-04-01 19:44:21 +0000468#define SHARP_LHF00L04 0xCF
Ronald G. Minnich5b582f22006-02-23 17:16:44 +0000469
Uwe Hermann372eeb52007-12-04 21:49:06 +0000470/*
Peter Stuge10e091b2008-01-25 01:52:45 +0000471 * Spansion was previously a joint venture of AMD and Fujitsu.
472 * S25 chips are SPI. The first device ID byte is memory type and
473 * the second device ID byte is memory capacity.
474 */
475#define SPANSION_ID 0x01 /* Spansion */
476#define SPANSION_S25FL016A 0x0214
477
478/*
Uwe Hermann372eeb52007-12-04 21:49:06 +0000479 * SST25 chips are SPI, first byte of device ID is memory type, second
480 * byte of device ID is related to log(bitsize) at least for some chips.
481 */
Uwe Hermannaf2b52d2007-04-01 20:00:32 +0000482#define SST_ID 0xBF /* SST */
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000483#define SST_25WF512 0x2501
484#define SST_25WF010 0x2502
485#define SST_25WF020 0x2503
486#define SST_25WF040 0x2504
Carl-Daniel Hailfinger052cdc32008-12-04 00:58:10 +0000487#define SST_25VF512A_REMS 0x48 /* REMS or RES opcode */
488#define SST_25VF010_REMS 0x49 /* REMS or RES opcode */
489#define SST_25VF020_REMS 0x43 /* REMS or RES opcode */
490#define SST_25VF040_REMS 0x44 /* REMS or RES opcode */
491#define SST_25VF040B 0x258D
492#define SST_25VF040B_REMS 0x8D /* REMS or RES opcode */
493#define SST_25VF080_REMS 0x80 /* REMS or RES opcode */
494#define SST_25VF080B 0x258E
495#define SST_25VF080B_REMS 0x8E /* REMS or RES opcode */
Carl-Daniel Hailfinger5b1c6ed2007-10-22 16:15:28 +0000496#define SST_25VF016B 0x2541
497#define SST_25VF032B 0x254A
Carl-Daniel Hailfinger052cdc32008-12-04 00:58:10 +0000498#define SST_25VF032B_REMS 0x4A /* REMS or RES opcode */
499#define SST_26VF016 0x2601
500#define SST_26VF032 0x2602
Carl-Daniel Hailfinger07202922008-05-15 03:24:43 +0000501#define SST_27SF512 0xA4
502#define SST_27SF010 0xA5
503#define SST_27SF020 0xA6
504#define SST_27VF010 0xA9
505#define SST_27VF020 0xAA
Uwe Hermannaf2b52d2007-04-01 20:00:32 +0000506#define SST_28SF040 0x04
Carl-Daniel Hailfinger07202922008-05-15 03:24:43 +0000507#define SST_29EE512 0x5D
508#define SST_29EE010 0x07
509#define SST_29LE010 0x08 /* also SST29VE010 */
Mateusz Murawskie33890d2009-06-12 11:45:10 +0000510#define SST_29EE020A 0x10 /* also SST29EE020 */
Carl-Daniel Hailfinger07202922008-05-15 03:24:43 +0000511#define SST_29LE020 0x12 /* also SST29VE020 */
512#define SST_29SF020 0x24
513#define SST_29VF020 0x25
514#define SST_29SF040 0x13
515#define SST_29VF040 0x14
Uwe Hermannaf2b52d2007-04-01 20:00:32 +0000516#define SST_39SF010 0xB5
517#define SST_39SF020 0xB6
518#define SST_39SF040 0xB7
Carl-Daniel Hailfinger78c6dfe2008-05-12 14:25:31 +0000519#define SST_39VF512 0xD4
520#define SST_39VF010 0xD5
Uwe Hermannaf2b52d2007-04-01 20:00:32 +0000521#define SST_39VF020 0xD6
Carl-Daniel Hailfinger78c6dfe2008-05-12 14:25:31 +0000522#define SST_39VF040 0xD7
Mateusz Murawskie33890d2009-06-12 11:45:10 +0000523#define SST_39VF080 0xD8
Uwe Hermannaf2b52d2007-04-01 20:00:32 +0000524#define SST_49LF040B 0x50
525#define SST_49LF040 0x51
Sven Schnellec208dfb2009-01-07 12:35:09 +0000526#define SST_49LF020 0x61
Uwe Hermannaf2b52d2007-04-01 20:00:32 +0000527#define SST_49LF020A 0x52
528#define SST_49LF080A 0x5B
529#define SST_49LF002A 0x57
530#define SST_49LF003A 0x1B
531#define SST_49LF004A 0x60
532#define SST_49LF008A 0x5A
533#define SST_49LF004C 0x54
534#define SST_49LF008C 0x59
535#define SST_49LF016C 0x5C
536#define SST_49LF160C 0x4C
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000537
Carl-Daniel Hailfingerf5df46f2007-12-16 21:15:27 +0000538/*
539 * ST25P chips are SPI, first byte of device ID is memory type, second
540 * byte of device ID is related to log(bitsize) at least for some chips.
541 */
Carl-Daniel Hailfingerc2a18452007-12-31 01:18:26 +0000542#define ST_ID 0x20 /* ST / SGS/Thomson */
Carl-Daniel Hailfingerd8cc58c2007-12-17 22:22:40 +0000543#define ST_M25P05A 0x2010
544#define ST_M25P10A 0x2011
545#define ST_M25P20 0x2012
546#define ST_M25P40 0x2013
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000547#define ST_M25P40_RES 0x12
Carl-Daniel Hailfingerf5df46f2007-12-16 21:15:27 +0000548#define ST_M25P80 0x2014
Carl-Daniel Hailfingerd8cc58c2007-12-17 22:22:40 +0000549#define ST_M25P16 0x2015
550#define ST_M25P32 0x2016
551#define ST_M25P64 0x2017
552#define ST_M25P128 0x2018
Mateusz Murawskie33890d2009-06-12 11:45:10 +0000553#define ST_M25PE10 0x8011
554#define ST_M25PE20 0x8012
555#define ST_M25PE40 0x8013
556#define ST_M25PE80 0x8014
557#define ST_M25PE16 0x8015
Carl-Daniel Hailfingerf41c66f2007-07-25 17:55:45 +0000558#define ST_M50FLW040A 0x08
559#define ST_M50FLW040B 0x28
560#define ST_M50FLW080A 0x80
561#define ST_M50FLW080B 0x81
Carl-Daniel Hailfinger96e1b552008-11-02 14:25:11 +0000562#define ST_M50FW002 0x29
Carl-Daniel Hailfingere087fa22007-07-24 18:18:05 +0000563#define ST_M50FW040 0x2C
Carl-Daniel Hailfingerf41c66f2007-07-25 17:55:45 +0000564#define ST_M50FW080 0x2D
565#define ST_M50FW016 0x2E
566#define ST_M50LPW116 0x30
Uwe Hermannd7f48062007-04-28 02:22:59 +0000567#define ST_M29F002B 0x34
568#define ST_M29F002T 0xB0 /* M29F002T / M29F002NT */
Uwe Hermann0b7afe62007-04-01 19:44:21 +0000569#define ST_M29F400BT 0xD5
Uwe Hermannd7f48062007-04-28 02:22:59 +0000570#define ST_M29F040B 0xE2
Carl-Daniel Hailfingerf41c66f2007-07-25 17:55:45 +0000571#define ST_M29W010B 0x23
Carl-Daniel Hailfingere087fa22007-07-24 18:18:05 +0000572#define ST_M29W040B 0xE3
Ronald G. Minnich3c910ed2002-05-28 23:29:17 +0000573
Peter Lemenkov539478d2007-10-22 20:36:16 +0000574#define SYNCMOS_ID 0x40 /* SyncMOS and Mosel Vitelic */
Uwe Hermannaf2b52d2007-04-01 20:00:32 +0000575#define S29C51001T 0x01
576#define S29C51002T 0x02
577#define S29C51004T 0x03
578#define S29C31004T 0x63
Giampiero Giancipolia8c80822006-11-20 20:03:07 +0000579
Peter Lemenkov539478d2007-10-22 20:36:16 +0000580#define TI_ID 0x97 /* Texas Instruments */
Carl-Daniel Hailfinger09b4fb72009-05-26 21:26:23 +0000581#define TI_OLD_ID 0x01 /* TI chips from last century */
582#define TI_TMS29F002RT 0xB0
583#define TI_TMS29F002RB 0x34
Peter Lemenkov539478d2007-10-22 20:36:16 +0000584
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000585/*
586 * W25X chips are SPI, first byte of device ID is memory type, second
587 * byte of device ID is related to log(bitsize).
588 */
Peter Lemenkov539478d2007-10-22 20:36:16 +0000589#define WINBOND_ID 0xDA /* Winbond */
Uwe Hermannd1129ac2009-05-28 15:07:42 +0000590#define WINBOND_NEX_ID 0xEF /* Winbond (ex Nexcom) serial flashes */
Ronald Hoogenboom7ff530b2008-01-19 00:04:46 +0000591#define W_25X10 0x3011
592#define W_25X20 0x3012
593#define W_25X40 0x3013
594#define W_25X80 0x3014
Carl-Daniel Hailfinger052cdc32008-12-04 00:58:10 +0000595#define W_25X16 0x3015
596#define W_25X32 0x3016
597#define W_25X64 0x3017
Peter Lemenkov539478d2007-10-22 20:36:16 +0000598#define W_29C011 0xC1
599#define W_29C020C 0x45
600#define W_29C040P 0x46
601#define W_29EE011 0xC1
602#define W_39V040FA 0x34
603#define W_39V040A 0x3D
604#define W_39V040B 0x54
Mateusz Murawskie33890d2009-06-12 11:45:10 +0000605#define W_39V040C 0x50
Peter Lemenkov539478d2007-10-22 20:36:16 +0000606#define W_39V080A 0xD0
Stefan Reinauerac378972008-03-17 22:59:40 +0000607#define W_39V080FA 0xD3
608#define W_39V080FA_DM 0x93
Peter Lemenkov539478d2007-10-22 20:36:16 +0000609#define W_49F002U 0x0B
610#define W_49V002A 0xB0
611#define W_49V002FA 0x32
612
Uwe Hermann372eeb52007-12-04 21:49:06 +0000613/* udelay.c */
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000614void myusec_delay(int usecs);
Carl-Daniel Hailfinger43634392009-05-01 12:22:17 +0000615void myusec_calibrate_delay(void);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000616
Uwe Hermann515ab3d2009-05-15 17:02:34 +0000617/* pcidev.c */
618#define PCI_OK 0
619#define PCI_NT 1 /* Not tested */
Rudolf Marek68720c72009-05-17 19:39:27 +0000620
Uwe Hermann515ab3d2009-05-15 17:02:34 +0000621extern uint32_t io_base_addr;
622extern struct pci_access *pacc;
623extern struct pci_filter filter;
Uwe Hermann8403ccb2009-05-16 21:39:19 +0000624extern struct pci_dev *pcidev_dev;
Uwe Hermann515ab3d2009-05-15 17:02:34 +0000625struct pcidev_status {
626 uint16_t vendor_id;
627 uint16_t device_id;
628 int status;
629 const char *vendor_name;
630 const char *device_name;
631};
632uint32_t pcidev_validate(struct pci_dev *dev, struct pcidev_status *devs);
633uint32_t pcidev_init(uint16_t vendor_id, struct pcidev_status *devs);
634void print_supported_pcidevs(struct pcidev_status *devs);
635
Uwe Hermann372eeb52007-12-04 21:49:06 +0000636/* board_enable.c */
Peter Stuge9d9399c2009-01-26 02:34:51 +0000637void w836xx_ext_enter(uint16_t port);
638void w836xx_ext_leave(uint16_t port);
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000639uint8_t sio_read(uint16_t port, uint8_t reg);
640void sio_write(uint16_t port, uint8_t reg, uint8_t data);
641void sio_mask(uint16_t port, uint8_t reg, uint8_t data, uint8_t mask);
Uwe Hermann372eeb52007-12-04 21:49:06 +0000642int board_flash_enable(const char *vendor, const char *part);
Uwe Hermanne5ac1642008-03-12 11:54:51 +0000643void print_supported_boards(void);
Adam Kaufman064b1f22007-02-06 19:47:50 +0000644
Uwe Hermann372eeb52007-12-04 21:49:06 +0000645/* chipset_enable.c */
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000646extern enum chipbustype buses_supported;
Uwe Hermann372eeb52007-12-04 21:49:06 +0000647int chipset_flash_enable(void);
Uwe Hermanne5ac1642008-03-12 11:54:51 +0000648void print_supported_chipsets(void);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000649
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000650extern unsigned long flashbase;
651
Stefan Reinauer0593f212009-01-26 01:10:48 +0000652/* physmap.c */
653void *physmap(const char *descr, unsigned long phys_addr, size_t len);
654void physunmap(void *virt_addr, size_t len);
655
Carl-Daniel Hailfinger702218d2009-05-08 17:43:22 +0000656/* internal.c */
Uwe Hermann2cac6862009-05-16 22:05:42 +0000657struct pci_dev *pci_dev_find_filter(struct pci_filter filter);
658struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device);
659struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device,
660 uint16_t card_vendor, uint16_t card_device);
Carl-Daniel Hailfinger3b7e75a2009-05-14 21:41:10 +0000661void get_io_perms(void);
Carl-Daniel Hailfinger702218d2009-05-08 17:43:22 +0000662int internal_init(void);
663int internal_shutdown(void);
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000664void internal_chip_writeb(uint8_t val, chipaddr addr);
665void internal_chip_writew(uint16_t val, chipaddr addr);
666void internal_chip_writel(uint32_t val, chipaddr addr);
667uint8_t internal_chip_readb(const chipaddr addr);
668uint16_t internal_chip_readw(const chipaddr addr);
669uint32_t internal_chip_readl(const chipaddr addr);
Carl-Daniel Hailfinger0bd2a2b2009-06-05 18:32:07 +0000670void internal_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000671void mmio_writeb(uint8_t val, void *addr);
672void mmio_writew(uint16_t val, void *addr);
673void mmio_writel(uint32_t val, void *addr);
674uint8_t mmio_readb(void *addr);
675uint16_t mmio_readw(void *addr);
676uint32_t mmio_readl(void *addr);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000677void internal_delay(int usecs);
Uwe Hermannc6915932009-05-17 23:12:17 +0000678void *fallback_map(const char *descr, unsigned long phys_addr, size_t len);
679void fallback_unmap(void *virt_addr, size_t len);
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000680void fallback_chip_writew(uint16_t val, chipaddr addr);
681void fallback_chip_writel(uint32_t val, chipaddr addr);
Carl-Daniel Hailfinger0bd2a2b2009-06-05 18:32:07 +0000682void fallback_chip_writen(uint8_t *buf, chipaddr addr, size_t len);
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000683uint16_t fallback_chip_readw(const chipaddr addr);
684uint32_t fallback_chip_readl(const chipaddr addr);
Carl-Daniel Hailfinger0bd2a2b2009-06-05 18:32:07 +0000685void fallback_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
Uwe Hermanna0869322009-05-14 20:41:57 +0000686#if defined(__FreeBSD__) || defined(__DragonFly__)
687extern int io_fd;
688#endif
Carl-Daniel Hailfinger702218d2009-05-08 17:43:22 +0000689
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000690/* dummyflasher.c */
Carl-Daniel Hailfinger3504b532009-06-01 00:02:11 +0000691extern char *dummytype;
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000692int dummy_init(void);
693int dummy_shutdown(void);
Carl-Daniel Hailfinger1455b2b2009-05-11 14:13:25 +0000694void *dummy_map(const char *descr, unsigned long phys_addr, size_t len);
695void dummy_unmap(void *virt_addr, size_t len);
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000696void dummy_chip_writeb(uint8_t val, chipaddr addr);
697void dummy_chip_writew(uint16_t val, chipaddr addr);
698void dummy_chip_writel(uint32_t val, chipaddr addr);
Carl-Daniel Hailfinger0bd2a2b2009-06-05 18:32:07 +0000699void dummy_chip_writen(uint8_t *buf, chipaddr addr, size_t len);
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000700uint8_t dummy_chip_readb(const chipaddr addr);
701uint16_t dummy_chip_readw(const chipaddr addr);
702uint32_t dummy_chip_readl(const chipaddr addr);
Carl-Daniel Hailfinger0bd2a2b2009-06-05 18:32:07 +0000703void dummy_chip_readn(uint8_t *buf, const chipaddr addr, size_t len);
Carl-Daniel Hailfingerbfe2e0c2009-05-14 12:59:36 +0000704int dummy_spi_command(unsigned int writecnt, unsigned int readcnt,
705 const unsigned char *writearr, unsigned char *readarr);
Carl-Daniel Hailfingerc3129202009-05-09 00:54:55 +0000706
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000707/* nic3com.c */
708int nic3com_init(void);
709int nic3com_shutdown(void);
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000710void nic3com_chip_writeb(uint8_t val, chipaddr addr);
711uint8_t nic3com_chip_readb(const chipaddr addr);
Uwe Hermann515ab3d2009-05-15 17:02:34 +0000712extern struct pcidev_status nics_3com[];
Uwe Hermannb4dcb712009-05-13 11:36:06 +0000713
Rudolf Marek68720c72009-05-17 19:39:27 +0000714/* satasii.c */
715int satasii_init(void);
716int satasii_shutdown(void);
Rudolf Marek68720c72009-05-17 19:39:27 +0000717void satasii_chip_writeb(uint8_t val, chipaddr addr);
718uint8_t satasii_chip_readb(const chipaddr addr);
719extern struct pcidev_status satas_sii[];
720
Uwe Hermann0846f892007-08-23 13:34:59 +0000721/* flashrom.c */
Uwe Hermannad216bf2009-04-24 16:17:41 +0000722extern int verbose;
723#define printf_debug(x...) { if (verbose) printf(x); }
Peter Stuge776d2022009-01-26 00:39:57 +0000724void map_flash_registers(struct flashchip *flash);
Carl-Daniel Hailfinger03b4e712009-05-08 12:49:03 +0000725int read_memmapped(struct flashchip *flash, uint8_t *buf);
Carl-Daniel Hailfinger38a059d2009-06-13 12:04:03 +0000726int min(int a, int b);
Uwe Hermann515ab3d2009-05-15 17:02:34 +0000727extern char *pcidev_bdf;
Uwe Hermann0846f892007-08-23 13:34:59 +0000728
729/* layout.c */
Peter Stuge7ffbc6f2008-06-18 02:08:40 +0000730int show_id(uint8_t *bios, int size, int force);
Uwe Hermann0846f892007-08-23 13:34:59 +0000731int read_romlayout(char *name);
732int find_romentry(char *name);
733int handle_romentries(uint8_t *buffer, uint8_t *content);
734
Uwe Hermannad216bf2009-04-24 16:17:41 +0000735/* cbtable.c */
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +0000736int coreboot_init(void);
Uwe Hermann0846f892007-08-23 13:34:59 +0000737extern char *lb_part, *lb_vendor;
738
Carl-Daniel Hailfinger00f911e2007-10-15 21:44:47 +0000739/* spi.c */
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000740enum spi_controller {
741 SPI_CONTROLLER_NONE,
742 SPI_CONTROLLER_ICH7,
743 SPI_CONTROLLER_ICH9,
744 SPI_CONTROLLER_IT87XX,
745 SPI_CONTROLLER_SB600,
746 SPI_CONTROLLER_VIA,
747 SPI_CONTROLLER_WBSIO,
748 SPI_CONTROLLER_DUMMY,
749};
750extern enum spi_controller spi_controller;
751extern void *spibar;
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000752int probe_spi_rdid(struct flashchip *flash);
Rudolf Marek48a85e42008-06-30 21:45:17 +0000753int probe_spi_rdid4(struct flashchip *flash);
Carl-Daniel Hailfinger14e50ac2008-11-28 01:25:00 +0000754int probe_spi_rems(struct flashchip *flash);
Carl-Daniel Hailfinger42c54972008-05-15 03:19:49 +0000755int probe_spi_res(struct flashchip *flash);
Uwe Hermann394131e2008-10-18 21:14:13 +0000756int spi_command(unsigned int writecnt, unsigned int readcnt,
757 const unsigned char *writearr, unsigned char *readarr);
Carl-Daniel Hailfinger43634392009-05-01 12:22:17 +0000758int spi_write_enable(void);
759int spi_write_disable(void);
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000760int spi_chip_erase_60(struct flashchip *flash);
Peter Stugefa8c5502008-05-10 23:07:52 +0000761int spi_chip_erase_c7(struct flashchip *flash);
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000762int spi_chip_erase_60_c7(struct flashchip *flash);
Stefan Reinauer424ed222008-10-29 22:13:20 +0000763int spi_chip_erase_d8(struct flashchip *flash);
Carl-Daniel Hailfinger6afb6132008-11-03 00:02:11 +0000764int spi_block_erase_52(const struct flashchip *flash, unsigned long addr);
765int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr);
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000766int spi_chip_write_1(struct flashchip *flash, uint8_t *buf);
Carl-Daniel Hailfinger8d497012009-05-09 02:34:18 +0000767int spi_chip_write_256(struct flashchip *flash, uint8_t *buf);
Peter Stugefa8c5502008-05-10 23:07:52 +0000768int spi_chip_read(struct flashchip *flash, uint8_t *buf);
Carl-Daniel Hailfinger43634392009-05-01 12:22:17 +0000769uint8_t spi_read_status_register(void);
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000770int spi_disable_blockprotect(void);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000771void spi_byte_program(int address, uint8_t byte);
Paul Foxeb3acef2009-06-12 08:10:33 +0000772int spi_nbyte_program(int address, uint8_t *bytes, int len);
Carl-Daniel Hailfinger598ec582008-11-18 00:41:02 +0000773int spi_nbyte_read(int address, uint8_t *bytes, int len);
Carl-Daniel Hailfinger38a059d2009-06-13 12:04:03 +0000774int spi_read_chunked(struct flashchip *flash, uint8_t *buf, int chunksize);
Peter Stugefd9217d2009-01-26 03:37:40 +0000775int spi_aai_write(struct flashchip *flash, uint8_t *buf);
Carl-Daniel Hailfinger3e9dbea2009-05-13 11:40:08 +0000776uint32_t spi_get_valid_read_addr(void);
Carl-Daniel Hailfingere1514992007-10-02 15:49:25 +0000777
Uwe Hermann0846f892007-08-23 13:34:59 +0000778/* 82802ab.c */
Uwe Hermanna0cc53d2007-09-09 20:24:29 +0000779int probe_82802ab(struct flashchip *flash);
780int erase_82802ab(struct flashchip *flash);
781int write_82802ab(struct flashchip *flash, uint8_t *buf);
Uwe Hermann0846f892007-08-23 13:34:59 +0000782
783/* am29f040b.c */
Uwe Hermanna0cc53d2007-09-09 20:24:29 +0000784int probe_29f040b(struct flashchip *flash);
785int erase_29f040b(struct flashchip *flash);
786int write_29f040b(struct flashchip *flash, uint8_t *buf);
Uwe Hermann0846f892007-08-23 13:34:59 +0000787
Uwe Hermannf983d9f2009-06-14 21:53:26 +0000788/* pm29f002.c */
789int write_pm29f002(struct flashchip *flash, uint8_t *buf);
790
Mats Erik Andersson44e1a192008-09-26 13:19:02 +0000791/* en29f002a.c */
792int probe_en29f002a(struct flashchip *flash);
793int erase_en29f002a(struct flashchip *flash);
794int write_en29f002a(struct flashchip *flash, uint8_t *buf);
795
Dominik Geyerb46acba2008-05-16 12:55:55 +0000796/* ichspi.c */
Carl-Daniel Hailfinger43634392009-05-01 12:22:17 +0000797int ich_init_opcodes(void);
Uwe Hermann394131e2008-10-18 21:14:13 +0000798int ich_spi_command(unsigned int writecnt, unsigned int readcnt,
799 const unsigned char *writearr, unsigned char *readarr);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000800int ich_spi_read(struct flashchip *flash, uint8_t * buf);
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000801int ich_spi_write_256(struct flashchip *flash, uint8_t * buf);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000802
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000803/* it87spi.c */
804extern uint16_t it8716f_flashport;
Carl-Daniel Hailfinger24c1a162009-05-25 23:26:50 +0000805void enter_conf_mode_ite(uint16_t port);
806void exit_conf_mode_ite(uint16_t port);
Carl-Daniel Hailfingerb8afecd2009-05-31 18:00:57 +0000807int it87spi_init(void);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000808int it87xx_probe_spi_flash(const char *name);
Uwe Hermann394131e2008-10-18 21:14:13 +0000809int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt,
810 const unsigned char *writearr, unsigned char *readarr);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000811int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf);
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000812int it8716f_spi_chip_write_1(struct flashchip *flash, uint8_t *buf);
813int it8716f_spi_chip_write_256(struct flashchip *flash, uint8_t *buf);
Carl-Daniel Hailfingerbfe5b4a2008-05-13 23:03:12 +0000814
Jason Wanga3f04be2008-11-28 21:36:51 +0000815/* sb600spi.c */
816int sb600_spi_command(unsigned int writecnt, unsigned int readcnt,
817 const unsigned char *writearr, unsigned char *readarr);
818int sb600_spi_read(struct flashchip *flash, uint8_t *buf);
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000819int sb600_spi_write_1(struct flashchip *flash, uint8_t *buf);
Jason Wanga3f04be2008-11-28 21:36:51 +0000820uint8_t sb600_read_status_register(void);
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000821extern uint8_t *sb600_spibar;
Jason Wanga3f04be2008-11-28 21:36:51 +0000822
Uwe Hermann0846f892007-08-23 13:34:59 +0000823/* jedec.c */
Carl-Daniel Hailfingera758f512008-05-14 12:03:06 +0000824uint8_t oddparity(uint8_t val);
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000825void toggle_ready_jedec(chipaddr dst);
826void data_polling_jedec(chipaddr dst, uint8_t data);
827void unprotect_jedec(chipaddr bios);
828void protect_jedec(chipaddr bios);
829int write_byte_program_jedec(chipaddr bios, uint8_t *src,
830 chipaddr dst);
Uwe Hermanna0cc53d2007-09-09 20:24:29 +0000831int probe_jedec(struct flashchip *flash);
832int erase_chip_jedec(struct flashchip *flash);
833int write_jedec(struct flashchip *flash, uint8_t *buf);
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000834int erase_sector_jedec(chipaddr bios, unsigned int page);
835int erase_block_jedec(chipaddr bios, unsigned int page);
836int write_sector_jedec(chipaddr bios, uint8_t *src,
837 chipaddr dst, unsigned int page_size);
Uwe Hermann0846f892007-08-23 13:34:59 +0000838
Peter Stugeaf8ffac2009-01-26 06:42:02 +0000839/* m29f002.c */
840int erase_m29f002(struct flashchip *flash);
841int write_m29f002t(struct flashchip *flash, uint8_t *buf);
842int write_m29f002b(struct flashchip *flash, uint8_t *buf);
843
Uwe Hermann0846f892007-08-23 13:34:59 +0000844/* m29f400bt.c */
Uwe Hermanna0cc53d2007-09-09 20:24:29 +0000845int probe_m29f400bt(struct flashchip *flash);
846int erase_m29f400bt(struct flashchip *flash);
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000847int block_erase_m29f400bt(chipaddr bios,
848 chipaddr dst);
Uwe Hermanna0cc53d2007-09-09 20:24:29 +0000849int write_m29f400bt(struct flashchip *flash, uint8_t *buf);
Stefan Reinauere3f3e2e2008-01-18 15:33:10 +0000850int write_coreboot_m29f400bt(struct flashchip *flash, uint8_t *buf);
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000851void toggle_ready_m29f400bt(chipaddr dst);
852void data_polling_m29f400bt(chipaddr dst, uint8_t data);
853void protect_m29f400bt(chipaddr bios);
854void write_page_m29f400bt(chipaddr bios, uint8_t *src,
855 chipaddr dst, int page_size);
Uwe Hermann0846f892007-08-23 13:34:59 +0000856
857/* mx29f002.c */
Uwe Hermanna0cc53d2007-09-09 20:24:29 +0000858int probe_29f002(struct flashchip *flash);
859int erase_29f002(struct flashchip *flash);
860int write_29f002(struct flashchip *flash, uint8_t *buf);
Uwe Hermann0846f892007-08-23 13:34:59 +0000861
Nikolay Petukhov4784c472008-05-17 01:08:58 +0000862/* pm49fl00x.c */
863int probe_49fl00x(struct flashchip *flash);
864int erase_49fl00x(struct flashchip *flash);
865int write_49fl00x(struct flashchip *flash, uint8_t *buf);
Uwe Hermann0846f892007-08-23 13:34:59 +0000866
867/* sharplhf00l04.c */
Uwe Hermanna0cc53d2007-09-09 20:24:29 +0000868int probe_lhf00l04(struct flashchip *flash);
869int erase_lhf00l04(struct flashchip *flash);
870int write_lhf00l04(struct flashchip *flash, uint8_t *buf);
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000871void toggle_ready_lhf00l04(chipaddr dst);
872void data_polling_lhf00l04(chipaddr dst, uint8_t data);
873void protect_lhf00l04(chipaddr bios);
Uwe Hermann0846f892007-08-23 13:34:59 +0000874
875/* sst28sf040.c */
Uwe Hermanna0cc53d2007-09-09 20:24:29 +0000876int probe_28sf040(struct flashchip *flash);
877int erase_28sf040(struct flashchip *flash);
878int write_28sf040(struct flashchip *flash, uint8_t *buf);
Uwe Hermann0846f892007-08-23 13:34:59 +0000879
880/* sst39sf020.c */
Uwe Hermanna0cc53d2007-09-09 20:24:29 +0000881int probe_39sf020(struct flashchip *flash);
882int write_39sf020(struct flashchip *flash, uint8_t *buf);
Uwe Hermann0846f892007-08-23 13:34:59 +0000883
884/* sst49lf040.c */
Uwe Hermanna0cc53d2007-09-09 20:24:29 +0000885int erase_49lf040(struct flashchip *flash);
886int write_49lf040(struct flashchip *flash, uint8_t *buf);
Uwe Hermann0846f892007-08-23 13:34:59 +0000887
888/* sst49lfxxxc.c */
Uwe Hermanna0cc53d2007-09-09 20:24:29 +0000889int probe_49lfxxxc(struct flashchip *flash);
890int erase_49lfxxxc(struct flashchip *flash);
891int write_49lfxxxc(struct flashchip *flash, uint8_t *buf);
Uwe Hermann0846f892007-08-23 13:34:59 +0000892
893/* sst_fwhub.c */
Uwe Hermanna0cc53d2007-09-09 20:24:29 +0000894int probe_sst_fwhub(struct flashchip *flash);
895int erase_sst_fwhub(struct flashchip *flash);
896int write_sst_fwhub(struct flashchip *flash, uint8_t *buf);
Uwe Hermann0846f892007-08-23 13:34:59 +0000897
Peter Stugecce26822008-07-21 17:48:40 +0000898/* w39v040c.c */
899int probe_w39v040c(struct flashchip *flash);
900int erase_w39v040c(struct flashchip *flash);
901int write_w39v040c(struct flashchip *flash, uint8_t *buf);
902
Stefan Reinauerac378972008-03-17 22:59:40 +0000903/* w39V080fa.c */
904int probe_winbond_fwhub(struct flashchip *flash);
905int erase_winbond_fwhub(struct flashchip *flash);
906int write_winbond_fwhub(struct flashchip *flash, uint8_t *buf);
907
Markus Boasd2ac6fc2007-08-30 10:17:50 +0000908/* w29ee011.c */
Uwe Hermanna0cc53d2007-09-09 20:24:29 +0000909int probe_w29ee011(struct flashchip *flash);
Markus Boasd2ac6fc2007-08-30 10:17:50 +0000910
Uwe Hermann0846f892007-08-23 13:34:59 +0000911/* w49f002u.c */
Uwe Hermanna0cc53d2007-09-09 20:24:29 +0000912int write_49f002(struct flashchip *flash, uint8_t *buf);
Stefan Reinauerff4f1972007-05-24 08:48:10 +0000913
Peter Stugebf196e92009-01-26 03:08:45 +0000914/* wbsio_spi.c */
915int wbsio_check_for_spi(const char *name);
Uwe Hermannd1129ac2009-05-28 15:07:42 +0000916int wbsio_spi_command(unsigned int writecnt, unsigned int readcnt,
917 const unsigned char *writearr, unsigned char *readarr);
Peter Stugebf196e92009-01-26 03:08:45 +0000918int wbsio_spi_read(struct flashchip *flash, uint8_t *buf);
Carl-Daniel Hailfinger96930c32009-05-09 02:30:21 +0000919int wbsio_spi_write_1(struct flashchip *flash, uint8_t *buf);
Peter Stugebf196e92009-01-26 03:08:45 +0000920
Claus Gindharta7b35512008-04-28 17:51:09 +0000921/* stm50flw0x0x.c */
922int probe_stm50flw0x0x(struct flashchip *flash);
923int erase_stm50flw0x0x(struct flashchip *flash);
924int write_stm50flw0x0x(struct flashchip *flash, uint8_t *buf);
Dominik Geyerb46acba2008-05-16 12:55:55 +0000925
Ollie Lho761bf1b2004-03-20 16:46:10 +0000926#endif /* !__FLASH_H__ */