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Ollie Lho184a4042005-11-26 21:55:36 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ollie Lho184a4042005-11-26 21:55:36 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Stefan Reinauer8fa64812009-08-12 09:27:45 +00005 * Copyright (C) 2005-2009 coresystems GmbH
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Ollie Lho184a4042005-11-26 21:55:36 +00007 *
Uwe Hermannd1107642007-08-29 17:52:32 +00008 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
Ollie Lho184a4042005-11-26 21:55:36 +000011 *
Uwe Hermannd1107642007-08-29 17:52:32 +000012 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22/*
23 * Contains the chipset specific flash enables.
Ollie Lho184a4042005-11-26 21:55:36 +000024 */
25
Lane Brooksd54958a2007-11-13 16:45:22 +000026#define _LARGEFILE64_SOURCE
27
Ollie Lhocbbf1252004-03-17 22:22:08 +000028#include <stdlib.h>
Uwe Hermanne8ba5382009-05-22 11:37:27 +000029#include <string.h>
Lane Brooksd54958a2007-11-13 16:45:22 +000030#include <sys/types.h>
31#include <sys/stat.h>
32#include <fcntl.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000033#include "flash.h"
Stefan Reinauer86de2832006-03-31 11:26:55 +000034
Stefan Reinauer9a6d1762008-12-03 21:24:40 +000035unsigned long flashbase = 0;
36
Stefan Reinauer2cb94e12008-06-30 23:45:22 +000037/**
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +000038 * flashrom defaults to Parallel/LPC/FWH flash devices. If a known host
39 * controller is found, the init routine sets the buses_supported bitfield to
40 * contain the supported buses for that controller.
Stefan Reinauer2cb94e12008-06-30 23:45:22 +000041 */
42
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +000043enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +000044
Carl-Daniel Hailfinger115d3902009-10-31 01:53:09 +000045/**
46 * Programmers supporting multiple buses can have differing size limits on
47 * each bus. Store the limits for each bus in a common struct.
48 */
49struct decode_sizes max_rom_decode = {
50 .parallel = 0xffffffff,
51 .lpc = 0xffffffff,
52 .fwh = 0xffffffff,
53 .spi = 0xffffffff
54};
55
FENG yu ningc05a2952008-12-08 18:16:58 +000056extern int ichspi_lock;
57
Uwe Hermann372eeb52007-12-04 21:49:06 +000058static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
Luc Verhaegen6b141752007-05-20 16:16:13 +000059{
60 uint8_t tmp;
61
Uwe Hermann372eeb52007-12-04 21:49:06 +000062 /*
63 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
64 * 0xFFFE0000-0xFFFFFFFF ROM select enable.
65 */
Luc Verhaegen6b141752007-05-20 16:16:13 +000066 tmp = pci_read_byte(dev, 0x47);
67 tmp |= 0x46;
68 pci_write_byte(dev, 0x47, tmp);
69
70 return 0;
71}
72
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +000073static int enable_flash_sis85c496(struct pci_dev *dev, const char *name)
74{
75 uint8_t tmp;
76
77 tmp = pci_read_byte(dev, 0xd0);
78 tmp |= 0xf8;
79 pci_write_byte(dev, 0xd0, tmp);
80
81 return 0;
82}
83
84static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name)
85{
86 uint8_t new, newer;
87
88 /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
89 /* This is 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
90 new = pci_read_byte(dev, 0x40);
91 new &= (~0x04); /* No idea why we clear bit 2. */
92 new |= 0xb; /* 0x3 for some chipsets, bit 7 seems to be don't care. */
93 pci_write_byte(dev, 0x40, new);
94 newer = pci_read_byte(dev, 0x40);
95 if (newer != new) {
96 printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
97 printf_debug("Stuck at 0x%x\n", newer);
98 return -1;
99 }
100 return 0;
101}
102
103static struct pci_dev *find_southbridge(uint16_t vendor, const char *name)
104{
105 struct pci_dev *sbdev;
106
107 sbdev = pci_dev_find_vendorclass(vendor, 0x0601);
108 if (!sbdev)
109 sbdev = pci_dev_find_vendorclass(vendor, 0x0680);
110 if (!sbdev)
111 sbdev = pci_dev_find_vendorclass(vendor, 0x0000);
112 if (!sbdev)
113 fprintf(stderr, "No southbridge found for %s!\n", name);
114 if (sbdev)
115 printf_debug("Found southbridge %04x:%04x at %02x:%02x:%01x\n",
116 sbdev->vendor_id, sbdev->device_id,
117 sbdev->bus, sbdev->dev, sbdev->func);
118 return sbdev;
119}
120
121static int enable_flash_sis501(struct pci_dev *dev, const char *name)
122{
123 uint8_t tmp;
124 int ret = 0;
125 struct pci_dev *sbdev;
126
127 sbdev = find_southbridge(dev->vendor_id, name);
128 if (!sbdev)
129 return -1;
130
131 ret = enable_flash_sis_mapping(sbdev, name);
132
133 tmp = sio_read(0x22, 0x80);
134 tmp &= (~0x20);
135 tmp |= 0x4;
136 sio_write(0x22, 0x80, tmp);
137
138 tmp = sio_read(0x22, 0x70);
139 tmp &= (~0x20);
140 tmp |= 0x4;
141 sio_write(0x22, 0x70, tmp);
142
143 return ret;
144}
145
146static int enable_flash_sis5511(struct pci_dev *dev, const char *name)
147{
148 uint8_t tmp;
149 int ret = 0;
150 struct pci_dev *sbdev;
151
152 sbdev = find_southbridge(dev->vendor_id, name);
153 if (!sbdev)
154 return -1;
155
156 ret = enable_flash_sis_mapping(sbdev, name);
157
158 tmp = sio_read(0x22, 0x50);
159 tmp &= (~0x20);
160 tmp |= 0x4;
161 sio_write(0x22, 0x50, tmp);
162
163 return ret;
164}
165
166static int enable_flash_sis5596(struct pci_dev *dev, const char *name)
167{
168 int ret;
169
170 ret = enable_flash_sis5511(dev, name);
171
172 /* FIXME: Needs same superio handling as enable_flash_sis630 */
173 return ret;
174}
175
176static int enable_flash_sis530(struct pci_dev *dev, const char *name)
177{
178 uint8_t new, newer;
179 int ret = 0;
180 struct pci_dev *sbdev;
181
182 sbdev = find_southbridge(dev->vendor_id, name);
183 if (!sbdev)
184 return -1;
185
186 ret = enable_flash_sis_mapping(sbdev, name);
187
188 new = pci_read_byte(sbdev, 0x45);
189 new &= (~0x20);
190 new |= 0x4;
191 pci_write_byte(sbdev, 0x45, new);
192 newer = pci_read_byte(dev, 0x45);
193 if (newer != new) {
194 printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
195 printf_debug("Stuck at 0x%x\n", newer);
196 ret = -1;
197 }
198
199 return ret;
200}
201
202static int enable_flash_sis540(struct pci_dev *dev, const char *name)
203{
204 uint8_t new, newer;
205 int ret = 0;
206 struct pci_dev *sbdev;
207
208 sbdev = find_southbridge(dev->vendor_id, name);
209 if (!sbdev)
210 return -1;
211
212 ret = enable_flash_sis_mapping(sbdev, name);
213
214 new = pci_read_byte(sbdev, 0x45);
215 new &= (~0x80);
216 new |= 0x40;
217 pci_write_byte(sbdev, 0x45, new);
218 newer = pci_read_byte(dev, 0x45);
219 if (newer != new) {
220 printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
221 printf_debug("Stuck at 0x%x\n", newer);
222 ret = -1;
223 }
224
225 return ret;
226}
227
Uwe Hermann372eeb52007-12-04 21:49:06 +0000228static int enable_flash_sis630(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000229{
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000230 uint8_t tmp;
231 uint16_t siobase;
232 int ret;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000233
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000234 ret = enable_flash_sis540(dev, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000235
Uwe Hermann372eeb52007-12-04 21:49:06 +0000236 /* The same thing on SiS 950 Super I/O side... */
237
238 /* First probe for Super I/O on config port 0x2e. */
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000239 siobase = 0x2e;
240 enter_conf_mode_ite(siobase);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000241
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000242 if (INB(siobase + 1) != 0x87) {
Uwe Hermann372eeb52007-12-04 21:49:06 +0000243 /* If that failed, try config port 0x4e. */
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000244 siobase = 0x4e;
245 enter_conf_mode_ite(siobase);
246 if (INB(siobase + 1) != 0x87) {
247 printf("Can not find SuperI/O.\n");
Ollie Lhocbbf1252004-03-17 22:22:08 +0000248 return -1;
249 }
Ollie Lhocbbf1252004-03-17 22:22:08 +0000250 }
251
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000252 /* Enable flash mapping. Works for most old ITE style SuperI/O. */
253 tmp = sio_read(siobase, 0x24);
254 tmp |= 0xfc;
255 sio_write(siobase, 0x24, tmp);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000256
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000257 exit_conf_mode_ite(siobase);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000258
Carl-Daniel Hailfinger9f46cfc2009-11-15 17:13:29 +0000259 return ret;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000260}
261
Uwe Hermann987942d2006-11-07 11:16:21 +0000262/* Datasheet:
263 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
264 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
265 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
266 * - Order Number: 290562-001
267 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000268static int enable_flash_piix4(struct pci_dev *dev, const char *name)
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000269{
270 uint16_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000271 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000272
273 old = pci_read_word(dev, xbcs);
274
275 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
Uwe Hermanna7e05482007-05-09 10:17:44 +0000276 * FFF00000-FFF7FFFF are forwarded to ISA).
Uwe Hermannc556d322008-10-28 11:50:05 +0000277 * Note: This bit is reserved on PIIX/PIIX3/MPIIX.
Uwe Hermanna7e05482007-05-09 10:17:44 +0000278 * Set bit 7: Extended BIOS Enable (PCI master accesses to
279 * FFF80000-FFFDFFFF are forwarded to ISA).
280 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
281 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
282 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
283 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
284 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
285 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
286 */
Uwe Hermannc556d322008-10-28 11:50:05 +0000287 if (dev->device_id == 0x122e || dev->device_id == 0x7000
288 || dev->device_id == 0x1234)
289 new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
Uwe Hermann87203452008-10-26 18:40:42 +0000290 else
291 new = old | 0x02c4;
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000292
293 if (new == old)
294 return 0;
295
296 pci_write_word(dev, xbcs, new);
297
298 if (pci_read_word(dev, xbcs) != new) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000299 printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000300 return -1;
301 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000302
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000303 return 0;
304}
305
Uwe Hermann372eeb52007-12-04 21:49:06 +0000306/*
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000307 * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet"
308 * http://download.intel.com/design/chipsets/datashts/30701303.pdf
Uwe Hermann372eeb52007-12-04 21:49:06 +0000309 */
310static int enable_flash_ich(struct pci_dev *dev, const char *name,
311 int bios_cntl)
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000312{
Ollie Lho184a4042005-11-26 21:55:36 +0000313 uint8_t old, new;
Stefan Reinauereb366472006-09-06 15:48:48 +0000314
Uwe Hermann372eeb52007-12-04 21:49:06 +0000315 /*
316 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
Uwe Hermanna7e05482007-05-09 10:17:44 +0000317 * just treating it as 8 bit wide seems to work fine in practice.
Stefan Reinauereb366472006-09-06 15:48:48 +0000318 */
Stefan Reinauer86de2832006-03-31 11:26:55 +0000319 old = pci_read_byte(dev, bios_cntl);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000320
Uwe Hermann793bdcd2008-05-22 22:47:04 +0000321 printf_debug("\nBIOS Lock Enable: %sabled, ",
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000322 (old & (1 << 1)) ? "en" : "dis");
323 printf_debug("BIOS Write Enable: %sabled, ",
324 (old & (1 << 0)) ? "en" : "dis");
325 printf_debug("BIOS_CNTL is 0x%x\n", old);
326
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000327 new = old | 1;
328
329 if (new == old)
330 return 0;
331
Stefan Reinauer86de2832006-03-31 11:26:55 +0000332 pci_write_byte(dev, bios_cntl, new);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000333
Stefan Reinauer86de2832006-03-31 11:26:55 +0000334 if (pci_read_byte(dev, bios_cntl) != new) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000335 printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000336 return -1;
337 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000338
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000339 return 0;
340}
341
Uwe Hermann372eeb52007-12-04 21:49:06 +0000342static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000343{
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000344 /*
345 * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and
346 * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and
347 * FB_DEC_EN2.
348 */
Stefan Reinauereb366472006-09-06 15:48:48 +0000349 return enable_flash_ich(dev, name, 0x4e);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000350}
351
Uwe Hermann372eeb52007-12-04 21:49:06 +0000352static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000353{
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000354 uint32_t fwh_conf;
355 int i;
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000356 char *idsel = NULL;
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000357
358 /* Ignore all legacy ranges below 1 MB. */
359 /* FWH_SEL1 */
360 fwh_conf = pci_read_long(dev, 0xd0);
361 for (i = 7; i >= 0; i--)
362 printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
363 (0x1ff8 + i) * 0x80000,
364 (0x1ff0 + i) * 0x80000,
365 (fwh_conf >> (i * 4)) & 0xf);
366 /* FWH_SEL2 */
367 fwh_conf = pci_read_word(dev, 0xd4);
368 for (i = 3; i >= 0; i--)
369 printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
370 (0xff4 + i) * 0x100000,
371 (0xff0 + i) * 0x100000,
372 (fwh_conf >> (i * 4)) & 0xf);
373 /* FWH_DEC_EN1 */
374 fwh_conf = pci_read_word(dev, 0xd8);
375 for (i = 7; i >= 0; i--)
376 printf_debug("\n0x%08x/0x%08x FWH decode %sabled",
377 (0x1ff8 + i) * 0x80000,
378 (0x1ff0 + i) * 0x80000,
379 (fwh_conf >> (i + 0x8)) & 0x1 ? "en" : "dis");
380 for (i = 3; i >= 0; i--)
381 printf_debug("\n0x%08x/0x%08x FWH decode %sabled",
382 (0xff4 + i) * 0x100000,
383 (0xff0 + i) * 0x100000,
384 (fwh_conf >> i) & 0x1 ? "en" : "dis");
385
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000386 if (programmer_param)
387 idsel = strstr(programmer_param, "fwh_idsel=");
388
389 if (idsel) {
390 idsel += strlen("fwh_idsel=");
391 fwh_conf = (uint32_t)strtoul(idsel, NULL, 0);
392
393 /* FIXME: Need to undo this on shutdown. */
394 printf("\nSetting IDSEL=0x%x for top 16 MB", fwh_conf);
395 pci_write_long(dev, 0xd0, fwh_conf);
396 pci_write_word(dev, 0xd4, fwh_conf);
397 }
398
Stefan Reinauereb366472006-09-06 15:48:48 +0000399 return enable_flash_ich(dev, name, 0xdc);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000400}
401
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000402#define ICH_STRAP_RSVD 0x00
403#define ICH_STRAP_SPI 0x01
404#define ICH_STRAP_PCI 0x02
405#define ICH_STRAP_LPC 0x03
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000406
Uwe Hermann394131e2008-10-18 21:14:13 +0000407static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
408{
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000409 uint32_t mmio_base;
410
411 mmio_base = (pci_read_long(dev, 0xbc)) << 8;
412 printf_debug("MMIO base at = 0x%x\n", mmio_base);
Stefan Reinauer0593f212009-01-26 01:10:48 +0000413 spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70);
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000414
Uwe Hermann394131e2008-10-18 21:14:13 +0000415 printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000416 mmio_readw(spibar + 0x6c));
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000417
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000418 /* Not sure if it speaks all these bus protocols. */
419 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000420 spi_controller = SPI_CONTROLLER_VIA;
Rudolf Marek0c2029f2009-02-01 18:40:50 +0000421 ich_init_opcodes();
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000422
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000423 return 0;
424}
425
Uwe Hermann394131e2008-10-18 21:14:13 +0000426static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
427 int ich_generation)
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000428{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000429 int ret, i;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000430 uint8_t old, new, bbs, buc;
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000431 uint16_t spibar_offset, tmp2;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000432 uint32_t tmp, gcs;
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000433 void *rcrb;
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000434 //TODO: These names are incorrect for EP80579. For that, the solution would look like the commented line
435 //static const char *straps_names[] = {"SPI", "reserved", "reserved", "LPC" };
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000436 static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" };
Uwe Hermann394131e2008-10-18 21:14:13 +0000437
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000438 /* Enable Flash Writes */
439 ret = enable_flash_ich_dc(dev, name);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000440
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000441 /* Get physical address of Root Complex Register Block */
442 tmp = pci_read_long(dev, 0xf0) & 0xffffc000;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000443 printf_debug("\nRoot Complex Register Block address = 0x%x\n", tmp);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000444
445 /* Map RCBA to virtual memory */
Stefan Reinauer0593f212009-01-26 01:10:48 +0000446 rcrb = physmap("ICH RCRB", tmp, 0x4000);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000447
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000448 gcs = mmio_readl(rcrb + 0x3410);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000449 printf_debug("GCS = 0x%x: ", gcs);
450 printf_debug("BIOS Interface Lock-Down: %sabled, ",
451 (gcs & 0x1) ? "en" : "dis");
452 bbs = (gcs >> 10) & 0x3;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000453 printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000454
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000455 buc = mmio_readb(rcrb + 0x3414);
Uwe Hermann394131e2008-10-18 21:14:13 +0000456 printf_debug("Top Swap : %s\n",
457 (buc & 1) ? "enabled (A16 inverted)" : "not enabled");
Stefan Reinauera9424d52008-06-27 16:28:34 +0000458
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000459 /* It seems the ICH7 does not support SPI and LPC chips at the same
460 * time. At least not with our current code. So we prevent searching
461 * on ICH7 when the southbridge is strapped to LPC
462 */
463
464 if (ich_generation == 7 && bbs == ICH_STRAP_LPC) {
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000465 /* Not sure if it speaks LPC as well. */
466 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000467 /* No further SPI initialization required */
468 return ret;
469 }
470
471 switch (ich_generation) {
472 case 7:
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000473 buses_supported = CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000474 spi_controller = SPI_CONTROLLER_ICH7;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000475 spibar_offset = 0x3020;
476 break;
477 case 8:
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000478 /* Not sure if it speaks LPC as well. */
479 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000480 spi_controller = SPI_CONTROLLER_ICH9;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000481 spibar_offset = 0x3020;
482 break;
483 case 9:
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000484 case 10:
Uwe Hermann394131e2008-10-18 21:14:13 +0000485 default: /* Future version might behave the same */
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000486 /* Not sure if it speaks LPC as well. */
487 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000488 spi_controller = SPI_CONTROLLER_ICH9;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000489 spibar_offset = 0x3800;
490 break;
491 }
492
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000493 /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000494 printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000495
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000496 /* Assign Virtual Address */
Uwe Hermann394131e2008-10-18 21:14:13 +0000497 spibar = rcrb + spibar_offset;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000498
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000499 switch (spi_controller) {
500 case SPI_CONTROLLER_ICH7:
Uwe Hermann394131e2008-10-18 21:14:13 +0000501 printf_debug("0x00: 0x%04x (SPIS)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000502 mmio_readw(spibar + 0));
Uwe Hermann394131e2008-10-18 21:14:13 +0000503 printf_debug("0x02: 0x%04x (SPIC)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000504 mmio_readw(spibar + 2));
Uwe Hermann394131e2008-10-18 21:14:13 +0000505 printf_debug("0x04: 0x%08x (SPIA)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000506 mmio_readl(spibar + 4));
Uwe Hermann394131e2008-10-18 21:14:13 +0000507 for (i = 0; i < 8; i++) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000508 int offs;
509 offs = 8 + (i * 8);
Uwe Hermann394131e2008-10-18 21:14:13 +0000510 printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs,
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000511 mmio_readl(spibar + offs), i);
Uwe Hermann394131e2008-10-18 21:14:13 +0000512 printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000513 mmio_readl(spibar + offs + 4), i);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000514 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000515 printf_debug("0x50: 0x%08x (BBAR)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000516 mmio_readl(spibar + 0x50));
Uwe Hermann394131e2008-10-18 21:14:13 +0000517 printf_debug("0x54: 0x%04x (PREOP)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000518 mmio_readw(spibar + 0x54));
Uwe Hermann394131e2008-10-18 21:14:13 +0000519 printf_debug("0x56: 0x%04x (OPTYPE)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000520 mmio_readw(spibar + 0x56));
Uwe Hermann394131e2008-10-18 21:14:13 +0000521 printf_debug("0x58: 0x%08x (OPMENU)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000522 mmio_readl(spibar + 0x58));
Uwe Hermann394131e2008-10-18 21:14:13 +0000523 printf_debug("0x5c: 0x%08x (OPMENU+4)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000524 mmio_readl(spibar + 0x5c));
Uwe Hermann394131e2008-10-18 21:14:13 +0000525 for (i = 0; i < 4; i++) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000526 int offs;
527 offs = 0x60 + (i * 4);
Uwe Hermann394131e2008-10-18 21:14:13 +0000528 printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs,
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000529 mmio_readl(spibar + offs), i);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000530 }
531 printf_debug("\n");
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000532 if (mmio_readw(spibar) & (1 << 15)) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000533 printf("WARNING: SPI Configuration Lockdown activated.\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000534 ichspi_lock = 1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000535 }
FENG yu ningf041e9b2008-12-15 02:32:11 +0000536 ich_init_opcodes();
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000537 break;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000538 case SPI_CONTROLLER_ICH9:
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000539 tmp2 = mmio_readw(spibar + 4);
FENG yu ning37179b82009-01-18 06:39:32 +0000540 printf_debug("0x04: 0x%04x (HSFS)\n", tmp2);
541 printf_debug("FLOCKDN %i, ", (tmp2 >> 15 & 1));
542 printf_debug("FDV %i, ", (tmp2 >> 14) & 1);
543 printf_debug("FDOPSS %i, ", (tmp2 >> 13) & 1);
544 printf_debug("SCIP %i, ", (tmp2 >> 5) & 1);
545 printf_debug("BERASE %i, ", (tmp2 >> 3) & 3);
546 printf_debug("AEL %i, ", (tmp2 >> 2) & 1);
547 printf_debug("FCERR %i, ", (tmp2 >> 1) & 1);
548 printf_debug("FDONE %i\n", (tmp2 >> 0) & 1);
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000549
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000550 tmp = mmio_readl(spibar + 0x50);
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000551 printf_debug("0x50: 0x%08x (FRAP)\n", tmp);
552 printf_debug("BMWAG %i, ", (tmp >> 24) & 0xff);
553 printf_debug("BMRAG %i, ", (tmp >> 16) & 0xff);
554 printf_debug("BRWA %i, ", (tmp >> 8) & 0xff);
555 printf_debug("BRRA %i\n", (tmp >> 0) & 0xff);
556
557 printf_debug("0x54: 0x%08x (FREG0)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000558 mmio_readl(spibar + 0x54));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000559 printf_debug("0x58: 0x%08x (FREG1)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000560 mmio_readl(spibar + 0x58));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000561 printf_debug("0x5C: 0x%08x (FREG2)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000562 mmio_readl(spibar + 0x5C));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000563 printf_debug("0x60: 0x%08x (FREG3)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000564 mmio_readl(spibar + 0x60));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000565 printf_debug("0x64: 0x%08x (FREG4)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000566 mmio_readl(spibar + 0x64));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000567 printf_debug("0x74: 0x%08x (PR0)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000568 mmio_readl(spibar + 0x74));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000569 printf_debug("0x78: 0x%08x (PR1)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000570 mmio_readl(spibar + 0x78));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000571 printf_debug("0x7C: 0x%08x (PR2)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000572 mmio_readl(spibar + 0x7C));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000573 printf_debug("0x80: 0x%08x (PR3)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000574 mmio_readl(spibar + 0x80));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000575 printf_debug("0x84: 0x%08x (PR4)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000576 mmio_readl(spibar + 0x84));
FENG yu ning37179b82009-01-18 06:39:32 +0000577 printf_debug("0x90: 0x%08x (SSFS, SSFC)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000578 mmio_readl(spibar + 0x90));
FENG yu ning37179b82009-01-18 06:39:32 +0000579 printf_debug("0x94: 0x%04x (PREOP)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000580 mmio_readw(spibar + 0x94));
FENG yu ning37179b82009-01-18 06:39:32 +0000581 printf_debug("0x96: 0x%04x (OPTYPE)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000582 mmio_readw(spibar + 0x96));
FENG yu ning37179b82009-01-18 06:39:32 +0000583 printf_debug("0x98: 0x%08x (OPMENU)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000584 mmio_readl(spibar + 0x98));
FENG yu ning37179b82009-01-18 06:39:32 +0000585 printf_debug("0x9C: 0x%08x (OPMENU+4)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000586 mmio_readl(spibar + 0x9C));
FENG yu ning37179b82009-01-18 06:39:32 +0000587 printf_debug("0xA0: 0x%08x (BBAR)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000588 mmio_readl(spibar + 0xA0));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000589 printf_debug("0xB0: 0x%08x (FDOC)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000590 mmio_readl(spibar + 0xB0));
FENG yu ning37179b82009-01-18 06:39:32 +0000591 if (tmp2 & (1 << 15)) {
592 printf("WARNING: SPI Configuration Lockdown activated.\n");
593 ichspi_lock = 1;
594 }
Peter Stugee8a3e4c2008-12-22 14:12:08 +0000595 ich_init_opcodes();
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000596 break;
597 default:
598 /* Nothing */
599 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000600 }
601
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000602 old = pci_read_byte(dev, 0xdc);
603 printf_debug("SPI Read Configuration: ");
604 new = (old >> 2) & 0x3;
605 switch (new) {
606 case 0:
607 case 1:
608 case 2:
609 printf_debug("prefetching %sabled, caching %sabled, ",
Uwe Hermann394131e2008-10-18 21:14:13 +0000610 (new & 0x2) ? "en" : "dis",
611 (new & 0x1) ? "dis" : "en");
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000612 break;
613 default:
614 printf_debug("invalid prefetching/caching settings, ");
615 break;
616 }
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000617
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000618 return ret;
619}
Stefan Reinauera9424d52008-06-27 16:28:34 +0000620
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000621static int enable_flash_ich7(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000622{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000623 return enable_flash_ich_dc_spi(dev, name, 7);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000624}
625
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000626static int enable_flash_ich8(struct pci_dev *dev, const char *name)
627{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000628 return enable_flash_ich_dc_spi(dev, name, 8);
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000629}
630
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000631static int enable_flash_ich9(struct pci_dev *dev, const char *name)
632{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000633 return enable_flash_ich_dc_spi(dev, name, 9);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000634}
635
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000636static int enable_flash_ich10(struct pci_dev *dev, const char *name)
637{
638 return enable_flash_ich_dc_spi(dev, name, 10);
639}
640
Uwe Hermann372eeb52007-12-04 21:49:06 +0000641static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000642{
Ollie Lho184a4042005-11-26 21:55:36 +0000643 uint8_t val;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000644
Uwe Hermann394131e2008-10-18 21:14:13 +0000645 /* enable ROM decode range (1MB) FFC00000 - FFFFFFFF */
Bari Ari9477c4e2008-04-29 13:46:38 +0000646 pci_write_byte(dev, 0x41, 0x7f);
647
Uwe Hermannffec5f32007-08-23 16:08:21 +0000648 /* ROM write enable */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000649 val = pci_read_byte(dev, 0x40);
650 val |= 0x10;
651 pci_write_byte(dev, 0x40, val);
652
653 if (pci_read_byte(dev, 0x40) != val) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000654 printf("\nWARNING: Failed to enable flash write on \"%s\"\n",
Uwe Hermanna7e05482007-05-09 10:17:44 +0000655 name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000656 return -1;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000657 }
Luc Verhaegen6382b442007-03-02 22:16:38 +0000658
Uwe Hermanna7e05482007-05-09 10:17:44 +0000659 return 0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000660}
661
Uwe Hermann372eeb52007-12-04 21:49:06 +0000662static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000663{
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000664 uint8_t reg8;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000665
Uwe Hermann394131e2008-10-18 21:14:13 +0000666#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
667#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000668
Uwe Hermann394131e2008-10-18 21:14:13 +0000669#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
670#define ROM_WRITE_ENABLE (1 << 1)
671#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
672#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000673
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000674 /* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
675 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
676 * Make the configured ROM areas writable.
677 */
678 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
679 reg8 |= LOWER_ROM_ADDRESS_RANGE;
680 reg8 |= UPPER_ROM_ADDRESS_RANGE;
681 reg8 |= ROM_WRITE_ENABLE;
682 pci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000683
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000684 /* Set positive decode on ROM. */
685 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
686 reg8 |= BIOS_ROM_POSITIVE_DECODE;
687 pci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000688
Ollie Lhocbbf1252004-03-17 22:22:08 +0000689 return 0;
690}
691
Mart Raudseppe1344da2008-02-08 10:10:57 +0000692/**
693 * Geode systems write protect the BIOS via RCONFs (cache settings similar
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000694 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
Mart Raudseppe1344da2008-02-08 10:10:57 +0000695 *
696 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
697 * To enable write to NOR Boot flash for the benefit of systems that have such
698 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
Mart Raudseppe1344da2008-02-08 10:10:57 +0000699 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000700static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
Lane Brooksd54958a2007-11-13 16:45:22 +0000701{
Uwe Hermann394131e2008-10-18 21:14:13 +0000702#define MSR_RCONF_DEFAULT 0x1808
703#define MSR_NORF_CTL 0x51400018
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000704
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000705 msr_t msr;
Lane Brooksd54958a2007-11-13 16:45:22 +0000706
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000707 /* Geode only has a single core */
708 if (setup_cpu_msr(0))
Lane Brooksd54958a2007-11-13 16:45:22 +0000709 return -1;
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000710
711 msr = rdmsr(MSR_RCONF_DEFAULT);
712 if ((msr.hi >> 24) != 0x22) {
713 msr.hi &= 0xfbffffff;
714 wrmsr(MSR_RCONF_DEFAULT, msr);
Lane Brooksd54958a2007-11-13 16:45:22 +0000715 }
Mart Raudseppe1344da2008-02-08 10:10:57 +0000716
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000717 msr = rdmsr(MSR_NORF_CTL);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000718 /* Raise WE_CS3 bit. */
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000719 msr.lo |= 0x08;
720 wrmsr(MSR_NORF_CTL, msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000721
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000722 cleanup_cpu_msr();
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000723
Uwe Hermann394131e2008-10-18 21:14:13 +0000724#undef MSR_RCONF_DEFAULT
725#undef MSR_NORF_CTL
Lane Brooksd54958a2007-11-13 16:45:22 +0000726 return 0;
727}
728
Uwe Hermann372eeb52007-12-04 21:49:06 +0000729static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000730{
Ollie Lho184a4042005-11-26 21:55:36 +0000731 uint8_t new;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000732
Ollie Lhocbbf1252004-03-17 22:22:08 +0000733 pci_write_byte(dev, 0x52, 0xee);
734
735 new = pci_read_byte(dev, 0x52);
736
737 if (new != 0xee) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000738 printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000739 return -1;
740 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000741
Ollie Lhocbbf1252004-03-17 22:22:08 +0000742 return 0;
743}
744
Uwe Hermann190f8492008-10-25 18:03:50 +0000745/* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000746static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000747{
Ollie Lho184a4042005-11-26 21:55:36 +0000748 uint8_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000749
Uwe Hermann372eeb52007-12-04 21:49:06 +0000750 /* Enable decoding at 0xffb00000 to 0xffffffff. */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000751 old = pci_read_byte(dev, 0x43);
Ollie Lhod11f3612004-12-07 17:19:04 +0000752 new = old | 0xC0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000753 if (new != old) {
754 pci_write_byte(dev, 0x43, new);
755 if (pci_read_byte(dev, 0x43) != new) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000756 printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000757 }
758 }
759
Uwe Hermann190f8492008-10-25 18:03:50 +0000760 /* Enable 'ROM write' bit. */
Ollie Lho761bf1b2004-03-20 16:46:10 +0000761 old = pci_read_byte(dev, 0x40);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000762 new = old | 0x01;
763 if (new == old)
764 return 0;
765 pci_write_byte(dev, 0x40, new);
766
767 if (pci_read_byte(dev, 0x40) != new) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000768 printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000769 return -1;
770 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000771
Ollie Lhocbbf1252004-03-17 22:22:08 +0000772 return 0;
773}
774
Marc Jones3af487d2008-10-15 17:50:29 +0000775static int enable_flash_sb600(struct pci_dev *dev, const char *name)
776{
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000777 uint32_t tmp, prot;
Marc Jones3af487d2008-10-15 17:50:29 +0000778 uint8_t reg;
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000779 struct pci_dev *smbus_dev;
780 int has_spi = 1;
Marc Jones3af487d2008-10-15 17:50:29 +0000781
Jason Wanga3f04be2008-11-28 21:36:51 +0000782 /* Clear ROM protect 0-3. */
783 for (reg = 0x50; reg < 0x60; reg += 4) {
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000784 prot = pci_read_long(dev, reg);
785 /* No protection flags for this region?*/
786 if ((prot & 0x3) == 0)
787 continue;
788 printf_debug("SB600 %s%sprotected from %u to %u\n",
789 (prot & 0x1) ? "write " : "",
790 (prot & 0x2) ? "read " : "",
791 (prot & 0xfffffc00),
792 (prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
793 prot &= 0xfffffffc;
794 pci_write_byte(dev, reg, prot);
795 prot = pci_read_long(dev, reg);
Carl-Daniel Hailfinger9bb88ac2009-05-06 13:51:44 +0000796 if (prot & 0x3)
Peter Stuge19997ae2009-05-06 15:05:39 +0000797 printf("SB600 %s%sunprotect failed from %u to %u\n",
Carl-Daniel Hailfinger9bb88ac2009-05-06 13:51:44 +0000798 (prot & 0x1) ? "write " : "",
799 (prot & 0x2) ? "read " : "",
800 (prot & 0xfffffc00),
801 (prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
Jason Wanga3f04be2008-11-28 21:36:51 +0000802 }
803
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000804 /* Read SPI_BaseAddr */
805 tmp = pci_read_long(dev, 0xa0);
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000806 tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000807 printf_debug("SPI base address is at 0x%x\n", tmp);
808
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000809 /* If the BAR has address 0, it is unlikely SPI is used. */
810 if (!tmp)
811 has_spi = 0;
812
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000813 if (has_spi) {
814 /* Physical memory has to be mapped at page (4k) boundaries. */
815 sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000,
816 0x1000);
817 /* The low bits of the SPI base address are used as offset into
818 * the mapped page.
819 */
820 sb600_spibar += tmp & 0xfff;
821
822 tmp = pci_read_long(dev, 0xa0);
823 printf_debug("AltSpiCSEnable=%i, SpiRomEnable=%i, "
824 "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1,
825 (tmp & 0x4) >> 2);
826 tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2;
827 printf_debug("PrefetchEnSPIFromIMC=%i, ", tmp);
828
829 tmp = pci_read_byte(dev, 0xbb);
830 printf_debug("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n",
831 tmp & 0x1, (tmp & 0x20) >> 5);
832 tmp = mmio_readl(sb600_spibar);
833 printf_debug("SpiArbEnable=%i, SpiAccessMacRomEn=%i, "
834 "SpiHostAccessRomEn=%i, ArbWaitCount=%i, "
835 "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n",
836 (tmp >> 19) & 0x1, (tmp >> 22) & 0x1,
837 (tmp >> 23) & 0x1, (tmp >> 24) & 0x7,
838 (tmp >> 27) & 0x1, (tmp >> 28) & 0x1);
839 }
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000840
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000841 /* Look for the SMBus device. */
842 smbus_dev = pci_dev_find(0x1002, 0x4385);
843
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000844 if (has_spi && !smbus_dev) {
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000845 fprintf(stderr, "ERROR: SMBus device not found. Not enabling SPI.\n");
846 has_spi = 0;
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000847 }
848 if (has_spi) {
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000849 /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */
850 /* GPIO11/SPI_DO and GPIO12/SPI_DI status */
851 reg = pci_read_byte(smbus_dev, 0xAB);
852 reg &= 0xC0;
853 printf_debug("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO");
854 printf_debug("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI");
855 if (reg != 0x00)
856 has_spi = 0;
857 /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */
858 reg = pci_read_byte(smbus_dev, 0x83);
859 reg &= 0xC0;
860 printf_debug("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD");
861 printf_debug("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000862 /* SPI_HOLD is not used on all boards, filter it out. */
863 if ((reg & 0x80) != 0x00)
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000864 has_spi = 0;
865 /* GPIO47/SPI_CLK status */
866 reg = pci_read_byte(smbus_dev, 0xA7);
867 reg &= 0x40;
868 printf_debug("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK");
869 if (reg != 0x00)
870 has_spi = 0;
871 }
872
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000873 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH;
874 if (has_spi) {
875 buses_supported |= CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000876 spi_controller = SPI_CONTROLLER_SB600;
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000877 }
Jason Wanga3f04be2008-11-28 21:36:51 +0000878
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000879 /* Read ROM strap override register. */
880 OUTB(0x8f, 0xcd6);
881 reg = INB(0xcd7);
882 reg &= 0x0e;
883 printf_debug("ROM strap override is %sactive", (reg & 0x02) ? "" : "not ");
884 if (reg & 0x02) {
885 switch ((reg & 0x0c) >> 2) {
886 case 0x00:
887 printf_debug(": LPC");
888 break;
889 case 0x01:
890 printf_debug(": PCI");
891 break;
892 case 0x02:
893 printf_debug(": FWH");
894 break;
895 case 0x03:
896 printf_debug(": SPI");
897 break;
898 }
899 }
900 printf_debug("\n");
901
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000902 /* Force enable SPI ROM in SB600 PM register.
903 * If we enable SPI ROM here, we have to disable it after we leave.
Zheng Bao284a6002009-05-04 22:33:50 +0000904 * But how can we know which ROM we are going to handle? So we have
905 * to trade off. We only access LPC ROM if we boot via LPC ROM. And
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000906 * only SPI ROM if we boot via SPI ROM. If you want to access SPI on
907 * boards with LPC straps, you have to use the code below.
Zheng Bao284a6002009-05-04 22:33:50 +0000908 */
909 /*
Jason Wanga3f04be2008-11-28 21:36:51 +0000910 OUTB(0x8f, 0xcd6);
911 OUTB(0x0e, 0xcd7);
Zheng Bao284a6002009-05-04 22:33:50 +0000912 */
Marc Jones3af487d2008-10-15 17:50:29 +0000913
914 return 0;
915}
916
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000917static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name)
918{
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000919 uint8_t tmp;
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000920
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000921 pci_write_byte(dev, 0x92, 0);
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000922
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000923 tmp = pci_read_byte(dev, 0x6d);
924 tmp |= 0x01;
925 pci_write_byte(dev, 0x6d, tmp);
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000926
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000927 return 0;
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000928}
929
Uwe Hermann372eeb52007-12-04 21:49:06 +0000930static int enable_flash_ck804(struct pci_dev *dev, const char *name)
Yinghai Lu952dfce2005-07-06 17:13:46 +0000931{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000932 uint8_t old, new;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000933
Uwe Hermanna7e05482007-05-09 10:17:44 +0000934 old = pci_read_byte(dev, 0x88);
935 new = old | 0xc0;
936 if (new != old) {
937 pci_write_byte(dev, 0x88, new);
938 if (pci_read_byte(dev, 0x88) != new) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000939 printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000940 }
941 }
Yinghai Lu952dfce2005-07-06 17:13:46 +0000942
Uwe Hermanna7e05482007-05-09 10:17:44 +0000943 old = pci_read_byte(dev, 0x6d);
944 new = old | 0x01;
945 if (new == old)
946 return 0;
947 pci_write_byte(dev, 0x6d, new);
948
949 if (pci_read_byte(dev, 0x6d) != new) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000950 printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000951 return -1;
952 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000953
Uwe Hermanna7e05482007-05-09 10:17:44 +0000954 return 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000955}
956
Uwe Hermann372eeb52007-12-04 21:49:06 +0000957/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
958static int enable_flash_sb400(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000959{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000960 uint8_t tmp;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000961 struct pci_dev *smbusdev;
962
Uwe Hermann372eeb52007-12-04 21:49:06 +0000963 /* Look for the SMBus device. */
Carl-Daniel Hailfingerf6e3efb2009-05-06 00:35:31 +0000964 smbusdev = pci_dev_find(0x1002, 0x4372);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000965
Uwe Hermanna7e05482007-05-09 10:17:44 +0000966 if (!smbusdev) {
Uwe Hermann372eeb52007-12-04 21:49:06 +0000967 fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n");
Stefan Reinauer86de2832006-03-31 11:26:55 +0000968 exit(1);
969 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000970
Uwe Hermann372eeb52007-12-04 21:49:06 +0000971 /* Enable some SMBus stuff. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000972 tmp = pci_read_byte(smbusdev, 0x79);
973 tmp |= 0x01;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000974 pci_write_byte(smbusdev, 0x79, tmp);
975
Uwe Hermann372eeb52007-12-04 21:49:06 +0000976 /* Change southbridge. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000977 tmp = pci_read_byte(dev, 0x48);
978 tmp |= 0x21;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000979 pci_write_byte(dev, 0x48, tmp);
980
Uwe Hermann372eeb52007-12-04 21:49:06 +0000981 /* Now become a bit silly. */
Andriy Gapon65c1b862008-05-22 13:22:45 +0000982 tmp = INB(0xc6f);
983 OUTB(tmp, 0xeb);
984 OUTB(tmp, 0xeb);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000985 tmp |= 0x40;
Andriy Gapon65c1b862008-05-22 13:22:45 +0000986 OUTB(tmp, 0xc6f);
987 OUTB(tmp, 0xeb);
988 OUTB(tmp, 0xeb);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000989
990 return 0;
991}
992
Uwe Hermann372eeb52007-12-04 21:49:06 +0000993static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
Yinghai Luca782972007-01-22 20:21:17 +0000994{
Uwe Hermann372eeb52007-12-04 21:49:06 +0000995 uint8_t old, new, byte;
996 uint16_t word;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000997
Uwe Hermann372eeb52007-12-04 21:49:06 +0000998 /* Set the 0-16 MB enable bits. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000999 byte = pci_read_byte(dev, 0x88);
1000 byte |= 0xff; /* 256K */
1001 pci_write_byte(dev, 0x88, byte);
1002 byte = pci_read_byte(dev, 0x8c);
1003 byte |= 0xff; /* 1M */
1004 pci_write_byte(dev, 0x8c, byte);
1005 word = pci_read_word(dev, 0x90);
Carl-Daniel Hailfingerdca0ab12007-10-17 22:30:07 +00001006 word |= 0x7fff; /* 16M */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001007 pci_write_word(dev, 0x90, word);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +00001008
Uwe Hermanna7e05482007-05-09 10:17:44 +00001009 old = pci_read_byte(dev, 0x6d);
1010 new = old | 0x01;
1011 if (new == old)
1012 return 0;
1013 pci_write_byte(dev, 0x6d, new);
Yinghai Luca782972007-01-22 20:21:17 +00001014
Uwe Hermanna7e05482007-05-09 10:17:44 +00001015 if (pci_read_byte(dev, 0x6d) != new) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +00001016 printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001017 return -1;
1018 }
Yinghai Luca782972007-01-22 20:21:17 +00001019
1020 return 0;
Yinghai Luca782972007-01-22 20:21:17 +00001021}
1022
Uwe Hermann372eeb52007-12-04 21:49:06 +00001023static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001024{
Uwe Hermanne823ee02007-06-05 15:02:18 +00001025 uint8_t byte;
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001026
Uwe Hermanne823ee02007-06-05 15:02:18 +00001027 /* Set the 4MB enable bit. */
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001028 byte = pci_read_byte(dev, 0x41);
1029 byte |= 0x0e;
1030 pci_write_byte(dev, 0x41, byte);
1031
1032 byte = pci_read_byte(dev, 0x43);
Uwe Hermannffec5f32007-08-23 16:08:21 +00001033 byte |= (1 << 4);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001034 pci_write_byte(dev, 0x43, byte);
1035
Stefan Reinauerc868b9e2007-06-05 10:28:39 +00001036 return 0;
1037}
1038
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001039/**
1040 * Usually on the x86 architectures (and on other PC-like platforms like some
1041 * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
1042 * Elan SC520 only a small piece of the system flash is mapped there, but the
1043 * complete flash is mapped somewhere below 1G. The position can be determined
1044 * by the BOOTCS PAR register.
1045 */
1046static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
1047{
1048 int i, bootcs_found = 0;
1049 uint32_t parx = 0;
1050 void *mmcr;
1051
1052 /* 1. Map MMCR */
Stefan Reinauer0593f212009-01-26 01:10:48 +00001053 mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001054
1055 /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for
1056 * BOOTCS region (PARx[31:29] = 100b)e
1057 */
1058 for (i = 0x88; i <= 0xc4; i += 4) {
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +00001059 parx = mmio_readl(mmcr + i);
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001060 if ((parx >> 29) == 4) {
1061 bootcs_found = 1;
1062 break; /* BOOTCS found */
1063 }
1064 }
1065
1066 /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0]
1067 * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0]
1068 */
1069 if (bootcs_found) {
1070 if (parx & (1 << 25)) {
1071 parx &= (1 << 14) - 1; /* Mask [13:0] */
1072 flashbase = parx << 16;
1073 } else {
1074 parx &= (1 << 18) - 1; /* Mask [17:0] */
1075 flashbase = parx << 12;
1076 }
1077 } else {
1078 printf("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n");
1079 }
1080
1081 /* 4. Clean up */
Carl-Daniel Hailfingerbe726812009-08-09 12:44:08 +00001082 physunmap(mmcr, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +00001083 return 0;
1084}
1085
Uwe Hermann4179d292009-05-08 17:50:51 +00001086/* Please keep this list alphabetically sorted by vendor/device. */
Uwe Hermann05fab752009-05-16 23:42:17 +00001087const struct penable chipset_enables[] = {
Uwe Hermann4179d292009-05-08 17:50:51 +00001088 {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533},
1089 {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111},
1090 {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111},
1091 {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530},
1092 {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536},
Nils Jacobse715c7b2009-09-23 02:09:23 +00001093 {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536},
Uwe Hermann4179d292009-05-08 17:50:51 +00001094 {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520},
1095 {0x1002, 0x438D, OK, "AMD", "SB600", enable_flash_sb600},
Carl-Daniel Hailfinger174962d2009-09-01 22:13:42 +00001096 {0x1002, 0x439d, OK, "AMD", "SB700/SB710/SB750", enable_flash_sb600},
Uwe Hermann4179d292009-05-08 17:50:51 +00001097 {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100},
1098 {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400},
1099 {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000},
Carl-Daniel Hailfinger797a8342009-11-26 16:51:39 +00001100 {0x8086, 0x3b00, NT, "Intel", "3400 Desktop", enable_flash_ich10},
1101 {0x8086, 0x3b01, NT, "Intel", "3400 Mobile", enable_flash_ich10},
1102 {0x8086, 0x3b0d, NT, "Intel", "3400 Mobile SFF", enable_flash_ich10},
Uwe Hermannb0039912009-05-07 13:24:49 +00001103 {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4},
Uwe Hermann4179d292009-05-08 17:50:51 +00001104 {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich_4e},
1105 {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich_dc},
1106 {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7},
Uwe Hermannb0039912009-05-07 13:24:49 +00001107 {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e},
Uwe Hermann4179d292009-05-08 17:50:51 +00001108 {0x8086, 0x3a18, OK, "Intel", "ICH10", enable_flash_ich10},
1109 {0x8086, 0x3a1a, OK, "Intel", "ICH10D", enable_flash_ich10},
1110 {0x8086, 0x3a14, OK, "Intel", "ICH10DO", enable_flash_ich10},
1111 {0x8086, 0x3a16, OK, "Intel", "ICH10R", enable_flash_ich10},
Uwe Hermannb0039912009-05-07 13:24:49 +00001112 {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e},
1113 {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +00001114 {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich_4e},
Uwe Hermann4179d292009-05-08 17:50:51 +00001115 {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +00001116 {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich_4e},
1117 {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich_4e},
1118 {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +00001119 {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich_dc},
1120 {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich_dc},
Uwe Hermannb0039912009-05-07 13:24:49 +00001121 {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7},
1122 {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7},
1123 {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7},
1124 {0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7},
Uwe Hermann4179d292009-05-08 17:50:51 +00001125 {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +00001126 {0x8086, 0x2812, OK, "Intel", "ICH8DH", enable_flash_ich8},
1127 {0x8086, 0x2814, OK, "Intel", "ICH8DO", enable_flash_ich8},
Uwe Hermann4179d292009-05-08 17:50:51 +00001128 {0x8086, 0x2810, OK, "Intel", "ICH8/ICH8R", enable_flash_ich8},
Uwe Hermannb0039912009-05-07 13:24:49 +00001129 {0x8086, 0x2815, OK, "Intel", "ICH8M", enable_flash_ich8},
Uwe Hermann4179d292009-05-08 17:50:51 +00001130 {0x8086, 0x2811, OK, "Intel", "ICH8M-E", enable_flash_ich8},
1131 {0x8086, 0x2918, OK, "Intel", "ICH9", enable_flash_ich9},
Uwe Hermannb0039912009-05-07 13:24:49 +00001132 {0x8086, 0x2912, OK, "Intel", "ICH9DH", enable_flash_ich9},
1133 {0x8086, 0x2914, OK, "Intel", "ICH9DO", enable_flash_ich9},
Uwe Hermannb0039912009-05-07 13:24:49 +00001134 {0x8086, 0x2919, OK, "Intel", "ICH9M", enable_flash_ich9},
Uwe Hermann4179d292009-05-08 17:50:51 +00001135 {0x8086, 0x2917, OK, "Intel", "ICH9M-E", enable_flash_ich9},
1136 {0x8086, 0x2916, OK, "Intel", "ICH9R", enable_flash_ich9},
Carl-Daniel Hailfinger95baaad2009-08-21 17:26:13 +00001137 {0x8086, 0x2910, OK, "Intel", "ICH9 Engineering Sample", enable_flash_ich9},
Uwe Hermann4179d292009-05-08 17:50:51 +00001138 {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4},
1139 {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4},
1140 {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4},
1141 {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4},
Luc Verhaegenaad7e672009-10-06 11:32:21 +00001142 {0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2},
Uwe Hermannb0039912009-05-07 13:24:49 +00001143 {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */
1144 {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */
Luc Verhaegen90e8e612009-05-26 09:48:28 +00001145 {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2},
Uwe Hermanneac10162008-03-13 18:52:51 +00001146 /* Slave, should not be here, to fix known bug for A01. */
Uwe Hermannb0039912009-05-07 13:24:49 +00001147 {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804},
1148 {0x10de, 0x0260, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1149 {0x10de, 0x0261, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1150 {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1151 {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1152 {0x10de, 0x0360, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/
1153 {0x10de, 0x0361, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1154 {0x10de, 0x0362, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1155 {0x10de, 0x0363, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1156 {0x10de, 0x0364, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1157 {0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1158 {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1159 {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */
1160 {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp55},
Carl-Daniel Hailfinger6a0269e2009-11-15 17:20:21 +00001161 {0x1039, 0x0496, NT, "SiS", "85C496+497", enable_flash_sis85c496},
1162 {0x1039, 0x0406, NT, "SiS", "501/5101/5501", enable_flash_sis501},
1163 {0x1039, 0x5511, NT, "SiS", "5511", enable_flash_sis5511},
1164 {0x1039, 0x5596, NT, "SiS", "5596", enable_flash_sis5596},
1165 {0x1039, 0x5571, NT, "SiS", "5571", enable_flash_sis530},
1166 {0x1039, 0x5591, NT, "SiS", "5591/5592", enable_flash_sis530},
1167 {0x1039, 0x5597, NT, "SiS", "5597/5598/5581/5120", enable_flash_sis530},
1168 {0x1039, 0x0530, NT, "SiS", "530", enable_flash_sis530},
1169 {0x1039, 0x5600, NT, "SiS", "600", enable_flash_sis530},
1170 {0x1039, 0x0620, NT, "SiS", "620", enable_flash_sis530},
1171 {0x1039, 0x0540, NT, "SiS", "540", enable_flash_sis540},
1172 {0x1039, 0x0630, NT, "SiS", "630", enable_flash_sis630},
1173 {0x1039, 0x0635, NT, "SiS", "635", enable_flash_sis630},
1174 {0x1039, 0x0640, NT, "SiS", "640", enable_flash_sis630},
1175 {0x1039, 0x0645, NT, "SiS", "645", enable_flash_sis630},
1176 {0x1039, 0x0646, NT, "SiS", "645DX", enable_flash_sis630},
1177 {0x1039, 0x0648, NT, "SiS", "648", enable_flash_sis630},
1178 {0x1039, 0x0650, NT, "SiS", "650", enable_flash_sis630},
1179 {0x1039, 0x0651, NT, "SiS", "651", enable_flash_sis630},
1180 {0x1039, 0x0655, NT, "SiS", "655", enable_flash_sis630},
1181 {0x1039, 0x0730, NT, "SiS", "730", enable_flash_sis630},
1182 {0x1039, 0x0733, NT, "SiS", "733", enable_flash_sis630},
1183 {0x1039, 0x0735, OK, "SiS", "735", enable_flash_sis630},
1184 {0x1039, 0x0740, NT, "SiS", "740", enable_flash_sis630},
1185 {0x1039, 0x0745, NT, "SiS", "745", enable_flash_sis630},
1186 {0x1039, 0x0746, NT, "SiS", "746", enable_flash_sis630},
1187 {0x1039, 0x0748, NT, "SiS", "748", enable_flash_sis630},
1188 {0x1039, 0x0755, NT, "SiS", "755", enable_flash_sis630},
Uwe Hermann4179d292009-05-08 17:50:51 +00001189 {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x},
1190 {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x},
Mateusz Murawskie6abef02009-06-18 12:42:46 +00001191 {0x1106, 0x3074, NT, "VIA", "VT8233", enable_flash_vt823x},
Uwe Hermann4179d292009-05-08 17:50:51 +00001192 {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x},
1193 {0x1106, 0x3227, OK, "VIA", "VT8237", enable_flash_vt823x},
1194 {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x},
1195 {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi},
Arjan Koers8dfea832009-06-15 00:03:37 +00001196 {0x1106, 0x8353, OK, "VIA", "VX800", enable_flash_vt8237s_spi},
Uwe Hermann3e0774d2009-09-25 01:05:06 +00001197 {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111},
Uwe Hermann4179d292009-05-08 17:50:51 +00001198 {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111},
1199 {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111},
Uwe Hermann05fab752009-05-16 23:42:17 +00001200
1201 {},
Ollie Lhocbbf1252004-03-17 22:22:08 +00001202};
Ollie Lho761bf1b2004-03-20 16:46:10 +00001203
Uwe Hermanna7e05482007-05-09 10:17:44 +00001204int chipset_flash_enable(void)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001205{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001206 struct pci_dev *dev = 0;
Uwe Hermann372eeb52007-12-04 21:49:06 +00001207 int ret = -2; /* Nothing! */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001208 int i;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001209
Uwe Hermann372eeb52007-12-04 21:49:06 +00001210 /* Now let's try to find the chipset we have... */
Uwe Hermann05fab752009-05-16 23:42:17 +00001211 for (i = 0; chipset_enables[i].vendor_name != NULL; i++) {
1212 dev = pci_dev_find(chipset_enables[i].vendor_id,
1213 chipset_enables[i].device_id);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001214 if (dev)
1215 break;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001216 }
1217
Uwe Hermanna7e05482007-05-09 10:17:44 +00001218 if (dev) {
Uwe Hermannb0039912009-05-07 13:24:49 +00001219 printf("Found chipset \"%s %s\", enabling flash write... ",
Uwe Hermann05fab752009-05-16 23:42:17 +00001220 chipset_enables[i].vendor_name,
1221 chipset_enables[i].device_name);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001222
Uwe Hermann05fab752009-05-16 23:42:17 +00001223 ret = chipset_enables[i].doit(dev,
1224 chipset_enables[i].device_name);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001225 if (ret)
Uwe Hermanna502dce2007-10-17 23:55:15 +00001226 printf("FAILED!\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00001227 else
Uwe Hermannac309342007-10-10 17:42:20 +00001228 printf("OK.\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00001229 }
Uwe Hermann1432a602009-06-28 23:26:37 +00001230 printf("This chipset supports the following protocols: %s.\n",
Uwe Hermann9899cad2009-06-28 21:47:57 +00001231 flashbuses_to_text(buses_supported));
Uwe Hermanna7e05482007-05-09 10:17:44 +00001232
1233 return ret;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001234}