blob: 8ca55e1fde3e45286b18b2d754bd574af9052743 [file] [log] [blame]
Ollie Lho184a4042005-11-26 21:55:36 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ollie Lho184a4042005-11-26 21:55:36 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
Stefan Reinauer8fa64812009-08-12 09:27:45 +00005 * Copyright (C) 2005-2009 coresystems GmbH
Uwe Hermannd1107642007-08-29 17:52:32 +00006 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Ollie Lho184a4042005-11-26 21:55:36 +00007 *
Uwe Hermannd1107642007-08-29 17:52:32 +00008 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
Ollie Lho184a4042005-11-26 21:55:36 +000011 *
Uwe Hermannd1107642007-08-29 17:52:32 +000012 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22/*
23 * Contains the chipset specific flash enables.
Ollie Lho184a4042005-11-26 21:55:36 +000024 */
25
Lane Brooksd54958a2007-11-13 16:45:22 +000026#define _LARGEFILE64_SOURCE
27
Ollie Lhocbbf1252004-03-17 22:22:08 +000028#include <stdlib.h>
Uwe Hermanne8ba5382009-05-22 11:37:27 +000029#include <string.h>
Lane Brooksd54958a2007-11-13 16:45:22 +000030#include <sys/types.h>
31#include <sys/stat.h>
32#include <fcntl.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000033#include "flash.h"
Stefan Reinauer86de2832006-03-31 11:26:55 +000034
Stefan Reinauer9a6d1762008-12-03 21:24:40 +000035unsigned long flashbase = 0;
36
Stefan Reinauer2cb94e12008-06-30 23:45:22 +000037/**
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +000038 * flashrom defaults to Parallel/LPC/FWH flash devices. If a known host
39 * controller is found, the init routine sets the buses_supported bitfield to
40 * contain the supported buses for that controller.
Stefan Reinauer2cb94e12008-06-30 23:45:22 +000041 */
42
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +000043enum chipbustype buses_supported = CHIP_BUSTYPE_NONSPI;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +000044
FENG yu ningc05a2952008-12-08 18:16:58 +000045extern int ichspi_lock;
46
Uwe Hermann372eeb52007-12-04 21:49:06 +000047static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
Luc Verhaegen6b141752007-05-20 16:16:13 +000048{
49 uint8_t tmp;
50
Uwe Hermann372eeb52007-12-04 21:49:06 +000051 /*
52 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
53 * 0xFFFE0000-0xFFFFFFFF ROM select enable.
54 */
Luc Verhaegen6b141752007-05-20 16:16:13 +000055 tmp = pci_read_byte(dev, 0x47);
56 tmp |= 0x46;
57 pci_write_byte(dev, 0x47, tmp);
58
59 return 0;
60}
61
Uwe Hermann372eeb52007-12-04 21:49:06 +000062static int enable_flash_sis630(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +000063{
Uwe Hermann372eeb52007-12-04 21:49:06 +000064 uint8_t b;
Ollie Lhocbbf1252004-03-17 22:22:08 +000065
Uwe Hermann372eeb52007-12-04 21:49:06 +000066 /* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
Alex Beregszaszic9fb5d92007-09-11 15:58:18 +000067 b = pci_read_byte(dev, 0x40);
68 pci_write_byte(dev, 0x40, b | 0xb);
Uwe Hermann372eeb52007-12-04 21:49:06 +000069
70 /* Flash write enable on SiS 540/630. */
Alex Beregszaszic9fb5d92007-09-11 15:58:18 +000071 b = pci_read_byte(dev, 0x45);
72 pci_write_byte(dev, 0x45, b | 0x40);
Ollie Lhocbbf1252004-03-17 22:22:08 +000073
Uwe Hermann372eeb52007-12-04 21:49:06 +000074 /* The same thing on SiS 950 Super I/O side... */
75
76 /* First probe for Super I/O on config port 0x2e. */
Andriy Gapon65c1b862008-05-22 13:22:45 +000077 OUTB(0x87, 0x2e);
78 OUTB(0x01, 0x2e);
79 OUTB(0x55, 0x2e);
80 OUTB(0x55, 0x2e);
Ollie Lhocbbf1252004-03-17 22:22:08 +000081
Andriy Gapon65c1b862008-05-22 13:22:45 +000082 if (INB(0x2f) != 0x87) {
Uwe Hermann372eeb52007-12-04 21:49:06 +000083 /* If that failed, try config port 0x4e. */
Andriy Gapon65c1b862008-05-22 13:22:45 +000084 OUTB(0x87, 0x4e);
85 OUTB(0x01, 0x4e);
86 OUTB(0x55, 0x4e);
87 OUTB(0xaa, 0x4e);
88 if (INB(0x4f) != 0x87) {
Ollie Lhocbbf1252004-03-17 22:22:08 +000089 printf("Can not access SiS 950\n");
90 return -1;
91 }
Andriy Gapon65c1b862008-05-22 13:22:45 +000092 OUTB(0x24, 0x4e);
93 b = INB(0x4f) | 0xfc;
94 OUTB(0x24, 0x4e);
95 OUTB(b, 0x4f);
96 OUTB(0x02, 0x4e);
97 OUTB(0x02, 0x4f);
Ollie Lhocbbf1252004-03-17 22:22:08 +000098 }
99
Andriy Gapon65c1b862008-05-22 13:22:45 +0000100 OUTB(0x24, 0x2e);
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000101 printf_debug("2f is %#x\n", INB(0x2f));
Andriy Gapon65c1b862008-05-22 13:22:45 +0000102 b = INB(0x2f) | 0xfc;
103 OUTB(0x24, 0x2e);
104 OUTB(b, 0x2f);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000105
Andriy Gapon65c1b862008-05-22 13:22:45 +0000106 OUTB(0x02, 0x2e);
107 OUTB(0x02, 0x2f);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000108
109 return 0;
110}
111
Uwe Hermann987942d2006-11-07 11:16:21 +0000112/* Datasheet:
113 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
114 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
115 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
116 * - Order Number: 290562-001
117 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000118static int enable_flash_piix4(struct pci_dev *dev, const char *name)
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000119{
120 uint16_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000121 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000122
123 old = pci_read_word(dev, xbcs);
124
125 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
Uwe Hermanna7e05482007-05-09 10:17:44 +0000126 * FFF00000-FFF7FFFF are forwarded to ISA).
Uwe Hermannc556d322008-10-28 11:50:05 +0000127 * Note: This bit is reserved on PIIX/PIIX3/MPIIX.
Uwe Hermanna7e05482007-05-09 10:17:44 +0000128 * Set bit 7: Extended BIOS Enable (PCI master accesses to
129 * FFF80000-FFFDFFFF are forwarded to ISA).
130 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
131 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
132 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
133 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
134 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
135 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
136 */
Uwe Hermannc556d322008-10-28 11:50:05 +0000137 if (dev->device_id == 0x122e || dev->device_id == 0x7000
138 || dev->device_id == 0x1234)
139 new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
Uwe Hermann87203452008-10-26 18:40:42 +0000140 else
141 new = old | 0x02c4;
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000142
143 if (new == old)
144 return 0;
145
146 pci_write_word(dev, xbcs, new);
147
148 if (pci_read_word(dev, xbcs) != new) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000149 printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name);
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000150 return -1;
151 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000152
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000153 return 0;
154}
155
Uwe Hermann372eeb52007-12-04 21:49:06 +0000156/*
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000157 * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet"
158 * http://download.intel.com/design/chipsets/datashts/30701303.pdf
Uwe Hermann372eeb52007-12-04 21:49:06 +0000159 */
160static int enable_flash_ich(struct pci_dev *dev, const char *name,
161 int bios_cntl)
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000162{
Ollie Lho184a4042005-11-26 21:55:36 +0000163 uint8_t old, new;
Stefan Reinauereb366472006-09-06 15:48:48 +0000164
Uwe Hermann372eeb52007-12-04 21:49:06 +0000165 /*
166 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
Uwe Hermanna7e05482007-05-09 10:17:44 +0000167 * just treating it as 8 bit wide seems to work fine in practice.
Stefan Reinauereb366472006-09-06 15:48:48 +0000168 */
Stefan Reinauer86de2832006-03-31 11:26:55 +0000169 old = pci_read_byte(dev, bios_cntl);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000170
Uwe Hermann793bdcd2008-05-22 22:47:04 +0000171 printf_debug("\nBIOS Lock Enable: %sabled, ",
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000172 (old & (1 << 1)) ? "en" : "dis");
173 printf_debug("BIOS Write Enable: %sabled, ",
174 (old & (1 << 0)) ? "en" : "dis");
175 printf_debug("BIOS_CNTL is 0x%x\n", old);
176
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000177 new = old | 1;
178
179 if (new == old)
180 return 0;
181
Stefan Reinauer86de2832006-03-31 11:26:55 +0000182 pci_write_byte(dev, bios_cntl, new);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000183
Stefan Reinauer86de2832006-03-31 11:26:55 +0000184 if (pci_read_byte(dev, bios_cntl) != new) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000185 printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000186 return -1;
187 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000188
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000189 return 0;
190}
191
Uwe Hermann372eeb52007-12-04 21:49:06 +0000192static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000193{
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000194 /*
195 * Note: ICH5 has registers similar to FWH_SEL1, FWH_SEL2 and
196 * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and
197 * FB_DEC_EN2.
198 */
Stefan Reinauereb366472006-09-06 15:48:48 +0000199 return enable_flash_ich(dev, name, 0x4e);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000200}
201
Uwe Hermann372eeb52007-12-04 21:49:06 +0000202static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000203{
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000204 uint32_t fwh_conf;
205 int i;
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000206 char *idsel = NULL;
Carl-Daniel Hailfinger4c7ea382009-08-10 23:30:45 +0000207
208 /* Ignore all legacy ranges below 1 MB. */
209 /* FWH_SEL1 */
210 fwh_conf = pci_read_long(dev, 0xd0);
211 for (i = 7; i >= 0; i--)
212 printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
213 (0x1ff8 + i) * 0x80000,
214 (0x1ff0 + i) * 0x80000,
215 (fwh_conf >> (i * 4)) & 0xf);
216 /* FWH_SEL2 */
217 fwh_conf = pci_read_word(dev, 0xd4);
218 for (i = 3; i >= 0; i--)
219 printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
220 (0xff4 + i) * 0x100000,
221 (0xff0 + i) * 0x100000,
222 (fwh_conf >> (i * 4)) & 0xf);
223 /* FWH_DEC_EN1 */
224 fwh_conf = pci_read_word(dev, 0xd8);
225 for (i = 7; i >= 0; i--)
226 printf_debug("\n0x%08x/0x%08x FWH decode %sabled",
227 (0x1ff8 + i) * 0x80000,
228 (0x1ff0 + i) * 0x80000,
229 (fwh_conf >> (i + 0x8)) & 0x1 ? "en" : "dis");
230 for (i = 3; i >= 0; i--)
231 printf_debug("\n0x%08x/0x%08x FWH decode %sabled",
232 (0xff4 + i) * 0x100000,
233 (0xff0 + i) * 0x100000,
234 (fwh_conf >> i) & 0x1 ? "en" : "dis");
235
Carl-Daniel Hailfinger44498682009-08-13 23:23:37 +0000236 if (programmer_param)
237 idsel = strstr(programmer_param, "fwh_idsel=");
238
239 if (idsel) {
240 idsel += strlen("fwh_idsel=");
241 fwh_conf = (uint32_t)strtoul(idsel, NULL, 0);
242
243 /* FIXME: Need to undo this on shutdown. */
244 printf("\nSetting IDSEL=0x%x for top 16 MB", fwh_conf);
245 pci_write_long(dev, 0xd0, fwh_conf);
246 pci_write_word(dev, 0xd4, fwh_conf);
247 }
248
Stefan Reinauereb366472006-09-06 15:48:48 +0000249 return enable_flash_ich(dev, name, 0xdc);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000250}
251
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000252#define ICH_STRAP_RSVD 0x00
253#define ICH_STRAP_SPI 0x01
254#define ICH_STRAP_PCI 0x02
255#define ICH_STRAP_LPC 0x03
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000256
Uwe Hermann394131e2008-10-18 21:14:13 +0000257static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
258{
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000259 uint32_t mmio_base;
260
261 mmio_base = (pci_read_long(dev, 0xbc)) << 8;
262 printf_debug("MMIO base at = 0x%x\n", mmio_base);
Stefan Reinauer0593f212009-01-26 01:10:48 +0000263 spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70);
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000264
Uwe Hermann394131e2008-10-18 21:14:13 +0000265 printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000266 mmio_readw(spibar + 0x6c));
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000267
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000268 /* Not sure if it speaks all these bus protocols. */
269 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000270 spi_controller = SPI_CONTROLLER_VIA;
Rudolf Marek0c2029f2009-02-01 18:40:50 +0000271 ich_init_opcodes();
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000272
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000273 return 0;
274}
275
Uwe Hermann394131e2008-10-18 21:14:13 +0000276static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
277 int ich_generation)
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000278{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000279 int ret, i;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000280 uint8_t old, new, bbs, buc;
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000281 uint16_t spibar_offset, tmp2;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000282 uint32_t tmp, gcs;
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000283 void *rcrb;
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000284 //TODO: These names are incorrect for EP80579. For that, the solution would look like the commented line
285 //static const char *straps_names[] = {"SPI", "reserved", "reserved", "LPC" };
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000286 static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" };
Uwe Hermann394131e2008-10-18 21:14:13 +0000287
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000288 /* Enable Flash Writes */
289 ret = enable_flash_ich_dc(dev, name);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000290
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000291 /* Get physical address of Root Complex Register Block */
292 tmp = pci_read_long(dev, 0xf0) & 0xffffc000;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000293 printf_debug("\nRoot Complex Register Block address = 0x%x\n", tmp);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000294
295 /* Map RCBA to virtual memory */
Stefan Reinauer0593f212009-01-26 01:10:48 +0000296 rcrb = physmap("ICH RCRB", tmp, 0x4000);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000297
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000298 gcs = mmio_readl(rcrb + 0x3410);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000299 printf_debug("GCS = 0x%x: ", gcs);
300 printf_debug("BIOS Interface Lock-Down: %sabled, ",
301 (gcs & 0x1) ? "en" : "dis");
302 bbs = (gcs >> 10) & 0x3;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000303 printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000304
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000305 buc = mmio_readb(rcrb + 0x3414);
Uwe Hermann394131e2008-10-18 21:14:13 +0000306 printf_debug("Top Swap : %s\n",
307 (buc & 1) ? "enabled (A16 inverted)" : "not enabled");
Stefan Reinauera9424d52008-06-27 16:28:34 +0000308
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000309 /* It seems the ICH7 does not support SPI and LPC chips at the same
310 * time. At least not with our current code. So we prevent searching
311 * on ICH7 when the southbridge is strapped to LPC
312 */
313
314 if (ich_generation == 7 && bbs == ICH_STRAP_LPC) {
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000315 /* Not sure if it speaks LPC as well. */
316 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000317 /* No further SPI initialization required */
318 return ret;
319 }
320
321 switch (ich_generation) {
322 case 7:
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000323 buses_supported = CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000324 spi_controller = SPI_CONTROLLER_ICH7;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000325 spibar_offset = 0x3020;
326 break;
327 case 8:
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000328 /* Not sure if it speaks LPC as well. */
329 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000330 spi_controller = SPI_CONTROLLER_ICH9;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000331 spibar_offset = 0x3020;
332 break;
333 case 9:
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000334 case 10:
Uwe Hermann394131e2008-10-18 21:14:13 +0000335 default: /* Future version might behave the same */
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000336 /* Not sure if it speaks LPC as well. */
337 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000338 spi_controller = SPI_CONTROLLER_ICH9;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000339 spibar_offset = 0x3800;
340 break;
341 }
342
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000343 /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000344 printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000345
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000346 /* Assign Virtual Address */
Uwe Hermann394131e2008-10-18 21:14:13 +0000347 spibar = rcrb + spibar_offset;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000348
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000349 switch (spi_controller) {
350 case SPI_CONTROLLER_ICH7:
Uwe Hermann394131e2008-10-18 21:14:13 +0000351 printf_debug("0x00: 0x%04x (SPIS)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000352 mmio_readw(spibar + 0));
Uwe Hermann394131e2008-10-18 21:14:13 +0000353 printf_debug("0x02: 0x%04x (SPIC)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000354 mmio_readw(spibar + 2));
Uwe Hermann394131e2008-10-18 21:14:13 +0000355 printf_debug("0x04: 0x%08x (SPIA)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000356 mmio_readl(spibar + 4));
Uwe Hermann394131e2008-10-18 21:14:13 +0000357 for (i = 0; i < 8; i++) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000358 int offs;
359 offs = 8 + (i * 8);
Uwe Hermann394131e2008-10-18 21:14:13 +0000360 printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs,
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000361 mmio_readl(spibar + offs), i);
Uwe Hermann394131e2008-10-18 21:14:13 +0000362 printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000363 mmio_readl(spibar + offs + 4), i);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000364 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000365 printf_debug("0x50: 0x%08x (BBAR)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000366 mmio_readl(spibar + 0x50));
Uwe Hermann394131e2008-10-18 21:14:13 +0000367 printf_debug("0x54: 0x%04x (PREOP)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000368 mmio_readw(spibar + 0x54));
Uwe Hermann394131e2008-10-18 21:14:13 +0000369 printf_debug("0x56: 0x%04x (OPTYPE)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000370 mmio_readw(spibar + 0x56));
Uwe Hermann394131e2008-10-18 21:14:13 +0000371 printf_debug("0x58: 0x%08x (OPMENU)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000372 mmio_readl(spibar + 0x58));
Uwe Hermann394131e2008-10-18 21:14:13 +0000373 printf_debug("0x5c: 0x%08x (OPMENU+4)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000374 mmio_readl(spibar + 0x5c));
Uwe Hermann394131e2008-10-18 21:14:13 +0000375 for (i = 0; i < 4; i++) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000376 int offs;
377 offs = 0x60 + (i * 4);
Uwe Hermann394131e2008-10-18 21:14:13 +0000378 printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs,
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000379 mmio_readl(spibar + offs), i);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000380 }
381 printf_debug("\n");
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000382 if (mmio_readw(spibar) & (1 << 15)) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000383 printf("WARNING: SPI Configuration Lockdown activated.\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000384 ichspi_lock = 1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000385 }
FENG yu ningf041e9b2008-12-15 02:32:11 +0000386 ich_init_opcodes();
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000387 break;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000388 case SPI_CONTROLLER_ICH9:
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000389 tmp2 = mmio_readw(spibar + 4);
FENG yu ning37179b82009-01-18 06:39:32 +0000390 printf_debug("0x04: 0x%04x (HSFS)\n", tmp2);
391 printf_debug("FLOCKDN %i, ", (tmp2 >> 15 & 1));
392 printf_debug("FDV %i, ", (tmp2 >> 14) & 1);
393 printf_debug("FDOPSS %i, ", (tmp2 >> 13) & 1);
394 printf_debug("SCIP %i, ", (tmp2 >> 5) & 1);
395 printf_debug("BERASE %i, ", (tmp2 >> 3) & 3);
396 printf_debug("AEL %i, ", (tmp2 >> 2) & 1);
397 printf_debug("FCERR %i, ", (tmp2 >> 1) & 1);
398 printf_debug("FDONE %i\n", (tmp2 >> 0) & 1);
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000399
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000400 tmp = mmio_readl(spibar + 0x50);
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000401 printf_debug("0x50: 0x%08x (FRAP)\n", tmp);
402 printf_debug("BMWAG %i, ", (tmp >> 24) & 0xff);
403 printf_debug("BMRAG %i, ", (tmp >> 16) & 0xff);
404 printf_debug("BRWA %i, ", (tmp >> 8) & 0xff);
405 printf_debug("BRRA %i\n", (tmp >> 0) & 0xff);
406
407 printf_debug("0x54: 0x%08x (FREG0)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000408 mmio_readl(spibar + 0x54));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000409 printf_debug("0x58: 0x%08x (FREG1)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000410 mmio_readl(spibar + 0x58));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000411 printf_debug("0x5C: 0x%08x (FREG2)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000412 mmio_readl(spibar + 0x5C));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000413 printf_debug("0x60: 0x%08x (FREG3)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000414 mmio_readl(spibar + 0x60));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000415 printf_debug("0x64: 0x%08x (FREG4)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000416 mmio_readl(spibar + 0x64));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000417 printf_debug("0x74: 0x%08x (PR0)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000418 mmio_readl(spibar + 0x74));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000419 printf_debug("0x78: 0x%08x (PR1)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000420 mmio_readl(spibar + 0x78));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000421 printf_debug("0x7C: 0x%08x (PR2)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000422 mmio_readl(spibar + 0x7C));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000423 printf_debug("0x80: 0x%08x (PR3)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000424 mmio_readl(spibar + 0x80));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000425 printf_debug("0x84: 0x%08x (PR4)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000426 mmio_readl(spibar + 0x84));
FENG yu ning37179b82009-01-18 06:39:32 +0000427 printf_debug("0x90: 0x%08x (SSFS, SSFC)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000428 mmio_readl(spibar + 0x90));
FENG yu ning37179b82009-01-18 06:39:32 +0000429 printf_debug("0x94: 0x%04x (PREOP)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000430 mmio_readw(spibar + 0x94));
FENG yu ning37179b82009-01-18 06:39:32 +0000431 printf_debug("0x96: 0x%04x (OPTYPE)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000432 mmio_readw(spibar + 0x96));
FENG yu ning37179b82009-01-18 06:39:32 +0000433 printf_debug("0x98: 0x%08x (OPMENU)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000434 mmio_readl(spibar + 0x98));
FENG yu ning37179b82009-01-18 06:39:32 +0000435 printf_debug("0x9C: 0x%08x (OPMENU+4)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000436 mmio_readl(spibar + 0x9C));
FENG yu ning37179b82009-01-18 06:39:32 +0000437 printf_debug("0xA0: 0x%08x (BBAR)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000438 mmio_readl(spibar + 0xA0));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000439 printf_debug("0xB0: 0x%08x (FDOC)\n",
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000440 mmio_readl(spibar + 0xB0));
FENG yu ning37179b82009-01-18 06:39:32 +0000441 if (tmp2 & (1 << 15)) {
442 printf("WARNING: SPI Configuration Lockdown activated.\n");
443 ichspi_lock = 1;
444 }
Peter Stugee8a3e4c2008-12-22 14:12:08 +0000445 ich_init_opcodes();
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000446 break;
447 default:
448 /* Nothing */
449 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000450 }
451
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000452 old = pci_read_byte(dev, 0xdc);
453 printf_debug("SPI Read Configuration: ");
454 new = (old >> 2) & 0x3;
455 switch (new) {
456 case 0:
457 case 1:
458 case 2:
459 printf_debug("prefetching %sabled, caching %sabled, ",
Uwe Hermann394131e2008-10-18 21:14:13 +0000460 (new & 0x2) ? "en" : "dis",
461 (new & 0x1) ? "dis" : "en");
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000462 break;
463 default:
464 printf_debug("invalid prefetching/caching settings, ");
465 break;
466 }
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000467
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000468 return ret;
469}
Stefan Reinauera9424d52008-06-27 16:28:34 +0000470
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000471static int enable_flash_ich7(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000472{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000473 return enable_flash_ich_dc_spi(dev, name, 7);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000474}
475
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000476static int enable_flash_ich8(struct pci_dev *dev, const char *name)
477{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000478 return enable_flash_ich_dc_spi(dev, name, 8);
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000479}
480
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000481static int enable_flash_ich9(struct pci_dev *dev, const char *name)
482{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000483 return enable_flash_ich_dc_spi(dev, name, 9);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000484}
485
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000486static int enable_flash_ich10(struct pci_dev *dev, const char *name)
487{
488 return enable_flash_ich_dc_spi(dev, name, 10);
489}
490
Uwe Hermann372eeb52007-12-04 21:49:06 +0000491static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000492{
Ollie Lho184a4042005-11-26 21:55:36 +0000493 uint8_t val;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000494
Uwe Hermann394131e2008-10-18 21:14:13 +0000495 /* enable ROM decode range (1MB) FFC00000 - FFFFFFFF */
Bari Ari9477c4e2008-04-29 13:46:38 +0000496 pci_write_byte(dev, 0x41, 0x7f);
497
Uwe Hermannffec5f32007-08-23 16:08:21 +0000498 /* ROM write enable */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000499 val = pci_read_byte(dev, 0x40);
500 val |= 0x10;
501 pci_write_byte(dev, 0x40, val);
502
503 if (pci_read_byte(dev, 0x40) != val) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000504 printf("\nWARNING: Failed to enable flash write on \"%s\"\n",
Uwe Hermanna7e05482007-05-09 10:17:44 +0000505 name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000506 return -1;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000507 }
Luc Verhaegen6382b442007-03-02 22:16:38 +0000508
Uwe Hermanna7e05482007-05-09 10:17:44 +0000509 return 0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000510}
511
Uwe Hermann372eeb52007-12-04 21:49:06 +0000512static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000513{
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000514 uint8_t reg8;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000515
Uwe Hermann394131e2008-10-18 21:14:13 +0000516#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
517#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000518
Uwe Hermann394131e2008-10-18 21:14:13 +0000519#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
520#define ROM_WRITE_ENABLE (1 << 1)
521#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
522#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000523
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000524 /* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
525 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
526 * Make the configured ROM areas writable.
527 */
528 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
529 reg8 |= LOWER_ROM_ADDRESS_RANGE;
530 reg8 |= UPPER_ROM_ADDRESS_RANGE;
531 reg8 |= ROM_WRITE_ENABLE;
532 pci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000533
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000534 /* Set positive decode on ROM. */
535 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
536 reg8 |= BIOS_ROM_POSITIVE_DECODE;
537 pci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000538
Ollie Lhocbbf1252004-03-17 22:22:08 +0000539 return 0;
540}
541
Mart Raudseppe1344da2008-02-08 10:10:57 +0000542/**
543 * Geode systems write protect the BIOS via RCONFs (cache settings similar
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000544 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22.
Mart Raudseppe1344da2008-02-08 10:10:57 +0000545 *
546 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
547 * To enable write to NOR Boot flash for the benefit of systems that have such
548 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
Mart Raudseppe1344da2008-02-08 10:10:57 +0000549 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000550static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
Lane Brooksd54958a2007-11-13 16:45:22 +0000551{
Uwe Hermann394131e2008-10-18 21:14:13 +0000552#define MSR_RCONF_DEFAULT 0x1808
553#define MSR_NORF_CTL 0x51400018
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000554
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000555 msr_t msr;
Lane Brooksd54958a2007-11-13 16:45:22 +0000556
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000557 /* Geode only has a single core */
558 if (setup_cpu_msr(0))
Lane Brooksd54958a2007-11-13 16:45:22 +0000559 return -1;
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000560
561 msr = rdmsr(MSR_RCONF_DEFAULT);
562 if ((msr.hi >> 24) != 0x22) {
563 msr.hi &= 0xfbffffff;
564 wrmsr(MSR_RCONF_DEFAULT, msr);
Lane Brooksd54958a2007-11-13 16:45:22 +0000565 }
Mart Raudseppe1344da2008-02-08 10:10:57 +0000566
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000567 msr = rdmsr(MSR_NORF_CTL);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000568 /* Raise WE_CS3 bit. */
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000569 msr.lo |= 0x08;
570 wrmsr(MSR_NORF_CTL, msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000571
Stefan Reinauer8fa64812009-08-12 09:27:45 +0000572 cleanup_cpu_msr();
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000573
Uwe Hermann394131e2008-10-18 21:14:13 +0000574#undef MSR_RCONF_DEFAULT
575#undef MSR_NORF_CTL
Lane Brooksd54958a2007-11-13 16:45:22 +0000576 return 0;
577}
578
Uwe Hermann372eeb52007-12-04 21:49:06 +0000579static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000580{
Ollie Lho184a4042005-11-26 21:55:36 +0000581 uint8_t new;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000582
Ollie Lhocbbf1252004-03-17 22:22:08 +0000583 pci_write_byte(dev, 0x52, 0xee);
584
585 new = pci_read_byte(dev, 0x52);
586
587 if (new != 0xee) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000588 printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000589 return -1;
590 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000591
Ollie Lhocbbf1252004-03-17 22:22:08 +0000592 return 0;
593}
594
Uwe Hermann372eeb52007-12-04 21:49:06 +0000595static int enable_flash_sis5595(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000596{
Ollie Lho184a4042005-11-26 21:55:36 +0000597 uint8_t new, newer;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000598
Ollie Lhocbbf1252004-03-17 22:22:08 +0000599 new = pci_read_byte(dev, 0x45);
600
Uwe Hermann372eeb52007-12-04 21:49:06 +0000601 new &= (~0x20); /* Clear bit 5. */
602 new |= 0x4; /* Set bit 2. */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000603
604 pci_write_byte(dev, 0x45, new);
605
606 newer = pci_read_byte(dev, 0x45);
607 if (newer != new) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000608 printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
609 printf_debug("Stuck at 0x%x\n", newer);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000610 return -1;
611 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000612
Urja Rannikkoa88daa72008-10-18 13:54:30 +0000613 /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
Uwe Hermann394131e2008-10-18 21:14:13 +0000614 new = pci_read_byte(dev, 0x40);
Urja Rannikkoa88daa72008-10-18 13:54:30 +0000615 new &= 0xFB;
616 new |= 0x3;
Uwe Hermann394131e2008-10-18 21:14:13 +0000617 pci_write_byte(dev, 0x40, new);
618 newer = pci_read_byte(dev, 0x40);
Urja Rannikkoa88daa72008-10-18 13:54:30 +0000619 if (newer != new) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000620 printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
621 printf_debug("Stuck at 0x%x\n", newer);
Urja Rannikkoa88daa72008-10-18 13:54:30 +0000622 return -1;
623 }
Ollie Lhocbbf1252004-03-17 22:22:08 +0000624 return 0;
625}
626
Uwe Hermann190f8492008-10-25 18:03:50 +0000627/* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000628static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000629{
Ollie Lho184a4042005-11-26 21:55:36 +0000630 uint8_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000631
Uwe Hermann372eeb52007-12-04 21:49:06 +0000632 /* Enable decoding at 0xffb00000 to 0xffffffff. */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000633 old = pci_read_byte(dev, 0x43);
Ollie Lhod11f3612004-12-07 17:19:04 +0000634 new = old | 0xC0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000635 if (new != old) {
636 pci_write_byte(dev, 0x43, new);
637 if (pci_read_byte(dev, 0x43) != new) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000638 printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000639 }
640 }
641
Uwe Hermann190f8492008-10-25 18:03:50 +0000642 /* Enable 'ROM write' bit. */
Ollie Lho761bf1b2004-03-20 16:46:10 +0000643 old = pci_read_byte(dev, 0x40);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000644 new = old | 0x01;
645 if (new == old)
646 return 0;
647 pci_write_byte(dev, 0x40, new);
648
649 if (pci_read_byte(dev, 0x40) != new) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000650 printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000651 return -1;
652 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000653
Ollie Lhocbbf1252004-03-17 22:22:08 +0000654 return 0;
655}
656
Marc Jones3af487d2008-10-15 17:50:29 +0000657static int enable_flash_sb600(struct pci_dev *dev, const char *name)
658{
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000659 uint32_t tmp, prot;
Marc Jones3af487d2008-10-15 17:50:29 +0000660 uint8_t reg;
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000661 struct pci_dev *smbus_dev;
662 int has_spi = 1;
Marc Jones3af487d2008-10-15 17:50:29 +0000663
Jason Wanga3f04be2008-11-28 21:36:51 +0000664 /* Clear ROM protect 0-3. */
665 for (reg = 0x50; reg < 0x60; reg += 4) {
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000666 prot = pci_read_long(dev, reg);
667 /* No protection flags for this region?*/
668 if ((prot & 0x3) == 0)
669 continue;
670 printf_debug("SB600 %s%sprotected from %u to %u\n",
671 (prot & 0x1) ? "write " : "",
672 (prot & 0x2) ? "read " : "",
673 (prot & 0xfffffc00),
674 (prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
675 prot &= 0xfffffffc;
676 pci_write_byte(dev, reg, prot);
677 prot = pci_read_long(dev, reg);
Carl-Daniel Hailfinger9bb88ac2009-05-06 13:51:44 +0000678 if (prot & 0x3)
Peter Stuge19997ae2009-05-06 15:05:39 +0000679 printf("SB600 %s%sunprotect failed from %u to %u\n",
Carl-Daniel Hailfinger9bb88ac2009-05-06 13:51:44 +0000680 (prot & 0x1) ? "write " : "",
681 (prot & 0x2) ? "read " : "",
682 (prot & 0xfffffc00),
683 (prot & 0xfffffc00) + ((prot & 0x3ff) << 8));
Jason Wanga3f04be2008-11-28 21:36:51 +0000684 }
685
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000686 /* Read SPI_BaseAddr */
687 tmp = pci_read_long(dev, 0xa0);
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000688 tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000689 printf_debug("SPI base address is at 0x%x\n", tmp);
690
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000691 /* If the BAR has address 0, it is unlikely SPI is used. */
692 if (!tmp)
693 has_spi = 0;
694
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000695 if (has_spi) {
696 /* Physical memory has to be mapped at page (4k) boundaries. */
697 sb600_spibar = physmap("SB600 SPI registers", tmp & 0xfffff000,
698 0x1000);
699 /* The low bits of the SPI base address are used as offset into
700 * the mapped page.
701 */
702 sb600_spibar += tmp & 0xfff;
703
704 tmp = pci_read_long(dev, 0xa0);
705 printf_debug("AltSpiCSEnable=%i, SpiRomEnable=%i, "
706 "AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1,
707 (tmp & 0x4) >> 2);
708 tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2;
709 printf_debug("PrefetchEnSPIFromIMC=%i, ", tmp);
710
711 tmp = pci_read_byte(dev, 0xbb);
712 printf_debug("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n",
713 tmp & 0x1, (tmp & 0x20) >> 5);
714 tmp = mmio_readl(sb600_spibar);
715 printf_debug("SpiArbEnable=%i, SpiAccessMacRomEn=%i, "
716 "SpiHostAccessRomEn=%i, ArbWaitCount=%i, "
717 "SpiBridgeDisable=%i, DropOneClkOnRd=%i\n",
718 (tmp >> 19) & 0x1, (tmp >> 22) & 0x1,
719 (tmp >> 23) & 0x1, (tmp >> 24) & 0x7,
720 (tmp >> 27) & 0x1, (tmp >> 28) & 0x1);
721 }
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000722
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000723 /* Look for the SMBus device. */
724 smbus_dev = pci_dev_find(0x1002, 0x4385);
725
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000726 if (has_spi && !smbus_dev) {
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000727 fprintf(stderr, "ERROR: SMBus device not found. Not enabling SPI.\n");
728 has_spi = 0;
Carl-Daniel Hailfingerf8555e22009-07-23 01:36:08 +0000729 }
730 if (has_spi) {
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000731 /* Note about the bit tests below: If a bit is zero, the GPIO is SPI. */
732 /* GPIO11/SPI_DO and GPIO12/SPI_DI status */
733 reg = pci_read_byte(smbus_dev, 0xAB);
734 reg &= 0xC0;
735 printf_debug("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO");
736 printf_debug("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI");
737 if (reg != 0x00)
738 has_spi = 0;
739 /* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */
740 reg = pci_read_byte(smbus_dev, 0x83);
741 reg &= 0xC0;
742 printf_debug("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD");
743 printf_debug("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS");
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000744 /* SPI_HOLD is not used on all boards, filter it out. */
745 if ((reg & 0x80) != 0x00)
Carl-Daniel Hailfingerdbfa0292009-05-10 14:11:07 +0000746 has_spi = 0;
747 /* GPIO47/SPI_CLK status */
748 reg = pci_read_byte(smbus_dev, 0xA7);
749 reg &= 0x40;
750 printf_debug("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK");
751 if (reg != 0x00)
752 has_spi = 0;
753 }
754
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000755 buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH;
756 if (has_spi) {
757 buses_supported |= CHIP_BUSTYPE_SPI;
Carl-Daniel Hailfinger1dfe0ff2009-05-31 17:57:34 +0000758 spi_controller = SPI_CONTROLLER_SB600;
Carl-Daniel Hailfingerb22918c2009-06-01 02:08:58 +0000759 }
Jason Wanga3f04be2008-11-28 21:36:51 +0000760
Carl-Daniel Hailfinger98622512009-05-15 23:36:23 +0000761 /* Read ROM strap override register. */
762 OUTB(0x8f, 0xcd6);
763 reg = INB(0xcd7);
764 reg &= 0x0e;
765 printf_debug("ROM strap override is %sactive", (reg & 0x02) ? "" : "not ");
766 if (reg & 0x02) {
767 switch ((reg & 0x0c) >> 2) {
768 case 0x00:
769 printf_debug(": LPC");
770 break;
771 case 0x01:
772 printf_debug(": PCI");
773 break;
774 case 0x02:
775 printf_debug(": FWH");
776 break;
777 case 0x03:
778 printf_debug(": SPI");
779 break;
780 }
781 }
782 printf_debug("\n");
783
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000784 /* Force enable SPI ROM in SB600 PM register.
785 * If we enable SPI ROM here, we have to disable it after we leave.
Zheng Bao284a6002009-05-04 22:33:50 +0000786 * But how can we know which ROM we are going to handle? So we have
787 * to trade off. We only access LPC ROM if we boot via LPC ROM. And
Carl-Daniel Hailfinger41d6bd92009-05-05 22:50:07 +0000788 * only SPI ROM if we boot via SPI ROM. If you want to access SPI on
789 * boards with LPC straps, you have to use the code below.
Zheng Bao284a6002009-05-04 22:33:50 +0000790 */
791 /*
Jason Wanga3f04be2008-11-28 21:36:51 +0000792 OUTB(0x8f, 0xcd6);
793 OUTB(0x0e, 0xcd7);
Zheng Bao284a6002009-05-04 22:33:50 +0000794 */
Marc Jones3af487d2008-10-15 17:50:29 +0000795
796 return 0;
797}
798
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000799static int enable_flash_nvidia_nforce2(struct pci_dev *dev, const char *name)
800{
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000801 uint8_t tmp;
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000802
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000803 pci_write_byte(dev, 0x92, 0);
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000804
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000805 tmp = pci_read_byte(dev, 0x6d);
806 tmp |= 0x01;
807 pci_write_byte(dev, 0x6d, tmp);
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000808
Uwe Hermanne9d04d42009-06-02 19:54:22 +0000809 return 0;
Luc Verhaegen90e8e612009-05-26 09:48:28 +0000810}
811
Uwe Hermann372eeb52007-12-04 21:49:06 +0000812static int enable_flash_ck804(struct pci_dev *dev, const char *name)
Yinghai Lu952dfce2005-07-06 17:13:46 +0000813{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000814 uint8_t old, new;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000815
Uwe Hermanna7e05482007-05-09 10:17:44 +0000816 old = pci_read_byte(dev, 0x88);
817 new = old | 0xc0;
818 if (new != old) {
819 pci_write_byte(dev, 0x88, new);
820 if (pci_read_byte(dev, 0x88) != new) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000821 printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000822 }
823 }
Yinghai Lu952dfce2005-07-06 17:13:46 +0000824
Uwe Hermanna7e05482007-05-09 10:17:44 +0000825 old = pci_read_byte(dev, 0x6d);
826 new = old | 0x01;
827 if (new == old)
828 return 0;
829 pci_write_byte(dev, 0x6d, new);
830
831 if (pci_read_byte(dev, 0x6d) != new) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000832 printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000833 return -1;
834 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000835
Uwe Hermanna7e05482007-05-09 10:17:44 +0000836 return 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000837}
838
Uwe Hermann372eeb52007-12-04 21:49:06 +0000839/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
840static int enable_flash_sb400(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000841{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000842 uint8_t tmp;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000843 struct pci_dev *smbusdev;
844
Uwe Hermann372eeb52007-12-04 21:49:06 +0000845 /* Look for the SMBus device. */
Carl-Daniel Hailfingerf6e3efb2009-05-06 00:35:31 +0000846 smbusdev = pci_dev_find(0x1002, 0x4372);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000847
Uwe Hermanna7e05482007-05-09 10:17:44 +0000848 if (!smbusdev) {
Uwe Hermann372eeb52007-12-04 21:49:06 +0000849 fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n");
Stefan Reinauer86de2832006-03-31 11:26:55 +0000850 exit(1);
851 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000852
Uwe Hermann372eeb52007-12-04 21:49:06 +0000853 /* Enable some SMBus stuff. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000854 tmp = pci_read_byte(smbusdev, 0x79);
855 tmp |= 0x01;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000856 pci_write_byte(smbusdev, 0x79, tmp);
857
Uwe Hermann372eeb52007-12-04 21:49:06 +0000858 /* Change southbridge. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000859 tmp = pci_read_byte(dev, 0x48);
860 tmp |= 0x21;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000861 pci_write_byte(dev, 0x48, tmp);
862
Uwe Hermann372eeb52007-12-04 21:49:06 +0000863 /* Now become a bit silly. */
Andriy Gapon65c1b862008-05-22 13:22:45 +0000864 tmp = INB(0xc6f);
865 OUTB(tmp, 0xeb);
866 OUTB(tmp, 0xeb);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000867 tmp |= 0x40;
Andriy Gapon65c1b862008-05-22 13:22:45 +0000868 OUTB(tmp, 0xc6f);
869 OUTB(tmp, 0xeb);
870 OUTB(tmp, 0xeb);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000871
872 return 0;
873}
874
Uwe Hermann372eeb52007-12-04 21:49:06 +0000875static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
Yinghai Luca782972007-01-22 20:21:17 +0000876{
Uwe Hermann372eeb52007-12-04 21:49:06 +0000877 uint8_t old, new, byte;
878 uint16_t word;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000879
Uwe Hermann372eeb52007-12-04 21:49:06 +0000880 /* Set the 0-16 MB enable bits. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000881 byte = pci_read_byte(dev, 0x88);
882 byte |= 0xff; /* 256K */
883 pci_write_byte(dev, 0x88, byte);
884 byte = pci_read_byte(dev, 0x8c);
885 byte |= 0xff; /* 1M */
886 pci_write_byte(dev, 0x8c, byte);
887 word = pci_read_word(dev, 0x90);
Carl-Daniel Hailfingerdca0ab12007-10-17 22:30:07 +0000888 word |= 0x7fff; /* 16M */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000889 pci_write_word(dev, 0x90, word);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000890
Uwe Hermanna7e05482007-05-09 10:17:44 +0000891 old = pci_read_byte(dev, 0x6d);
892 new = old | 0x01;
893 if (new == old)
894 return 0;
895 pci_write_byte(dev, 0x6d, new);
Yinghai Luca782972007-01-22 20:21:17 +0000896
Uwe Hermanna7e05482007-05-09 10:17:44 +0000897 if (pci_read_byte(dev, 0x6d) != new) {
Stefan Reinauer630c79d2009-08-11 12:15:39 +0000898 printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000899 return -1;
900 }
Yinghai Luca782972007-01-22 20:21:17 +0000901
902 return 0;
Yinghai Luca782972007-01-22 20:21:17 +0000903}
904
Uwe Hermann372eeb52007-12-04 21:49:06 +0000905static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000906{
Uwe Hermanne823ee02007-06-05 15:02:18 +0000907 uint8_t byte;
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000908
Uwe Hermanne823ee02007-06-05 15:02:18 +0000909 /* Set the 4MB enable bit. */
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000910 byte = pci_read_byte(dev, 0x41);
911 byte |= 0x0e;
912 pci_write_byte(dev, 0x41, byte);
913
914 byte = pci_read_byte(dev, 0x43);
Uwe Hermannffec5f32007-08-23 16:08:21 +0000915 byte |= (1 << 4);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000916 pci_write_byte(dev, 0x43, byte);
917
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000918 return 0;
919}
920
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000921/**
922 * Usually on the x86 architectures (and on other PC-like platforms like some
923 * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
924 * Elan SC520 only a small piece of the system flash is mapped there, but the
925 * complete flash is mapped somewhere below 1G. The position can be determined
926 * by the BOOTCS PAR register.
927 */
928static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
929{
930 int i, bootcs_found = 0;
931 uint32_t parx = 0;
932 void *mmcr;
933
934 /* 1. Map MMCR */
Stefan Reinauer0593f212009-01-26 01:10:48 +0000935 mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000936
937 /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for
938 * BOOTCS region (PARx[31:29] = 100b)e
939 */
940 for (i = 0x88; i <= 0xc4; i += 4) {
Carl-Daniel Hailfinger78185dc2009-05-17 15:49:24 +0000941 parx = mmio_readl(mmcr + i);
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000942 if ((parx >> 29) == 4) {
943 bootcs_found = 1;
944 break; /* BOOTCS found */
945 }
946 }
947
948 /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0]
949 * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0]
950 */
951 if (bootcs_found) {
952 if (parx & (1 << 25)) {
953 parx &= (1 << 14) - 1; /* Mask [13:0] */
954 flashbase = parx << 16;
955 } else {
956 parx &= (1 << 18) - 1; /* Mask [17:0] */
957 flashbase = parx << 12;
958 }
959 } else {
960 printf("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n");
961 }
962
963 /* 4. Clean up */
Carl-Daniel Hailfingerbe726812009-08-09 12:44:08 +0000964 physunmap(mmcr, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000965 return 0;
966}
967
Uwe Hermann4179d292009-05-08 17:50:51 +0000968/* Please keep this list alphabetically sorted by vendor/device. */
Uwe Hermann05fab752009-05-16 23:42:17 +0000969const struct penable chipset_enables[] = {
Uwe Hermann4179d292009-05-08 17:50:51 +0000970 {0x10B9, 0x1533, OK, "ALi", "M1533", enable_flash_ali_m1533},
971 {0x1022, 0x7440, OK, "AMD", "AMD-768", enable_flash_amd8111},
972 {0x1022, 0x7468, OK, "AMD", "AMD8111", enable_flash_amd8111},
973 {0x1078, 0x0100, OK, "AMD", "CS5530(A)", enable_flash_cs5530},
974 {0x1022, 0x2080, OK, "AMD", "CS5536", enable_flash_cs5536},
Nils Jacobse715c7b2009-09-23 02:09:23 +0000975 {0x1022, 0x2090, OK, "AMD", "CS5536", enable_flash_cs5536},
Uwe Hermann4179d292009-05-08 17:50:51 +0000976 {0x1022, 0x3000, OK, "AMD", "Elan SC520", get_flashbase_sc520},
977 {0x1002, 0x438D, OK, "AMD", "SB600", enable_flash_sb600},
Carl-Daniel Hailfinger174962d2009-09-01 22:13:42 +0000978 {0x1002, 0x439d, OK, "AMD", "SB700/SB710/SB750", enable_flash_sb600},
Uwe Hermann4179d292009-05-08 17:50:51 +0000979 {0x100b, 0x0510, NT, "AMD", "SC1100", enable_flash_sc1100},
980 {0x1002, 0x4377, OK, "ATI", "SB400", enable_flash_sb400},
981 {0x1166, 0x0205, OK, "Broadcom", "HT-1000", enable_flash_ht1000},
Uwe Hermannb0039912009-05-07 13:24:49 +0000982 {0x8086, 0x7198, OK, "Intel", "440MX", enable_flash_piix4},
Uwe Hermann4179d292009-05-08 17:50:51 +0000983 {0x8086, 0x25a1, OK, "Intel", "6300ESB", enable_flash_ich_4e},
984 {0x8086, 0x2670, OK, "Intel", "631xESB/632xESB/3100", enable_flash_ich_dc},
985 {0x8086, 0x5031, OK, "Intel", "EP80579", enable_flash_ich7},
Uwe Hermannb0039912009-05-07 13:24:49 +0000986 {0x8086, 0x2420, OK, "Intel", "ICH0", enable_flash_ich_4e},
Uwe Hermann4179d292009-05-08 17:50:51 +0000987 {0x8086, 0x3a18, OK, "Intel", "ICH10", enable_flash_ich10},
988 {0x8086, 0x3a1a, OK, "Intel", "ICH10D", enable_flash_ich10},
989 {0x8086, 0x3a14, OK, "Intel", "ICH10DO", enable_flash_ich10},
990 {0x8086, 0x3a16, OK, "Intel", "ICH10R", enable_flash_ich10},
Uwe Hermannb0039912009-05-07 13:24:49 +0000991 {0x8086, 0x2440, OK, "Intel", "ICH2", enable_flash_ich_4e},
992 {0x8086, 0x244c, OK, "Intel", "ICH2-M", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +0000993 {0x8086, 0x248c, OK, "Intel", "ICH3-M", enable_flash_ich_4e},
Uwe Hermann4179d292009-05-08 17:50:51 +0000994 {0x8086, 0x2480, OK, "Intel", "ICH3-S", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +0000995 {0x8086, 0x24c0, OK, "Intel", "ICH4/ICH4-L", enable_flash_ich_4e},
996 {0x8086, 0x24cc, OK, "Intel", "ICH4-M", enable_flash_ich_4e},
997 {0x8086, 0x24d0, OK, "Intel", "ICH5/ICH5R", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +0000998 {0x8086, 0x2640, OK, "Intel", "ICH6/ICH6R", enable_flash_ich_dc},
999 {0x8086, 0x2641, OK, "Intel", "ICH6-M", enable_flash_ich_dc},
Uwe Hermannb0039912009-05-07 13:24:49 +00001000 {0x8086, 0x27b0, OK, "Intel", "ICH7DH", enable_flash_ich7},
1001 {0x8086, 0x27b8, OK, "Intel", "ICH7/ICH7R", enable_flash_ich7},
1002 {0x8086, 0x27b9, OK, "Intel", "ICH7M", enable_flash_ich7},
1003 {0x8086, 0x27bd, OK, "Intel", "ICH7MDH", enable_flash_ich7},
Uwe Hermann4179d292009-05-08 17:50:51 +00001004 {0x8086, 0x2410, OK, "Intel", "ICH", enable_flash_ich_4e},
Uwe Hermannb0039912009-05-07 13:24:49 +00001005 {0x8086, 0x2812, OK, "Intel", "ICH8DH", enable_flash_ich8},
1006 {0x8086, 0x2814, OK, "Intel", "ICH8DO", enable_flash_ich8},
Uwe Hermann4179d292009-05-08 17:50:51 +00001007 {0x8086, 0x2810, OK, "Intel", "ICH8/ICH8R", enable_flash_ich8},
Uwe Hermannb0039912009-05-07 13:24:49 +00001008 {0x8086, 0x2815, OK, "Intel", "ICH8M", enable_flash_ich8},
Uwe Hermann4179d292009-05-08 17:50:51 +00001009 {0x8086, 0x2811, OK, "Intel", "ICH8M-E", enable_flash_ich8},
1010 {0x8086, 0x2918, OK, "Intel", "ICH9", enable_flash_ich9},
Uwe Hermannb0039912009-05-07 13:24:49 +00001011 {0x8086, 0x2912, OK, "Intel", "ICH9DH", enable_flash_ich9},
1012 {0x8086, 0x2914, OK, "Intel", "ICH9DO", enable_flash_ich9},
Uwe Hermannb0039912009-05-07 13:24:49 +00001013 {0x8086, 0x2919, OK, "Intel", "ICH9M", enable_flash_ich9},
Uwe Hermann4179d292009-05-08 17:50:51 +00001014 {0x8086, 0x2917, OK, "Intel", "ICH9M-E", enable_flash_ich9},
1015 {0x8086, 0x2916, OK, "Intel", "ICH9R", enable_flash_ich9},
Carl-Daniel Hailfinger95baaad2009-08-21 17:26:13 +00001016 {0x8086, 0x2910, OK, "Intel", "ICH9 Engineering Sample", enable_flash_ich9},
Uwe Hermann4179d292009-05-08 17:50:51 +00001017 {0x8086, 0x1234, NT, "Intel", "MPIIX", enable_flash_piix4},
1018 {0x8086, 0x7000, OK, "Intel", "PIIX3", enable_flash_piix4},
1019 {0x8086, 0x7110, OK, "Intel", "PIIX4/4E/4M", enable_flash_piix4},
1020 {0x8086, 0x122e, OK, "Intel", "PIIX", enable_flash_piix4},
Luc Verhaegenaad7e672009-10-06 11:32:21 +00001021 {0x10de, 0x0030, OK, "NVIDIA", "nForce4/MCP4", enable_flash_nvidia_nforce2},
Uwe Hermannb0039912009-05-07 13:24:49 +00001022 {0x10de, 0x0050, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* LPC */
1023 {0x10de, 0x0051, OK, "NVIDIA", "CK804", enable_flash_ck804}, /* Pro */
Luc Verhaegen90e8e612009-05-26 09:48:28 +00001024 {0x10de, 0x0060, OK, "NVIDIA", "NForce2", enable_flash_nvidia_nforce2},
Uwe Hermanneac10162008-03-13 18:52:51 +00001025 /* Slave, should not be here, to fix known bug for A01. */
Uwe Hermannb0039912009-05-07 13:24:49 +00001026 {0x10de, 0x00d3, OK, "NVIDIA", "CK804", enable_flash_ck804},
1027 {0x10de, 0x0260, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1028 {0x10de, 0x0261, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1029 {0x10de, 0x0262, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1030 {0x10de, 0x0263, NT, "NVIDIA", "MCP51", enable_flash_ck804},
1031 {0x10de, 0x0360, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* M57SLI*/
1032 {0x10de, 0x0361, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1033 {0x10de, 0x0362, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1034 {0x10de, 0x0363, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1035 {0x10de, 0x0364, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1036 {0x10de, 0x0365, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1037 {0x10de, 0x0366, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* LPC */
1038 {0x10de, 0x0367, OK, "NVIDIA", "MCP55", enable_flash_mcp55}, /* Pro */
1039 {0x10de, 0x0548, OK, "NVIDIA", "MCP67", enable_flash_mcp55},
Uwe Hermann4179d292009-05-08 17:50:51 +00001040 {0x1039, 0x0008, OK, "SiS", "SiS5595", enable_flash_sis5595},
1041 {0x1039, 0x0630, NT, "SiS", "SiS630", enable_flash_sis630},
1042 {0x1106, 0x8324, OK, "VIA", "CX700", enable_flash_vt823x},
1043 {0x1106, 0x8231, NT, "VIA", "VT8231", enable_flash_vt823x},
Mateusz Murawskie6abef02009-06-18 12:42:46 +00001044 {0x1106, 0x3074, NT, "VIA", "VT8233", enable_flash_vt823x},
Uwe Hermann4179d292009-05-08 17:50:51 +00001045 {0x1106, 0x3177, OK, "VIA", "VT8235", enable_flash_vt823x},
1046 {0x1106, 0x3227, OK, "VIA", "VT8237", enable_flash_vt823x},
1047 {0x1106, 0x3337, OK, "VIA", "VT8237A", enable_flash_vt823x},
1048 {0x1106, 0x3372, OK, "VIA", "VT8237S", enable_flash_vt8237s_spi},
Arjan Koers8dfea832009-06-15 00:03:37 +00001049 {0x1106, 0x8353, OK, "VIA", "VX800", enable_flash_vt8237s_spi},
Uwe Hermann3e0774d2009-09-25 01:05:06 +00001050 {0x1106, 0x0596, OK, "VIA", "VT82C596", enable_flash_amd8111},
Uwe Hermann4179d292009-05-08 17:50:51 +00001051 {0x1106, 0x0586, OK, "VIA", "VT82C586A/B", enable_flash_amd8111},
1052 {0x1106, 0x0686, NT, "VIA", "VT82C686A/B", enable_flash_amd8111},
Uwe Hermann05fab752009-05-16 23:42:17 +00001053
1054 {},
Ollie Lhocbbf1252004-03-17 22:22:08 +00001055};
Ollie Lho761bf1b2004-03-20 16:46:10 +00001056
Uwe Hermanna7e05482007-05-09 10:17:44 +00001057int chipset_flash_enable(void)
Ollie Lhocbbf1252004-03-17 22:22:08 +00001058{
Uwe Hermanna7e05482007-05-09 10:17:44 +00001059 struct pci_dev *dev = 0;
Uwe Hermann372eeb52007-12-04 21:49:06 +00001060 int ret = -2; /* Nothing! */
Uwe Hermanna7e05482007-05-09 10:17:44 +00001061 int i;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001062
Uwe Hermann372eeb52007-12-04 21:49:06 +00001063 /* Now let's try to find the chipset we have... */
Uwe Hermann05fab752009-05-16 23:42:17 +00001064 for (i = 0; chipset_enables[i].vendor_name != NULL; i++) {
1065 dev = pci_dev_find(chipset_enables[i].vendor_id,
1066 chipset_enables[i].device_id);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001067 if (dev)
1068 break;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001069 }
1070
Uwe Hermanna7e05482007-05-09 10:17:44 +00001071 if (dev) {
Uwe Hermannb0039912009-05-07 13:24:49 +00001072 printf("Found chipset \"%s %s\", enabling flash write... ",
Uwe Hermann05fab752009-05-16 23:42:17 +00001073 chipset_enables[i].vendor_name,
1074 chipset_enables[i].device_name);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001075
Uwe Hermann05fab752009-05-16 23:42:17 +00001076 ret = chipset_enables[i].doit(dev,
1077 chipset_enables[i].device_name);
Uwe Hermanna7e05482007-05-09 10:17:44 +00001078 if (ret)
Uwe Hermanna502dce2007-10-17 23:55:15 +00001079 printf("FAILED!\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00001080 else
Uwe Hermannac309342007-10-10 17:42:20 +00001081 printf("OK.\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +00001082 }
Uwe Hermann1432a602009-06-28 23:26:37 +00001083 printf("This chipset supports the following protocols: %s.\n",
Uwe Hermann9899cad2009-06-28 21:47:57 +00001084 flashbuses_to_text(buses_supported));
Uwe Hermanna7e05482007-05-09 10:17:44 +00001085
1086 return ret;
Ollie Lhocbbf1252004-03-17 22:22:08 +00001087}