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review.sourcearcade.org / libgfxinit / afadcace9e96289e3aff808c4fac5830c11bdc6c / . / common / hw-gfx-gma-registers.ads
blob: 4e58651dbc26a1d3ca3762dd1800f432e5e6897a [file] [log] [blame]
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1--
2-- Copyright (C) 2015-2016 secunet Security Networks AG
3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +0200[diff] [blame]6-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]8--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
15with System;
16with HW.GFX.GMA;
17with HW.GFX.GMA.Config;
18
19private package HW.GFX.GMA.Registers
20with
21 Abstract_State =>
22 ((Address_State with Part_Of => GMA.State),
23 (Register_State with External, Part_Of => GMA.Device_State),
24 (GTT_State with External, Part_Of => GMA.Device_State)),
25 Initializes => Address_State
26is
27 type Registers_Invalid_Index is
28 (Invalid_Register, -- Allow a placeholder when access is not acceptable
29
30 RCS_RING_BUFFER_TAIL,
31 RCS_RING_BUFFER_HEAD,
32 RCS_RING_BUFFER_STRT,
33 RCS_RING_BUFFER_CTL,
34 QUIRK_02084,
35 QUIRK_02090,
36 HWSTAM,
37 MI_MODE,
38 INSTPM,
39 GT_MODE,
40 CACHE_MODE_0,
41 CTX_SIZE,
42 PP_DCLV_HIGH,
43 PP_DCLV_LOW,
44 GFX_MODE,
45 ARB_MODE,
46 HWS_PGA,
47 GAM_ECOCHK,
48 MBCTL,
49 UCGCTL1,
50 UCGCTL2,
51 VCS_RING_BUFFER_TAIL,
52 VCS_RING_BUFFER_HEAD,
53 VCS_RING_BUFFER_STRT,
54 VCS_RING_BUFFER_CTL,
55 SLEEP_PSMI_CONTROL,
56 VCS_HWSTAM,
57 VCS_PP_DCLV_HIGH,
58 VCS_PP_DCLV_LOW,
59 GAC_ECO_BITS,
60 BCS_RING_BUFFER_TAIL,
61 BCS_RING_BUFFER_HEAD,
62 BCS_RING_BUFFER_STRT,
63 BCS_RING_BUFFER_CTL,
64 BCS_HWSTAM,
65 BCS_PP_DCLV_HIGH,
66 BCS_PP_DCLV_LOW,
67 GAB_CTL_REG,
68 VGACNTRL,
69 FUSE_STATUS,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]70 ILK_DISPLAY_CHICKEN2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]71 DSPCLK_GATE_D,
72 FBA_CFB_BASE,
73 FBC_CTL,
74 IPS_CTL,
75 DEISR,
76 DEIMR,
77 DEIIR,
78 DEIER,
79 GTISR,
80 GTIMR,
81 GTIIR,
82 GTIER,
83 IIR,
84 HOTPLUG_CTL,
85 ARB_CTL,
86 DBUF_CTL,
87 WM_PIPE_A,
88 WM_PIPE_B,
89 WM1_LP_ILK,
90 WM2_LP_ILK,
91 WM3_LP_ILK,
92 WM_PIPE_C,
93 WM_LINETIME_A,
94 WM_LINETIME_B,
95 WM_LINETIME_C,
96 PWR_WELL_CTL_BIOS,
97 PWR_WELL_CTL_DRIVER,
98 PWR_WELL_CTL_KVMR,
99 PWR_WELL_CTL_DEBUG,
100 PWR_WELL_CTL5,
101 PWR_WELL_CTL6,
102 CDCLK_CTL,
103 LCPLL1_CTL,
104 LCPLL2_CTL,
105 SPLL_CTL,
106 WRPLL_CTL_1,
107 WRPLL_CTL_2,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]108 BXT_DE_PLL_ENABLE,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]109 BXT_PORT_PLL_ENABLE_A,
110 BXT_PORT_PLL_ENABLE_B,
111 BXT_PORT_PLL_ENABLE_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]112 PORT_CLK_SEL_DDIA,
113 PORT_CLK_SEL_DDIB,
114 PORT_CLK_SEL_DDIC,
115 PORT_CLK_SEL_DDID,
116 PORT_CLK_SEL_DDIE,
117 TRANSA_CLK_SEL,
118 TRANSB_CLK_SEL,
119 TRANSC_CLK_SEL,
120 NDE_RSTWRN_OPT,
121 BLC_PWM_CPU_CTL2,
122 BLC_PWM_CPU_CTL,
123 HTOTAL_A,
124 HBLANK_A,
125 HSYNC_A,
126 VTOTAL_A,
127 VBLANK_A,
128 VSYNC_A,
129 PIPEASRC,
130 PIPE_VSYNCSHIFT_A,
131 PIPEA_DATA_M1,
132 PIPEA_DATA_N1,
133 PIPEA_LINK_M1,
134 PIPEA_LINK_N1,
135 FDI_TX_CTL_A,
136 PIPEA_DDI_FUNC_CTL,
137 PIPEA_MSA_MISC,
138 SRD_CTL_A,
139 SRD_STATUS_A,
140 HTOTAL_B,
141 HBLANK_B,
142 HSYNC_B,
143 VTOTAL_B,
144 VBLANK_B,
145 VSYNC_B,
146 PIPEBSRC,
147 PIPE_VSYNCSHIFT_B,
148 PIPEB_DATA_M1,
149 PIPEB_DATA_N1,
150 PIPEB_LINK_M1,
151 PIPEB_LINK_N1,
152 FDI_TX_CTL_B,
153 PIPEB_DDI_FUNC_CTL,
154 PIPEB_MSA_MISC,
155 SRD_CTL_B,
156 SRD_STATUS_B,
157 HTOTAL_C,
158 HBLANK_C,
159 HSYNC_C,
160 VTOTAL_C,
161 VBLANK_C,
162 VSYNC_C,
163 PIPECSRC,
164 PIPE_VSYNCSHIFT_C,
165 PIPEC_DATA_M1,
166 PIPEC_DATA_N1,
167 PIPEC_LINK_M1,
168 PIPEC_LINK_N1,
169 FDI_TX_CTL_C,
170 PIPEC_DDI_FUNC_CTL,
171 PIPEC_MSA_MISC,
172 SRD_CTL_C,
173 SRD_STATUS_C,
174 DDI_BUF_CTL_A,
175 DDI_AUX_CTL_A,
176 DDI_AUX_DATA_A_1,
177 DDI_AUX_DATA_A_2,
178 DDI_AUX_DATA_A_3,
179 DDI_AUX_DATA_A_4,
180 DDI_AUX_DATA_A_5,
181 DDI_AUX_MUTEX_A,
182 DP_TP_CTL_A,
183 DDI_BUF_CTL_B,
184 DDI_AUX_CTL_B,
185 DDI_AUX_DATA_B_1,
186 DDI_AUX_DATA_B_2,
187 DDI_AUX_DATA_B_3,
188 DDI_AUX_DATA_B_4,
189 DDI_AUX_DATA_B_5,
190 DDI_AUX_MUTEX_B,
191 DP_TP_CTL_B,
192 DP_TP_STATUS_B,
193 DDI_BUF_CTL_C,
194 DDI_AUX_CTL_C,
195 DDI_AUX_DATA_C_1,
196 DDI_AUX_DATA_C_2,
197 DDI_AUX_DATA_C_3,
198 DDI_AUX_DATA_C_4,
199 DDI_AUX_DATA_C_5,
200 DDI_AUX_MUTEX_C,
201 DP_TP_CTL_C,
202 DP_TP_STATUS_C,
203 DDI_BUF_CTL_D,
204 DDI_AUX_CTL_D,
205 DDI_AUX_DATA_D_1,
206 DDI_AUX_DATA_D_2,
207 DDI_AUX_DATA_D_3,
208 DDI_AUX_DATA_D_4,
209 DDI_AUX_DATA_D_5,
210 DDI_AUX_MUTEX_D,
211 DP_TP_CTL_D,
212 DP_TP_STATUS_D,
213 DDI_BUF_CTL_E,
214 DP_TP_CTL_E,
215 DP_TP_STATUS_E,
216 SRD_CTL,
217 SRD_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]218 BXT_PHY_CTL_A,
219 BXT_PHY_CTL_B,
220 BXT_PHY_CTL_C,
221 BXT_PHY_CTL_FAM_EDP,
222 BXT_PHY_CTL_FAM_DDI,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]223 AUD_VID_DID,
224 PFA_WIN_POS,
225 PFA_WIN_SZ,
226 PFA_CTL_1,
227 PS_WIN_POS_1_A,
228 PS_WIN_SZ_1_A,
229 PS_CTRL_1_A,
230 PS_WIN_POS_2_A,
231 PS_WIN_SZ_2_A,
232 PS_CTRL_2_A,
233 PFB_WIN_POS,
234 PFB_WIN_SZ,
235 PFB_CTL_1,
236 PS_WIN_POS_1_B,
237 PS_WIN_SZ_1_B,
238 PS_CTRL_1_B,
239 PS_WIN_POS_2_B,
240 PS_WIN_SZ_2_B,
241 PS_CTRL_2_B,
242 PFC_WIN_POS,
243 PFC_WIN_SZ,
244 PFC_CTL_1,
245 PS_WIN_POS_1_C,
246 PS_WIN_SZ_1_C,
247 PS_CTRL_1_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]248 BXT_PORT_CL1CM_DW0_BC,
249 BXT_PORT_CL1CM_DW9_BC,
250 BXT_PORT_CL1CM_DW10_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]251 BXT_PORT_PLL_EBB_0_B,
252 BXT_PORT_PLL_EBB_4_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]253 DPLL1_CFGR1,
254 DPLL1_CFGR2,
255 DPLL2_CFGR1,
256 DPLL2_CFGR2,
257 DPLL3_CFGR1,
258 DPLL3_CFGR2,
259 DPLL_CTRL1,
260 DPLL_CTRL2,
261 DPLL_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]262 BXT_PORT_CL1CM_DW28_BC,
263 BXT_PORT_CL1CM_DW30_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]264 BXT_PORT_PLL_0_B,
265 BXT_PORT_PLL_1_B,
266 BXT_PORT_PLL_2_B,
267 BXT_PORT_PLL_3_B,
268 BXT_PORT_PLL_6_B,
269 BXT_PORT_PLL_8_B,
270 BXT_PORT_PLL_9_B,
271 BXT_PORT_PLL_10_B,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]272 BXT_PORT_REF_DW3_BC,
273 BXT_PORT_REF_DW6_BC,
274 BXT_PORT_REF_DW8_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]275 BXT_PORT_PLL_EBB_0_C,
276 BXT_PORT_PLL_EBB_4_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]277 BXT_PORT_CL2CM_DW6_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]278 BXT_PORT_PLL_0_C,
279 BXT_PORT_PLL_1_C,
280 BXT_PORT_PLL_2_C,
281 BXT_PORT_PLL_3_C,
282 BXT_PORT_PLL_6_C,
283 BXT_PORT_PLL_8_C,
284 BXT_PORT_PLL_9_C,
285 BXT_PORT_PLL_10_C,
286 BXT_PORT_PCS_DW12_01_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame^]287 BXT_PORT_TX_DW14_LN0_B,
288 BXT_PORT_TX_DW14_LN1_B,
289 BXT_PORT_TX_DW14_LN2_B,
290 BXT_PORT_TX_DW14_LN3_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]291 BXT_PORT_PCS_DW12_01_C,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame^]292 BXT_PORT_TX_DW14_LN0_C,
293 BXT_PORT_TX_DW14_LN1_C,
294 BXT_PORT_TX_DW14_LN2_C,
295 BXT_PORT_TX_DW14_LN3_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]296 BXT_PORT_PCS_DW12_GRP_B,
297 BXT_PORT_PCS_DW12_GRP_C,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]298 BXT_DE_PLL_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]299 HTOTAL_EDP,
300 HBLANK_EDP,
301 HSYNC_EDP,
302 VTOTAL_EDP,
303 VBLANK_EDP,
304 VSYNC_EDP,
305 PIPE_EDP_DATA_M1,
306 PIPE_EDP_DATA_N1,
307 PIPE_EDP_LINK_M1,
308 PIPE_EDP_LINK_N1,
309 PIPE_EDP_DDI_FUNC_CTL,
310 PIPE_EDP_MSA_MISC,
311 SRD_CTL_EDP,
312 SRD_STATUS_EDP,
313 PIPE_SCANLINE_A,
314 PIPEACONF,
315 PIPEAMISC,
316 PIPE_FRMCNT_A,
317 DSPACNTR,
318 DSPALINOFF,
319 DSPASTRIDE,
320 PLANE_POS_1_A,
321 PLANE_SIZE_1_A,
322 DSPASURF,
323 DSPATILEOFF,
324 PLANE_WM_1_A_0,
325 PLANE_WM_1_A_1,
326 PLANE_WM_1_A_2,
327 PLANE_WM_1_A_3,
328 PLANE_WM_1_A_4,
329 PLANE_WM_1_A_5,
330 PLANE_WM_1_A_6,
331 PLANE_WM_1_A_7,
332 PLANE_BUF_CFG_1_A,
333 SPACNTR,
334 PIPE_SCANLINE_B,
335 PIPEBCONF,
336 PIPEBMISC,
337 PIPE_FRMCNT_B,
338 DSPBCNTR,
339 DSPBLINOFF,
340 DSPBSTRIDE,
341 PLANE_POS_1_B,
342 PLANE_SIZE_1_B,
343 DSPBSURF,
344 DSPBTILEOFF,
345 PLANE_WM_1_B_0,
346 PLANE_WM_1_B_1,
347 PLANE_WM_1_B_2,
348 PLANE_WM_1_B_3,
349 PLANE_WM_1_B_4,
350 PLANE_WM_1_B_5,
351 PLANE_WM_1_B_6,
352 PLANE_WM_1_B_7,
353 PLANE_BUF_CFG_1_B,
354 SPBCNTR,
355 PIPE_SCANLINE_C,
356 PIPECCONF,
357 PIPECMISC,
358 PIPE_FRMCNT_C,
359 DSPCCNTR,
360 DSPCLINOFF,
361 DSPCSTRIDE,
362 PLANE_POS_1_C,
363 PLANE_SIZE_1_C,
364 DSPCSURF,
365 DSPCTILEOFF,
366 PLANE_WM_1_C_0,
367 PLANE_WM_1_C_1,
368 PLANE_WM_1_C_2,
369 PLANE_WM_1_C_3,
370 PLANE_WM_1_C_4,
371 PLANE_WM_1_C_5,
372 PLANE_WM_1_C_6,
373 PLANE_WM_1_C_7,
374 PLANE_BUF_CFG_1_C,
375 SPCCNTR,
376 PIPE_EDP_CONF,
377 PCH_FDI_CHICKEN_B_C,
378 QUIRK_C2004,
379 SFUSE_STRAP,
380 PCH_DSPCLK_GATE_D,
381 SDEISR,
382 SDEIMR,
383 SDEIIR,
384 SDEIER,
385 SHOTPLUG_CTL,
386 PCH_GMBUS0,
387 PCH_GMBUS1,
388 PCH_GMBUS2,
389 PCH_GMBUS3,
390 PCH_GMBUS4,
391 PCH_GMBUS5,
392 SBI_ADDR,
393 SBI_DATA,
394 SBI_CTL_STAT,
395 PCH_DPLL_A,
396 PCH_DPLL_B,
397 PCH_PIXCLK_GATE,
398 PCH_FPA0,
399 PCH_FPA1,
400 PCH_FPB0,
401 PCH_FPB1,
402 PCH_DREF_CONTROL,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]403 PCH_RAWCLK_FREQ,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]404 PCH_DPLL_SEL,
405 PCH_PP_STATUS,
406 PCH_PP_CONTROL,
407 PCH_PP_ON_DELAYS,
408 PCH_PP_OFF_DELAYS,
409 PCH_PP_DIVISOR,
410 BLC_PWM_PCH_CTL1,
411 BLC_PWM_PCH_CTL2,
412 TRANS_HTOTAL_A,
413 TRANS_HBLANK_A,
414 TRANS_HSYNC_A,
415 TRANS_VTOTAL_A,
416 TRANS_VBLANK_A,
417 TRANS_VSYNC_A,
418 TRANS_VSYNCSHIFT_A,
419 TRANSA_DATA_M1,
420 TRANSA_DATA_N1,
421 TRANSA_DP_LINK_M1,
422 TRANSA_DP_LINK_N1,
423 TRANS_DP_CTL_A,
424 TRANS_HTOTAL_B,
425 TRANS_HBLANK_B,
426 TRANS_HSYNC_B,
427 TRANS_VTOTAL_B,
428 TRANS_VBLANK_B,
429 TRANS_VSYNC_B,
430 TRANS_VSYNCSHIFT_B,
431 TRANSB_DATA_M1,
432 TRANSB_DATA_N1,
433 TRANSB_DP_LINK_M1,
434 TRANSB_DP_LINK_N1,
435 PCH_ADPA,
436 PCH_HDMIB,
437 PCH_HDMIC,
438 PCH_HDMID,
439 PCH_LVDS,
440 TRANS_DP_CTL_B,
441 TRANS_HTOTAL_C,
442 TRANS_HBLANK_C,
443 TRANS_HSYNC_C,
444 TRANS_VTOTAL_C,
445 TRANS_VBLANK_C,
446 TRANS_VSYNC_C,
447 TRANS_VSYNCSHIFT_C,
448 TRANSC_DATA_M1,
449 TRANSC_DATA_N1,
450 TRANSC_DP_LINK_M1,
451 TRANSC_DP_LINK_N1,
452 TRANS_DP_CTL_C,
453 PCH_DP_B,
454 PCH_DP_AUX_CTL_B,
455 PCH_DP_AUX_DATA_B_1,
456 PCH_DP_AUX_DATA_B_2,
457 PCH_DP_AUX_DATA_B_3,
458 PCH_DP_AUX_DATA_B_4,
459 PCH_DP_AUX_DATA_B_5,
460 PCH_DP_C,
461 PCH_DP_AUX_CTL_C,
462 PCH_DP_AUX_DATA_C_1,
463 PCH_DP_AUX_DATA_C_2,
464 PCH_DP_AUX_DATA_C_3,
465 PCH_DP_AUX_DATA_C_4,
466 PCH_DP_AUX_DATA_C_5,
467 PCH_DP_D,
468 PCH_DP_AUX_CTL_D,
469 PCH_DP_AUX_DATA_D_1,
470 PCH_DP_AUX_DATA_D_2,
471 PCH_DP_AUX_DATA_D_3,
472 PCH_DP_AUX_DATA_D_4,
473 PCH_DP_AUX_DATA_D_5,
474 AUD_CONFIG_A,
475 PCH_AUD_VID_DID,
476 AUD_HDMIW_HDMIEDID_A,
477 AUD_CNTL_ST_A,
478 AUD_CNTRL_ST2,
479 AUD_CONFIG_B,
480 AUD_HDMIW_HDMIEDID_B,
481 AUD_CNTL_ST_B,
482 AUD_CONFIG_C,
483 AUD_HDMIW_HDMIEDID_C,
484 AUD_CNTL_ST_C,
485 TRANSACONF,
486 FDI_RXA_CTL,
487 FDI_RX_MISC_A,
488 FDI_RXA_IIR,
489 FDI_RXA_IMR,
490 FDI_RXA_TUSIZE1,
491 QUIRK_F0060,
492 TRANSA_CHICKEN2,
493 TRANSBCONF,
494 FDI_RXB_CTL,
495 FDI_RX_MISC_B,
496 FDI_RXB_IIR,
497 FDI_RXB_IMR,
498 FDI_RXB_TUSIZE1,
499 QUIRK_F1060,
500 TRANSB_CHICKEN2,
501 TRANSCCONF,
502 FDI_RXC_CTL,
503 FDI_RX_MISC_C,
504 FDI_RXC_IIR,
505 FDI_RXC_IMR,
506 FDI_RXC_TUSIZE1,
507 QUIRK_F2060,
508 TRANSC_CHICKEN2,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]509 BXT_P_CR_GT_DISP_PWRON,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]510 GT_MAILBOX,
511 GT_MAILBOX_DATA,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]512 GT_MAILBOX_DATA_1,
513 BXT_PORT_CL1CM_DW0_A,
514 BXT_PORT_CL1CM_DW9_A,
515 BXT_PORT_CL1CM_DW10_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]516 BXT_PORT_PLL_EBB_0_A,
517 BXT_PORT_PLL_EBB_4_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]518 BXT_PORT_CL1CM_DW28_A,
519 BXT_PORT_CL1CM_DW30_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]520 BXT_PORT_PLL_0_A,
521 BXT_PORT_PLL_1_A,
522 BXT_PORT_PLL_2_A,
523 BXT_PORT_PLL_3_A,
524 BXT_PORT_PLL_6_A,
525 BXT_PORT_PLL_8_A,
526 BXT_PORT_PLL_9_A,
527 BXT_PORT_PLL_10_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]528 BXT_PORT_REF_DW3_A,
529 BXT_PORT_REF_DW6_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]530 BXT_PORT_REF_DW8_A,
531 BXT_PORT_PCS_DW12_01_A,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame^]532 BXT_PORT_TX_DW14_LN0_A,
533 BXT_PORT_TX_DW14_LN1_A,
534 BXT_PORT_TX_DW14_LN2_A,
535 BXT_PORT_TX_DW14_LN3_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]536 BXT_PORT_PCS_DW12_GRP_A);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]537
538 pragma Warnings
539 (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)",
540 Reason => "TODO: Should it matter?");
541 pragma Keep_Names (Registers_Invalid_Index);
542 pragma Warnings
543 (GNATprove, On, "pragma ""KEEP_NAMES"" ignored *(not yet supported)");
544
545 Register_Width : constant := 4;
546
547 for Registers_Invalid_Index use
548 (Invalid_Register => 0,
549
550 ---------------------------------------------------------------------------
551 -- Pipe A registers
552 ---------------------------------------------------------------------------
553
554 -- pipe timing registers
555
556 HTOTAL_A => 16#06_0000# / Register_Width,
557 HBLANK_A => 16#06_0004# / Register_Width,
558 HSYNC_A => 16#06_0008# / Register_Width,
559 VTOTAL_A => 16#06_000c# / Register_Width,
560 VBLANK_A => 16#06_0010# / Register_Width,
561 VSYNC_A => 16#06_0014# / Register_Width,
562 PIPEASRC => 16#06_001c# / Register_Width,
563 PIPEACONF => 16#07_0008# / Register_Width,
564 PIPEAMISC => 16#07_0030# / Register_Width,
565 TRANS_HTOTAL_A => 16#0e_0000# / Register_Width,
566 TRANS_HBLANK_A => 16#0e_0004# / Register_Width,
567 TRANS_HSYNC_A => 16#0e_0008# / Register_Width,
568 TRANS_VTOTAL_A => 16#0e_000c# / Register_Width,
569 TRANS_VBLANK_A => 16#0e_0010# / Register_Width,
570 TRANS_VSYNC_A => 16#0e_0014# / Register_Width,
571 TRANSA_DATA_M1 => 16#0e_0030# / Register_Width,
572 TRANSA_DATA_N1 => 16#0e_0034# / Register_Width,
573 TRANSA_DP_LINK_M1 => 16#0e_0040# / Register_Width,
574 TRANSA_DP_LINK_N1 => 16#0e_0044# / Register_Width,
575 PIPEA_DATA_M1 => 16#06_0030# / Register_Width,
576 PIPEA_DATA_N1 => 16#06_0034# / Register_Width,
577 PIPEA_LINK_M1 => 16#06_0040# / Register_Width,
578 PIPEA_LINK_N1 => 16#06_0044# / Register_Width,
579 PIPEA_DDI_FUNC_CTL => 16#06_0400# / Register_Width,
580 PIPEA_MSA_MISC => 16#06_0410# / Register_Width,
581
582 -- PCH sideband interface registers
583 SBI_ADDR => 16#0c_6000# / Register_Width,
584 SBI_DATA => 16#0c_6004# / Register_Width,
585 SBI_CTL_STAT => 16#0c_6008# / Register_Width,
586
587 -- clock registers
588 PCH_DPLL_A => 16#0c_6014# / Register_Width,
589 PCH_PIXCLK_GATE => 16#0c_6020# / Register_Width,
590 PCH_FPA0 => 16#0c_6040# / Register_Width,
591 PCH_FPA1 => 16#0c_6044# / Register_Width,
592
593 -- panel fitter
594 PFA_CTL_1 => 16#06_8080# / Register_Width,
595 PFA_WIN_POS => 16#06_8070# / Register_Width,
596 PFA_WIN_SZ => 16#06_8074# / Register_Width,
597 PS_WIN_POS_1_A => 16#06_8170# / Register_Width,
598 PS_WIN_SZ_1_A => 16#06_8174# / Register_Width,
599 PS_CTRL_1_A => 16#06_8180# / Register_Width,
600 PS_WIN_POS_2_A => 16#06_8270# / Register_Width,
601 PS_WIN_SZ_2_A => 16#06_8274# / Register_Width,
602 PS_CTRL_2_A => 16#06_8280# / Register_Width,
603
604 -- display control
605 DSPACNTR => 16#07_0180# / Register_Width,
606 DSPALINOFF => 16#07_0184# / Register_Width,
607 DSPASTRIDE => 16#07_0188# / Register_Width,
608 PLANE_POS_1_A => 16#07_018c# / Register_Width,
609 PLANE_SIZE_1_A => 16#07_0190# / Register_Width,
610 DSPASURF => 16#07_019c# / Register_Width,
611 DSPATILEOFF => 16#07_01a4# / Register_Width,
612
613 -- sprite control
614 SPACNTR => 16#07_0280# / Register_Width,
615
616 -- FDI and PCH transcoder control
617 FDI_TX_CTL_A => 16#06_0100# / Register_Width,
618 FDI_RXA_CTL => 16#0f_000c# / Register_Width,
619 FDI_RX_MISC_A => 16#0f_0010# / Register_Width,
620 FDI_RXA_IIR => 16#0f_0014# / Register_Width,
621 FDI_RXA_IMR => 16#0f_0018# / Register_Width,
622 FDI_RXA_TUSIZE1 => 16#0f_0030# / Register_Width,
623 TRANSACONF => 16#0f_0008# / Register_Width,
624 TRANSA_CHICKEN2 => 16#0f_0064# / Register_Width,
625
626 -- watermark registers
627 WM_LINETIME_A => 16#04_5270# / Register_Width,
628 PLANE_WM_1_A_0 => 16#07_0240# / Register_Width,
629 PLANE_WM_1_A_1 => 16#07_0244# / Register_Width,
630 PLANE_WM_1_A_2 => 16#07_0248# / Register_Width,
631 PLANE_WM_1_A_3 => 16#07_024c# / Register_Width,
632 PLANE_WM_1_A_4 => 16#07_0250# / Register_Width,
633 PLANE_WM_1_A_5 => 16#07_0254# / Register_Width,
634 PLANE_WM_1_A_6 => 16#07_0258# / Register_Width,
635 PLANE_WM_1_A_7 => 16#07_025c# / Register_Width,
636 PLANE_BUF_CFG_1_A => 16#07_027c# / Register_Width,
637
638 -- CPU transcoder clock select
639 TRANSA_CLK_SEL => 16#04_6140# / Register_Width,
640
641 ---------------------------------------------------------------------------
642 -- Pipe B registers
643 ---------------------------------------------------------------------------
644
645 -- pipe timing registers
646
647 HTOTAL_B => 16#06_1000# / Register_Width,
648 HBLANK_B => 16#06_1004# / Register_Width,
649 HSYNC_B => 16#06_1008# / Register_Width,
650 VTOTAL_B => 16#06_100c# / Register_Width,
651 VBLANK_B => 16#06_1010# / Register_Width,
652 VSYNC_B => 16#06_1014# / Register_Width,
653 PIPEBSRC => 16#06_101c# / Register_Width,
654 PIPEBCONF => 16#07_1008# / Register_Width,
655 PIPEBMISC => 16#07_1030# / Register_Width,
656 TRANS_HTOTAL_B => 16#0e_1000# / Register_Width,
657 TRANS_HBLANK_B => 16#0e_1004# / Register_Width,
658 TRANS_HSYNC_B => 16#0e_1008# / Register_Width,
659 TRANS_VTOTAL_B => 16#0e_100c# / Register_Width,
660 TRANS_VBLANK_B => 16#0e_1010# / Register_Width,
661 TRANS_VSYNC_B => 16#0e_1014# / Register_Width,
662 TRANSB_DATA_M1 => 16#0e_1030# / Register_Width,
663 TRANSB_DATA_N1 => 16#0e_1034# / Register_Width,
664 TRANSB_DP_LINK_M1 => 16#0e_1040# / Register_Width,
665 TRANSB_DP_LINK_N1 => 16#0e_1044# / Register_Width,
666 PIPEB_DATA_M1 => 16#06_1030# / Register_Width,
667 PIPEB_DATA_N1 => 16#06_1034# / Register_Width,
668 PIPEB_LINK_M1 => 16#06_1040# / Register_Width,
669 PIPEB_LINK_N1 => 16#06_1044# / Register_Width,
670 PIPEB_DDI_FUNC_CTL => 16#06_1400# / Register_Width,
671 PIPEB_MSA_MISC => 16#06_1410# / Register_Width,
672
673 -- clock registers
674 PCH_DPLL_B => 16#0c_6018# / Register_Width,
675 PCH_FPB0 => 16#0c_6048# / Register_Width,
676 PCH_FPB1 => 16#0c_604c# / Register_Width,
677
678 -- panel fitter
679 PFB_CTL_1 => 16#06_8880# / Register_Width,
680 PFB_WIN_POS => 16#06_8870# / Register_Width,
681 PFB_WIN_SZ => 16#06_8874# / Register_Width,
682 PS_WIN_POS_1_B => 16#06_8970# / Register_Width,
683 PS_WIN_SZ_1_B => 16#06_8974# / Register_Width,
684 PS_CTRL_1_B => 16#06_8980# / Register_Width,
685 PS_WIN_POS_2_B => 16#06_8a70# / Register_Width,
686 PS_WIN_SZ_2_B => 16#06_8a74# / Register_Width,
687 PS_CTRL_2_B => 16#06_8a80# / Register_Width,
688
689 -- display control
690 DSPBCNTR => 16#07_1180# / Register_Width,
691 DSPBLINOFF => 16#07_1184# / Register_Width,
692 DSPBSTRIDE => 16#07_1188# / Register_Width,
693 PLANE_POS_1_B => 16#07_118c# / Register_Width,
694 PLANE_SIZE_1_B => 16#07_1190# / Register_Width,
695 DSPBSURF => 16#07_119c# / Register_Width,
696 DSPBTILEOFF => 16#07_11a4# / Register_Width,
697
698 -- sprite control
699 SPBCNTR => 16#07_1280# / Register_Width,
700
701 -- FDI and PCH transcoder control
702 FDI_TX_CTL_B => 16#06_1100# / Register_Width,
703 FDI_RXB_CTL => 16#0f_100c# / Register_Width,
704 FDI_RX_MISC_B => 16#0f_1010# / Register_Width,
705 FDI_RXB_IIR => 16#0f_1014# / Register_Width,
706 FDI_RXB_IMR => 16#0f_1018# / Register_Width,
707 FDI_RXB_TUSIZE1 => 16#0f_1030# / Register_Width,
708 TRANSBCONF => 16#0f_1008# / Register_Width,
709 TRANSB_CHICKEN2 => 16#0f_1064# / Register_Width,
710
711 -- watermark registers
712 WM_LINETIME_B => 16#04_5274# / Register_Width,
713 PLANE_WM_1_B_0 => 16#07_1240# / Register_Width,
714 PLANE_WM_1_B_1 => 16#07_1244# / Register_Width,
715 PLANE_WM_1_B_2 => 16#07_1248# / Register_Width,
716 PLANE_WM_1_B_3 => 16#07_124c# / Register_Width,
717 PLANE_WM_1_B_4 => 16#07_1250# / Register_Width,
718 PLANE_WM_1_B_5 => 16#07_1254# / Register_Width,
719 PLANE_WM_1_B_6 => 16#07_1258# / Register_Width,
720 PLANE_WM_1_B_7 => 16#07_125c# / Register_Width,
721 PLANE_BUF_CFG_1_B => 16#07_127c# / Register_Width,
722
723 -- CPU transcoder clock select
724 TRANSB_CLK_SEL => 16#04_6144# / Register_Width,
725
726 ---------------------------------------------------------------------------
727 -- Pipe C registers
728 ---------------------------------------------------------------------------
729
730 -- pipe timing registers
731
732 HTOTAL_C => 16#06_2000# / Register_Width,
733 HBLANK_C => 16#06_2004# / Register_Width,
734 HSYNC_C => 16#06_2008# / Register_Width,
735 VTOTAL_C => 16#06_200c# / Register_Width,
736 VBLANK_C => 16#06_2010# / Register_Width,
737 VSYNC_C => 16#06_2014# / Register_Width,
738 PIPECSRC => 16#06_201c# / Register_Width,
739 PIPECCONF => 16#07_2008# / Register_Width,
740 PIPECMISC => 16#07_2030# / Register_Width,
741 TRANS_HTOTAL_C => 16#0e_2000# / Register_Width,
742 TRANS_HBLANK_C => 16#0e_2004# / Register_Width,
743 TRANS_HSYNC_C => 16#0e_2008# / Register_Width,
744 TRANS_VTOTAL_C => 16#0e_200c# / Register_Width,
745 TRANS_VBLANK_C => 16#0e_2010# / Register_Width,
746 TRANS_VSYNC_C => 16#0e_2014# / Register_Width,
747 TRANSC_DATA_M1 => 16#0e_2030# / Register_Width,
748 TRANSC_DATA_N1 => 16#0e_2034# / Register_Width,
749 TRANSC_DP_LINK_M1 => 16#0e_2040# / Register_Width,
750 TRANSC_DP_LINK_N1 => 16#0e_2044# / Register_Width,
751 PIPEC_DATA_M1 => 16#06_2030# / Register_Width,
752 PIPEC_DATA_N1 => 16#06_2034# / Register_Width,
753 PIPEC_LINK_M1 => 16#06_2040# / Register_Width,
754 PIPEC_LINK_N1 => 16#06_2044# / Register_Width,
755 PIPEC_DDI_FUNC_CTL => 16#06_2400# / Register_Width,
756 PIPEC_MSA_MISC => 16#06_2410# / Register_Width,
757
758 -- panel fitter
759 PFC_CTL_1 => 16#06_9080# / Register_Width,
760 PFC_WIN_POS => 16#06_9070# / Register_Width,
761 PFC_WIN_SZ => 16#06_9074# / Register_Width,
762 PS_WIN_POS_1_C => 16#06_9170# / Register_Width,
763 PS_WIN_SZ_1_C => 16#06_9174# / Register_Width,
764 PS_CTRL_1_C => 16#06_9180# / Register_Width,
765
766 -- display control
767 DSPCCNTR => 16#07_2180# / Register_Width,
768 DSPCLINOFF => 16#07_2184# / Register_Width,
769 DSPCSTRIDE => 16#07_2188# / Register_Width,
770 PLANE_POS_1_C => 16#07_218c# / Register_Width,
771 PLANE_SIZE_1_C => 16#07_2190# / Register_Width,
772 DSPCSURF => 16#07_219c# / Register_Width,
773 DSPCTILEOFF => 16#07_21a4# / Register_Width,
774
775 -- sprite control
776 SPCCNTR => 16#07_2280# / Register_Width,
777
778 -- PCH transcoder control
779 FDI_TX_CTL_C => 16#06_2100# / Register_Width,
780 FDI_RXC_CTL => 16#0f_200c# / Register_Width,
781 FDI_RX_MISC_C => 16#0f_2010# / Register_Width,
782 FDI_RXC_IIR => 16#0f_2014# / Register_Width,
783 FDI_RXC_IMR => 16#0f_2018# / Register_Width,
784 FDI_RXC_TUSIZE1 => 16#0f_2030# / Register_Width,
785 TRANSCCONF => 16#0f_2008# / Register_Width,
786 TRANSC_CHICKEN2 => 16#0f_2064# / Register_Width,
787
788 -- watermark registers
789 WM_LINETIME_C => 16#04_5278# / Register_Width,
790 PLANE_WM_1_C_0 => 16#07_2240# / Register_Width,
791 PLANE_WM_1_C_1 => 16#07_2244# / Register_Width,
792 PLANE_WM_1_C_2 => 16#07_2248# / Register_Width,
793 PLANE_WM_1_C_3 => 16#07_224c# / Register_Width,
794 PLANE_WM_1_C_4 => 16#07_2250# / Register_Width,
795 PLANE_WM_1_C_5 => 16#07_2254# / Register_Width,
796 PLANE_WM_1_C_6 => 16#07_2258# / Register_Width,
797 PLANE_WM_1_C_7 => 16#07_225c# / Register_Width,
798 PLANE_BUF_CFG_1_C => 16#07_227c# / Register_Width,
799
800 -- CPU transcoder clock select
801 TRANSC_CLK_SEL => 16#04_6148# / Register_Width,
802
803 ---------------------------------------------------------------------------
804 -- Pipe EDP registers
805 ---------------------------------------------------------------------------
806
807 -- pipe timing registers
808
809 HTOTAL_EDP => 16#06_f000# / Register_Width,
810 HBLANK_EDP => 16#06_f004# / Register_Width,
811 HSYNC_EDP => 16#06_f008# / Register_Width,
812 VTOTAL_EDP => 16#06_f00c# / Register_Width,
813 VBLANK_EDP => 16#06_f010# / Register_Width,
814 VSYNC_EDP => 16#06_f014# / Register_Width,
815 PIPE_EDP_CONF => 16#07_f008# / Register_Width,
816 PIPE_EDP_DATA_M1 => 16#06_f030# / Register_Width,
817 PIPE_EDP_DATA_N1 => 16#06_f034# / Register_Width,
818 PIPE_EDP_LINK_M1 => 16#06_f040# / Register_Width,
819 PIPE_EDP_LINK_N1 => 16#06_f044# / Register_Width,
820 PIPE_EDP_DDI_FUNC_CTL => 16#06_f400# / Register_Width,
821 PIPE_EDP_MSA_MISC => 16#06_f410# / Register_Width,
822
823 -- PSR registers
824 SRD_CTL => 16#06_4800# / Register_Width,
825 SRD_CTL_A => 16#06_0800# / Register_Width,
826 SRD_CTL_B => 16#06_1800# / Register_Width,
827 SRD_CTL_C => 16#06_2800# / Register_Width,
828 SRD_CTL_EDP => 16#06_f800# / Register_Width,
829 SRD_STATUS => 16#06_4840# / Register_Width,
830 SRD_STATUS_A => 16#06_0840# / Register_Width,
831 SRD_STATUS_B => 16#06_1840# / Register_Width,
832 SRD_STATUS_C => 16#06_2840# / Register_Width,
833 SRD_STATUS_EDP => 16#06_f840# / Register_Width,
834
835 -- DDI registers
836 DDI_BUF_CTL_A => 16#06_4000# / Register_Width, -- aliased by DP_CTL_A
837 DDI_AUX_CTL_A => 16#06_4010# / Register_Width, -- aliased by DP_AUX_CTL_A
838 DDI_AUX_DATA_A_1 => 16#06_4014# / Register_Width, -- aliased by DP_AUX_DATA_A_1
839 DDI_AUX_DATA_A_2 => 16#06_4018# / Register_Width, -- aliased by DP_AUX_DATA_A_2
840 DDI_AUX_DATA_A_3 => 16#06_401c# / Register_Width, -- aliased by DP_AUX_DATA_A_3
841 DDI_AUX_DATA_A_4 => 16#06_4020# / Register_Width, -- aliased by DP_AUX_DATA_A_4
842 DDI_AUX_DATA_A_5 => 16#06_4024# / Register_Width, -- aliased by DP_AUX_DATA_A_5
843 DDI_AUX_MUTEX_A => 16#06_402c# / Register_Width,
844 DDI_BUF_CTL_B => 16#06_4100# / Register_Width,
845 DDI_AUX_CTL_B => 16#06_4110# / Register_Width,
846 DDI_AUX_DATA_B_1 => 16#06_4114# / Register_Width,
847 DDI_AUX_DATA_B_2 => 16#06_4118# / Register_Width,
848 DDI_AUX_DATA_B_3 => 16#06_411c# / Register_Width,
849 DDI_AUX_DATA_B_4 => 16#06_4120# / Register_Width,
850 DDI_AUX_DATA_B_5 => 16#06_4124# / Register_Width,
851 DDI_AUX_MUTEX_B => 16#06_412c# / Register_Width,
852 DDI_BUF_CTL_C => 16#06_4200# / Register_Width,
853 DDI_AUX_CTL_C => 16#06_4210# / Register_Width,
854 DDI_AUX_DATA_C_1 => 16#06_4214# / Register_Width,
855 DDI_AUX_DATA_C_2 => 16#06_4218# / Register_Width,
856 DDI_AUX_DATA_C_3 => 16#06_421c# / Register_Width,
857 DDI_AUX_DATA_C_4 => 16#06_4220# / Register_Width,
858 DDI_AUX_DATA_C_5 => 16#06_4224# / Register_Width,
859 DDI_AUX_MUTEX_C => 16#06_422c# / Register_Width,
860 DDI_BUF_CTL_D => 16#06_4300# / Register_Width,
861 DDI_AUX_CTL_D => 16#06_4310# / Register_Width,
862 DDI_AUX_DATA_D_1 => 16#06_4314# / Register_Width,
863 DDI_AUX_DATA_D_2 => 16#06_4318# / Register_Width,
864 DDI_AUX_DATA_D_3 => 16#06_431c# / Register_Width,
865 DDI_AUX_DATA_D_4 => 16#06_4320# / Register_Width,
866 DDI_AUX_DATA_D_5 => 16#06_4324# / Register_Width,
867 DDI_AUX_MUTEX_D => 16#06_432c# / Register_Width,
868 DDI_BUF_CTL_E => 16#06_4400# / Register_Width,
869 DP_TP_CTL_A => 16#06_4040# / Register_Width,
870 DP_TP_CTL_B => 16#06_4140# / Register_Width,
871 DP_TP_CTL_C => 16#06_4240# / Register_Width,
872 DP_TP_CTL_D => 16#06_4340# / Register_Width,
873 DP_TP_CTL_E => 16#06_4440# / Register_Width,
874 DP_TP_STATUS_B => 16#06_4144# / Register_Width,
875 DP_TP_STATUS_C => 16#06_4244# / Register_Width,
876 DP_TP_STATUS_D => 16#06_4344# / Register_Width,
877 DP_TP_STATUS_E => 16#06_4444# / Register_Width,
878 PORT_CLK_SEL_DDIA => 16#04_6100# / Register_Width,
879 PORT_CLK_SEL_DDIB => 16#04_6104# / Register_Width,
880 PORT_CLK_SEL_DDIC => 16#04_6108# / Register_Width,
881 PORT_CLK_SEL_DDID => 16#04_610c# / Register_Width,
882 PORT_CLK_SEL_DDIE => 16#04_6110# / Register_Width,
883
884 -- Skylake DPLL registers
885 DPLL1_CFGR1 => 16#06_c040# / Register_Width,
886 DPLL1_CFGR2 => 16#06_c044# / Register_Width,
887 DPLL2_CFGR1 => 16#06_c048# / Register_Width,
888 DPLL2_CFGR2 => 16#06_c04c# / Register_Width,
889 DPLL3_CFGR1 => 16#06_c050# / Register_Width,
890 DPLL3_CFGR2 => 16#06_c054# / Register_Width,
891 DPLL_CTRL1 => 16#06_c058# / Register_Width,
892 DPLL_CTRL2 => 16#06_c05c# / Register_Width,
893 DPLL_STATUS => 16#06_c060# / Register_Width,
894
895 -- CD CLK register
896 CDCLK_CTL => 16#04_6000# / Register_Width,
897
898 -- Skylake LCPLL registers
899 LCPLL1_CTL => 16#04_6010# / Register_Width,
900 LCPLL2_CTL => 16#04_6014# / Register_Width,
901
902 -- SPLL register
903 SPLL_CTL => 16#04_6020# / Register_Width,
904
905 -- WRPLL registers
906 WRPLL_CTL_1 => 16#04_6040# / Register_Width,
907 WRPLL_CTL_2 => 16#04_6060# / Register_Width,
908
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]909 -- Broxton Display Engine PLL registers
910 BXT_DE_PLL_CTL => 16#06_d000# / Register_Width,
911 BXT_DE_PLL_ENABLE => 16#04_6070# / Register_Width,
912
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]913 -- Broxton DDI PHY PLL registers
914 BXT_PORT_PLL_ENABLE_A => 16#04_6074# / Register_Width,
915 BXT_PORT_PLL_ENABLE_B => 16#04_6078# / Register_Width,
916 BXT_PORT_PLL_ENABLE_C => 16#04_607c# / Register_Width,
917 BXT_PORT_PLL_EBB_0_A => 16#16_2034# / Register_Width,
918 BXT_PORT_PLL_EBB_4_A => 16#16_2038# / Register_Width,
919 BXT_PORT_PLL_0_A => 16#16_2100# / Register_Width,
920 BXT_PORT_PLL_1_A => 16#16_2104# / Register_Width,
921 BXT_PORT_PLL_2_A => 16#16_2108# / Register_Width,
922 BXT_PORT_PLL_3_A => 16#16_210c# / Register_Width,
923 BXT_PORT_PLL_6_A => 16#16_2118# / Register_Width,
924 BXT_PORT_PLL_8_A => 16#16_2120# / Register_Width,
925 BXT_PORT_PLL_9_A => 16#16_2124# / Register_Width,
926 BXT_PORT_PLL_10_A => 16#16_2128# / Register_Width,
927 BXT_PORT_PCS_DW12_01_A => 16#16_2430# / Register_Width,
928 BXT_PORT_PCS_DW12_GRP_A => 16#16_2c30# / Register_Width,
929 BXT_PORT_PLL_EBB_0_B => 16#06_c034# / Register_Width,
930 BXT_PORT_PLL_EBB_4_B => 16#06_c038# / Register_Width,
931 BXT_PORT_PLL_0_B => 16#06_c100# / Register_Width,
932 BXT_PORT_PLL_1_B => 16#06_c104# / Register_Width,
933 BXT_PORT_PLL_2_B => 16#06_c108# / Register_Width,
934 BXT_PORT_PLL_3_B => 16#06_c10c# / Register_Width,
935 BXT_PORT_PLL_6_B => 16#06_c118# / Register_Width,
936 BXT_PORT_PLL_8_B => 16#06_c120# / Register_Width,
937 BXT_PORT_PLL_9_B => 16#06_c124# / Register_Width,
938 BXT_PORT_PLL_10_B => 16#06_c128# / Register_Width,
939 BXT_PORT_PCS_DW12_01_B => 16#06_c430# / Register_Width,
940 BXT_PORT_PCS_DW12_GRP_B => 16#06_cc30# / Register_Width,
941 BXT_PORT_PLL_EBB_0_C => 16#06_c340# / Register_Width,
942 BXT_PORT_PLL_EBB_4_C => 16#06_c344# / Register_Width,
943 BXT_PORT_PLL_0_C => 16#06_c380# / Register_Width,
944 BXT_PORT_PLL_1_C => 16#06_c384# / Register_Width,
945 BXT_PORT_PLL_2_C => 16#06_c388# / Register_Width,
946 BXT_PORT_PLL_3_C => 16#06_c38c# / Register_Width,
947 BXT_PORT_PLL_6_C => 16#06_c398# / Register_Width,
948 BXT_PORT_PLL_8_C => 16#06_c3a0# / Register_Width,
949 BXT_PORT_PLL_9_C => 16#06_c3a4# / Register_Width,
950 BXT_PORT_PLL_10_C => 16#06_c3a8# / Register_Width,
951 BXT_PORT_PCS_DW12_01_C => 16#06_c830# / Register_Width,
952 BXT_PORT_PCS_DW12_GRP_C => 16#06_ce30# / Register_Width,
953
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]954 -- Broxton DDI PHY registers
955 BXT_P_CR_GT_DISP_PWRON => 16#13_8090# / Register_Width,
956 BXT_PHY_CTL_A => 16#06_4c00# / Register_Width,
957 BXT_PHY_CTL_B => 16#06_4c10# / Register_Width,
958 BXT_PHY_CTL_C => 16#06_4c20# / Register_Width,
959 BXT_PHY_CTL_FAM_EDP => 16#06_4c80# / Register_Width,
960 BXT_PHY_CTL_FAM_DDI => 16#06_4c90# / Register_Width,
961
962 -- Broxton DDI PHY common lane registers
963 BXT_PORT_CL1CM_DW0_A => 16#16_2000# / Register_Width,
964 BXT_PORT_CL1CM_DW0_BC => 16#06_c000# / Register_Width,
965 BXT_PORT_CL1CM_DW9_A => 16#16_2024# / Register_Width,
966 BXT_PORT_CL1CM_DW9_BC => 16#06_c024# / Register_Width,
967 BXT_PORT_CL1CM_DW10_A => 16#16_2028# / Register_Width,
968 BXT_PORT_CL1CM_DW10_BC => 16#06_c028# / Register_Width,
969 BXT_PORT_CL1CM_DW28_A => 16#16_2070# / Register_Width,
970 BXT_PORT_CL1CM_DW28_BC => 16#06_c070# / Register_Width,
971 BXT_PORT_CL1CM_DW30_A => 16#16_2078# / Register_Width,
972 BXT_PORT_CL1CM_DW30_BC => 16#06_c078# / Register_Width,
973 BXT_PORT_CL2CM_DW6_BC => 16#06_c358# / Register_Width,
974
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame^]975 -- Broxton DDI PHY TX lane registers
976 BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width,
977 BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width,
978 BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width,
979 BXT_PORT_TX_DW14_LN3_A => 16#16_27b8# / Register_Width,
980 BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width,
981 BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width,
982 BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width,
983 BXT_PORT_TX_DW14_LN3_B => 16#06_c7b8# / Register_Width,
984 BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width,
985 BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width,
986 BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width,
987 BXT_PORT_TX_DW14_LN3_C => 16#06_cbb8# / Register_Width,
988
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]989 -- Broxton DDI PHY ref registers
990 BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width,
991 BXT_PORT_REF_DW3_BC => 16#06_c18c# / Register_Width,
992 BXT_PORT_REF_DW6_A => 16#16_2198# / Register_Width,
993 BXT_PORT_REF_DW6_BC => 16#06_c198# / Register_Width,
994 BXT_PORT_REF_DW8_A => 16#16_21a0# / Register_Width,
995 BXT_PORT_REF_DW8_BC => 16#06_c1a0# / Register_Width,
996
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]997 -- Power Down Well registers
998 PWR_WELL_CTL_BIOS => 16#04_5400# / Register_Width,
999 PWR_WELL_CTL_DRIVER => 16#04_5404# / Register_Width,
1000 PWR_WELL_CTL_KVMR => 16#04_5408# / Register_Width,
1001 PWR_WELL_CTL_DEBUG => 16#04_540c# / Register_Width,
1002 PWR_WELL_CTL5 => 16#04_5410# / Register_Width,
1003 PWR_WELL_CTL6 => 16#04_5414# / Register_Width,
1004
1005 -- class Panel registers
1006 PCH_PP_STATUS => 16#0c_7200# / Register_Width,
1007 PCH_PP_CONTROL => 16#0c_7204# / Register_Width,
1008 PCH_PP_ON_DELAYS => 16#0c_7208# / Register_Width,
1009 PCH_PP_OFF_DELAYS => 16#0c_720c# / Register_Width,
1010 PCH_PP_DIVISOR => 16#0c_7210# / Register_Width,
1011 BLC_PWM_CPU_CTL => 16#04_8254# / Register_Width,
1012 BLC_PWM_PCH_CTL2 => 16#0c_8254# / Register_Width,
1013
1014 -- PCH LVDS Connector Registers
1015 PCH_LVDS => 16#0e_1180# / Register_Width,
1016
1017 -- PCH ADPA Connector Registers
1018 PCH_ADPA => 16#0e_1100# / Register_Width,
1019
1020 -- PCH HDMIB Connector Registers
1021 PCH_HDMIB => 16#0e_1140# / Register_Width,
1022
1023 -- PCH HDMIC Connector Registers
1024 PCH_HDMIC => 16#0e_1150# / Register_Width,
1025
1026 -- PCH HDMID Connector Registers
1027 PCH_HDMID => 16#0e_1160# / Register_Width,
1028
1029 -- Intel Registers
1030 VGACNTRL => 16#04_1000# / Register_Width,
1031 FUSE_STATUS => 16#04_2000# / Register_Width,
1032 FBA_CFB_BASE => 16#04_3200# / Register_Width,
1033 IPS_CTL => 16#04_3408# / Register_Width,
1034 ARB_CTL => 16#04_5000# / Register_Width,
1035 DBUF_CTL => 16#04_5008# / Register_Width,
1036 NDE_RSTWRN_OPT => 16#04_6408# / Register_Width,
1037 PCH_DREF_CONTROL => 16#0c_6200# / Register_Width,
1038 BLC_PWM_PCH_CTL1 => 16#0c_8250# / Register_Width,
1039 BLC_PWM_CPU_CTL2 => 16#04_8250# / Register_Width,
1040 PCH_DPLL_SEL => 16#0c_7000# / Register_Width,
1041 GT_MAILBOX => 16#13_8124# / Register_Width,
1042 GT_MAILBOX_DATA => 16#13_8128# / Register_Width,
1043 GT_MAILBOX_DATA_1 => 16#13_812c# / Register_Width,
1044
1045 PCH_DP_B => 16#0e_4100# / Register_Width,
1046 PCH_DP_AUX_CTL_B => 16#0e_4110# / Register_Width,
1047 PCH_DP_AUX_DATA_B_1 => 16#0e_4114# / Register_Width,
1048 PCH_DP_AUX_DATA_B_2 => 16#0e_4118# / Register_Width,
1049 PCH_DP_AUX_DATA_B_3 => 16#0e_411c# / Register_Width,
1050 PCH_DP_AUX_DATA_B_4 => 16#0e_4120# / Register_Width,
1051 PCH_DP_AUX_DATA_B_5 => 16#0e_4124# / Register_Width,
1052 PCH_DP_C => 16#0e_4200# / Register_Width,
1053 PCH_DP_AUX_CTL_C => 16#0e_4210# / Register_Width,
1054 PCH_DP_AUX_DATA_C_1 => 16#0e_4214# / Register_Width,
1055 PCH_DP_AUX_DATA_C_2 => 16#0e_4218# / Register_Width,
1056 PCH_DP_AUX_DATA_C_3 => 16#0e_421c# / Register_Width,
1057 PCH_DP_AUX_DATA_C_4 => 16#0e_4220# / Register_Width,
1058 PCH_DP_AUX_DATA_C_5 => 16#0e_4224# / Register_Width,
1059 PCH_DP_D => 16#0e_4300# / Register_Width,
1060 PCH_DP_AUX_CTL_D => 16#0e_4310# / Register_Width,
1061 PCH_DP_AUX_DATA_D_1 => 16#0e_4314# / Register_Width,
1062 PCH_DP_AUX_DATA_D_2 => 16#0e_4318# / Register_Width,
1063 PCH_DP_AUX_DATA_D_3 => 16#0e_431c# / Register_Width,
1064 PCH_DP_AUX_DATA_D_4 => 16#0e_4320# / Register_Width,
1065 PCH_DP_AUX_DATA_D_5 => 16#0e_4324# / Register_Width,
1066
1067 -- watermark registers
1068 WM1_LP_ILK => 16#04_5108# / Register_Width,
1069 WM2_LP_ILK => 16#04_510c# / Register_Width,
1070 WM3_LP_ILK => 16#04_5110# / Register_Width,
1071
1072 -- audio VID/DID
1073 AUD_VID_DID => 16#06_5020# / Register_Width,
1074 PCH_AUD_VID_DID => 16#0e_5020# / Register_Width,
1075
1076 -- interrupt registers
1077 DEISR => 16#04_4000# / Register_Width,
1078 DEIMR => 16#04_4004# / Register_Width,
1079 DEIIR => 16#04_4008# / Register_Width,
1080 DEIER => 16#04_400c# / Register_Width,
1081 GTISR => 16#04_4010# / Register_Width,
1082 GTIMR => 16#04_4014# / Register_Width,
1083 GTIIR => 16#04_4018# / Register_Width,
1084 GTIER => 16#04_401c# / Register_Width,
1085 SDEISR => 16#0c_4000# / Register_Width,
1086 SDEIMR => 16#0c_4004# / Register_Width,
1087 SDEIIR => 16#0c_4008# / Register_Width,
1088 SDEIER => 16#0c_400c# / Register_Width,
1089
1090 -- I2C stuff
1091 PCH_GMBUS0 => 16#0c_5100# / Register_Width,
1092 PCH_GMBUS1 => 16#0c_5104# / Register_Width,
1093 PCH_GMBUS2 => 16#0c_5108# / Register_Width,
1094 PCH_GMBUS3 => 16#0c_510c# / Register_Width,
1095 PCH_GMBUS4 => 16#0c_5110# / Register_Width,
1096 PCH_GMBUS5 => 16#0c_5120# / Register_Width,
1097
1098 -- clock gating -- maybe have to touch this
1099 DSPCLK_GATE_D => 16#04_2020# / Register_Width,
1100 PCH_FDI_CHICKEN_B_C => 16#0c_2000# / Register_Width,
1101 PCH_DSPCLK_GATE_D => 16#0c_2020# / Register_Width,
1102
1103 -- hotplug and initial detection
1104 HOTPLUG_CTL => 16#04_4030# / Register_Width,
1105 SHOTPLUG_CTL => 16#0c_4030# / Register_Width,
1106 SFUSE_STRAP => 16#0c_2014# / Register_Width,
1107
1108 -- Render Engine Command Streamer
1109 ARB_MODE => 16#00_4030# / Register_Width,
1110 HWS_PGA => 16#00_4080# / Register_Width,
1111 RCS_RING_BUFFER_TAIL => 16#00_2030# / Register_Width,
1112 VCS_RING_BUFFER_TAIL => 16#01_2030# / Register_Width,
1113 BCS_RING_BUFFER_TAIL => 16#02_2030# / Register_Width,
1114 RCS_RING_BUFFER_HEAD => 16#00_2034# / Register_Width,
1115 VCS_RING_BUFFER_HEAD => 16#01_2034# / Register_Width,
1116 BCS_RING_BUFFER_HEAD => 16#02_2034# / Register_Width,
1117 RCS_RING_BUFFER_STRT => 16#00_2038# / Register_Width,
1118 VCS_RING_BUFFER_STRT => 16#01_2038# / Register_Width,
1119 BCS_RING_BUFFER_STRT => 16#02_2038# / Register_Width,
1120 RCS_RING_BUFFER_CTL => 16#00_203c# / Register_Width,
1121 VCS_RING_BUFFER_CTL => 16#01_203c# / Register_Width,
1122 BCS_RING_BUFFER_CTL => 16#02_203c# / Register_Width,
1123 MI_MODE => 16#00_209c# / Register_Width,
1124 INSTPM => 16#00_20c0# / Register_Width,
1125 GAB_CTL_REG => 16#02_4000# / Register_Width,
1126 PP_DCLV_HIGH => 16#00_2220# / Register_Width,
1127 PP_DCLV_LOW => 16#00_2228# / Register_Width,
1128 VCS_PP_DCLV_HIGH => 16#01_2220# / Register_Width,
1129 VCS_PP_DCLV_LOW => 16#01_2228# / Register_Width,
1130 BCS_PP_DCLV_HIGH => 16#02_2220# / Register_Width,
1131 BCS_PP_DCLV_LOW => 16#02_2228# / Register_Width,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1132 ILK_DISPLAY_CHICKEN2 => 16#04_2004# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1133 UCGCTL1 => 16#00_9400# / Register_Width,
1134 UCGCTL2 => 16#00_9404# / Register_Width,
1135 MBCTL => 16#00_907c# / Register_Width,
1136 HWSTAM => 16#00_2098# / Register_Width,
1137 VCS_HWSTAM => 16#01_2098# / Register_Width,
1138 BCS_HWSTAM => 16#02_2098# / Register_Width,
1139 IIR => 16#04_4028# / Register_Width,
1140 PIPE_FRMCNT_A => 16#07_0040# / Register_Width,
1141 PIPE_FRMCNT_B => 16#07_1040# / Register_Width,
1142 PIPE_FRMCNT_C => 16#07_2040# / Register_Width,
1143 FBC_CTL => 16#04_3208# / Register_Width,
1144 PIPE_VSYNCSHIFT_A => 16#06_0028# / Register_Width,
1145 PIPE_VSYNCSHIFT_B => 16#06_1028# / Register_Width,
1146 PIPE_VSYNCSHIFT_C => 16#06_2028# / Register_Width,
1147 WM_PIPE_A => 16#04_5100# / Register_Width,
1148 WM_PIPE_B => 16#04_5104# / Register_Width,
1149 WM_PIPE_C => 16#04_5200# / Register_Width,
1150 PIPE_SCANLINE_A => 16#07_0000# / Register_Width,
1151 PIPE_SCANLINE_B => 16#07_1000# / Register_Width,
1152 PIPE_SCANLINE_C => 16#07_2000# / Register_Width,
1153 GFX_MODE => 16#00_2520# / Register_Width,
1154 CACHE_MODE_0 => 16#00_2120# / Register_Width,
1155 SLEEP_PSMI_CONTROL => 16#01_2050# / Register_Width,
1156 CTX_SIZE => 16#00_21a0# / Register_Width,
1157 GAC_ECO_BITS => 16#01_4090# / Register_Width,
1158 GAM_ECOCHK => 16#00_4090# / Register_Width,
1159 QUIRK_02084 => 16#00_2084# / Register_Width,
1160 QUIRK_02090 => 16#00_2090# / Register_Width,
1161 GT_MODE => 16#00_20d0# / Register_Width,
1162 QUIRK_F0060 => 16#0f_0060# / Register_Width,
1163 QUIRK_F1060 => 16#0f_1060# / Register_Width,
1164 QUIRK_F2060 => 16#0f_2060# / Register_Width,
1165 AUD_CNTRL_ST2 => 16#0e_50c0# / Register_Width,
1166 AUD_CNTL_ST_A => 16#0e_50b4# / Register_Width,
1167 AUD_CNTL_ST_B => 16#0e_51b4# / Register_Width,
1168 AUD_CNTL_ST_C => 16#0e_52b4# / Register_Width,
1169 AUD_HDMIW_HDMIEDID_A => 16#0e_5050# / Register_Width,
1170 AUD_HDMIW_HDMIEDID_B => 16#0e_5150# / Register_Width,
1171 AUD_HDMIW_HDMIEDID_C => 16#0e_5250# / Register_Width,
1172 AUD_CONFIG_A => 16#0e_5000# / Register_Width,
1173 AUD_CONFIG_B => 16#0e_5100# / Register_Width,
1174 AUD_CONFIG_C => 16#0e_5200# / Register_Width,
1175 TRANS_DP_CTL_A => 16#0e_0300# / Register_Width,
1176 TRANS_DP_CTL_B => 16#0e_1300# / Register_Width,
1177 TRANS_DP_CTL_C => 16#0e_2300# / Register_Width,
1178 TRANS_VSYNCSHIFT_A => 16#0e_0028# / Register_Width,
1179 TRANS_VSYNCSHIFT_B => 16#0e_1028# / Register_Width,
1180 TRANS_VSYNCSHIFT_C => 16#0e_2028# / Register_Width,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]1181 PCH_RAWCLK_FREQ => 16#0c_6204# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1182 QUIRK_C2004 => 16#0c_2004# / Register_Width);
1183
1184 subtype Registers_Index is Registers_Invalid_Index range
1185 Registers_Invalid_Index'Succ (Invalid_Register) ..
1186 Registers_Invalid_Index'Last;
1187
1188 -- aliased registers
1189 DP_CTL_A : constant Registers_Index := DDI_BUF_CTL_A;
1190 DP_AUX_CTL_A : constant Registers_Index := DDI_AUX_CTL_A;
1191 DP_AUX_DATA_A_1 : constant Registers_Index := DDI_AUX_DATA_A_1;
1192 DP_AUX_DATA_A_2 : constant Registers_Index := DDI_AUX_DATA_A_2;
1193 DP_AUX_DATA_A_3 : constant Registers_Index := DDI_AUX_DATA_A_3;
1194 DP_AUX_DATA_A_4 : constant Registers_Index := DDI_AUX_DATA_A_4;
1195 DP_AUX_DATA_A_5 : constant Registers_Index := DDI_AUX_DATA_A_5;
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1196 ILK_DISPLAY_CHICKEN1 : constant Registers_Index := FUSE_STATUS;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1197
1198 ---------------------------------------------------------------------------
1199
1200 Default_Timeout_MS : constant := 10;
1201
1202 ---------------------------------------------------------------------------
1203
1204 procedure Posting_Read
1205 (Register : in Registers_Index)
1206 with
1207 Global => (In_Out => Register_State),
1208 Depends => (Register_State =>+ (Register)),
1209 Pre => True,
1210 Post => True;
1211
1212 pragma Warnings (GNATprove, Off, "unused variable ""Verbose""",
1213 Reason => "Only used on debugging path");
1214 procedure Read
1215 (Register : in Registers_Index;
1216 Value : out Word32;
1217 Verbose : in Boolean := True)
1218 with
1219 Global => (In_Out => Register_State),
1220 Depends => ((Value, Register_State) => (Register, Register_State),
1221 null => Verbose),
1222 Pre => True,
1223 Post => True;
1224 pragma Warnings (GNATprove, On, "unused variable ""Verbose""");
1225
1226 procedure Write
1227 (Register : Registers_Index;
1228 Value : Word32)
1229 with
1230 Global => (In_Out => Register_State),
1231 Depends => (Register_State => (Register, Register_State, Value)),
1232 Pre => True,
1233 Post => True;
1234
1235 procedure Is_Set_Mask
1236 (Register : in Registers_Index;
1237 Mask : in Word32;
1238 Result : out Boolean);
1239
1240 pragma Warnings (GNATprove, Off, "unused initial value of ""Verbose""",
1241 Reason => "Only used on debugging path");
Nico Huberbcb2c472017-02-02 16:39:26 +0100[diff] [blame]1242 procedure Wait
1243 (Register : Registers_Index;
1244 Mask : Word32;
1245 Value : Word32;
1246 TOut_MS : Natural := Default_Timeout_MS;
1247 Verbose : Boolean := False);
1248
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1249 procedure Wait_Set_Mask
1250 (Register : Registers_Index;
1251 Mask : Word32;
1252 TOut_MS : Natural := Default_Timeout_MS;
1253 Verbose : Boolean := False);
1254
1255 procedure Wait_Unset_Mask
1256 (Register : Registers_Index;
1257 Mask : Word32;
1258 TOut_MS : Natural := Default_Timeout_MS;
1259 Verbose : Boolean := False);
1260 pragma Warnings (GNATprove, On, "unused initial value of ""Verbose""");
1261
1262 procedure Set_Mask
1263 (Register : Registers_Index;
1264 Mask : Word32);
1265
1266 procedure Unset_Mask
1267 (Register : Registers_Index;
1268 Mask : Word32);
1269
1270 procedure Unset_And_Set_Mask
1271 (Register : Registers_Index;
1272 Mask_Unset : Word32;
1273 Mask_Set : Word32);
1274
1275 pragma Warnings (Off, "declaration of ""Write_GTT"" hides one at *");
1276 procedure Write_GTT
1277 (GTT_Page : GTT_Range;
1278 Device_Address : GTT_Address_Type;
1279 Valid : Boolean)
1280 with
1281 Global => (In_Out => GTT_State),
1282 Depends => (GTT_State =>+ (GTT_Page, Device_Address, Valid)),
1283 Pre => True,
1284 Post => True;
1285 pragma Warnings (On, "declaration of ""Write_GTT"" hides one at *");
1286
1287 procedure Set_Register_Base (Base : Word64)
1288 with
1289 Global => (Output => Address_State),
1290 Depends => (Address_State => Base),
1291 Pre => True,
1292 Post => True;
1293
1294end HW.GFX.GMA.Registers;