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review.sourcearcade.org / libgfxinit / 18ff0c13b740f4153f39dfeb5b9af474bfa13e0a / . / common / hw-gfx-gma-registers.ads
blob: ef257705e94e9121bc1bb551dae29bc3616081cb [file] [log] [blame]
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1--
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]2-- Copyright (C) 2015-2017 secunet Security Networks AG
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]3--
4-- This program is free software; you can redistribute it and/or modify
5-- it under the terms of the GNU General Public License as published by
Nico Huber125a29e2016-10-18 00:23:54 +0200[diff] [blame]6-- the Free Software Foundation; either version 2 of the License, or
7-- (at your option) any later version.
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]8--
9-- This program is distributed in the hope that it will be useful,
10-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12-- GNU General Public License for more details.
13--
14
15with System;
16with HW.GFX.GMA;
17with HW.GFX.GMA.Config;
18
19private package HW.GFX.GMA.Registers
20with
21 Abstract_State =>
22 ((Address_State with Part_Of => GMA.State),
23 (Register_State with External, Part_Of => GMA.Device_State),
24 (GTT_State with External, Part_Of => GMA.Device_State)),
25 Initializes => Address_State
26is
27 type Registers_Invalid_Index is
28 (Invalid_Register, -- Allow a placeholder when access is not acceptable
29
30 RCS_RING_BUFFER_TAIL,
31 RCS_RING_BUFFER_HEAD,
32 RCS_RING_BUFFER_STRT,
33 RCS_RING_BUFFER_CTL,
34 QUIRK_02084,
35 QUIRK_02090,
36 HWSTAM,
37 MI_MODE,
38 INSTPM,
39 GT_MODE,
40 CACHE_MODE_0,
41 CTX_SIZE,
42 PP_DCLV_HIGH,
43 PP_DCLV_LOW,
44 GFX_MODE,
45 ARB_MODE,
46 HWS_PGA,
47 GAM_ECOCHK,
48 MBCTL,
49 UCGCTL1,
50 UCGCTL2,
51 VCS_RING_BUFFER_TAIL,
52 VCS_RING_BUFFER_HEAD,
53 VCS_RING_BUFFER_STRT,
54 VCS_RING_BUFFER_CTL,
55 SLEEP_PSMI_CONTROL,
56 VCS_HWSTAM,
57 VCS_PP_DCLV_HIGH,
58 VCS_PP_DCLV_LOW,
59 GAC_ECO_BITS,
60 BCS_RING_BUFFER_TAIL,
61 BCS_RING_BUFFER_HEAD,
62 BCS_RING_BUFFER_STRT,
63 BCS_RING_BUFFER_CTL,
64 BCS_HWSTAM,
65 BCS_PP_DCLV_HIGH,
66 BCS_PP_DCLV_LOW,
67 GAB_CTL_REG,
68 VGACNTRL,
69 FUSE_STATUS,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]70 ILK_DISPLAY_CHICKEN2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]71 DSPCLK_GATE_D,
72 FBA_CFB_BASE,
73 FBC_CTL,
74 IPS_CTL,
75 DEISR,
76 DEIMR,
77 DEIIR,
78 DEIER,
79 GTISR,
80 GTIMR,
81 GTIIR,
82 GTIER,
83 IIR,
84 HOTPLUG_CTL,
85 ARB_CTL,
86 DBUF_CTL,
87 WM_PIPE_A,
88 WM_PIPE_B,
89 WM1_LP_ILK,
90 WM2_LP_ILK,
91 WM3_LP_ILK,
92 WM_PIPE_C,
93 WM_LINETIME_A,
94 WM_LINETIME_B,
95 WM_LINETIME_C,
96 PWR_WELL_CTL_BIOS,
97 PWR_WELL_CTL_DRIVER,
98 PWR_WELL_CTL_KVMR,
99 PWR_WELL_CTL_DEBUG,
100 PWR_WELL_CTL5,
101 PWR_WELL_CTL6,
102 CDCLK_CTL,
103 LCPLL1_CTL,
104 LCPLL2_CTL,
105 SPLL_CTL,
106 WRPLL_CTL_1,
107 WRPLL_CTL_2,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]108 BXT_DE_PLL_ENABLE,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]109 BXT_PORT_PLL_ENABLE_A,
110 BXT_PORT_PLL_ENABLE_B,
111 BXT_PORT_PLL_ENABLE_C,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]112 PORT_CLK_SEL_DDIA,
113 PORT_CLK_SEL_DDIB,
114 PORT_CLK_SEL_DDIC,
115 PORT_CLK_SEL_DDID,
116 PORT_CLK_SEL_DDIE,
117 TRANSA_CLK_SEL,
118 TRANSB_CLK_SEL,
119 TRANSC_CLK_SEL,
120 NDE_RSTWRN_OPT,
121 BLC_PWM_CPU_CTL2,
122 BLC_PWM_CPU_CTL,
123 HTOTAL_A,
124 HBLANK_A,
125 HSYNC_A,
126 VTOTAL_A,
127 VBLANK_A,
128 VSYNC_A,
129 PIPEASRC,
130 PIPE_VSYNCSHIFT_A,
131 PIPEA_DATA_M1,
132 PIPEA_DATA_N1,
133 PIPEA_LINK_M1,
134 PIPEA_LINK_N1,
135 FDI_TX_CTL_A,
136 PIPEA_DDI_FUNC_CTL,
137 PIPEA_MSA_MISC,
138 SRD_CTL_A,
139 SRD_STATUS_A,
140 HTOTAL_B,
141 HBLANK_B,
142 HSYNC_B,
143 VTOTAL_B,
144 VBLANK_B,
145 VSYNC_B,
146 PIPEBSRC,
147 PIPE_VSYNCSHIFT_B,
148 PIPEB_DATA_M1,
149 PIPEB_DATA_N1,
150 PIPEB_LINK_M1,
151 PIPEB_LINK_N1,
152 FDI_TX_CTL_B,
153 PIPEB_DDI_FUNC_CTL,
154 PIPEB_MSA_MISC,
155 SRD_CTL_B,
156 SRD_STATUS_B,
157 HTOTAL_C,
158 HBLANK_C,
159 HSYNC_C,
160 VTOTAL_C,
161 VBLANK_C,
162 VSYNC_C,
163 PIPECSRC,
164 PIPE_VSYNCSHIFT_C,
165 PIPEC_DATA_M1,
166 PIPEC_DATA_N1,
167 PIPEC_LINK_M1,
168 PIPEC_LINK_N1,
169 FDI_TX_CTL_C,
170 PIPEC_DDI_FUNC_CTL,
171 PIPEC_MSA_MISC,
172 SRD_CTL_C,
173 SRD_STATUS_C,
174 DDI_BUF_CTL_A,
175 DDI_AUX_CTL_A,
176 DDI_AUX_DATA_A_1,
177 DDI_AUX_DATA_A_2,
178 DDI_AUX_DATA_A_3,
179 DDI_AUX_DATA_A_4,
180 DDI_AUX_DATA_A_5,
181 DDI_AUX_MUTEX_A,
182 DP_TP_CTL_A,
183 DDI_BUF_CTL_B,
184 DDI_AUX_CTL_B,
185 DDI_AUX_DATA_B_1,
186 DDI_AUX_DATA_B_2,
187 DDI_AUX_DATA_B_3,
188 DDI_AUX_DATA_B_4,
189 DDI_AUX_DATA_B_5,
190 DDI_AUX_MUTEX_B,
191 DP_TP_CTL_B,
192 DP_TP_STATUS_B,
193 DDI_BUF_CTL_C,
194 DDI_AUX_CTL_C,
195 DDI_AUX_DATA_C_1,
196 DDI_AUX_DATA_C_2,
197 DDI_AUX_DATA_C_3,
198 DDI_AUX_DATA_C_4,
199 DDI_AUX_DATA_C_5,
200 DDI_AUX_MUTEX_C,
201 DP_TP_CTL_C,
202 DP_TP_STATUS_C,
203 DDI_BUF_CTL_D,
204 DDI_AUX_CTL_D,
205 DDI_AUX_DATA_D_1,
206 DDI_AUX_DATA_D_2,
207 DDI_AUX_DATA_D_3,
208 DDI_AUX_DATA_D_4,
209 DDI_AUX_DATA_D_5,
210 DDI_AUX_MUTEX_D,
211 DP_TP_CTL_D,
212 DP_TP_STATUS_D,
213 DDI_BUF_CTL_E,
214 DP_TP_CTL_E,
215 DP_TP_STATUS_E,
216 SRD_CTL,
217 SRD_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]218 BXT_PHY_CTL_A,
219 BXT_PHY_CTL_B,
220 BXT_PHY_CTL_C,
221 BXT_PHY_CTL_FAM_EDP,
222 BXT_PHY_CTL_FAM_DDI,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]223 DDI_BUF_TRANS_A_S0T1,
224 DDI_BUF_TRANS_A_S0T2,
225 DDI_BUF_TRANS_A_S1T1,
226 DDI_BUF_TRANS_A_S1T2,
227 DDI_BUF_TRANS_A_S2T1,
228 DDI_BUF_TRANS_A_S2T2,
229 DDI_BUF_TRANS_A_S3T1,
230 DDI_BUF_TRANS_A_S3T2,
231 DDI_BUF_TRANS_A_S4T1,
232 DDI_BUF_TRANS_A_S4T2,
233 DDI_BUF_TRANS_A_S5T1,
234 DDI_BUF_TRANS_A_S5T2,
235 DDI_BUF_TRANS_A_S6T1,
236 DDI_BUF_TRANS_A_S6T2,
237 DDI_BUF_TRANS_A_S7T1,
238 DDI_BUF_TRANS_A_S7T2,
239 DDI_BUF_TRANS_A_S8T1,
240 DDI_BUF_TRANS_A_S8T2,
241 DDI_BUF_TRANS_A_S9T1,
242 DDI_BUF_TRANS_A_S9T2,
243 DDI_BUF_TRANS_B_S0T1,
244 DDI_BUF_TRANS_B_S0T2,
245 DDI_BUF_TRANS_B_S1T1,
246 DDI_BUF_TRANS_B_S1T2,
247 DDI_BUF_TRANS_B_S2T1,
248 DDI_BUF_TRANS_B_S2T2,
249 DDI_BUF_TRANS_B_S3T1,
250 DDI_BUF_TRANS_B_S3T2,
251 DDI_BUF_TRANS_B_S4T1,
252 DDI_BUF_TRANS_B_S4T2,
253 DDI_BUF_TRANS_B_S5T1,
254 DDI_BUF_TRANS_B_S5T2,
255 DDI_BUF_TRANS_B_S6T1,
256 DDI_BUF_TRANS_B_S6T2,
257 DDI_BUF_TRANS_B_S7T1,
258 DDI_BUF_TRANS_B_S7T2,
259 DDI_BUF_TRANS_B_S8T1,
260 DDI_BUF_TRANS_B_S8T2,
261 DDI_BUF_TRANS_B_S9T1,
262 DDI_BUF_TRANS_B_S9T2,
263 DDI_BUF_TRANS_C_S0T1,
264 DDI_BUF_TRANS_C_S0T2,
265 DDI_BUF_TRANS_C_S1T1,
266 DDI_BUF_TRANS_C_S1T2,
267 DDI_BUF_TRANS_C_S2T1,
268 DDI_BUF_TRANS_C_S2T2,
269 DDI_BUF_TRANS_C_S3T1,
270 DDI_BUF_TRANS_C_S3T2,
271 DDI_BUF_TRANS_C_S4T1,
272 DDI_BUF_TRANS_C_S4T2,
273 DDI_BUF_TRANS_C_S5T1,
274 DDI_BUF_TRANS_C_S5T2,
275 DDI_BUF_TRANS_C_S6T1,
276 DDI_BUF_TRANS_C_S6T2,
277 DDI_BUF_TRANS_C_S7T1,
278 DDI_BUF_TRANS_C_S7T2,
279 DDI_BUF_TRANS_C_S8T1,
280 DDI_BUF_TRANS_C_S8T2,
281 DDI_BUF_TRANS_C_S9T1,
282 DDI_BUF_TRANS_C_S9T2,
283 DDI_BUF_TRANS_D_S0T1,
284 DDI_BUF_TRANS_D_S0T2,
285 DDI_BUF_TRANS_D_S1T1,
286 DDI_BUF_TRANS_D_S1T2,
287 DDI_BUF_TRANS_D_S2T1,
288 DDI_BUF_TRANS_D_S2T2,
289 DDI_BUF_TRANS_D_S3T1,
290 DDI_BUF_TRANS_D_S3T2,
291 DDI_BUF_TRANS_D_S4T1,
292 DDI_BUF_TRANS_D_S4T2,
293 DDI_BUF_TRANS_D_S5T1,
294 DDI_BUF_TRANS_D_S5T2,
295 DDI_BUF_TRANS_D_S6T1,
296 DDI_BUF_TRANS_D_S6T2,
297 DDI_BUF_TRANS_D_S7T1,
298 DDI_BUF_TRANS_D_S7T2,
299 DDI_BUF_TRANS_D_S8T1,
300 DDI_BUF_TRANS_D_S8T2,
301 DDI_BUF_TRANS_D_S9T1,
302 DDI_BUF_TRANS_D_S9T2,
303 DDI_BUF_TRANS_E_S0T1,
304 DDI_BUF_TRANS_E_S0T2,
305 DDI_BUF_TRANS_E_S1T1,
306 DDI_BUF_TRANS_E_S1T2,
307 DDI_BUF_TRANS_E_S2T1,
308 DDI_BUF_TRANS_E_S2T2,
309 DDI_BUF_TRANS_E_S3T1,
310 DDI_BUF_TRANS_E_S3T2,
311 DDI_BUF_TRANS_E_S4T1,
312 DDI_BUF_TRANS_E_S4T2,
313 DDI_BUF_TRANS_E_S5T1,
314 DDI_BUF_TRANS_E_S5T2,
315 DDI_BUF_TRANS_E_S6T1,
316 DDI_BUF_TRANS_E_S6T2,
317 DDI_BUF_TRANS_E_S7T1,
318 DDI_BUF_TRANS_E_S7T2,
319 DDI_BUF_TRANS_E_S8T1,
320 DDI_BUF_TRANS_E_S8T2,
321 DDI_BUF_TRANS_E_S9T1,
322 DDI_BUF_TRANS_E_S9T2,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]323 AUD_VID_DID,
324 PFA_WIN_POS,
325 PFA_WIN_SZ,
326 PFA_CTL_1,
327 PS_WIN_POS_1_A,
328 PS_WIN_SZ_1_A,
329 PS_CTRL_1_A,
330 PS_WIN_POS_2_A,
331 PS_WIN_SZ_2_A,
332 PS_CTRL_2_A,
333 PFB_WIN_POS,
334 PFB_WIN_SZ,
335 PFB_CTL_1,
336 PS_WIN_POS_1_B,
337 PS_WIN_SZ_1_B,
338 PS_CTRL_1_B,
339 PS_WIN_POS_2_B,
340 PS_WIN_SZ_2_B,
341 PS_CTRL_2_B,
342 PFC_WIN_POS,
343 PFC_WIN_SZ,
344 PFC_CTL_1,
345 PS_WIN_POS_1_C,
346 PS_WIN_SZ_1_C,
347 PS_CTRL_1_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]348 BXT_PORT_CL1CM_DW0_BC,
349 BXT_PORT_CL1CM_DW9_BC,
350 BXT_PORT_CL1CM_DW10_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]351 BXT_PORT_PLL_EBB_0_B,
352 BXT_PORT_PLL_EBB_4_B,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]353 DPLL1_CFGR1,
354 DPLL1_CFGR2,
355 DPLL2_CFGR1,
356 DPLL2_CFGR2,
357 DPLL3_CFGR1,
358 DPLL3_CFGR2,
359 DPLL_CTRL1,
360 DPLL_CTRL2,
361 DPLL_STATUS,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]362 BXT_PORT_CL1CM_DW28_BC,
363 BXT_PORT_CL1CM_DW30_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]364 BXT_PORT_PLL_0_B,
365 BXT_PORT_PLL_1_B,
366 BXT_PORT_PLL_2_B,
367 BXT_PORT_PLL_3_B,
368 BXT_PORT_PLL_6_B,
369 BXT_PORT_PLL_8_B,
370 BXT_PORT_PLL_9_B,
371 BXT_PORT_PLL_10_B,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]372 BXT_PORT_REF_DW3_BC,
373 BXT_PORT_REF_DW6_BC,
374 BXT_PORT_REF_DW8_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]375 BXT_PORT_PLL_EBB_0_C,
376 BXT_PORT_PLL_EBB_4_C,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]377 BXT_PORT_CL2CM_DW6_BC,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]378 BXT_PORT_PLL_0_C,
379 BXT_PORT_PLL_1_C,
380 BXT_PORT_PLL_2_C,
381 BXT_PORT_PLL_3_C,
382 BXT_PORT_PLL_6_C,
383 BXT_PORT_PLL_8_C,
384 BXT_PORT_PLL_9_C,
385 BXT_PORT_PLL_10_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]386 BXT_PORT_PCS_DW10_01_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]387 BXT_PORT_PCS_DW12_01_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]388 BXT_PORT_TX_DW2_LN0_B,
389 BXT_PORT_TX_DW3_LN0_B,
390 BXT_PORT_TX_DW4_LN0_B,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]391 BXT_PORT_TX_DW14_LN0_B,
392 BXT_PORT_TX_DW14_LN1_B,
393 BXT_PORT_TX_DW14_LN2_B,
394 BXT_PORT_TX_DW14_LN3_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]395 BXT_PORT_PCS_DW10_01_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]396 BXT_PORT_PCS_DW12_01_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]397 BXT_PORT_TX_DW2_LN0_C,
398 BXT_PORT_TX_DW3_LN0_C,
399 BXT_PORT_TX_DW4_LN0_C,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]400 BXT_PORT_TX_DW14_LN0_C,
401 BXT_PORT_TX_DW14_LN1_C,
402 BXT_PORT_TX_DW14_LN2_C,
403 BXT_PORT_TX_DW14_LN3_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]404 BXT_PORT_PCS_DW10_GRP_B,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]405 BXT_PORT_PCS_DW12_GRP_B,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]406 BXT_PORT_TX_DW2_GRP_B,
407 BXT_PORT_TX_DW3_GRP_B,
408 BXT_PORT_TX_DW4_GRP_B,
409 BXT_PORT_PCS_DW10_GRP_C,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]410 BXT_PORT_PCS_DW12_GRP_C,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]411 BXT_PORT_TX_DW2_GRP_C,
412 BXT_PORT_TX_DW3_GRP_C,
413 BXT_PORT_TX_DW4_GRP_C,
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]414 BXT_DE_PLL_CTL,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]415 HTOTAL_EDP,
416 HBLANK_EDP,
417 HSYNC_EDP,
418 VTOTAL_EDP,
419 VBLANK_EDP,
420 VSYNC_EDP,
421 PIPE_EDP_DATA_M1,
422 PIPE_EDP_DATA_N1,
423 PIPE_EDP_LINK_M1,
424 PIPE_EDP_LINK_N1,
425 PIPE_EDP_DDI_FUNC_CTL,
426 PIPE_EDP_MSA_MISC,
427 SRD_CTL_EDP,
428 SRD_STATUS_EDP,
429 PIPE_SCANLINE_A,
430 PIPEACONF,
431 PIPEAMISC,
432 PIPE_FRMCNT_A,
433 DSPACNTR,
434 DSPALINOFF,
435 DSPASTRIDE,
436 PLANE_POS_1_A,
437 PLANE_SIZE_1_A,
438 DSPASURF,
439 DSPATILEOFF,
440 PLANE_WM_1_A_0,
441 PLANE_WM_1_A_1,
442 PLANE_WM_1_A_2,
443 PLANE_WM_1_A_3,
444 PLANE_WM_1_A_4,
445 PLANE_WM_1_A_5,
446 PLANE_WM_1_A_6,
447 PLANE_WM_1_A_7,
448 PLANE_BUF_CFG_1_A,
449 SPACNTR,
450 PIPE_SCANLINE_B,
451 PIPEBCONF,
452 PIPEBMISC,
453 PIPE_FRMCNT_B,
454 DSPBCNTR,
455 DSPBLINOFF,
456 DSPBSTRIDE,
457 PLANE_POS_1_B,
458 PLANE_SIZE_1_B,
459 DSPBSURF,
460 DSPBTILEOFF,
461 PLANE_WM_1_B_0,
462 PLANE_WM_1_B_1,
463 PLANE_WM_1_B_2,
464 PLANE_WM_1_B_3,
465 PLANE_WM_1_B_4,
466 PLANE_WM_1_B_5,
467 PLANE_WM_1_B_6,
468 PLANE_WM_1_B_7,
469 PLANE_BUF_CFG_1_B,
470 SPBCNTR,
471 PIPE_SCANLINE_C,
472 PIPECCONF,
473 PIPECMISC,
474 PIPE_FRMCNT_C,
475 DSPCCNTR,
476 DSPCLINOFF,
477 DSPCSTRIDE,
478 PLANE_POS_1_C,
479 PLANE_SIZE_1_C,
480 DSPCSURF,
481 DSPCTILEOFF,
482 PLANE_WM_1_C_0,
483 PLANE_WM_1_C_1,
484 PLANE_WM_1_C_2,
485 PLANE_WM_1_C_3,
486 PLANE_WM_1_C_4,
487 PLANE_WM_1_C_5,
488 PLANE_WM_1_C_6,
489 PLANE_WM_1_C_7,
490 PLANE_BUF_CFG_1_C,
491 SPCCNTR,
492 PIPE_EDP_CONF,
493 PCH_FDI_CHICKEN_B_C,
494 QUIRK_C2004,
495 SFUSE_STRAP,
496 PCH_DSPCLK_GATE_D,
497 SDEISR,
498 SDEIMR,
499 SDEIIR,
500 SDEIER,
501 SHOTPLUG_CTL,
502 PCH_GMBUS0,
503 PCH_GMBUS1,
504 PCH_GMBUS2,
505 PCH_GMBUS3,
506 PCH_GMBUS4,
507 PCH_GMBUS5,
508 SBI_ADDR,
509 SBI_DATA,
510 SBI_CTL_STAT,
511 PCH_DPLL_A,
512 PCH_DPLL_B,
513 PCH_PIXCLK_GATE,
514 PCH_FPA0,
515 PCH_FPA1,
516 PCH_FPB0,
517 PCH_FPB1,
518 PCH_DREF_CONTROL,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]519 PCH_RAWCLK_FREQ,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]520 PCH_DPLL_SEL,
521 PCH_PP_STATUS,
522 PCH_PP_CONTROL,
523 PCH_PP_ON_DELAYS,
524 PCH_PP_OFF_DELAYS,
525 PCH_PP_DIVISOR,
526 BLC_PWM_PCH_CTL1,
527 BLC_PWM_PCH_CTL2,
528 TRANS_HTOTAL_A,
529 TRANS_HBLANK_A,
530 TRANS_HSYNC_A,
531 TRANS_VTOTAL_A,
532 TRANS_VBLANK_A,
533 TRANS_VSYNC_A,
534 TRANS_VSYNCSHIFT_A,
535 TRANSA_DATA_M1,
536 TRANSA_DATA_N1,
537 TRANSA_DP_LINK_M1,
538 TRANSA_DP_LINK_N1,
539 TRANS_DP_CTL_A,
540 TRANS_HTOTAL_B,
541 TRANS_HBLANK_B,
542 TRANS_HSYNC_B,
543 TRANS_VTOTAL_B,
544 TRANS_VBLANK_B,
545 TRANS_VSYNC_B,
546 TRANS_VSYNCSHIFT_B,
547 TRANSB_DATA_M1,
548 TRANSB_DATA_N1,
549 TRANSB_DP_LINK_M1,
550 TRANSB_DP_LINK_N1,
551 PCH_ADPA,
552 PCH_HDMIB,
553 PCH_HDMIC,
554 PCH_HDMID,
555 PCH_LVDS,
556 TRANS_DP_CTL_B,
557 TRANS_HTOTAL_C,
558 TRANS_HBLANK_C,
559 TRANS_HSYNC_C,
560 TRANS_VTOTAL_C,
561 TRANS_VBLANK_C,
562 TRANS_VSYNC_C,
563 TRANS_VSYNCSHIFT_C,
564 TRANSC_DATA_M1,
565 TRANSC_DATA_N1,
566 TRANSC_DP_LINK_M1,
567 TRANSC_DP_LINK_N1,
568 TRANS_DP_CTL_C,
569 PCH_DP_B,
570 PCH_DP_AUX_CTL_B,
571 PCH_DP_AUX_DATA_B_1,
572 PCH_DP_AUX_DATA_B_2,
573 PCH_DP_AUX_DATA_B_3,
574 PCH_DP_AUX_DATA_B_4,
575 PCH_DP_AUX_DATA_B_5,
576 PCH_DP_C,
577 PCH_DP_AUX_CTL_C,
578 PCH_DP_AUX_DATA_C_1,
579 PCH_DP_AUX_DATA_C_2,
580 PCH_DP_AUX_DATA_C_3,
581 PCH_DP_AUX_DATA_C_4,
582 PCH_DP_AUX_DATA_C_5,
583 PCH_DP_D,
584 PCH_DP_AUX_CTL_D,
585 PCH_DP_AUX_DATA_D_1,
586 PCH_DP_AUX_DATA_D_2,
587 PCH_DP_AUX_DATA_D_3,
588 PCH_DP_AUX_DATA_D_4,
589 PCH_DP_AUX_DATA_D_5,
590 AUD_CONFIG_A,
591 PCH_AUD_VID_DID,
592 AUD_HDMIW_HDMIEDID_A,
593 AUD_CNTL_ST_A,
594 AUD_CNTRL_ST2,
595 AUD_CONFIG_B,
596 AUD_HDMIW_HDMIEDID_B,
597 AUD_CNTL_ST_B,
598 AUD_CONFIG_C,
599 AUD_HDMIW_HDMIEDID_C,
600 AUD_CNTL_ST_C,
601 TRANSACONF,
602 FDI_RXA_CTL,
603 FDI_RX_MISC_A,
604 FDI_RXA_IIR,
605 FDI_RXA_IMR,
606 FDI_RXA_TUSIZE1,
607 QUIRK_F0060,
608 TRANSA_CHICKEN2,
609 TRANSBCONF,
610 FDI_RXB_CTL,
611 FDI_RX_MISC_B,
612 FDI_RXB_IIR,
613 FDI_RXB_IMR,
614 FDI_RXB_TUSIZE1,
615 QUIRK_F1060,
616 TRANSB_CHICKEN2,
617 TRANSCCONF,
618 FDI_RXC_CTL,
619 FDI_RX_MISC_C,
620 FDI_RXC_IIR,
621 FDI_RXC_IMR,
622 FDI_RXC_TUSIZE1,
623 QUIRK_F2060,
624 TRANSC_CHICKEN2,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]625 BXT_P_CR_GT_DISP_PWRON,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]626 GT_MAILBOX,
627 GT_MAILBOX_DATA,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]628 GT_MAILBOX_DATA_1,
629 BXT_PORT_CL1CM_DW0_A,
630 BXT_PORT_CL1CM_DW9_A,
631 BXT_PORT_CL1CM_DW10_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]632 BXT_PORT_PLL_EBB_0_A,
633 BXT_PORT_PLL_EBB_4_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]634 BXT_PORT_CL1CM_DW28_A,
635 BXT_PORT_CL1CM_DW30_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]636 BXT_PORT_PLL_0_A,
637 BXT_PORT_PLL_1_A,
638 BXT_PORT_PLL_2_A,
639 BXT_PORT_PLL_3_A,
640 BXT_PORT_PLL_6_A,
641 BXT_PORT_PLL_8_A,
642 BXT_PORT_PLL_9_A,
643 BXT_PORT_PLL_10_A,
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]644 BXT_PORT_REF_DW3_A,
645 BXT_PORT_REF_DW6_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]646 BXT_PORT_REF_DW8_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]647 BXT_PORT_PCS_DW10_01_A,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]648 BXT_PORT_PCS_DW12_01_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]649 BXT_PORT_TX_DW2_LN0_A,
650 BXT_PORT_TX_DW3_LN0_A,
651 BXT_PORT_TX_DW4_LN0_A,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]652 BXT_PORT_TX_DW14_LN0_A,
653 BXT_PORT_TX_DW14_LN1_A,
654 BXT_PORT_TX_DW14_LN2_A,
655 BXT_PORT_TX_DW14_LN3_A,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]656 BXT_PORT_PCS_DW10_GRP_A,
657 BXT_PORT_PCS_DW12_GRP_A,
658 BXT_PORT_TX_DW2_GRP_A,
659 BXT_PORT_TX_DW3_GRP_A,
660 BXT_PORT_TX_DW4_GRP_A);
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]661
662 pragma Warnings
663 (GNATprove, Off, "pragma ""KEEP_NAMES"" ignored *(not yet supported)",
664 Reason => "TODO: Should it matter?");
665 pragma Keep_Names (Registers_Invalid_Index);
666 pragma Warnings
667 (GNATprove, On, "pragma ""KEEP_NAMES"" ignored *(not yet supported)");
668
669 Register_Width : constant := 4;
670
671 for Registers_Invalid_Index use
672 (Invalid_Register => 0,
673
674 ---------------------------------------------------------------------------
675 -- Pipe A registers
676 ---------------------------------------------------------------------------
677
678 -- pipe timing registers
679
680 HTOTAL_A => 16#06_0000# / Register_Width,
681 HBLANK_A => 16#06_0004# / Register_Width,
682 HSYNC_A => 16#06_0008# / Register_Width,
683 VTOTAL_A => 16#06_000c# / Register_Width,
684 VBLANK_A => 16#06_0010# / Register_Width,
685 VSYNC_A => 16#06_0014# / Register_Width,
686 PIPEASRC => 16#06_001c# / Register_Width,
687 PIPEACONF => 16#07_0008# / Register_Width,
688 PIPEAMISC => 16#07_0030# / Register_Width,
689 TRANS_HTOTAL_A => 16#0e_0000# / Register_Width,
690 TRANS_HBLANK_A => 16#0e_0004# / Register_Width,
691 TRANS_HSYNC_A => 16#0e_0008# / Register_Width,
692 TRANS_VTOTAL_A => 16#0e_000c# / Register_Width,
693 TRANS_VBLANK_A => 16#0e_0010# / Register_Width,
694 TRANS_VSYNC_A => 16#0e_0014# / Register_Width,
695 TRANSA_DATA_M1 => 16#0e_0030# / Register_Width,
696 TRANSA_DATA_N1 => 16#0e_0034# / Register_Width,
697 TRANSA_DP_LINK_M1 => 16#0e_0040# / Register_Width,
698 TRANSA_DP_LINK_N1 => 16#0e_0044# / Register_Width,
699 PIPEA_DATA_M1 => 16#06_0030# / Register_Width,
700 PIPEA_DATA_N1 => 16#06_0034# / Register_Width,
701 PIPEA_LINK_M1 => 16#06_0040# / Register_Width,
702 PIPEA_LINK_N1 => 16#06_0044# / Register_Width,
703 PIPEA_DDI_FUNC_CTL => 16#06_0400# / Register_Width,
704 PIPEA_MSA_MISC => 16#06_0410# / Register_Width,
705
706 -- PCH sideband interface registers
707 SBI_ADDR => 16#0c_6000# / Register_Width,
708 SBI_DATA => 16#0c_6004# / Register_Width,
709 SBI_CTL_STAT => 16#0c_6008# / Register_Width,
710
711 -- clock registers
712 PCH_DPLL_A => 16#0c_6014# / Register_Width,
713 PCH_PIXCLK_GATE => 16#0c_6020# / Register_Width,
714 PCH_FPA0 => 16#0c_6040# / Register_Width,
715 PCH_FPA1 => 16#0c_6044# / Register_Width,
716
717 -- panel fitter
718 PFA_CTL_1 => 16#06_8080# / Register_Width,
719 PFA_WIN_POS => 16#06_8070# / Register_Width,
720 PFA_WIN_SZ => 16#06_8074# / Register_Width,
721 PS_WIN_POS_1_A => 16#06_8170# / Register_Width,
722 PS_WIN_SZ_1_A => 16#06_8174# / Register_Width,
723 PS_CTRL_1_A => 16#06_8180# / Register_Width,
724 PS_WIN_POS_2_A => 16#06_8270# / Register_Width,
725 PS_WIN_SZ_2_A => 16#06_8274# / Register_Width,
726 PS_CTRL_2_A => 16#06_8280# / Register_Width,
727
728 -- display control
729 DSPACNTR => 16#07_0180# / Register_Width,
730 DSPALINOFF => 16#07_0184# / Register_Width,
731 DSPASTRIDE => 16#07_0188# / Register_Width,
732 PLANE_POS_1_A => 16#07_018c# / Register_Width,
733 PLANE_SIZE_1_A => 16#07_0190# / Register_Width,
734 DSPASURF => 16#07_019c# / Register_Width,
735 DSPATILEOFF => 16#07_01a4# / Register_Width,
736
737 -- sprite control
738 SPACNTR => 16#07_0280# / Register_Width,
739
740 -- FDI and PCH transcoder control
741 FDI_TX_CTL_A => 16#06_0100# / Register_Width,
742 FDI_RXA_CTL => 16#0f_000c# / Register_Width,
743 FDI_RX_MISC_A => 16#0f_0010# / Register_Width,
744 FDI_RXA_IIR => 16#0f_0014# / Register_Width,
745 FDI_RXA_IMR => 16#0f_0018# / Register_Width,
746 FDI_RXA_TUSIZE1 => 16#0f_0030# / Register_Width,
747 TRANSACONF => 16#0f_0008# / Register_Width,
748 TRANSA_CHICKEN2 => 16#0f_0064# / Register_Width,
749
750 -- watermark registers
751 WM_LINETIME_A => 16#04_5270# / Register_Width,
752 PLANE_WM_1_A_0 => 16#07_0240# / Register_Width,
753 PLANE_WM_1_A_1 => 16#07_0244# / Register_Width,
754 PLANE_WM_1_A_2 => 16#07_0248# / Register_Width,
755 PLANE_WM_1_A_3 => 16#07_024c# / Register_Width,
756 PLANE_WM_1_A_4 => 16#07_0250# / Register_Width,
757 PLANE_WM_1_A_5 => 16#07_0254# / Register_Width,
758 PLANE_WM_1_A_6 => 16#07_0258# / Register_Width,
759 PLANE_WM_1_A_7 => 16#07_025c# / Register_Width,
760 PLANE_BUF_CFG_1_A => 16#07_027c# / Register_Width,
761
762 -- CPU transcoder clock select
763 TRANSA_CLK_SEL => 16#04_6140# / Register_Width,
764
765 ---------------------------------------------------------------------------
766 -- Pipe B registers
767 ---------------------------------------------------------------------------
768
769 -- pipe timing registers
770
771 HTOTAL_B => 16#06_1000# / Register_Width,
772 HBLANK_B => 16#06_1004# / Register_Width,
773 HSYNC_B => 16#06_1008# / Register_Width,
774 VTOTAL_B => 16#06_100c# / Register_Width,
775 VBLANK_B => 16#06_1010# / Register_Width,
776 VSYNC_B => 16#06_1014# / Register_Width,
777 PIPEBSRC => 16#06_101c# / Register_Width,
778 PIPEBCONF => 16#07_1008# / Register_Width,
779 PIPEBMISC => 16#07_1030# / Register_Width,
780 TRANS_HTOTAL_B => 16#0e_1000# / Register_Width,
781 TRANS_HBLANK_B => 16#0e_1004# / Register_Width,
782 TRANS_HSYNC_B => 16#0e_1008# / Register_Width,
783 TRANS_VTOTAL_B => 16#0e_100c# / Register_Width,
784 TRANS_VBLANK_B => 16#0e_1010# / Register_Width,
785 TRANS_VSYNC_B => 16#0e_1014# / Register_Width,
786 TRANSB_DATA_M1 => 16#0e_1030# / Register_Width,
787 TRANSB_DATA_N1 => 16#0e_1034# / Register_Width,
788 TRANSB_DP_LINK_M1 => 16#0e_1040# / Register_Width,
789 TRANSB_DP_LINK_N1 => 16#0e_1044# / Register_Width,
790 PIPEB_DATA_M1 => 16#06_1030# / Register_Width,
791 PIPEB_DATA_N1 => 16#06_1034# / Register_Width,
792 PIPEB_LINK_M1 => 16#06_1040# / Register_Width,
793 PIPEB_LINK_N1 => 16#06_1044# / Register_Width,
794 PIPEB_DDI_FUNC_CTL => 16#06_1400# / Register_Width,
795 PIPEB_MSA_MISC => 16#06_1410# / Register_Width,
796
797 -- clock registers
798 PCH_DPLL_B => 16#0c_6018# / Register_Width,
799 PCH_FPB0 => 16#0c_6048# / Register_Width,
800 PCH_FPB1 => 16#0c_604c# / Register_Width,
801
802 -- panel fitter
803 PFB_CTL_1 => 16#06_8880# / Register_Width,
804 PFB_WIN_POS => 16#06_8870# / Register_Width,
805 PFB_WIN_SZ => 16#06_8874# / Register_Width,
806 PS_WIN_POS_1_B => 16#06_8970# / Register_Width,
807 PS_WIN_SZ_1_B => 16#06_8974# / Register_Width,
808 PS_CTRL_1_B => 16#06_8980# / Register_Width,
809 PS_WIN_POS_2_B => 16#06_8a70# / Register_Width,
810 PS_WIN_SZ_2_B => 16#06_8a74# / Register_Width,
811 PS_CTRL_2_B => 16#06_8a80# / Register_Width,
812
813 -- display control
814 DSPBCNTR => 16#07_1180# / Register_Width,
815 DSPBLINOFF => 16#07_1184# / Register_Width,
816 DSPBSTRIDE => 16#07_1188# / Register_Width,
817 PLANE_POS_1_B => 16#07_118c# / Register_Width,
818 PLANE_SIZE_1_B => 16#07_1190# / Register_Width,
819 DSPBSURF => 16#07_119c# / Register_Width,
820 DSPBTILEOFF => 16#07_11a4# / Register_Width,
821
822 -- sprite control
823 SPBCNTR => 16#07_1280# / Register_Width,
824
825 -- FDI and PCH transcoder control
826 FDI_TX_CTL_B => 16#06_1100# / Register_Width,
827 FDI_RXB_CTL => 16#0f_100c# / Register_Width,
828 FDI_RX_MISC_B => 16#0f_1010# / Register_Width,
829 FDI_RXB_IIR => 16#0f_1014# / Register_Width,
830 FDI_RXB_IMR => 16#0f_1018# / Register_Width,
831 FDI_RXB_TUSIZE1 => 16#0f_1030# / Register_Width,
832 TRANSBCONF => 16#0f_1008# / Register_Width,
833 TRANSB_CHICKEN2 => 16#0f_1064# / Register_Width,
834
835 -- watermark registers
836 WM_LINETIME_B => 16#04_5274# / Register_Width,
837 PLANE_WM_1_B_0 => 16#07_1240# / Register_Width,
838 PLANE_WM_1_B_1 => 16#07_1244# / Register_Width,
839 PLANE_WM_1_B_2 => 16#07_1248# / Register_Width,
840 PLANE_WM_1_B_3 => 16#07_124c# / Register_Width,
841 PLANE_WM_1_B_4 => 16#07_1250# / Register_Width,
842 PLANE_WM_1_B_5 => 16#07_1254# / Register_Width,
843 PLANE_WM_1_B_6 => 16#07_1258# / Register_Width,
844 PLANE_WM_1_B_7 => 16#07_125c# / Register_Width,
845 PLANE_BUF_CFG_1_B => 16#07_127c# / Register_Width,
846
847 -- CPU transcoder clock select
848 TRANSB_CLK_SEL => 16#04_6144# / Register_Width,
849
850 ---------------------------------------------------------------------------
851 -- Pipe C registers
852 ---------------------------------------------------------------------------
853
854 -- pipe timing registers
855
856 HTOTAL_C => 16#06_2000# / Register_Width,
857 HBLANK_C => 16#06_2004# / Register_Width,
858 HSYNC_C => 16#06_2008# / Register_Width,
859 VTOTAL_C => 16#06_200c# / Register_Width,
860 VBLANK_C => 16#06_2010# / Register_Width,
861 VSYNC_C => 16#06_2014# / Register_Width,
862 PIPECSRC => 16#06_201c# / Register_Width,
863 PIPECCONF => 16#07_2008# / Register_Width,
864 PIPECMISC => 16#07_2030# / Register_Width,
865 TRANS_HTOTAL_C => 16#0e_2000# / Register_Width,
866 TRANS_HBLANK_C => 16#0e_2004# / Register_Width,
867 TRANS_HSYNC_C => 16#0e_2008# / Register_Width,
868 TRANS_VTOTAL_C => 16#0e_200c# / Register_Width,
869 TRANS_VBLANK_C => 16#0e_2010# / Register_Width,
870 TRANS_VSYNC_C => 16#0e_2014# / Register_Width,
871 TRANSC_DATA_M1 => 16#0e_2030# / Register_Width,
872 TRANSC_DATA_N1 => 16#0e_2034# / Register_Width,
873 TRANSC_DP_LINK_M1 => 16#0e_2040# / Register_Width,
874 TRANSC_DP_LINK_N1 => 16#0e_2044# / Register_Width,
875 PIPEC_DATA_M1 => 16#06_2030# / Register_Width,
876 PIPEC_DATA_N1 => 16#06_2034# / Register_Width,
877 PIPEC_LINK_M1 => 16#06_2040# / Register_Width,
878 PIPEC_LINK_N1 => 16#06_2044# / Register_Width,
879 PIPEC_DDI_FUNC_CTL => 16#06_2400# / Register_Width,
880 PIPEC_MSA_MISC => 16#06_2410# / Register_Width,
881
882 -- panel fitter
883 PFC_CTL_1 => 16#06_9080# / Register_Width,
884 PFC_WIN_POS => 16#06_9070# / Register_Width,
885 PFC_WIN_SZ => 16#06_9074# / Register_Width,
886 PS_WIN_POS_1_C => 16#06_9170# / Register_Width,
887 PS_WIN_SZ_1_C => 16#06_9174# / Register_Width,
888 PS_CTRL_1_C => 16#06_9180# / Register_Width,
889
890 -- display control
891 DSPCCNTR => 16#07_2180# / Register_Width,
892 DSPCLINOFF => 16#07_2184# / Register_Width,
893 DSPCSTRIDE => 16#07_2188# / Register_Width,
894 PLANE_POS_1_C => 16#07_218c# / Register_Width,
895 PLANE_SIZE_1_C => 16#07_2190# / Register_Width,
896 DSPCSURF => 16#07_219c# / Register_Width,
897 DSPCTILEOFF => 16#07_21a4# / Register_Width,
898
899 -- sprite control
900 SPCCNTR => 16#07_2280# / Register_Width,
901
902 -- PCH transcoder control
903 FDI_TX_CTL_C => 16#06_2100# / Register_Width,
904 FDI_RXC_CTL => 16#0f_200c# / Register_Width,
905 FDI_RX_MISC_C => 16#0f_2010# / Register_Width,
906 FDI_RXC_IIR => 16#0f_2014# / Register_Width,
907 FDI_RXC_IMR => 16#0f_2018# / Register_Width,
908 FDI_RXC_TUSIZE1 => 16#0f_2030# / Register_Width,
909 TRANSCCONF => 16#0f_2008# / Register_Width,
910 TRANSC_CHICKEN2 => 16#0f_2064# / Register_Width,
911
912 -- watermark registers
913 WM_LINETIME_C => 16#04_5278# / Register_Width,
914 PLANE_WM_1_C_0 => 16#07_2240# / Register_Width,
915 PLANE_WM_1_C_1 => 16#07_2244# / Register_Width,
916 PLANE_WM_1_C_2 => 16#07_2248# / Register_Width,
917 PLANE_WM_1_C_3 => 16#07_224c# / Register_Width,
918 PLANE_WM_1_C_4 => 16#07_2250# / Register_Width,
919 PLANE_WM_1_C_5 => 16#07_2254# / Register_Width,
920 PLANE_WM_1_C_6 => 16#07_2258# / Register_Width,
921 PLANE_WM_1_C_7 => 16#07_225c# / Register_Width,
922 PLANE_BUF_CFG_1_C => 16#07_227c# / Register_Width,
923
924 -- CPU transcoder clock select
925 TRANSC_CLK_SEL => 16#04_6148# / Register_Width,
926
927 ---------------------------------------------------------------------------
928 -- Pipe EDP registers
929 ---------------------------------------------------------------------------
930
931 -- pipe timing registers
932
933 HTOTAL_EDP => 16#06_f000# / Register_Width,
934 HBLANK_EDP => 16#06_f004# / Register_Width,
935 HSYNC_EDP => 16#06_f008# / Register_Width,
936 VTOTAL_EDP => 16#06_f00c# / Register_Width,
937 VBLANK_EDP => 16#06_f010# / Register_Width,
938 VSYNC_EDP => 16#06_f014# / Register_Width,
939 PIPE_EDP_CONF => 16#07_f008# / Register_Width,
940 PIPE_EDP_DATA_M1 => 16#06_f030# / Register_Width,
941 PIPE_EDP_DATA_N1 => 16#06_f034# / Register_Width,
942 PIPE_EDP_LINK_M1 => 16#06_f040# / Register_Width,
943 PIPE_EDP_LINK_N1 => 16#06_f044# / Register_Width,
944 PIPE_EDP_DDI_FUNC_CTL => 16#06_f400# / Register_Width,
945 PIPE_EDP_MSA_MISC => 16#06_f410# / Register_Width,
946
947 -- PSR registers
948 SRD_CTL => 16#06_4800# / Register_Width,
949 SRD_CTL_A => 16#06_0800# / Register_Width,
950 SRD_CTL_B => 16#06_1800# / Register_Width,
951 SRD_CTL_C => 16#06_2800# / Register_Width,
952 SRD_CTL_EDP => 16#06_f800# / Register_Width,
953 SRD_STATUS => 16#06_4840# / Register_Width,
954 SRD_STATUS_A => 16#06_0840# / Register_Width,
955 SRD_STATUS_B => 16#06_1840# / Register_Width,
956 SRD_STATUS_C => 16#06_2840# / Register_Width,
957 SRD_STATUS_EDP => 16#06_f840# / Register_Width,
958
959 -- DDI registers
960 DDI_BUF_CTL_A => 16#06_4000# / Register_Width, -- aliased by DP_CTL_A
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]961 DDI_BUF_TRANS_A_S0T1 => 16#06_4e00# / Register_Width,
962 DDI_BUF_TRANS_A_S0T2 => 16#06_4e04# / Register_Width,
963 DDI_BUF_TRANS_A_S1T1 => 16#06_4e08# / Register_Width,
964 DDI_BUF_TRANS_A_S1T2 => 16#06_4e0c# / Register_Width,
965 DDI_BUF_TRANS_A_S2T1 => 16#06_4e10# / Register_Width,
966 DDI_BUF_TRANS_A_S2T2 => 16#06_4e14# / Register_Width,
967 DDI_BUF_TRANS_A_S3T1 => 16#06_4e18# / Register_Width,
968 DDI_BUF_TRANS_A_S3T2 => 16#06_4e1c# / Register_Width,
969 DDI_BUF_TRANS_A_S4T1 => 16#06_4e20# / Register_Width,
970 DDI_BUF_TRANS_A_S4T2 => 16#06_4e24# / Register_Width,
971 DDI_BUF_TRANS_A_S5T1 => 16#06_4e28# / Register_Width,
972 DDI_BUF_TRANS_A_S5T2 => 16#06_4e2c# / Register_Width,
973 DDI_BUF_TRANS_A_S6T1 => 16#06_4e30# / Register_Width,
974 DDI_BUF_TRANS_A_S6T2 => 16#06_4e34# / Register_Width,
975 DDI_BUF_TRANS_A_S7T1 => 16#06_4e38# / Register_Width,
976 DDI_BUF_TRANS_A_S7T2 => 16#06_4e3c# / Register_Width,
977 DDI_BUF_TRANS_A_S8T1 => 16#06_4e40# / Register_Width,
978 DDI_BUF_TRANS_A_S8T2 => 16#06_4e44# / Register_Width,
979 DDI_BUF_TRANS_A_S9T1 => 16#06_4e48# / Register_Width,
980 DDI_BUF_TRANS_A_S9T2 => 16#06_4e4c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]981 DDI_AUX_CTL_A => 16#06_4010# / Register_Width, -- aliased by DP_AUX_CTL_A
982 DDI_AUX_DATA_A_1 => 16#06_4014# / Register_Width, -- aliased by DP_AUX_DATA_A_1
983 DDI_AUX_DATA_A_2 => 16#06_4018# / Register_Width, -- aliased by DP_AUX_DATA_A_2
984 DDI_AUX_DATA_A_3 => 16#06_401c# / Register_Width, -- aliased by DP_AUX_DATA_A_3
985 DDI_AUX_DATA_A_4 => 16#06_4020# / Register_Width, -- aliased by DP_AUX_DATA_A_4
986 DDI_AUX_DATA_A_5 => 16#06_4024# / Register_Width, -- aliased by DP_AUX_DATA_A_5
987 DDI_AUX_MUTEX_A => 16#06_402c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]988
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]989 DDI_BUF_CTL_B => 16#06_4100# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]990 DDI_BUF_TRANS_B_S0T1 => 16#06_4e60# / Register_Width,
991 DDI_BUF_TRANS_B_S0T2 => 16#06_4e64# / Register_Width,
992 DDI_BUF_TRANS_B_S1T1 => 16#06_4e68# / Register_Width,
993 DDI_BUF_TRANS_B_S1T2 => 16#06_4e6c# / Register_Width,
994 DDI_BUF_TRANS_B_S2T1 => 16#06_4e70# / Register_Width,
995 DDI_BUF_TRANS_B_S2T2 => 16#06_4e74# / Register_Width,
996 DDI_BUF_TRANS_B_S3T1 => 16#06_4e78# / Register_Width,
997 DDI_BUF_TRANS_B_S3T2 => 16#06_4e7c# / Register_Width,
998 DDI_BUF_TRANS_B_S4T1 => 16#06_4e80# / Register_Width,
999 DDI_BUF_TRANS_B_S4T2 => 16#06_4e84# / Register_Width,
1000 DDI_BUF_TRANS_B_S5T1 => 16#06_4e88# / Register_Width,
1001 DDI_BUF_TRANS_B_S5T2 => 16#06_4e8c# / Register_Width,
1002 DDI_BUF_TRANS_B_S6T1 => 16#06_4e90# / Register_Width,
1003 DDI_BUF_TRANS_B_S6T2 => 16#06_4e94# / Register_Width,
1004 DDI_BUF_TRANS_B_S7T1 => 16#06_4e98# / Register_Width,
1005 DDI_BUF_TRANS_B_S7T2 => 16#06_4e9c# / Register_Width,
1006 DDI_BUF_TRANS_B_S8T1 => 16#06_4ea0# / Register_Width,
1007 DDI_BUF_TRANS_B_S8T2 => 16#06_4ea4# / Register_Width,
1008 DDI_BUF_TRANS_B_S9T1 => 16#06_4ea8# / Register_Width,
1009 DDI_BUF_TRANS_B_S9T2 => 16#06_4eac# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1010 DDI_AUX_CTL_B => 16#06_4110# / Register_Width,
1011 DDI_AUX_DATA_B_1 => 16#06_4114# / Register_Width,
1012 DDI_AUX_DATA_B_2 => 16#06_4118# / Register_Width,
1013 DDI_AUX_DATA_B_3 => 16#06_411c# / Register_Width,
1014 DDI_AUX_DATA_B_4 => 16#06_4120# / Register_Width,
1015 DDI_AUX_DATA_B_5 => 16#06_4124# / Register_Width,
1016 DDI_AUX_MUTEX_B => 16#06_412c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1017
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1018 DDI_BUF_CTL_C => 16#06_4200# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1019 DDI_BUF_TRANS_C_S0T1 => 16#06_4ec0# / Register_Width,
1020 DDI_BUF_TRANS_C_S0T2 => 16#06_4ec4# / Register_Width,
1021 DDI_BUF_TRANS_C_S1T1 => 16#06_4ec8# / Register_Width,
1022 DDI_BUF_TRANS_C_S1T2 => 16#06_4ecc# / Register_Width,
1023 DDI_BUF_TRANS_C_S2T1 => 16#06_4ed0# / Register_Width,
1024 DDI_BUF_TRANS_C_S2T2 => 16#06_4ed4# / Register_Width,
1025 DDI_BUF_TRANS_C_S3T1 => 16#06_4ed8# / Register_Width,
1026 DDI_BUF_TRANS_C_S3T2 => 16#06_4edc# / Register_Width,
1027 DDI_BUF_TRANS_C_S4T1 => 16#06_4ee0# / Register_Width,
1028 DDI_BUF_TRANS_C_S4T2 => 16#06_4ee4# / Register_Width,
1029 DDI_BUF_TRANS_C_S5T1 => 16#06_4ee8# / Register_Width,
1030 DDI_BUF_TRANS_C_S5T2 => 16#06_4eec# / Register_Width,
1031 DDI_BUF_TRANS_C_S6T1 => 16#06_4ef0# / Register_Width,
1032 DDI_BUF_TRANS_C_S6T2 => 16#06_4ef4# / Register_Width,
1033 DDI_BUF_TRANS_C_S7T1 => 16#06_4ef8# / Register_Width,
1034 DDI_BUF_TRANS_C_S7T2 => 16#06_4efc# / Register_Width,
1035 DDI_BUF_TRANS_C_S8T1 => 16#06_4f00# / Register_Width,
1036 DDI_BUF_TRANS_C_S8T2 => 16#06_4f04# / Register_Width,
1037 DDI_BUF_TRANS_C_S9T1 => 16#06_4f08# / Register_Width,
1038 DDI_BUF_TRANS_C_S9T2 => 16#06_4f0c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1039 DDI_AUX_CTL_C => 16#06_4210# / Register_Width,
1040 DDI_AUX_DATA_C_1 => 16#06_4214# / Register_Width,
1041 DDI_AUX_DATA_C_2 => 16#06_4218# / Register_Width,
1042 DDI_AUX_DATA_C_3 => 16#06_421c# / Register_Width,
1043 DDI_AUX_DATA_C_4 => 16#06_4220# / Register_Width,
1044 DDI_AUX_DATA_C_5 => 16#06_4224# / Register_Width,
1045 DDI_AUX_MUTEX_C => 16#06_422c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1046
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1047 DDI_BUF_CTL_D => 16#06_4300# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1048 DDI_BUF_TRANS_D_S0T1 => 16#06_4f20# / Register_Width,
1049 DDI_BUF_TRANS_D_S0T2 => 16#06_4f24# / Register_Width,
1050 DDI_BUF_TRANS_D_S1T1 => 16#06_4f28# / Register_Width,
1051 DDI_BUF_TRANS_D_S1T2 => 16#06_4f2c# / Register_Width,
1052 DDI_BUF_TRANS_D_S2T1 => 16#06_4f30# / Register_Width,
1053 DDI_BUF_TRANS_D_S2T2 => 16#06_4f34# / Register_Width,
1054 DDI_BUF_TRANS_D_S3T1 => 16#06_4f38# / Register_Width,
1055 DDI_BUF_TRANS_D_S3T2 => 16#06_4f3c# / Register_Width,
1056 DDI_BUF_TRANS_D_S4T1 => 16#06_4f40# / Register_Width,
1057 DDI_BUF_TRANS_D_S4T2 => 16#06_4f44# / Register_Width,
1058 DDI_BUF_TRANS_D_S5T1 => 16#06_4f48# / Register_Width,
1059 DDI_BUF_TRANS_D_S5T2 => 16#06_4f4c# / Register_Width,
1060 DDI_BUF_TRANS_D_S6T1 => 16#06_4f50# / Register_Width,
1061 DDI_BUF_TRANS_D_S6T2 => 16#06_4f54# / Register_Width,
1062 DDI_BUF_TRANS_D_S7T1 => 16#06_4f58# / Register_Width,
1063 DDI_BUF_TRANS_D_S7T2 => 16#06_4f5c# / Register_Width,
1064 DDI_BUF_TRANS_D_S8T1 => 16#06_4f60# / Register_Width,
1065 DDI_BUF_TRANS_D_S8T2 => 16#06_4f64# / Register_Width,
1066 DDI_BUF_TRANS_D_S9T1 => 16#06_4f68# / Register_Width,
1067 DDI_BUF_TRANS_D_S9T2 => 16#06_4f6c# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1068 DDI_AUX_CTL_D => 16#06_4310# / Register_Width,
1069 DDI_AUX_DATA_D_1 => 16#06_4314# / Register_Width,
1070 DDI_AUX_DATA_D_2 => 16#06_4318# / Register_Width,
1071 DDI_AUX_DATA_D_3 => 16#06_431c# / Register_Width,
1072 DDI_AUX_DATA_D_4 => 16#06_4320# / Register_Width,
1073 DDI_AUX_DATA_D_5 => 16#06_4324# / Register_Width,
1074 DDI_AUX_MUTEX_D => 16#06_432c# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1075
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1076 DDI_BUF_CTL_E => 16#06_4400# / Register_Width,
Nico Huber01b680f2017-06-09 16:24:22 +0200[diff] [blame]1077 DDI_BUF_TRANS_E_S0T1 => 16#06_4f80# / Register_Width,
1078 DDI_BUF_TRANS_E_S0T2 => 16#06_4f84# / Register_Width,
1079 DDI_BUF_TRANS_E_S1T1 => 16#06_4f88# / Register_Width,
1080 DDI_BUF_TRANS_E_S1T2 => 16#06_4f8c# / Register_Width,
1081 DDI_BUF_TRANS_E_S2T1 => 16#06_4f90# / Register_Width,
1082 DDI_BUF_TRANS_E_S2T2 => 16#06_4f94# / Register_Width,
1083 DDI_BUF_TRANS_E_S3T1 => 16#06_4f98# / Register_Width,
1084 DDI_BUF_TRANS_E_S3T2 => 16#06_4f9c# / Register_Width,
1085 DDI_BUF_TRANS_E_S4T1 => 16#06_4fa0# / Register_Width,
1086 DDI_BUF_TRANS_E_S4T2 => 16#06_4fa4# / Register_Width,
1087 DDI_BUF_TRANS_E_S5T1 => 16#06_4fa8# / Register_Width,
1088 DDI_BUF_TRANS_E_S5T2 => 16#06_4fac# / Register_Width,
1089 DDI_BUF_TRANS_E_S6T1 => 16#06_4fb0# / Register_Width,
1090 DDI_BUF_TRANS_E_S6T2 => 16#06_4fb4# / Register_Width,
1091 DDI_BUF_TRANS_E_S7T1 => 16#06_4fb8# / Register_Width,
1092 DDI_BUF_TRANS_E_S7T2 => 16#06_4fbc# / Register_Width,
1093 DDI_BUF_TRANS_E_S8T1 => 16#06_4fc0# / Register_Width,
1094 DDI_BUF_TRANS_E_S8T2 => 16#06_4fc4# / Register_Width,
1095 DDI_BUF_TRANS_E_S9T1 => 16#06_4fc8# / Register_Width,
1096 DDI_BUF_TRANS_E_S9T2 => 16#06_4fcc# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1097 DP_TP_CTL_A => 16#06_4040# / Register_Width,
1098 DP_TP_CTL_B => 16#06_4140# / Register_Width,
1099 DP_TP_CTL_C => 16#06_4240# / Register_Width,
1100 DP_TP_CTL_D => 16#06_4340# / Register_Width,
1101 DP_TP_CTL_E => 16#06_4440# / Register_Width,
1102 DP_TP_STATUS_B => 16#06_4144# / Register_Width,
1103 DP_TP_STATUS_C => 16#06_4244# / Register_Width,
1104 DP_TP_STATUS_D => 16#06_4344# / Register_Width,
1105 DP_TP_STATUS_E => 16#06_4444# / Register_Width,
1106 PORT_CLK_SEL_DDIA => 16#04_6100# / Register_Width,
1107 PORT_CLK_SEL_DDIB => 16#04_6104# / Register_Width,
1108 PORT_CLK_SEL_DDIC => 16#04_6108# / Register_Width,
1109 PORT_CLK_SEL_DDID => 16#04_610c# / Register_Width,
1110 PORT_CLK_SEL_DDIE => 16#04_6110# / Register_Width,
1111
1112 -- Skylake DPLL registers
1113 DPLL1_CFGR1 => 16#06_c040# / Register_Width,
1114 DPLL1_CFGR2 => 16#06_c044# / Register_Width,
1115 DPLL2_CFGR1 => 16#06_c048# / Register_Width,
1116 DPLL2_CFGR2 => 16#06_c04c# / Register_Width,
1117 DPLL3_CFGR1 => 16#06_c050# / Register_Width,
1118 DPLL3_CFGR2 => 16#06_c054# / Register_Width,
1119 DPLL_CTRL1 => 16#06_c058# / Register_Width,
1120 DPLL_CTRL2 => 16#06_c05c# / Register_Width,
1121 DPLL_STATUS => 16#06_c060# / Register_Width,
1122
1123 -- CD CLK register
1124 CDCLK_CTL => 16#04_6000# / Register_Width,
1125
1126 -- Skylake LCPLL registers
1127 LCPLL1_CTL => 16#04_6010# / Register_Width,
1128 LCPLL2_CTL => 16#04_6014# / Register_Width,
1129
1130 -- SPLL register
1131 SPLL_CTL => 16#04_6020# / Register_Width,
1132
1133 -- WRPLL registers
1134 WRPLL_CTL_1 => 16#04_6040# / Register_Width,
1135 WRPLL_CTL_2 => 16#04_6060# / Register_Width,
1136
Nico Huber40820442017-01-20 14:00:53 +0100[diff] [blame]1137 -- Broxton Display Engine PLL registers
1138 BXT_DE_PLL_CTL => 16#06_d000# / Register_Width,
1139 BXT_DE_PLL_ENABLE => 16#04_6070# / Register_Width,
1140
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1141 -- Broxton DDI PHY PLL registers
1142 BXT_PORT_PLL_ENABLE_A => 16#04_6074# / Register_Width,
1143 BXT_PORT_PLL_ENABLE_B => 16#04_6078# / Register_Width,
1144 BXT_PORT_PLL_ENABLE_C => 16#04_607c# / Register_Width,
1145 BXT_PORT_PLL_EBB_0_A => 16#16_2034# / Register_Width,
1146 BXT_PORT_PLL_EBB_4_A => 16#16_2038# / Register_Width,
1147 BXT_PORT_PLL_0_A => 16#16_2100# / Register_Width,
1148 BXT_PORT_PLL_1_A => 16#16_2104# / Register_Width,
1149 BXT_PORT_PLL_2_A => 16#16_2108# / Register_Width,
1150 BXT_PORT_PLL_3_A => 16#16_210c# / Register_Width,
1151 BXT_PORT_PLL_6_A => 16#16_2118# / Register_Width,
1152 BXT_PORT_PLL_8_A => 16#16_2120# / Register_Width,
1153 BXT_PORT_PLL_9_A => 16#16_2124# / Register_Width,
1154 BXT_PORT_PLL_10_A => 16#16_2128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1155 BXT_PORT_PLL_EBB_0_B => 16#06_c034# / Register_Width,
1156 BXT_PORT_PLL_EBB_4_B => 16#06_c038# / Register_Width,
1157 BXT_PORT_PLL_0_B => 16#06_c100# / Register_Width,
1158 BXT_PORT_PLL_1_B => 16#06_c104# / Register_Width,
1159 BXT_PORT_PLL_2_B => 16#06_c108# / Register_Width,
1160 BXT_PORT_PLL_3_B => 16#06_c10c# / Register_Width,
1161 BXT_PORT_PLL_6_B => 16#06_c118# / Register_Width,
1162 BXT_PORT_PLL_8_B => 16#06_c120# / Register_Width,
1163 BXT_PORT_PLL_9_B => 16#06_c124# / Register_Width,
1164 BXT_PORT_PLL_10_B => 16#06_c128# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1165 BXT_PORT_PLL_EBB_0_C => 16#06_c340# / Register_Width,
1166 BXT_PORT_PLL_EBB_4_C => 16#06_c344# / Register_Width,
1167 BXT_PORT_PLL_0_C => 16#06_c380# / Register_Width,
1168 BXT_PORT_PLL_1_C => 16#06_c384# / Register_Width,
1169 BXT_PORT_PLL_2_C => 16#06_c388# / Register_Width,
1170 BXT_PORT_PLL_3_C => 16#06_c38c# / Register_Width,
1171 BXT_PORT_PLL_6_C => 16#06_c398# / Register_Width,
1172 BXT_PORT_PLL_8_C => 16#06_c3a0# / Register_Width,
1173 BXT_PORT_PLL_9_C => 16#06_c3a4# / Register_Width,
1174 BXT_PORT_PLL_10_C => 16#06_c3a8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1175
1176 -- Broxton DDI PHY PCS? registers
1177 BXT_PORT_PCS_DW10_01_A => 16#16_2428# / Register_Width,
1178 BXT_PORT_PCS_DW12_01_A => 16#16_2430# / Register_Width,
1179 BXT_PORT_PCS_DW10_GRP_A => 16#16_2c28# / Register_Width,
1180 BXT_PORT_PCS_DW12_GRP_A => 16#16_2c30# / Register_Width,
1181 BXT_PORT_PCS_DW10_01_B => 16#06_c428# / Register_Width,
1182 BXT_PORT_PCS_DW12_01_B => 16#06_c430# / Register_Width,
1183 BXT_PORT_PCS_DW10_01_C => 16#06_c828# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1184 BXT_PORT_PCS_DW12_01_C => 16#06_c830# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1185 BXT_PORT_PCS_DW10_GRP_B => 16#06_cc28# / Register_Width,
1186 BXT_PORT_PCS_DW12_GRP_B => 16#06_cc30# / Register_Width,
1187 BXT_PORT_PCS_DW10_GRP_C => 16#06_ce28# / Register_Width,
Nico Huber4b0239f2017-02-07 18:26:51 +0100[diff] [blame]1188 BXT_PORT_PCS_DW12_GRP_C => 16#06_ce30# / Register_Width,
1189
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1190 -- Broxton DDI PHY registers
1191 BXT_P_CR_GT_DISP_PWRON => 16#13_8090# / Register_Width,
1192 BXT_PHY_CTL_A => 16#06_4c00# / Register_Width,
1193 BXT_PHY_CTL_B => 16#06_4c10# / Register_Width,
1194 BXT_PHY_CTL_C => 16#06_4c20# / Register_Width,
1195 BXT_PHY_CTL_FAM_EDP => 16#06_4c80# / Register_Width,
1196 BXT_PHY_CTL_FAM_DDI => 16#06_4c90# / Register_Width,
1197
1198 -- Broxton DDI PHY common lane registers
1199 BXT_PORT_CL1CM_DW0_A => 16#16_2000# / Register_Width,
1200 BXT_PORT_CL1CM_DW0_BC => 16#06_c000# / Register_Width,
1201 BXT_PORT_CL1CM_DW9_A => 16#16_2024# / Register_Width,
1202 BXT_PORT_CL1CM_DW9_BC => 16#06_c024# / Register_Width,
1203 BXT_PORT_CL1CM_DW10_A => 16#16_2028# / Register_Width,
1204 BXT_PORT_CL1CM_DW10_BC => 16#06_c028# / Register_Width,
1205 BXT_PORT_CL1CM_DW28_A => 16#16_2070# / Register_Width,
1206 BXT_PORT_CL1CM_DW28_BC => 16#06_c070# / Register_Width,
1207 BXT_PORT_CL1CM_DW30_A => 16#16_2078# / Register_Width,
1208 BXT_PORT_CL1CM_DW30_BC => 16#06_c078# / Register_Width,
1209 BXT_PORT_CL2CM_DW6_BC => 16#06_c358# / Register_Width,
1210
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1211 -- Broxton DDI PHY TX lane registers
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1212 BXT_PORT_TX_DW2_LN0_A => 16#16_2508# / Register_Width,
1213 BXT_PORT_TX_DW3_LN0_A => 16#16_250c# / Register_Width,
1214 BXT_PORT_TX_DW4_LN0_A => 16#16_2510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1215 BXT_PORT_TX_DW14_LN0_A => 16#16_2538# / Register_Width,
1216 BXT_PORT_TX_DW14_LN1_A => 16#16_25b8# / Register_Width,
1217 BXT_PORT_TX_DW14_LN2_A => 16#16_2738# / Register_Width,
1218 BXT_PORT_TX_DW14_LN3_A => 16#16_27b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1219 BXT_PORT_TX_DW2_GRP_A => 16#16_2d08# / Register_Width,
1220 BXT_PORT_TX_DW3_GRP_A => 16#16_2d0c# / Register_Width,
1221 BXT_PORT_TX_DW4_GRP_A => 16#16_2d10# / Register_Width,
1222 BXT_PORT_TX_DW2_LN0_B => 16#06_c508# / Register_Width,
1223 BXT_PORT_TX_DW3_LN0_B => 16#06_c50c# / Register_Width,
1224 BXT_PORT_TX_DW4_LN0_B => 16#06_c510# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1225 BXT_PORT_TX_DW14_LN0_B => 16#06_c538# / Register_Width,
1226 BXT_PORT_TX_DW14_LN1_B => 16#06_c5b8# / Register_Width,
1227 BXT_PORT_TX_DW14_LN2_B => 16#06_c738# / Register_Width,
1228 BXT_PORT_TX_DW14_LN3_B => 16#06_c7b8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1229 BXT_PORT_TX_DW2_GRP_B => 16#06_cd08# / Register_Width,
1230 BXT_PORT_TX_DW3_GRP_B => 16#06_cd0c# / Register_Width,
1231 BXT_PORT_TX_DW4_GRP_B => 16#06_cd10# / Register_Width,
1232 BXT_PORT_TX_DW2_LN0_C => 16#06_c908# / Register_Width,
1233 BXT_PORT_TX_DW3_LN0_C => 16#06_c90c# / Register_Width,
1234 BXT_PORT_TX_DW4_LN0_C => 16#06_c910# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1235 BXT_PORT_TX_DW14_LN0_C => 16#06_c938# / Register_Width,
1236 BXT_PORT_TX_DW14_LN1_C => 16#06_c9b8# / Register_Width,
1237 BXT_PORT_TX_DW14_LN2_C => 16#06_cb38# / Register_Width,
1238 BXT_PORT_TX_DW14_LN3_C => 16#06_cbb8# / Register_Width,
Nico Huberfdd93652017-02-08 13:41:38 +0100[diff] [blame]1239 BXT_PORT_TX_DW2_GRP_C => 16#06_cf08# / Register_Width,
1240 BXT_PORT_TX_DW3_GRP_C => 16#06_cf0c# / Register_Width,
1241 BXT_PORT_TX_DW4_GRP_C => 16#06_cf10# / Register_Width,
Nico Huberafadcac2017-02-08 13:41:38 +0100[diff] [blame]1242
Nico Huberf6266002017-02-03 12:17:28 +0100[diff] [blame]1243 -- Broxton DDI PHY ref registers
1244 BXT_PORT_REF_DW3_A => 16#16_218c# / Register_Width,
1245 BXT_PORT_REF_DW3_BC => 16#06_c18c# / Register_Width,
1246 BXT_PORT_REF_DW6_A => 16#16_2198# / Register_Width,
1247 BXT_PORT_REF_DW6_BC => 16#06_c198# / Register_Width,
1248 BXT_PORT_REF_DW8_A => 16#16_21a0# / Register_Width,
1249 BXT_PORT_REF_DW8_BC => 16#06_c1a0# / Register_Width,
1250
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1251 -- Power Down Well registers
1252 PWR_WELL_CTL_BIOS => 16#04_5400# / Register_Width,
1253 PWR_WELL_CTL_DRIVER => 16#04_5404# / Register_Width,
1254 PWR_WELL_CTL_KVMR => 16#04_5408# / Register_Width,
1255 PWR_WELL_CTL_DEBUG => 16#04_540c# / Register_Width,
1256 PWR_WELL_CTL5 => 16#04_5410# / Register_Width,
1257 PWR_WELL_CTL6 => 16#04_5414# / Register_Width,
1258
1259 -- class Panel registers
1260 PCH_PP_STATUS => 16#0c_7200# / Register_Width,
1261 PCH_PP_CONTROL => 16#0c_7204# / Register_Width,
1262 PCH_PP_ON_DELAYS => 16#0c_7208# / Register_Width,
1263 PCH_PP_OFF_DELAYS => 16#0c_720c# / Register_Width,
1264 PCH_PP_DIVISOR => 16#0c_7210# / Register_Width,
1265 BLC_PWM_CPU_CTL => 16#04_8254# / Register_Width,
1266 BLC_PWM_PCH_CTL2 => 16#0c_8254# / Register_Width,
1267
1268 -- PCH LVDS Connector Registers
1269 PCH_LVDS => 16#0e_1180# / Register_Width,
1270
1271 -- PCH ADPA Connector Registers
1272 PCH_ADPA => 16#0e_1100# / Register_Width,
1273
1274 -- PCH HDMIB Connector Registers
1275 PCH_HDMIB => 16#0e_1140# / Register_Width,
1276
1277 -- PCH HDMIC Connector Registers
1278 PCH_HDMIC => 16#0e_1150# / Register_Width,
1279
1280 -- PCH HDMID Connector Registers
1281 PCH_HDMID => 16#0e_1160# / Register_Width,
1282
1283 -- Intel Registers
1284 VGACNTRL => 16#04_1000# / Register_Width,
1285 FUSE_STATUS => 16#04_2000# / Register_Width,
1286 FBA_CFB_BASE => 16#04_3200# / Register_Width,
1287 IPS_CTL => 16#04_3408# / Register_Width,
1288 ARB_CTL => 16#04_5000# / Register_Width,
1289 DBUF_CTL => 16#04_5008# / Register_Width,
1290 NDE_RSTWRN_OPT => 16#04_6408# / Register_Width,
1291 PCH_DREF_CONTROL => 16#0c_6200# / Register_Width,
1292 BLC_PWM_PCH_CTL1 => 16#0c_8250# / Register_Width,
1293 BLC_PWM_CPU_CTL2 => 16#04_8250# / Register_Width,
1294 PCH_DPLL_SEL => 16#0c_7000# / Register_Width,
1295 GT_MAILBOX => 16#13_8124# / Register_Width,
1296 GT_MAILBOX_DATA => 16#13_8128# / Register_Width,
1297 GT_MAILBOX_DATA_1 => 16#13_812c# / Register_Width,
1298
1299 PCH_DP_B => 16#0e_4100# / Register_Width,
1300 PCH_DP_AUX_CTL_B => 16#0e_4110# / Register_Width,
1301 PCH_DP_AUX_DATA_B_1 => 16#0e_4114# / Register_Width,
1302 PCH_DP_AUX_DATA_B_2 => 16#0e_4118# / Register_Width,
1303 PCH_DP_AUX_DATA_B_3 => 16#0e_411c# / Register_Width,
1304 PCH_DP_AUX_DATA_B_4 => 16#0e_4120# / Register_Width,
1305 PCH_DP_AUX_DATA_B_5 => 16#0e_4124# / Register_Width,
1306 PCH_DP_C => 16#0e_4200# / Register_Width,
1307 PCH_DP_AUX_CTL_C => 16#0e_4210# / Register_Width,
1308 PCH_DP_AUX_DATA_C_1 => 16#0e_4214# / Register_Width,
1309 PCH_DP_AUX_DATA_C_2 => 16#0e_4218# / Register_Width,
1310 PCH_DP_AUX_DATA_C_3 => 16#0e_421c# / Register_Width,
1311 PCH_DP_AUX_DATA_C_4 => 16#0e_4220# / Register_Width,
1312 PCH_DP_AUX_DATA_C_5 => 16#0e_4224# / Register_Width,
1313 PCH_DP_D => 16#0e_4300# / Register_Width,
1314 PCH_DP_AUX_CTL_D => 16#0e_4310# / Register_Width,
1315 PCH_DP_AUX_DATA_D_1 => 16#0e_4314# / Register_Width,
1316 PCH_DP_AUX_DATA_D_2 => 16#0e_4318# / Register_Width,
1317 PCH_DP_AUX_DATA_D_3 => 16#0e_431c# / Register_Width,
1318 PCH_DP_AUX_DATA_D_4 => 16#0e_4320# / Register_Width,
1319 PCH_DP_AUX_DATA_D_5 => 16#0e_4324# / Register_Width,
1320
1321 -- watermark registers
1322 WM1_LP_ILK => 16#04_5108# / Register_Width,
1323 WM2_LP_ILK => 16#04_510c# / Register_Width,
1324 WM3_LP_ILK => 16#04_5110# / Register_Width,
1325
1326 -- audio VID/DID
1327 AUD_VID_DID => 16#06_5020# / Register_Width,
1328 PCH_AUD_VID_DID => 16#0e_5020# / Register_Width,
1329
1330 -- interrupt registers
1331 DEISR => 16#04_4000# / Register_Width,
1332 DEIMR => 16#04_4004# / Register_Width,
1333 DEIIR => 16#04_4008# / Register_Width,
1334 DEIER => 16#04_400c# / Register_Width,
1335 GTISR => 16#04_4010# / Register_Width,
1336 GTIMR => 16#04_4014# / Register_Width,
1337 GTIIR => 16#04_4018# / Register_Width,
1338 GTIER => 16#04_401c# / Register_Width,
1339 SDEISR => 16#0c_4000# / Register_Width,
1340 SDEIMR => 16#0c_4004# / Register_Width,
1341 SDEIIR => 16#0c_4008# / Register_Width,
1342 SDEIER => 16#0c_400c# / Register_Width,
1343
1344 -- I2C stuff
1345 PCH_GMBUS0 => 16#0c_5100# / Register_Width,
1346 PCH_GMBUS1 => 16#0c_5104# / Register_Width,
1347 PCH_GMBUS2 => 16#0c_5108# / Register_Width,
1348 PCH_GMBUS3 => 16#0c_510c# / Register_Width,
1349 PCH_GMBUS4 => 16#0c_5110# / Register_Width,
1350 PCH_GMBUS5 => 16#0c_5120# / Register_Width,
1351
1352 -- clock gating -- maybe have to touch this
1353 DSPCLK_GATE_D => 16#04_2020# / Register_Width,
1354 PCH_FDI_CHICKEN_B_C => 16#0c_2000# / Register_Width,
1355 PCH_DSPCLK_GATE_D => 16#0c_2020# / Register_Width,
1356
1357 -- hotplug and initial detection
1358 HOTPLUG_CTL => 16#04_4030# / Register_Width,
1359 SHOTPLUG_CTL => 16#0c_4030# / Register_Width,
1360 SFUSE_STRAP => 16#0c_2014# / Register_Width,
1361
1362 -- Render Engine Command Streamer
1363 ARB_MODE => 16#00_4030# / Register_Width,
1364 HWS_PGA => 16#00_4080# / Register_Width,
1365 RCS_RING_BUFFER_TAIL => 16#00_2030# / Register_Width,
1366 VCS_RING_BUFFER_TAIL => 16#01_2030# / Register_Width,
1367 BCS_RING_BUFFER_TAIL => 16#02_2030# / Register_Width,
1368 RCS_RING_BUFFER_HEAD => 16#00_2034# / Register_Width,
1369 VCS_RING_BUFFER_HEAD => 16#01_2034# / Register_Width,
1370 BCS_RING_BUFFER_HEAD => 16#02_2034# / Register_Width,
1371 RCS_RING_BUFFER_STRT => 16#00_2038# / Register_Width,
1372 VCS_RING_BUFFER_STRT => 16#01_2038# / Register_Width,
1373 BCS_RING_BUFFER_STRT => 16#02_2038# / Register_Width,
1374 RCS_RING_BUFFER_CTL => 16#00_203c# / Register_Width,
1375 VCS_RING_BUFFER_CTL => 16#01_203c# / Register_Width,
1376 BCS_RING_BUFFER_CTL => 16#02_203c# / Register_Width,
1377 MI_MODE => 16#00_209c# / Register_Width,
1378 INSTPM => 16#00_20c0# / Register_Width,
1379 GAB_CTL_REG => 16#02_4000# / Register_Width,
1380 PP_DCLV_HIGH => 16#00_2220# / Register_Width,
1381 PP_DCLV_LOW => 16#00_2228# / Register_Width,
1382 VCS_PP_DCLV_HIGH => 16#01_2220# / Register_Width,
1383 VCS_PP_DCLV_LOW => 16#01_2228# / Register_Width,
1384 BCS_PP_DCLV_HIGH => 16#02_2220# / Register_Width,
1385 BCS_PP_DCLV_LOW => 16#02_2228# / Register_Width,
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1386 ILK_DISPLAY_CHICKEN2 => 16#04_2004# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1387 UCGCTL1 => 16#00_9400# / Register_Width,
1388 UCGCTL2 => 16#00_9404# / Register_Width,
1389 MBCTL => 16#00_907c# / Register_Width,
1390 HWSTAM => 16#00_2098# / Register_Width,
1391 VCS_HWSTAM => 16#01_2098# / Register_Width,
1392 BCS_HWSTAM => 16#02_2098# / Register_Width,
1393 IIR => 16#04_4028# / Register_Width,
1394 PIPE_FRMCNT_A => 16#07_0040# / Register_Width,
1395 PIPE_FRMCNT_B => 16#07_1040# / Register_Width,
1396 PIPE_FRMCNT_C => 16#07_2040# / Register_Width,
1397 FBC_CTL => 16#04_3208# / Register_Width,
1398 PIPE_VSYNCSHIFT_A => 16#06_0028# / Register_Width,
1399 PIPE_VSYNCSHIFT_B => 16#06_1028# / Register_Width,
1400 PIPE_VSYNCSHIFT_C => 16#06_2028# / Register_Width,
1401 WM_PIPE_A => 16#04_5100# / Register_Width,
1402 WM_PIPE_B => 16#04_5104# / Register_Width,
1403 WM_PIPE_C => 16#04_5200# / Register_Width,
1404 PIPE_SCANLINE_A => 16#07_0000# / Register_Width,
1405 PIPE_SCANLINE_B => 16#07_1000# / Register_Width,
1406 PIPE_SCANLINE_C => 16#07_2000# / Register_Width,
1407 GFX_MODE => 16#00_2520# / Register_Width,
1408 CACHE_MODE_0 => 16#00_2120# / Register_Width,
1409 SLEEP_PSMI_CONTROL => 16#01_2050# / Register_Width,
1410 CTX_SIZE => 16#00_21a0# / Register_Width,
1411 GAC_ECO_BITS => 16#01_4090# / Register_Width,
1412 GAM_ECOCHK => 16#00_4090# / Register_Width,
1413 QUIRK_02084 => 16#00_2084# / Register_Width,
1414 QUIRK_02090 => 16#00_2090# / Register_Width,
1415 GT_MODE => 16#00_20d0# / Register_Width,
1416 QUIRK_F0060 => 16#0f_0060# / Register_Width,
1417 QUIRK_F1060 => 16#0f_1060# / Register_Width,
1418 QUIRK_F2060 => 16#0f_2060# / Register_Width,
1419 AUD_CNTRL_ST2 => 16#0e_50c0# / Register_Width,
1420 AUD_CNTL_ST_A => 16#0e_50b4# / Register_Width,
1421 AUD_CNTL_ST_B => 16#0e_51b4# / Register_Width,
1422 AUD_CNTL_ST_C => 16#0e_52b4# / Register_Width,
1423 AUD_HDMIW_HDMIEDID_A => 16#0e_5050# / Register_Width,
1424 AUD_HDMIW_HDMIEDID_B => 16#0e_5150# / Register_Width,
1425 AUD_HDMIW_HDMIEDID_C => 16#0e_5250# / Register_Width,
1426 AUD_CONFIG_A => 16#0e_5000# / Register_Width,
1427 AUD_CONFIG_B => 16#0e_5100# / Register_Width,
1428 AUD_CONFIG_C => 16#0e_5200# / Register_Width,
1429 TRANS_DP_CTL_A => 16#0e_0300# / Register_Width,
1430 TRANS_DP_CTL_B => 16#0e_1300# / Register_Width,
1431 TRANS_DP_CTL_C => 16#0e_2300# / Register_Width,
1432 TRANS_VSYNCSHIFT_A => 16#0e_0028# / Register_Width,
1433 TRANS_VSYNCSHIFT_B => 16#0e_1028# / Register_Width,
1434 TRANS_VSYNCSHIFT_C => 16#0e_2028# / Register_Width,
Nico Huberf54d0962016-10-20 14:17:18 +0200[diff] [blame]1435 PCH_RAWCLK_FREQ => 16#0c_6204# / Register_Width,
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1436 QUIRK_C2004 => 16#0c_2004# / Register_Width);
1437
1438 subtype Registers_Index is Registers_Invalid_Index range
1439 Registers_Invalid_Index'Succ (Invalid_Register) ..
1440 Registers_Invalid_Index'Last;
1441
1442 -- aliased registers
1443 DP_CTL_A : constant Registers_Index := DDI_BUF_CTL_A;
1444 DP_AUX_CTL_A : constant Registers_Index := DDI_AUX_CTL_A;
1445 DP_AUX_DATA_A_1 : constant Registers_Index := DDI_AUX_DATA_A_1;
1446 DP_AUX_DATA_A_2 : constant Registers_Index := DDI_AUX_DATA_A_2;
1447 DP_AUX_DATA_A_3 : constant Registers_Index := DDI_AUX_DATA_A_3;
1448 DP_AUX_DATA_A_4 : constant Registers_Index := DDI_AUX_DATA_A_4;
1449 DP_AUX_DATA_A_5 : constant Registers_Index := DDI_AUX_DATA_A_5;
Nico Huberfbb42202016-11-07 15:08:26 +0100[diff] [blame]1450 ILK_DISPLAY_CHICKEN1 : constant Registers_Index := FUSE_STATUS;
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1451
1452 ---------------------------------------------------------------------------
1453
1454 Default_Timeout_MS : constant := 10;
1455
1456 ---------------------------------------------------------------------------
1457
1458 procedure Posting_Read
1459 (Register : in Registers_Index)
1460 with
1461 Global => (In_Out => Register_State),
1462 Depends => (Register_State =>+ (Register)),
1463 Pre => True,
1464 Post => True;
1465
1466 pragma Warnings (GNATprove, Off, "unused variable ""Verbose""",
1467 Reason => "Only used on debugging path");
1468 procedure Read
1469 (Register : in Registers_Index;
1470 Value : out Word32;
1471 Verbose : in Boolean := True)
1472 with
1473 Global => (In_Out => Register_State),
1474 Depends => ((Value, Register_State) => (Register, Register_State),
1475 null => Verbose),
1476 Pre => True,
1477 Post => True;
1478 pragma Warnings (GNATprove, On, "unused variable ""Verbose""");
1479
1480 procedure Write
1481 (Register : Registers_Index;
1482 Value : Word32)
1483 with
1484 Global => (In_Out => Register_State),
1485 Depends => (Register_State => (Register, Register_State, Value)),
1486 Pre => True,
1487 Post => True;
1488
1489 procedure Is_Set_Mask
1490 (Register : in Registers_Index;
1491 Mask : in Word32;
1492 Result : out Boolean);
1493
1494 pragma Warnings (GNATprove, Off, "unused initial value of ""Verbose""",
1495 Reason => "Only used on debugging path");
Nico Huberbcb2c472017-02-02 16:39:26 +0100[diff] [blame]1496 procedure Wait
1497 (Register : Registers_Index;
1498 Mask : Word32;
1499 Value : Word32;
1500 TOut_MS : Natural := Default_Timeout_MS;
1501 Verbose : Boolean := False);
1502
Nico Huber83693c82016-10-08 22:17:55 +0200[diff] [blame]1503 procedure Wait_Set_Mask
1504 (Register : Registers_Index;
1505 Mask : Word32;
1506 TOut_MS : Natural := Default_Timeout_MS;
1507 Verbose : Boolean := False);
1508
1509 procedure Wait_Unset_Mask
1510 (Register : Registers_Index;
1511 Mask : Word32;
1512 TOut_MS : Natural := Default_Timeout_MS;
1513 Verbose : Boolean := False);
1514 pragma Warnings (GNATprove, On, "unused initial value of ""Verbose""");
1515
1516 procedure Set_Mask
1517 (Register : Registers_Index;
1518 Mask : Word32);
1519
1520 procedure Unset_Mask
1521 (Register : Registers_Index;
1522 Mask : Word32);
1523
1524 procedure Unset_And_Set_Mask
1525 (Register : Registers_Index;
1526 Mask_Unset : Word32;
1527 Mask_Set : Word32);
1528
1529 pragma Warnings (Off, "declaration of ""Write_GTT"" hides one at *");
1530 procedure Write_GTT
1531 (GTT_Page : GTT_Range;
1532 Device_Address : GTT_Address_Type;
1533 Valid : Boolean)
1534 with
1535 Global => (In_Out => GTT_State),
1536 Depends => (GTT_State =>+ (GTT_Page, Device_Address, Valid)),
1537 Pre => True,
1538 Post => True;
1539 pragma Warnings (On, "declaration of ""Write_GTT"" hides one at *");
1540
1541 procedure Set_Register_Base (Base : Word64)
1542 with
1543 Global => (Output => Address_State),
1544 Depends => (Address_State => Base),
1545 Pre => True,
1546 Post => True;
1547
1548end HW.GFX.GMA.Registers;