Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 1 | /* |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 2 | * This file is part of the flashrom project. |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 3 | * |
Uwe Hermann | d22a1d4 | 2007-09-09 20:21:05 +0000 | [diff] [blame] | 4 | * Copyright (C) 2000 Silicon Integrated System Corporation |
| 5 | * Copyright (C) 2006 Giampiero Giancipoli <gianci@email.it> |
| 6 | * Copyright (C) 2006 coresystems GmbH <info@coresystems.de> |
Carl-Daniel Hailfinger | ef3ac8a | 2014-08-03 13:05:34 +0000 | [diff] [blame^] | 7 | * Copyright (C) 2007, 2011 Carl-Daniel Hailfinger |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 8 | * Copyright (C) 2009 Sean Nelson <audiohacked@gmail.com> |
Carl-Daniel Hailfinger | ef3ac8a | 2014-08-03 13:05:34 +0000 | [diff] [blame^] | 9 | * Copyright (C) 2014 Stefan Tauner |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 10 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or |
| 14 | * (at your option) any later version. |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 15 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 20 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 24 | */ |
| 25 | |
| 26 | #include "flash.h" |
Stefan Tauner | 0ab1e5d | 2014-05-29 11:51:24 +0000 | [diff] [blame] | 27 | #include "chipdrivers.h" |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 28 | |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 29 | #define MAX_REFLASH_TRIES 0x10 |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 30 | #define MASK_FULL 0xffff |
| 31 | #define MASK_2AA 0x7ff |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 32 | #define MASK_AAA 0xfff |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 33 | |
Carl-Daniel Hailfinger | a758f51 | 2008-05-14 12:03:06 +0000 | [diff] [blame] | 34 | /* Check one byte for odd parity */ |
| 35 | uint8_t oddparity(uint8_t val) |
| 36 | { |
| 37 | val = (val ^ (val >> 4)) & 0xf; |
| 38 | val = (val ^ (val >> 2)) & 0x3; |
| 39 | return (val ^ (val >> 1)) & 0x1; |
| 40 | } |
| 41 | |
Stefan Tauner | f80419c | 2014-05-02 15:41:42 +0000 | [diff] [blame] | 42 | static void toggle_ready_jedec_common(const struct flashctx *flash, chipaddr dst, unsigned int delay) |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 43 | { |
| 44 | unsigned int i = 0; |
| 45 | uint8_t tmp1, tmp2; |
| 46 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 47 | tmp1 = chip_readb(flash, dst) & 0x40; |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 48 | |
| 49 | while (i++ < 0xFFFFFFF) { |
Carl-Daniel Hailfinger | aa00098 | 2009-12-17 16:20:26 +0000 | [diff] [blame] | 50 | if (delay) |
| 51 | programmer_delay(delay); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 52 | tmp2 = chip_readb(flash, dst) & 0x40; |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 53 | if (tmp1 == tmp2) { |
| 54 | break; |
| 55 | } |
| 56 | tmp1 = tmp2; |
| 57 | } |
Carl-Daniel Hailfinger | aa00098 | 2009-12-17 16:20:26 +0000 | [diff] [blame] | 58 | if (i > 0x100000) |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 59 | msg_cdbg("%s: excessive loops, i=0x%x\n", __func__, i); |
Carl-Daniel Hailfinger | aa00098 | 2009-12-17 16:20:26 +0000 | [diff] [blame] | 60 | } |
| 61 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 62 | void toggle_ready_jedec(const struct flashctx *flash, chipaddr dst) |
Carl-Daniel Hailfinger | aa00098 | 2009-12-17 16:20:26 +0000 | [diff] [blame] | 63 | { |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 64 | toggle_ready_jedec_common(flash, dst, 0); |
Carl-Daniel Hailfinger | aa00098 | 2009-12-17 16:20:26 +0000 | [diff] [blame] | 65 | } |
| 66 | |
| 67 | /* Some chips require a minimum delay between toggle bit reads. |
| 68 | * The Winbond W39V040C wants 50 ms between reads on sector erase toggle, |
| 69 | * but experiments show that 2 ms are already enough. Pick a safety factor |
| 70 | * of 4 and use an 8 ms delay. |
| 71 | * Given that erase is slow on all chips, it is recommended to use |
| 72 | * toggle_ready_jedec_slow in erase functions. |
| 73 | */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 74 | static void toggle_ready_jedec_slow(const struct flashctx *flash, chipaddr dst) |
Carl-Daniel Hailfinger | aa00098 | 2009-12-17 16:20:26 +0000 | [diff] [blame] | 75 | { |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 76 | toggle_ready_jedec_common(flash, dst, 8 * 1000); |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 77 | } |
| 78 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 79 | void data_polling_jedec(const struct flashctx *flash, chipaddr dst, |
| 80 | uint8_t data) |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 81 | { |
| 82 | unsigned int i = 0; |
| 83 | uint8_t tmp; |
| 84 | |
| 85 | data &= 0x80; |
| 86 | |
| 87 | while (i++ < 0xFFFFFFF) { |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 88 | tmp = chip_readb(flash, dst) & 0x80; |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 89 | if (tmp == data) { |
| 90 | break; |
| 91 | } |
| 92 | } |
Carl-Daniel Hailfinger | aa00098 | 2009-12-17 16:20:26 +0000 | [diff] [blame] | 93 | if (i > 0x100000) |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 94 | msg_cdbg("%s: excessive loops, i=0x%x\n", __func__, i); |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 95 | } |
| 96 | |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 97 | static unsigned int getaddrmask(const struct flashchip *chip) |
Carl-Daniel Hailfinger | 79e6757 | 2010-10-13 21:49:30 +0000 | [diff] [blame] | 98 | { |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 99 | switch (chip->feature_bits & FEATURE_ADDR_MASK) { |
Carl-Daniel Hailfinger | 79e6757 | 2010-10-13 21:49:30 +0000 | [diff] [blame] | 100 | case FEATURE_ADDR_FULL: |
| 101 | return MASK_FULL; |
| 102 | break; |
| 103 | case FEATURE_ADDR_2AA: |
| 104 | return MASK_2AA; |
| 105 | break; |
| 106 | case FEATURE_ADDR_AAA: |
| 107 | return MASK_AAA; |
| 108 | break; |
| 109 | default: |
| 110 | msg_cerr("%s called with unknown mask\n", __func__); |
| 111 | return 0; |
| 112 | break; |
| 113 | } |
| 114 | } |
| 115 | |
Stefan Tauner | 0ab1e5d | 2014-05-29 11:51:24 +0000 | [diff] [blame] | 116 | static void start_program_jedec_common(const struct flashctx *flash, unsigned int mask) |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 117 | { |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 118 | chipaddr bios = flash->virtual_memory; |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 119 | chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); |
| 120 | chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); |
| 121 | chip_writeb(flash, 0xA0, bios + (0x5555 & mask)); |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 122 | } |
| 123 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 124 | static int probe_jedec_common(struct flashctx *flash, unsigned int mask) |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 125 | { |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 126 | chipaddr bios = flash->virtual_memory; |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 127 | const struct flashchip *chip = flash->chip; |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 128 | uint8_t id1, id2; |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 129 | uint32_t largeid1, largeid2; |
Carl-Daniel Hailfinger | 8130f2d | 2009-05-11 14:40:31 +0000 | [diff] [blame] | 130 | uint32_t flashcontent1, flashcontent2; |
Stefan Tauner | f80419c | 2014-05-02 15:41:42 +0000 | [diff] [blame] | 131 | unsigned int probe_timing_enter, probe_timing_exit; |
Maciej Pijanka | c6e1111 | 2009-06-03 14:46:22 +0000 | [diff] [blame] | 132 | |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 133 | if (chip->probe_timing > 0) |
| 134 | probe_timing_enter = probe_timing_exit = chip->probe_timing; |
| 135 | else if (chip->probe_timing == TIMING_ZERO) { /* No delay. */ |
Maciej Pijanka | c6e1111 | 2009-06-03 14:46:22 +0000 | [diff] [blame] | 136 | probe_timing_enter = probe_timing_exit = 0; |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 137 | } else if (chip->probe_timing == TIMING_FIXME) { /* == _IGNORED */ |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 138 | msg_cdbg("Chip lacks correct probe timing information, " |
Carl-Daniel Hailfinger | 414bd32 | 2009-07-23 01:33:43 +0000 | [diff] [blame] | 139 | "using default 10mS/40uS. "); |
Maciej Pijanka | c6e1111 | 2009-06-03 14:46:22 +0000 | [diff] [blame] | 140 | probe_timing_enter = 10000; |
| 141 | probe_timing_exit = 40; |
| 142 | } else { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 143 | msg_cerr("Chip has negative value in probe_timing, failing " |
Maciej Pijanka | c6e1111 | 2009-06-03 14:46:22 +0000 | [diff] [blame] | 144 | "without chip access\n"); |
| 145 | return 0; |
| 146 | } |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 147 | |
Sean Nelson | f59e263 | 2010-10-20 21:13:19 +0000 | [diff] [blame] | 148 | /* Earlier probes might have been too fast for the chip to enter ID |
| 149 | * mode completely. Allow the chip to finish this before seeing a |
| 150 | * reset command. |
| 151 | */ |
| 152 | if (probe_timing_enter) |
| 153 | programmer_delay(probe_timing_enter); |
| 154 | /* Reset chip to a clean slate */ |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 155 | if ((chip->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET) |
Sean Nelson | f59e263 | 2010-10-20 21:13:19 +0000 | [diff] [blame] | 156 | { |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 157 | chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); |
Sean Nelson | f59e263 | 2010-10-20 21:13:19 +0000 | [diff] [blame] | 158 | if (probe_timing_exit) |
| 159 | programmer_delay(10); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 160 | chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); |
Sean Nelson | f59e263 | 2010-10-20 21:13:19 +0000 | [diff] [blame] | 161 | if (probe_timing_exit) |
| 162 | programmer_delay(10); |
| 163 | } |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 164 | chip_writeb(flash, 0xF0, bios + (0x5555 & mask)); |
Sean Nelson | f59e263 | 2010-10-20 21:13:19 +0000 | [diff] [blame] | 165 | if (probe_timing_exit) |
| 166 | programmer_delay(probe_timing_exit); |
| 167 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 168 | /* Issue JEDEC Product ID Entry command */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 169 | chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); |
Sean Nelson | c12fc71 | 2009-12-17 04:22:40 +0000 | [diff] [blame] | 170 | if (probe_timing_enter) |
| 171 | programmer_delay(10); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 172 | chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); |
Sean Nelson | c12fc71 | 2009-12-17 04:22:40 +0000 | [diff] [blame] | 173 | if (probe_timing_enter) |
| 174 | programmer_delay(10); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 175 | chip_writeb(flash, 0x90, bios + (0x5555 & mask)); |
Sean Nelson | c12fc71 | 2009-12-17 04:22:40 +0000 | [diff] [blame] | 176 | if (probe_timing_enter) |
| 177 | programmer_delay(probe_timing_enter); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 178 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 179 | /* Read product ID */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 180 | id1 = chip_readb(flash, bios); |
| 181 | id2 = chip_readb(flash, bios + 0x01); |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 182 | largeid1 = id1; |
| 183 | largeid2 = id2; |
| 184 | |
| 185 | /* Check if it is a continuation ID, this should be a while loop. */ |
| 186 | if (id1 == 0x7F) { |
| 187 | largeid1 <<= 8; |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 188 | id1 = chip_readb(flash, bios + 0x100); |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 189 | largeid1 |= id1; |
| 190 | } |
| 191 | if (id2 == 0x7F) { |
| 192 | largeid2 <<= 8; |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 193 | id2 = chip_readb(flash, bios + 0x101); |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 194 | largeid2 |= id2; |
| 195 | } |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 196 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 197 | /* Issue JEDEC Product ID Exit command */ |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 198 | if ((chip->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET) |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 199 | { |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 200 | chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 201 | if (probe_timing_exit) |
| 202 | programmer_delay(10); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 203 | chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 204 | if (probe_timing_exit) |
| 205 | programmer_delay(10); |
| 206 | } |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 207 | chip_writeb(flash, 0xF0, bios + (0x5555 & mask)); |
Sean Nelson | c12fc71 | 2009-12-17 04:22:40 +0000 | [diff] [blame] | 208 | if (probe_timing_exit) |
| 209 | programmer_delay(probe_timing_exit); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 210 | |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 211 | msg_cdbg("%s: id1 0x%02x, id2 0x%02x", __func__, largeid1, largeid2); |
Carl-Daniel Hailfinger | a758f51 | 2008-05-14 12:03:06 +0000 | [diff] [blame] | 212 | if (!oddparity(id1)) |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 213 | msg_cdbg(", id1 parity violation"); |
Carl-Daniel Hailfinger | 8130f2d | 2009-05-11 14:40:31 +0000 | [diff] [blame] | 214 | |
| 215 | /* Read the product ID location again. We should now see normal flash contents. */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 216 | flashcontent1 = chip_readb(flash, bios); |
| 217 | flashcontent2 = chip_readb(flash, bios + 0x01); |
Carl-Daniel Hailfinger | 8130f2d | 2009-05-11 14:40:31 +0000 | [diff] [blame] | 218 | |
| 219 | /* Check if it is a continuation ID, this should be a while loop. */ |
| 220 | if (flashcontent1 == 0x7F) { |
| 221 | flashcontent1 <<= 8; |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 222 | flashcontent1 |= chip_readb(flash, bios + 0x100); |
Carl-Daniel Hailfinger | 8130f2d | 2009-05-11 14:40:31 +0000 | [diff] [blame] | 223 | } |
| 224 | if (flashcontent2 == 0x7F) { |
| 225 | flashcontent2 <<= 8; |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 226 | flashcontent2 |= chip_readb(flash, bios + 0x101); |
Carl-Daniel Hailfinger | 8130f2d | 2009-05-11 14:40:31 +0000 | [diff] [blame] | 227 | } |
| 228 | |
| 229 | if (largeid1 == flashcontent1) |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 230 | msg_cdbg(", id1 is normal flash content"); |
Carl-Daniel Hailfinger | 8130f2d | 2009-05-11 14:40:31 +0000 | [diff] [blame] | 231 | if (largeid2 == flashcontent2) |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 232 | msg_cdbg(", id2 is normal flash content"); |
Carl-Daniel Hailfinger | 8130f2d | 2009-05-11 14:40:31 +0000 | [diff] [blame] | 233 | |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 234 | msg_cdbg("\n"); |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 235 | if (largeid1 != chip->manufacture_id || largeid2 != chip->model_id) |
Carl-Daniel Hailfinger | e940466 | 2010-01-09 02:24:17 +0000 | [diff] [blame] | 236 | return 0; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 237 | |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 238 | if (chip->feature_bits & FEATURE_REGISTERMAP) |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 239 | map_flash_registers(flash); |
| 240 | |
Carl-Daniel Hailfinger | e940466 | 2010-01-09 02:24:17 +0000 | [diff] [blame] | 241 | return 1; |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 242 | } |
| 243 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 244 | static int erase_sector_jedec_common(struct flashctx *flash, unsigned int page, |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 245 | unsigned int pagesize, unsigned int mask) |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 246 | { |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 247 | chipaddr bios = flash->virtual_memory; |
Stefan Tauner | f80419c | 2014-05-02 15:41:42 +0000 | [diff] [blame] | 248 | unsigned int delay_us = 0; |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 249 | if(flash->chip->probe_timing != TIMING_ZERO) |
Stefan Tauner | f80419c | 2014-05-02 15:41:42 +0000 | [diff] [blame] | 250 | delay_us = 10; |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 251 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 252 | /* Issue the Sector Erase command */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 253 | chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 254 | programmer_delay(delay_us); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 255 | chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 256 | programmer_delay(delay_us); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 257 | chip_writeb(flash, 0x80, bios + (0x5555 & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 258 | programmer_delay(delay_us); |
Ollie Lho | efa2858 | 2004-12-08 20:10:01 +0000 | [diff] [blame] | 259 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 260 | chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 261 | programmer_delay(delay_us); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 262 | chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 263 | programmer_delay(delay_us); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 264 | chip_writeb(flash, 0x30, bios + page); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 265 | programmer_delay(delay_us); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 266 | |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 267 | /* wait for Toggle bit ready */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 268 | toggle_ready_jedec_slow(flash, bios); |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 269 | |
Carl-Daniel Hailfinger | b4061f6 | 2011-06-26 17:04:16 +0000 | [diff] [blame] | 270 | /* FIXME: Check the status register for errors. */ |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 271 | return 0; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 272 | } |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 273 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 274 | static int erase_block_jedec_common(struct flashctx *flash, unsigned int block, |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 275 | unsigned int blocksize, unsigned int mask) |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 276 | { |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 277 | chipaddr bios = flash->virtual_memory; |
Stefan Tauner | f80419c | 2014-05-02 15:41:42 +0000 | [diff] [blame] | 278 | unsigned int delay_us = 0; |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 279 | if(flash->chip->probe_timing != TIMING_ZERO) |
Stefan Tauner | f80419c | 2014-05-02 15:41:42 +0000 | [diff] [blame] | 280 | delay_us = 10; |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 281 | |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 282 | /* Issue the Sector Erase command */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 283 | chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 284 | programmer_delay(delay_us); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 285 | chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 286 | programmer_delay(delay_us); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 287 | chip_writeb(flash, 0x80, bios + (0x5555 & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 288 | programmer_delay(delay_us); |
Ollie Lho | efa2858 | 2004-12-08 20:10:01 +0000 | [diff] [blame] | 289 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 290 | chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 291 | programmer_delay(delay_us); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 292 | chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 293 | programmer_delay(delay_us); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 294 | chip_writeb(flash, 0x50, bios + block); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 295 | programmer_delay(delay_us); |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 296 | |
| 297 | /* wait for Toggle bit ready */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 298 | toggle_ready_jedec_slow(flash, bios); |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 299 | |
Carl-Daniel Hailfinger | b4061f6 | 2011-06-26 17:04:16 +0000 | [diff] [blame] | 300 | /* FIXME: Check the status register for errors. */ |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 301 | return 0; |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 302 | } |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 303 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 304 | static int erase_chip_jedec_common(struct flashctx *flash, unsigned int mask) |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 305 | { |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 306 | chipaddr bios = flash->virtual_memory; |
Stefan Tauner | f80419c | 2014-05-02 15:41:42 +0000 | [diff] [blame] | 307 | unsigned int delay_us = 0; |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 308 | if(flash->chip->probe_timing != TIMING_ZERO) |
Stefan Tauner | f80419c | 2014-05-02 15:41:42 +0000 | [diff] [blame] | 309 | delay_us = 10; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 310 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 311 | /* Issue the JEDEC Chip Erase command */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 312 | chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 313 | programmer_delay(delay_us); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 314 | chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 315 | programmer_delay(delay_us); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 316 | chip_writeb(flash, 0x80, bios + (0x5555 & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 317 | programmer_delay(delay_us); |
Ollie Lho | efa2858 | 2004-12-08 20:10:01 +0000 | [diff] [blame] | 318 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 319 | chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 320 | programmer_delay(delay_us); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 321 | chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 322 | programmer_delay(delay_us); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 323 | chip_writeb(flash, 0x10, bios + (0x5555 & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 324 | programmer_delay(delay_us); |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 325 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 326 | toggle_ready_jedec_slow(flash, bios); |
Ronald G. Minnich | eaab50b | 2003-09-12 22:41:53 +0000 | [diff] [blame] | 327 | |
Carl-Daniel Hailfinger | b4061f6 | 2011-06-26 17:04:16 +0000 | [diff] [blame] | 328 | /* FIXME: Check the status register for errors. */ |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 329 | return 0; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 330 | } |
| 331 | |
Stefan Tauner | 0ab1e5d | 2014-05-29 11:51:24 +0000 | [diff] [blame] | 332 | static int write_byte_program_jedec_common(const struct flashctx *flash, const uint8_t *src, |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 333 | chipaddr dst, unsigned int mask) |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 334 | { |
| 335 | int tried = 0, failed = 0; |
| 336 | chipaddr bios = flash->virtual_memory; |
| 337 | |
| 338 | /* If the data is 0xFF, don't program it and don't complain. */ |
| 339 | if (*src == 0xFF) { |
| 340 | return 0; |
| 341 | } |
| 342 | |
| 343 | retry: |
| 344 | /* Issue JEDEC Byte Program command */ |
| 345 | start_program_jedec_common(flash, mask); |
| 346 | |
| 347 | /* transfer data from source to destination */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 348 | chip_writeb(flash, *src, dst); |
| 349 | toggle_ready_jedec(flash, bios); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 350 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 351 | if (chip_readb(flash, dst) != *src && tried++ < MAX_REFLASH_TRIES) { |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 352 | goto retry; |
| 353 | } |
| 354 | |
| 355 | if (tried >= MAX_REFLASH_TRIES) |
| 356 | failed = 1; |
| 357 | |
| 358 | return failed; |
| 359 | } |
| 360 | |
Carl-Daniel Hailfinger | 75a58f9 | 2010-10-13 22:26:56 +0000 | [diff] [blame] | 361 | /* chunksize is 1 */ |
Stefan Tauner | 0ab1e5d | 2014-05-29 11:51:24 +0000 | [diff] [blame] | 362 | int write_jedec_1(struct flashctx *flash, const uint8_t *src, unsigned int start, |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 363 | unsigned int len) |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 364 | { |
| 365 | int i, failed = 0; |
Carl-Daniel Hailfinger | b30a5ed | 2010-10-10 14:02:27 +0000 | [diff] [blame] | 366 | chipaddr dst = flash->virtual_memory + start; |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 367 | chipaddr olddst; |
Stefan Tauner | c69c9c8 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 368 | unsigned int mask; |
Carl-Daniel Hailfinger | 79e6757 | 2010-10-13 21:49:30 +0000 | [diff] [blame] | 369 | |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 370 | mask = getaddrmask(flash->chip); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 371 | |
| 372 | olddst = dst; |
Carl-Daniel Hailfinger | b30a5ed | 2010-10-10 14:02:27 +0000 | [diff] [blame] | 373 | for (i = 0; i < len; i++) { |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 374 | if (write_byte_program_jedec_common(flash, src, dst, mask)) |
| 375 | failed = 1; |
| 376 | dst++, src++; |
| 377 | } |
| 378 | if (failed) |
Stefan Tauner | c233375 | 2013-07-13 23:31:37 +0000 | [diff] [blame] | 379 | msg_cerr(" writing sector at 0x%" PRIxPTR " failed!\n", olddst); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 380 | |
| 381 | return failed; |
| 382 | } |
| 383 | |
Stefan Tauner | 0ab1e5d | 2014-05-29 11:51:24 +0000 | [diff] [blame] | 384 | static int write_page_write_jedec_common(struct flashctx *flash, const uint8_t *src, |
Stefan Tauner | 0554ca5 | 2013-07-25 22:54:25 +0000 | [diff] [blame] | 385 | unsigned int start, unsigned int page_size) |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 386 | { |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 387 | int i, tried = 0, failed; |
Stefan Tauner | 0ab1e5d | 2014-05-29 11:51:24 +0000 | [diff] [blame] | 388 | const uint8_t *s = src; |
Urja Rannikko | 0c854c0 | 2009-06-25 13:57:31 +0000 | [diff] [blame] | 389 | chipaddr bios = flash->virtual_memory; |
| 390 | chipaddr dst = bios + start; |
| 391 | chipaddr d = dst; |
Stefan Tauner | c69c9c8 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 392 | unsigned int mask; |
Carl-Daniel Hailfinger | 79e6757 | 2010-10-13 21:49:30 +0000 | [diff] [blame] | 393 | |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 394 | mask = getaddrmask(flash->chip); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 395 | |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 396 | retry: |
Uwe Hermann | 4e3d0b3 | 2010-03-25 23:18:41 +0000 | [diff] [blame] | 397 | /* Issue JEDEC Start Program command */ |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 398 | start_program_jedec_common(flash, mask); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 399 | |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 400 | /* transfer data from source to destination */ |
Carl-Daniel Hailfinger | 8a8a226 | 2009-11-14 03:48:33 +0000 | [diff] [blame] | 401 | for (i = 0; i < page_size; i++) { |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 402 | /* If the data is 0xFF, don't program it */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 403 | if (*src != 0xFF) |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 404 | chip_writeb(flash, *src, dst); |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 405 | dst++; |
| 406 | src++; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 407 | } |
| 408 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 409 | toggle_ready_jedec(flash, dst - 1); |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 410 | |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 411 | dst = d; |
| 412 | src = s; |
Stefan Tauner | 78ffbea | 2012-10-27 15:36:56 +0000 | [diff] [blame] | 413 | failed = verify_range(flash, src, start, page_size); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 414 | |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 415 | if (failed && tried++ < MAX_REFLASH_TRIES) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 416 | msg_cerr("retrying.\n"); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 417 | goto retry; |
| 418 | } |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 419 | if (failed) { |
Stefan Tauner | c233375 | 2013-07-13 23:31:37 +0000 | [diff] [blame] | 420 | msg_cerr(" page 0x%" PRIxPTR " failed!\n", (d - bios) / page_size); |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 421 | } |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 422 | return failed; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 423 | } |
| 424 | |
Carl-Daniel Hailfinger | 75a58f9 | 2010-10-13 22:26:56 +0000 | [diff] [blame] | 425 | /* chunksize is page_size */ |
Carl-Daniel Hailfinger | 79e6757 | 2010-10-13 21:49:30 +0000 | [diff] [blame] | 426 | /* |
| 427 | * Write a part of the flash chip. |
| 428 | * FIXME: Use the chunk code from Michael Karcher instead. |
| 429 | * This function is a slightly modified copy of spi_write_chunked. |
| 430 | * Each page is written separately in chunks with a maximum size of chunksize. |
| 431 | */ |
Stefan Tauner | 0ab1e5d | 2014-05-29 11:51:24 +0000 | [diff] [blame] | 432 | int write_jedec(struct flashctx *flash, const uint8_t *buf, unsigned int start, |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 433 | int unsigned len) |
Carl-Daniel Hailfinger | 4bf4e79 | 2010-01-09 03:15:50 +0000 | [diff] [blame] | 434 | { |
Stefan Tauner | c69c9c8 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 435 | unsigned int i, starthere, lenhere; |
Carl-Daniel Hailfinger | 79e6757 | 2010-10-13 21:49:30 +0000 | [diff] [blame] | 436 | /* FIXME: page_size is the wrong variable. We need max_writechunk_size |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 437 | * in struct flashctx to do this properly. All chips using |
Carl-Daniel Hailfinger | 79e6757 | 2010-10-13 21:49:30 +0000 | [diff] [blame] | 438 | * write_jedec have page_size set to max_writechunk_size, so |
| 439 | * we're OK for now. |
| 440 | */ |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 441 | unsigned int page_size = flash->chip->page_size; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 442 | |
Carl-Daniel Hailfinger | 79e6757 | 2010-10-13 21:49:30 +0000 | [diff] [blame] | 443 | /* Warning: This loop has a very unusual condition and body. |
| 444 | * The loop needs to go through each page with at least one affected |
| 445 | * byte. The lowest page number is (start / page_size) since that |
| 446 | * division rounds down. The highest page number we want is the page |
| 447 | * where the last byte of the range lives. That last byte has the |
| 448 | * address (start + len - 1), thus the highest page number is |
| 449 | * (start + len - 1) / page_size. Since we want to include that last |
| 450 | * page as well, the loop condition uses <=. |
| 451 | */ |
| 452 | for (i = start / page_size; i <= (start + len - 1) / page_size; i++) { |
| 453 | /* Byte position of the first byte in the range in this page. */ |
| 454 | /* starthere is an offset to the base address of the chip. */ |
| 455 | starthere = max(start, i * page_size); |
| 456 | /* Length of bytes in the range in this page. */ |
| 457 | lenhere = min(start + len, (i + 1) * page_size) - starthere; |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 458 | |
Carl-Daniel Hailfinger | 79e6757 | 2010-10-13 21:49:30 +0000 | [diff] [blame] | 459 | if (write_page_write_jedec_common(flash, buf + starthere - start, starthere, lenhere)) |
| 460 | return 1; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 461 | } |
Ronald G. Minnich | eaab50b | 2003-09-12 22:41:53 +0000 | [diff] [blame] | 462 | |
Carl-Daniel Hailfinger | 79e6757 | 2010-10-13 21:49:30 +0000 | [diff] [blame] | 463 | return 0; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 464 | } |
Michael Karcher | 1c296ca | 2009-11-27 17:49:42 +0000 | [diff] [blame] | 465 | |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 466 | /* erase chip with block_erase() prototype */ |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 467 | int erase_chip_block_jedec(struct flashctx *flash, unsigned int addr, |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 468 | unsigned int blocksize) |
| 469 | { |
Stefan Tauner | c69c9c8 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 470 | unsigned int mask; |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 471 | |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 472 | mask = getaddrmask(flash->chip); |
| 473 | if ((addr != 0) || (blocksize != flash->chip->total_size * 1024)) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 474 | msg_cerr("%s called with incorrect arguments\n", |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 475 | __func__); |
| 476 | return -1; |
| 477 | } |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 478 | return erase_chip_jedec_common(flash, mask); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 479 | } |
| 480 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 481 | int probe_jedec(struct flashctx *flash) |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 482 | { |
Stefan Tauner | c69c9c8 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 483 | unsigned int mask; |
Carl-Daniel Hailfinger | 4bf4e79 | 2010-01-09 03:15:50 +0000 | [diff] [blame] | 484 | |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 485 | mask = getaddrmask(flash->chip); |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 486 | return probe_jedec_common(flash, mask); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 487 | } |
| 488 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 489 | int erase_sector_jedec(struct flashctx *flash, unsigned int page, |
| 490 | unsigned int size) |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 491 | { |
Stefan Tauner | c69c9c8 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 492 | unsigned int mask; |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 493 | |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 494 | mask = getaddrmask(flash->chip); |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 495 | return erase_sector_jedec_common(flash, page, size, mask); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 496 | } |
| 497 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 498 | int erase_block_jedec(struct flashctx *flash, unsigned int page, |
| 499 | unsigned int size) |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 500 | { |
Stefan Tauner | c69c9c8 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 501 | unsigned int mask; |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 502 | |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 503 | mask = getaddrmask(flash->chip); |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 504 | return erase_block_jedec_common(flash, page, size, mask); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 505 | } |
| 506 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 507 | int erase_chip_jedec(struct flashctx *flash) |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 508 | { |
Stefan Tauner | c69c9c8 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 509 | unsigned int mask; |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 510 | |
Carl-Daniel Hailfinger | 5a7cb84 | 2012-08-25 01:17:58 +0000 | [diff] [blame] | 511 | mask = getaddrmask(flash->chip); |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 512 | return erase_chip_jedec_common(flash, mask); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 513 | } |
Carl-Daniel Hailfinger | ef3ac8a | 2014-08-03 13:05:34 +0000 | [diff] [blame^] | 514 | |
| 515 | struct unlockblock { |
| 516 | unsigned int size; |
| 517 | unsigned int count; |
| 518 | }; |
| 519 | |
| 520 | typedef int (*unlockblock_func)(const struct flashctx *flash, chipaddr offset); |
| 521 | static int regspace2_walk_unlockblocks(const struct flashctx *flash, const struct unlockblock *block, unlockblock_func func) |
| 522 | { |
| 523 | chipaddr off = flash->virtual_registers + 2; |
| 524 | while (block->count != 0) { |
| 525 | unsigned int j; |
| 526 | for (j = 0; j < block->count; j++) { |
| 527 | if (func(flash, off)) |
| 528 | return -1; |
| 529 | off += block->size; |
| 530 | } |
| 531 | block++; |
| 532 | } |
| 533 | return 0; |
| 534 | } |
| 535 | |
| 536 | #define REG2_RWLOCK ((1 << 2) | (1 << 0)) |
| 537 | #define REG2_LOCKDOWN (1 << 1) |
| 538 | #define REG2_MASK (REG2_RWLOCK | REG2_LOCKDOWN) |
| 539 | |
| 540 | static int printlock_regspace2_block(const struct flashctx *flash, chipaddr offset) |
| 541 | { |
| 542 | chipaddr wrprotect = flash->virtual_registers + offset + 2; |
| 543 | uint8_t state = chip_readb(flash, wrprotect); |
| 544 | msg_cdbg("Lock status of block at 0x%0*" PRIxPTR " is ", PRIxPTR_WIDTH, offset); |
| 545 | switch (state & REG2_MASK) { |
| 546 | case 0: |
| 547 | msg_cdbg("Full Access.\n"); |
| 548 | break; |
| 549 | case 1: |
| 550 | msg_cdbg("Write Lock (Default State).\n"); |
| 551 | break; |
| 552 | case 2: |
| 553 | msg_cdbg("Locked Open (Full Access, Locked Down).\n"); |
| 554 | break; |
| 555 | case 3: |
| 556 | msg_cdbg("Write Lock, Locked Down.\n"); |
| 557 | break; |
| 558 | case 4: |
| 559 | msg_cdbg("Read Lock.\n"); |
| 560 | break; |
| 561 | case 5: |
| 562 | msg_cdbg("Read/Write Lock.\n"); |
| 563 | break; |
| 564 | case 6: |
| 565 | msg_cdbg("Read Lock, Locked Down.\n"); |
| 566 | break; |
| 567 | case 7: |
| 568 | msg_cdbg("Read/Write Lock, Locked Down.\n"); |
| 569 | break; |
| 570 | } |
| 571 | return 0; |
| 572 | } |
| 573 | |
| 574 | int printlock_regspace2_blocks(const struct flashctx *flash, const struct unlockblock *blocks) |
| 575 | { |
| 576 | return regspace2_walk_unlockblocks(flash, blocks, &printlock_regspace2_block); |
| 577 | } |
| 578 | |
| 579 | static int printlock_regspace2_uniform(struct flashctx *flash, unsigned long block_size) |
| 580 | { |
| 581 | const unsigned int elems = flash->chip->total_size * 1024 / block_size; |
| 582 | struct unlockblock blocks[2] = {{.size = block_size, .count = elems}}; |
| 583 | return regspace2_walk_unlockblocks(flash, blocks, &printlock_regspace2_block); |
| 584 | } |
| 585 | |
| 586 | int printlock_regspace2_uniform_64k(struct flashctx *flash) |
| 587 | { |
| 588 | return printlock_regspace2_uniform(flash, 64 * 1024); |
| 589 | } |
| 590 | |
| 591 | int printlock_regspace2_block_eraser_0(struct flashctx *flash) |
| 592 | { |
| 593 | // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). |
| 594 | const struct unlockblock *unlockblocks = |
| 595 | (const struct unlockblock *)flash->chip->block_erasers[0].eraseblocks; |
| 596 | return regspace2_walk_unlockblocks(flash, unlockblocks, &printlock_regspace2_block); |
| 597 | } |
| 598 | |
| 599 | int printlock_regspace2_block_eraser_1(struct flashctx *flash) |
| 600 | { |
| 601 | // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). |
| 602 | const struct unlockblock *unlockblocks = |
| 603 | (const struct unlockblock *)flash->chip->block_erasers[1].eraseblocks; |
| 604 | return regspace2_walk_unlockblocks(flash, unlockblocks, &printlock_regspace2_block); |
| 605 | } |
| 606 | |
| 607 | static int changelock_regspace2_block(const struct flashctx *flash, chipaddr offset, uint8_t new_bits) |
| 608 | { |
| 609 | chipaddr wrprotect = flash->virtual_registers + offset + 2; |
| 610 | uint8_t old; |
| 611 | |
| 612 | if (new_bits & ~REG2_MASK) { |
| 613 | msg_cerr("Invalid locking change 0x%02x requested at 0x%0*" PRIxPTR "! " |
| 614 | "Please report a bug at flashrom@flashrom.org\n", |
| 615 | new_bits, PRIxPTR_WIDTH, offset); |
| 616 | return -1; |
| 617 | } |
| 618 | old = chip_readb(flash, wrprotect); |
| 619 | /* Early exist if no change (of read/write/lockdown) was requested. */ |
| 620 | if (((old ^ new_bits) & REG2_MASK) == 0) { |
| 621 | msg_cdbg2("Locking status at 0x%0*" PRIxPTR " not changed\n", PRIxPTR_WIDTH, offset); |
| 622 | return 0; |
| 623 | } |
| 624 | /* Normally lockdowns can not be cleared. Try nevertheless if requested. */ |
| 625 | if ((old & REG2_LOCKDOWN) && !(new_bits & REG2_LOCKDOWN)) { |
| 626 | chip_writeb(flash, old & ~REG2_LOCKDOWN, wrprotect); |
| 627 | if (chip_readb(flash, wrprotect) != (old & ~REG2_LOCKDOWN)) { |
| 628 | msg_cerr("Lockdown can't be removed at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); |
| 629 | return -1; |
| 630 | } |
| 631 | } |
| 632 | /* Change read or write lock? */ |
| 633 | if ((old ^ new_bits) & REG2_RWLOCK) { |
| 634 | /* Do not lockdown yet. */ |
| 635 | msg_cdbg("Changing locking status at 0x%0*" PRIxPTR " to 0x%02x\n", PRIxPTR_WIDTH, offset, new_bits & REG2_RWLOCK); |
| 636 | chip_writeb(flash, new_bits & REG2_RWLOCK, wrprotect); |
| 637 | if (chip_readb(flash, wrprotect) != (new_bits & REG2_RWLOCK)) { |
| 638 | msg_cerr("Locking status change FAILED at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); |
| 639 | return -1; |
| 640 | } |
| 641 | } |
| 642 | /* Enable lockdown if requested. */ |
| 643 | if (!(old & REG2_LOCKDOWN) && (new_bits & REG2_LOCKDOWN)) { |
| 644 | msg_cdbg("Enabling lockdown at 0x%0*" PRIxPTR "\n", PRIxPTR_WIDTH, offset); |
| 645 | chip_writeb(flash, new_bits, wrprotect); |
| 646 | if (chip_readb(flash, wrprotect) != new_bits) { |
| 647 | msg_cerr("Enabling lockdown FAILED at 0x%0*" PRIxPTR "!\n", PRIxPTR_WIDTH, offset); |
| 648 | return -1; |
| 649 | } |
| 650 | } |
| 651 | |
| 652 | return 0; |
| 653 | } |
| 654 | |
| 655 | int unlock_regspace2_block(const struct flashctx *flash, chipaddr off) |
| 656 | { |
| 657 | chipaddr wrprotect = flash->virtual_registers + off + 2; |
| 658 | uint8_t old = chip_readb(flash, wrprotect); |
| 659 | /* We don't care for the lockdown bit as long as the RW locks are 0 after we're done */ |
| 660 | return changelock_regspace2_block(flash, off, old & ~REG2_RWLOCK); |
| 661 | } |
| 662 | |
| 663 | static int unlock_regspace2_uniform(struct flashctx *flash, unsigned long block_size) |
| 664 | { |
| 665 | const unsigned int elems = flash->chip->total_size * 1024 / block_size; |
| 666 | struct unlockblock blocks[2] = {{.size = block_size, .count = elems}}; |
| 667 | return regspace2_walk_unlockblocks(flash, blocks, &unlock_regspace2_block); |
| 668 | } |
| 669 | |
| 670 | int unlock_regspace2_uniform_64k(struct flashctx *flash) |
| 671 | { |
| 672 | return unlock_regspace2_uniform(flash, 64 * 1024); |
| 673 | } |
| 674 | |
| 675 | int unlock_regspace2_uniform_32k(struct flashctx *flash) |
| 676 | { |
| 677 | return unlock_regspace2_uniform(flash, 32 * 1024); |
| 678 | } |
| 679 | |
| 680 | int unlock_regspace2_block_eraser_0(struct flashctx *flash) |
| 681 | { |
| 682 | // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). |
| 683 | const struct unlockblock *unlockblocks = |
| 684 | (const struct unlockblock *)flash->chip->block_erasers[0].eraseblocks; |
| 685 | return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block); |
| 686 | } |
| 687 | |
| 688 | int unlock_regspace2_block_eraser_1(struct flashctx *flash) |
| 689 | { |
| 690 | // FIXME: this depends on the eraseblocks not to be filled up completely (i.e. to be null-terminated). |
| 691 | const struct unlockblock *unlockblocks = |
| 692 | (const struct unlockblock *)flash->chip->block_erasers[1].eraseblocks; |
| 693 | return regspace2_walk_unlockblocks(flash, unlockblocks, &unlock_regspace2_block); |
| 694 | } |
| 695 | |