Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 1 | /* |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 2 | * This file is part of the flashrom project. |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 3 | * |
Uwe Hermann | d22a1d4 | 2007-09-09 20:21:05 +0000 | [diff] [blame] | 4 | * Copyright (C) 2000 Silicon Integrated System Corporation |
| 5 | * Copyright (C) 2006 Giampiero Giancipoli <gianci@email.it> |
| 6 | * Copyright (C) 2006 coresystems GmbH <info@coresystems.de> |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 7 | * Copyright (C) 2007 Carl-Daniel Hailfinger |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 8 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 13 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 18 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 22 | */ |
| 23 | |
| 24 | #include "flash.h" |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 25 | |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 26 | #define MAX_REFLASH_TRIES 0x10 |
| 27 | |
Carl-Daniel Hailfinger | a758f51 | 2008-05-14 12:03:06 +0000 | [diff] [blame] | 28 | /* Check one byte for odd parity */ |
| 29 | uint8_t oddparity(uint8_t val) |
| 30 | { |
| 31 | val = (val ^ (val >> 4)) & 0xf; |
| 32 | val = (val ^ (val >> 2)) & 0x3; |
| 33 | return (val ^ (val >> 1)) & 0x1; |
| 34 | } |
| 35 | |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 36 | void toggle_ready_jedec(chipaddr dst) |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 37 | { |
| 38 | unsigned int i = 0; |
| 39 | uint8_t tmp1, tmp2; |
| 40 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 41 | tmp1 = chip_readb(dst) & 0x40; |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 42 | |
| 43 | while (i++ < 0xFFFFFFF) { |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 44 | tmp2 = chip_readb(dst) & 0x40; |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 45 | if (tmp1 == tmp2) { |
| 46 | break; |
| 47 | } |
| 48 | tmp1 = tmp2; |
| 49 | } |
| 50 | } |
| 51 | |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 52 | void data_polling_jedec(chipaddr dst, uint8_t data) |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 53 | { |
| 54 | unsigned int i = 0; |
| 55 | uint8_t tmp; |
| 56 | |
| 57 | data &= 0x80; |
| 58 | |
| 59 | while (i++ < 0xFFFFFFF) { |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 60 | tmp = chip_readb(dst) & 0x80; |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 61 | if (tmp == data) { |
| 62 | break; |
| 63 | } |
| 64 | } |
| 65 | } |
| 66 | |
Michael Karcher | 972cec2 | 2009-11-26 14:50:52 +0000 | [diff] [blame] | 67 | void start_program_jedec(chipaddr bios) |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 68 | { |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 69 | chip_writeb(0xAA, bios + 0x5555); |
| 70 | chip_writeb(0x55, bios + 0x2AAA); |
| 71 | chip_writeb(0xA0, bios + 0x5555); |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 72 | } |
| 73 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 74 | int probe_jedec(struct flashchip *flash) |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 75 | { |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 76 | chipaddr bios = flash->virtual_memory; |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 77 | uint8_t id1, id2; |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 78 | uint32_t largeid1, largeid2; |
Carl-Daniel Hailfinger | 8130f2d | 2009-05-11 14:40:31 +0000 | [diff] [blame] | 79 | uint32_t flashcontent1, flashcontent2; |
Maciej Pijanka | c6e1111 | 2009-06-03 14:46:22 +0000 | [diff] [blame] | 80 | int probe_timing_enter, probe_timing_exit; |
| 81 | |
| 82 | if (flash->probe_timing > 0) |
| 83 | probe_timing_enter = probe_timing_exit = flash->probe_timing; |
| 84 | else if (flash->probe_timing == TIMING_ZERO) { /* No delay. */ |
| 85 | probe_timing_enter = probe_timing_exit = 0; |
| 86 | } else if (flash->probe_timing == TIMING_FIXME) { /* == _IGNORED */ |
| 87 | printf_debug("Chip lacks correct probe timing information, " |
Carl-Daniel Hailfinger | 414bd32 | 2009-07-23 01:33:43 +0000 | [diff] [blame] | 88 | "using default 10mS/40uS. "); |
Maciej Pijanka | c6e1111 | 2009-06-03 14:46:22 +0000 | [diff] [blame] | 89 | probe_timing_enter = 10000; |
| 90 | probe_timing_exit = 40; |
| 91 | } else { |
| 92 | printf("Chip has negative value in probe_timing, failing " |
| 93 | "without chip access\n"); |
| 94 | return 0; |
| 95 | } |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 96 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 97 | /* Issue JEDEC Product ID Entry command */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 98 | chip_writeb(0xAA, bios + 0x5555); |
Sean Nelson | c12fc71 | 2009-12-17 04:22:40 +0000 | [diff] [blame^] | 99 | if (probe_timing_enter) |
| 100 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 101 | chip_writeb(0x55, bios + 0x2AAA); |
Sean Nelson | c12fc71 | 2009-12-17 04:22:40 +0000 | [diff] [blame^] | 102 | if (probe_timing_enter) |
| 103 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 104 | chip_writeb(0x90, bios + 0x5555); |
Sean Nelson | c12fc71 | 2009-12-17 04:22:40 +0000 | [diff] [blame^] | 105 | if (probe_timing_enter) |
| 106 | programmer_delay(probe_timing_enter); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 107 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 108 | /* Read product ID */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 109 | id1 = chip_readb(bios); |
| 110 | id2 = chip_readb(bios + 0x01); |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 111 | largeid1 = id1; |
| 112 | largeid2 = id2; |
| 113 | |
| 114 | /* Check if it is a continuation ID, this should be a while loop. */ |
| 115 | if (id1 == 0x7F) { |
| 116 | largeid1 <<= 8; |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 117 | id1 = chip_readb(bios + 0x100); |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 118 | largeid1 |= id1; |
| 119 | } |
| 120 | if (id2 == 0x7F) { |
| 121 | largeid2 <<= 8; |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 122 | id2 = chip_readb(bios + 0x101); |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 123 | largeid2 |= id2; |
| 124 | } |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 125 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 126 | /* Issue JEDEC Product ID Exit command */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 127 | chip_writeb(0xAA, bios + 0x5555); |
Sean Nelson | c12fc71 | 2009-12-17 04:22:40 +0000 | [diff] [blame^] | 128 | if (probe_timing_exit) |
| 129 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 130 | chip_writeb(0x55, bios + 0x2AAA); |
Sean Nelson | c12fc71 | 2009-12-17 04:22:40 +0000 | [diff] [blame^] | 131 | if (probe_timing_exit) |
| 132 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 133 | chip_writeb(0xF0, bios + 0x5555); |
Sean Nelson | c12fc71 | 2009-12-17 04:22:40 +0000 | [diff] [blame^] | 134 | if (probe_timing_exit) |
| 135 | programmer_delay(probe_timing_exit); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 136 | |
Uwe Hermann | 04aa59a | 2009-09-02 22:09:00 +0000 | [diff] [blame] | 137 | printf_debug("%s: id1 0x%02x, id2 0x%02x", __func__, largeid1, largeid2); |
Carl-Daniel Hailfinger | a758f51 | 2008-05-14 12:03:06 +0000 | [diff] [blame] | 138 | if (!oddparity(id1)) |
| 139 | printf_debug(", id1 parity violation"); |
Carl-Daniel Hailfinger | 8130f2d | 2009-05-11 14:40:31 +0000 | [diff] [blame] | 140 | |
| 141 | /* Read the product ID location again. We should now see normal flash contents. */ |
| 142 | flashcontent1 = chip_readb(bios); |
| 143 | flashcontent2 = chip_readb(bios + 0x01); |
| 144 | |
| 145 | /* Check if it is a continuation ID, this should be a while loop. */ |
| 146 | if (flashcontent1 == 0x7F) { |
| 147 | flashcontent1 <<= 8; |
| 148 | flashcontent1 |= chip_readb(bios + 0x100); |
| 149 | } |
| 150 | if (flashcontent2 == 0x7F) { |
| 151 | flashcontent2 <<= 8; |
| 152 | flashcontent2 |= chip_readb(bios + 0x101); |
| 153 | } |
| 154 | |
| 155 | if (largeid1 == flashcontent1) |
| 156 | printf_debug(", id1 is normal flash content"); |
| 157 | if (largeid2 == flashcontent2) |
| 158 | printf_debug(", id2 is normal flash content"); |
| 159 | |
Carl-Daniel Hailfinger | a758f51 | 2008-05-14 12:03:06 +0000 | [diff] [blame] | 160 | printf_debug("\n"); |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 161 | if (largeid1 == flash->manufacture_id && largeid2 == flash->model_id) |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 162 | return 1; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 163 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 164 | return 0; |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 165 | } |
| 166 | |
Carl-Daniel Hailfinger | a06287c | 2009-09-23 22:01:33 +0000 | [diff] [blame] | 167 | int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int pagesize) |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 168 | { |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 169 | chipaddr bios = flash->virtual_memory; |
| 170 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 171 | /* Issue the Sector Erase command */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 172 | chip_writeb(0xAA, bios + 0x5555); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 173 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 174 | chip_writeb(0x55, bios + 0x2AAA); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 175 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 176 | chip_writeb(0x80, bios + 0x5555); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 177 | programmer_delay(10); |
Ollie Lho | efa2858 | 2004-12-08 20:10:01 +0000 | [diff] [blame] | 178 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 179 | chip_writeb(0xAA, bios + 0x5555); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 180 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 181 | chip_writeb(0x55, bios + 0x2AAA); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 182 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 183 | chip_writeb(0x30, bios + page); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 184 | programmer_delay(10); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 185 | |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 186 | /* wait for Toggle bit ready */ |
| 187 | toggle_ready_jedec(bios); |
| 188 | |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 189 | if (check_erased_range(flash, page, pagesize)) { |
| 190 | fprintf(stderr,"ERASE FAILED!\n"); |
| 191 | return -1; |
| 192 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 193 | return 0; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 194 | } |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 195 | |
Carl-Daniel Hailfinger | a06287c | 2009-09-23 22:01:33 +0000 | [diff] [blame] | 196 | int erase_block_jedec(struct flashchip *flash, unsigned int block, unsigned int blocksize) |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 197 | { |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 198 | chipaddr bios = flash->virtual_memory; |
| 199 | |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 200 | /* Issue the Sector Erase command */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 201 | chip_writeb(0xAA, bios + 0x5555); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 202 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 203 | chip_writeb(0x55, bios + 0x2AAA); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 204 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 205 | chip_writeb(0x80, bios + 0x5555); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 206 | programmer_delay(10); |
Ollie Lho | efa2858 | 2004-12-08 20:10:01 +0000 | [diff] [blame] | 207 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 208 | chip_writeb(0xAA, bios + 0x5555); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 209 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 210 | chip_writeb(0x55, bios + 0x2AAA); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 211 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 212 | chip_writeb(0x50, bios + block); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 213 | programmer_delay(10); |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 214 | |
| 215 | /* wait for Toggle bit ready */ |
| 216 | toggle_ready_jedec(bios); |
| 217 | |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 218 | if (check_erased_range(flash, block, blocksize)) { |
| 219 | fprintf(stderr,"ERASE FAILED!\n"); |
| 220 | return -1; |
| 221 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 222 | return 0; |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 223 | } |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 224 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 225 | int erase_chip_jedec(struct flashchip *flash) |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 226 | { |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 227 | int total_size = flash->total_size * 1024; |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 228 | chipaddr bios = flash->virtual_memory; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 229 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 230 | /* Issue the JEDEC Chip Erase command */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 231 | chip_writeb(0xAA, bios + 0x5555); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 232 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 233 | chip_writeb(0x55, bios + 0x2AAA); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 234 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 235 | chip_writeb(0x80, bios + 0x5555); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 236 | programmer_delay(10); |
Ollie Lho | efa2858 | 2004-12-08 20:10:01 +0000 | [diff] [blame] | 237 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 238 | chip_writeb(0xAA, bios + 0x5555); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 239 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 240 | chip_writeb(0x55, bios + 0x2AAA); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 241 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 242 | chip_writeb(0x10, bios + 0x5555); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 243 | programmer_delay(10); |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 244 | |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 245 | toggle_ready_jedec(bios); |
Ronald G. Minnich | eaab50b | 2003-09-12 22:41:53 +0000 | [diff] [blame] | 246 | |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 247 | if (check_erased_range(flash, 0, total_size)) { |
| 248 | fprintf(stderr,"ERASE FAILED!\n"); |
| 249 | return -1; |
| 250 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 251 | return 0; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 252 | } |
| 253 | |
Urja Rannikko | 0c854c0 | 2009-06-25 13:57:31 +0000 | [diff] [blame] | 254 | int write_page_write_jedec(struct flashchip *flash, uint8_t *src, |
| 255 | int start, int page_size) |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 256 | { |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 257 | int i, tried = 0, failed; |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 258 | uint8_t *s = src; |
Urja Rannikko | 0c854c0 | 2009-06-25 13:57:31 +0000 | [diff] [blame] | 259 | chipaddr bios = flash->virtual_memory; |
| 260 | chipaddr dst = bios + start; |
| 261 | chipaddr d = dst; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 262 | |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 263 | retry: |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 264 | /* Issue JEDEC Data Unprotect comand */ |
Michael Karcher | 972cec2 | 2009-11-26 14:50:52 +0000 | [diff] [blame] | 265 | start_program_jedec(bios); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 266 | |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 267 | /* transfer data from source to destination */ |
Carl-Daniel Hailfinger | 8a8a226 | 2009-11-14 03:48:33 +0000 | [diff] [blame] | 268 | for (i = 0; i < page_size; i++) { |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 269 | /* If the data is 0xFF, don't program it */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 270 | if (*src != 0xFF) |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 271 | chip_writeb(*src, dst); |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 272 | dst++; |
| 273 | src++; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 274 | } |
| 275 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 276 | toggle_ready_jedec(dst - 1); |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 277 | |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 278 | dst = d; |
| 279 | src = s; |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 280 | failed = verify_range(flash, src, start, page_size, NULL); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 281 | |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 282 | if (failed && tried++ < MAX_REFLASH_TRIES) { |
Carl-Daniel Hailfinger | 8a8a226 | 2009-11-14 03:48:33 +0000 | [diff] [blame] | 283 | fprintf(stderr, "retrying.\n"); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 284 | goto retry; |
| 285 | } |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 286 | if (failed) { |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 287 | fprintf(stderr, " page 0x%lx failed!\n", |
| 288 | (d - bios) / page_size); |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 289 | } |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 290 | return failed; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 291 | } |
| 292 | |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 293 | int write_byte_program_jedec(chipaddr bios, uint8_t *src, |
| 294 | chipaddr dst) |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 295 | { |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 296 | int tried = 0, failed = 0; |
Ollie Lho | 1b8b660 | 2004-12-08 02:10:33 +0000 | [diff] [blame] | 297 | |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 298 | /* If the data is 0xFF, don't program it and don't complain. */ |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 299 | if (*src == 0xFF) { |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 300 | return 0; |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 301 | } |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 302 | |
Ollie Lho | 1b8b660 | 2004-12-08 02:10:33 +0000 | [diff] [blame] | 303 | retry: |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 304 | /* Issue JEDEC Byte Program command */ |
Michael Karcher | 972cec2 | 2009-11-26 14:50:52 +0000 | [diff] [blame] | 305 | start_program_jedec(bios); |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 306 | |
| 307 | /* transfer data from source to destination */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 308 | chip_writeb(*src, dst); |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 309 | toggle_ready_jedec(bios); |
Ollie Lho | 8b8897a | 2004-03-27 00:18:15 +0000 | [diff] [blame] | 310 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 311 | if (chip_readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 312 | goto retry; |
| 313 | } |
Ollie Lho | 1b8b660 | 2004-12-08 02:10:33 +0000 | [diff] [blame] | 314 | |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 315 | if (tried >= MAX_REFLASH_TRIES) |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 316 | failed = 1; |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 317 | |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 318 | return failed; |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 319 | } |
| 320 | |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 321 | int write_sector_jedec(chipaddr bios, uint8_t *src, |
| 322 | chipaddr dst, unsigned int page_size) |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 323 | { |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 324 | int i, failed = 0; |
| 325 | chipaddr olddst; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 326 | |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 327 | olddst = dst; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 328 | for (i = 0; i < page_size; i++) { |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 329 | if (write_byte_program_jedec(bios, src, dst)) |
| 330 | failed = 1; |
Ollie Lho | 8b8897a | 2004-03-27 00:18:15 +0000 | [diff] [blame] | 331 | dst++, src++; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 332 | } |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 333 | if (failed) |
| 334 | fprintf(stderr, " writing sector at 0x%lx failed!\n", olddst); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 335 | |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 336 | return failed; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 337 | } |
| 338 | |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 339 | int write_jedec(struct flashchip *flash, uint8_t *buf) |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 340 | { |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 341 | int i, failed = 0; |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 342 | int total_size = flash->total_size * 1024; |
| 343 | int page_size = flash->page_size; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 344 | |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 345 | if (erase_chip_jedec(flash)) { |
| 346 | fprintf(stderr,"ERASE FAILED!\n"); |
| 347 | return -1; |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 348 | } |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 349 | |
Uwe Hermann | a502dce | 2007-10-17 23:55:15 +0000 | [diff] [blame] | 350 | printf("Programming page: "); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 351 | for (i = 0; i < total_size / page_size; i++) { |
| 352 | printf("%04d at address: 0x%08x", i, i * page_size); |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 353 | if (write_page_write_jedec(flash, buf + i * page_size, |
| 354 | i * page_size, page_size)) |
| 355 | failed = 1; |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 356 | printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 357 | } |
| 358 | printf("\n"); |
Ronald G. Minnich | eaab50b | 2003-09-12 22:41:53 +0000 | [diff] [blame] | 359 | |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 360 | return failed; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 361 | } |
Michael Karcher | 1c296ca | 2009-11-27 17:49:42 +0000 | [diff] [blame] | 362 | |
| 363 | int write_jedec_1(struct flashchip *flash, uint8_t * buf) |
| 364 | { |
| 365 | int i; |
| 366 | chipaddr bios = flash->virtual_memory; |
| 367 | chipaddr dst = bios; |
| 368 | |
| 369 | programmer_delay(10); |
| 370 | if (erase_flash(flash)) { |
| 371 | fprintf(stderr, "ERASE FAILED!\n"); |
| 372 | return -1; |
| 373 | } |
| 374 | |
| 375 | printf("Programming page: "); |
| 376 | for (i = 0; i < flash->total_size; i++) { |
| 377 | if ((i & 0x3) == 0) |
| 378 | printf("address: 0x%08lx", (unsigned long)i * 1024); |
| 379 | |
| 380 | write_sector_jedec(bios, buf + i * 1024, dst + i * 1024, 1024); |
| 381 | |
| 382 | if ((i & 0x3) == 0) |
| 383 | printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); |
| 384 | } |
| 385 | |
| 386 | printf("\n"); |
| 387 | return 0; |
| 388 | } |