Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 1 | /* |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 2 | * This file is part of the flashrom project. |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 3 | * |
Uwe Hermann | d22a1d4 | 2007-09-09 20:21:05 +0000 | [diff] [blame] | 4 | * Copyright (C) 2000 Silicon Integrated System Corporation |
| 5 | * Copyright (C) 2006 Giampiero Giancipoli <gianci@email.it> |
| 6 | * Copyright (C) 2006 coresystems GmbH <info@coresystems.de> |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 7 | * Copyright (C) 2007 Carl-Daniel Hailfinger |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 8 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 13 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 18 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 22 | */ |
| 23 | |
| 24 | #include "flash.h" |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 25 | |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 26 | #define MAX_REFLASH_TRIES 0x10 |
| 27 | |
Carl-Daniel Hailfinger | a758f51 | 2008-05-14 12:03:06 +0000 | [diff] [blame] | 28 | /* Check one byte for odd parity */ |
| 29 | uint8_t oddparity(uint8_t val) |
| 30 | { |
| 31 | val = (val ^ (val >> 4)) & 0xf; |
| 32 | val = (val ^ (val >> 2)) & 0x3; |
| 33 | return (val ^ (val >> 1)) & 0x1; |
| 34 | } |
| 35 | |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 36 | void toggle_ready_jedec(chipaddr dst) |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 37 | { |
| 38 | unsigned int i = 0; |
| 39 | uint8_t tmp1, tmp2; |
| 40 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 41 | tmp1 = chip_readb(dst) & 0x40; |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 42 | |
| 43 | while (i++ < 0xFFFFFFF) { |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 44 | tmp2 = chip_readb(dst) & 0x40; |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 45 | if (tmp1 == tmp2) { |
| 46 | break; |
| 47 | } |
| 48 | tmp1 = tmp2; |
| 49 | } |
| 50 | } |
| 51 | |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 52 | void data_polling_jedec(chipaddr dst, uint8_t data) |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 53 | { |
| 54 | unsigned int i = 0; |
| 55 | uint8_t tmp; |
| 56 | |
| 57 | data &= 0x80; |
| 58 | |
| 59 | while (i++ < 0xFFFFFFF) { |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 60 | tmp = chip_readb(dst) & 0x80; |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 61 | if (tmp == data) { |
| 62 | break; |
| 63 | } |
| 64 | } |
| 65 | } |
| 66 | |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 67 | void unprotect_jedec(chipaddr bios) |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 68 | { |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 69 | chip_writeb(0xAA, bios + 0x5555); |
| 70 | chip_writeb(0x55, bios + 0x2AAA); |
| 71 | chip_writeb(0x80, bios + 0x5555); |
| 72 | chip_writeb(0xAA, bios + 0x5555); |
| 73 | chip_writeb(0x55, bios + 0x2AAA); |
| 74 | chip_writeb(0x20, bios + 0x5555); |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 75 | |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 76 | programmer_delay(200); |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 77 | } |
| 78 | |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 79 | void protect_jedec(chipaddr bios) |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 80 | { |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 81 | chip_writeb(0xAA, bios + 0x5555); |
| 82 | chip_writeb(0x55, bios + 0x2AAA); |
| 83 | chip_writeb(0xA0, bios + 0x5555); |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 84 | |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 85 | programmer_delay(200); |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 86 | } |
| 87 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 88 | int probe_jedec(struct flashchip *flash) |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 89 | { |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 90 | chipaddr bios = flash->virtual_memory; |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 91 | uint8_t id1, id2; |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 92 | uint32_t largeid1, largeid2; |
Carl-Daniel Hailfinger | 8130f2d | 2009-05-11 14:40:31 +0000 | [diff] [blame] | 93 | uint32_t flashcontent1, flashcontent2; |
Maciej Pijanka | c6e1111 | 2009-06-03 14:46:22 +0000 | [diff] [blame] | 94 | int probe_timing_enter, probe_timing_exit; |
| 95 | |
| 96 | if (flash->probe_timing > 0) |
| 97 | probe_timing_enter = probe_timing_exit = flash->probe_timing; |
| 98 | else if (flash->probe_timing == TIMING_ZERO) { /* No delay. */ |
| 99 | probe_timing_enter = probe_timing_exit = 0; |
| 100 | } else if (flash->probe_timing == TIMING_FIXME) { /* == _IGNORED */ |
| 101 | printf_debug("Chip lacks correct probe timing information, " |
Carl-Daniel Hailfinger | 414bd32 | 2009-07-23 01:33:43 +0000 | [diff] [blame] | 102 | "using default 10mS/40uS. "); |
Maciej Pijanka | c6e1111 | 2009-06-03 14:46:22 +0000 | [diff] [blame] | 103 | probe_timing_enter = 10000; |
| 104 | probe_timing_exit = 40; |
| 105 | } else { |
| 106 | printf("Chip has negative value in probe_timing, failing " |
| 107 | "without chip access\n"); |
| 108 | return 0; |
| 109 | } |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 110 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 111 | /* Issue JEDEC Product ID Entry command */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 112 | chip_writeb(0xAA, bios + 0x5555); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 113 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 114 | chip_writeb(0x55, bios + 0x2AAA); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 115 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 116 | chip_writeb(0x90, bios + 0x5555); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 117 | programmer_delay(probe_timing_enter); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 118 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 119 | /* Read product ID */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 120 | id1 = chip_readb(bios); |
| 121 | id2 = chip_readb(bios + 0x01); |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 122 | largeid1 = id1; |
| 123 | largeid2 = id2; |
| 124 | |
| 125 | /* Check if it is a continuation ID, this should be a while loop. */ |
| 126 | if (id1 == 0x7F) { |
| 127 | largeid1 <<= 8; |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 128 | id1 = chip_readb(bios + 0x100); |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 129 | largeid1 |= id1; |
| 130 | } |
| 131 | if (id2 == 0x7F) { |
| 132 | largeid2 <<= 8; |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 133 | id2 = chip_readb(bios + 0x101); |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 134 | largeid2 |= id2; |
| 135 | } |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 136 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 137 | /* Issue JEDEC Product ID Exit command */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 138 | chip_writeb(0xAA, bios + 0x5555); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 139 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 140 | chip_writeb(0x55, bios + 0x2AAA); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 141 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 142 | chip_writeb(0xF0, bios + 0x5555); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 143 | programmer_delay(probe_timing_exit); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 144 | |
Uwe Hermann | 04aa59a | 2009-09-02 22:09:00 +0000 | [diff] [blame] | 145 | printf_debug("%s: id1 0x%02x, id2 0x%02x", __func__, largeid1, largeid2); |
Carl-Daniel Hailfinger | a758f51 | 2008-05-14 12:03:06 +0000 | [diff] [blame] | 146 | if (!oddparity(id1)) |
| 147 | printf_debug(", id1 parity violation"); |
Carl-Daniel Hailfinger | 8130f2d | 2009-05-11 14:40:31 +0000 | [diff] [blame] | 148 | |
| 149 | /* Read the product ID location again. We should now see normal flash contents. */ |
| 150 | flashcontent1 = chip_readb(bios); |
| 151 | flashcontent2 = chip_readb(bios + 0x01); |
| 152 | |
| 153 | /* Check if it is a continuation ID, this should be a while loop. */ |
| 154 | if (flashcontent1 == 0x7F) { |
| 155 | flashcontent1 <<= 8; |
| 156 | flashcontent1 |= chip_readb(bios + 0x100); |
| 157 | } |
| 158 | if (flashcontent2 == 0x7F) { |
| 159 | flashcontent2 <<= 8; |
| 160 | flashcontent2 |= chip_readb(bios + 0x101); |
| 161 | } |
| 162 | |
| 163 | if (largeid1 == flashcontent1) |
| 164 | printf_debug(", id1 is normal flash content"); |
| 165 | if (largeid2 == flashcontent2) |
| 166 | printf_debug(", id2 is normal flash content"); |
| 167 | |
Carl-Daniel Hailfinger | a758f51 | 2008-05-14 12:03:06 +0000 | [diff] [blame] | 168 | printf_debug("\n"); |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 169 | if (largeid1 == flash->manufacture_id && largeid2 == flash->model_id) |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 170 | return 1; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 171 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 172 | return 0; |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 173 | } |
| 174 | |
Carl-Daniel Hailfinger | a06287c | 2009-09-23 22:01:33 +0000 | [diff] [blame] | 175 | int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int pagesize) |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 176 | { |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 177 | chipaddr bios = flash->virtual_memory; |
| 178 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 179 | /* Issue the Sector Erase command */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 180 | chip_writeb(0xAA, bios + 0x5555); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 181 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 182 | chip_writeb(0x55, bios + 0x2AAA); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 183 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 184 | chip_writeb(0x80, bios + 0x5555); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 185 | programmer_delay(10); |
Ollie Lho | efa2858 | 2004-12-08 20:10:01 +0000 | [diff] [blame] | 186 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 187 | chip_writeb(0xAA, bios + 0x5555); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 188 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 189 | chip_writeb(0x55, bios + 0x2AAA); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 190 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 191 | chip_writeb(0x30, bios + page); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 192 | programmer_delay(10); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 193 | |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 194 | /* wait for Toggle bit ready */ |
| 195 | toggle_ready_jedec(bios); |
| 196 | |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 197 | if (check_erased_range(flash, page, pagesize)) { |
| 198 | fprintf(stderr,"ERASE FAILED!\n"); |
| 199 | return -1; |
| 200 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 201 | return 0; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 202 | } |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 203 | |
Carl-Daniel Hailfinger | a06287c | 2009-09-23 22:01:33 +0000 | [diff] [blame] | 204 | int erase_block_jedec(struct flashchip *flash, unsigned int block, unsigned int blocksize) |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 205 | { |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 206 | chipaddr bios = flash->virtual_memory; |
| 207 | |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 208 | /* Issue the Sector Erase command */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 209 | chip_writeb(0xAA, bios + 0x5555); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 210 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 211 | chip_writeb(0x55, bios + 0x2AAA); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 212 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 213 | chip_writeb(0x80, bios + 0x5555); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 214 | programmer_delay(10); |
Ollie Lho | efa2858 | 2004-12-08 20:10:01 +0000 | [diff] [blame] | 215 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 216 | chip_writeb(0xAA, bios + 0x5555); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 217 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 218 | chip_writeb(0x55, bios + 0x2AAA); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 219 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 220 | chip_writeb(0x50, bios + block); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 221 | programmer_delay(10); |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 222 | |
| 223 | /* wait for Toggle bit ready */ |
| 224 | toggle_ready_jedec(bios); |
| 225 | |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 226 | if (check_erased_range(flash, block, blocksize)) { |
| 227 | fprintf(stderr,"ERASE FAILED!\n"); |
| 228 | return -1; |
| 229 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 230 | return 0; |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 231 | } |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 232 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 233 | int erase_chip_jedec(struct flashchip *flash) |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 234 | { |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 235 | int total_size = flash->total_size * 1024; |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 236 | chipaddr bios = flash->virtual_memory; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 237 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 238 | /* Issue the JEDEC Chip Erase command */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 239 | chip_writeb(0xAA, bios + 0x5555); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 240 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 241 | chip_writeb(0x55, bios + 0x2AAA); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 242 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 243 | chip_writeb(0x80, bios + 0x5555); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 244 | programmer_delay(10); |
Ollie Lho | efa2858 | 2004-12-08 20:10:01 +0000 | [diff] [blame] | 245 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 246 | chip_writeb(0xAA, bios + 0x5555); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 247 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 248 | chip_writeb(0x55, bios + 0x2AAA); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 249 | programmer_delay(10); |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 250 | chip_writeb(0x10, bios + 0x5555); |
Carl-Daniel Hailfinger | ca8bfc6 | 2009-06-05 17:48:08 +0000 | [diff] [blame] | 251 | programmer_delay(10); |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 252 | |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 253 | toggle_ready_jedec(bios); |
Ronald G. Minnich | eaab50b | 2003-09-12 22:41:53 +0000 | [diff] [blame] | 254 | |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 255 | if (check_erased_range(flash, 0, total_size)) { |
| 256 | fprintf(stderr,"ERASE FAILED!\n"); |
| 257 | return -1; |
| 258 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 259 | return 0; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 260 | } |
| 261 | |
Urja Rannikko | 0c854c0 | 2009-06-25 13:57:31 +0000 | [diff] [blame] | 262 | int write_page_write_jedec(struct flashchip *flash, uint8_t *src, |
| 263 | int start, int page_size) |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 264 | { |
Carl-Daniel Hailfinger | 8a8a226 | 2009-11-14 03:48:33 +0000 | [diff] [blame^] | 265 | int i, tried = 0, ok; |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 266 | uint8_t *s = src; |
Urja Rannikko | 0c854c0 | 2009-06-25 13:57:31 +0000 | [diff] [blame] | 267 | chipaddr bios = flash->virtual_memory; |
| 268 | chipaddr dst = bios + start; |
| 269 | chipaddr d = dst; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 270 | |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 271 | retry: |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 272 | /* Issue JEDEC Data Unprotect comand */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 273 | chip_writeb(0xAA, bios + 0x5555); |
| 274 | chip_writeb(0x55, bios + 0x2AAA); |
| 275 | chip_writeb(0xA0, bios + 0x5555); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 276 | |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 277 | /* transfer data from source to destination */ |
Carl-Daniel Hailfinger | 8a8a226 | 2009-11-14 03:48:33 +0000 | [diff] [blame^] | 278 | for (i = 0; i < page_size; i++) { |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 279 | /* If the data is 0xFF, don't program it */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 280 | if (*src != 0xFF) |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 281 | chip_writeb(*src, dst); |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 282 | dst++; |
| 283 | src++; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 284 | } |
| 285 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 286 | toggle_ready_jedec(dst - 1); |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 287 | |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 288 | dst = d; |
| 289 | src = s; |
Urja Rannikko | 0c854c0 | 2009-06-25 13:57:31 +0000 | [diff] [blame] | 290 | ok = !verify_range(flash, src, start, page_size, NULL); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 291 | |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 292 | if (!ok && tried++ < MAX_REFLASH_TRIES) { |
Carl-Daniel Hailfinger | 8a8a226 | 2009-11-14 03:48:33 +0000 | [diff] [blame^] | 293 | fprintf(stderr, "retrying.\n"); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 294 | goto retry; |
| 295 | } |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 296 | if (!ok) { |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 297 | fprintf(stderr, " page 0x%lx failed!\n", |
| 298 | (d - bios) / page_size); |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 299 | } |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 300 | return !ok; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 301 | } |
| 302 | |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 303 | int write_byte_program_jedec(chipaddr bios, uint8_t *src, |
| 304 | chipaddr dst) |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 305 | { |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 306 | int tried = 0, ok = 1; |
Ollie Lho | 1b8b660 | 2004-12-08 02:10:33 +0000 | [diff] [blame] | 307 | |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 308 | /* If the data is 0xFF, don't program it */ |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 309 | if (*src == 0xFF) { |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 310 | return -1; |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 311 | } |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 312 | |
Ollie Lho | 1b8b660 | 2004-12-08 02:10:33 +0000 | [diff] [blame] | 313 | retry: |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 314 | /* Issue JEDEC Byte Program command */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 315 | chip_writeb(0xAA, bios + 0x5555); |
| 316 | chip_writeb(0x55, bios + 0x2AAA); |
| 317 | chip_writeb(0xA0, bios + 0x5555); |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 318 | |
| 319 | /* transfer data from source to destination */ |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 320 | chip_writeb(*src, dst); |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 321 | toggle_ready_jedec(bios); |
Ollie Lho | 8b8897a | 2004-03-27 00:18:15 +0000 | [diff] [blame] | 322 | |
Carl-Daniel Hailfinger | 0472f3d | 2009-03-06 22:26:00 +0000 | [diff] [blame] | 323 | if (chip_readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) { |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 324 | goto retry; |
| 325 | } |
Ollie Lho | 1b8b660 | 2004-12-08 02:10:33 +0000 | [diff] [blame] | 326 | |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 327 | if (tried >= MAX_REFLASH_TRIES) |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 328 | ok = 0; |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 329 | |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 330 | return !ok; |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 331 | } |
| 332 | |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 333 | int write_sector_jedec(chipaddr bios, uint8_t *src, |
| 334 | chipaddr dst, unsigned int page_size) |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 335 | { |
| 336 | int i; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 337 | |
| 338 | for (i = 0; i < page_size; i++) { |
Ollie Lho | 8b8897a | 2004-03-27 00:18:15 +0000 | [diff] [blame] | 339 | write_byte_program_jedec(bios, src, dst); |
| 340 | dst++, src++; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 341 | } |
| 342 | |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 343 | return 0; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 344 | } |
| 345 | |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 346 | int write_jedec(struct flashchip *flash, uint8_t *buf) |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 347 | { |
| 348 | int i; |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 349 | int total_size = flash->total_size * 1024; |
| 350 | int page_size = flash->page_size; |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 351 | chipaddr bios = flash->virtual_memory; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 352 | |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 353 | if (erase_chip_jedec(flash)) { |
| 354 | fprintf(stderr,"ERASE FAILED!\n"); |
| 355 | return -1; |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 356 | } |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 357 | |
Uwe Hermann | a502dce | 2007-10-17 23:55:15 +0000 | [diff] [blame] | 358 | printf("Programming page: "); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 359 | for (i = 0; i < total_size / page_size; i++) { |
| 360 | printf("%04d at address: 0x%08x", i, i * page_size); |
Urja Rannikko | 0c854c0 | 2009-06-25 13:57:31 +0000 | [diff] [blame] | 361 | write_page_write_jedec(flash, buf + i * page_size, |
| 362 | i * page_size, page_size); |
Ollie Lho | 070647d | 2004-03-22 22:19:17 +0000 | [diff] [blame] | 363 | printf("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b"); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 364 | } |
| 365 | printf("\n"); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 366 | protect_jedec(bios); |
Ronald G. Minnich | eaab50b | 2003-09-12 22:41:53 +0000 | [diff] [blame] | 367 | |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 368 | return 0; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 369 | } |