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Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00003 *
Uwe Hermannd22a1d42007-09-09 20:21:05 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2006 Giampiero Giancipoli <gianci@email.it>
6 * Copyright (C) 2006 coresystems GmbH <info@coresystems.de>
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Sean Nelsonc57a9202010-01-04 17:15:23 +00008 * Copyright (C) 2009 Sean Nelson <audiohacked@gmail.com>
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00009 *
Uwe Hermannd1107642007-08-29 17:52:32 +000010 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000014 *
Uwe Hermannd1107642007-08-29 17:52:32 +000015 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000019 *
Uwe Hermannd1107642007-08-29 17:52:32 +000020 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000023 */
24
25#include "flash.h"
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000026
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +000027#define MAX_REFLASH_TRIES 0x10
Sean Nelsonc57a9202010-01-04 17:15:23 +000028#define MASK_FULL 0xffff
29#define MASK_2AA 0x7ff
Sean Nelson35727f72010-01-28 23:55:12 +000030#define MASK_AAA 0xfff
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +000031
Carl-Daniel Hailfingera758f512008-05-14 12:03:06 +000032/* Check one byte for odd parity */
33uint8_t oddparity(uint8_t val)
34{
35 val = (val ^ (val >> 4)) & 0xf;
36 val = (val ^ (val >> 2)) & 0x3;
37 return (val ^ (val >> 1)) & 0x1;
38}
39
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +000040static void toggle_ready_jedec_common(chipaddr dst, int delay)
Uwe Hermann51582f22007-08-23 10:20:40 +000041{
42 unsigned int i = 0;
43 uint8_t tmp1, tmp2;
44
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000045 tmp1 = chip_readb(dst) & 0x40;
Uwe Hermann51582f22007-08-23 10:20:40 +000046
47 while (i++ < 0xFFFFFFF) {
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000048 if (delay)
49 programmer_delay(delay);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000050 tmp2 = chip_readb(dst) & 0x40;
Uwe Hermann51582f22007-08-23 10:20:40 +000051 if (tmp1 == tmp2) {
52 break;
53 }
54 tmp1 = tmp2;
55 }
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000056 if (i > 0x100000)
Sean Nelsoned479d22010-03-24 23:14:32 +000057 msg_cdbg("%s: excessive loops, i=0x%x\n", __func__, i);
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000058}
59
60void toggle_ready_jedec(chipaddr dst)
61{
62 toggle_ready_jedec_common(dst, 0);
63}
64
65/* Some chips require a minimum delay between toggle bit reads.
66 * The Winbond W39V040C wants 50 ms between reads on sector erase toggle,
67 * but experiments show that 2 ms are already enough. Pick a safety factor
68 * of 4 and use an 8 ms delay.
69 * Given that erase is slow on all chips, it is recommended to use
70 * toggle_ready_jedec_slow in erase functions.
71 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +000072static void toggle_ready_jedec_slow(chipaddr dst)
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000073{
74 toggle_ready_jedec_common(dst, 8 * 1000);
Uwe Hermann51582f22007-08-23 10:20:40 +000075}
76
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000077void data_polling_jedec(chipaddr dst, uint8_t data)
Uwe Hermann51582f22007-08-23 10:20:40 +000078{
79 unsigned int i = 0;
80 uint8_t tmp;
81
82 data &= 0x80;
83
84 while (i++ < 0xFFFFFFF) {
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000085 tmp = chip_readb(dst) & 0x80;
Uwe Hermann51582f22007-08-23 10:20:40 +000086 if (tmp == data) {
87 break;
88 }
89 }
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000090 if (i > 0x100000)
Sean Nelsoned479d22010-03-24 23:14:32 +000091 msg_cdbg("%s: excessive loops, i=0x%x\n", __func__, i);
Uwe Hermann51582f22007-08-23 10:20:40 +000092}
93
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +000094static unsigned int getaddrmask(struct flashctx *flash)
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +000095{
96 switch (flash->feature_bits & FEATURE_ADDR_MASK) {
97 case FEATURE_ADDR_FULL:
98 return MASK_FULL;
99 break;
100 case FEATURE_ADDR_2AA:
101 return MASK_2AA;
102 break;
103 case FEATURE_ADDR_AAA:
104 return MASK_AAA;
105 break;
106 default:
107 msg_cerr("%s called with unknown mask\n", __func__);
108 return 0;
109 break;
110 }
111}
112
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000113static void start_program_jedec_common(struct flashctx *flash, unsigned int mask)
Uwe Hermann51582f22007-08-23 10:20:40 +0000114{
Sean Nelsonc57a9202010-01-04 17:15:23 +0000115 chipaddr bios = flash->virtual_memory;
116 chip_writeb(0xAA, bios + (0x5555 & mask));
117 chip_writeb(0x55, bios + (0x2AAA & mask));
118 chip_writeb(0xA0, bios + (0x5555 & mask));
Uwe Hermann51582f22007-08-23 10:20:40 +0000119}
120
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000121static int probe_jedec_common(struct flashctx *flash, unsigned int mask)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000122{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000123 chipaddr bios = flash->virtual_memory;
Ollie Lho184a4042005-11-26 21:55:36 +0000124 uint8_t id1, id2;
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000125 uint32_t largeid1, largeid2;
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +0000126 uint32_t flashcontent1, flashcontent2;
Maciej Pijankac6e11112009-06-03 14:46:22 +0000127 int probe_timing_enter, probe_timing_exit;
128
129 if (flash->probe_timing > 0)
130 probe_timing_enter = probe_timing_exit = flash->probe_timing;
131 else if (flash->probe_timing == TIMING_ZERO) { /* No delay. */
132 probe_timing_enter = probe_timing_exit = 0;
133 } else if (flash->probe_timing == TIMING_FIXME) { /* == _IGNORED */
Sean Nelsoned479d22010-03-24 23:14:32 +0000134 msg_cdbg("Chip lacks correct probe timing information, "
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000135 "using default 10mS/40uS. ");
Maciej Pijankac6e11112009-06-03 14:46:22 +0000136 probe_timing_enter = 10000;
137 probe_timing_exit = 40;
138 } else {
Sean Nelsoned479d22010-03-24 23:14:32 +0000139 msg_cerr("Chip has negative value in probe_timing, failing "
Maciej Pijankac6e11112009-06-03 14:46:22 +0000140 "without chip access\n");
141 return 0;
142 }
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000143
Sean Nelsonf59e2632010-10-20 21:13:19 +0000144 /* Earlier probes might have been too fast for the chip to enter ID
145 * mode completely. Allow the chip to finish this before seeing a
146 * reset command.
147 */
148 if (probe_timing_enter)
149 programmer_delay(probe_timing_enter);
150 /* Reset chip to a clean slate */
151 if ((flash->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET)
152 {
153 chip_writeb(0xAA, bios + (0x5555 & mask));
154 if (probe_timing_exit)
155 programmer_delay(10);
156 chip_writeb(0x55, bios + (0x2AAA & mask));
157 if (probe_timing_exit)
158 programmer_delay(10);
159 }
160 chip_writeb(0xF0, bios + (0x5555 & mask));
161 if (probe_timing_exit)
162 programmer_delay(probe_timing_exit);
163
Ollie Lho761bf1b2004-03-20 16:46:10 +0000164 /* Issue JEDEC Product ID Entry command */
Sean Nelsonc57a9202010-01-04 17:15:23 +0000165 chip_writeb(0xAA, bios + (0x5555 & mask));
Sean Nelsonc12fc712009-12-17 04:22:40 +0000166 if (probe_timing_enter)
167 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000168 chip_writeb(0x55, bios + (0x2AAA & mask));
Sean Nelsonc12fc712009-12-17 04:22:40 +0000169 if (probe_timing_enter)
170 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000171 chip_writeb(0x90, bios + (0x5555 & mask));
Sean Nelsonc12fc712009-12-17 04:22:40 +0000172 if (probe_timing_enter)
173 programmer_delay(probe_timing_enter);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000174
Ollie Lho761bf1b2004-03-20 16:46:10 +0000175 /* Read product ID */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000176 id1 = chip_readb(bios);
177 id2 = chip_readb(bios + 0x01);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000178 largeid1 = id1;
179 largeid2 = id2;
180
181 /* Check if it is a continuation ID, this should be a while loop. */
182 if (id1 == 0x7F) {
183 largeid1 <<= 8;
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000184 id1 = chip_readb(bios + 0x100);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000185 largeid1 |= id1;
186 }
187 if (id2 == 0x7F) {
188 largeid2 <<= 8;
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000189 id2 = chip_readb(bios + 0x101);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000190 largeid2 |= id2;
191 }
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000192
Ollie Lho761bf1b2004-03-20 16:46:10 +0000193 /* Issue JEDEC Product ID Exit command */
Sean Nelsonf59e2632010-10-20 21:13:19 +0000194 if ((flash->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET)
Sean Nelsonc57a9202010-01-04 17:15:23 +0000195 {
196 chip_writeb(0xAA, bios + (0x5555 & mask));
197 if (probe_timing_exit)
198 programmer_delay(10);
199 chip_writeb(0x55, bios + (0x2AAA & mask));
200 if (probe_timing_exit)
201 programmer_delay(10);
202 }
203 chip_writeb(0xF0, bios + (0x5555 & mask));
Sean Nelsonc12fc712009-12-17 04:22:40 +0000204 if (probe_timing_exit)
205 programmer_delay(probe_timing_exit);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000206
Sean Nelsoned479d22010-03-24 23:14:32 +0000207 msg_cdbg("%s: id1 0x%02x, id2 0x%02x", __func__, largeid1, largeid2);
Carl-Daniel Hailfingera758f512008-05-14 12:03:06 +0000208 if (!oddparity(id1))
Sean Nelsoned479d22010-03-24 23:14:32 +0000209 msg_cdbg(", id1 parity violation");
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +0000210
211 /* Read the product ID location again. We should now see normal flash contents. */
212 flashcontent1 = chip_readb(bios);
213 flashcontent2 = chip_readb(bios + 0x01);
214
215 /* Check if it is a continuation ID, this should be a while loop. */
216 if (flashcontent1 == 0x7F) {
217 flashcontent1 <<= 8;
218 flashcontent1 |= chip_readb(bios + 0x100);
219 }
220 if (flashcontent2 == 0x7F) {
221 flashcontent2 <<= 8;
222 flashcontent2 |= chip_readb(bios + 0x101);
223 }
224
225 if (largeid1 == flashcontent1)
Sean Nelsoned479d22010-03-24 23:14:32 +0000226 msg_cdbg(", id1 is normal flash content");
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +0000227 if (largeid2 == flashcontent2)
Sean Nelsoned479d22010-03-24 23:14:32 +0000228 msg_cdbg(", id2 is normal flash content");
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +0000229
Sean Nelsoned479d22010-03-24 23:14:32 +0000230 msg_cdbg("\n");
Carl-Daniel Hailfingere9404662010-01-09 02:24:17 +0000231 if (largeid1 != flash->manufacture_id || largeid2 != flash->model_id)
232 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000233
Sean Nelsonc57a9202010-01-04 17:15:23 +0000234 if (flash->feature_bits & FEATURE_REGISTERMAP)
235 map_flash_registers(flash);
236
Carl-Daniel Hailfingere9404662010-01-09 02:24:17 +0000237 return 1;
Ollie Lho73eca802004-03-19 22:10:07 +0000238}
239
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000240static int erase_sector_jedec_common(struct flashctx *flash, unsigned int page,
Sean Nelsonc57a9202010-01-04 17:15:23 +0000241 unsigned int pagesize, unsigned int mask)
Ollie Lho73eca802004-03-19 22:10:07 +0000242{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000243 chipaddr bios = flash->virtual_memory;
Michael Karcher880e8672011-04-15 00:03:37 +0000244 int delay_us = 0;
245 if(flash->probe_timing != TIMING_ZERO)
246 delay_us = 10;
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000247
Ollie Lho761bf1b2004-03-20 16:46:10 +0000248 /* Issue the Sector Erase command */
Sean Nelsonc57a9202010-01-04 17:15:23 +0000249 chip_writeb(0xAA, bios + (0x5555 & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000250 programmer_delay(delay_us);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000251 chip_writeb(0x55, bios + (0x2AAA & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000252 programmer_delay(delay_us);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000253 chip_writeb(0x80, bios + (0x5555 & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000254 programmer_delay(delay_us);
Ollie Lhoefa28582004-12-08 20:10:01 +0000255
Sean Nelsonc57a9202010-01-04 17:15:23 +0000256 chip_writeb(0xAA, bios + (0x5555 & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000257 programmer_delay(delay_us);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000258 chip_writeb(0x55, bios + (0x2AAA & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000259 programmer_delay(delay_us);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000260 chip_writeb(0x30, bios + page);
Michael Karcher880e8672011-04-15 00:03:37 +0000261 programmer_delay(delay_us);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000262
Ollie Lho73eca802004-03-19 22:10:07 +0000263 /* wait for Toggle bit ready */
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +0000264 toggle_ready_jedec_slow(bios);
Ollie Lho73eca802004-03-19 22:10:07 +0000265
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000266 /* FIXME: Check the status register for errors. */
Uwe Hermannffec5f32007-08-23 16:08:21 +0000267 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000268}
Ollie Lho98bea8a2004-12-07 03:15:51 +0000269
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000270static int erase_block_jedec_common(struct flashctx *flash, unsigned int block,
Sean Nelsonc57a9202010-01-04 17:15:23 +0000271 unsigned int blocksize, unsigned int mask)
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000272{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000273 chipaddr bios = flash->virtual_memory;
Michael Karcher880e8672011-04-15 00:03:37 +0000274 int delay_us = 0;
275 if(flash->probe_timing != TIMING_ZERO)
276 delay_us = 10;
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000277
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000278 /* Issue the Sector Erase command */
Sean Nelsonc57a9202010-01-04 17:15:23 +0000279 chip_writeb(0xAA, bios + (0x5555 & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000280 programmer_delay(delay_us);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000281 chip_writeb(0x55, bios + (0x2AAA & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000282 programmer_delay(delay_us);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000283 chip_writeb(0x80, bios + (0x5555 & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000284 programmer_delay(delay_us);
Ollie Lhoefa28582004-12-08 20:10:01 +0000285
Sean Nelsonc57a9202010-01-04 17:15:23 +0000286 chip_writeb(0xAA, bios + (0x5555 & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000287 programmer_delay(delay_us);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000288 chip_writeb(0x55, bios + (0x2AAA & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000289 programmer_delay(delay_us);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000290 chip_writeb(0x50, bios + block);
Michael Karcher880e8672011-04-15 00:03:37 +0000291 programmer_delay(delay_us);
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000292
293 /* wait for Toggle bit ready */
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +0000294 toggle_ready_jedec_slow(bios);
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000295
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000296 /* FIXME: Check the status register for errors. */
Uwe Hermannffec5f32007-08-23 16:08:21 +0000297 return 0;
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000298}
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000299
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000300static int erase_chip_jedec_common(struct flashctx *flash, unsigned int mask)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000301{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000302 chipaddr bios = flash->virtual_memory;
Michael Karcher880e8672011-04-15 00:03:37 +0000303 int delay_us = 0;
304 if(flash->probe_timing != TIMING_ZERO)
305 delay_us = 10;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000306
Ollie Lho761bf1b2004-03-20 16:46:10 +0000307 /* Issue the JEDEC Chip Erase command */
Sean Nelsonc57a9202010-01-04 17:15:23 +0000308 chip_writeb(0xAA, bios + (0x5555 & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000309 programmer_delay(delay_us);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000310 chip_writeb(0x55, bios + (0x2AAA & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000311 programmer_delay(delay_us);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000312 chip_writeb(0x80, bios + (0x5555 & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000313 programmer_delay(delay_us);
Ollie Lhoefa28582004-12-08 20:10:01 +0000314
Sean Nelsonc57a9202010-01-04 17:15:23 +0000315 chip_writeb(0xAA, bios + (0x5555 & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000316 programmer_delay(delay_us);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000317 chip_writeb(0x55, bios + (0x2AAA & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000318 programmer_delay(delay_us);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000319 chip_writeb(0x10, bios + (0x5555 & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000320 programmer_delay(delay_us);
Ollie Lho73eca802004-03-19 22:10:07 +0000321
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +0000322 toggle_ready_jedec_slow(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000323
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000324 /* FIXME: Check the status register for errors. */
Uwe Hermannffec5f32007-08-23 16:08:21 +0000325 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000326}
327
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000328static int write_byte_program_jedec_common(struct flashctx *flash, uint8_t *src,
Sean Nelsonc57a9202010-01-04 17:15:23 +0000329 chipaddr dst, unsigned int mask)
330{
331 int tried = 0, failed = 0;
332 chipaddr bios = flash->virtual_memory;
333
334 /* If the data is 0xFF, don't program it and don't complain. */
335 if (*src == 0xFF) {
336 return 0;
337 }
338
339retry:
340 /* Issue JEDEC Byte Program command */
341 start_program_jedec_common(flash, mask);
342
343 /* transfer data from source to destination */
344 chip_writeb(*src, dst);
345 toggle_ready_jedec(bios);
346
347 if (chip_readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) {
348 goto retry;
349 }
350
351 if (tried >= MAX_REFLASH_TRIES)
352 failed = 1;
353
354 return failed;
355}
356
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000357/* chunksize is 1 */
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000358int write_jedec_1(struct flashctx *flash, uint8_t *src, unsigned int start, unsigned int len)
Sean Nelsonc57a9202010-01-04 17:15:23 +0000359{
360 int i, failed = 0;
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000361 chipaddr dst = flash->virtual_memory + start;
Sean Nelsonc57a9202010-01-04 17:15:23 +0000362 chipaddr olddst;
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000363 unsigned int mask;
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000364
365 mask = getaddrmask(flash);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000366
367 olddst = dst;
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000368 for (i = 0; i < len; i++) {
Sean Nelsonc57a9202010-01-04 17:15:23 +0000369 if (write_byte_program_jedec_common(flash, src, dst, mask))
370 failed = 1;
371 dst++, src++;
372 }
373 if (failed)
Sean Nelsoned479d22010-03-24 23:14:32 +0000374 msg_cerr(" writing sector at 0x%lx failed!\n", olddst);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000375
376 return failed;
377}
378
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000379int write_page_write_jedec_common(struct flashctx *flash, uint8_t *src, unsigned int start, unsigned int page_size)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000380{
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000381 int i, tried = 0, failed;
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000382 uint8_t *s = src;
Urja Rannikko0c854c02009-06-25 13:57:31 +0000383 chipaddr bios = flash->virtual_memory;
384 chipaddr dst = bios + start;
385 chipaddr d = dst;
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000386 unsigned int mask;
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000387
388 mask = getaddrmask(flash);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000389
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000390retry:
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000391 /* Issue JEDEC Start Program command */
Sean Nelsonc57a9202010-01-04 17:15:23 +0000392 start_program_jedec_common(flash, mask);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000393
Ollie Lho98bea8a2004-12-07 03:15:51 +0000394 /* transfer data from source to destination */
Carl-Daniel Hailfinger8a8a2262009-11-14 03:48:33 +0000395 for (i = 0; i < page_size; i++) {
Ollie Lho98bea8a2004-12-07 03:15:51 +0000396 /* If the data is 0xFF, don't program it */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000397 if (*src != 0xFF)
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000398 chip_writeb(*src, dst);
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000399 dst++;
400 src++;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000401 }
402
Ollie Lho761bf1b2004-03-20 16:46:10 +0000403 toggle_ready_jedec(dst - 1);
Ollie Lho98bea8a2004-12-07 03:15:51 +0000404
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000405 dst = d;
406 src = s;
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000407 failed = verify_range(flash, src, start, page_size, NULL);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000408
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000409 if (failed && tried++ < MAX_REFLASH_TRIES) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000410 msg_cerr("retrying.\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +0000411 goto retry;
412 }
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000413 if (failed) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000414 msg_cerr(" page 0x%lx failed!\n",
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000415 (d - bios) / page_size);
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000416 }
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000417 return failed;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000418}
419
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000420/* chunksize is page_size */
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000421/*
422 * Write a part of the flash chip.
423 * FIXME: Use the chunk code from Michael Karcher instead.
424 * This function is a slightly modified copy of spi_write_chunked.
425 * Each page is written separately in chunks with a maximum size of chunksize.
426 */
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000427int write_jedec(struct flashctx *flash, uint8_t *buf, unsigned int start, int unsigned len)
Carl-Daniel Hailfinger4bf4e792010-01-09 03:15:50 +0000428{
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000429 unsigned int i, starthere, lenhere;
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000430 /* FIXME: page_size is the wrong variable. We need max_writechunk_size
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000431 * in struct flashctx to do this properly. All chips using
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000432 * write_jedec have page_size set to max_writechunk_size, so
433 * we're OK for now.
434 */
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000435 unsigned int page_size = flash->page_size;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000436
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000437 /* Warning: This loop has a very unusual condition and body.
438 * The loop needs to go through each page with at least one affected
439 * byte. The lowest page number is (start / page_size) since that
440 * division rounds down. The highest page number we want is the page
441 * where the last byte of the range lives. That last byte has the
442 * address (start + len - 1), thus the highest page number is
443 * (start + len - 1) / page_size. Since we want to include that last
444 * page as well, the loop condition uses <=.
445 */
446 for (i = start / page_size; i <= (start + len - 1) / page_size; i++) {
447 /* Byte position of the first byte in the range in this page. */
448 /* starthere is an offset to the base address of the chip. */
449 starthere = max(start, i * page_size);
450 /* Length of bytes in the range in this page. */
451 lenhere = min(start + len, (i + 1) * page_size) - starthere;
Sean Nelson35727f72010-01-28 23:55:12 +0000452
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000453 if (write_page_write_jedec_common(flash, buf + starthere - start, starthere, lenhere))
454 return 1;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000455 }
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000456
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000457 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000458}
Michael Karcher1c296ca2009-11-27 17:49:42 +0000459
Sean Nelsonc57a9202010-01-04 17:15:23 +0000460/* erase chip with block_erase() prototype */
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000461int erase_chip_block_jedec(struct flashctx *flash, unsigned int addr,
Sean Nelsonc57a9202010-01-04 17:15:23 +0000462 unsigned int blocksize)
463{
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000464 unsigned int mask;
Sean Nelson35727f72010-01-28 23:55:12 +0000465
466 mask = getaddrmask(flash);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000467 if ((addr != 0) || (blocksize != flash->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000468 msg_cerr("%s called with incorrect arguments\n",
Sean Nelsonc57a9202010-01-04 17:15:23 +0000469 __func__);
470 return -1;
471 }
Sean Nelson35727f72010-01-28 23:55:12 +0000472 return erase_chip_jedec_common(flash, mask);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000473}
474
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000475int probe_jedec(struct flashctx *flash)
Sean Nelsonc57a9202010-01-04 17:15:23 +0000476{
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000477 unsigned int mask;
Carl-Daniel Hailfinger4bf4e792010-01-09 03:15:50 +0000478
479 mask = getaddrmask(flash);
Sean Nelson35727f72010-01-28 23:55:12 +0000480 return probe_jedec_common(flash, mask);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000481}
482
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000483int erase_sector_jedec(struct flashctx *flash, unsigned int page, unsigned int size)
Sean Nelsonc57a9202010-01-04 17:15:23 +0000484{
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000485 unsigned int mask;
Sean Nelson35727f72010-01-28 23:55:12 +0000486
487 mask = getaddrmask(flash);
488 return erase_sector_jedec_common(flash, page, size, mask);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000489}
490
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000491int erase_block_jedec(struct flashctx *flash, unsigned int page, unsigned int size)
Sean Nelsonc57a9202010-01-04 17:15:23 +0000492{
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000493 unsigned int mask;
Sean Nelson35727f72010-01-28 23:55:12 +0000494
495 mask = getaddrmask(flash);
496 return erase_block_jedec_common(flash, page, size, mask);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000497}
498
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000499int erase_chip_jedec(struct flashctx *flash)
Sean Nelsonc57a9202010-01-04 17:15:23 +0000500{
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000501 unsigned int mask;
Sean Nelson35727f72010-01-28 23:55:12 +0000502
503 mask = getaddrmask(flash);
504 return erase_chip_jedec_common(flash, mask);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000505}