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Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00003 *
Uwe Hermannd22a1d42007-09-09 20:21:05 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2006 Giampiero Giancipoli <gianci@email.it>
6 * Copyright (C) 2006 coresystems GmbH <info@coresystems.de>
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Sean Nelsonc57a9202010-01-04 17:15:23 +00008 * Copyright (C) 2009 Sean Nelson <audiohacked@gmail.com>
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00009 *
Uwe Hermannd1107642007-08-29 17:52:32 +000010 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000014 *
Uwe Hermannd1107642007-08-29 17:52:32 +000015 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000019 *
Uwe Hermannd1107642007-08-29 17:52:32 +000020 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000023 */
24
25#include "flash.h"
Sean Nelson14ba6682010-02-26 05:48:29 +000026#include "chipdrivers.h"
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000027
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +000028#define MAX_REFLASH_TRIES 0x10
Sean Nelsonc57a9202010-01-04 17:15:23 +000029#define MASK_FULL 0xffff
30#define MASK_2AA 0x7ff
Sean Nelson35727f72010-01-28 23:55:12 +000031#define MASK_AAA 0xfff
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +000032
Carl-Daniel Hailfingera758f512008-05-14 12:03:06 +000033/* Check one byte for odd parity */
34uint8_t oddparity(uint8_t val)
35{
36 val = (val ^ (val >> 4)) & 0xf;
37 val = (val ^ (val >> 2)) & 0x3;
38 return (val ^ (val >> 1)) & 0x1;
39}
40
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +000041static void toggle_ready_jedec_common(chipaddr dst, int delay)
Uwe Hermann51582f22007-08-23 10:20:40 +000042{
43 unsigned int i = 0;
44 uint8_t tmp1, tmp2;
45
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000046 tmp1 = chip_readb(dst) & 0x40;
Uwe Hermann51582f22007-08-23 10:20:40 +000047
48 while (i++ < 0xFFFFFFF) {
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000049 if (delay)
50 programmer_delay(delay);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000051 tmp2 = chip_readb(dst) & 0x40;
Uwe Hermann51582f22007-08-23 10:20:40 +000052 if (tmp1 == tmp2) {
53 break;
54 }
55 tmp1 = tmp2;
56 }
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000057 if (i > 0x100000)
Sean Nelsoned479d22010-03-24 23:14:32 +000058 msg_cdbg("%s: excessive loops, i=0x%x\n", __func__, i);
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000059}
60
61void toggle_ready_jedec(chipaddr dst)
62{
63 toggle_ready_jedec_common(dst, 0);
64}
65
66/* Some chips require a minimum delay between toggle bit reads.
67 * The Winbond W39V040C wants 50 ms between reads on sector erase toggle,
68 * but experiments show that 2 ms are already enough. Pick a safety factor
69 * of 4 and use an 8 ms delay.
70 * Given that erase is slow on all chips, it is recommended to use
71 * toggle_ready_jedec_slow in erase functions.
72 */
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +000073static void toggle_ready_jedec_slow(chipaddr dst)
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000074{
75 toggle_ready_jedec_common(dst, 8 * 1000);
Uwe Hermann51582f22007-08-23 10:20:40 +000076}
77
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +000078void data_polling_jedec(chipaddr dst, uint8_t data)
Uwe Hermann51582f22007-08-23 10:20:40 +000079{
80 unsigned int i = 0;
81 uint8_t tmp;
82
83 data &= 0x80;
84
85 while (i++ < 0xFFFFFFF) {
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +000086 tmp = chip_readb(dst) & 0x80;
Uwe Hermann51582f22007-08-23 10:20:40 +000087 if (tmp == data) {
88 break;
89 }
90 }
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000091 if (i > 0x100000)
Sean Nelsoned479d22010-03-24 23:14:32 +000092 msg_cdbg("%s: excessive loops, i=0x%x\n", __func__, i);
Uwe Hermann51582f22007-08-23 10:20:40 +000093}
94
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +000095static int getaddrmask(struct flashchip *flash)
96{
97 switch (flash->feature_bits & FEATURE_ADDR_MASK) {
98 case FEATURE_ADDR_FULL:
99 return MASK_FULL;
100 break;
101 case FEATURE_ADDR_2AA:
102 return MASK_2AA;
103 break;
104 case FEATURE_ADDR_AAA:
105 return MASK_AAA;
106 break;
107 default:
108 msg_cerr("%s called with unknown mask\n", __func__);
109 return 0;
110 break;
111 }
112}
113
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000114static void start_program_jedec_common(struct flashchip *flash, unsigned int mask)
Uwe Hermann51582f22007-08-23 10:20:40 +0000115{
Sean Nelsonc57a9202010-01-04 17:15:23 +0000116 chipaddr bios = flash->virtual_memory;
117 chip_writeb(0xAA, bios + (0x5555 & mask));
118 chip_writeb(0x55, bios + (0x2AAA & mask));
119 chip_writeb(0xA0, bios + (0x5555 & mask));
Uwe Hermann51582f22007-08-23 10:20:40 +0000120}
121
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000122static int probe_jedec_common(struct flashchip *flash, unsigned int mask)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000123{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000124 chipaddr bios = flash->virtual_memory;
Ollie Lho184a4042005-11-26 21:55:36 +0000125 uint8_t id1, id2;
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000126 uint32_t largeid1, largeid2;
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +0000127 uint32_t flashcontent1, flashcontent2;
Maciej Pijankac6e11112009-06-03 14:46:22 +0000128 int probe_timing_enter, probe_timing_exit;
129
130 if (flash->probe_timing > 0)
131 probe_timing_enter = probe_timing_exit = flash->probe_timing;
132 else if (flash->probe_timing == TIMING_ZERO) { /* No delay. */
133 probe_timing_enter = probe_timing_exit = 0;
134 } else if (flash->probe_timing == TIMING_FIXME) { /* == _IGNORED */
Sean Nelsoned479d22010-03-24 23:14:32 +0000135 msg_cdbg("Chip lacks correct probe timing information, "
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000136 "using default 10mS/40uS. ");
Maciej Pijankac6e11112009-06-03 14:46:22 +0000137 probe_timing_enter = 10000;
138 probe_timing_exit = 40;
139 } else {
Sean Nelsoned479d22010-03-24 23:14:32 +0000140 msg_cerr("Chip has negative value in probe_timing, failing "
Maciej Pijankac6e11112009-06-03 14:46:22 +0000141 "without chip access\n");
142 return 0;
143 }
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000144
Ollie Lho761bf1b2004-03-20 16:46:10 +0000145 /* Issue JEDEC Product ID Entry command */
Sean Nelsonc57a9202010-01-04 17:15:23 +0000146 chip_writeb(0xAA, bios + (0x5555 & mask));
Sean Nelsonc12fc712009-12-17 04:22:40 +0000147 if (probe_timing_enter)
148 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000149 chip_writeb(0x55, bios + (0x2AAA & mask));
Sean Nelsonc12fc712009-12-17 04:22:40 +0000150 if (probe_timing_enter)
151 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000152 chip_writeb(0x90, bios + (0x5555 & mask));
Sean Nelsonc12fc712009-12-17 04:22:40 +0000153 if (probe_timing_enter)
154 programmer_delay(probe_timing_enter);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000155
Ollie Lho761bf1b2004-03-20 16:46:10 +0000156 /* Read product ID */
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000157 id1 = chip_readb(bios);
158 id2 = chip_readb(bios + 0x01);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000159 largeid1 = id1;
160 largeid2 = id2;
161
162 /* Check if it is a continuation ID, this should be a while loop. */
163 if (id1 == 0x7F) {
164 largeid1 <<= 8;
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000165 id1 = chip_readb(bios + 0x100);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000166 largeid1 |= id1;
167 }
168 if (id2 == 0x7F) {
169 largeid2 <<= 8;
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000170 id2 = chip_readb(bios + 0x101);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000171 largeid2 |= id2;
172 }
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000173
Ollie Lho761bf1b2004-03-20 16:46:10 +0000174 /* Issue JEDEC Product ID Exit command */
Sean Nelson35727f72010-01-28 23:55:12 +0000175 if ((flash->feature_bits & FEATURE_SHORT_RESET) == FEATURE_LONG_RESET)
Sean Nelsonc57a9202010-01-04 17:15:23 +0000176 {
177 chip_writeb(0xAA, bios + (0x5555 & mask));
178 if (probe_timing_exit)
179 programmer_delay(10);
180 chip_writeb(0x55, bios + (0x2AAA & mask));
181 if (probe_timing_exit)
182 programmer_delay(10);
183 }
184 chip_writeb(0xF0, bios + (0x5555 & mask));
Sean Nelsonc12fc712009-12-17 04:22:40 +0000185 if (probe_timing_exit)
186 programmer_delay(probe_timing_exit);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000187
Sean Nelsoned479d22010-03-24 23:14:32 +0000188 msg_cdbg("%s: id1 0x%02x, id2 0x%02x", __func__, largeid1, largeid2);
Carl-Daniel Hailfingera758f512008-05-14 12:03:06 +0000189 if (!oddparity(id1))
Sean Nelsoned479d22010-03-24 23:14:32 +0000190 msg_cdbg(", id1 parity violation");
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +0000191
192 /* Read the product ID location again. We should now see normal flash contents. */
193 flashcontent1 = chip_readb(bios);
194 flashcontent2 = chip_readb(bios + 0x01);
195
196 /* Check if it is a continuation ID, this should be a while loop. */
197 if (flashcontent1 == 0x7F) {
198 flashcontent1 <<= 8;
199 flashcontent1 |= chip_readb(bios + 0x100);
200 }
201 if (flashcontent2 == 0x7F) {
202 flashcontent2 <<= 8;
203 flashcontent2 |= chip_readb(bios + 0x101);
204 }
205
206 if (largeid1 == flashcontent1)
Sean Nelsoned479d22010-03-24 23:14:32 +0000207 msg_cdbg(", id1 is normal flash content");
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +0000208 if (largeid2 == flashcontent2)
Sean Nelsoned479d22010-03-24 23:14:32 +0000209 msg_cdbg(", id2 is normal flash content");
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +0000210
Sean Nelsoned479d22010-03-24 23:14:32 +0000211 msg_cdbg("\n");
Carl-Daniel Hailfingere9404662010-01-09 02:24:17 +0000212 if (largeid1 != flash->manufacture_id || largeid2 != flash->model_id)
213 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000214
Sean Nelsonc57a9202010-01-04 17:15:23 +0000215 if (flash->feature_bits & FEATURE_REGISTERMAP)
216 map_flash_registers(flash);
217
Carl-Daniel Hailfingere9404662010-01-09 02:24:17 +0000218 return 1;
Ollie Lho73eca802004-03-19 22:10:07 +0000219}
220
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000221static int erase_sector_jedec_common(struct flashchip *flash, unsigned int page,
Sean Nelsonc57a9202010-01-04 17:15:23 +0000222 unsigned int pagesize, unsigned int mask)
Ollie Lho73eca802004-03-19 22:10:07 +0000223{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000224 chipaddr bios = flash->virtual_memory;
225
Ollie Lho761bf1b2004-03-20 16:46:10 +0000226 /* Issue the Sector Erase command */
Sean Nelsonc57a9202010-01-04 17:15:23 +0000227 chip_writeb(0xAA, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000228 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000229 chip_writeb(0x55, bios + (0x2AAA & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000230 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000231 chip_writeb(0x80, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000232 programmer_delay(10);
Ollie Lhoefa28582004-12-08 20:10:01 +0000233
Sean Nelsonc57a9202010-01-04 17:15:23 +0000234 chip_writeb(0xAA, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000235 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000236 chip_writeb(0x55, bios + (0x2AAA & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000237 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000238 chip_writeb(0x30, bios + page);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000239 programmer_delay(10);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000240
Ollie Lho73eca802004-03-19 22:10:07 +0000241 /* wait for Toggle bit ready */
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +0000242 toggle_ready_jedec_slow(bios);
Ollie Lho73eca802004-03-19 22:10:07 +0000243
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000244 if (check_erased_range(flash, page, pagesize)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000245 msg_cerr("ERASE FAILED!\n");
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000246 return -1;
247 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000248 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000249}
Ollie Lho98bea8a2004-12-07 03:15:51 +0000250
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000251static int erase_block_jedec_common(struct flashchip *flash, unsigned int block,
Sean Nelsonc57a9202010-01-04 17:15:23 +0000252 unsigned int blocksize, unsigned int mask)
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000253{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000254 chipaddr bios = flash->virtual_memory;
255
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000256 /* Issue the Sector Erase command */
Sean Nelsonc57a9202010-01-04 17:15:23 +0000257 chip_writeb(0xAA, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000258 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000259 chip_writeb(0x55, bios + (0x2AAA & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000260 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000261 chip_writeb(0x80, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000262 programmer_delay(10);
Ollie Lhoefa28582004-12-08 20:10:01 +0000263
Sean Nelsonc57a9202010-01-04 17:15:23 +0000264 chip_writeb(0xAA, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000265 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000266 chip_writeb(0x55, bios + (0x2AAA & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000267 programmer_delay(10);
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000268 chip_writeb(0x50, bios + block);
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000269 programmer_delay(10);
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000270
271 /* wait for Toggle bit ready */
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +0000272 toggle_ready_jedec_slow(bios);
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000273
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000274 if (check_erased_range(flash, block, blocksize)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000275 msg_cerr("ERASE FAILED!\n");
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000276 return -1;
277 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000278 return 0;
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000279}
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000280
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000281static int erase_chip_jedec_common(struct flashchip *flash, unsigned int mask)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000282{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000283 int total_size = flash->total_size * 1024;
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000284 chipaddr bios = flash->virtual_memory;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000285
Ollie Lho761bf1b2004-03-20 16:46:10 +0000286 /* Issue the JEDEC Chip Erase command */
Sean Nelsonc57a9202010-01-04 17:15:23 +0000287 chip_writeb(0xAA, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000288 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000289 chip_writeb(0x55, bios + (0x2AAA & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000290 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000291 chip_writeb(0x80, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000292 programmer_delay(10);
Ollie Lhoefa28582004-12-08 20:10:01 +0000293
Sean Nelsonc57a9202010-01-04 17:15:23 +0000294 chip_writeb(0xAA, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000295 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000296 chip_writeb(0x55, bios + (0x2AAA & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000297 programmer_delay(10);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000298 chip_writeb(0x10, bios + (0x5555 & mask));
Carl-Daniel Hailfingerca8bfc62009-06-05 17:48:08 +0000299 programmer_delay(10);
Ollie Lho73eca802004-03-19 22:10:07 +0000300
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +0000301 toggle_ready_jedec_slow(bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000302
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000303 if (check_erased_range(flash, 0, total_size)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000304 msg_cerr("ERASE FAILED!\n");
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000305 return -1;
306 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000307 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000308}
309
Carl-Daniel Hailfingerad3cc552010-07-03 11:02:10 +0000310static int write_byte_program_jedec_common(struct flashchip *flash, uint8_t *src,
Sean Nelsonc57a9202010-01-04 17:15:23 +0000311 chipaddr dst, unsigned int mask)
312{
313 int tried = 0, failed = 0;
314 chipaddr bios = flash->virtual_memory;
315
316 /* If the data is 0xFF, don't program it and don't complain. */
317 if (*src == 0xFF) {
318 return 0;
319 }
320
321retry:
322 /* Issue JEDEC Byte Program command */
323 start_program_jedec_common(flash, mask);
324
325 /* transfer data from source to destination */
326 chip_writeb(*src, dst);
327 toggle_ready_jedec(bios);
328
329 if (chip_readb(dst) != *src && tried++ < MAX_REFLASH_TRIES) {
330 goto retry;
331 }
332
333 if (tried >= MAX_REFLASH_TRIES)
334 failed = 1;
335
336 return failed;
337}
338
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000339/* chunksize is 1 */
340int write_jedec_1(struct flashchip *flash, uint8_t *src, int start, int len)
Sean Nelsonc57a9202010-01-04 17:15:23 +0000341{
342 int i, failed = 0;
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000343 chipaddr dst = flash->virtual_memory + start;
Sean Nelsonc57a9202010-01-04 17:15:23 +0000344 chipaddr olddst;
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000345 int mask;
346
347 mask = getaddrmask(flash);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000348
349 olddst = dst;
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000350 for (i = 0; i < len; i++) {
Sean Nelsonc57a9202010-01-04 17:15:23 +0000351 if (write_byte_program_jedec_common(flash, src, dst, mask))
352 failed = 1;
353 dst++, src++;
354 }
355 if (failed)
Sean Nelsoned479d22010-03-24 23:14:32 +0000356 msg_cerr(" writing sector at 0x%lx failed!\n", olddst);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000357
358 return failed;
359}
360
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000361int write_page_write_jedec_common(struct flashchip *flash, uint8_t *src, int start, int page_size)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000362{
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000363 int i, tried = 0, failed;
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000364 uint8_t *s = src;
Urja Rannikko0c854c02009-06-25 13:57:31 +0000365 chipaddr bios = flash->virtual_memory;
366 chipaddr dst = bios + start;
367 chipaddr d = dst;
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000368 int mask;
369
370 mask = getaddrmask(flash);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000371
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000372retry:
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000373 /* Issue JEDEC Start Program command */
Sean Nelsonc57a9202010-01-04 17:15:23 +0000374 start_program_jedec_common(flash, mask);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000375
Ollie Lho98bea8a2004-12-07 03:15:51 +0000376 /* transfer data from source to destination */
Carl-Daniel Hailfinger8a8a2262009-11-14 03:48:33 +0000377 for (i = 0; i < page_size; i++) {
Ollie Lho98bea8a2004-12-07 03:15:51 +0000378 /* If the data is 0xFF, don't program it */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000379 if (*src != 0xFF)
Carl-Daniel Hailfinger0472f3d2009-03-06 22:26:00 +0000380 chip_writeb(*src, dst);
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000381 dst++;
382 src++;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000383 }
384
Ollie Lho761bf1b2004-03-20 16:46:10 +0000385 toggle_ready_jedec(dst - 1);
Ollie Lho98bea8a2004-12-07 03:15:51 +0000386
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000387 dst = d;
388 src = s;
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000389 failed = verify_range(flash, src, start, page_size, NULL);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000390
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000391 if (failed && tried++ < MAX_REFLASH_TRIES) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000392 msg_cerr("retrying.\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +0000393 goto retry;
394 }
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000395 if (failed) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000396 msg_cerr(" page 0x%lx failed!\n",
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000397 (d - bios) / page_size);
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000398 }
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000399 return failed;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000400}
401
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000402/* chunksize is page_size */
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000403/*
404 * Write a part of the flash chip.
405 * FIXME: Use the chunk code from Michael Karcher instead.
406 * This function is a slightly modified copy of spi_write_chunked.
407 * Each page is written separately in chunks with a maximum size of chunksize.
408 */
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000409int write_jedec(struct flashchip *flash, uint8_t *buf, int start, int len)
Carl-Daniel Hailfinger4bf4e792010-01-09 03:15:50 +0000410{
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000411 int i, starthere, lenhere;
412 /* FIXME: page_size is the wrong variable. We need max_writechunk_size
413 * in struct flashchip to do this properly. All chips using
414 * write_jedec have page_size set to max_writechunk_size, so
415 * we're OK for now.
416 */
Ollie Lho070647d2004-03-22 22:19:17 +0000417 int page_size = flash->page_size;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000418
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000419 /* Warning: This loop has a very unusual condition and body.
420 * The loop needs to go through each page with at least one affected
421 * byte. The lowest page number is (start / page_size) since that
422 * division rounds down. The highest page number we want is the page
423 * where the last byte of the range lives. That last byte has the
424 * address (start + len - 1), thus the highest page number is
425 * (start + len - 1) / page_size. Since we want to include that last
426 * page as well, the loop condition uses <=.
427 */
428 for (i = start / page_size; i <= (start + len - 1) / page_size; i++) {
429 /* Byte position of the first byte in the range in this page. */
430 /* starthere is an offset to the base address of the chip. */
431 starthere = max(start, i * page_size);
432 /* Length of bytes in the range in this page. */
433 lenhere = min(start + len, (i + 1) * page_size) - starthere;
Sean Nelson35727f72010-01-28 23:55:12 +0000434
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000435 if (write_page_write_jedec_common(flash, buf + starthere - start, starthere, lenhere))
436 return 1;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000437 }
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000438
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000439 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000440}
Michael Karcher1c296ca2009-11-27 17:49:42 +0000441
Sean Nelsonc57a9202010-01-04 17:15:23 +0000442/* erase chip with block_erase() prototype */
443int erase_chip_block_jedec(struct flashchip *flash, unsigned int addr,
444 unsigned int blocksize)
445{
Sean Nelson35727f72010-01-28 23:55:12 +0000446 int mask;
447
448 mask = getaddrmask(flash);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000449 if ((addr != 0) || (blocksize != flash->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000450 msg_cerr("%s called with incorrect arguments\n",
Sean Nelsonc57a9202010-01-04 17:15:23 +0000451 __func__);
452 return -1;
453 }
Sean Nelson35727f72010-01-28 23:55:12 +0000454 return erase_chip_jedec_common(flash, mask);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000455}
456
457int probe_jedec(struct flashchip *flash)
458{
Carl-Daniel Hailfinger4bf4e792010-01-09 03:15:50 +0000459 int mask;
460
461 mask = getaddrmask(flash);
Sean Nelson35727f72010-01-28 23:55:12 +0000462 return probe_jedec_common(flash, mask);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000463}
464
465int erase_sector_jedec(struct flashchip *flash, unsigned int page, unsigned int size)
466{
Sean Nelson35727f72010-01-28 23:55:12 +0000467 int mask;
468
469 mask = getaddrmask(flash);
470 return erase_sector_jedec_common(flash, page, size, mask);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000471}
472
473int erase_block_jedec(struct flashchip *flash, unsigned int page, unsigned int size)
474{
Sean Nelson35727f72010-01-28 23:55:12 +0000475 int mask;
476
477 mask = getaddrmask(flash);
478 return erase_block_jedec_common(flash, page, size, mask);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000479}
480
481int erase_chip_jedec(struct flashchip *flash)
482{
Sean Nelson35727f72010-01-28 23:55:12 +0000483 int mask;
484
485 mask = getaddrmask(flash);
486 return erase_chip_jedec_common(flash, mask);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000487}