blob: 21864af4301431b775319fb08d50e39feb973027 [file] [log] [blame]
Ollie Lho184a4042005-11-26 21:55:36 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ollie Lho184a4042005-11-26 21:55:36 +00003 *
Uwe Hermannd1107642007-08-29 17:52:32 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2005-2007 coresystems GmbH <stepan@coresystems.de>
6 * Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
Ollie Lho184a4042005-11-26 21:55:36 +00007 *
Uwe Hermannd1107642007-08-29 17:52:32 +00008 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
Ollie Lho184a4042005-11-26 21:55:36 +000011 *
Uwe Hermannd1107642007-08-29 17:52:32 +000012 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22/*
23 * Contains the chipset specific flash enables.
Ollie Lho184a4042005-11-26 21:55:36 +000024 */
25
Lane Brooksd54958a2007-11-13 16:45:22 +000026#define _LARGEFILE64_SOURCE
27
Ollie Lhocbbf1252004-03-17 22:22:08 +000028#include <stdio.h>
29#include <pci/pci.h>
30#include <stdlib.h>
Lane Brooksd54958a2007-11-13 16:45:22 +000031#include <sys/types.h>
32#include <sys/stat.h>
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +000033#include <sys/mman.h>
Lane Brooksd54958a2007-11-13 16:45:22 +000034#include <fcntl.h>
35#include <unistd.h>
Luc Verhaegen8e3a6002007-04-04 22:45:58 +000036#include "flash.h"
Stefan Reinauer86de2832006-03-31 11:26:55 +000037
Stefan Reinauer9a6d1762008-12-03 21:24:40 +000038unsigned long flashbase = 0;
39
Stefan Reinauer2cb94e12008-06-30 23:45:22 +000040/**
41 * flashrom defaults to LPC flash devices. If a known SPI controller is found
42 * and the SPI strappings are set, this will be overwritten by the probing code.
43 *
44 * Eventually, this will become an array when multiple flash support works.
45 */
46
47flashbus_t flashbus = BUS_TYPE_LPC;
48void *spibar = NULL;
49
FENG yu ningc05a2952008-12-08 18:16:58 +000050extern int ichspi_lock;
51
Uwe Hermann372eeb52007-12-04 21:49:06 +000052static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
Luc Verhaegen6b141752007-05-20 16:16:13 +000053{
54 uint8_t tmp;
55
Uwe Hermann372eeb52007-12-04 21:49:06 +000056 /*
57 * ROM Write enable, 0xFFFC0000-0xFFFDFFFF and
58 * 0xFFFE0000-0xFFFFFFFF ROM select enable.
59 */
Luc Verhaegen6b141752007-05-20 16:16:13 +000060 tmp = pci_read_byte(dev, 0x47);
61 tmp |= 0x46;
62 pci_write_byte(dev, 0x47, tmp);
63
64 return 0;
65}
66
Uwe Hermann372eeb52007-12-04 21:49:06 +000067static int enable_flash_sis630(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +000068{
Uwe Hermann372eeb52007-12-04 21:49:06 +000069 uint8_t b;
Ollie Lhocbbf1252004-03-17 22:22:08 +000070
Uwe Hermann372eeb52007-12-04 21:49:06 +000071 /* Enable 0xFFF8000~0xFFFF0000 decoding on SiS 540/630. */
Alex Beregszaszic9fb5d92007-09-11 15:58:18 +000072 b = pci_read_byte(dev, 0x40);
73 pci_write_byte(dev, 0x40, b | 0xb);
Uwe Hermann372eeb52007-12-04 21:49:06 +000074
75 /* Flash write enable on SiS 540/630. */
Alex Beregszaszic9fb5d92007-09-11 15:58:18 +000076 b = pci_read_byte(dev, 0x45);
77 pci_write_byte(dev, 0x45, b | 0x40);
Ollie Lhocbbf1252004-03-17 22:22:08 +000078
Uwe Hermann372eeb52007-12-04 21:49:06 +000079 /* The same thing on SiS 950 Super I/O side... */
80
81 /* First probe for Super I/O on config port 0x2e. */
Andriy Gapon65c1b862008-05-22 13:22:45 +000082 OUTB(0x87, 0x2e);
83 OUTB(0x01, 0x2e);
84 OUTB(0x55, 0x2e);
85 OUTB(0x55, 0x2e);
Ollie Lhocbbf1252004-03-17 22:22:08 +000086
Andriy Gapon65c1b862008-05-22 13:22:45 +000087 if (INB(0x2f) != 0x87) {
Uwe Hermann372eeb52007-12-04 21:49:06 +000088 /* If that failed, try config port 0x4e. */
Andriy Gapon65c1b862008-05-22 13:22:45 +000089 OUTB(0x87, 0x4e);
90 OUTB(0x01, 0x4e);
91 OUTB(0x55, 0x4e);
92 OUTB(0xaa, 0x4e);
93 if (INB(0x4f) != 0x87) {
Ollie Lhocbbf1252004-03-17 22:22:08 +000094 printf("Can not access SiS 950\n");
95 return -1;
96 }
Andriy Gapon65c1b862008-05-22 13:22:45 +000097 OUTB(0x24, 0x4e);
98 b = INB(0x4f) | 0xfc;
99 OUTB(0x24, 0x4e);
100 OUTB(b, 0x4f);
101 OUTB(0x02, 0x4e);
102 OUTB(0x02, 0x4f);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000103 }
104
Andriy Gapon65c1b862008-05-22 13:22:45 +0000105 OUTB(0x24, 0x2e);
106 printf("2f is %#x\n", INB(0x2f));
107 b = INB(0x2f) | 0xfc;
108 OUTB(0x24, 0x2e);
109 OUTB(b, 0x2f);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000110
Andriy Gapon65c1b862008-05-22 13:22:45 +0000111 OUTB(0x02, 0x2e);
112 OUTB(0x02, 0x2f);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000113
114 return 0;
115}
116
Uwe Hermann987942d2006-11-07 11:16:21 +0000117/* Datasheet:
118 * - Name: 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4)
119 * - URL: http://www.intel.com/design/intarch/datashts/290562.htm
120 * - PDF: http://www.intel.com/design/intarch/datashts/29056201.pdf
121 * - Order Number: 290562-001
122 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000123static int enable_flash_piix4(struct pci_dev *dev, const char *name)
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000124{
125 uint16_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000126 uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000127
128 old = pci_read_word(dev, xbcs);
129
130 /* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
Uwe Hermanna7e05482007-05-09 10:17:44 +0000131 * FFF00000-FFF7FFFF are forwarded to ISA).
Uwe Hermannc556d322008-10-28 11:50:05 +0000132 * Note: This bit is reserved on PIIX/PIIX3/MPIIX.
Uwe Hermanna7e05482007-05-09 10:17:44 +0000133 * Set bit 7: Extended BIOS Enable (PCI master accesses to
134 * FFF80000-FFFDFFFF are forwarded to ISA).
135 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
136 * the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
137 * of 1 Mbyte, or the aliases at the top of 4 Gbyte
138 * (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
139 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
140 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
141 */
Uwe Hermannc556d322008-10-28 11:50:05 +0000142 if (dev->device_id == 0x122e || dev->device_id == 0x7000
143 || dev->device_id == 0x1234)
144 new = old | 0x00c4; /* PIIX/PIIX3/MPIIX: Bit 9 is reserved. */
Uwe Hermann87203452008-10-26 18:40:42 +0000145 else
146 new = old | 0x02c4;
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000147
148 if (new == old)
149 return 0;
150
151 pci_write_word(dev, xbcs, new);
152
153 if (pci_read_word(dev, xbcs) != new) {
154 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name);
155 return -1;
156 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000157
Uwe Hermannea2c66d2006-11-05 18:26:08 +0000158 return 0;
159}
160
Uwe Hermann372eeb52007-12-04 21:49:06 +0000161/*
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000162 * See ie. page 375 of "Intel I/O Controller Hub 7 (ICH7) Family Datasheet"
163 * http://download.intel.com/design/chipsets/datashts/30701303.pdf
Uwe Hermann372eeb52007-12-04 21:49:06 +0000164 */
165static int enable_flash_ich(struct pci_dev *dev, const char *name,
166 int bios_cntl)
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000167{
Ollie Lho184a4042005-11-26 21:55:36 +0000168 uint8_t old, new;
Stefan Reinauereb366472006-09-06 15:48:48 +0000169
Uwe Hermann372eeb52007-12-04 21:49:06 +0000170 /*
171 * Note: the ICH0-ICH5 BIOS_CNTL register is actually 16 bit wide, but
Uwe Hermanna7e05482007-05-09 10:17:44 +0000172 * just treating it as 8 bit wide seems to work fine in practice.
Stefan Reinauereb366472006-09-06 15:48:48 +0000173 */
Stefan Reinauer86de2832006-03-31 11:26:55 +0000174 old = pci_read_byte(dev, bios_cntl);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000175
Uwe Hermann793bdcd2008-05-22 22:47:04 +0000176 printf_debug("\nBIOS Lock Enable: %sabled, ",
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000177 (old & (1 << 1)) ? "en" : "dis");
178 printf_debug("BIOS Write Enable: %sabled, ",
179 (old & (1 << 0)) ? "en" : "dis");
180 printf_debug("BIOS_CNTL is 0x%x\n", old);
181
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000182 new = old | 1;
183
184 if (new == old)
185 return 0;
186
Stefan Reinauer86de2832006-03-31 11:26:55 +0000187 pci_write_byte(dev, bios_cntl, new);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000188
Stefan Reinauer86de2832006-03-31 11:26:55 +0000189 if (pci_read_byte(dev, bios_cntl) != new) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000190 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name);
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000191 return -1;
192 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000193
Ronald G. Minnich6a967412004-09-28 20:09:06 +0000194 return 0;
195}
196
Uwe Hermann372eeb52007-12-04 21:49:06 +0000197static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000198{
Stefan Reinauereb366472006-09-06 15:48:48 +0000199 return enable_flash_ich(dev, name, 0x4e);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000200}
201
Uwe Hermann372eeb52007-12-04 21:49:06 +0000202static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000203{
Stefan Reinauereb366472006-09-06 15:48:48 +0000204 return enable_flash_ich(dev, name, 0xdc);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000205}
206
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000207#define ICH_STRAP_RSVD 0x00
208#define ICH_STRAP_SPI 0x01
209#define ICH_STRAP_PCI 0x02
210#define ICH_STRAP_LPC 0x03
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000211
Uwe Hermann394131e2008-10-18 21:14:13 +0000212static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
213{
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000214 uint32_t mmio_base;
215
216 mmio_base = (pci_read_long(dev, 0xbc)) << 8;
217 printf_debug("MMIO base at = 0x%x\n", mmio_base);
Stefan Reinauer0593f212009-01-26 01:10:48 +0000218 spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70);
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000219
Uwe Hermann394131e2008-10-18 21:14:13 +0000220 printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n",
221 *(uint16_t *) (spibar + 0x6c));
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000222
223 flashbus = BUS_TYPE_VIA_SPI;
Rudolf Marek0c2029f2009-02-01 18:40:50 +0000224 ich_init_opcodes();
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000225
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000226 return 0;
227}
228
Uwe Hermann394131e2008-10-18 21:14:13 +0000229static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
230 int ich_generation)
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000231{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000232 int ret, i;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000233 uint8_t old, new, bbs, buc;
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000234 uint16_t spibar_offset, tmp2;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000235 uint32_t tmp, gcs;
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000236 void *rcrb;
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000237 //TODO: These names are incorrect for EP80579. For that, the solution would look like the commented line
238 //static const char *straps_names[] = {"SPI", "reserved", "reserved", "LPC" };
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000239 static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" };
Uwe Hermann394131e2008-10-18 21:14:13 +0000240
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000241 /* Enable Flash Writes */
242 ret = enable_flash_ich_dc(dev, name);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000243
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000244 /* Get physical address of Root Complex Register Block */
245 tmp = pci_read_long(dev, 0xf0) & 0xffffc000;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000246 printf_debug("\nRoot Complex Register Block address = 0x%x\n", tmp);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000247
248 /* Map RCBA to virtual memory */
Stefan Reinauer0593f212009-01-26 01:10:48 +0000249 rcrb = physmap("ICH RCRB", tmp, 0x4000);
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000250
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000251 gcs = *(volatile uint32_t *)(rcrb + 0x3410);
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000252 printf_debug("GCS = 0x%x: ", gcs);
253 printf_debug("BIOS Interface Lock-Down: %sabled, ",
254 (gcs & 0x1) ? "en" : "dis");
255 bbs = (gcs >> 10) & 0x3;
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000256 printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000257
Stefan Reinauera9424d52008-06-27 16:28:34 +0000258 buc = *(volatile uint8_t *)(rcrb + 0x3414);
Uwe Hermann394131e2008-10-18 21:14:13 +0000259 printf_debug("Top Swap : %s\n",
260 (buc & 1) ? "enabled (A16 inverted)" : "not enabled");
Stefan Reinauera9424d52008-06-27 16:28:34 +0000261
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000262 /* It seems the ICH7 does not support SPI and LPC chips at the same
263 * time. At least not with our current code. So we prevent searching
264 * on ICH7 when the southbridge is strapped to LPC
265 */
266
267 if (ich_generation == 7 && bbs == ICH_STRAP_LPC) {
268 /* No further SPI initialization required */
269 return ret;
270 }
271
272 switch (ich_generation) {
273 case 7:
274 flashbus = BUS_TYPE_ICH7_SPI;
275 spibar_offset = 0x3020;
276 break;
277 case 8:
278 flashbus = BUS_TYPE_ICH9_SPI;
279 spibar_offset = 0x3020;
280 break;
281 case 9:
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000282 case 10:
Uwe Hermann394131e2008-10-18 21:14:13 +0000283 default: /* Future version might behave the same */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000284 flashbus = BUS_TYPE_ICH9_SPI;
285 spibar_offset = 0x3800;
286 break;
287 }
288
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000289 /* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000290 printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000291
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000292 /* Assign Virtual Address */
Uwe Hermann394131e2008-10-18 21:14:13 +0000293 spibar = rcrb + spibar_offset;
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000294
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000295 switch (flashbus) {
296 case BUS_TYPE_ICH7_SPI:
Uwe Hermann394131e2008-10-18 21:14:13 +0000297 printf_debug("0x00: 0x%04x (SPIS)\n",
298 *(uint16_t *) (spibar + 0));
299 printf_debug("0x02: 0x%04x (SPIC)\n",
300 *(uint16_t *) (spibar + 2));
301 printf_debug("0x04: 0x%08x (SPIA)\n",
302 *(uint32_t *) (spibar + 4));
303 for (i = 0; i < 8; i++) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000304 int offs;
305 offs = 8 + (i * 8);
Uwe Hermann394131e2008-10-18 21:14:13 +0000306 printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs,
307 *(uint32_t *) (spibar + offs), i);
308 printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
309 *(uint32_t *) (spibar + offs + 4), i);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000310 }
Uwe Hermann394131e2008-10-18 21:14:13 +0000311 printf_debug("0x50: 0x%08x (BBAR)\n",
312 *(uint32_t *) (spibar + 0x50));
313 printf_debug("0x54: 0x%04x (PREOP)\n",
314 *(uint16_t *) (spibar + 0x54));
315 printf_debug("0x56: 0x%04x (OPTYPE)\n",
316 *(uint16_t *) (spibar + 0x56));
317 printf_debug("0x58: 0x%08x (OPMENU)\n",
318 *(uint32_t *) (spibar + 0x58));
319 printf_debug("0x5c: 0x%08x (OPMENU+4)\n",
320 *(uint32_t *) (spibar + 0x5c));
321 for (i = 0; i < 4; i++) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000322 int offs;
323 offs = 0x60 + (i * 4);
Uwe Hermann394131e2008-10-18 21:14:13 +0000324 printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs,
325 *(uint32_t *) (spibar + offs), i);
Stefan Reinauera9424d52008-06-27 16:28:34 +0000326 }
327 printf_debug("\n");
Uwe Hermann394131e2008-10-18 21:14:13 +0000328 if ((*(uint16_t *) spibar) & (1 << 15)) {
Stefan Reinauera9424d52008-06-27 16:28:34 +0000329 printf("WARNING: SPI Configuration Lockdown activated.\n");
FENG yu ningc05a2952008-12-08 18:16:58 +0000330 ichspi_lock = 1;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000331 }
FENG yu ningf041e9b2008-12-15 02:32:11 +0000332 ich_init_opcodes();
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000333 break;
334 case BUS_TYPE_ICH9_SPI:
FENG yu ning37179b82009-01-18 06:39:32 +0000335 tmp2 = *(uint16_t *) (spibar + 4);
336 printf_debug("0x04: 0x%04x (HSFS)\n", tmp2);
337 printf_debug("FLOCKDN %i, ", (tmp2 >> 15 & 1));
338 printf_debug("FDV %i, ", (tmp2 >> 14) & 1);
339 printf_debug("FDOPSS %i, ", (tmp2 >> 13) & 1);
340 printf_debug("SCIP %i, ", (tmp2 >> 5) & 1);
341 printf_debug("BERASE %i, ", (tmp2 >> 3) & 3);
342 printf_debug("AEL %i, ", (tmp2 >> 2) & 1);
343 printf_debug("FCERR %i, ", (tmp2 >> 1) & 1);
344 printf_debug("FDONE %i\n", (tmp2 >> 0) & 1);
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000345
346 tmp = *(uint32_t *) (spibar + 0x50);
347 printf_debug("0x50: 0x%08x (FRAP)\n", tmp);
348 printf_debug("BMWAG %i, ", (tmp >> 24) & 0xff);
349 printf_debug("BMRAG %i, ", (tmp >> 16) & 0xff);
350 printf_debug("BRWA %i, ", (tmp >> 8) & 0xff);
351 printf_debug("BRRA %i\n", (tmp >> 0) & 0xff);
352
353 printf_debug("0x54: 0x%08x (FREG0)\n",
354 *(uint32_t *) (spibar + 0x54));
355 printf_debug("0x58: 0x%08x (FREG1)\n",
356 *(uint32_t *) (spibar + 0x58));
357 printf_debug("0x5C: 0x%08x (FREG2)\n",
358 *(uint32_t *) (spibar + 0x5C));
359 printf_debug("0x60: 0x%08x (FREG3)\n",
360 *(uint32_t *) (spibar + 0x60));
361 printf_debug("0x64: 0x%08x (FREG4)\n",
362 *(uint32_t *) (spibar + 0x64));
363 printf_debug("0x74: 0x%08x (PR0)\n",
364 *(uint32_t *) (spibar + 0x74));
365 printf_debug("0x78: 0x%08x (PR1)\n",
366 *(uint32_t *) (spibar + 0x78));
367 printf_debug("0x7C: 0x%08x (PR2)\n",
368 *(uint32_t *) (spibar + 0x7C));
369 printf_debug("0x80: 0x%08x (PR3)\n",
370 *(uint32_t *) (spibar + 0x80));
371 printf_debug("0x84: 0x%08x (PR4)\n",
372 *(uint32_t *) (spibar + 0x84));
FENG yu ning37179b82009-01-18 06:39:32 +0000373 printf_debug("0x90: 0x%08x (SSFS, SSFC)\n",
374 *(uint32_t *) (spibar + 0x90));
375 printf_debug("0x94: 0x%04x (PREOP)\n",
376 *(uint16_t *) (spibar + 0x94));
377 printf_debug("0x96: 0x%04x (OPTYPE)\n",
378 *(uint16_t *) (spibar + 0x96));
379 printf_debug("0x98: 0x%08x (OPMENU)\n",
380 *(uint32_t *) (spibar + 0x98));
381 printf_debug("0x9C: 0x%08x (OPMENU+4)\n",
382 *(uint32_t *) (spibar + 0x9C));
383 printf_debug("0xA0: 0x%08x (BBAR)\n",
384 *(uint32_t *) (spibar + 0xA0));
Carl-Daniel Hailfingerd3b0e392008-11-03 00:20:22 +0000385 printf_debug("0xB0: 0x%08x (FDOC)\n",
386 *(uint32_t *) (spibar + 0xB0));
FENG yu ning37179b82009-01-18 06:39:32 +0000387 if (tmp2 & (1 << 15)) {
388 printf("WARNING: SPI Configuration Lockdown activated.\n");
389 ichspi_lock = 1;
390 }
Peter Stugee8a3e4c2008-12-22 14:12:08 +0000391 ich_init_opcodes();
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000392 break;
393 default:
394 /* Nothing */
395 break;
Stefan Reinauera9424d52008-06-27 16:28:34 +0000396 }
397
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000398 old = pci_read_byte(dev, 0xdc);
399 printf_debug("SPI Read Configuration: ");
400 new = (old >> 2) & 0x3;
401 switch (new) {
402 case 0:
403 case 1:
404 case 2:
405 printf_debug("prefetching %sabled, caching %sabled, ",
Uwe Hermann394131e2008-10-18 21:14:13 +0000406 (new & 0x2) ? "en" : "dis",
407 (new & 0x1) ? "dis" : "en");
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000408 break;
409 default:
410 printf_debug("invalid prefetching/caching settings, ");
411 break;
412 }
Carl-Daniel Hailfinger67f9ea32008-03-14 17:20:59 +0000413
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000414 return ret;
415}
Stefan Reinauera9424d52008-06-27 16:28:34 +0000416
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000417static int enable_flash_ich7(struct pci_dev *dev, const char *name)
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000418{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000419 return enable_flash_ich_dc_spi(dev, name, 7);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000420}
421
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000422static int enable_flash_ich8(struct pci_dev *dev, const char *name)
423{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000424 return enable_flash_ich_dc_spi(dev, name, 8);
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000425}
426
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000427static int enable_flash_ich9(struct pci_dev *dev, const char *name)
428{
Stefan Reinauer2cb94e12008-06-30 23:45:22 +0000429 return enable_flash_ich_dc_spi(dev, name, 9);
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000430}
431
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000432static int enable_flash_ich10(struct pci_dev *dev, const char *name)
433{
434 return enable_flash_ich_dc_spi(dev, name, 10);
435}
436
Uwe Hermann372eeb52007-12-04 21:49:06 +0000437static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000438{
Ollie Lho184a4042005-11-26 21:55:36 +0000439 uint8_t val;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000440
Uwe Hermann394131e2008-10-18 21:14:13 +0000441 /* enable ROM decode range (1MB) FFC00000 - FFFFFFFF */
Bari Ari9477c4e2008-04-29 13:46:38 +0000442 pci_write_byte(dev, 0x41, 0x7f);
443
Uwe Hermannffec5f32007-08-23 16:08:21 +0000444 /* ROM write enable */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000445 val = pci_read_byte(dev, 0x40);
446 val |= 0x10;
447 pci_write_byte(dev, 0x40, val);
448
449 if (pci_read_byte(dev, 0x40) != val) {
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000450 printf("\nWARNING: Failed to enable ROM Write on \"%s\"\n",
Uwe Hermanna7e05482007-05-09 10:17:44 +0000451 name);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000452 return -1;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000453 }
Luc Verhaegen6382b442007-03-02 22:16:38 +0000454
Uwe Hermanna7e05482007-05-09 10:17:44 +0000455 return 0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000456}
457
Uwe Hermann372eeb52007-12-04 21:49:06 +0000458static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000459{
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000460 uint8_t reg8;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000461
Uwe Hermann394131e2008-10-18 21:14:13 +0000462#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
463#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000464
Uwe Hermann394131e2008-10-18 21:14:13 +0000465#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
466#define ROM_WRITE_ENABLE (1 << 1)
467#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
468#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000469
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000470 /* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
471 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
472 * Make the configured ROM areas writable.
473 */
474 reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
475 reg8 |= LOWER_ROM_ADDRESS_RANGE;
476 reg8 |= UPPER_ROM_ADDRESS_RANGE;
477 reg8 |= ROM_WRITE_ENABLE;
478 pci_write_byte(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000479
Uwe Hermannf4a673b2007-06-06 21:35:45 +0000480 /* Set positive decode on ROM. */
481 reg8 = pci_read_byte(dev, DECODE_CONTROL_REG2);
482 reg8 |= BIOS_ROM_POSITIVE_DECODE;
483 pci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000484
Ollie Lhocbbf1252004-03-17 22:22:08 +0000485 return 0;
486}
487
Mart Raudseppe1344da2008-02-08 10:10:57 +0000488/**
489 * Geode systems write protect the BIOS via RCONFs (cache settings similar
490 * to MTRRs). To unlock, change MSR 0x1808 top byte to 0x22. Reading and
491 * writing to MSRs, however requires instructions rdmsr/wrmsr, which are
492 * ring0 privileged instructions so only the kernel can do the read/write.
493 * This function, therefore, requires that the msr kernel module be loaded
494 * to access these instructions from user space using device /dev/cpu/0/msr.
495 *
496 * This hard-coded location could have potential problems on SMP machines
497 * since it assumes cpu0, but it is safe on the Geode which is not SMP.
498 *
499 * Geode systems also write protect the NOR flash chip itself via MSR_NORF_CTL.
500 * To enable write to NOR Boot flash for the benefit of systems that have such
501 * a setup, raise MSR 0x51400018 WE_CS3 (write enable Boot Flash Chip Select).
502 *
503 * This is probably not portable beyond Linux.
504 */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000505static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
Lane Brooksd54958a2007-11-13 16:45:22 +0000506{
Uwe Hermann394131e2008-10-18 21:14:13 +0000507#define MSR_RCONF_DEFAULT 0x1808
508#define MSR_NORF_CTL 0x51400018
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000509
Lane Brooksd54958a2007-11-13 16:45:22 +0000510 int fd_msr;
511 unsigned char buf[8];
Lane Brooksd54958a2007-11-13 16:45:22 +0000512
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000513 fd_msr = open("/dev/cpu/0/msr", O_RDWR);
Lane Brooksd54958a2007-11-13 16:45:22 +0000514 if (!fd_msr) {
515 perror("open msr");
516 return -1;
517 }
Mart Raudseppe1344da2008-02-08 10:10:57 +0000518
519 if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) {
520 perror("lseek64");
Mart Raudsepp3697ac72008-02-11 14:32:45 +0000521 printf("Cannot operate on MSR. Did you run 'modprobe msr'?\n");
Mart Raudseppe1344da2008-02-08 10:10:57 +0000522 close(fd_msr);
523 return -1;
524 }
525
526 if (read(fd_msr, buf, 8) != 8) {
Mart Raudsepp3697ac72008-02-11 14:32:45 +0000527 perror("read msr");
Mart Raudseppe1344da2008-02-08 10:10:57 +0000528 close(fd_msr);
529 return -1;
530 }
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000531
Lane Brooksd54958a2007-11-13 16:45:22 +0000532 if (buf[7] != 0x22) {
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000533 buf[7] &= 0xfb;
Uwe Hermann394131e2008-10-18 21:14:13 +0000534 if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT,
535 SEEK_SET) == -1) {
Mart Raudseppe1344da2008-02-08 10:10:57 +0000536 perror("lseek64");
537 close(fd_msr);
538 return -1;
539 }
540
Lane Brooksd54958a2007-11-13 16:45:22 +0000541 if (write(fd_msr, buf, 8) < 0) {
542 perror("msr write");
Mart Raudseppe1344da2008-02-08 10:10:57 +0000543 close(fd_msr);
Lane Brooksd54958a2007-11-13 16:45:22 +0000544 return -1;
545 }
Lane Brooksd54958a2007-11-13 16:45:22 +0000546 }
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000547
Mart Raudseppe1344da2008-02-08 10:10:57 +0000548 if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) {
549 perror("lseek64");
550 close(fd_msr);
551 return -1;
552 }
553
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000554 if (read(fd_msr, buf, 8) != 8) {
555 perror("read msr");
Mart Raudseppe1344da2008-02-08 10:10:57 +0000556 close(fd_msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000557 return -1;
558 }
559
560 /* Raise WE_CS3 bit. */
561 buf[0] |= 0x08;
562
Mart Raudseppe1344da2008-02-08 10:10:57 +0000563 if (lseek64(fd_msr, (off64_t) MSR_NORF_CTL, SEEK_SET) == -1) {
564 perror("lseek64");
565 close(fd_msr);
566 return -1;
567 }
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000568 if (write(fd_msr, buf, 8) < 0) {
569 perror("msr write");
Mart Raudseppe1344da2008-02-08 10:10:57 +0000570 close(fd_msr);
Mart Raudsepp0514a5f2008-02-08 09:59:58 +0000571 return -1;
572 }
573
574 close(fd_msr);
575
Uwe Hermann394131e2008-10-18 21:14:13 +0000576#undef MSR_RCONF_DEFAULT
577#undef MSR_NORF_CTL
Lane Brooksd54958a2007-11-13 16:45:22 +0000578 return 0;
579}
580
Uwe Hermann372eeb52007-12-04 21:49:06 +0000581static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000582{
Ollie Lho184a4042005-11-26 21:55:36 +0000583 uint8_t new;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000584
Ollie Lhocbbf1252004-03-17 22:22:08 +0000585 pci_write_byte(dev, 0x52, 0xee);
586
587 new = pci_read_byte(dev, 0x52);
588
589 if (new != 0xee) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000590 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000591 return -1;
592 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000593
Ollie Lhocbbf1252004-03-17 22:22:08 +0000594 return 0;
595}
596
Uwe Hermann372eeb52007-12-04 21:49:06 +0000597static int enable_flash_sis5595(struct pci_dev *dev, const char *name)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000598{
Ollie Lho184a4042005-11-26 21:55:36 +0000599 uint8_t new, newer;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000600
Ollie Lhocbbf1252004-03-17 22:22:08 +0000601 new = pci_read_byte(dev, 0x45);
602
Uwe Hermann372eeb52007-12-04 21:49:06 +0000603 new &= (~0x20); /* Clear bit 5. */
604 new |= 0x4; /* Set bit 2. */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000605
606 pci_write_byte(dev, 0x45, new);
607
608 newer = pci_read_byte(dev, 0x45);
609 if (newer != new) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000610 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000611 printf("Stuck at 0x%x\n", newer);
612 return -1;
613 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000614
Urja Rannikkoa88daa72008-10-18 13:54:30 +0000615 /* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
Uwe Hermann394131e2008-10-18 21:14:13 +0000616 new = pci_read_byte(dev, 0x40);
Urja Rannikkoa88daa72008-10-18 13:54:30 +0000617 new &= 0xFB;
618 new |= 0x3;
Uwe Hermann394131e2008-10-18 21:14:13 +0000619 pci_write_byte(dev, 0x40, new);
620 newer = pci_read_byte(dev, 0x40);
Urja Rannikkoa88daa72008-10-18 13:54:30 +0000621 if (newer != new) {
622 printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
623 printf("Stuck at 0x%x\n", newer);
624 return -1;
625 }
Ollie Lhocbbf1252004-03-17 22:22:08 +0000626 return 0;
627}
628
Uwe Hermann190f8492008-10-25 18:03:50 +0000629/* Works for AMD-8111, VIA VT82C586A/B, VIA VT82C686A/B. */
Uwe Hermann372eeb52007-12-04 21:49:06 +0000630static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
Ollie Lho761bf1b2004-03-20 16:46:10 +0000631{
Ollie Lho184a4042005-11-26 21:55:36 +0000632 uint8_t old, new;
Uwe Hermanna7e05482007-05-09 10:17:44 +0000633
Uwe Hermann372eeb52007-12-04 21:49:06 +0000634 /* Enable decoding at 0xffb00000 to 0xffffffff. */
Ollie Lhocbbf1252004-03-17 22:22:08 +0000635 old = pci_read_byte(dev, 0x43);
Ollie Lhod11f3612004-12-07 17:19:04 +0000636 new = old | 0xC0;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000637 if (new != old) {
638 pci_write_byte(dev, 0x43, new);
639 if (pci_read_byte(dev, 0x43) != new) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000640 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000641 }
642 }
643
Uwe Hermann190f8492008-10-25 18:03:50 +0000644 /* Enable 'ROM write' bit. */
Ollie Lho761bf1b2004-03-20 16:46:10 +0000645 old = pci_read_byte(dev, 0x40);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000646 new = old | 0x01;
647 if (new == old)
648 return 0;
649 pci_write_byte(dev, 0x40, new);
650
651 if (pci_read_byte(dev, 0x40) != new) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000652 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000653 return -1;
654 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000655
Ollie Lhocbbf1252004-03-17 22:22:08 +0000656 return 0;
657}
658
Marc Jones3af487d2008-10-15 17:50:29 +0000659static int enable_flash_sb600(struct pci_dev *dev, const char *name)
660{
Jason Wanga3f04be2008-11-28 21:36:51 +0000661 uint32_t tmp, low_bits, num;
Marc Jones3af487d2008-10-15 17:50:29 +0000662 uint8_t reg;
663
Jason Wanga3f04be2008-11-28 21:36:51 +0000664 low_bits = tmp = pci_read_long(dev, 0xa0);
665 low_bits &= ~0xffffc000; /* for mmap aligning requirements */
666 low_bits &= 0xfffffff0; /* remove low 4 bits */
667 tmp &= 0xffffc000;
668 printf_debug("SPI base address is at 0x%x\n", tmp + low_bits);
669
Stefan Reinauer0593f212009-01-26 01:10:48 +0000670 sb600_spibar = physmap("SB600 SPI registers", tmp, 0x4000);
Jason Wanga3f04be2008-11-28 21:36:51 +0000671 sb600_spibar += low_bits;
672
673 /* Clear ROM protect 0-3. */
674 for (reg = 0x50; reg < 0x60; reg += 4) {
675 num = pci_read_long(dev, reg);
676 num &= 0xfffffffc;
677 pci_write_byte(dev, reg, num);
678 }
679
680 flashbus = BUS_TYPE_SB600_SPI;
681
682 /* Enable SPI ROM in SB600 PM register. */
683 OUTB(0x8f, 0xcd6);
684 OUTB(0x0e, 0xcd7);
Marc Jones3af487d2008-10-15 17:50:29 +0000685
686 return 0;
687}
688
Uwe Hermann372eeb52007-12-04 21:49:06 +0000689static int enable_flash_ck804(struct pci_dev *dev, const char *name)
Yinghai Lu952dfce2005-07-06 17:13:46 +0000690{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000691 uint8_t old, new;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000692
Uwe Hermanna7e05482007-05-09 10:17:44 +0000693 old = pci_read_byte(dev, 0x88);
694 new = old | 0xc0;
695 if (new != old) {
696 pci_write_byte(dev, 0x88, new);
697 if (pci_read_byte(dev, 0x88) != new) {
698 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name);
699 }
700 }
Yinghai Lu952dfce2005-07-06 17:13:46 +0000701
Uwe Hermanna7e05482007-05-09 10:17:44 +0000702 old = pci_read_byte(dev, 0x6d);
703 new = old | 0x01;
704 if (new == old)
705 return 0;
706 pci_write_byte(dev, 0x6d, new);
707
708 if (pci_read_byte(dev, 0x6d) != new) {
709 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
710 return -1;
711 }
Uwe Hermannffec5f32007-08-23 16:08:21 +0000712
Uwe Hermanna7e05482007-05-09 10:17:44 +0000713 return 0;
Yinghai Lu952dfce2005-07-06 17:13:46 +0000714}
715
Uwe Hermann372eeb52007-12-04 21:49:06 +0000716/* ATI Technologies Inc IXP SB400 PCI-ISA Bridge (rev 80) */
717static int enable_flash_sb400(struct pci_dev *dev, const char *name)
Stefan Reinauer86de2832006-03-31 11:26:55 +0000718{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000719 uint8_t tmp;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000720 struct pci_filter f;
721 struct pci_dev *smbusdev;
722
Uwe Hermann372eeb52007-12-04 21:49:06 +0000723 /* Look for the SMBus device. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000724 pci_filter_init((struct pci_access *)0, &f);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000725 f.vendor = 0x1002;
726 f.device = 0x4372;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000727
Stefan Reinauer86de2832006-03-31 11:26:55 +0000728 for (smbusdev = pacc->devices; smbusdev; smbusdev = smbusdev->next) {
Uwe Hermann394131e2008-10-18 21:14:13 +0000729 if (pci_filter_match(&f, smbusdev))
Stefan Reinauer86de2832006-03-31 11:26:55 +0000730 break;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000731 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000732
Uwe Hermanna7e05482007-05-09 10:17:44 +0000733 if (!smbusdev) {
Uwe Hermann372eeb52007-12-04 21:49:06 +0000734 fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n");
Stefan Reinauer86de2832006-03-31 11:26:55 +0000735 exit(1);
736 }
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000737
Uwe Hermann372eeb52007-12-04 21:49:06 +0000738 /* Enable some SMBus stuff. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000739 tmp = pci_read_byte(smbusdev, 0x79);
740 tmp |= 0x01;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000741 pci_write_byte(smbusdev, 0x79, tmp);
742
Uwe Hermann372eeb52007-12-04 21:49:06 +0000743 /* Change southbridge. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000744 tmp = pci_read_byte(dev, 0x48);
745 tmp |= 0x21;
Stefan Reinauer86de2832006-03-31 11:26:55 +0000746 pci_write_byte(dev, 0x48, tmp);
747
Uwe Hermann372eeb52007-12-04 21:49:06 +0000748 /* Now become a bit silly. */
Andriy Gapon65c1b862008-05-22 13:22:45 +0000749 tmp = INB(0xc6f);
750 OUTB(tmp, 0xeb);
751 OUTB(tmp, 0xeb);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000752 tmp |= 0x40;
Andriy Gapon65c1b862008-05-22 13:22:45 +0000753 OUTB(tmp, 0xc6f);
754 OUTB(tmp, 0xeb);
755 OUTB(tmp, 0xeb);
Stefan Reinauer86de2832006-03-31 11:26:55 +0000756
757 return 0;
758}
759
Uwe Hermann372eeb52007-12-04 21:49:06 +0000760static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
Yinghai Luca782972007-01-22 20:21:17 +0000761{
Uwe Hermann372eeb52007-12-04 21:49:06 +0000762 uint8_t old, new, byte;
763 uint16_t word;
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000764
Uwe Hermann372eeb52007-12-04 21:49:06 +0000765 /* Set the 0-16 MB enable bits. */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000766 byte = pci_read_byte(dev, 0x88);
767 byte |= 0xff; /* 256K */
768 pci_write_byte(dev, 0x88, byte);
769 byte = pci_read_byte(dev, 0x8c);
770 byte |= 0xff; /* 1M */
771 pci_write_byte(dev, 0x8c, byte);
772 word = pci_read_word(dev, 0x90);
Carl-Daniel Hailfingerdca0ab12007-10-17 22:30:07 +0000773 word |= 0x7fff; /* 16M */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000774 pci_write_word(dev, 0x90, word);
Luc Verhaegen8e3a6002007-04-04 22:45:58 +0000775
Uwe Hermanna7e05482007-05-09 10:17:44 +0000776 old = pci_read_byte(dev, 0x6d);
777 new = old | 0x01;
778 if (new == old)
779 return 0;
780 pci_write_byte(dev, 0x6d, new);
Yinghai Luca782972007-01-22 20:21:17 +0000781
Uwe Hermanna7e05482007-05-09 10:17:44 +0000782 if (pci_read_byte(dev, 0x6d) != new) {
Uwe Hermann394131e2008-10-18 21:14:13 +0000783 printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000784 return -1;
785 }
Yinghai Luca782972007-01-22 20:21:17 +0000786
787 return 0;
Yinghai Luca782972007-01-22 20:21:17 +0000788}
789
Uwe Hermann372eeb52007-12-04 21:49:06 +0000790static int enable_flash_ht1000(struct pci_dev *dev, const char *name)
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000791{
Uwe Hermanne823ee02007-06-05 15:02:18 +0000792 uint8_t byte;
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000793
Uwe Hermanne823ee02007-06-05 15:02:18 +0000794 /* Set the 4MB enable bit. */
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000795 byte = pci_read_byte(dev, 0x41);
796 byte |= 0x0e;
797 pci_write_byte(dev, 0x41, byte);
798
799 byte = pci_read_byte(dev, 0x43);
Uwe Hermannffec5f32007-08-23 16:08:21 +0000800 byte |= (1 << 4);
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000801 pci_write_byte(dev, 0x43, byte);
802
Stefan Reinauerc868b9e2007-06-05 10:28:39 +0000803 return 0;
804}
805
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000806/**
807 * Usually on the x86 architectures (and on other PC-like platforms like some
808 * Alphas or Itanium) the system flash is mapped right below 4G. On the AMD
809 * Elan SC520 only a small piece of the system flash is mapped there, but the
810 * complete flash is mapped somewhere below 1G. The position can be determined
811 * by the BOOTCS PAR register.
812 */
813static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
814{
815 int i, bootcs_found = 0;
816 uint32_t parx = 0;
817 void *mmcr;
818
819 /* 1. Map MMCR */
Stefan Reinauer0593f212009-01-26 01:10:48 +0000820 mmcr = physmap("Elan SC520 MMCR", 0xfffef000, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000821
822 /* 2. Scan PAR0 (0x88) - PAR15 (0xc4) for
823 * BOOTCS region (PARx[31:29] = 100b)e
824 */
825 for (i = 0x88; i <= 0xc4; i += 4) {
826 parx = *(volatile uint32_t *)(mmcr + i);
827 if ((parx >> 29) == 4) {
828 bootcs_found = 1;
829 break; /* BOOTCS found */
830 }
831 }
832
833 /* 3. PARx[25] = 1b --> flashbase[29:16] = PARx[13:0]
834 * PARx[25] = 0b --> flashbase[29:12] = PARx[17:0]
835 */
836 if (bootcs_found) {
837 if (parx & (1 << 25)) {
838 parx &= (1 << 14) - 1; /* Mask [13:0] */
839 flashbase = parx << 16;
840 } else {
841 parx &= (1 << 18) - 1; /* Mask [17:0] */
842 flashbase = parx << 12;
843 }
844 } else {
845 printf("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n");
846 }
847
848 /* 4. Clean up */
Uwe Hermann7b2969b2009-04-15 10:52:49 +0000849 munmap(mmcr, getpagesize());
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000850 return 0;
851}
852
Ollie Lhocbbf1252004-03-17 22:22:08 +0000853typedef struct penable {
Uwe Hermann372eeb52007-12-04 21:49:06 +0000854 uint16_t vendor, device;
855 const char *name;
856 int (*doit) (struct pci_dev *dev, const char *name);
Ollie Lhocbbf1252004-03-17 22:22:08 +0000857} FLASH_ENABLE;
858
Uwe Hermann372eeb52007-12-04 21:49:06 +0000859static const FLASH_ENABLE enables[] = {
Uwe Hermanneac10162008-03-13 18:52:51 +0000860 {0x1039, 0x0630, "SiS630", enable_flash_sis630},
Uwe Hermann87203452008-10-26 18:40:42 +0000861 {0x8086, 0x122e, "Intel PIIX", enable_flash_piix4},
Uwe Hermannc556d322008-10-28 11:50:05 +0000862 {0x8086, 0x1234, "Intel MPIIX", enable_flash_piix4},
Uwe Hermann87203452008-10-26 18:40:42 +0000863 {0x8086, 0x7000, "Intel PIIX3", enable_flash_piix4},
Uwe Hermanneac10162008-03-13 18:52:51 +0000864 {0x8086, 0x7110, "Intel PIIX4/4E/4M", enable_flash_piix4},
865 {0x8086, 0x7198, "Intel 440MX", enable_flash_piix4},
866 {0x8086, 0x2410, "Intel ICH", enable_flash_ich_4e},
867 {0x8086, 0x2420, "Intel ICH0", enable_flash_ich_4e},
868 {0x8086, 0x2440, "Intel ICH2", enable_flash_ich_4e},
869 {0x8086, 0x244c, "Intel ICH2-M", enable_flash_ich_4e},
870 {0x8086, 0x2480, "Intel ICH3-S", enable_flash_ich_4e},
871 {0x8086, 0x248c, "Intel ICH3-M", enable_flash_ich_4e},
872 {0x8086, 0x24c0, "Intel ICH4/ICH4-L", enable_flash_ich_4e},
873 {0x8086, 0x24cc, "Intel ICH4-M", enable_flash_ich_4e},
874 {0x8086, 0x24d0, "Intel ICH5/ICH5R", enable_flash_ich_4e},
Claus Gindharta00e2a02008-05-14 12:22:38 +0000875 {0x8086, 0x25a1, "Intel 6300ESB", enable_flash_ich_4e},
Sven Schnelleed2352b2009-01-07 12:11:13 +0000876 {0x8086, 0x2670, "Intel 631xESB/632xESB/3100", enable_flash_ich_dc},
Uwe Hermanneac10162008-03-13 18:52:51 +0000877 {0x8086, 0x2640, "Intel ICH6/ICH6R", enable_flash_ich_dc},
878 {0x8086, 0x2641, "Intel ICH6-M", enable_flash_ich_dc},
Ed Swierkb759db22008-10-29 14:54:36 +0000879 {0x8086, 0x5031, "Intel EP80579", enable_flash_ich7},
Carl-Daniel Hailfinger1b18b3c2008-05-16 14:39:39 +0000880 {0x8086, 0x27b0, "Intel ICH7DH", enable_flash_ich7},
881 {0x8086, 0x27b8, "Intel ICH7/ICH7R", enable_flash_ich7},
882 {0x8086, 0x27b9, "Intel ICH7M", enable_flash_ich7},
883 {0x8086, 0x27bd, "Intel ICH7MDH", enable_flash_ich7},
884 {0x8086, 0x2810, "Intel ICH8/ICH8R", enable_flash_ich8},
885 {0x8086, 0x2811, "Intel ICH8M-E", enable_flash_ich8},
886 {0x8086, 0x2812, "Intel ICH8DH", enable_flash_ich8},
887 {0x8086, 0x2814, "Intel ICH8DO", enable_flash_ich8},
888 {0x8086, 0x2815, "Intel ICH8M", enable_flash_ich8},
Carl-Daniel Hailfinger6dc1d3b2008-05-14 14:51:22 +0000889 {0x8086, 0x2912, "Intel ICH9DH", enable_flash_ich9},
890 {0x8086, 0x2914, "Intel ICH9DO", enable_flash_ich9},
891 {0x8086, 0x2916, "Intel ICH9R", enable_flash_ich9},
892 {0x8086, 0x2917, "Intel ICH9M-E", enable_flash_ich9},
893 {0x8086, 0x2918, "Intel ICH9", enable_flash_ich9},
894 {0x8086, 0x2919, "Intel ICH9M", enable_flash_ich9},
Carl-Daniel Hailfinger28ec74b2008-10-10 20:54:41 +0000895 {0x8086, 0x3a14, "Intel ICH10DO", enable_flash_ich10},
896 {0x8086, 0x3a16, "Intel ICH10R", enable_flash_ich10},
897 {0x8086, 0x3a18, "Intel ICH10", enable_flash_ich10},
898 {0x8086, 0x3a1a, "Intel ICH10D", enable_flash_ich10},
Uwe Hermanneac10162008-03-13 18:52:51 +0000899 {0x1106, 0x8231, "VIA VT8231", enable_flash_vt823x},
900 {0x1106, 0x3177, "VIA VT8235", enable_flash_vt823x},
901 {0x1106, 0x3227, "VIA VT8237", enable_flash_vt823x},
Peter Stuge20ed5d12009-01-26 15:29:27 +0000902 {0x1106, 0x3337, "VIA VT8237A", enable_flash_vt823x},
Rudolf Marek3fdbccf2008-06-30 21:38:30 +0000903 {0x1106, 0x3372, "VIA VT8237S", enable_flash_vt8237s_spi},
Uwe Hermanneac10162008-03-13 18:52:51 +0000904 {0x1106, 0x8324, "VIA CX700", enable_flash_vt823x},
Uwe Hermann190f8492008-10-25 18:03:50 +0000905 {0x1106, 0x0586, "VIA VT82C586A/B", enable_flash_amd8111},
906 {0x1106, 0x0686, "VIA VT82C686A/B", enable_flash_amd8111},
Uwe Hermanneac10162008-03-13 18:52:51 +0000907 {0x1078, 0x0100, "AMD CS5530(A)", enable_flash_cs5530},
908 {0x100b, 0x0510, "AMD SC1100", enable_flash_sc1100},
909 {0x1039, 0x0008, "SiS5595", enable_flash_sis5595},
910 {0x1022, 0x2080, "AMD CS5536", enable_flash_cs5536},
911 {0x1022, 0x7468, "AMD8111", enable_flash_amd8111},
Marc Jones3af487d2008-10-15 17:50:29 +0000912 {0x1002, 0x438D, "ATI(AMD) SB600", enable_flash_sb600},
Niels Ole Salscheiderf63c0dc2008-12-05 11:58:43 +0000913 {0x1002, 0x439d, "ATI(AMD) SB700", enable_flash_sb600},
Uwe Hermanneac10162008-03-13 18:52:51 +0000914 {0x10B9, 0x1533, "ALi M1533", enable_flash_ali_m1533},
915 {0x10de, 0x0050, "NVIDIA CK804", enable_flash_ck804}, /* LPC */
916 {0x10de, 0x0051, "NVIDIA CK804", enable_flash_ck804}, /* Pro */
917 /* Slave, should not be here, to fix known bug for A01. */
918 {0x10de, 0x00d3, "NVIDIA CK804", enable_flash_ck804},
919 {0x10de, 0x0260, "NVIDIA MCP51", enable_flash_ck804},
920 {0x10de, 0x0261, "NVIDIA MCP51", enable_flash_ck804},
921 {0x10de, 0x0262, "NVIDIA MCP51", enable_flash_ck804},
922 {0x10de, 0x0263, "NVIDIA MCP51", enable_flash_ck804},
923 {0x10de, 0x0360, "NVIDIA MCP55", enable_flash_mcp55}, /* M57SLI*/
924 {0x10de, 0x0361, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
925 {0x10de, 0x0362, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
926 {0x10de, 0x0363, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
927 {0x10de, 0x0364, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
928 {0x10de, 0x0365, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
929 {0x10de, 0x0366, "NVIDIA MCP55", enable_flash_mcp55}, /* LPC */
930 {0x10de, 0x0367, "NVIDIA MCP55", enable_flash_mcp55}, /* Pro */
Stefan Reinauer7f274642008-07-05 09:48:30 +0000931 {0x10de, 0x0548, "NVIDIA MCP67", enable_flash_mcp55},
Uwe Hermanneac10162008-03-13 18:52:51 +0000932 {0x1002, 0x4377, "ATI SB400", enable_flash_sb400},
933 {0x1166, 0x0205, "Broadcom HT-1000", enable_flash_ht1000},
Stefan Reinauer9a6d1762008-12-03 21:24:40 +0000934 {0x1022, 0x3000, "AMD Elan SC520", get_flashbase_sc520},
Sven Schnelleb5d677b2009-01-07 12:15:46 +0000935 {0x1022, 0x7440, "AMD AMD-768", enable_flash_amd8111},
Ollie Lhocbbf1252004-03-17 22:22:08 +0000936};
Ollie Lho761bf1b2004-03-20 16:46:10 +0000937
Uwe Hermanne5ac1642008-03-12 11:54:51 +0000938void print_supported_chipsets(void)
939{
940 int i;
941
942 printf("\nSupported chipsets:\n\n");
943
944 for (i = 0; i < ARRAY_SIZE(enables); i++)
945 printf("%s (%04x:%04x)\n", enables[i].name,
946 enables[i].vendor, enables[i].device);
947}
948
Uwe Hermanna7e05482007-05-09 10:17:44 +0000949int chipset_flash_enable(void)
Ollie Lhocbbf1252004-03-17 22:22:08 +0000950{
Uwe Hermanna7e05482007-05-09 10:17:44 +0000951 struct pci_dev *dev = 0;
Uwe Hermann372eeb52007-12-04 21:49:06 +0000952 int ret = -2; /* Nothing! */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000953 int i;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000954
Uwe Hermann372eeb52007-12-04 21:49:06 +0000955 /* Now let's try to find the chipset we have... */
Uwe Hermanne5ac1642008-03-12 11:54:51 +0000956 for (i = 0; i < ARRAY_SIZE(enables); i++) {
Uwe Hermanna7e05482007-05-09 10:17:44 +0000957 dev = pci_dev_find(enables[i].vendor, enables[i].device);
958 if (dev)
959 break;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000960 }
961
Uwe Hermanna7e05482007-05-09 10:17:44 +0000962 if (dev) {
Uwe Hermanna502dce2007-10-17 23:55:15 +0000963 printf("Found chipset \"%s\", enabling flash write... ",
Uwe Hermanna7e05482007-05-09 10:17:44 +0000964 enables[i].name);
965
966 ret = enables[i].doit(dev, enables[i].name);
967 if (ret)
Uwe Hermanna502dce2007-10-17 23:55:15 +0000968 printf("FAILED!\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +0000969 else
Uwe Hermannac309342007-10-10 17:42:20 +0000970 printf("OK.\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +0000971 }
972
973 return ret;
Ollie Lhocbbf1252004-03-17 22:22:08 +0000974}