Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 1 | /* |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 2 | * This file is part of the flashrom project. |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 3 | * |
Uwe Hermann | d22a1d4 | 2007-09-09 20:21:05 +0000 | [diff] [blame] | 4 | * Copyright (C) 2000 Silicon Integrated System Corporation |
| 5 | * Copyright (C) 2006 Giampiero Giancipoli <gianci@email.it> |
| 6 | * Copyright (C) 2006 coresystems GmbH <info@coresystems.de> |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 7 | * Copyright (C) 2007 Carl-Daniel Hailfinger |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 8 | * Copyright (C) 2009 Sean Nelson <audiohacked@gmail.com> |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 9 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | * (at your option) any later version. |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 14 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 19 | * |
Uwe Hermann | d110764 | 2007-08-29 17:52:32 +0000 | [diff] [blame] | 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 23 | */ |
| 24 | |
| 25 | #include "flash.h" |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 26 | |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 27 | #define MAX_REFLASH_TRIES 0x10 |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 28 | #define MASK_FULL 0xffff |
| 29 | #define MASK_2AA 0x7ff |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 30 | #define MASK_AAA 0xfff |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 31 | |
Carl-Daniel Hailfinger | a758f51 | 2008-05-14 12:03:06 +0000 | [diff] [blame] | 32 | /* Check one byte for odd parity */ |
| 33 | uint8_t oddparity(uint8_t val) |
| 34 | { |
| 35 | val = (val ^ (val >> 4)) & 0xf; |
| 36 | val = (val ^ (val >> 2)) & 0x3; |
| 37 | return (val ^ (val >> 1)) & 0x1; |
| 38 | } |
| 39 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 40 | static void toggle_ready_jedec_common(const struct flashctx *flash, |
| 41 | chipaddr dst, int delay) |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 42 | { |
| 43 | unsigned int i = 0; |
| 44 | uint8_t tmp1, tmp2; |
| 45 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 46 | tmp1 = chip_readb(flash, dst) & 0x40; |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 47 | |
| 48 | while (i++ < 0xFFFFFFF) { |
Carl-Daniel Hailfinger | aa00098 | 2009-12-17 16:20:26 +0000 | [diff] [blame] | 49 | if (delay) |
| 50 | programmer_delay(delay); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 51 | tmp2 = chip_readb(flash, dst) & 0x40; |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 52 | if (tmp1 == tmp2) { |
| 53 | break; |
| 54 | } |
| 55 | tmp1 = tmp2; |
| 56 | } |
Carl-Daniel Hailfinger | aa00098 | 2009-12-17 16:20:26 +0000 | [diff] [blame] | 57 | if (i > 0x100000) |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 58 | msg_cdbg("%s: excessive loops, i=0x%x\n", __func__, i); |
Carl-Daniel Hailfinger | aa00098 | 2009-12-17 16:20:26 +0000 | [diff] [blame] | 59 | } |
| 60 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 61 | void toggle_ready_jedec(const struct flashctx *flash, chipaddr dst) |
Carl-Daniel Hailfinger | aa00098 | 2009-12-17 16:20:26 +0000 | [diff] [blame] | 62 | { |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 63 | toggle_ready_jedec_common(flash, dst, 0); |
Carl-Daniel Hailfinger | aa00098 | 2009-12-17 16:20:26 +0000 | [diff] [blame] | 64 | } |
| 65 | |
| 66 | /* Some chips require a minimum delay between toggle bit reads. |
| 67 | * The Winbond W39V040C wants 50 ms between reads on sector erase toggle, |
| 68 | * but experiments show that 2 ms are already enough. Pick a safety factor |
| 69 | * of 4 and use an 8 ms delay. |
| 70 | * Given that erase is slow on all chips, it is recommended to use |
| 71 | * toggle_ready_jedec_slow in erase functions. |
| 72 | */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 73 | static void toggle_ready_jedec_slow(const struct flashctx *flash, chipaddr dst) |
Carl-Daniel Hailfinger | aa00098 | 2009-12-17 16:20:26 +0000 | [diff] [blame] | 74 | { |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 75 | toggle_ready_jedec_common(flash, dst, 8 * 1000); |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 76 | } |
| 77 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 78 | void data_polling_jedec(const struct flashctx *flash, chipaddr dst, |
| 79 | uint8_t data) |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 80 | { |
| 81 | unsigned int i = 0; |
| 82 | uint8_t tmp; |
| 83 | |
| 84 | data &= 0x80; |
| 85 | |
| 86 | while (i++ < 0xFFFFFFF) { |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 87 | tmp = chip_readb(flash, dst) & 0x80; |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 88 | if (tmp == data) { |
| 89 | break; |
| 90 | } |
| 91 | } |
Carl-Daniel Hailfinger | aa00098 | 2009-12-17 16:20:26 +0000 | [diff] [blame] | 92 | if (i > 0x100000) |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 93 | msg_cdbg("%s: excessive loops, i=0x%x\n", __func__, i); |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 94 | } |
| 95 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 96 | static unsigned int getaddrmask(struct flashctx *flash) |
Carl-Daniel Hailfinger | 79e6757 | 2010-10-13 21:49:30 +0000 | [diff] [blame] | 97 | { |
| 98 | switch (flash->feature_bits & FEATURE_ADDR_MASK) { |
| 99 | case FEATURE_ADDR_FULL: |
| 100 | return MASK_FULL; |
| 101 | break; |
| 102 | case FEATURE_ADDR_2AA: |
| 103 | return MASK_2AA; |
| 104 | break; |
| 105 | case FEATURE_ADDR_AAA: |
| 106 | return MASK_AAA; |
| 107 | break; |
| 108 | default: |
| 109 | msg_cerr("%s called with unknown mask\n", __func__); |
| 110 | return 0; |
| 111 | break; |
| 112 | } |
| 113 | } |
| 114 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 115 | static void start_program_jedec_common(struct flashctx *flash, |
| 116 | unsigned int mask) |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 117 | { |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 118 | chipaddr bios = flash->virtual_memory; |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 119 | chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); |
| 120 | chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); |
| 121 | chip_writeb(flash, 0xA0, bios + (0x5555 & mask)); |
Uwe Hermann | 51582f2 | 2007-08-23 10:20:40 +0000 | [diff] [blame] | 122 | } |
| 123 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 124 | static int probe_jedec_common(struct flashctx *flash, unsigned int mask) |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 125 | { |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 126 | chipaddr bios = flash->virtual_memory; |
Ollie Lho | 184a404 | 2005-11-26 21:55:36 +0000 | [diff] [blame] | 127 | uint8_t id1, id2; |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 128 | uint32_t largeid1, largeid2; |
Carl-Daniel Hailfinger | 8130f2d | 2009-05-11 14:40:31 +0000 | [diff] [blame] | 129 | uint32_t flashcontent1, flashcontent2; |
Maciej Pijanka | c6e1111 | 2009-06-03 14:46:22 +0000 | [diff] [blame] | 130 | int probe_timing_enter, probe_timing_exit; |
| 131 | |
| 132 | if (flash->probe_timing > 0) |
| 133 | probe_timing_enter = probe_timing_exit = flash->probe_timing; |
| 134 | else if (flash->probe_timing == TIMING_ZERO) { /* No delay. */ |
| 135 | probe_timing_enter = probe_timing_exit = 0; |
| 136 | } else if (flash->probe_timing == TIMING_FIXME) { /* == _IGNORED */ |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 137 | msg_cdbg("Chip lacks correct probe timing information, " |
Carl-Daniel Hailfinger | 414bd32 | 2009-07-23 01:33:43 +0000 | [diff] [blame] | 138 | "using default 10mS/40uS. "); |
Maciej Pijanka | c6e1111 | 2009-06-03 14:46:22 +0000 | [diff] [blame] | 139 | probe_timing_enter = 10000; |
| 140 | probe_timing_exit = 40; |
| 141 | } else { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 142 | msg_cerr("Chip has negative value in probe_timing, failing " |
Maciej Pijanka | c6e1111 | 2009-06-03 14:46:22 +0000 | [diff] [blame] | 143 | "without chip access\n"); |
| 144 | return 0; |
| 145 | } |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 146 | |
Sean Nelson | f59e263 | 2010-10-20 21:13:19 +0000 | [diff] [blame] | 147 | /* Earlier probes might have been too fast for the chip to enter ID |
| 148 | * mode completely. Allow the chip to finish this before seeing a |
| 149 | * reset command. |
| 150 | */ |
| 151 | if (probe_timing_enter) |
| 152 | programmer_delay(probe_timing_enter); |
| 153 | /* Reset chip to a clean slate */ |
| 154 | if ((flash->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET) |
| 155 | { |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 156 | chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); |
Sean Nelson | f59e263 | 2010-10-20 21:13:19 +0000 | [diff] [blame] | 157 | if (probe_timing_exit) |
| 158 | programmer_delay(10); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 159 | chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); |
Sean Nelson | f59e263 | 2010-10-20 21:13:19 +0000 | [diff] [blame] | 160 | if (probe_timing_exit) |
| 161 | programmer_delay(10); |
| 162 | } |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 163 | chip_writeb(flash, 0xF0, bios + (0x5555 & mask)); |
Sean Nelson | f59e263 | 2010-10-20 21:13:19 +0000 | [diff] [blame] | 164 | if (probe_timing_exit) |
| 165 | programmer_delay(probe_timing_exit); |
| 166 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 167 | /* Issue JEDEC Product ID Entry command */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 168 | chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); |
Sean Nelson | c12fc71 | 2009-12-17 04:22:40 +0000 | [diff] [blame] | 169 | if (probe_timing_enter) |
| 170 | programmer_delay(10); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 171 | chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); |
Sean Nelson | c12fc71 | 2009-12-17 04:22:40 +0000 | [diff] [blame] | 172 | if (probe_timing_enter) |
| 173 | programmer_delay(10); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 174 | chip_writeb(flash, 0x90, bios + (0x5555 & mask)); |
Sean Nelson | c12fc71 | 2009-12-17 04:22:40 +0000 | [diff] [blame] | 175 | if (probe_timing_enter) |
| 176 | programmer_delay(probe_timing_enter); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 177 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 178 | /* Read product ID */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 179 | id1 = chip_readb(flash, bios); |
| 180 | id2 = chip_readb(flash, bios + 0x01); |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 181 | largeid1 = id1; |
| 182 | largeid2 = id2; |
| 183 | |
| 184 | /* Check if it is a continuation ID, this should be a while loop. */ |
| 185 | if (id1 == 0x7F) { |
| 186 | largeid1 <<= 8; |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 187 | id1 = chip_readb(flash, bios + 0x100); |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 188 | largeid1 |= id1; |
| 189 | } |
| 190 | if (id2 == 0x7F) { |
| 191 | largeid2 <<= 8; |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 192 | id2 = chip_readb(flash, bios + 0x101); |
Carl-Daniel Hailfinger | ae8afa9 | 2007-12-31 01:49:00 +0000 | [diff] [blame] | 193 | largeid2 |= id2; |
| 194 | } |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 195 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 196 | /* Issue JEDEC Product ID Exit command */ |
Sean Nelson | f59e263 | 2010-10-20 21:13:19 +0000 | [diff] [blame] | 197 | if ((flash->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET) |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 198 | { |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 199 | chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 200 | if (probe_timing_exit) |
| 201 | programmer_delay(10); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 202 | chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 203 | if (probe_timing_exit) |
| 204 | programmer_delay(10); |
| 205 | } |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 206 | chip_writeb(flash, 0xF0, bios + (0x5555 & mask)); |
Sean Nelson | c12fc71 | 2009-12-17 04:22:40 +0000 | [diff] [blame] | 207 | if (probe_timing_exit) |
| 208 | programmer_delay(probe_timing_exit); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 209 | |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 210 | msg_cdbg("%s: id1 0x%02x, id2 0x%02x", __func__, largeid1, largeid2); |
Carl-Daniel Hailfinger | a758f51 | 2008-05-14 12:03:06 +0000 | [diff] [blame] | 211 | if (!oddparity(id1)) |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 212 | msg_cdbg(", id1 parity violation"); |
Carl-Daniel Hailfinger | 8130f2d | 2009-05-11 14:40:31 +0000 | [diff] [blame] | 213 | |
| 214 | /* Read the product ID location again. We should now see normal flash contents. */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 215 | flashcontent1 = chip_readb(flash, bios); |
| 216 | flashcontent2 = chip_readb(flash, bios + 0x01); |
Carl-Daniel Hailfinger | 8130f2d | 2009-05-11 14:40:31 +0000 | [diff] [blame] | 217 | |
| 218 | /* Check if it is a continuation ID, this should be a while loop. */ |
| 219 | if (flashcontent1 == 0x7F) { |
| 220 | flashcontent1 <<= 8; |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 221 | flashcontent1 |= chip_readb(flash, bios + 0x100); |
Carl-Daniel Hailfinger | 8130f2d | 2009-05-11 14:40:31 +0000 | [diff] [blame] | 222 | } |
| 223 | if (flashcontent2 == 0x7F) { |
| 224 | flashcontent2 <<= 8; |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 225 | flashcontent2 |= chip_readb(flash, bios + 0x101); |
Carl-Daniel Hailfinger | 8130f2d | 2009-05-11 14:40:31 +0000 | [diff] [blame] | 226 | } |
| 227 | |
| 228 | if (largeid1 == flashcontent1) |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 229 | msg_cdbg(", id1 is normal flash content"); |
Carl-Daniel Hailfinger | 8130f2d | 2009-05-11 14:40:31 +0000 | [diff] [blame] | 230 | if (largeid2 == flashcontent2) |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 231 | msg_cdbg(", id2 is normal flash content"); |
Carl-Daniel Hailfinger | 8130f2d | 2009-05-11 14:40:31 +0000 | [diff] [blame] | 232 | |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 233 | msg_cdbg("\n"); |
Carl-Daniel Hailfinger | e940466 | 2010-01-09 02:24:17 +0000 | [diff] [blame] | 234 | if (largeid1 != flash->manufacture_id || largeid2 != flash->model_id) |
| 235 | return 0; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 236 | |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 237 | if (flash->feature_bits & FEATURE_REGISTERMAP) |
| 238 | map_flash_registers(flash); |
| 239 | |
Carl-Daniel Hailfinger | e940466 | 2010-01-09 02:24:17 +0000 | [diff] [blame] | 240 | return 1; |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 241 | } |
| 242 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 243 | static int erase_sector_jedec_common(struct flashctx *flash, unsigned int page, |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 244 | unsigned int pagesize, unsigned int mask) |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 245 | { |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 246 | chipaddr bios = flash->virtual_memory; |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 247 | int delay_us = 0; |
| 248 | if(flash->probe_timing != TIMING_ZERO) |
| 249 | delay_us = 10; |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 250 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 251 | /* Issue the Sector Erase command */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 252 | chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 253 | programmer_delay(delay_us); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 254 | chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 255 | programmer_delay(delay_us); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 256 | chip_writeb(flash, 0x80, bios + (0x5555 & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 257 | programmer_delay(delay_us); |
Ollie Lho | efa2858 | 2004-12-08 20:10:01 +0000 | [diff] [blame] | 258 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 259 | chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 260 | programmer_delay(delay_us); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 261 | chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 262 | programmer_delay(delay_us); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 263 | chip_writeb(flash, 0x30, bios + page); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 264 | programmer_delay(delay_us); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 265 | |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 266 | /* wait for Toggle bit ready */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 267 | toggle_ready_jedec_slow(flash, bios); |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 268 | |
Carl-Daniel Hailfinger | b4061f6 | 2011-06-26 17:04:16 +0000 | [diff] [blame] | 269 | /* FIXME: Check the status register for errors. */ |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 270 | return 0; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 271 | } |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 272 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 273 | static int erase_block_jedec_common(struct flashctx *flash, unsigned int block, |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 274 | unsigned int blocksize, unsigned int mask) |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 275 | { |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 276 | chipaddr bios = flash->virtual_memory; |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 277 | int delay_us = 0; |
| 278 | if(flash->probe_timing != TIMING_ZERO) |
| 279 | delay_us = 10; |
Carl-Daniel Hailfinger | 30f7cb2 | 2009-06-15 17:23:36 +0000 | [diff] [blame] | 280 | |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 281 | /* Issue the Sector Erase command */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 282 | chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 283 | programmer_delay(delay_us); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 284 | chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 285 | programmer_delay(delay_us); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 286 | chip_writeb(flash, 0x80, bios + (0x5555 & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 287 | programmer_delay(delay_us); |
Ollie Lho | efa2858 | 2004-12-08 20:10:01 +0000 | [diff] [blame] | 288 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 289 | chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 290 | programmer_delay(delay_us); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 291 | chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 292 | programmer_delay(delay_us); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 293 | chip_writeb(flash, 0x50, bios + block); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 294 | programmer_delay(delay_us); |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 295 | |
| 296 | /* wait for Toggle bit ready */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 297 | toggle_ready_jedec_slow(flash, bios); |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 298 | |
Carl-Daniel Hailfinger | b4061f6 | 2011-06-26 17:04:16 +0000 | [diff] [blame] | 299 | /* FIXME: Check the status register for errors. */ |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 300 | return 0; |
Ronald G. Minnich | 1f4d653 | 2004-09-30 16:37:01 +0000 | [diff] [blame] | 301 | } |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 302 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 303 | static int erase_chip_jedec_common(struct flashctx *flash, unsigned int mask) |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 304 | { |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 305 | chipaddr bios = flash->virtual_memory; |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 306 | int delay_us = 0; |
| 307 | if(flash->probe_timing != TIMING_ZERO) |
| 308 | delay_us = 10; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 309 | |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 310 | /* Issue the JEDEC Chip Erase command */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 311 | chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 312 | programmer_delay(delay_us); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 313 | chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 314 | programmer_delay(delay_us); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 315 | chip_writeb(flash, 0x80, bios + (0x5555 & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 316 | programmer_delay(delay_us); |
Ollie Lho | efa2858 | 2004-12-08 20:10:01 +0000 | [diff] [blame] | 317 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 318 | chip_writeb(flash, 0xAA, bios + (0x5555 & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 319 | programmer_delay(delay_us); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 320 | chip_writeb(flash, 0x55, bios + (0x2AAA & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 321 | programmer_delay(delay_us); |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 322 | chip_writeb(flash, 0x10, bios + (0x5555 & mask)); |
Michael Karcher | 880e867 | 2011-04-15 00:03:37 +0000 | [diff] [blame] | 323 | programmer_delay(delay_us); |
Ollie Lho | 73eca80 | 2004-03-19 22:10:07 +0000 | [diff] [blame] | 324 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 325 | toggle_ready_jedec_slow(flash, bios); |
Ronald G. Minnich | eaab50b | 2003-09-12 22:41:53 +0000 | [diff] [blame] | 326 | |
Carl-Daniel Hailfinger | b4061f6 | 2011-06-26 17:04:16 +0000 | [diff] [blame] | 327 | /* FIXME: Check the status register for errors. */ |
Uwe Hermann | ffec5f3 | 2007-08-23 16:08:21 +0000 | [diff] [blame] | 328 | return 0; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 329 | } |
| 330 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 331 | static int write_byte_program_jedec_common(struct flashctx *flash, uint8_t *src, |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 332 | chipaddr dst, unsigned int mask) |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 333 | { |
| 334 | int tried = 0, failed = 0; |
| 335 | chipaddr bios = flash->virtual_memory; |
| 336 | |
| 337 | /* If the data is 0xFF, don't program it and don't complain. */ |
| 338 | if (*src == 0xFF) { |
| 339 | return 0; |
| 340 | } |
| 341 | |
| 342 | retry: |
| 343 | /* Issue JEDEC Byte Program command */ |
| 344 | start_program_jedec_common(flash, mask); |
| 345 | |
| 346 | /* transfer data from source to destination */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 347 | chip_writeb(flash, *src, dst); |
| 348 | toggle_ready_jedec(flash, bios); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 349 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 350 | if (chip_readb(flash, dst) != *src && tried++ < MAX_REFLASH_TRIES) { |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 351 | goto retry; |
| 352 | } |
| 353 | |
| 354 | if (tried >= MAX_REFLASH_TRIES) |
| 355 | failed = 1; |
| 356 | |
| 357 | return failed; |
| 358 | } |
| 359 | |
Carl-Daniel Hailfinger | 75a58f9 | 2010-10-13 22:26:56 +0000 | [diff] [blame] | 360 | /* chunksize is 1 */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 361 | int write_jedec_1(struct flashctx *flash, uint8_t *src, unsigned int start, |
| 362 | unsigned int len) |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 363 | { |
| 364 | int i, failed = 0; |
Carl-Daniel Hailfinger | b30a5ed | 2010-10-10 14:02:27 +0000 | [diff] [blame] | 365 | chipaddr dst = flash->virtual_memory + start; |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 366 | chipaddr olddst; |
Stefan Tauner | c69c9c8 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 367 | unsigned int mask; |
Carl-Daniel Hailfinger | 79e6757 | 2010-10-13 21:49:30 +0000 | [diff] [blame] | 368 | |
| 369 | mask = getaddrmask(flash); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 370 | |
| 371 | olddst = dst; |
Carl-Daniel Hailfinger | b30a5ed | 2010-10-10 14:02:27 +0000 | [diff] [blame] | 372 | for (i = 0; i < len; i++) { |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 373 | if (write_byte_program_jedec_common(flash, src, dst, mask)) |
| 374 | failed = 1; |
| 375 | dst++, src++; |
| 376 | } |
| 377 | if (failed) |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 378 | msg_cerr(" writing sector at 0x%lx failed!\n", olddst); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 379 | |
| 380 | return failed; |
| 381 | } |
| 382 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 383 | int write_page_write_jedec_common(struct flashctx *flash, uint8_t *src, |
| 384 | unsigned int start, unsigned int page_size) |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 385 | { |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 386 | int i, tried = 0, failed; |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 387 | uint8_t *s = src; |
Urja Rannikko | 0c854c0 | 2009-06-25 13:57:31 +0000 | [diff] [blame] | 388 | chipaddr bios = flash->virtual_memory; |
| 389 | chipaddr dst = bios + start; |
| 390 | chipaddr d = dst; |
Stefan Tauner | c69c9c8 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 391 | unsigned int mask; |
Carl-Daniel Hailfinger | 79e6757 | 2010-10-13 21:49:30 +0000 | [diff] [blame] | 392 | |
| 393 | mask = getaddrmask(flash); |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 394 | |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 395 | retry: |
Uwe Hermann | 4e3d0b3 | 2010-03-25 23:18:41 +0000 | [diff] [blame] | 396 | /* Issue JEDEC Start Program command */ |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 397 | start_program_jedec_common(flash, mask); |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 398 | |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 399 | /* transfer data from source to destination */ |
Carl-Daniel Hailfinger | 8a8a226 | 2009-11-14 03:48:33 +0000 | [diff] [blame] | 400 | for (i = 0; i < page_size; i++) { |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 401 | /* If the data is 0xFF, don't program it */ |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 402 | if (*src != 0xFF) |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 403 | chip_writeb(flash, *src, dst); |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 404 | dst++; |
| 405 | src++; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 406 | } |
| 407 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 408 | toggle_ready_jedec(flash, dst - 1); |
Ollie Lho | 98bea8a | 2004-12-07 03:15:51 +0000 | [diff] [blame] | 409 | |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 410 | dst = d; |
| 411 | src = s; |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 412 | failed = verify_range(flash, src, start, page_size, NULL); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 413 | |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 414 | if (failed && tried++ < MAX_REFLASH_TRIES) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 415 | msg_cerr("retrying.\n"); |
Uwe Hermann | a7e0548 | 2007-05-09 10:17:44 +0000 | [diff] [blame] | 416 | goto retry; |
| 417 | } |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 418 | if (failed) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 419 | msg_cerr(" page 0x%lx failed!\n", |
Carl-Daniel Hailfinger | 5820f42 | 2009-05-16 21:22:56 +0000 | [diff] [blame] | 420 | (d - bios) / page_size); |
Giampiero Giancipoli | 8c5299f | 2006-11-22 00:29:51 +0000 | [diff] [blame] | 421 | } |
Carl-Daniel Hailfinger | 2925d6f | 2009-11-25 16:41:50 +0000 | [diff] [blame] | 422 | return failed; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 423 | } |
| 424 | |
Carl-Daniel Hailfinger | 75a58f9 | 2010-10-13 22:26:56 +0000 | [diff] [blame] | 425 | /* chunksize is page_size */ |
Carl-Daniel Hailfinger | 79e6757 | 2010-10-13 21:49:30 +0000 | [diff] [blame] | 426 | /* |
| 427 | * Write a part of the flash chip. |
| 428 | * FIXME: Use the chunk code from Michael Karcher instead. |
| 429 | * This function is a slightly modified copy of spi_write_chunked. |
| 430 | * Each page is written separately in chunks with a maximum size of chunksize. |
| 431 | */ |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 432 | int write_jedec(struct flashctx *flash, uint8_t *buf, unsigned int start, |
| 433 | int unsigned len) |
Carl-Daniel Hailfinger | 4bf4e79 | 2010-01-09 03:15:50 +0000 | [diff] [blame] | 434 | { |
Stefan Tauner | c69c9c8 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 435 | unsigned int i, starthere, lenhere; |
Carl-Daniel Hailfinger | 79e6757 | 2010-10-13 21:49:30 +0000 | [diff] [blame] | 436 | /* FIXME: page_size is the wrong variable. We need max_writechunk_size |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 437 | * in struct flashctx to do this properly. All chips using |
Carl-Daniel Hailfinger | 79e6757 | 2010-10-13 21:49:30 +0000 | [diff] [blame] | 438 | * write_jedec have page_size set to max_writechunk_size, so |
| 439 | * we're OK for now. |
| 440 | */ |
Stefan Tauner | c69c9c8 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 441 | unsigned int page_size = flash->page_size; |
Ollie Lho | 761bf1b | 2004-03-20 16:46:10 +0000 | [diff] [blame] | 442 | |
Carl-Daniel Hailfinger | 79e6757 | 2010-10-13 21:49:30 +0000 | [diff] [blame] | 443 | /* Warning: This loop has a very unusual condition and body. |
| 444 | * The loop needs to go through each page with at least one affected |
| 445 | * byte. The lowest page number is (start / page_size) since that |
| 446 | * division rounds down. The highest page number we want is the page |
| 447 | * where the last byte of the range lives. That last byte has the |
| 448 | * address (start + len - 1), thus the highest page number is |
| 449 | * (start + len - 1) / page_size. Since we want to include that last |
| 450 | * page as well, the loop condition uses <=. |
| 451 | */ |
| 452 | for (i = start / page_size; i <= (start + len - 1) / page_size; i++) { |
| 453 | /* Byte position of the first byte in the range in this page. */ |
| 454 | /* starthere is an offset to the base address of the chip. */ |
| 455 | starthere = max(start, i * page_size); |
| 456 | /* Length of bytes in the range in this page. */ |
| 457 | lenhere = min(start + len, (i + 1) * page_size) - starthere; |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 458 | |
Carl-Daniel Hailfinger | 79e6757 | 2010-10-13 21:49:30 +0000 | [diff] [blame] | 459 | if (write_page_write_jedec_common(flash, buf + starthere - start, starthere, lenhere)) |
| 460 | return 1; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 461 | } |
Ronald G. Minnich | eaab50b | 2003-09-12 22:41:53 +0000 | [diff] [blame] | 462 | |
Carl-Daniel Hailfinger | 79e6757 | 2010-10-13 21:49:30 +0000 | [diff] [blame] | 463 | return 0; |
Ronald G. Minnich | 5e5f75e | 2002-01-29 18:21:41 +0000 | [diff] [blame] | 464 | } |
Michael Karcher | 1c296ca | 2009-11-27 17:49:42 +0000 | [diff] [blame] | 465 | |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 466 | /* erase chip with block_erase() prototype */ |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 467 | int erase_chip_block_jedec(struct flashctx *flash, unsigned int addr, |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 468 | unsigned int blocksize) |
| 469 | { |
Stefan Tauner | c69c9c8 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 470 | unsigned int mask; |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 471 | |
| 472 | mask = getaddrmask(flash); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 473 | if ((addr != 0) || (blocksize != flash->total_size * 1024)) { |
Sean Nelson | ed479d2 | 2010-03-24 23:14:32 +0000 | [diff] [blame] | 474 | msg_cerr("%s called with incorrect arguments\n", |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 475 | __func__); |
| 476 | return -1; |
| 477 | } |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 478 | return erase_chip_jedec_common(flash, mask); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 479 | } |
| 480 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 481 | int probe_jedec(struct flashctx *flash) |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 482 | { |
Stefan Tauner | c69c9c8 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 483 | unsigned int mask; |
Carl-Daniel Hailfinger | 4bf4e79 | 2010-01-09 03:15:50 +0000 | [diff] [blame] | 484 | |
| 485 | mask = getaddrmask(flash); |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 486 | return probe_jedec_common(flash, mask); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 487 | } |
| 488 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 489 | int erase_sector_jedec(struct flashctx *flash, unsigned int page, |
| 490 | unsigned int size) |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 491 | { |
Stefan Tauner | c69c9c8 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 492 | unsigned int mask; |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 493 | |
| 494 | mask = getaddrmask(flash); |
| 495 | return erase_sector_jedec_common(flash, page, size, mask); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 496 | } |
| 497 | |
Carl-Daniel Hailfinger | 8a3c60c | 2011-12-18 15:01:24 +0000 | [diff] [blame] | 498 | int erase_block_jedec(struct flashctx *flash, unsigned int page, |
| 499 | unsigned int size) |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 500 | { |
Stefan Tauner | c69c9c8 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 501 | unsigned int mask; |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 502 | |
| 503 | mask = getaddrmask(flash); |
| 504 | return erase_block_jedec_common(flash, page, size, mask); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 505 | } |
| 506 | |
Carl-Daniel Hailfinger | 63fd902 | 2011-12-14 22:25:15 +0000 | [diff] [blame] | 507 | int erase_chip_jedec(struct flashctx *flash) |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 508 | { |
Stefan Tauner | c69c9c8 | 2011-11-23 09:13:48 +0000 | [diff] [blame] | 509 | unsigned int mask; |
Sean Nelson | 35727f7 | 2010-01-28 23:55:12 +0000 | [diff] [blame] | 510 | |
| 511 | mask = getaddrmask(flash); |
| 512 | return erase_chip_jedec_common(flash, mask); |
Sean Nelson | c57a920 | 2010-01-04 17:15:23 +0000 | [diff] [blame] | 513 | } |