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Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00001/*
Uwe Hermannd1107642007-08-29 17:52:32 +00002 * This file is part of the flashrom project.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00003 *
Uwe Hermannd22a1d42007-09-09 20:21:05 +00004 * Copyright (C) 2000 Silicon Integrated System Corporation
5 * Copyright (C) 2006 Giampiero Giancipoli <gianci@email.it>
6 * Copyright (C) 2006 coresystems GmbH <info@coresystems.de>
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +00007 * Copyright (C) 2007 Carl-Daniel Hailfinger
Sean Nelsonc57a9202010-01-04 17:15:23 +00008 * Copyright (C) 2009 Sean Nelson <audiohacked@gmail.com>
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +00009 *
Uwe Hermannd1107642007-08-29 17:52:32 +000010 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000014 *
Uwe Hermannd1107642007-08-29 17:52:32 +000015 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000019 *
Uwe Hermannd1107642007-08-29 17:52:32 +000020 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000023 */
24
25#include "flash.h"
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +000026
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +000027#define MAX_REFLASH_TRIES 0x10
Sean Nelsonc57a9202010-01-04 17:15:23 +000028#define MASK_FULL 0xffff
29#define MASK_2AA 0x7ff
Sean Nelson35727f72010-01-28 23:55:12 +000030#define MASK_AAA 0xfff
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +000031
Carl-Daniel Hailfingera758f512008-05-14 12:03:06 +000032/* Check one byte for odd parity */
33uint8_t oddparity(uint8_t val)
34{
35 val = (val ^ (val >> 4)) & 0xf;
36 val = (val ^ (val >> 2)) & 0x3;
37 return (val ^ (val >> 1)) & 0x1;
38}
39
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000040static void toggle_ready_jedec_common(const struct flashctx *flash,
41 chipaddr dst, int delay)
Uwe Hermann51582f22007-08-23 10:20:40 +000042{
43 unsigned int i = 0;
44 uint8_t tmp1, tmp2;
45
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000046 tmp1 = chip_readb(flash, dst) & 0x40;
Uwe Hermann51582f22007-08-23 10:20:40 +000047
48 while (i++ < 0xFFFFFFF) {
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000049 if (delay)
50 programmer_delay(delay);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000051 tmp2 = chip_readb(flash, dst) & 0x40;
Uwe Hermann51582f22007-08-23 10:20:40 +000052 if (tmp1 == tmp2) {
53 break;
54 }
55 tmp1 = tmp2;
56 }
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000057 if (i > 0x100000)
Sean Nelsoned479d22010-03-24 23:14:32 +000058 msg_cdbg("%s: excessive loops, i=0x%x\n", __func__, i);
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000059}
60
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000061void toggle_ready_jedec(const struct flashctx *flash, chipaddr dst)
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000062{
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000063 toggle_ready_jedec_common(flash, dst, 0);
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000064}
65
66/* Some chips require a minimum delay between toggle bit reads.
67 * The Winbond W39V040C wants 50 ms between reads on sector erase toggle,
68 * but experiments show that 2 ms are already enough. Pick a safety factor
69 * of 4 and use an 8 ms delay.
70 * Given that erase is slow on all chips, it is recommended to use
71 * toggle_ready_jedec_slow in erase functions.
72 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000073static void toggle_ready_jedec_slow(const struct flashctx *flash, chipaddr dst)
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000074{
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000075 toggle_ready_jedec_common(flash, dst, 8 * 1000);
Uwe Hermann51582f22007-08-23 10:20:40 +000076}
77
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000078void data_polling_jedec(const struct flashctx *flash, chipaddr dst,
79 uint8_t data)
Uwe Hermann51582f22007-08-23 10:20:40 +000080{
81 unsigned int i = 0;
82 uint8_t tmp;
83
84 data &= 0x80;
85
86 while (i++ < 0xFFFFFFF) {
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +000087 tmp = chip_readb(flash, dst) & 0x80;
Uwe Hermann51582f22007-08-23 10:20:40 +000088 if (tmp == data) {
89 break;
90 }
91 }
Carl-Daniel Hailfingeraa000982009-12-17 16:20:26 +000092 if (i > 0x100000)
Sean Nelsoned479d22010-03-24 23:14:32 +000093 msg_cdbg("%s: excessive loops, i=0x%x\n", __func__, i);
Uwe Hermann51582f22007-08-23 10:20:40 +000094}
95
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +000096static unsigned int getaddrmask(struct flashctx *flash)
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +000097{
98 switch (flash->feature_bits & FEATURE_ADDR_MASK) {
99 case FEATURE_ADDR_FULL:
100 return MASK_FULL;
101 break;
102 case FEATURE_ADDR_2AA:
103 return MASK_2AA;
104 break;
105 case FEATURE_ADDR_AAA:
106 return MASK_AAA;
107 break;
108 default:
109 msg_cerr("%s called with unknown mask\n", __func__);
110 return 0;
111 break;
112 }
113}
114
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000115static void start_program_jedec_common(struct flashctx *flash,
116 unsigned int mask)
Uwe Hermann51582f22007-08-23 10:20:40 +0000117{
Sean Nelsonc57a9202010-01-04 17:15:23 +0000118 chipaddr bios = flash->virtual_memory;
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000119 chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
120 chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
121 chip_writeb(flash, 0xA0, bios + (0x5555 & mask));
Uwe Hermann51582f22007-08-23 10:20:40 +0000122}
123
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000124static int probe_jedec_common(struct flashctx *flash, unsigned int mask)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000125{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000126 chipaddr bios = flash->virtual_memory;
Ollie Lho184a4042005-11-26 21:55:36 +0000127 uint8_t id1, id2;
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000128 uint32_t largeid1, largeid2;
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +0000129 uint32_t flashcontent1, flashcontent2;
Maciej Pijankac6e11112009-06-03 14:46:22 +0000130 int probe_timing_enter, probe_timing_exit;
131
132 if (flash->probe_timing > 0)
133 probe_timing_enter = probe_timing_exit = flash->probe_timing;
134 else if (flash->probe_timing == TIMING_ZERO) { /* No delay. */
135 probe_timing_enter = probe_timing_exit = 0;
136 } else if (flash->probe_timing == TIMING_FIXME) { /* == _IGNORED */
Sean Nelsoned479d22010-03-24 23:14:32 +0000137 msg_cdbg("Chip lacks correct probe timing information, "
Carl-Daniel Hailfinger414bd322009-07-23 01:33:43 +0000138 "using default 10mS/40uS. ");
Maciej Pijankac6e11112009-06-03 14:46:22 +0000139 probe_timing_enter = 10000;
140 probe_timing_exit = 40;
141 } else {
Sean Nelsoned479d22010-03-24 23:14:32 +0000142 msg_cerr("Chip has negative value in probe_timing, failing "
Maciej Pijankac6e11112009-06-03 14:46:22 +0000143 "without chip access\n");
144 return 0;
145 }
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000146
Sean Nelsonf59e2632010-10-20 21:13:19 +0000147 /* Earlier probes might have been too fast for the chip to enter ID
148 * mode completely. Allow the chip to finish this before seeing a
149 * reset command.
150 */
151 if (probe_timing_enter)
152 programmer_delay(probe_timing_enter);
153 /* Reset chip to a clean slate */
154 if ((flash->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET)
155 {
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000156 chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
Sean Nelsonf59e2632010-10-20 21:13:19 +0000157 if (probe_timing_exit)
158 programmer_delay(10);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000159 chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
Sean Nelsonf59e2632010-10-20 21:13:19 +0000160 if (probe_timing_exit)
161 programmer_delay(10);
162 }
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000163 chip_writeb(flash, 0xF0, bios + (0x5555 & mask));
Sean Nelsonf59e2632010-10-20 21:13:19 +0000164 if (probe_timing_exit)
165 programmer_delay(probe_timing_exit);
166
Ollie Lho761bf1b2004-03-20 16:46:10 +0000167 /* Issue JEDEC Product ID Entry command */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000168 chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
Sean Nelsonc12fc712009-12-17 04:22:40 +0000169 if (probe_timing_enter)
170 programmer_delay(10);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000171 chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
Sean Nelsonc12fc712009-12-17 04:22:40 +0000172 if (probe_timing_enter)
173 programmer_delay(10);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000174 chip_writeb(flash, 0x90, bios + (0x5555 & mask));
Sean Nelsonc12fc712009-12-17 04:22:40 +0000175 if (probe_timing_enter)
176 programmer_delay(probe_timing_enter);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000177
Ollie Lho761bf1b2004-03-20 16:46:10 +0000178 /* Read product ID */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000179 id1 = chip_readb(flash, bios);
180 id2 = chip_readb(flash, bios + 0x01);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000181 largeid1 = id1;
182 largeid2 = id2;
183
184 /* Check if it is a continuation ID, this should be a while loop. */
185 if (id1 == 0x7F) {
186 largeid1 <<= 8;
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000187 id1 = chip_readb(flash, bios + 0x100);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000188 largeid1 |= id1;
189 }
190 if (id2 == 0x7F) {
191 largeid2 <<= 8;
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000192 id2 = chip_readb(flash, bios + 0x101);
Carl-Daniel Hailfingerae8afa92007-12-31 01:49:00 +0000193 largeid2 |= id2;
194 }
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000195
Ollie Lho761bf1b2004-03-20 16:46:10 +0000196 /* Issue JEDEC Product ID Exit command */
Sean Nelsonf59e2632010-10-20 21:13:19 +0000197 if ((flash->feature_bits & FEATURE_RESET_MASK) == FEATURE_LONG_RESET)
Sean Nelsonc57a9202010-01-04 17:15:23 +0000198 {
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000199 chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
Sean Nelsonc57a9202010-01-04 17:15:23 +0000200 if (probe_timing_exit)
201 programmer_delay(10);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000202 chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
Sean Nelsonc57a9202010-01-04 17:15:23 +0000203 if (probe_timing_exit)
204 programmer_delay(10);
205 }
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000206 chip_writeb(flash, 0xF0, bios + (0x5555 & mask));
Sean Nelsonc12fc712009-12-17 04:22:40 +0000207 if (probe_timing_exit)
208 programmer_delay(probe_timing_exit);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000209
Sean Nelsoned479d22010-03-24 23:14:32 +0000210 msg_cdbg("%s: id1 0x%02x, id2 0x%02x", __func__, largeid1, largeid2);
Carl-Daniel Hailfingera758f512008-05-14 12:03:06 +0000211 if (!oddparity(id1))
Sean Nelsoned479d22010-03-24 23:14:32 +0000212 msg_cdbg(", id1 parity violation");
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +0000213
214 /* Read the product ID location again. We should now see normal flash contents. */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000215 flashcontent1 = chip_readb(flash, bios);
216 flashcontent2 = chip_readb(flash, bios + 0x01);
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +0000217
218 /* Check if it is a continuation ID, this should be a while loop. */
219 if (flashcontent1 == 0x7F) {
220 flashcontent1 <<= 8;
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000221 flashcontent1 |= chip_readb(flash, bios + 0x100);
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +0000222 }
223 if (flashcontent2 == 0x7F) {
224 flashcontent2 <<= 8;
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000225 flashcontent2 |= chip_readb(flash, bios + 0x101);
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +0000226 }
227
228 if (largeid1 == flashcontent1)
Sean Nelsoned479d22010-03-24 23:14:32 +0000229 msg_cdbg(", id1 is normal flash content");
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +0000230 if (largeid2 == flashcontent2)
Sean Nelsoned479d22010-03-24 23:14:32 +0000231 msg_cdbg(", id2 is normal flash content");
Carl-Daniel Hailfinger8130f2d2009-05-11 14:40:31 +0000232
Sean Nelsoned479d22010-03-24 23:14:32 +0000233 msg_cdbg("\n");
Carl-Daniel Hailfingere9404662010-01-09 02:24:17 +0000234 if (largeid1 != flash->manufacture_id || largeid2 != flash->model_id)
235 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000236
Sean Nelsonc57a9202010-01-04 17:15:23 +0000237 if (flash->feature_bits & FEATURE_REGISTERMAP)
238 map_flash_registers(flash);
239
Carl-Daniel Hailfingere9404662010-01-09 02:24:17 +0000240 return 1;
Ollie Lho73eca802004-03-19 22:10:07 +0000241}
242
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000243static int erase_sector_jedec_common(struct flashctx *flash, unsigned int page,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000244 unsigned int pagesize, unsigned int mask)
Ollie Lho73eca802004-03-19 22:10:07 +0000245{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000246 chipaddr bios = flash->virtual_memory;
Michael Karcher880e8672011-04-15 00:03:37 +0000247 int delay_us = 0;
248 if(flash->probe_timing != TIMING_ZERO)
249 delay_us = 10;
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000250
Ollie Lho761bf1b2004-03-20 16:46:10 +0000251 /* Issue the Sector Erase command */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000252 chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000253 programmer_delay(delay_us);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000254 chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000255 programmer_delay(delay_us);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000256 chip_writeb(flash, 0x80, bios + (0x5555 & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000257 programmer_delay(delay_us);
Ollie Lhoefa28582004-12-08 20:10:01 +0000258
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000259 chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000260 programmer_delay(delay_us);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000261 chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000262 programmer_delay(delay_us);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000263 chip_writeb(flash, 0x30, bios + page);
Michael Karcher880e8672011-04-15 00:03:37 +0000264 programmer_delay(delay_us);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000265
Ollie Lho73eca802004-03-19 22:10:07 +0000266 /* wait for Toggle bit ready */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000267 toggle_ready_jedec_slow(flash, bios);
Ollie Lho73eca802004-03-19 22:10:07 +0000268
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000269 /* FIXME: Check the status register for errors. */
Uwe Hermannffec5f32007-08-23 16:08:21 +0000270 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000271}
Ollie Lho98bea8a2004-12-07 03:15:51 +0000272
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000273static int erase_block_jedec_common(struct flashctx *flash, unsigned int block,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000274 unsigned int blocksize, unsigned int mask)
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000275{
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000276 chipaddr bios = flash->virtual_memory;
Michael Karcher880e8672011-04-15 00:03:37 +0000277 int delay_us = 0;
278 if(flash->probe_timing != TIMING_ZERO)
279 delay_us = 10;
Carl-Daniel Hailfinger30f7cb22009-06-15 17:23:36 +0000280
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000281 /* Issue the Sector Erase command */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000282 chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000283 programmer_delay(delay_us);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000284 chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000285 programmer_delay(delay_us);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000286 chip_writeb(flash, 0x80, bios + (0x5555 & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000287 programmer_delay(delay_us);
Ollie Lhoefa28582004-12-08 20:10:01 +0000288
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000289 chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000290 programmer_delay(delay_us);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000291 chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000292 programmer_delay(delay_us);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000293 chip_writeb(flash, 0x50, bios + block);
Michael Karcher880e8672011-04-15 00:03:37 +0000294 programmer_delay(delay_us);
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000295
296 /* wait for Toggle bit ready */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000297 toggle_ready_jedec_slow(flash, bios);
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000298
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000299 /* FIXME: Check the status register for errors. */
Uwe Hermannffec5f32007-08-23 16:08:21 +0000300 return 0;
Ronald G. Minnich1f4d6532004-09-30 16:37:01 +0000301}
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000302
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000303static int erase_chip_jedec_common(struct flashctx *flash, unsigned int mask)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000304{
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000305 chipaddr bios = flash->virtual_memory;
Michael Karcher880e8672011-04-15 00:03:37 +0000306 int delay_us = 0;
307 if(flash->probe_timing != TIMING_ZERO)
308 delay_us = 10;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000309
Ollie Lho761bf1b2004-03-20 16:46:10 +0000310 /* Issue the JEDEC Chip Erase command */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000311 chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000312 programmer_delay(delay_us);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000313 chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000314 programmer_delay(delay_us);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000315 chip_writeb(flash, 0x80, bios + (0x5555 & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000316 programmer_delay(delay_us);
Ollie Lhoefa28582004-12-08 20:10:01 +0000317
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000318 chip_writeb(flash, 0xAA, bios + (0x5555 & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000319 programmer_delay(delay_us);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000320 chip_writeb(flash, 0x55, bios + (0x2AAA & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000321 programmer_delay(delay_us);
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000322 chip_writeb(flash, 0x10, bios + (0x5555 & mask));
Michael Karcher880e8672011-04-15 00:03:37 +0000323 programmer_delay(delay_us);
Ollie Lho73eca802004-03-19 22:10:07 +0000324
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000325 toggle_ready_jedec_slow(flash, bios);
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000326
Carl-Daniel Hailfingerb4061f62011-06-26 17:04:16 +0000327 /* FIXME: Check the status register for errors. */
Uwe Hermannffec5f32007-08-23 16:08:21 +0000328 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000329}
330
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000331static int write_byte_program_jedec_common(struct flashctx *flash, uint8_t *src,
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000332 chipaddr dst, unsigned int mask)
Sean Nelsonc57a9202010-01-04 17:15:23 +0000333{
334 int tried = 0, failed = 0;
335 chipaddr bios = flash->virtual_memory;
336
337 /* If the data is 0xFF, don't program it and don't complain. */
338 if (*src == 0xFF) {
339 return 0;
340 }
341
342retry:
343 /* Issue JEDEC Byte Program command */
344 start_program_jedec_common(flash, mask);
345
346 /* transfer data from source to destination */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000347 chip_writeb(flash, *src, dst);
348 toggle_ready_jedec(flash, bios);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000349
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000350 if (chip_readb(flash, dst) != *src && tried++ < MAX_REFLASH_TRIES) {
Sean Nelsonc57a9202010-01-04 17:15:23 +0000351 goto retry;
352 }
353
354 if (tried >= MAX_REFLASH_TRIES)
355 failed = 1;
356
357 return failed;
358}
359
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000360/* chunksize is 1 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000361int write_jedec_1(struct flashctx *flash, uint8_t *src, unsigned int start,
362 unsigned int len)
Sean Nelsonc57a9202010-01-04 17:15:23 +0000363{
364 int i, failed = 0;
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000365 chipaddr dst = flash->virtual_memory + start;
Sean Nelsonc57a9202010-01-04 17:15:23 +0000366 chipaddr olddst;
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000367 unsigned int mask;
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000368
369 mask = getaddrmask(flash);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000370
371 olddst = dst;
Carl-Daniel Hailfingerb30a5ed2010-10-10 14:02:27 +0000372 for (i = 0; i < len; i++) {
Sean Nelsonc57a9202010-01-04 17:15:23 +0000373 if (write_byte_program_jedec_common(flash, src, dst, mask))
374 failed = 1;
375 dst++, src++;
376 }
377 if (failed)
Sean Nelsoned479d22010-03-24 23:14:32 +0000378 msg_cerr(" writing sector at 0x%lx failed!\n", olddst);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000379
380 return failed;
381}
382
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000383int write_page_write_jedec_common(struct flashctx *flash, uint8_t *src,
384 unsigned int start, unsigned int page_size)
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000385{
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000386 int i, tried = 0, failed;
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000387 uint8_t *s = src;
Urja Rannikko0c854c02009-06-25 13:57:31 +0000388 chipaddr bios = flash->virtual_memory;
389 chipaddr dst = bios + start;
390 chipaddr d = dst;
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000391 unsigned int mask;
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000392
393 mask = getaddrmask(flash);
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000394
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000395retry:
Uwe Hermann4e3d0b32010-03-25 23:18:41 +0000396 /* Issue JEDEC Start Program command */
Sean Nelsonc57a9202010-01-04 17:15:23 +0000397 start_program_jedec_common(flash, mask);
Ollie Lho761bf1b2004-03-20 16:46:10 +0000398
Ollie Lho98bea8a2004-12-07 03:15:51 +0000399 /* transfer data from source to destination */
Carl-Daniel Hailfinger8a8a2262009-11-14 03:48:33 +0000400 for (i = 0; i < page_size; i++) {
Ollie Lho98bea8a2004-12-07 03:15:51 +0000401 /* If the data is 0xFF, don't program it */
Uwe Hermanna7e05482007-05-09 10:17:44 +0000402 if (*src != 0xFF)
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000403 chip_writeb(flash, *src, dst);
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000404 dst++;
405 src++;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000406 }
407
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000408 toggle_ready_jedec(flash, dst - 1);
Ollie Lho98bea8a2004-12-07 03:15:51 +0000409
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000410 dst = d;
411 src = s;
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000412 failed = verify_range(flash, src, start, page_size, NULL);
Uwe Hermanna7e05482007-05-09 10:17:44 +0000413
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000414 if (failed && tried++ < MAX_REFLASH_TRIES) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000415 msg_cerr("retrying.\n");
Uwe Hermanna7e05482007-05-09 10:17:44 +0000416 goto retry;
417 }
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000418 if (failed) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000419 msg_cerr(" page 0x%lx failed!\n",
Carl-Daniel Hailfinger5820f422009-05-16 21:22:56 +0000420 (d - bios) / page_size);
Giampiero Giancipoli8c5299f2006-11-22 00:29:51 +0000421 }
Carl-Daniel Hailfinger2925d6f2009-11-25 16:41:50 +0000422 return failed;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000423}
424
Carl-Daniel Hailfinger75a58f92010-10-13 22:26:56 +0000425/* chunksize is page_size */
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000426/*
427 * Write a part of the flash chip.
428 * FIXME: Use the chunk code from Michael Karcher instead.
429 * This function is a slightly modified copy of spi_write_chunked.
430 * Each page is written separately in chunks with a maximum size of chunksize.
431 */
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000432int write_jedec(struct flashctx *flash, uint8_t *buf, unsigned int start,
433 int unsigned len)
Carl-Daniel Hailfinger4bf4e792010-01-09 03:15:50 +0000434{
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000435 unsigned int i, starthere, lenhere;
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000436 /* FIXME: page_size is the wrong variable. We need max_writechunk_size
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000437 * in struct flashctx to do this properly. All chips using
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000438 * write_jedec have page_size set to max_writechunk_size, so
439 * we're OK for now.
440 */
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000441 unsigned int page_size = flash->page_size;
Ollie Lho761bf1b2004-03-20 16:46:10 +0000442
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000443 /* Warning: This loop has a very unusual condition and body.
444 * The loop needs to go through each page with at least one affected
445 * byte. The lowest page number is (start / page_size) since that
446 * division rounds down. The highest page number we want is the page
447 * where the last byte of the range lives. That last byte has the
448 * address (start + len - 1), thus the highest page number is
449 * (start + len - 1) / page_size. Since we want to include that last
450 * page as well, the loop condition uses <=.
451 */
452 for (i = start / page_size; i <= (start + len - 1) / page_size; i++) {
453 /* Byte position of the first byte in the range in this page. */
454 /* starthere is an offset to the base address of the chip. */
455 starthere = max(start, i * page_size);
456 /* Length of bytes in the range in this page. */
457 lenhere = min(start + len, (i + 1) * page_size) - starthere;
Sean Nelson35727f72010-01-28 23:55:12 +0000458
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000459 if (write_page_write_jedec_common(flash, buf + starthere - start, starthere, lenhere))
460 return 1;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000461 }
Ronald G. Minnicheaab50b2003-09-12 22:41:53 +0000462
Carl-Daniel Hailfinger79e67572010-10-13 21:49:30 +0000463 return 0;
Ronald G. Minnich5e5f75e2002-01-29 18:21:41 +0000464}
Michael Karcher1c296ca2009-11-27 17:49:42 +0000465
Sean Nelsonc57a9202010-01-04 17:15:23 +0000466/* erase chip with block_erase() prototype */
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000467int erase_chip_block_jedec(struct flashctx *flash, unsigned int addr,
Sean Nelsonc57a9202010-01-04 17:15:23 +0000468 unsigned int blocksize)
469{
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000470 unsigned int mask;
Sean Nelson35727f72010-01-28 23:55:12 +0000471
472 mask = getaddrmask(flash);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000473 if ((addr != 0) || (blocksize != flash->total_size * 1024)) {
Sean Nelsoned479d22010-03-24 23:14:32 +0000474 msg_cerr("%s called with incorrect arguments\n",
Sean Nelsonc57a9202010-01-04 17:15:23 +0000475 __func__);
476 return -1;
477 }
Sean Nelson35727f72010-01-28 23:55:12 +0000478 return erase_chip_jedec_common(flash, mask);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000479}
480
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000481int probe_jedec(struct flashctx *flash)
Sean Nelsonc57a9202010-01-04 17:15:23 +0000482{
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000483 unsigned int mask;
Carl-Daniel Hailfinger4bf4e792010-01-09 03:15:50 +0000484
485 mask = getaddrmask(flash);
Sean Nelson35727f72010-01-28 23:55:12 +0000486 return probe_jedec_common(flash, mask);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000487}
488
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000489int erase_sector_jedec(struct flashctx *flash, unsigned int page,
490 unsigned int size)
Sean Nelsonc57a9202010-01-04 17:15:23 +0000491{
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000492 unsigned int mask;
Sean Nelson35727f72010-01-28 23:55:12 +0000493
494 mask = getaddrmask(flash);
495 return erase_sector_jedec_common(flash, page, size, mask);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000496}
497
Carl-Daniel Hailfinger8a3c60c2011-12-18 15:01:24 +0000498int erase_block_jedec(struct flashctx *flash, unsigned int page,
499 unsigned int size)
Sean Nelsonc57a9202010-01-04 17:15:23 +0000500{
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000501 unsigned int mask;
Sean Nelson35727f72010-01-28 23:55:12 +0000502
503 mask = getaddrmask(flash);
504 return erase_block_jedec_common(flash, page, size, mask);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000505}
506
Carl-Daniel Hailfinger63fd9022011-12-14 22:25:15 +0000507int erase_chip_jedec(struct flashctx *flash)
Sean Nelsonc57a9202010-01-04 17:15:23 +0000508{
Stefan Taunerc69c9c82011-11-23 09:13:48 +0000509 unsigned int mask;
Sean Nelson35727f72010-01-28 23:55:12 +0000510
511 mask = getaddrmask(flash);
512 return erase_chip_jedec_common(flash, mask);
Sean Nelsonc57a9202010-01-04 17:15:23 +0000513}